2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/port.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
39 int mlx5_core_access_reg(struct mlx5_core_dev
*dev
, void *data_in
,
40 int size_in
, void *data_out
, int size_out
,
41 u16 reg_num
, int arg
, int write
)
43 struct mlx5_access_reg_mbox_in
*in
= NULL
;
44 struct mlx5_access_reg_mbox_out
*out
= NULL
;
47 in
= mlx5_vzalloc(sizeof(*in
) + size_in
);
51 out
= mlx5_vzalloc(sizeof(*out
) + size_out
);
55 memcpy(in
->data
, data_in
, size_in
);
56 in
->hdr
.opcode
= cpu_to_be16(MLX5_CMD_OP_ACCESS_REG
);
57 in
->hdr
.opmod
= cpu_to_be16(!write
);
58 in
->arg
= cpu_to_be32(arg
);
59 in
->register_id
= cpu_to_be16(reg_num
);
60 err
= mlx5_cmd_exec(dev
, in
, sizeof(*in
) + size_in
, out
,
61 sizeof(*out
) + size_out
);
66 err
= mlx5_cmd_status_to_err(&out
->hdr
);
69 memcpy(data_out
, out
->data
, size_out
);
77 EXPORT_SYMBOL_GPL(mlx5_core_access_reg
);
80 struct mlx5_reg_pcap
{
90 int mlx5_set_port_caps(struct mlx5_core_dev
*dev
, u8 port_num
, u32 caps
)
92 struct mlx5_reg_pcap in
;
93 struct mlx5_reg_pcap out
;
95 memset(&in
, 0, sizeof(in
));
96 in
.caps_127_96
= cpu_to_be32(caps
);
97 in
.port_num
= port_num
;
99 return mlx5_core_access_reg(dev
, &in
, sizeof(in
), &out
,
100 sizeof(out
), MLX5_REG_PCAP
, 0, 1);
102 EXPORT_SYMBOL_GPL(mlx5_set_port_caps
);
104 int mlx5_query_port_ptys(struct mlx5_core_dev
*dev
, u32
*ptys
,
105 int ptys_size
, int proto_mask
, u8 local_port
)
107 u32 in
[MLX5_ST_SZ_DW(ptys_reg
)];
109 memset(in
, 0, sizeof(in
));
110 MLX5_SET(ptys_reg
, in
, local_port
, local_port
);
111 MLX5_SET(ptys_reg
, in
, proto_mask
, proto_mask
);
113 return mlx5_core_access_reg(dev
, in
, sizeof(in
), ptys
,
114 ptys_size
, MLX5_REG_PTYS
, 0, 0);
116 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys
);
118 int mlx5_query_port_proto_cap(struct mlx5_core_dev
*dev
,
119 u32
*proto_cap
, int proto_mask
)
121 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
124 err
= mlx5_query_port_ptys(dev
, out
, sizeof(out
), proto_mask
, 1);
128 if (proto_mask
== MLX5_PTYS_EN
)
129 *proto_cap
= MLX5_GET(ptys_reg
, out
, eth_proto_capability
);
131 *proto_cap
= MLX5_GET(ptys_reg
, out
, ib_proto_capability
);
135 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap
);
137 int mlx5_query_port_proto_admin(struct mlx5_core_dev
*dev
,
138 u32
*proto_admin
, int proto_mask
)
140 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
143 err
= mlx5_query_port_ptys(dev
, out
, sizeof(out
), proto_mask
, 1);
147 if (proto_mask
== MLX5_PTYS_EN
)
148 *proto_admin
= MLX5_GET(ptys_reg
, out
, eth_proto_admin
);
150 *proto_admin
= MLX5_GET(ptys_reg
, out
, ib_proto_admin
);
154 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin
);
156 int mlx5_query_port_link_width_oper(struct mlx5_core_dev
*dev
,
157 u8
*link_width_oper
, u8 local_port
)
159 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
162 err
= mlx5_query_port_ptys(dev
, out
, sizeof(out
), MLX5_PTYS_IB
, local_port
);
166 *link_width_oper
= MLX5_GET(ptys_reg
, out
, ib_link_width_oper
);
170 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper
);
172 int mlx5_query_port_proto_oper(struct mlx5_core_dev
*dev
,
173 u8
*proto_oper
, int proto_mask
,
176 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
179 err
= mlx5_query_port_ptys(dev
, out
, sizeof(out
), proto_mask
, local_port
);
183 if (proto_mask
== MLX5_PTYS_EN
)
184 *proto_oper
= MLX5_GET(ptys_reg
, out
, eth_proto_oper
);
186 *proto_oper
= MLX5_GET(ptys_reg
, out
, ib_proto_oper
);
190 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper
);
192 int mlx5_set_port_proto(struct mlx5_core_dev
*dev
, u32 proto_admin
,
195 u32 in
[MLX5_ST_SZ_DW(ptys_reg
)];
196 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
198 memset(in
, 0, sizeof(in
));
200 MLX5_SET(ptys_reg
, in
, local_port
, 1);
201 MLX5_SET(ptys_reg
, in
, proto_mask
, proto_mask
);
202 if (proto_mask
== MLX5_PTYS_EN
)
203 MLX5_SET(ptys_reg
, in
, eth_proto_admin
, proto_admin
);
205 MLX5_SET(ptys_reg
, in
, ib_proto_admin
, proto_admin
);
207 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
208 sizeof(out
), MLX5_REG_PTYS
, 0, 1);
210 EXPORT_SYMBOL_GPL(mlx5_set_port_proto
);
212 int mlx5_set_port_admin_status(struct mlx5_core_dev
*dev
,
213 enum mlx5_port_status status
)
215 u32 in
[MLX5_ST_SZ_DW(paos_reg
)];
216 u32 out
[MLX5_ST_SZ_DW(paos_reg
)];
218 memset(in
, 0, sizeof(in
));
220 MLX5_SET(paos_reg
, in
, local_port
, 1);
221 MLX5_SET(paos_reg
, in
, admin_status
, status
);
222 MLX5_SET(paos_reg
, in
, ase
, 1);
224 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
225 sizeof(out
), MLX5_REG_PAOS
, 0, 1);
227 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status
);
229 int mlx5_query_port_admin_status(struct mlx5_core_dev
*dev
,
230 enum mlx5_port_status
*status
)
232 u32 in
[MLX5_ST_SZ_DW(paos_reg
)];
233 u32 out
[MLX5_ST_SZ_DW(paos_reg
)];
236 memset(in
, 0, sizeof(in
));
238 MLX5_SET(paos_reg
, in
, local_port
, 1);
240 err
= mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
241 sizeof(out
), MLX5_REG_PAOS
, 0, 0);
245 *status
= MLX5_GET(paos_reg
, out
, admin_status
);
248 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status
);
250 static void mlx5_query_port_mtu(struct mlx5_core_dev
*dev
, int *admin_mtu
,
251 int *max_mtu
, int *oper_mtu
, u8 port
)
253 u32 in
[MLX5_ST_SZ_DW(pmtu_reg
)];
254 u32 out
[MLX5_ST_SZ_DW(pmtu_reg
)];
256 memset(in
, 0, sizeof(in
));
258 MLX5_SET(pmtu_reg
, in
, local_port
, port
);
260 mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
261 sizeof(out
), MLX5_REG_PMTU
, 0, 0);
264 *max_mtu
= MLX5_GET(pmtu_reg
, out
, max_mtu
);
266 *oper_mtu
= MLX5_GET(pmtu_reg
, out
, oper_mtu
);
268 *admin_mtu
= MLX5_GET(pmtu_reg
, out
, admin_mtu
);
271 int mlx5_set_port_mtu(struct mlx5_core_dev
*dev
, int mtu
, u8 port
)
273 u32 in
[MLX5_ST_SZ_DW(pmtu_reg
)];
274 u32 out
[MLX5_ST_SZ_DW(pmtu_reg
)];
276 memset(in
, 0, sizeof(in
));
278 MLX5_SET(pmtu_reg
, in
, admin_mtu
, mtu
);
279 MLX5_SET(pmtu_reg
, in
, local_port
, port
);
281 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
282 sizeof(out
), MLX5_REG_PMTU
, 0, 1);
284 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu
);
286 void mlx5_query_port_max_mtu(struct mlx5_core_dev
*dev
, int *max_mtu
,
289 mlx5_query_port_mtu(dev
, NULL
, max_mtu
, NULL
, port
);
291 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu
);
293 void mlx5_query_port_oper_mtu(struct mlx5_core_dev
*dev
, int *oper_mtu
,
296 mlx5_query_port_mtu(dev
, NULL
, NULL
, oper_mtu
, port
);
298 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu
);
300 static int mlx5_query_port_pvlc(struct mlx5_core_dev
*dev
, u32
*pvlc
,
301 int pvlc_size
, u8 local_port
)
303 u32 in
[MLX5_ST_SZ_DW(pvlc_reg
)];
305 memset(in
, 0, sizeof(in
));
306 MLX5_SET(pvlc_reg
, in
, local_port
, local_port
);
308 return mlx5_core_access_reg(dev
, in
, sizeof(in
), pvlc
,
309 pvlc_size
, MLX5_REG_PVLC
, 0, 0);
312 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev
*dev
,
313 u8
*vl_hw_cap
, u8 local_port
)
315 u32 out
[MLX5_ST_SZ_DW(pvlc_reg
)];
318 err
= mlx5_query_port_pvlc(dev
, out
, sizeof(out
), local_port
);
322 *vl_hw_cap
= MLX5_GET(pvlc_reg
, out
, vl_hw_cap
);
326 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap
);
328 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev
*dev
,
329 u8 port_num
, void *out
, size_t sz
)
334 in
= mlx5_vzalloc(sz
);
340 MLX5_SET(ppcnt_reg
, in
, local_port
, port_num
);
342 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_INFINIBAND_PORT_COUNTERS_GROUP
);
343 err
= mlx5_core_access_reg(dev
, in
, sz
, out
,
344 sz
, MLX5_REG_PPCNT
, 0, 0);
349 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt
);
351 int mlx5_set_port_pause(struct mlx5_core_dev
*dev
, u32 rx_pause
, u32 tx_pause
)
353 u32 in
[MLX5_ST_SZ_DW(pfcc_reg
)];
354 u32 out
[MLX5_ST_SZ_DW(pfcc_reg
)];
356 memset(in
, 0, sizeof(in
));
357 MLX5_SET(pfcc_reg
, in
, local_port
, 1);
358 MLX5_SET(pfcc_reg
, in
, pptx
, tx_pause
);
359 MLX5_SET(pfcc_reg
, in
, pprx
, rx_pause
);
361 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
362 sizeof(out
), MLX5_REG_PFCC
, 0, 1);
364 EXPORT_SYMBOL_GPL(mlx5_set_port_pause
);
366 int mlx5_query_port_pause(struct mlx5_core_dev
*dev
,
367 u32
*rx_pause
, u32
*tx_pause
)
369 u32 in
[MLX5_ST_SZ_DW(pfcc_reg
)];
370 u32 out
[MLX5_ST_SZ_DW(pfcc_reg
)];
373 memset(in
, 0, sizeof(in
));
374 MLX5_SET(pfcc_reg
, in
, local_port
, 1);
376 err
= mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
377 sizeof(out
), MLX5_REG_PFCC
, 0, 0);
382 *rx_pause
= MLX5_GET(pfcc_reg
, out
, pprx
);
385 *tx_pause
= MLX5_GET(pfcc_reg
, out
, pptx
);
389 EXPORT_SYMBOL_GPL(mlx5_query_port_pause
);
391 int mlx5_set_port_pfc(struct mlx5_core_dev
*dev
, u8 pfc_en_tx
, u8 pfc_en_rx
)
393 u32 in
[MLX5_ST_SZ_DW(pfcc_reg
)];
394 u32 out
[MLX5_ST_SZ_DW(pfcc_reg
)];
396 memset(in
, 0, sizeof(in
));
397 MLX5_SET(pfcc_reg
, in
, local_port
, 1);
398 MLX5_SET(pfcc_reg
, in
, pfctx
, pfc_en_tx
);
399 MLX5_SET(pfcc_reg
, in
, pfcrx
, pfc_en_rx
);
400 MLX5_SET_TO_ONES(pfcc_reg
, in
, prio_mask_tx
);
401 MLX5_SET_TO_ONES(pfcc_reg
, in
, prio_mask_rx
);
403 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
404 sizeof(out
), MLX5_REG_PFCC
, 0, 1);
406 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc
);
408 int mlx5_query_port_pfc(struct mlx5_core_dev
*dev
, u8
*pfc_en_tx
, u8
*pfc_en_rx
)
410 u32 in
[MLX5_ST_SZ_DW(pfcc_reg
)];
411 u32 out
[MLX5_ST_SZ_DW(pfcc_reg
)];
414 memset(in
, 0, sizeof(in
));
415 MLX5_SET(pfcc_reg
, in
, local_port
, 1);
417 err
= mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
418 sizeof(out
), MLX5_REG_PFCC
, 0, 0);
423 *pfc_en_tx
= MLX5_GET(pfcc_reg
, out
, pfctx
);
426 *pfc_en_rx
= MLX5_GET(pfcc_reg
, out
, pfcrx
);
430 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc
);
432 int mlx5_max_tc(struct mlx5_core_dev
*mdev
)
434 u8 num_tc
= MLX5_CAP_GEN(mdev
, max_tc
) ? : 8;
439 int mlx5_set_port_prio_tc(struct mlx5_core_dev
*mdev
, u8
*prio_tc
)
441 u32 in
[MLX5_ST_SZ_DW(qtct_reg
)];
442 u32 out
[MLX5_ST_SZ_DW(qtct_reg
)];
446 memset(in
, 0, sizeof(in
));
447 for (i
= 0; i
< 8; i
++) {
448 if (prio_tc
[i
] > mlx5_max_tc(mdev
))
451 MLX5_SET(qtct_reg
, in
, prio
, i
);
452 MLX5_SET(qtct_reg
, in
, tclass
, prio_tc
[i
]);
454 err
= mlx5_core_access_reg(mdev
, in
, sizeof(in
), out
,
455 sizeof(out
), MLX5_REG_QTCT
, 0, 1);
462 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc
);
464 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev
*mdev
, u32
*in
,
467 u32 out
[MLX5_ST_SZ_DW(qtct_reg
)];
469 if (!MLX5_CAP_GEN(mdev
, ets
))
472 return mlx5_core_access_reg(mdev
, in
, inlen
, out
, sizeof(out
),
473 MLX5_REG_QETCR
, 0, 1);
476 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev
*mdev
, u32
*out
,
479 u32 in
[MLX5_ST_SZ_DW(qtct_reg
)];
481 if (!MLX5_CAP_GEN(mdev
, ets
))
484 memset(in
, 0, sizeof(in
));
485 return mlx5_core_access_reg(mdev
, in
, sizeof(in
), out
, outlen
,
486 MLX5_REG_QETCR
, 0, 0);
489 int mlx5_set_port_tc_group(struct mlx5_core_dev
*mdev
, u8
*tc_group
)
491 u32 in
[MLX5_ST_SZ_DW(qetc_reg
)];
494 memset(in
, 0, sizeof(in
));
496 for (i
= 0; i
<= mlx5_max_tc(mdev
); i
++) {
497 MLX5_SET(qetc_reg
, in
, tc_configuration
[i
].g
, 1);
498 MLX5_SET(qetc_reg
, in
, tc_configuration
[i
].group
, tc_group
[i
]);
501 return mlx5_set_port_qetcr_reg(mdev
, in
, sizeof(in
));
503 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group
);
505 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev
*mdev
, u8
*tc_bw
)
507 u32 in
[MLX5_ST_SZ_DW(qetc_reg
)];
510 memset(in
, 0, sizeof(in
));
512 for (i
= 0; i
<= mlx5_max_tc(mdev
); i
++) {
513 MLX5_SET(qetc_reg
, in
, tc_configuration
[i
].b
, 1);
514 MLX5_SET(qetc_reg
, in
, tc_configuration
[i
].bw_allocation
, tc_bw
[i
]);
517 return mlx5_set_port_qetcr_reg(mdev
, in
, sizeof(in
));
519 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc
);
521 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev
*mdev
,
525 u32 in
[MLX5_ST_SZ_DW(qetc_reg
)];
529 memset(in
, 0, sizeof(in
));
531 MLX5_SET(qetc_reg
, in
, port_number
, 1);
533 for (i
= 0; i
<= mlx5_max_tc(mdev
); i
++) {
534 ets_tcn_conf
= MLX5_ADDR_OF(qetc_reg
, in
, tc_configuration
[i
]);
536 MLX5_SET(ets_tcn_config_reg
, ets_tcn_conf
, r
, 1);
537 MLX5_SET(ets_tcn_config_reg
, ets_tcn_conf
, max_bw_units
,
539 MLX5_SET(ets_tcn_config_reg
, ets_tcn_conf
, max_bw_value
,
543 return mlx5_set_port_qetcr_reg(mdev
, in
, sizeof(in
));
545 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit
);
547 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev
*mdev
,
551 u32 out
[MLX5_ST_SZ_DW(qetc_reg
)];
556 err
= mlx5_query_port_qetcr_reg(mdev
, out
, sizeof(out
));
560 for (i
= 0; i
<= mlx5_max_tc(mdev
); i
++) {
561 ets_tcn_conf
= MLX5_ADDR_OF(qetc_reg
, out
, tc_configuration
[i
]);
563 max_bw_value
[i
] = MLX5_GET(ets_tcn_config_reg
, ets_tcn_conf
,
565 max_bw_units
[i
] = MLX5_GET(ets_tcn_config_reg
, ets_tcn_conf
,
571 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit
);
573 int mlx5_set_port_wol(struct mlx5_core_dev
*mdev
, u8 wol_mode
)
575 u32 in
[MLX5_ST_SZ_DW(set_wol_rol_in
)];
576 u32 out
[MLX5_ST_SZ_DW(set_wol_rol_out
)];
578 memset(in
, 0, sizeof(in
));
579 memset(out
, 0, sizeof(out
));
581 MLX5_SET(set_wol_rol_in
, in
, opcode
, MLX5_CMD_OP_SET_WOL_ROL
);
582 MLX5_SET(set_wol_rol_in
, in
, wol_mode_valid
, 1);
583 MLX5_SET(set_wol_rol_in
, in
, wol_mode
, wol_mode
);
585 return mlx5_cmd_exec_check_status(mdev
, in
, sizeof(in
),
588 EXPORT_SYMBOL_GPL(mlx5_set_port_wol
);
590 int mlx5_query_port_wol(struct mlx5_core_dev
*mdev
, u8
*wol_mode
)
592 u32 in
[MLX5_ST_SZ_DW(query_wol_rol_in
)];
593 u32 out
[MLX5_ST_SZ_DW(query_wol_rol_out
)];
596 memset(in
, 0, sizeof(in
));
597 memset(out
, 0, sizeof(out
));
599 MLX5_SET(query_wol_rol_in
, in
, opcode
, MLX5_CMD_OP_QUERY_WOL_ROL
);
601 err
= mlx5_cmd_exec_check_status(mdev
, in
, sizeof(in
),
605 *wol_mode
= MLX5_GET(query_wol_rol_out
, out
, wol_mode
);
609 EXPORT_SYMBOL_GPL(mlx5_query_port_wol
);