drivers/net/ethernet/mellanox/mlxsw/reg.h

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/reg.h
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
   5  * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
   6  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Neither the names of the copyright holders nor the names of its
  17  *    contributors may be used to endorse or promote products derived from
  18  *    this software without specific prior written permission.
  19  *
  20  * Alternatively, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") version 2 as published by the Free
  22  * Software Foundation.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  28  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34  * POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #ifndef _MLXSW_REG_H
  38 #define _MLXSW_REG_H
  39
  40 #include <linux/string.h>
  41 #include <linux/bitops.h>
  42 #include <linux/if_vlan.h>
  43
  44 #include "item.h"
  45 #include "port.h"
  46
  47 struct mlxsw_reg_info {
  48         u16 id;
  49         u16 len; /* In u8 */
  50 };
  51
  52 #define MLXSW_REG(type) (&mlxsw_reg_##type)
  53 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
  54 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
  55
  56 /* SGCR - Switch General Configuration Register
  57  * --------------------------------------------
  58  * This register is used for configuration of the switch capabilities.
  59  */
  60 #define MLXSW_REG_SGCR_ID 0x2000
  61 #define MLXSW_REG_SGCR_LEN 0x10
  62
  63 static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
  64         .id = MLXSW_REG_SGCR_ID,
  65         .len = MLXSW_REG_SGCR_LEN,
  66 };
  67
  68 /* reg_sgcr_llb
  69  * Link Local Broadcast (Default=0)
  70  * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
  71  * packets and ignore the IGMP snooping entries.
  72  * Access: RW
  73  */
  74 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
  75
  76 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
  77 {
  78         MLXSW_REG_ZERO(sgcr, payload);
  79         mlxsw_reg_sgcr_llb_set(payload, !!llb);
  80 }
  81
  82 /* SPAD - Switch Physical Address Register
  83  * ---------------------------------------
  84  * The SPAD register configures the switch physical MAC address.
  85  */
  86 #define MLXSW_REG_SPAD_ID 0x2002
  87 #define MLXSW_REG_SPAD_LEN 0x10
  88
  89 static const struct mlxsw_reg_info mlxsw_reg_spad = {
  90         .id = MLXSW_REG_SPAD_ID,
  91         .len = MLXSW_REG_SPAD_LEN,
  92 };
  93
  94 /* reg_spad_base_mac
  95  * Base MAC address for the switch partitions.
  96  * Per switch partition MAC address is equal to:
  97  * base_mac + swid
  98  * Access: RW
  99  */
 100 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
 101
 102 /* SSPR - Switch System Port Record Register
 103  * -----------------------------------------
 104  * Configures the system port to local port mapping.
 105  */
 106 #define MLXSW_REG_SSPR_ID 0x2008
 107 #define MLXSW_REG_SSPR_LEN 0x8
 108
 109 static const struct mlxsw_reg_info mlxsw_reg_sspr = {
 110         .id = MLXSW_REG_SSPR_ID,
 111         .len = MLXSW_REG_SSPR_LEN,
 112 };
 113
 114 /* reg_sspr_m
 115  * Master - if set, then the record describes the master system port.
 116  * This is needed in case a local port is mapped into several system ports
 117  * (for multipathing). That number will be reported as the source system
 118  * port when packets are forwarded to the CPU. Only one master port is allowed
 119  * per local port.
 120  *
 121  * Note: Must be set for Spectrum.
 122  * Access: RW
 123  */
 124 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
 125
 126 /* reg_sspr_local_port
 127  * Local port number.
 128  *
 129  * Access: RW
 130  */
 131 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
 132
 133 /* reg_sspr_sub_port
 134  * Virtual port within the physical port.
 135  * Should be set to 0 when virtual ports are not enabled on the port.
 136  *
 137  * Access: RW
 138  */
 139 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
 140
 141 /* reg_sspr_system_port
 142  * Unique identifier within the stacking domain that represents all the ports
 143  * that are available in the system (external ports).
 144  *
 145  * Currently, only single-ASIC configurations are supported, so we default to
 146  * 1:1 mapping between system ports and local ports.
 147  * Access: Index
 148  */
 149 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
 150
 151 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
 152 {
 153         MLXSW_REG_ZERO(sspr, payload);
 154         mlxsw_reg_sspr_m_set(payload, 1);
 155         mlxsw_reg_sspr_local_port_set(payload, local_port);
 156         mlxsw_reg_sspr_sub_port_set(payload, 0);
 157         mlxsw_reg_sspr_system_port_set(payload, local_port);
 158 }
 159
 160 /* SFDAT - Switch Filtering Database Aging Time
 161  * --------------------------------------------
 162  * Controls the Switch aging time. Aging time is able to be set per Switch
 163  * Partition.
 164  */
 165 #define MLXSW_REG_SFDAT_ID 0x2009
 166 #define MLXSW_REG_SFDAT_LEN 0x8
 167
 168 static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
 169         .id = MLXSW_REG_SFDAT_ID,
 170         .len = MLXSW_REG_SFDAT_LEN,
 171 };
 172
 173 /* reg_sfdat_swid
 174  * Switch partition ID.
 175  * Access: Index
 176  */
 177 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
 178
 179 /* reg_sfdat_age_time
 180  * Aging time in seconds
 181  * Min - 10 seconds
 182  * Max - 1,000,000 seconds
 183  * Default is 300 seconds.
 184  * Access: RW
 185  */
 186 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
 187
 188 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
 189 {
 190         MLXSW_REG_ZERO(sfdat, payload);
 191         mlxsw_reg_sfdat_swid_set(payload, 0);
 192         mlxsw_reg_sfdat_age_time_set(payload, age_time);
 193 }
 194
 195 /* SFD - Switch Filtering Database
 196  * -------------------------------
 197  * The following register defines the access to the filtering database.
 198  * The register supports querying, adding, removing and modifying the database.
 199  * The access is optimized for bulk updates in which case more than one
 200  * FDB record is present in the same command.
 201  */
 202 #define MLXSW_REG_SFD_ID 0x200A
 203 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
 204 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
 205 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
 206 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +     \
 207                            MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
 208
 209 static const struct mlxsw_reg_info mlxsw_reg_sfd = {
 210         .id = MLXSW_REG_SFD_ID,
 211         .len = MLXSW_REG_SFD_LEN,
 212 };
 213
 214 /* reg_sfd_swid
 215  * Switch partition ID for queries. Reserved on Write.
 216  * Access: Index
 217  */
 218 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
 219
 220 enum mlxsw_reg_sfd_op {
 221         /* Dump entire FDB a (process according to record_locator) */
 222         MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
 223         /* Query records by {MAC, VID/FID} value */
 224         MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
 225         /* Query and clear activity. Query records by {MAC, VID/FID} value */
 226         MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
 227         /* Test. Response indicates if each of the records could be
 228          * added to the FDB.
 229          */
 230         MLXSW_REG_SFD_OP_WRITE_TEST = 0,
 231         /* Add/modify. Aged-out records cannot be added. This command removes
 232          * the learning notification of the {MAC, VID/FID}. Response includes
 233          * the entries that were added to the FDB.
 234          */
 235         MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
 236         /* Remove record by {MAC, VID/FID}. This command also removes
 237          * the learning notification and aged-out notifications
 238          * of the {MAC, VID/FID}. The response provides current (pre-removal)
 239          * entries as non-aged-out.
 240          */
 241         MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
 242         /* Remove learned notification by {MAC, VID/FID}. The response provides
 243          * the removed learning notification.
 244          */
 245         MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
 246 };
 247
 248 /* reg_sfd_op
 249  * Operation.
 250  * Access: OP
 251  */
 252 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
 253
 254 /* reg_sfd_record_locator
 255  * Used for querying the FDB. Use record_locator=0 to initiate the
 256  * query. When a record is returned, a new record_locator is
 257  * returned to be used in the subsequent query.
 258  * Reserved for database update.
 259  * Access: Index
 260  */
 261 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
 262
 263 /* reg_sfd_num_rec
 264  * Request: Number of records to read/add/modify/remove
 265  * Response: Number of records read/added/replaced/removed
 266  * See above description for more details.
 267  * Ranges 0..64
 268  * Access: RW
 269  */
 270 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
 271
 272 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
 273                                       u32 record_locator)
 274 {
 275         MLXSW_REG_ZERO(sfd, payload);
 276         mlxsw_reg_sfd_op_set(payload, op);
 277         mlxsw_reg_sfd_record_locator_set(payload, record_locator);
 278 }
 279
 280 /* reg_sfd_rec_swid
 281  * Switch partition ID.
 282  * Access: Index
 283  */
 284 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
 285                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 286
 287 enum mlxsw_reg_sfd_rec_type {
 288         MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
 289 };
 290
 291 /* reg_sfd_rec_type
 292  * FDB record type.
 293  * Access: RW
 294  */
 295 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
 296                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 297
 298 enum mlxsw_reg_sfd_rec_policy {
 299         /* Replacement disabled, aging disabled. */
 300         MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
 301         /* (mlag remote): Replacement enabled, aging disabled,
 302          * learning notification enabled on this port.
 303          */
 304         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
 305         /* (ingress device): Replacement enabled, aging enabled. */
 306         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
 307 };
 308
 309 /* reg_sfd_rec_policy
 310  * Policy.
 311  * Access: RW
 312  */
 313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
 314                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 315
 316 /* reg_sfd_rec_a
 317  * Activity. Set for new static entries. Set for static entries if a frame SMAC
 318  * lookup hits on the entry.
 319  * To clear the a bit, use "query and clear activity" op.
 320  * Access: RO
 321  */
 322 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
 323                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 324
 325 /* reg_sfd_rec_mac
 326  * MAC address.
 327  * Access: Index
 328  */
 329 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
 330                        MLXSW_REG_SFD_REC_LEN, 0x02);
 331
 332 enum mlxsw_reg_sfd_rec_action {
 333         /* forward */
 334         MLXSW_REG_SFD_REC_ACTION_NOP = 0,
 335         /* forward and trap, trap_id is FDB_TRAP */
 336         MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
 337         /* trap and do not forward, trap_id is FDB_TRAP */
 338         MLXSW_REG_SFD_REC_ACTION_TRAP = 3,
 339         MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
 340 };
 341
 342 /* reg_sfd_rec_action
 343  * Action to apply on the packet.
 344  * Note: Dynamic entries can only be configured with NOP action.
 345  * Access: RW
 346  */
 347 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
 348                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 349
 350 /* reg_sfd_uc_sub_port
 351  * VEPA channel on local port.
 352  * Valid only if local port is a non-stacking port. Must be 0 if multichannel
 353  * VEPA is not enabled.
 354  * Access: RW
 355  */
 356 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 357                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 358
 359 /* reg_sfd_uc_fid_vid
 360  * Filtering ID or VLAN ID
 361  * For SwitchX and SwitchX-2:
 362  * - Dynamic entries (policy 2,3) use FID
 363  * - Static entries (policy 0) use VID
 364  * - When independent learning is configured, VID=FID
 365  * For Spectrum: use FID for both Dynamic and Static entries.
 366  * VID should not be used.
 367  * Access: Index
 368  */
 369 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 370                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 371
 372 /* reg_sfd_uc_system_port
 373  * Unique port identifier for the final destination of the packet.
 374  * Access: RW
 375  */
 376 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 377                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 378
 379 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
 380                                          enum mlxsw_reg_sfd_rec_policy policy,
 381                                          const char *mac, u16 vid,
 382                                          enum mlxsw_reg_sfd_rec_action action,
 383                                          u8 local_port)
 384 {
 385         u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
 386
 387         if (rec_index >= num_rec)
 388                 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
 389         mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
 390         mlxsw_reg_sfd_rec_type_set(payload, rec_index,
 391                                    MLXSW_REG_SFD_REC_TYPE_UNICAST);
 392         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 393         mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
 394         mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
 395         mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, vid);
 396         mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
 397         mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
 398 }
 399
 400 static inline void
 401 mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
 402                         char *mac, u16 *p_vid,
 403                         u8 *p_local_port)
 404 {
 405         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 406         *p_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
 407         *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
 408 }
 409
 410 /* SFN - Switch FDB Notification Register
 411  * -------------------------------------------
 412  * The switch provides notifications on newly learned FDB entries and
 413  * aged out entries. The notifications can be polled by software.
 414  */
 415 #define MLXSW_REG_SFN_ID 0x200B
 416 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
 417 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
 418 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
 419 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +     \
 420                            MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
 421
 422 static const struct mlxsw_reg_info mlxsw_reg_sfn = {
 423         .id = MLXSW_REG_SFN_ID,
 424         .len = MLXSW_REG_SFN_LEN,
 425 };
 426
 427 /* reg_sfn_swid
 428  * Switch partition ID.
 429  * Access: Index
 430  */
 431 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
 432
 433 /* reg_sfn_num_rec
 434  * Request: Number of learned notifications and aged-out notification
 435  * records requested.
 436  * Response: Number of notification records returned (must be smaller
 437  * than or equal to the value requested)
 438  * Ranges 0..64
 439  * Access: OP
 440  */
 441 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
 442
 443 static inline void mlxsw_reg_sfn_pack(char *payload)
 444 {
 445         MLXSW_REG_ZERO(sfn, payload);
 446         mlxsw_reg_sfn_swid_set(payload, 0);
 447         mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
 448 }
 449
 450 /* reg_sfn_rec_swid
 451  * Switch partition ID.
 452  * Access: RO
 453  */
 454 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
 455                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 456
 457 enum mlxsw_reg_sfn_rec_type {
 458         /* MAC addresses learned on a regular port. */
 459         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
 460         /* Aged-out MAC address on a regular port */
 461         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
 462 };
 463
 464 /* reg_sfn_rec_type
 465  * Notification record type.
 466  * Access: RO
 467  */
 468 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
 469                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 470
 471 /* reg_sfn_rec_mac
 472  * MAC address.
 473  * Access: RO
 474  */
 475 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
 476                        MLXSW_REG_SFN_REC_LEN, 0x02);
 477
 478 /* reg_sfn_mac_sub_port
 479  * VEPA channel on the local port.
 480  * 0 if multichannel VEPA is not enabled.
 481  * Access: RO
 482  */
 483 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
 484                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 485
 486 /* reg_sfn_mac_fid
 487  * Filtering identifier.
 488  * Access: RO
 489  */
 490 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 491                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 492
 493 /* reg_sfn_mac_system_port
 494  * Unique port identifier for the final destination of the packet.
 495  * Access: RO
 496  */
 497 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 498                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 499
 500 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
 501                                             char *mac, u16 *p_vid,
 502                                             u8 *p_local_port)
 503 {
 504         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 505         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 506         *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
 507 }
 508
 509 /* SPMS - Switch Port MSTP/RSTP State Register
 510  * -------------------------------------------
 511  * Configures the spanning tree state of a physical port.
 512  */
 513 #define MLXSW_REG_SPMS_ID 0x200D
 514 #define MLXSW_REG_SPMS_LEN 0x404
 515
 516 static const struct mlxsw_reg_info mlxsw_reg_spms = {
 517         .id = MLXSW_REG_SPMS_ID,
 518         .len = MLXSW_REG_SPMS_LEN,
 519 };
 520
 521 /* reg_spms_local_port
 522  * Local port number.
 523  * Access: Index
 524  */
 525 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
 526
 527 enum mlxsw_reg_spms_state {
 528         MLXSW_REG_SPMS_STATE_NO_CHANGE,
 529         MLXSW_REG_SPMS_STATE_DISCARDING,
 530         MLXSW_REG_SPMS_STATE_LEARNING,
 531         MLXSW_REG_SPMS_STATE_FORWARDING,
 532 };
 533
 534 /* reg_spms_state
 535  * Spanning tree state of each VLAN ID (VID) of the local port.
 536  * 0 - Do not change spanning tree state (used only when writing).
 537  * 1 - Discarding. No learning or forwarding to/from this port (default).
 538  * 2 - Learning. Port is learning, but not forwarding.
 539  * 3 - Forwarding. Port is learning and forwarding.
 540  * Access: RW
 541  */
 542 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
 543
 544 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
 545 {
 546         MLXSW_REG_ZERO(spms, payload);
 547         mlxsw_reg_spms_local_port_set(payload, local_port);
 548 }
 549
 550 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
 551                                            enum mlxsw_reg_spms_state state)
 552 {
 553         mlxsw_reg_spms_state_set(payload, vid, state);
 554 }
 555
 556 /* SPVID - Switch Port VID
 557  * -----------------------
 558  * The switch port VID configures the default VID for a port.
 559  */
 560 #define MLXSW_REG_SPVID_ID 0x200E
 561 #define MLXSW_REG_SPVID_LEN 0x08
 562
 563 static const struct mlxsw_reg_info mlxsw_reg_spvid = {
 564         .id = MLXSW_REG_SPVID_ID,
 565         .len = MLXSW_REG_SPVID_LEN,
 566 };
 567
 568 /* reg_spvid_local_port
 569  * Local port number.
 570  * Access: Index
 571  */
 572 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
 573
 574 /* reg_spvid_sub_port
 575  * Virtual port within the physical port.
 576  * Should be set to 0 when virtual ports are not enabled on the port.
 577  * Access: Index
 578  */
 579 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
 580
 581 /* reg_spvid_pvid
 582  * Port default VID
 583  * Access: RW
 584  */
 585 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
 586
 587 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
 588 {
 589         MLXSW_REG_ZERO(spvid, payload);
 590         mlxsw_reg_spvid_local_port_set(payload, local_port);
 591         mlxsw_reg_spvid_pvid_set(payload, pvid);
 592 }
 593
 594 /* SPVM - Switch Port VLAN Membership
 595  * ----------------------------------
 596  * The Switch Port VLAN Membership register configures the VLAN membership
 597  * of a port in a VLAN denoted by VID. VLAN membership is managed per
 598  * virtual port. The register can be used to add and remove VID(s) from a port.
 599  */
 600 #define MLXSW_REG_SPVM_ID 0x200F
 601 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
 602 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
 603 #define MLXSW_REG_SPVM_REC_MAX_COUNT 256
 604 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +   \
 605                     MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
 606
 607 static const struct mlxsw_reg_info mlxsw_reg_spvm = {
 608         .id = MLXSW_REG_SPVM_ID,
 609         .len = MLXSW_REG_SPVM_LEN,
 610 };
 611
 612 /* reg_spvm_pt
 613  * Priority tagged. If this bit is set, packets forwarded to the port with
 614  * untagged VLAN membership (u bit is set) will be tagged with priority tag
 615  * (VID=0)
 616  * Access: RW
 617  */
 618 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
 619
 620 /* reg_spvm_pte
 621  * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
 622  * the pt bit will NOT be updated. To update the pt bit, pte must be set.
 623  * Access: WO
 624  */
 625 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
 626
 627 /* reg_spvm_local_port
 628  * Local port number.
 629  * Access: Index
 630  */
 631 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
 632
 633 /* reg_spvm_sub_port
 634  * Virtual port within the physical port.
 635  * Should be set to 0 when virtual ports are not enabled on the port.
 636  * Access: Index
 637  */
 638 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
 639
 640 /* reg_spvm_num_rec
 641  * Number of records to update. Each record contains: i, e, u, vid.
 642  * Access: OP
 643  */
 644 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
 645
 646 /* reg_spvm_rec_i
 647  * Ingress membership in VLAN ID.
 648  * Access: Index
 649  */
 650 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
 651                      MLXSW_REG_SPVM_BASE_LEN, 14, 1,
 652                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 653
 654 /* reg_spvm_rec_e
 655  * Egress membership in VLAN ID.
 656  * Access: Index
 657  */
 658 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
 659                      MLXSW_REG_SPVM_BASE_LEN, 13, 1,
 660                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 661
 662 /* reg_spvm_rec_u
 663  * Untagged - port is an untagged member - egress transmission uses untagged
 664  * frames on VID<n>
 665  * Access: Index
 666  */
 667 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
 668                      MLXSW_REG_SPVM_BASE_LEN, 12, 1,
 669                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 670
 671 /* reg_spvm_rec_vid
 672  * Egress membership in VLAN ID.
 673  * Access: Index
 674  */
 675 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
 676                      MLXSW_REG_SPVM_BASE_LEN, 0, 12,
 677                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 678
 679 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
 680                                        u16 vid_begin, u16 vid_end,
 681                                        bool is_member, bool untagged)
 682 {
 683         int size = vid_end - vid_begin + 1;
 684         int i;
 685
 686         MLXSW_REG_ZERO(spvm, payload);
 687         mlxsw_reg_spvm_local_port_set(payload, local_port);
 688         mlxsw_reg_spvm_num_rec_set(payload, size);
 689
 690         for (i = 0; i < size; i++) {
 691                 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
 692                 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
 693                 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
 694                 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
 695         }
 696 }
 697
 698 /* SFGC - Switch Flooding Group Configuration
 699  * ------------------------------------------
 700  * The following register controls the association of flooding tables and MIDs
 701  * to packet types used for flooding.
 702  */
 703 #define MLXSW_REG_SFGC_ID 0x2011
 704 #define MLXSW_REG_SFGC_LEN 0x10
 705
 706 static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
 707         .id = MLXSW_REG_SFGC_ID,
 708         .len = MLXSW_REG_SFGC_LEN,
 709 };
 710
 711 enum mlxsw_reg_sfgc_type {
 712         MLXSW_REG_SFGC_TYPE_BROADCAST,
 713         MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
 714         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
 715         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
 716         MLXSW_REG_SFGC_TYPE_RESERVED,
 717         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
 718         MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
 719         MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
 720         MLXSW_REG_SFGC_TYPE_MAX,
 721 };
 722
 723 /* reg_sfgc_type
 724  * The traffic type to reach the flooding table.
 725  * Access: Index
 726  */
 727 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
 728
 729 enum mlxsw_reg_sfgc_bridge_type {
 730         MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
 731         MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
 732 };
 733
 734 /* reg_sfgc_bridge_type
 735  * Access: Index
 736  *
 737  * Note: SwitchX-2 only supports 802.1Q mode.
 738  */
 739 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
 740
 741 enum mlxsw_flood_table_type {
 742         MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
 743         MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
 744         MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
 745         MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
 746         MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
 747 };
 748
 749 /* reg_sfgc_table_type
 750  * See mlxsw_flood_table_type
 751  * Access: RW
 752  *
 753  * Note: FID offset and FID types are not supported in SwitchX-2.
 754  */
 755 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
 756
 757 /* reg_sfgc_flood_table
 758  * Flooding table index to associate with the specific type on the specific
 759  * switch partition.
 760  * Access: RW
 761  */
 762 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
 763
 764 /* reg_sfgc_mid
 765  * The multicast ID for the swid. Not supported for Spectrum
 766  * Access: RW
 767  */
 768 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
 769
 770 /* reg_sfgc_counter_set_type
 771  * Counter Set Type for flow counters.
 772  * Access: RW
 773  */
 774 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
 775
 776 /* reg_sfgc_counter_index
 777  * Counter Index for flow counters.
 778  * Access: RW
 779  */
 780 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
 781
 782 static inline void
 783 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
 784                     enum mlxsw_reg_sfgc_bridge_type bridge_type,
 785                     enum mlxsw_flood_table_type table_type,
 786                     unsigned int flood_table)
 787 {
 788         MLXSW_REG_ZERO(sfgc, payload);
 789         mlxsw_reg_sfgc_type_set(payload, type);
 790         mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
 791         mlxsw_reg_sfgc_table_type_set(payload, table_type);
 792         mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
 793         mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
 794 }
 795
 796 /* SFTR - Switch Flooding Table Register
 797  * -------------------------------------
 798  * The switch flooding table is used for flooding packet replication. The table
 799  * defines a bit mask of ports for packet replication.
 800  */
 801 #define MLXSW_REG_SFTR_ID 0x2012
 802 #define MLXSW_REG_SFTR_LEN 0x420
 803
 804 static const struct mlxsw_reg_info mlxsw_reg_sftr = {
 805         .id = MLXSW_REG_SFTR_ID,
 806         .len = MLXSW_REG_SFTR_LEN,
 807 };
 808
 809 /* reg_sftr_swid
 810  * Switch partition ID with which to associate the port.
 811  * Access: Index
 812  */
 813 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
 814
 815 /* reg_sftr_flood_table
 816  * Flooding table index to associate with the specific type on the specific
 817  * switch partition.
 818  * Access: Index
 819  */
 820 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
 821
 822 /* reg_sftr_index
 823  * Index. Used as an index into the Flooding Table in case the table is
 824  * configured to use VID / FID or FID Offset.
 825  * Access: Index
 826  */
 827 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
 828
 829 /* reg_sftr_table_type
 830  * See mlxsw_flood_table_type
 831  * Access: RW
 832  */
 833 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
 834
 835 /* reg_sftr_range
 836  * Range of entries to update
 837  * Access: Index
 838  */
 839 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
 840
 841 /* reg_sftr_port
 842  * Local port membership (1 bit per port).
 843  * Access: RW
 844  */
 845 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
 846
 847 /* reg_sftr_cpu_port_mask
 848  * CPU port mask (1 bit per port).
 849  * Access: W
 850  */
 851 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
 852
 853 static inline void mlxsw_reg_sftr_pack(char *payload,
 854                                        unsigned int flood_table,
 855                                        unsigned int index,
 856                                        enum mlxsw_flood_table_type table_type,
 857                                        unsigned int range, u8 port, bool set)
 858 {
 859         MLXSW_REG_ZERO(sftr, payload);
 860         mlxsw_reg_sftr_swid_set(payload, 0);
 861         mlxsw_reg_sftr_flood_table_set(payload, flood_table);
 862         mlxsw_reg_sftr_index_set(payload, index);
 863         mlxsw_reg_sftr_table_type_set(payload, table_type);
 864         mlxsw_reg_sftr_range_set(payload, range);
 865         mlxsw_reg_sftr_port_set(payload, port, set);
 866         mlxsw_reg_sftr_port_mask_set(payload, port, 1);
 867 }
 868
 869 /* SPMLR - Switch Port MAC Learning Register
 870  * -----------------------------------------
 871  * Controls the Switch MAC learning policy per port.
 872  */
 873 #define MLXSW_REG_SPMLR_ID 0x2018
 874 #define MLXSW_REG_SPMLR_LEN 0x8
 875
 876 static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
 877         .id = MLXSW_REG_SPMLR_ID,
 878         .len = MLXSW_REG_SPMLR_LEN,
 879 };
 880
 881 /* reg_spmlr_local_port
 882  * Local port number.
 883  * Access: Index
 884  */
 885 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
 886
 887 /* reg_spmlr_sub_port
 888  * Virtual port within the physical port.
 889  * Should be set to 0 when virtual ports are not enabled on the port.
 890  * Access: Index
 891  */
 892 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
 893
 894 enum mlxsw_reg_spmlr_learn_mode {
 895         MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
 896         MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
 897         MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
 898 };
 899
 900 /* reg_spmlr_learn_mode
 901  * Learning mode on the port.
 902  * 0 - Learning disabled.
 903  * 2 - Learning enabled.
 904  * 3 - Security mode.
 905  *
 906  * In security mode the switch does not learn MACs on the port, but uses the
 907  * SMAC to see if it exists on another ingress port. If so, the packet is
 908  * classified as a bad packet and is discarded unless the software registers
 909  * to receive port security error packets usign HPKT.
 910  */
 911 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
 912
 913 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
 914                                         enum mlxsw_reg_spmlr_learn_mode mode)
 915 {
 916         MLXSW_REG_ZERO(spmlr, payload);
 917         mlxsw_reg_spmlr_local_port_set(payload, local_port);
 918         mlxsw_reg_spmlr_sub_port_set(payload, 0);
 919         mlxsw_reg_spmlr_learn_mode_set(payload, mode);
 920 }
 921
 922 /* SVFA - Switch VID to FID Allocation Register
 923  * --------------------------------------------
 924  * Controls the VID to FID mapping and {Port, VID} to FID mapping for
 925  * virtualized ports.
 926  */
 927 #define MLXSW_REG_SVFA_ID 0x201C
 928 #define MLXSW_REG_SVFA_LEN 0x10
 929
 930 static const struct mlxsw_reg_info mlxsw_reg_svfa = {
 931         .id = MLXSW_REG_SVFA_ID,
 932         .len = MLXSW_REG_SVFA_LEN,
 933 };
 934
 935 /* reg_svfa_swid
 936  * Switch partition ID.
 937  * Access: Index
 938  */
 939 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
 940
 941 /* reg_svfa_local_port
 942  * Local port number.
 943  * Access: Index
 944  *
 945  * Note: Reserved for 802.1Q FIDs.
 946  */
 947 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
 948
 949 enum mlxsw_reg_svfa_mt {
 950         MLXSW_REG_SVFA_MT_VID_TO_FID,
 951         MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
 952 };
 953
 954 /* reg_svfa_mapping_table
 955  * Mapping table:
 956  * 0 - VID to FID
 957  * 1 - {Port, VID} to FID
 958  * Access: Index
 959  *
 960  * Note: Reserved for SwitchX-2.
 961  */
 962 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
 963
 964 /* reg_svfa_v
 965  * Valid.
 966  * Valid if set.
 967  * Access: RW
 968  *
 969  * Note: Reserved for SwitchX-2.
 970  */
 971 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
 972
 973 /* reg_svfa_fid
 974  * Filtering ID.
 975  * Access: RW
 976  */
 977 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
 978
 979 /* reg_svfa_vid
 980  * VLAN ID.
 981  * Access: Index
 982  */
 983 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
 984
 985 /* reg_svfa_counter_set_type
 986  * Counter set type for flow counters.
 987  * Access: RW
 988  *
 989  * Note: Reserved for SwitchX-2.
 990  */
 991 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
 992
 993 /* reg_svfa_counter_index
 994  * Counter index for flow counters.
 995  * Access: RW
 996  *
 997  * Note: Reserved for SwitchX-2.
 998  */
 999 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1000
1001 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1002                                        enum mlxsw_reg_svfa_mt mt, bool valid,
1003                                        u16 fid, u16 vid)
1004 {
1005         MLXSW_REG_ZERO(svfa, payload);
1006         local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1007         mlxsw_reg_svfa_swid_set(payload, 0);
1008         mlxsw_reg_svfa_local_port_set(payload, local_port);
1009         mlxsw_reg_svfa_mapping_table_set(payload, mt);
1010         mlxsw_reg_svfa_v_set(payload, valid);
1011         mlxsw_reg_svfa_fid_set(payload, fid);
1012         mlxsw_reg_svfa_vid_set(payload, vid);
1013 }
1014
1015 /* SVPE - Switch Virtual-Port Enabling Register
1016  * --------------------------------------------
1017  * Enables port virtualization.
1018  */
1019 #define MLXSW_REG_SVPE_ID 0x201E
1020 #define MLXSW_REG_SVPE_LEN 0x4
1021
1022 static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1023         .id = MLXSW_REG_SVPE_ID,
1024         .len = MLXSW_REG_SVPE_LEN,
1025 };
1026
1027 /* reg_svpe_local_port
1028  * Local port number
1029  * Access: Index
1030  *
1031  * Note: CPU port is not supported (uses VLAN mode only).
1032  */
1033 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1034
1035 /* reg_svpe_vp_en
1036  * Virtual port enable.
1037  * 0 - Disable, VLAN mode (VID to FID).
1038  * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1039  * Access: RW
1040  */
1041 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1042
1043 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1044                                        bool enable)
1045 {
1046         MLXSW_REG_ZERO(svpe, payload);
1047         mlxsw_reg_svpe_local_port_set(payload, local_port);
1048         mlxsw_reg_svpe_vp_en_set(payload, enable);
1049 }
1050
1051 /* SFMR - Switch FID Management Register
1052  * -------------------------------------
1053  * Creates and configures FIDs.
1054  */
1055 #define MLXSW_REG_SFMR_ID 0x201F
1056 #define MLXSW_REG_SFMR_LEN 0x18
1057
1058 static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1059         .id = MLXSW_REG_SFMR_ID,
1060         .len = MLXSW_REG_SFMR_LEN,
1061 };
1062
1063 enum mlxsw_reg_sfmr_op {
1064         MLXSW_REG_SFMR_OP_CREATE_FID,
1065         MLXSW_REG_SFMR_OP_DESTROY_FID,
1066 };
1067
1068 /* reg_sfmr_op
1069  * Operation.
1070  * 0 - Create or edit FID.
1071  * 1 - Destroy FID.
1072  * Access: WO
1073  */
1074 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1075
1076 /* reg_sfmr_fid
1077  * Filtering ID.
1078  * Access: Index
1079  */
1080 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1081
1082 /* reg_sfmr_fid_offset
1083  * FID offset.
1084  * Used to point into the flooding table selected by SFGC register if
1085  * the table is of type FID-Offset. Otherwise, this field is reserved.
1086  * Access: RW
1087  */
1088 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1089
1090 /* reg_sfmr_vtfp
1091  * Valid Tunnel Flood Pointer.
1092  * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1093  * Access: RW
1094  *
1095  * Note: Reserved for 802.1Q FIDs.
1096  */
1097 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1098
1099 /* reg_sfmr_nve_tunnel_flood_ptr
1100  * Underlay Flooding and BC Pointer.
1101  * Used as a pointer to the first entry of the group based link lists of
1102  * flooding or BC entries (for NVE tunnels).
1103  * Access: RW
1104  */
1105 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1106
1107 /* reg_sfmr_vv
1108  * VNI Valid.
1109  * If not set, then vni is reserved.
1110  * Access: RW
1111  *
1112  * Note: Reserved for 802.1Q FIDs.
1113  */
1114 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1115
1116 /* reg_sfmr_vni
1117  * Virtual Network Identifier.
1118  * Access: RW
1119  *
1120  * Note: A given VNI can only be assigned to one FID.
1121  */
1122 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1123
1124 static inline void mlxsw_reg_sfmr_pack(char *payload,
1125                                        enum mlxsw_reg_sfmr_op op, u16 fid,
1126                                        u16 fid_offset)
1127 {
1128         MLXSW_REG_ZERO(sfmr, payload);
1129         mlxsw_reg_sfmr_op_set(payload, op);
1130         mlxsw_reg_sfmr_fid_set(payload, fid);
1131         mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1132         mlxsw_reg_sfmr_vtfp_set(payload, false);
1133         mlxsw_reg_sfmr_vv_set(payload, false);
1134 }
1135
1136 /* SPVMLR - Switch Port VLAN MAC Learning Register
1137  * -----------------------------------------------
1138  * Controls the switch MAC learning policy per {Port, VID}.
1139  */
1140 #define MLXSW_REG_SPVMLR_ID 0x2020
1141 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1142 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1143 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1144 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1145                               MLXSW_REG_SPVMLR_REC_LEN * \
1146                               MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1147
1148 static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1149         .id = MLXSW_REG_SPVMLR_ID,
1150         .len = MLXSW_REG_SPVMLR_LEN,
1151 };
1152
1153 /* reg_spvmlr_local_port
1154  * Local ingress port.
1155  * Access: Index
1156  *
1157  * Note: CPU port is not supported.
1158  */
1159 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1160
1161 /* reg_spvmlr_num_rec
1162  * Number of records to update.
1163  * Access: OP
1164  */
1165 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1166
1167 /* reg_spvmlr_rec_learn_enable
1168  * 0 - Disable learning for {Port, VID}.
1169  * 1 - Enable learning for {Port, VID}.
1170  * Access: RW
1171  */
1172 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1173                      31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1174
1175 /* reg_spvmlr_rec_vid
1176  * VLAN ID to be added/removed from port or for querying.
1177  * Access: Index
1178  */
1179 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1180                      MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1181
1182 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1183                                          u16 vid_begin, u16 vid_end,
1184                                          bool learn_enable)
1185 {
1186         int num_rec = vid_end - vid_begin + 1;
1187         int i;
1188
1189         WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1190
1191         MLXSW_REG_ZERO(spvmlr, payload);
1192         mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1193         mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1194
1195         for (i = 0; i < num_rec; i++) {
1196                 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1197                 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1198         }
1199 }
1200
1201 /* PMLP - Ports Module to Local Port Register
1202  * ------------------------------------------
1203  * Configures the assignment of modules to local ports.
1204  */
1205 #define MLXSW_REG_PMLP_ID 0x5002
1206 #define MLXSW_REG_PMLP_LEN 0x40
1207
1208 static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
1209         .id = MLXSW_REG_PMLP_ID,
1210         .len = MLXSW_REG_PMLP_LEN,
1211 };
1212
1213 /* reg_pmlp_rxtx
1214  * 0 - Tx value is used for both Tx and Rx.
1215  * 1 - Rx value is taken from a separte field.
1216  * Access: RW
1217  */
1218 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
1219
1220 /* reg_pmlp_local_port
1221  * Local port number.
1222  * Access: Index
1223  */
1224 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
1225
1226 /* reg_pmlp_width
1227  * 0 - Unmap local port.
1228  * 1 - Lane 0 is used.
1229  * 2 - Lanes 0 and 1 are used.
1230  * 4 - Lanes 0, 1, 2 and 3 are used.
1231  * Access: RW
1232  */
1233 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
1234
1235 /* reg_pmlp_module
1236  * Module number.
1237  * Access: RW
1238  */
1239 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0, false);
1240
1241 /* reg_pmlp_tx_lane
1242  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
1243  * Access: RW
1244  */
1245 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 16, false);
1246
1247 /* reg_pmlp_rx_lane
1248  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
1249  * equal to Tx lane.
1250  * Access: RW
1251  */
1252 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 24, false);
1253
1254 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
1255 {
1256         MLXSW_REG_ZERO(pmlp, payload);
1257         mlxsw_reg_pmlp_local_port_set(payload, local_port);
1258 }
1259
1260 /* PMTU - Port MTU Register
1261  * ------------------------
1262  * Configures and reports the port MTU.
1263  */
1264 #define MLXSW_REG_PMTU_ID 0x5003
1265 #define MLXSW_REG_PMTU_LEN 0x10
1266
1267 static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
1268         .id = MLXSW_REG_PMTU_ID,
1269         .len = MLXSW_REG_PMTU_LEN,
1270 };
1271
1272 /* reg_pmtu_local_port
1273  * Local port number.
1274  * Access: Index
1275  */
1276 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
1277
1278 /* reg_pmtu_max_mtu
1279  * Maximum MTU.
1280  * When port type (e.g. Ethernet) is configured, the relevant MTU is
1281  * reported, otherwise the minimum between the max_mtu of the different
1282  * types is reported.
1283  * Access: RO
1284  */
1285 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
1286
1287 /* reg_pmtu_admin_mtu
1288  * MTU value to set port to. Must be smaller or equal to max_mtu.
1289  * Note: If port type is Infiniband, then port must be disabled, when its
1290  * MTU is set.
1291  * Access: RW
1292  */
1293 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
1294
1295 /* reg_pmtu_oper_mtu
1296  * The actual MTU configured on the port. Packets exceeding this size
1297  * will be dropped.
1298  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
1299  * oper_mtu might be smaller than admin_mtu.
1300  * Access: RO
1301  */
1302 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
1303
1304 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
1305                                        u16 new_mtu)
1306 {
1307         MLXSW_REG_ZERO(pmtu, payload);
1308         mlxsw_reg_pmtu_local_port_set(payload, local_port);
1309         mlxsw_reg_pmtu_max_mtu_set(payload, 0);
1310         mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
1311         mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
1312 }
1313
1314 /* PTYS - Port Type and Speed Register
1315  * -----------------------------------
1316  * Configures and reports the port speed type.
1317  *
1318  * Note: When set while the link is up, the changes will not take effect
1319  * until the port transitions from down to up state.
1320  */
1321 #define MLXSW_REG_PTYS_ID 0x5004
1322 #define MLXSW_REG_PTYS_LEN 0x40
1323
1324 static const struct mlxsw_reg_info mlxsw_reg_ptys = {
1325         .id = MLXSW_REG_PTYS_ID,
1326         .len = MLXSW_REG_PTYS_LEN,
1327 };
1328
1329 /* reg_ptys_local_port
1330  * Local port number.
1331  * Access: Index
1332  */
1333 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
1334
1335 #define MLXSW_REG_PTYS_PROTO_MASK_ETH   BIT(2)
1336
1337 /* reg_ptys_proto_mask
1338  * Protocol mask. Indicates which protocol is used.
1339  * 0 - Infiniband.
1340  * 1 - Fibre Channel.
1341  * 2 - Ethernet.
1342  * Access: Index
1343  */
1344 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
1345
1346 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII                  BIT(0)
1347 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX            BIT(1)
1348 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4            BIT(2)
1349 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4            BIT(3)
1350 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR             BIT(4)
1351 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2            BIT(5)
1352 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4            BIT(6)
1353 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4            BIT(7)
1354 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4             BIT(8)
1355 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR             BIT(12)
1356 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR             BIT(13)
1357 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR          BIT(14)
1358 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4            BIT(15)
1359 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4        BIT(16)
1360 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4            BIT(19)
1361 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4           BIT(20)
1362 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4           BIT(21)
1363 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4           BIT(22)
1364 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4       BIT(23)
1365 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX             BIT(24)
1366 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T              BIT(25)
1367 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T              BIT(26)
1368 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR             BIT(27)
1369 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR             BIT(28)
1370 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR             BIT(29)
1371 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2            BIT(30)
1372 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2            BIT(31)
1373
1374 /* reg_ptys_eth_proto_cap
1375  * Ethernet port supported speeds and protocols.
1376  * Access: RO
1377  */
1378 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
1379
1380 /* reg_ptys_eth_proto_admin
1381  * Speed and protocol to set port to.
1382  * Access: RW
1383  */
1384 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
1385
1386 /* reg_ptys_eth_proto_oper
1387  * The current speed and protocol configured for the port.
1388  * Access: RO
1389  */
1390 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
1391
1392 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
1393                                        u32 proto_admin)
1394 {
1395         MLXSW_REG_ZERO(ptys, payload);
1396         mlxsw_reg_ptys_local_port_set(payload, local_port);
1397         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
1398         mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
1399 }
1400
1401 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
1402                                          u32 *p_eth_proto_adm,
1403                                          u32 *p_eth_proto_oper)
1404 {
1405         if (p_eth_proto_cap)
1406                 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
1407         if (p_eth_proto_adm)
1408                 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
1409         if (p_eth_proto_oper)
1410                 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
1411 }
1412
1413 /* PPAD - Port Physical Address Register
1414  * -------------------------------------
1415  * The PPAD register configures the per port physical MAC address.
1416  */
1417 #define MLXSW_REG_PPAD_ID 0x5005
1418 #define MLXSW_REG_PPAD_LEN 0x10
1419
1420 static const struct mlxsw_reg_info mlxsw_reg_ppad = {
1421         .id = MLXSW_REG_PPAD_ID,
1422         .len = MLXSW_REG_PPAD_LEN,
1423 };
1424
1425 /* reg_ppad_single_base_mac
1426  * 0: base_mac, local port should be 0 and mac[7:0] is
1427  * reserved. HW will set incremental
1428  * 1: single_mac - mac of the local_port
1429  * Access: RW
1430  */
1431 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
1432
1433 /* reg_ppad_local_port
1434  * port number, if single_base_mac = 0 then local_port is reserved
1435  * Access: RW
1436  */
1437 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
1438
1439 /* reg_ppad_mac
1440  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
1441  * If single_base_mac = 1 - the per port MAC address
1442  * Access: RW
1443  */
1444 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
1445
1446 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
1447                                        u8 local_port)
1448 {
1449         MLXSW_REG_ZERO(ppad, payload);
1450         mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
1451         mlxsw_reg_ppad_local_port_set(payload, local_port);
1452 }
1453
1454 /* PAOS - Ports Administrative and Operational Status Register
1455  * -----------------------------------------------------------
1456  * Configures and retrieves per port administrative and operational status.
1457  */
1458 #define MLXSW_REG_PAOS_ID 0x5006
1459 #define MLXSW_REG_PAOS_LEN 0x10
1460
1461 static const struct mlxsw_reg_info mlxsw_reg_paos = {
1462         .id = MLXSW_REG_PAOS_ID,
1463         .len = MLXSW_REG_PAOS_LEN,
1464 };
1465
1466 /* reg_paos_swid
1467  * Switch partition ID with which to associate the port.
1468  * Note: while external ports uses unique local port numbers (and thus swid is
1469  * redundant), router ports use the same local port number where swid is the
1470  * only indication for the relevant port.
1471  * Access: Index
1472  */
1473 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
1474
1475 /* reg_paos_local_port
1476  * Local port number.
1477  * Access: Index
1478  */
1479 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
1480
1481 /* reg_paos_admin_status
1482  * Port administrative state (the desired state of the port):
1483  * 1 - Up.
1484  * 2 - Down.
1485  * 3 - Up once. This means that in case of link failure, the port won't go
1486  *     into polling mode, but will wait to be re-enabled by software.
1487  * 4 - Disabled by system. Can only be set by hardware.
1488  * Access: RW
1489  */
1490 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
1491
1492 /* reg_paos_oper_status
1493  * Port operational state (the current state):
1494  * 1 - Up.
1495  * 2 - Down.
1496  * 3 - Down by port failure. This means that the device will not let the
1497  *     port up again until explicitly specified by software.
1498  * Access: RO
1499  */
1500 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
1501
1502 /* reg_paos_ase
1503  * Admin state update enabled.
1504  * Access: WO
1505  */
1506 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
1507
1508 /* reg_paos_ee
1509  * Event update enable. If this bit is set, event generation will be
1510  * updated based on the e field.
1511  * Access: WO
1512  */
1513 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
1514
1515 /* reg_paos_e
1516  * Event generation on operational state change:
1517  * 0 - Do not generate event.
1518  * 1 - Generate Event.
1519  * 2 - Generate Single Event.
1520  * Access: RW
1521  */
1522 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
1523
1524 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
1525                                        enum mlxsw_port_admin_status status)
1526 {
1527         MLXSW_REG_ZERO(paos, payload);
1528         mlxsw_reg_paos_swid_set(payload, 0);
1529         mlxsw_reg_paos_local_port_set(payload, local_port);
1530         mlxsw_reg_paos_admin_status_set(payload, status);
1531         mlxsw_reg_paos_oper_status_set(payload, 0);
1532         mlxsw_reg_paos_ase_set(payload, 1);
1533         mlxsw_reg_paos_ee_set(payload, 1);
1534         mlxsw_reg_paos_e_set(payload, 1);
1535 }
1536
1537 /* PPCNT - Ports Performance Counters Register
1538  * -------------------------------------------
1539  * The PPCNT register retrieves per port performance counters.
1540  */
1541 #define MLXSW_REG_PPCNT_ID 0x5008
1542 #define MLXSW_REG_PPCNT_LEN 0x100
1543
1544 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
1545         .id = MLXSW_REG_PPCNT_ID,
1546         .len = MLXSW_REG_PPCNT_LEN,
1547 };
1548
1549 /* reg_ppcnt_swid
1550  * For HCA: must be always 0.
1551  * Switch partition ID to associate port with.
1552  * Switch partitions are numbered from 0 to 7 inclusively.
1553  * Switch partition 254 indicates stacking ports.
1554  * Switch partition 255 indicates all switch partitions.
1555  * Only valid on Set() operation with local_port=255.
1556  * Access: Index
1557  */
1558 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
1559
1560 /* reg_ppcnt_local_port
1561  * Local port number.
1562  * 255 indicates all ports on the device, and is only allowed
1563  * for Set() operation.
1564  * Access: Index
1565  */
1566 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
1567
1568 /* reg_ppcnt_pnat
1569  * Port number access type:
1570  * 0 - Local port number
1571  * 1 - IB port number
1572  * Access: Index
1573  */
1574 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
1575
1576 /* reg_ppcnt_grp
1577  * Performance counter group.
1578  * Group 63 indicates all groups. Only valid on Set() operation with
1579  * clr bit set.
1580  * 0x0: IEEE 802.3 Counters
1581  * 0x1: RFC 2863 Counters
1582  * 0x2: RFC 2819 Counters
1583  * 0x3: RFC 3635 Counters
1584  * 0x5: Ethernet Extended Counters
1585  * 0x8: Link Level Retransmission Counters
1586  * 0x10: Per Priority Counters
1587  * 0x11: Per Traffic Class Counters
1588  * 0x12: Physical Layer Counters
1589  * Access: Index
1590  */
1591 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
1592
1593 /* reg_ppcnt_clr
1594  * Clear counters. Setting the clr bit will reset the counter value
1595  * for all counters in the counter group. This bit can be set
1596  * for both Set() and Get() operation.
1597  * Access: OP
1598  */
1599 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
1600
1601 /* reg_ppcnt_prio_tc
1602  * Priority for counter set that support per priority, valid values: 0-7.
1603  * Traffic class for counter set that support per traffic class,
1604  * valid values: 0- cap_max_tclass-1 .
1605  * For HCA: cap_max_tclass is always 8.
1606  * Otherwise must be 0.
1607  * Access: Index
1608  */
1609 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
1610
1611 /* reg_ppcnt_a_frames_transmitted_ok
1612  * Access: RO
1613  */
1614 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
1615              0x08 + 0x00, 0, 64);
1616
1617 /* reg_ppcnt_a_frames_received_ok
1618  * Access: RO
1619  */
1620 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
1621              0x08 + 0x08, 0, 64);
1622
1623 /* reg_ppcnt_a_frame_check_sequence_errors
1624  * Access: RO
1625  */
1626 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
1627              0x08 + 0x10, 0, 64);
1628
1629 /* reg_ppcnt_a_alignment_errors
1630  * Access: RO
1631  */
1632 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
1633              0x08 + 0x18, 0, 64);
1634
1635 /* reg_ppcnt_a_octets_transmitted_ok
1636  * Access: RO
1637  */
1638 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
1639              0x08 + 0x20, 0, 64);
1640
1641 /* reg_ppcnt_a_octets_received_ok
1642  * Access: RO
1643  */
1644 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
1645              0x08 + 0x28, 0, 64);
1646
1647 /* reg_ppcnt_a_multicast_frames_xmitted_ok
1648  * Access: RO
1649  */
1650 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
1651              0x08 + 0x30, 0, 64);
1652
1653 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
1654  * Access: RO
1655  */
1656 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
1657              0x08 + 0x38, 0, 64);
1658
1659 /* reg_ppcnt_a_multicast_frames_received_ok
1660  * Access: RO
1661  */
1662 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
1663              0x08 + 0x40, 0, 64);
1664
1665 /* reg_ppcnt_a_broadcast_frames_received_ok
1666  * Access: RO
1667  */
1668 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
1669              0x08 + 0x48, 0, 64);
1670
1671 /* reg_ppcnt_a_in_range_length_errors
1672  * Access: RO
1673  */
1674 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
1675              0x08 + 0x50, 0, 64);
1676
1677 /* reg_ppcnt_a_out_of_range_length_field
1678  * Access: RO
1679  */
1680 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
1681              0x08 + 0x58, 0, 64);
1682
1683 /* reg_ppcnt_a_frame_too_long_errors
1684  * Access: RO
1685  */
1686 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
1687              0x08 + 0x60, 0, 64);
1688
1689 /* reg_ppcnt_a_symbol_error_during_carrier
1690  * Access: RO
1691  */
1692 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
1693              0x08 + 0x68, 0, 64);
1694
1695 /* reg_ppcnt_a_mac_control_frames_transmitted
1696  * Access: RO
1697  */
1698 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
1699              0x08 + 0x70, 0, 64);
1700
1701 /* reg_ppcnt_a_mac_control_frames_received
1702  * Access: RO
1703  */
1704 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
1705              0x08 + 0x78, 0, 64);
1706
1707 /* reg_ppcnt_a_unsupported_opcodes_received
1708  * Access: RO
1709  */
1710 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
1711              0x08 + 0x80, 0, 64);
1712
1713 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
1714  * Access: RO
1715  */
1716 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
1717              0x08 + 0x88, 0, 64);
1718
1719 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
1720  * Access: RO
1721  */
1722 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
1723              0x08 + 0x90, 0, 64);
1724
1725 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port)
1726 {
1727         MLXSW_REG_ZERO(ppcnt, payload);
1728         mlxsw_reg_ppcnt_swid_set(payload, 0);
1729         mlxsw_reg_ppcnt_local_port_set(payload, local_port);
1730         mlxsw_reg_ppcnt_pnat_set(payload, 0);
1731         mlxsw_reg_ppcnt_grp_set(payload, 0);
1732         mlxsw_reg_ppcnt_clr_set(payload, 0);
1733         mlxsw_reg_ppcnt_prio_tc_set(payload, 0);
1734 }
1735
1736 /* PBMC - Port Buffer Management Control Register
1737  * ----------------------------------------------
1738  * The PBMC register configures and retrieves the port packet buffer
1739  * allocation for different Prios, and the Pause threshold management.
1740  */
1741 #define MLXSW_REG_PBMC_ID 0x500C
1742 #define MLXSW_REG_PBMC_LEN 0x68
1743
1744 static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
1745         .id = MLXSW_REG_PBMC_ID,
1746         .len = MLXSW_REG_PBMC_LEN,
1747 };
1748
1749 /* reg_pbmc_local_port
1750  * Local port number.
1751  * Access: Index
1752  */
1753 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
1754
1755 /* reg_pbmc_xoff_timer_value
1756  * When device generates a pause frame, it uses this value as the pause
1757  * timer (time for the peer port to pause in quota-512 bit time).
1758  * Access: RW
1759  */
1760 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
1761
1762 /* reg_pbmc_xoff_refresh
1763  * The time before a new pause frame should be sent to refresh the pause RW
1764  * state. Using the same units as xoff_timer_value above (in quota-512 bit
1765  * time).
1766  * Access: RW
1767  */
1768 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
1769
1770 /* reg_pbmc_buf_lossy
1771  * The field indicates if the buffer is lossy.
1772  * 0 - Lossless
1773  * 1 - Lossy
1774  * Access: RW
1775  */
1776 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
1777
1778 /* reg_pbmc_buf_epsb
1779  * Eligible for Port Shared buffer.
1780  * If epsb is set, packets assigned to buffer are allowed to insert the port
1781  * shared buffer.
1782  * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
1783  * Access: RW
1784  */
1785 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
1786
1787 /* reg_pbmc_buf_size
1788  * The part of the packet buffer array is allocated for the specific buffer.
1789  * Units are represented in cells.
1790  * Access: RW
1791  */
1792 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
1793
1794 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
1795                                        u16 xoff_timer_value, u16 xoff_refresh)
1796 {
1797         MLXSW_REG_ZERO(pbmc, payload);
1798         mlxsw_reg_pbmc_local_port_set(payload, local_port);
1799         mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
1800         mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
1801 }
1802
1803 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
1804                                                     int buf_index,
1805                                                     u16 size)
1806 {
1807         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
1808         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
1809         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
1810 }
1811
1812 /* PSPA - Port Switch Partition Allocation
1813  * ---------------------------------------
1814  * Controls the association of a port with a switch partition and enables
1815  * configuring ports as stacking ports.
1816  */
1817 #define MLXSW_REG_PSPA_ID 0x500D
1818 #define MLXSW_REG_PSPA_LEN 0x8
1819
1820 static const struct mlxsw_reg_info mlxsw_reg_pspa = {
1821         .id = MLXSW_REG_PSPA_ID,
1822         .len = MLXSW_REG_PSPA_LEN,
1823 };
1824
1825 /* reg_pspa_swid
1826  * Switch partition ID.
1827  * Access: RW
1828  */
1829 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
1830
1831 /* reg_pspa_local_port
1832  * Local port number.
1833  * Access: Index
1834  */
1835 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
1836
1837 /* reg_pspa_sub_port
1838  * Virtual port within the local port. Set to 0 when virtual ports are
1839  * disabled on the local port.
1840  * Access: Index
1841  */
1842 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
1843
1844 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
1845 {
1846         MLXSW_REG_ZERO(pspa, payload);
1847         mlxsw_reg_pspa_swid_set(payload, swid);
1848         mlxsw_reg_pspa_local_port_set(payload, local_port);
1849         mlxsw_reg_pspa_sub_port_set(payload, 0);
1850 }
1851
1852 /* HTGT - Host Trap Group Table
1853  * ----------------------------
1854  * Configures the properties for forwarding to CPU.
1855  */
1856 #define MLXSW_REG_HTGT_ID 0x7002
1857 #define MLXSW_REG_HTGT_LEN 0x100
1858
1859 static const struct mlxsw_reg_info mlxsw_reg_htgt = {
1860         .id = MLXSW_REG_HTGT_ID,
1861         .len = MLXSW_REG_HTGT_LEN,
1862 };
1863
1864 /* reg_htgt_swid
1865  * Switch partition ID.
1866  * Access: Index
1867  */
1868 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
1869
1870 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0      /* For locally attached CPU */
1871
1872 /* reg_htgt_type
1873  * CPU path type.
1874  * Access: RW
1875  */
1876 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
1877
1878 enum mlxsw_reg_htgt_trap_group {
1879         MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1880         MLXSW_REG_HTGT_TRAP_GROUP_RX,
1881         MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
1882 };
1883
1884 /* reg_htgt_trap_group
1885  * Trap group number. User defined number specifying which trap groups
1886  * should be forwarded to the CPU. The mapping between trap IDs and trap
1887  * groups is configured using HPKT register.
1888  * Access: Index
1889  */
1890 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
1891
1892 enum {
1893         MLXSW_REG_HTGT_POLICER_DISABLE,
1894         MLXSW_REG_HTGT_POLICER_ENABLE,
1895 };
1896
1897 /* reg_htgt_pide
1898  * Enable policer ID specified using 'pid' field.
1899  * Access: RW
1900  */
1901 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
1902
1903 /* reg_htgt_pid
1904  * Policer ID for the trap group.
1905  * Access: RW
1906  */
1907 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
1908
1909 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
1910
1911 /* reg_htgt_mirror_action
1912  * Mirror action to use.
1913  * 0 - Trap to CPU.
1914  * 1 - Trap to CPU and mirror to a mirroring agent.
1915  * 2 - Mirror to a mirroring agent and do not trap to CPU.
1916  * Access: RW
1917  *
1918  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
1919  */
1920 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
1921
1922 /* reg_htgt_mirroring_agent
1923  * Mirroring agent.
1924  * Access: RW
1925  */
1926 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
1927
1928 /* reg_htgt_priority
1929  * Trap group priority.
1930  * In case a packet matches multiple classification rules, the packet will
1931  * only be trapped once, based on the trap ID associated with the group (via
1932  * register HPKT) with the highest priority.
1933  * Supported values are 0-7, with 7 represnting the highest priority.
1934  * Access: RW
1935  *
1936  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
1937  * by the 'trap_group' field.
1938  */
1939 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
1940
1941 /* reg_htgt_local_path_cpu_tclass
1942  * CPU ingress traffic class for the trap group.
1943  * Access: RW
1944  */
1945 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
1946
1947 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD      0x15
1948 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX        0x14
1949 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL      0x13
1950
1951 /* reg_htgt_local_path_rdq
1952  * Receive descriptor queue (RDQ) to use for the trap group.
1953  * Access: RW
1954  */
1955 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
1956
1957 static inline void mlxsw_reg_htgt_pack(char *payload,
1958                                        enum mlxsw_reg_htgt_trap_group group)
1959 {
1960         u8 swid, rdq;
1961
1962         MLXSW_REG_ZERO(htgt, payload);
1963         switch (group) {
1964         case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
1965                 swid = MLXSW_PORT_SWID_ALL_SWIDS;
1966                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
1967                 break;
1968         case MLXSW_REG_HTGT_TRAP_GROUP_RX:
1969                 swid = 0;
1970                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
1971                 break;
1972         case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
1973                 swid = 0;
1974                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
1975                 break;
1976         }
1977         mlxsw_reg_htgt_swid_set(payload, swid);
1978         mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
1979         mlxsw_reg_htgt_trap_group_set(payload, group);
1980         mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
1981         mlxsw_reg_htgt_pid_set(payload, 0);
1982         mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
1983         mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
1984         mlxsw_reg_htgt_priority_set(payload, 0);
1985         mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
1986         mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
1987 }
1988
1989 /* HPKT - Host Packet Trap
1990  * -----------------------
1991  * Configures trap IDs inside trap groups.
1992  */
1993 #define MLXSW_REG_HPKT_ID 0x7003
1994 #define MLXSW_REG_HPKT_LEN 0x10
1995
1996 static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
1997         .id = MLXSW_REG_HPKT_ID,
1998         .len = MLXSW_REG_HPKT_LEN,
1999 };
2000
2001 enum {
2002         MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
2003         MLXSW_REG_HPKT_ACK_REQUIRED,
2004 };
2005
2006 /* reg_hpkt_ack
2007  * Require acknowledgements from the host for events.
2008  * If set, then the device will wait for the event it sent to be acknowledged
2009  * by the host. This option is only relevant for event trap IDs.
2010  * Access: RW
2011  *
2012  * Note: Currently not supported by firmware.
2013  */
2014 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
2015
2016 enum mlxsw_reg_hpkt_action {
2017         MLXSW_REG_HPKT_ACTION_FORWARD,
2018         MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2019         MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
2020         MLXSW_REG_HPKT_ACTION_DISCARD,
2021         MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
2022         MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
2023 };
2024
2025 /* reg_hpkt_action
2026  * Action to perform on packet when trapped.
2027  * 0 - No action. Forward to CPU based on switching rules.
2028  * 1 - Trap to CPU (CPU receives sole copy).
2029  * 2 - Mirror to CPU (CPU receives a replica of the packet).
2030  * 3 - Discard.
2031  * 4 - Soft discard (allow other traps to act on the packet).
2032  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
2033  * Access: RW
2034  *
2035  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
2036  * addressed to the CPU.
2037  */
2038 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
2039
2040 /* reg_hpkt_trap_group
2041  * Trap group to associate the trap with.
2042  * Access: RW
2043  */
2044 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
2045
2046 /* reg_hpkt_trap_id
2047  * Trap ID.
2048  * Access: Index
2049  *
2050  * Note: A trap ID can only be associated with a single trap group. The device
2051  * will associate the trap ID with the last trap group configured.
2052  */
2053 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
2054
2055 enum {
2056         MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
2057         MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
2058         MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
2059 };
2060
2061 /* reg_hpkt_ctrl
2062  * Configure dedicated buffer resources for control packets.
2063  * 0 - Keep factory defaults.
2064  * 1 - Do not use control buffer for this trap ID.
2065  * 2 - Use control buffer for this trap ID.
2066  * Access: RW
2067  */
2068 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
2069
2070 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
2071 {
2072         enum mlxsw_reg_htgt_trap_group trap_group;
2073
2074         MLXSW_REG_ZERO(hpkt, payload);
2075         mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
2076         mlxsw_reg_hpkt_action_set(payload, action);
2077         switch (trap_id) {
2078         case MLXSW_TRAP_ID_ETHEMAD:
2079         case MLXSW_TRAP_ID_PUDE:
2080                 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
2081                 break;
2082         default:
2083                 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
2084                 break;
2085         }
2086         mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
2087         mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
2088         mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
2089 }
2090
2091 /* SBPR - Shared Buffer Pools Register
2092  * -----------------------------------
2093  * The SBPR configures and retrieves the shared buffer pools and configuration.
2094  */
2095 #define MLXSW_REG_SBPR_ID 0xB001
2096 #define MLXSW_REG_SBPR_LEN 0x14
2097
2098 static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
2099         .id = MLXSW_REG_SBPR_ID,
2100         .len = MLXSW_REG_SBPR_LEN,
2101 };
2102
2103 enum mlxsw_reg_sbpr_dir {
2104         MLXSW_REG_SBPR_DIR_INGRESS,
2105         MLXSW_REG_SBPR_DIR_EGRESS,
2106 };
2107
2108 /* reg_sbpr_dir
2109  * Direction.
2110  * Access: Index
2111  */
2112 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
2113
2114 /* reg_sbpr_pool
2115  * Pool index.
2116  * Access: Index
2117  */
2118 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
2119
2120 /* reg_sbpr_size
2121  * Pool size in buffer cells.
2122  * Access: RW
2123  */
2124 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
2125
2126 enum mlxsw_reg_sbpr_mode {
2127         MLXSW_REG_SBPR_MODE_STATIC,
2128         MLXSW_REG_SBPR_MODE_DYNAMIC,
2129 };
2130
2131 /* reg_sbpr_mode
2132  * Pool quota calculation mode.
2133  * Access: RW
2134  */
2135 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
2136
2137 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
2138                                        enum mlxsw_reg_sbpr_dir dir,
2139                                        enum mlxsw_reg_sbpr_mode mode, u32 size)
2140 {
2141         MLXSW_REG_ZERO(sbpr, payload);
2142         mlxsw_reg_sbpr_pool_set(payload, pool);
2143         mlxsw_reg_sbpr_dir_set(payload, dir);
2144         mlxsw_reg_sbpr_mode_set(payload, mode);
2145         mlxsw_reg_sbpr_size_set(payload, size);
2146 }
2147
2148 /* SBCM - Shared Buffer Class Management Register
2149  * ----------------------------------------------
2150  * The SBCM register configures and retrieves the shared buffer allocation
2151  * and configuration according to Port-PG, including the binding to pool
2152  * and definition of the associated quota.
2153  */
2154 #define MLXSW_REG_SBCM_ID 0xB002
2155 #define MLXSW_REG_SBCM_LEN 0x28
2156
2157 static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
2158         .id = MLXSW_REG_SBCM_ID,
2159         .len = MLXSW_REG_SBCM_LEN,
2160 };
2161
2162 /* reg_sbcm_local_port
2163  * Local port number.
2164  * For Ingress: excludes CPU port and Router port
2165  * For Egress: excludes IP Router
2166  * Access: Index
2167  */
2168 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
2169
2170 /* reg_sbcm_pg_buff
2171  * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
2172  * For PG buffer: range is 0..cap_max_pg_buffers - 1
2173  * For traffic class: range is 0..cap_max_tclass - 1
2174  * Note that when traffic class is in MC aware mode then the traffic
2175  * classes which are MC aware cannot be configured.
2176  * Access: Index
2177  */
2178 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
2179
2180 enum mlxsw_reg_sbcm_dir {
2181         MLXSW_REG_SBCM_DIR_INGRESS,
2182         MLXSW_REG_SBCM_DIR_EGRESS,
2183 };
2184
2185 /* reg_sbcm_dir
2186  * Direction.
2187  * Access: Index
2188  */
2189 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
2190
2191 /* reg_sbcm_min_buff
2192  * Minimum buffer size for the limiter, in cells.
2193  * Access: RW
2194  */
2195 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
2196
2197 /* reg_sbcm_max_buff
2198  * When the pool associated to the port-pg/tclass is configured to
2199  * static, Maximum buffer size for the limiter configured in cells.
2200  * When the pool associated to the port-pg/tclass is configured to
2201  * dynamic, the max_buff holds the "alpha" parameter, supporting
2202  * the following values:
2203  * 0: 0
2204  * i: (1/128)*2^(i-1), for i=1..14
2205  * 0xFF: Infinity
2206  * Access: RW
2207  */
2208 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
2209
2210 /* reg_sbcm_pool
2211  * Association of the port-priority to a pool.
2212  * Access: RW
2213  */
2214 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
2215
2216 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
2217                                        enum mlxsw_reg_sbcm_dir dir,
2218                                        u32 min_buff, u32 max_buff, u8 pool)
2219 {
2220         MLXSW_REG_ZERO(sbcm, payload);
2221         mlxsw_reg_sbcm_local_port_set(payload, local_port);
2222         mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
2223         mlxsw_reg_sbcm_dir_set(payload, dir);
2224         mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
2225         mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
2226         mlxsw_reg_sbcm_pool_set(payload, pool);
2227 }
2228
2229 /* SBPM - Shared Buffer Class Management Register
2230  * ----------------------------------------------
2231  * The SBPM register configures and retrieves the shared buffer allocation
2232  * and configuration according to Port-Pool, including the definition
2233  * of the associated quota.
2234  */
2235 #define MLXSW_REG_SBPM_ID 0xB003
2236 #define MLXSW_REG_SBPM_LEN 0x28
2237
2238 static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
2239         .id = MLXSW_REG_SBPM_ID,
2240         .len = MLXSW_REG_SBPM_LEN,
2241 };
2242
2243 /* reg_sbpm_local_port
2244  * Local port number.
2245  * For Ingress: excludes CPU port and Router port
2246  * For Egress: excludes IP Router
2247  * Access: Index
2248  */
2249 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
2250
2251 /* reg_sbpm_pool
2252  * The pool associated to quota counting on the local_port.
2253  * Access: Index
2254  */
2255 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
2256
2257 enum mlxsw_reg_sbpm_dir {
2258         MLXSW_REG_SBPM_DIR_INGRESS,
2259         MLXSW_REG_SBPM_DIR_EGRESS,
2260 };
2261
2262 /* reg_sbpm_dir
2263  * Direction.
2264  * Access: Index
2265  */
2266 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
2267
2268 /* reg_sbpm_min_buff
2269  * Minimum buffer size for the limiter, in cells.
2270  * Access: RW
2271  */
2272 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
2273
2274 /* reg_sbpm_max_buff
2275  * When the pool associated to the port-pg/tclass is configured to
2276  * static, Maximum buffer size for the limiter configured in cells.
2277  * When the pool associated to the port-pg/tclass is configured to
2278  * dynamic, the max_buff holds the "alpha" parameter, supporting
2279  * the following values:
2280  * 0: 0
2281  * i: (1/128)*2^(i-1), for i=1..14
2282  * 0xFF: Infinity
2283  * Access: RW
2284  */
2285 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
2286
2287 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
2288                                        enum mlxsw_reg_sbpm_dir dir,
2289                                        u32 min_buff, u32 max_buff)
2290 {
2291         MLXSW_REG_ZERO(sbpm, payload);
2292         mlxsw_reg_sbpm_local_port_set(payload, local_port);
2293         mlxsw_reg_sbpm_pool_set(payload, pool);
2294         mlxsw_reg_sbpm_dir_set(payload, dir);
2295         mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
2296         mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
2297 }
2298
2299 /* SBMM - Shared Buffer Multicast Management Register
2300  * --------------------------------------------------
2301  * The SBMM register configures and retrieves the shared buffer allocation
2302  * and configuration for MC packets according to Switch-Priority, including
2303  * the binding to pool and definition of the associated quota.
2304  */
2305 #define MLXSW_REG_SBMM_ID 0xB004
2306 #define MLXSW_REG_SBMM_LEN 0x28
2307
2308 static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
2309         .id = MLXSW_REG_SBMM_ID,
2310         .len = MLXSW_REG_SBMM_LEN,
2311 };
2312
2313 /* reg_sbmm_prio
2314  * Switch Priority.
2315  * Access: Index
2316  */
2317 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
2318
2319 /* reg_sbmm_min_buff
2320  * Minimum buffer size for the limiter, in cells.
2321  * Access: RW
2322  */
2323 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
2324
2325 /* reg_sbmm_max_buff
2326  * When the pool associated to the port-pg/tclass is configured to
2327  * static, Maximum buffer size for the limiter configured in cells.
2328  * When the pool associated to the port-pg/tclass is configured to
2329  * dynamic, the max_buff holds the "alpha" parameter, supporting
2330  * the following values:
2331  * 0: 0
2332  * i: (1/128)*2^(i-1), for i=1..14
2333  * 0xFF: Infinity
2334  * Access: RW
2335  */
2336 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
2337
2338 /* reg_sbmm_pool
2339  * Association of the port-priority to a pool.
2340  * Access: RW
2341  */
2342 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
2343
2344 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
2345                                        u32 max_buff, u8 pool)
2346 {
2347         MLXSW_REG_ZERO(sbmm, payload);
2348         mlxsw_reg_sbmm_prio_set(payload, prio);
2349         mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
2350         mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
2351         mlxsw_reg_sbmm_pool_set(payload, pool);
2352 }
2353
2354 static inline const char *mlxsw_reg_id_str(u16 reg_id)
2355 {
2356         switch (reg_id) {
2357         case MLXSW_REG_SGCR_ID:
2358                 return "SGCR";
2359         case MLXSW_REG_SPAD_ID:
2360                 return "SPAD";
2361         case MLXSW_REG_SSPR_ID:
2362                 return "SSPR";
2363         case MLXSW_REG_SFDAT_ID:
2364                 return "SFDAT";
2365         case MLXSW_REG_SFD_ID:
2366                 return "SFD";
2367         case MLXSW_REG_SFN_ID:
2368                 return "SFN";
2369         case MLXSW_REG_SPMS_ID:
2370                 return "SPMS";
2371         case MLXSW_REG_SPVID_ID:
2372                 return "SPVID";
2373         case MLXSW_REG_SPVM_ID:
2374                 return "SPVM";
2375         case MLXSW_REG_SFGC_ID:
2376                 return "SFGC";
2377         case MLXSW_REG_SFTR_ID:
2378                 return "SFTR";
2379         case MLXSW_REG_SPMLR_ID:
2380                 return "SPMLR";
2381         case MLXSW_REG_SVFA_ID:
2382                 return "SVFA";
2383         case MLXSW_REG_SVPE_ID:
2384                 return "SVPE";
2385         case MLXSW_REG_SFMR_ID:
2386                 return "SFMR";
2387         case MLXSW_REG_SPVMLR_ID:
2388                 return "SPVMLR";
2389         case MLXSW_REG_PMLP_ID:
2390                 return "PMLP";
2391         case MLXSW_REG_PMTU_ID:
2392                 return "PMTU";
2393         case MLXSW_REG_PTYS_ID:
2394                 return "PTYS";
2395         case MLXSW_REG_PPAD_ID:
2396                 return "PPAD";
2397         case MLXSW_REG_PAOS_ID:
2398                 return "PAOS";
2399         case MLXSW_REG_PPCNT_ID:
2400                 return "PPCNT";
2401         case MLXSW_REG_PBMC_ID:
2402                 return "PBMC";
2403         case MLXSW_REG_PSPA_ID:
2404                 return "PSPA";
2405         case MLXSW_REG_HTGT_ID:
2406                 return "HTGT";
2407         case MLXSW_REG_HPKT_ID:
2408                 return "HPKT";
2409         case MLXSW_REG_SBPR_ID:
2410                 return "SBPR";
2411         case MLXSW_REG_SBCM_ID:
2412                 return "SBCM";
2413         case MLXSW_REG_SBPM_ID:
2414                 return "SBPM";
2415         case MLXSW_REG_SBMM_ID:
2416                 return "SBMM";
2417         default:
2418                 return "*UNKNOWN*";
2419         }
2420 }
2421
2422 /* PUDE - Port Up / Down Event
2423  * ---------------------------
2424  * Reports the operational state change of a port.
2425  */
2426 #define MLXSW_REG_PUDE_LEN 0x10
2427
2428 /* reg_pude_swid
2429  * Switch partition ID with which to associate the port.
2430  * Access: Index
2431  */
2432 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
2433
2434 /* reg_pude_local_port
2435  * Local port number.
2436  * Access: Index
2437  */
2438 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
2439
2440 /* reg_pude_admin_status
2441  * Port administrative state (the desired state).
2442  * 1 - Up.
2443  * 2 - Down.
2444  * 3 - Up once. This means that in case of link failure, the port won't go
2445  *     into polling mode, but will wait to be re-enabled by software.
2446  * 4 - Disabled by system. Can only be set by hardware.
2447  * Access: RO
2448  */
2449 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
2450
2451 /* reg_pude_oper_status
2452  * Port operatioanl state.
2453  * 1 - Up.
2454  * 2 - Down.
2455  * 3 - Down by port failure. This means that the device will not let the
2456  *     port up again until explicitly specified by software.
2457  * Access: RO
2458  */
2459 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
2460
2461 #endif