drivers/net/ethernet/mellanox/mlxsw/reg.h

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/reg.h
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com>
   5  * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
   6  * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com>
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Neither the names of the copyright holders nor the names of its
  17  *    contributors may be used to endorse or promote products derived from
  18  *    this software without specific prior written permission.
  19  *
  20  * Alternatively, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") version 2 as published by the Free
  22  * Software Foundation.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  28  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34  * POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #ifndef _MLXSW_REG_H
  38 #define _MLXSW_REG_H
  39
  40 #include <linux/string.h>
  41 #include <linux/bitops.h>
  42 #include <linux/if_vlan.h>
  43
  44 #include "item.h"
  45 #include "port.h"
  46
  47 struct mlxsw_reg_info {
  48         u16 id;
  49         u16 len; /* In u8 */
  50 };
  51
  52 #define MLXSW_REG(type) (&mlxsw_reg_##type)
  53 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
  54 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
  55
  56 /* SGCR - Switch General Configuration Register
  57  * --------------------------------------------
  58  * This register is used for configuration of the switch capabilities.
  59  */
  60 #define MLXSW_REG_SGCR_ID 0x2000
  61 #define MLXSW_REG_SGCR_LEN 0x10
  62
  63 static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
  64         .id = MLXSW_REG_SGCR_ID,
  65         .len = MLXSW_REG_SGCR_LEN,
  66 };
  67
  68 /* reg_sgcr_llb
  69  * Link Local Broadcast (Default=0)
  70  * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
  71  * packets and ignore the IGMP snooping entries.
  72  * Access: RW
  73  */
  74 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
  75
  76 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
  77 {
  78         MLXSW_REG_ZERO(sgcr, payload);
  79         mlxsw_reg_sgcr_llb_set(payload, !!llb);
  80 }
  81
  82 /* SPAD - Switch Physical Address Register
  83  * ---------------------------------------
  84  * The SPAD register configures the switch physical MAC address.
  85  */
  86 #define MLXSW_REG_SPAD_ID 0x2002
  87 #define MLXSW_REG_SPAD_LEN 0x10
  88
  89 static const struct mlxsw_reg_info mlxsw_reg_spad = {
  90         .id = MLXSW_REG_SPAD_ID,
  91         .len = MLXSW_REG_SPAD_LEN,
  92 };
  93
  94 /* reg_spad_base_mac
  95  * Base MAC address for the switch partitions.
  96  * Per switch partition MAC address is equal to:
  97  * base_mac + swid
  98  * Access: RW
  99  */
 100 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
 101
 102 /* SMID - Switch Multicast ID
 103  * --------------------------
 104  * The MID record maps from a MID (Multicast ID), which is a unique identifier
 105  * of the multicast group within the stacking domain, into a list of local
 106  * ports into which the packet is replicated.
 107  */
 108 #define MLXSW_REG_SMID_ID 0x2007
 109 #define MLXSW_REG_SMID_LEN 0x240
 110
 111 static const struct mlxsw_reg_info mlxsw_reg_smid = {
 112         .id = MLXSW_REG_SMID_ID,
 113         .len = MLXSW_REG_SMID_LEN,
 114 };
 115
 116 /* reg_smid_swid
 117  * Switch partition ID.
 118  * Access: Index
 119  */
 120 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
 121
 122 /* reg_smid_mid
 123  * Multicast identifier - global identifier that represents the multicast group
 124  * across all devices.
 125  * Access: Index
 126  */
 127 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
 128
 129 /* reg_smid_port
 130  * Local port memebership (1 bit per port).
 131  * Access: RW
 132  */
 133 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
 134
 135 /* reg_smid_port_mask
 136  * Local port mask (1 bit per port).
 137  * Access: W
 138  */
 139 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
 140
 141 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
 142                                        u8 port, bool set)
 143 {
 144         MLXSW_REG_ZERO(smid, payload);
 145         mlxsw_reg_smid_swid_set(payload, 0);
 146         mlxsw_reg_smid_mid_set(payload, mid);
 147         mlxsw_reg_smid_port_set(payload, port, set);
 148         mlxsw_reg_smid_port_mask_set(payload, port, 1);
 149 }
 150
 151 /* SSPR - Switch System Port Record Register
 152  * -----------------------------------------
 153  * Configures the system port to local port mapping.
 154  */
 155 #define MLXSW_REG_SSPR_ID 0x2008
 156 #define MLXSW_REG_SSPR_LEN 0x8
 157
 158 static const struct mlxsw_reg_info mlxsw_reg_sspr = {
 159         .id = MLXSW_REG_SSPR_ID,
 160         .len = MLXSW_REG_SSPR_LEN,
 161 };
 162
 163 /* reg_sspr_m
 164  * Master - if set, then the record describes the master system port.
 165  * This is needed in case a local port is mapped into several system ports
 166  * (for multipathing). That number will be reported as the source system
 167  * port when packets are forwarded to the CPU. Only one master port is allowed
 168  * per local port.
 169  *
 170  * Note: Must be set for Spectrum.
 171  * Access: RW
 172  */
 173 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
 174
 175 /* reg_sspr_local_port
 176  * Local port number.
 177  *
 178  * Access: RW
 179  */
 180 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
 181
 182 /* reg_sspr_sub_port
 183  * Virtual port within the physical port.
 184  * Should be set to 0 when virtual ports are not enabled on the port.
 185  *
 186  * Access: RW
 187  */
 188 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
 189
 190 /* reg_sspr_system_port
 191  * Unique identifier within the stacking domain that represents all the ports
 192  * that are available in the system (external ports).
 193  *
 194  * Currently, only single-ASIC configurations are supported, so we default to
 195  * 1:1 mapping between system ports and local ports.
 196  * Access: Index
 197  */
 198 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
 199
 200 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
 201 {
 202         MLXSW_REG_ZERO(sspr, payload);
 203         mlxsw_reg_sspr_m_set(payload, 1);
 204         mlxsw_reg_sspr_local_port_set(payload, local_port);
 205         mlxsw_reg_sspr_sub_port_set(payload, 0);
 206         mlxsw_reg_sspr_system_port_set(payload, local_port);
 207 }
 208
 209 /* SFDAT - Switch Filtering Database Aging Time
 210  * --------------------------------------------
 211  * Controls the Switch aging time. Aging time is able to be set per Switch
 212  * Partition.
 213  */
 214 #define MLXSW_REG_SFDAT_ID 0x2009
 215 #define MLXSW_REG_SFDAT_LEN 0x8
 216
 217 static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
 218         .id = MLXSW_REG_SFDAT_ID,
 219         .len = MLXSW_REG_SFDAT_LEN,
 220 };
 221
 222 /* reg_sfdat_swid
 223  * Switch partition ID.
 224  * Access: Index
 225  */
 226 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
 227
 228 /* reg_sfdat_age_time
 229  * Aging time in seconds
 230  * Min - 10 seconds
 231  * Max - 1,000,000 seconds
 232  * Default is 300 seconds.
 233  * Access: RW
 234  */
 235 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
 236
 237 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
 238 {
 239         MLXSW_REG_ZERO(sfdat, payload);
 240         mlxsw_reg_sfdat_swid_set(payload, 0);
 241         mlxsw_reg_sfdat_age_time_set(payload, age_time);
 242 }
 243
 244 /* SFD - Switch Filtering Database
 245  * -------------------------------
 246  * The following register defines the access to the filtering database.
 247  * The register supports querying, adding, removing and modifying the database.
 248  * The access is optimized for bulk updates in which case more than one
 249  * FDB record is present in the same command.
 250  */
 251 #define MLXSW_REG_SFD_ID 0x200A
 252 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
 253 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
 254 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
 255 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +     \
 256                            MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
 257
 258 static const struct mlxsw_reg_info mlxsw_reg_sfd = {
 259         .id = MLXSW_REG_SFD_ID,
 260         .len = MLXSW_REG_SFD_LEN,
 261 };
 262
 263 /* reg_sfd_swid
 264  * Switch partition ID for queries. Reserved on Write.
 265  * Access: Index
 266  */
 267 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
 268
 269 enum mlxsw_reg_sfd_op {
 270         /* Dump entire FDB a (process according to record_locator) */
 271         MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
 272         /* Query records by {MAC, VID/FID} value */
 273         MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
 274         /* Query and clear activity. Query records by {MAC, VID/FID} value */
 275         MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
 276         /* Test. Response indicates if each of the records could be
 277          * added to the FDB.
 278          */
 279         MLXSW_REG_SFD_OP_WRITE_TEST = 0,
 280         /* Add/modify. Aged-out records cannot be added. This command removes
 281          * the learning notification of the {MAC, VID/FID}. Response includes
 282          * the entries that were added to the FDB.
 283          */
 284         MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
 285         /* Remove record by {MAC, VID/FID}. This command also removes
 286          * the learning notification and aged-out notifications
 287          * of the {MAC, VID/FID}. The response provides current (pre-removal)
 288          * entries as non-aged-out.
 289          */
 290         MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
 291         /* Remove learned notification by {MAC, VID/FID}. The response provides
 292          * the removed learning notification.
 293          */
 294         MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
 295 };
 296
 297 /* reg_sfd_op
 298  * Operation.
 299  * Access: OP
 300  */
 301 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
 302
 303 /* reg_sfd_record_locator
 304  * Used for querying the FDB. Use record_locator=0 to initiate the
 305  * query. When a record is returned, a new record_locator is
 306  * returned to be used in the subsequent query.
 307  * Reserved for database update.
 308  * Access: Index
 309  */
 310 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
 311
 312 /* reg_sfd_num_rec
 313  * Request: Number of records to read/add/modify/remove
 314  * Response: Number of records read/added/replaced/removed
 315  * See above description for more details.
 316  * Ranges 0..64
 317  * Access: RW
 318  */
 319 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
 320
 321 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
 322                                       u32 record_locator)
 323 {
 324         MLXSW_REG_ZERO(sfd, payload);
 325         mlxsw_reg_sfd_op_set(payload, op);
 326         mlxsw_reg_sfd_record_locator_set(payload, record_locator);
 327 }
 328
 329 /* reg_sfd_rec_swid
 330  * Switch partition ID.
 331  * Access: Index
 332  */
 333 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
 334                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 335
 336 enum mlxsw_reg_sfd_rec_type {
 337         MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
 338         MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
 339         MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
 340 };
 341
 342 /* reg_sfd_rec_type
 343  * FDB record type.
 344  * Access: RW
 345  */
 346 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
 347                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 348
 349 enum mlxsw_reg_sfd_rec_policy {
 350         /* Replacement disabled, aging disabled. */
 351         MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
 352         /* (mlag remote): Replacement enabled, aging disabled,
 353          * learning notification enabled on this port.
 354          */
 355         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
 356         /* (ingress device): Replacement enabled, aging enabled. */
 357         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
 358 };
 359
 360 /* reg_sfd_rec_policy
 361  * Policy.
 362  * Access: RW
 363  */
 364 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
 365                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 366
 367 /* reg_sfd_rec_a
 368  * Activity. Set for new static entries. Set for static entries if a frame SMAC
 369  * lookup hits on the entry.
 370  * To clear the a bit, use "query and clear activity" op.
 371  * Access: RO
 372  */
 373 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
 374                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 375
 376 /* reg_sfd_rec_mac
 377  * MAC address.
 378  * Access: Index
 379  */
 380 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
 381                        MLXSW_REG_SFD_REC_LEN, 0x02);
 382
 383 enum mlxsw_reg_sfd_rec_action {
 384         /* forward */
 385         MLXSW_REG_SFD_REC_ACTION_NOP = 0,
 386         /* forward and trap, trap_id is FDB_TRAP */
 387         MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
 388         /* trap and do not forward, trap_id is FDB_TRAP */
 389         MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
 390         /* forward to IP router */
 391         MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
 392         MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
 393 };
 394
 395 /* reg_sfd_rec_action
 396  * Action to apply on the packet.
 397  * Note: Dynamic entries can only be configured with NOP action.
 398  * Access: RW
 399  */
 400 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
 401                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 402
 403 /* reg_sfd_uc_sub_port
 404  * VEPA channel on local port.
 405  * Valid only if local port is a non-stacking port. Must be 0 if multichannel
 406  * VEPA is not enabled.
 407  * Access: RW
 408  */
 409 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 410                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 411
 412 /* reg_sfd_uc_fid_vid
 413  * Filtering ID or VLAN ID
 414  * For SwitchX and SwitchX-2:
 415  * - Dynamic entries (policy 2,3) use FID
 416  * - Static entries (policy 0) use VID
 417  * - When independent learning is configured, VID=FID
 418  * For Spectrum: use FID for both Dynamic and Static entries.
 419  * VID should not be used.
 420  * Access: Index
 421  */
 422 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 423                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 424
 425 /* reg_sfd_uc_system_port
 426  * Unique port identifier for the final destination of the packet.
 427  * Access: RW
 428  */
 429 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 430                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 431
 432 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
 433                                           enum mlxsw_reg_sfd_rec_type rec_type,
 434                                           const char *mac,
 435                                           enum mlxsw_reg_sfd_rec_action action)
 436 {
 437         u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
 438
 439         if (rec_index >= num_rec)
 440                 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
 441         mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
 442         mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
 443         mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
 444         mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
 445 }
 446
 447 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
 448                                          enum mlxsw_reg_sfd_rec_policy policy,
 449                                          const char *mac, u16 fid_vid,
 450                                          enum mlxsw_reg_sfd_rec_action action,
 451                                          u8 local_port)
 452 {
 453         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 454                                MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
 455         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 456         mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
 457         mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
 458         mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
 459 }
 460
 461 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
 462                                            char *mac, u16 *p_fid_vid,
 463                                            u8 *p_local_port)
 464 {
 465         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 466         *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
 467         *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
 468 }
 469
 470 /* reg_sfd_uc_lag_sub_port
 471  * LAG sub port.
 472  * Must be 0 if multichannel VEPA is not enabled.
 473  * Access: RW
 474  */
 475 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 476                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 477
 478 /* reg_sfd_uc_lag_fid_vid
 479  * Filtering ID or VLAN ID
 480  * For SwitchX and SwitchX-2:
 481  * - Dynamic entries (policy 2,3) use FID
 482  * - Static entries (policy 0) use VID
 483  * - When independent learning is configured, VID=FID
 484  * For Spectrum: use FID for both Dynamic and Static entries.
 485  * VID should not be used.
 486  * Access: Index
 487  */
 488 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 489                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 490
 491 /* reg_sfd_uc_lag_lag_vid
 492  * Indicates VID in case of vFIDs. Reserved for FIDs.
 493  * Access: RW
 494  */
 495 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
 496                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 497
 498 /* reg_sfd_uc_lag_lag_id
 499  * LAG Identifier - pointer into the LAG descriptor table.
 500  * Access: RW
 501  */
 502 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
 503                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 504
 505 static inline void
 506 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
 507                           enum mlxsw_reg_sfd_rec_policy policy,
 508                           const char *mac, u16 fid_vid,
 509                           enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
 510                           u16 lag_id)
 511 {
 512         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 513                                MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
 514                                mac, action);
 515         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 516         mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
 517         mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
 518         mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
 519         mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
 520 }
 521
 522 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
 523                                                char *mac, u16 *p_vid,
 524                                                u16 *p_lag_id)
 525 {
 526         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 527         *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
 528         *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
 529 }
 530
 531 /* reg_sfd_mc_pgi
 532  *
 533  * Multicast port group index - index into the port group table.
 534  * Value 0x1FFF indicates the pgi should point to the MID entry.
 535  * For Spectrum this value must be set to 0x1FFF
 536  * Access: RW
 537  */
 538 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
 539                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 540
 541 /* reg_sfd_mc_fid_vid
 542  *
 543  * Filtering ID or VLAN ID
 544  * Access: Index
 545  */
 546 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 547                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 548
 549 /* reg_sfd_mc_mid
 550  *
 551  * Multicast identifier - global identifier that represents the multicast
 552  * group across all devices.
 553  * Access: RW
 554  */
 555 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 556                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 557
 558 static inline void
 559 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
 560                       const char *mac, u16 fid_vid,
 561                       enum mlxsw_reg_sfd_rec_action action, u16 mid)
 562 {
 563         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 564                                MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
 565         mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
 566         mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
 567         mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
 568 }
 569
 570 /* SFN - Switch FDB Notification Register
 571  * -------------------------------------------
 572  * The switch provides notifications on newly learned FDB entries and
 573  * aged out entries. The notifications can be polled by software.
 574  */
 575 #define MLXSW_REG_SFN_ID 0x200B
 576 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
 577 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
 578 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
 579 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +     \
 580                            MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
 581
 582 static const struct mlxsw_reg_info mlxsw_reg_sfn = {
 583         .id = MLXSW_REG_SFN_ID,
 584         .len = MLXSW_REG_SFN_LEN,
 585 };
 586
 587 /* reg_sfn_swid
 588  * Switch partition ID.
 589  * Access: Index
 590  */
 591 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
 592
 593 /* reg_sfn_num_rec
 594  * Request: Number of learned notifications and aged-out notification
 595  * records requested.
 596  * Response: Number of notification records returned (must be smaller
 597  * than or equal to the value requested)
 598  * Ranges 0..64
 599  * Access: OP
 600  */
 601 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
 602
 603 static inline void mlxsw_reg_sfn_pack(char *payload)
 604 {
 605         MLXSW_REG_ZERO(sfn, payload);
 606         mlxsw_reg_sfn_swid_set(payload, 0);
 607         mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
 608 }
 609
 610 /* reg_sfn_rec_swid
 611  * Switch partition ID.
 612  * Access: RO
 613  */
 614 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
 615                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 616
 617 enum mlxsw_reg_sfn_rec_type {
 618         /* MAC addresses learned on a regular port. */
 619         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
 620         /* MAC addresses learned on a LAG port. */
 621         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
 622         /* Aged-out MAC address on a regular port. */
 623         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
 624         /* Aged-out MAC address on a LAG port. */
 625         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
 626 };
 627
 628 /* reg_sfn_rec_type
 629  * Notification record type.
 630  * Access: RO
 631  */
 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
 633                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 634
 635 /* reg_sfn_rec_mac
 636  * MAC address.
 637  * Access: RO
 638  */
 639 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
 640                        MLXSW_REG_SFN_REC_LEN, 0x02);
 641
 642 /* reg_sfn_mac_sub_port
 643  * VEPA channel on the local port.
 644  * 0 if multichannel VEPA is not enabled.
 645  * Access: RO
 646  */
 647 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
 648                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 649
 650 /* reg_sfn_mac_fid
 651  * Filtering identifier.
 652  * Access: RO
 653  */
 654 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 655                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 656
 657 /* reg_sfn_mac_system_port
 658  * Unique port identifier for the final destination of the packet.
 659  * Access: RO
 660  */
 661 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 662                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 663
 664 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
 665                                             char *mac, u16 *p_vid,
 666                                             u8 *p_local_port)
 667 {
 668         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 669         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 670         *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
 671 }
 672
 673 /* reg_sfn_mac_lag_lag_id
 674  * LAG ID (pointer into the LAG descriptor table).
 675  * Access: RO
 676  */
 677 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
 678                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 679
 680 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
 681                                                 char *mac, u16 *p_vid,
 682                                                 u16 *p_lag_id)
 683 {
 684         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 685         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 686         *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
 687 }
 688
 689 /* SPMS - Switch Port MSTP/RSTP State Register
 690  * -------------------------------------------
 691  * Configures the spanning tree state of a physical port.
 692  */
 693 #define MLXSW_REG_SPMS_ID 0x200D
 694 #define MLXSW_REG_SPMS_LEN 0x404
 695
 696 static const struct mlxsw_reg_info mlxsw_reg_spms = {
 697         .id = MLXSW_REG_SPMS_ID,
 698         .len = MLXSW_REG_SPMS_LEN,
 699 };
 700
 701 /* reg_spms_local_port
 702  * Local port number.
 703  * Access: Index
 704  */
 705 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
 706
 707 enum mlxsw_reg_spms_state {
 708         MLXSW_REG_SPMS_STATE_NO_CHANGE,
 709         MLXSW_REG_SPMS_STATE_DISCARDING,
 710         MLXSW_REG_SPMS_STATE_LEARNING,
 711         MLXSW_REG_SPMS_STATE_FORWARDING,
 712 };
 713
 714 /* reg_spms_state
 715  * Spanning tree state of each VLAN ID (VID) of the local port.
 716  * 0 - Do not change spanning tree state (used only when writing).
 717  * 1 - Discarding. No learning or forwarding to/from this port (default).
 718  * 2 - Learning. Port is learning, but not forwarding.
 719  * 3 - Forwarding. Port is learning and forwarding.
 720  * Access: RW
 721  */
 722 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
 723
 724 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
 725 {
 726         MLXSW_REG_ZERO(spms, payload);
 727         mlxsw_reg_spms_local_port_set(payload, local_port);
 728 }
 729
 730 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
 731                                            enum mlxsw_reg_spms_state state)
 732 {
 733         mlxsw_reg_spms_state_set(payload, vid, state);
 734 }
 735
 736 /* SPVID - Switch Port VID
 737  * -----------------------
 738  * The switch port VID configures the default VID for a port.
 739  */
 740 #define MLXSW_REG_SPVID_ID 0x200E
 741 #define MLXSW_REG_SPVID_LEN 0x08
 742
 743 static const struct mlxsw_reg_info mlxsw_reg_spvid = {
 744         .id = MLXSW_REG_SPVID_ID,
 745         .len = MLXSW_REG_SPVID_LEN,
 746 };
 747
 748 /* reg_spvid_local_port
 749  * Local port number.
 750  * Access: Index
 751  */
 752 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
 753
 754 /* reg_spvid_sub_port
 755  * Virtual port within the physical port.
 756  * Should be set to 0 when virtual ports are not enabled on the port.
 757  * Access: Index
 758  */
 759 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
 760
 761 /* reg_spvid_pvid
 762  * Port default VID
 763  * Access: RW
 764  */
 765 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
 766
 767 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
 768 {
 769         MLXSW_REG_ZERO(spvid, payload);
 770         mlxsw_reg_spvid_local_port_set(payload, local_port);
 771         mlxsw_reg_spvid_pvid_set(payload, pvid);
 772 }
 773
 774 /* SPVM - Switch Port VLAN Membership
 775  * ----------------------------------
 776  * The Switch Port VLAN Membership register configures the VLAN membership
 777  * of a port in a VLAN denoted by VID. VLAN membership is managed per
 778  * virtual port. The register can be used to add and remove VID(s) from a port.
 779  */
 780 #define MLXSW_REG_SPVM_ID 0x200F
 781 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
 782 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
 783 #define MLXSW_REG_SPVM_REC_MAX_COUNT 256
 784 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +   \
 785                     MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
 786
 787 static const struct mlxsw_reg_info mlxsw_reg_spvm = {
 788         .id = MLXSW_REG_SPVM_ID,
 789         .len = MLXSW_REG_SPVM_LEN,
 790 };
 791
 792 /* reg_spvm_pt
 793  * Priority tagged. If this bit is set, packets forwarded to the port with
 794  * untagged VLAN membership (u bit is set) will be tagged with priority tag
 795  * (VID=0)
 796  * Access: RW
 797  */
 798 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
 799
 800 /* reg_spvm_pte
 801  * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
 802  * the pt bit will NOT be updated. To update the pt bit, pte must be set.
 803  * Access: WO
 804  */
 805 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
 806
 807 /* reg_spvm_local_port
 808  * Local port number.
 809  * Access: Index
 810  */
 811 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
 812
 813 /* reg_spvm_sub_port
 814  * Virtual port within the physical port.
 815  * Should be set to 0 when virtual ports are not enabled on the port.
 816  * Access: Index
 817  */
 818 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
 819
 820 /* reg_spvm_num_rec
 821  * Number of records to update. Each record contains: i, e, u, vid.
 822  * Access: OP
 823  */
 824 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
 825
 826 /* reg_spvm_rec_i
 827  * Ingress membership in VLAN ID.
 828  * Access: Index
 829  */
 830 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
 831                      MLXSW_REG_SPVM_BASE_LEN, 14, 1,
 832                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 833
 834 /* reg_spvm_rec_e
 835  * Egress membership in VLAN ID.
 836  * Access: Index
 837  */
 838 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
 839                      MLXSW_REG_SPVM_BASE_LEN, 13, 1,
 840                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 841
 842 /* reg_spvm_rec_u
 843  * Untagged - port is an untagged member - egress transmission uses untagged
 844  * frames on VID<n>
 845  * Access: Index
 846  */
 847 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
 848                      MLXSW_REG_SPVM_BASE_LEN, 12, 1,
 849                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 850
 851 /* reg_spvm_rec_vid
 852  * Egress membership in VLAN ID.
 853  * Access: Index
 854  */
 855 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
 856                      MLXSW_REG_SPVM_BASE_LEN, 0, 12,
 857                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 858
 859 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
 860                                        u16 vid_begin, u16 vid_end,
 861                                        bool is_member, bool untagged)
 862 {
 863         int size = vid_end - vid_begin + 1;
 864         int i;
 865
 866         MLXSW_REG_ZERO(spvm, payload);
 867         mlxsw_reg_spvm_local_port_set(payload, local_port);
 868         mlxsw_reg_spvm_num_rec_set(payload, size);
 869
 870         for (i = 0; i < size; i++) {
 871                 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
 872                 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
 873                 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
 874                 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
 875         }
 876 }
 877
 878 /* SPAFT - Switch Port Acceptable Frame Types
 879  * ------------------------------------------
 880  * The Switch Port Acceptable Frame Types register configures the frame
 881  * admittance of the port.
 882  */
 883 #define MLXSW_REG_SPAFT_ID 0x2010
 884 #define MLXSW_REG_SPAFT_LEN 0x08
 885
 886 static const struct mlxsw_reg_info mlxsw_reg_spaft = {
 887         .id = MLXSW_REG_SPAFT_ID,
 888         .len = MLXSW_REG_SPAFT_LEN,
 889 };
 890
 891 /* reg_spaft_local_port
 892  * Local port number.
 893  * Access: Index
 894  *
 895  * Note: CPU port is not supported (all tag types are allowed).
 896  */
 897 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
 898
 899 /* reg_spaft_sub_port
 900  * Virtual port within the physical port.
 901  * Should be set to 0 when virtual ports are not enabled on the port.
 902  * Access: RW
 903  */
 904 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
 905
 906 /* reg_spaft_allow_untagged
 907  * When set, untagged frames on the ingress are allowed (default).
 908  * Access: RW
 909  */
 910 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
 911
 912 /* reg_spaft_allow_prio_tagged
 913  * When set, priority tagged frames on the ingress are allowed (default).
 914  * Access: RW
 915  */
 916 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
 917
 918 /* reg_spaft_allow_tagged
 919  * When set, tagged frames on the ingress are allowed (default).
 920  * Access: RW
 921  */
 922 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
 923
 924 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
 925                                         bool allow_untagged)
 926 {
 927         MLXSW_REG_ZERO(spaft, payload);
 928         mlxsw_reg_spaft_local_port_set(payload, local_port);
 929         mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
 930         mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
 931         mlxsw_reg_spaft_allow_tagged_set(payload, true);
 932 }
 933
 934 /* SFGC - Switch Flooding Group Configuration
 935  * ------------------------------------------
 936  * The following register controls the association of flooding tables and MIDs
 937  * to packet types used for flooding.
 938  */
 939 #define MLXSW_REG_SFGC_ID 0x2011
 940 #define MLXSW_REG_SFGC_LEN 0x10
 941
 942 static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
 943         .id = MLXSW_REG_SFGC_ID,
 944         .len = MLXSW_REG_SFGC_LEN,
 945 };
 946
 947 enum mlxsw_reg_sfgc_type {
 948         MLXSW_REG_SFGC_TYPE_BROADCAST,
 949         MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
 950         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
 951         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
 952         MLXSW_REG_SFGC_TYPE_RESERVED,
 953         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
 954         MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
 955         MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
 956         MLXSW_REG_SFGC_TYPE_MAX,
 957 };
 958
 959 /* reg_sfgc_type
 960  * The traffic type to reach the flooding table.
 961  * Access: Index
 962  */
 963 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
 964
 965 enum mlxsw_reg_sfgc_bridge_type {
 966         MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
 967         MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
 968 };
 969
 970 /* reg_sfgc_bridge_type
 971  * Access: Index
 972  *
 973  * Note: SwitchX-2 only supports 802.1Q mode.
 974  */
 975 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
 976
 977 enum mlxsw_flood_table_type {
 978         MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
 979         MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
 980         MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
 981         MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
 982         MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
 983 };
 984
 985 /* reg_sfgc_table_type
 986  * See mlxsw_flood_table_type
 987  * Access: RW
 988  *
 989  * Note: FID offset and FID types are not supported in SwitchX-2.
 990  */
 991 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
 992
 993 /* reg_sfgc_flood_table
 994  * Flooding table index to associate with the specific type on the specific
 995  * switch partition.
 996  * Access: RW
 997  */
 998 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
 999
1000 /* reg_sfgc_mid
1001  * The multicast ID for the swid. Not supported for Spectrum
1002  * Access: RW
1003  */
1004 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1005
1006 /* reg_sfgc_counter_set_type
1007  * Counter Set Type for flow counters.
1008  * Access: RW
1009  */
1010 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1011
1012 /* reg_sfgc_counter_index
1013  * Counter Index for flow counters.
1014  * Access: RW
1015  */
1016 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1017
1018 static inline void
1019 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1020                     enum mlxsw_reg_sfgc_bridge_type bridge_type,
1021                     enum mlxsw_flood_table_type table_type,
1022                     unsigned int flood_table)
1023 {
1024         MLXSW_REG_ZERO(sfgc, payload);
1025         mlxsw_reg_sfgc_type_set(payload, type);
1026         mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1027         mlxsw_reg_sfgc_table_type_set(payload, table_type);
1028         mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1029         mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1030 }
1031
1032 /* SFTR - Switch Flooding Table Register
1033  * -------------------------------------
1034  * The switch flooding table is used for flooding packet replication. The table
1035  * defines a bit mask of ports for packet replication.
1036  */
1037 #define MLXSW_REG_SFTR_ID 0x2012
1038 #define MLXSW_REG_SFTR_LEN 0x420
1039
1040 static const struct mlxsw_reg_info mlxsw_reg_sftr = {
1041         .id = MLXSW_REG_SFTR_ID,
1042         .len = MLXSW_REG_SFTR_LEN,
1043 };
1044
1045 /* reg_sftr_swid
1046  * Switch partition ID with which to associate the port.
1047  * Access: Index
1048  */
1049 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1050
1051 /* reg_sftr_flood_table
1052  * Flooding table index to associate with the specific type on the specific
1053  * switch partition.
1054  * Access: Index
1055  */
1056 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1057
1058 /* reg_sftr_index
1059  * Index. Used as an index into the Flooding Table in case the table is
1060  * configured to use VID / FID or FID Offset.
1061  * Access: Index
1062  */
1063 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1064
1065 /* reg_sftr_table_type
1066  * See mlxsw_flood_table_type
1067  * Access: RW
1068  */
1069 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1070
1071 /* reg_sftr_range
1072  * Range of entries to update
1073  * Access: Index
1074  */
1075 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1076
1077 /* reg_sftr_port
1078  * Local port membership (1 bit per port).
1079  * Access: RW
1080  */
1081 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1082
1083 /* reg_sftr_cpu_port_mask
1084  * CPU port mask (1 bit per port).
1085  * Access: W
1086  */
1087 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1088
1089 static inline void mlxsw_reg_sftr_pack(char *payload,
1090                                        unsigned int flood_table,
1091                                        unsigned int index,
1092                                        enum mlxsw_flood_table_type table_type,
1093                                        unsigned int range, u8 port, bool set)
1094 {
1095         MLXSW_REG_ZERO(sftr, payload);
1096         mlxsw_reg_sftr_swid_set(payload, 0);
1097         mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1098         mlxsw_reg_sftr_index_set(payload, index);
1099         mlxsw_reg_sftr_table_type_set(payload, table_type);
1100         mlxsw_reg_sftr_range_set(payload, range);
1101         mlxsw_reg_sftr_port_set(payload, port, set);
1102         mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1103 }
1104
1105 /* SFDF - Switch Filtering DB Flush
1106  * --------------------------------
1107  * The switch filtering DB flush register is used to flush the FDB.
1108  * Note that FDB notifications are flushed as well.
1109  */
1110 #define MLXSW_REG_SFDF_ID 0x2013
1111 #define MLXSW_REG_SFDF_LEN 0x14
1112
1113 static const struct mlxsw_reg_info mlxsw_reg_sfdf = {
1114         .id = MLXSW_REG_SFDF_ID,
1115         .len = MLXSW_REG_SFDF_LEN,
1116 };
1117
1118 /* reg_sfdf_swid
1119  * Switch partition ID.
1120  * Access: Index
1121  */
1122 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1123
1124 enum mlxsw_reg_sfdf_flush_type {
1125         MLXSW_REG_SFDF_FLUSH_PER_SWID,
1126         MLXSW_REG_SFDF_FLUSH_PER_FID,
1127         MLXSW_REG_SFDF_FLUSH_PER_PORT,
1128         MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1129         MLXSW_REG_SFDF_FLUSH_PER_LAG,
1130         MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1131 };
1132
1133 /* reg_sfdf_flush_type
1134  * Flush type.
1135  * 0 - All SWID dynamic entries are flushed.
1136  * 1 - All FID dynamic entries are flushed.
1137  * 2 - All dynamic entries pointing to port are flushed.
1138  * 3 - All FID dynamic entries pointing to port are flushed.
1139  * 4 - All dynamic entries pointing to LAG are flushed.
1140  * 5 - All FID dynamic entries pointing to LAG are flushed.
1141  * Access: RW
1142  */
1143 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1144
1145 /* reg_sfdf_flush_static
1146  * Static.
1147  * 0 - Flush only dynamic entries.
1148  * 1 - Flush both dynamic and static entries.
1149  * Access: RW
1150  */
1151 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1152
1153 static inline void mlxsw_reg_sfdf_pack(char *payload,
1154                                        enum mlxsw_reg_sfdf_flush_type type)
1155 {
1156         MLXSW_REG_ZERO(sfdf, payload);
1157         mlxsw_reg_sfdf_flush_type_set(payload, type);
1158         mlxsw_reg_sfdf_flush_static_set(payload, true);
1159 }
1160
1161 /* reg_sfdf_fid
1162  * FID to flush.
1163  * Access: RW
1164  */
1165 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1166
1167 /* reg_sfdf_system_port
1168  * Port to flush.
1169  * Access: RW
1170  */
1171 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1172
1173 /* reg_sfdf_port_fid_system_port
1174  * Port to flush, pointed to by FID.
1175  * Access: RW
1176  */
1177 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1178
1179 /* reg_sfdf_lag_id
1180  * LAG ID to flush.
1181  * Access: RW
1182  */
1183 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1184
1185 /* reg_sfdf_lag_fid_lag_id
1186  * LAG ID to flush, pointed to by FID.
1187  * Access: RW
1188  */
1189 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1190
1191 /* SLDR - Switch LAG Descriptor Register
1192  * -----------------------------------------
1193  * The switch LAG descriptor register is populated by LAG descriptors.
1194  * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1195  * max_lag-1.
1196  */
1197 #define MLXSW_REG_SLDR_ID 0x2014
1198 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1199
1200 static const struct mlxsw_reg_info mlxsw_reg_sldr = {
1201         .id = MLXSW_REG_SLDR_ID,
1202         .len = MLXSW_REG_SLDR_LEN,
1203 };
1204
1205 enum mlxsw_reg_sldr_op {
1206         /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1207         MLXSW_REG_SLDR_OP_LAG_CREATE,
1208         MLXSW_REG_SLDR_OP_LAG_DESTROY,
1209         /* Ports that appear in the list have the Distributor enabled */
1210         MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1211         /* Removes ports from the disributor list */
1212         MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1213 };
1214
1215 /* reg_sldr_op
1216  * Operation.
1217  * Access: RW
1218  */
1219 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1220
1221 /* reg_sldr_lag_id
1222  * LAG identifier. The lag_id is the index into the LAG descriptor table.
1223  * Access: Index
1224  */
1225 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1226
1227 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1228 {
1229         MLXSW_REG_ZERO(sldr, payload);
1230         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1231         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1232 }
1233
1234 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1235 {
1236         MLXSW_REG_ZERO(sldr, payload);
1237         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1238         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1239 }
1240
1241 /* reg_sldr_num_ports
1242  * The number of member ports of the LAG.
1243  * Reserved for Create / Destroy operations
1244  * For Add / Remove operations - indicates the number of ports in the list.
1245  * Access: RW
1246  */
1247 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1248
1249 /* reg_sldr_system_port
1250  * System port.
1251  * Access: RW
1252  */
1253 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1254
1255 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1256                                                     u8 local_port)
1257 {
1258         MLXSW_REG_ZERO(sldr, payload);
1259         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1260         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1261         mlxsw_reg_sldr_num_ports_set(payload, 1);
1262         mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1263 }
1264
1265 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1266                                                        u8 local_port)
1267 {
1268         MLXSW_REG_ZERO(sldr, payload);
1269         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1270         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1271         mlxsw_reg_sldr_num_ports_set(payload, 1);
1272         mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1273 }
1274
1275 /* SLCR - Switch LAG Configuration 2 Register
1276  * -------------------------------------------
1277  * The Switch LAG Configuration register is used for configuring the
1278  * LAG properties of the switch.
1279  */
1280 #define MLXSW_REG_SLCR_ID 0x2015
1281 #define MLXSW_REG_SLCR_LEN 0x10
1282
1283 static const struct mlxsw_reg_info mlxsw_reg_slcr = {
1284         .id = MLXSW_REG_SLCR_ID,
1285         .len = MLXSW_REG_SLCR_LEN,
1286 };
1287
1288 enum mlxsw_reg_slcr_pp {
1289         /* Global Configuration (for all ports) */
1290         MLXSW_REG_SLCR_PP_GLOBAL,
1291         /* Per port configuration, based on local_port field */
1292         MLXSW_REG_SLCR_PP_PER_PORT,
1293 };
1294
1295 /* reg_slcr_pp
1296  * Per Port Configuration
1297  * Note: Reading at Global mode results in reading port 1 configuration.
1298  * Access: Index
1299  */
1300 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1301
1302 /* reg_slcr_local_port
1303  * Local port number
1304  * Supported from CPU port
1305  * Not supported from router port
1306  * Reserved when pp = Global Configuration
1307  * Access: Index
1308  */
1309 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1310
1311 enum mlxsw_reg_slcr_type {
1312         MLXSW_REG_SLCR_TYPE_CRC, /* default */
1313         MLXSW_REG_SLCR_TYPE_XOR,
1314         MLXSW_REG_SLCR_TYPE_RANDOM,
1315 };
1316
1317 /* reg_slcr_type
1318  * Hash type
1319  * Access: RW
1320  */
1321 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1322
1323 /* Ingress port */
1324 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT         BIT(0)
1325 /* SMAC - for IPv4 and IPv6 packets */
1326 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP         BIT(1)
1327 /* SMAC - for non-IP packets */
1328 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP      BIT(2)
1329 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1330         (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1331          MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1332 /* DMAC - for IPv4 and IPv6 packets */
1333 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP         BIT(3)
1334 /* DMAC - for non-IP packets */
1335 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP      BIT(4)
1336 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1337         (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1338          MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1339 /* Ethertype - for IPv4 and IPv6 packets */
1340 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP    BIT(5)
1341 /* Ethertype - for non-IP packets */
1342 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1343 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1344         (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1345          MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1346 /* VLAN ID - for IPv4 and IPv6 packets */
1347 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP       BIT(7)
1348 /* VLAN ID - for non-IP packets */
1349 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP    BIT(8)
1350 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1351         (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1352          MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1353 /* Source IP address (can be IPv4 or IPv6) */
1354 #define MLXSW_REG_SLCR_LAG_HASH_SIP             BIT(9)
1355 /* Destination IP address (can be IPv4 or IPv6) */
1356 #define MLXSW_REG_SLCR_LAG_HASH_DIP             BIT(10)
1357 /* TCP/UDP source port */
1358 #define MLXSW_REG_SLCR_LAG_HASH_SPORT           BIT(11)
1359 /* TCP/UDP destination port*/
1360 #define MLXSW_REG_SLCR_LAG_HASH_DPORT           BIT(12)
1361 /* IPv4 Protocol/IPv6 Next Header */
1362 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO         BIT(13)
1363 /* IPv6 Flow label */
1364 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL       BIT(14)
1365 /* SID - FCoE source ID */
1366 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID        BIT(15)
1367 /* DID - FCoE destination ID */
1368 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID        BIT(16)
1369 /* OXID - FCoE originator exchange ID */
1370 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID       BIT(17)
1371 /* Destination QP number - for RoCE packets */
1372 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP        BIT(19)
1373
1374 /* reg_slcr_lag_hash
1375  * LAG hashing configuration. This is a bitmask, in which each set
1376  * bit includes the corresponding item in the LAG hash calculation.
1377  * The default lag_hash contains SMAC, DMAC, VLANID and
1378  * Ethertype (for all packet types).
1379  * Access: RW
1380  */
1381 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1382
1383 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1384 {
1385         MLXSW_REG_ZERO(slcr, payload);
1386         mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1387         mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR);
1388         mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1389 }
1390
1391 /* SLCOR - Switch LAG Collector Register
1392  * -------------------------------------
1393  * The Switch LAG Collector register controls the Local Port membership
1394  * in a LAG and enablement of the collector.
1395  */
1396 #define MLXSW_REG_SLCOR_ID 0x2016
1397 #define MLXSW_REG_SLCOR_LEN 0x10
1398
1399 static const struct mlxsw_reg_info mlxsw_reg_slcor = {
1400         .id = MLXSW_REG_SLCOR_ID,
1401         .len = MLXSW_REG_SLCOR_LEN,
1402 };
1403
1404 enum mlxsw_reg_slcor_col {
1405         /* Port is added with collector disabled */
1406         MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1407         MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1408         MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1409         MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1410 };
1411
1412 /* reg_slcor_col
1413  * Collector configuration
1414  * Access: RW
1415  */
1416 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1417
1418 /* reg_slcor_local_port
1419  * Local port number
1420  * Not supported for CPU port
1421  * Access: Index
1422  */
1423 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1424
1425 /* reg_slcor_lag_id
1426  * LAG Identifier. Index into the LAG descriptor table.
1427  * Access: Index
1428  */
1429 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1430
1431 /* reg_slcor_port_index
1432  * Port index in the LAG list. Only valid on Add Port to LAG col.
1433  * Valid range is from 0 to cap_max_lag_members-1
1434  * Access: RW
1435  */
1436 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1437
1438 static inline void mlxsw_reg_slcor_pack(char *payload,
1439                                         u8 local_port, u16 lag_id,
1440                                         enum mlxsw_reg_slcor_col col)
1441 {
1442         MLXSW_REG_ZERO(slcor, payload);
1443         mlxsw_reg_slcor_col_set(payload, col);
1444         mlxsw_reg_slcor_local_port_set(payload, local_port);
1445         mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1446 }
1447
1448 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1449                                                  u8 local_port, u16 lag_id,
1450                                                  u8 port_index)
1451 {
1452         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1453                              MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1454         mlxsw_reg_slcor_port_index_set(payload, port_index);
1455 }
1456
1457 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1458                                                     u8 local_port, u16 lag_id)
1459 {
1460         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1461                              MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1462 }
1463
1464 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1465                                                    u8 local_port, u16 lag_id)
1466 {
1467         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1468                              MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1469 }
1470
1471 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1472                                                     u8 local_port, u16 lag_id)
1473 {
1474         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1475                              MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1476 }
1477
1478 /* SPMLR - Switch Port MAC Learning Register
1479  * -----------------------------------------
1480  * Controls the Switch MAC learning policy per port.
1481  */
1482 #define MLXSW_REG_SPMLR_ID 0x2018
1483 #define MLXSW_REG_SPMLR_LEN 0x8
1484
1485 static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
1486         .id = MLXSW_REG_SPMLR_ID,
1487         .len = MLXSW_REG_SPMLR_LEN,
1488 };
1489
1490 /* reg_spmlr_local_port
1491  * Local port number.
1492  * Access: Index
1493  */
1494 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1495
1496 /* reg_spmlr_sub_port
1497  * Virtual port within the physical port.
1498  * Should be set to 0 when virtual ports are not enabled on the port.
1499  * Access: Index
1500  */
1501 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1502
1503 enum mlxsw_reg_spmlr_learn_mode {
1504         MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1505         MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1506         MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1507 };
1508
1509 /* reg_spmlr_learn_mode
1510  * Learning mode on the port.
1511  * 0 - Learning disabled.
1512  * 2 - Learning enabled.
1513  * 3 - Security mode.
1514  *
1515  * In security mode the switch does not learn MACs on the port, but uses the
1516  * SMAC to see if it exists on another ingress port. If so, the packet is
1517  * classified as a bad packet and is discarded unless the software registers
1518  * to receive port security error packets usign HPKT.
1519  */
1520 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1521
1522 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1523                                         enum mlxsw_reg_spmlr_learn_mode mode)
1524 {
1525         MLXSW_REG_ZERO(spmlr, payload);
1526         mlxsw_reg_spmlr_local_port_set(payload, local_port);
1527         mlxsw_reg_spmlr_sub_port_set(payload, 0);
1528         mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1529 }
1530
1531 /* SVFA - Switch VID to FID Allocation Register
1532  * --------------------------------------------
1533  * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1534  * virtualized ports.
1535  */
1536 #define MLXSW_REG_SVFA_ID 0x201C
1537 #define MLXSW_REG_SVFA_LEN 0x10
1538
1539 static const struct mlxsw_reg_info mlxsw_reg_svfa = {
1540         .id = MLXSW_REG_SVFA_ID,
1541         .len = MLXSW_REG_SVFA_LEN,
1542 };
1543
1544 /* reg_svfa_swid
1545  * Switch partition ID.
1546  * Access: Index
1547  */
1548 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1549
1550 /* reg_svfa_local_port
1551  * Local port number.
1552  * Access: Index
1553  *
1554  * Note: Reserved for 802.1Q FIDs.
1555  */
1556 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1557
1558 enum mlxsw_reg_svfa_mt {
1559         MLXSW_REG_SVFA_MT_VID_TO_FID,
1560         MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1561 };
1562
1563 /* reg_svfa_mapping_table
1564  * Mapping table:
1565  * 0 - VID to FID
1566  * 1 - {Port, VID} to FID
1567  * Access: Index
1568  *
1569  * Note: Reserved for SwitchX-2.
1570  */
1571 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1572
1573 /* reg_svfa_v
1574  * Valid.
1575  * Valid if set.
1576  * Access: RW
1577  *
1578  * Note: Reserved for SwitchX-2.
1579  */
1580 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1581
1582 /* reg_svfa_fid
1583  * Filtering ID.
1584  * Access: RW
1585  */
1586 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1587
1588 /* reg_svfa_vid
1589  * VLAN ID.
1590  * Access: Index
1591  */
1592 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1593
1594 /* reg_svfa_counter_set_type
1595  * Counter set type for flow counters.
1596  * Access: RW
1597  *
1598  * Note: Reserved for SwitchX-2.
1599  */
1600 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1601
1602 /* reg_svfa_counter_index
1603  * Counter index for flow counters.
1604  * Access: RW
1605  *
1606  * Note: Reserved for SwitchX-2.
1607  */
1608 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1609
1610 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1611                                        enum mlxsw_reg_svfa_mt mt, bool valid,
1612                                        u16 fid, u16 vid)
1613 {
1614         MLXSW_REG_ZERO(svfa, payload);
1615         local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1616         mlxsw_reg_svfa_swid_set(payload, 0);
1617         mlxsw_reg_svfa_local_port_set(payload, local_port);
1618         mlxsw_reg_svfa_mapping_table_set(payload, mt);
1619         mlxsw_reg_svfa_v_set(payload, valid);
1620         mlxsw_reg_svfa_fid_set(payload, fid);
1621         mlxsw_reg_svfa_vid_set(payload, vid);
1622 }
1623
1624 /* SVPE - Switch Virtual-Port Enabling Register
1625  * --------------------------------------------
1626  * Enables port virtualization.
1627  */
1628 #define MLXSW_REG_SVPE_ID 0x201E
1629 #define MLXSW_REG_SVPE_LEN 0x4
1630
1631 static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1632         .id = MLXSW_REG_SVPE_ID,
1633         .len = MLXSW_REG_SVPE_LEN,
1634 };
1635
1636 /* reg_svpe_local_port
1637  * Local port number
1638  * Access: Index
1639  *
1640  * Note: CPU port is not supported (uses VLAN mode only).
1641  */
1642 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1643
1644 /* reg_svpe_vp_en
1645  * Virtual port enable.
1646  * 0 - Disable, VLAN mode (VID to FID).
1647  * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1648  * Access: RW
1649  */
1650 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1651
1652 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1653                                        bool enable)
1654 {
1655         MLXSW_REG_ZERO(svpe, payload);
1656         mlxsw_reg_svpe_local_port_set(payload, local_port);
1657         mlxsw_reg_svpe_vp_en_set(payload, enable);
1658 }
1659
1660 /* SFMR - Switch FID Management Register
1661  * -------------------------------------
1662  * Creates and configures FIDs.
1663  */
1664 #define MLXSW_REG_SFMR_ID 0x201F
1665 #define MLXSW_REG_SFMR_LEN 0x18
1666
1667 static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1668         .id = MLXSW_REG_SFMR_ID,
1669         .len = MLXSW_REG_SFMR_LEN,
1670 };
1671
1672 enum mlxsw_reg_sfmr_op {
1673         MLXSW_REG_SFMR_OP_CREATE_FID,
1674         MLXSW_REG_SFMR_OP_DESTROY_FID,
1675 };
1676
1677 /* reg_sfmr_op
1678  * Operation.
1679  * 0 - Create or edit FID.
1680  * 1 - Destroy FID.
1681  * Access: WO
1682  */
1683 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1684
1685 /* reg_sfmr_fid
1686  * Filtering ID.
1687  * Access: Index
1688  */
1689 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1690
1691 /* reg_sfmr_fid_offset
1692  * FID offset.
1693  * Used to point into the flooding table selected by SFGC register if
1694  * the table is of type FID-Offset. Otherwise, this field is reserved.
1695  * Access: RW
1696  */
1697 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1698
1699 /* reg_sfmr_vtfp
1700  * Valid Tunnel Flood Pointer.
1701  * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1702  * Access: RW
1703  *
1704  * Note: Reserved for 802.1Q FIDs.
1705  */
1706 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1707
1708 /* reg_sfmr_nve_tunnel_flood_ptr
1709  * Underlay Flooding and BC Pointer.
1710  * Used as a pointer to the first entry of the group based link lists of
1711  * flooding or BC entries (for NVE tunnels).
1712  * Access: RW
1713  */
1714 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1715
1716 /* reg_sfmr_vv
1717  * VNI Valid.
1718  * If not set, then vni is reserved.
1719  * Access: RW
1720  *
1721  * Note: Reserved for 802.1Q FIDs.
1722  */
1723 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1724
1725 /* reg_sfmr_vni
1726  * Virtual Network Identifier.
1727  * Access: RW
1728  *
1729  * Note: A given VNI can only be assigned to one FID.
1730  */
1731 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1732
1733 static inline void mlxsw_reg_sfmr_pack(char *payload,
1734                                        enum mlxsw_reg_sfmr_op op, u16 fid,
1735                                        u16 fid_offset)
1736 {
1737         MLXSW_REG_ZERO(sfmr, payload);
1738         mlxsw_reg_sfmr_op_set(payload, op);
1739         mlxsw_reg_sfmr_fid_set(payload, fid);
1740         mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1741         mlxsw_reg_sfmr_vtfp_set(payload, false);
1742         mlxsw_reg_sfmr_vv_set(payload, false);
1743 }
1744
1745 /* SPVMLR - Switch Port VLAN MAC Learning Register
1746  * -----------------------------------------------
1747  * Controls the switch MAC learning policy per {Port, VID}.
1748  */
1749 #define MLXSW_REG_SPVMLR_ID 0x2020
1750 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1751 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1752 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1753 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1754                               MLXSW_REG_SPVMLR_REC_LEN * \
1755                               MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1756
1757 static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1758         .id = MLXSW_REG_SPVMLR_ID,
1759         .len = MLXSW_REG_SPVMLR_LEN,
1760 };
1761
1762 /* reg_spvmlr_local_port
1763  * Local ingress port.
1764  * Access: Index
1765  *
1766  * Note: CPU port is not supported.
1767  */
1768 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1769
1770 /* reg_spvmlr_num_rec
1771  * Number of records to update.
1772  * Access: OP
1773  */
1774 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1775
1776 /* reg_spvmlr_rec_learn_enable
1777  * 0 - Disable learning for {Port, VID}.
1778  * 1 - Enable learning for {Port, VID}.
1779  * Access: RW
1780  */
1781 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1782                      31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1783
1784 /* reg_spvmlr_rec_vid
1785  * VLAN ID to be added/removed from port or for querying.
1786  * Access: Index
1787  */
1788 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1789                      MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1790
1791 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1792                                          u16 vid_begin, u16 vid_end,
1793                                          bool learn_enable)
1794 {
1795         int num_rec = vid_end - vid_begin + 1;
1796         int i;
1797
1798         WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1799
1800         MLXSW_REG_ZERO(spvmlr, payload);
1801         mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1802         mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1803
1804         for (i = 0; i < num_rec; i++) {
1805                 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1806                 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1807         }
1808 }
1809
1810 /* QTCT - QoS Switch Traffic Class Table
1811  * -------------------------------------
1812  * Configures the mapping between the packet switch priority and the
1813  * traffic class on the transmit port.
1814  */
1815 #define MLXSW_REG_QTCT_ID 0x400A
1816 #define MLXSW_REG_QTCT_LEN 0x08
1817
1818 static const struct mlxsw_reg_info mlxsw_reg_qtct = {
1819         .id = MLXSW_REG_QTCT_ID,
1820         .len = MLXSW_REG_QTCT_LEN,
1821 };
1822
1823 /* reg_qtct_local_port
1824  * Local port number.
1825  * Access: Index
1826  *
1827  * Note: CPU port is not supported.
1828  */
1829 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
1830
1831 /* reg_qtct_sub_port
1832  * Virtual port within the physical port.
1833  * Should be set to 0 when virtual ports are not enabled on the port.
1834  * Access: Index
1835  */
1836 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
1837
1838 /* reg_qtct_switch_prio
1839  * Switch priority.
1840  * Access: Index
1841  */
1842 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
1843
1844 /* reg_qtct_tclass
1845  * Traffic class.
1846  * Default values:
1847  * switch_prio 0 : tclass 1
1848  * switch_prio 1 : tclass 0
1849  * switch_prio i : tclass i, for i > 1
1850  * Access: RW
1851  */
1852 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
1853
1854 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
1855                                        u8 switch_prio, u8 tclass)
1856 {
1857         MLXSW_REG_ZERO(qtct, payload);
1858         mlxsw_reg_qtct_local_port_set(payload, local_port);
1859         mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
1860         mlxsw_reg_qtct_tclass_set(payload, tclass);
1861 }
1862
1863 /* QEEC - QoS ETS Element Configuration Register
1864  * ---------------------------------------------
1865  * Configures the ETS elements.
1866  */
1867 #define MLXSW_REG_QEEC_ID 0x400D
1868 #define MLXSW_REG_QEEC_LEN 0x1C
1869
1870 static const struct mlxsw_reg_info mlxsw_reg_qeec = {
1871         .id = MLXSW_REG_QEEC_ID,
1872         .len = MLXSW_REG_QEEC_LEN,
1873 };
1874
1875 /* reg_qeec_local_port
1876  * Local port number.
1877  * Access: Index
1878  *
1879  * Note: CPU port is supported.
1880  */
1881 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
1882
1883 enum mlxsw_reg_qeec_hr {
1884         MLXSW_REG_QEEC_HIERARCY_PORT,
1885         MLXSW_REG_QEEC_HIERARCY_GROUP,
1886         MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1887         MLXSW_REG_QEEC_HIERARCY_TC,
1888 };
1889
1890 /* reg_qeec_element_hierarchy
1891  * 0 - Port
1892  * 1 - Group
1893  * 2 - Subgroup
1894  * 3 - Traffic Class
1895  * Access: Index
1896  */
1897 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
1898
1899 /* reg_qeec_element_index
1900  * The index of the element in the hierarchy.
1901  * Access: Index
1902  */
1903 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
1904
1905 /* reg_qeec_next_element_index
1906  * The index of the next (lower) element in the hierarchy.
1907  * Access: RW
1908  *
1909  * Note: Reserved for element_hierarchy 0.
1910  */
1911 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
1912
1913 enum {
1914         MLXSW_REG_QEEC_BYTES_MODE,
1915         MLXSW_REG_QEEC_PACKETS_MODE,
1916 };
1917
1918 /* reg_qeec_pb
1919  * Packets or bytes mode.
1920  * 0 - Bytes mode
1921  * 1 - Packets mode
1922  * Access: RW
1923  *
1924  * Note: Used for max shaper configuration. For Spectrum, packets mode
1925  * is supported only for traffic classes of CPU port.
1926  */
1927 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
1928
1929 /* reg_qeec_mase
1930  * Max shaper configuration enable. Enables configuration of the max
1931  * shaper on this ETS element.
1932  * 0 - Disable
1933  * 1 - Enable
1934  * Access: RW
1935  */
1936 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
1937
1938 /* A large max rate will disable the max shaper. */
1939 #define MLXSW_REG_QEEC_MAS_DIS  200000000       /* Kbps */
1940
1941 /* reg_qeec_max_shaper_rate
1942  * Max shaper information rate.
1943  * For CPU port, can only be configured for port hierarchy.
1944  * When in bytes mode, value is specified in units of 1000bps.
1945  * Access: RW
1946  */
1947 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
1948
1949 /* reg_qeec_de
1950  * DWRR configuration enable. Enables configuration of the dwrr and
1951  * dwrr_weight.
1952  * 0 - Disable
1953  * 1 - Enable
1954  * Access: RW
1955  */
1956 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
1957
1958 /* reg_qeec_dwrr
1959  * Transmission selection algorithm to use on the link going down from
1960  * the ETS element.
1961  * 0 - Strict priority
1962  * 1 - DWRR
1963  * Access: RW
1964  */
1965 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
1966
1967 /* reg_qeec_dwrr_weight
1968  * DWRR weight on the link going down from the ETS element. The
1969  * percentage of bandwidth guaranteed to an ETS element within
1970  * its hierarchy. The sum of all weights across all ETS elements
1971  * within one hierarchy should be equal to 100. Reserved when
1972  * transmission selection algorithm is strict priority.
1973  * Access: RW
1974  */
1975 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
1976
1977 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
1978                                        enum mlxsw_reg_qeec_hr hr, u8 index,
1979                                        u8 next_index)
1980 {
1981         MLXSW_REG_ZERO(qeec, payload);
1982         mlxsw_reg_qeec_local_port_set(payload, local_port);
1983         mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
1984         mlxsw_reg_qeec_element_index_set(payload, index);
1985         mlxsw_reg_qeec_next_element_index_set(payload, next_index);
1986 }
1987
1988 /* PMLP - Ports Module to Local Port Register
1989  * ------------------------------------------
1990  * Configures the assignment of modules to local ports.
1991  */
1992 #define MLXSW_REG_PMLP_ID 0x5002
1993 #define MLXSW_REG_PMLP_LEN 0x40
1994
1995 static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
1996         .id = MLXSW_REG_PMLP_ID,
1997         .len = MLXSW_REG_PMLP_LEN,
1998 };
1999
2000 /* reg_pmlp_rxtx
2001  * 0 - Tx value is used for both Tx and Rx.
2002  * 1 - Rx value is taken from a separte field.
2003  * Access: RW
2004  */
2005 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
2006
2007 /* reg_pmlp_local_port
2008  * Local port number.
2009  * Access: Index
2010  */
2011 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
2012
2013 /* reg_pmlp_width
2014  * 0 - Unmap local port.
2015  * 1 - Lane 0 is used.
2016  * 2 - Lanes 0 and 1 are used.
2017  * 4 - Lanes 0, 1, 2 and 3 are used.
2018  * Access: RW
2019  */
2020 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
2021
2022 /* reg_pmlp_module
2023  * Module number.
2024  * Access: RW
2025  */
2026 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
2027
2028 /* reg_pmlp_tx_lane
2029  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
2030  * Access: RW
2031  */
2032 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
2033
2034 /* reg_pmlp_rx_lane
2035  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
2036  * equal to Tx lane.
2037  * Access: RW
2038  */
2039 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
2040
2041 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
2042 {
2043         MLXSW_REG_ZERO(pmlp, payload);
2044         mlxsw_reg_pmlp_local_port_set(payload, local_port);
2045 }
2046
2047 /* PMTU - Port MTU Register
2048  * ------------------------
2049  * Configures and reports the port MTU.
2050  */
2051 #define MLXSW_REG_PMTU_ID 0x5003
2052 #define MLXSW_REG_PMTU_LEN 0x10
2053
2054 static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
2055         .id = MLXSW_REG_PMTU_ID,
2056         .len = MLXSW_REG_PMTU_LEN,
2057 };
2058
2059 /* reg_pmtu_local_port
2060  * Local port number.
2061  * Access: Index
2062  */
2063 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
2064
2065 /* reg_pmtu_max_mtu
2066  * Maximum MTU.
2067  * When port type (e.g. Ethernet) is configured, the relevant MTU is
2068  * reported, otherwise the minimum between the max_mtu of the different
2069  * types is reported.
2070  * Access: RO
2071  */
2072 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
2073
2074 /* reg_pmtu_admin_mtu
2075  * MTU value to set port to. Must be smaller or equal to max_mtu.
2076  * Note: If port type is Infiniband, then port must be disabled, when its
2077  * MTU is set.
2078  * Access: RW
2079  */
2080 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
2081
2082 /* reg_pmtu_oper_mtu
2083  * The actual MTU configured on the port. Packets exceeding this size
2084  * will be dropped.
2085  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
2086  * oper_mtu might be smaller than admin_mtu.
2087  * Access: RO
2088  */
2089 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
2090
2091 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
2092                                        u16 new_mtu)
2093 {
2094         MLXSW_REG_ZERO(pmtu, payload);
2095         mlxsw_reg_pmtu_local_port_set(payload, local_port);
2096         mlxsw_reg_pmtu_max_mtu_set(payload, 0);
2097         mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
2098         mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
2099 }
2100
2101 /* PTYS - Port Type and Speed Register
2102  * -----------------------------------
2103  * Configures and reports the port speed type.
2104  *
2105  * Note: When set while the link is up, the changes will not take effect
2106  * until the port transitions from down to up state.
2107  */
2108 #define MLXSW_REG_PTYS_ID 0x5004
2109 #define MLXSW_REG_PTYS_LEN 0x40
2110
2111 static const struct mlxsw_reg_info mlxsw_reg_ptys = {
2112         .id = MLXSW_REG_PTYS_ID,
2113         .len = MLXSW_REG_PTYS_LEN,
2114 };
2115
2116 /* reg_ptys_local_port
2117  * Local port number.
2118  * Access: Index
2119  */
2120 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
2121
2122 #define MLXSW_REG_PTYS_PROTO_MASK_ETH   BIT(2)
2123
2124 /* reg_ptys_proto_mask
2125  * Protocol mask. Indicates which protocol is used.
2126  * 0 - Infiniband.
2127  * 1 - Fibre Channel.
2128  * 2 - Ethernet.
2129  * Access: Index
2130  */
2131 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
2132
2133 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII                  BIT(0)
2134 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX            BIT(1)
2135 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4            BIT(2)
2136 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4            BIT(3)
2137 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR             BIT(4)
2138 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2            BIT(5)
2139 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4            BIT(6)
2140 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4            BIT(7)
2141 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4             BIT(8)
2142 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR             BIT(12)
2143 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR             BIT(13)
2144 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR          BIT(14)
2145 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4            BIT(15)
2146 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4        BIT(16)
2147 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4            BIT(19)
2148 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4           BIT(20)
2149 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4           BIT(21)
2150 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4           BIT(22)
2151 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4       BIT(23)
2152 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX             BIT(24)
2153 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T              BIT(25)
2154 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T              BIT(26)
2155 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR             BIT(27)
2156 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR             BIT(28)
2157 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR             BIT(29)
2158 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2            BIT(30)
2159 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2            BIT(31)
2160
2161 /* reg_ptys_eth_proto_cap
2162  * Ethernet port supported speeds and protocols.
2163  * Access: RO
2164  */
2165 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
2166
2167 /* reg_ptys_eth_proto_admin
2168  * Speed and protocol to set port to.
2169  * Access: RW
2170  */
2171 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
2172
2173 /* reg_ptys_eth_proto_oper
2174  * The current speed and protocol configured for the port.
2175  * Access: RO
2176  */
2177 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
2178
2179 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
2180                                        u32 proto_admin)
2181 {
2182         MLXSW_REG_ZERO(ptys, payload);
2183         mlxsw_reg_ptys_local_port_set(payload, local_port);
2184         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
2185         mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
2186 }
2187
2188 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
2189                                          u32 *p_eth_proto_adm,
2190                                          u32 *p_eth_proto_oper)
2191 {
2192         if (p_eth_proto_cap)
2193                 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
2194         if (p_eth_proto_adm)
2195                 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
2196         if (p_eth_proto_oper)
2197                 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
2198 }
2199
2200 /* PPAD - Port Physical Address Register
2201  * -------------------------------------
2202  * The PPAD register configures the per port physical MAC address.
2203  */
2204 #define MLXSW_REG_PPAD_ID 0x5005
2205 #define MLXSW_REG_PPAD_LEN 0x10
2206
2207 static const struct mlxsw_reg_info mlxsw_reg_ppad = {
2208         .id = MLXSW_REG_PPAD_ID,
2209         .len = MLXSW_REG_PPAD_LEN,
2210 };
2211
2212 /* reg_ppad_single_base_mac
2213  * 0: base_mac, local port should be 0 and mac[7:0] is
2214  * reserved. HW will set incremental
2215  * 1: single_mac - mac of the local_port
2216  * Access: RW
2217  */
2218 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
2219
2220 /* reg_ppad_local_port
2221  * port number, if single_base_mac = 0 then local_port is reserved
2222  * Access: RW
2223  */
2224 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
2225
2226 /* reg_ppad_mac
2227  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
2228  * If single_base_mac = 1 - the per port MAC address
2229  * Access: RW
2230  */
2231 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
2232
2233 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
2234                                        u8 local_port)
2235 {
2236         MLXSW_REG_ZERO(ppad, payload);
2237         mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
2238         mlxsw_reg_ppad_local_port_set(payload, local_port);
2239 }
2240
2241 /* PAOS - Ports Administrative and Operational Status Register
2242  * -----------------------------------------------------------
2243  * Configures and retrieves per port administrative and operational status.
2244  */
2245 #define MLXSW_REG_PAOS_ID 0x5006
2246 #define MLXSW_REG_PAOS_LEN 0x10
2247
2248 static const struct mlxsw_reg_info mlxsw_reg_paos = {
2249         .id = MLXSW_REG_PAOS_ID,
2250         .len = MLXSW_REG_PAOS_LEN,
2251 };
2252
2253 /* reg_paos_swid
2254  * Switch partition ID with which to associate the port.
2255  * Note: while external ports uses unique local port numbers (and thus swid is
2256  * redundant), router ports use the same local port number where swid is the
2257  * only indication for the relevant port.
2258  * Access: Index
2259  */
2260 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
2261
2262 /* reg_paos_local_port
2263  * Local port number.
2264  * Access: Index
2265  */
2266 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
2267
2268 /* reg_paos_admin_status
2269  * Port administrative state (the desired state of the port):
2270  * 1 - Up.
2271  * 2 - Down.
2272  * 3 - Up once. This means that in case of link failure, the port won't go
2273  *     into polling mode, but will wait to be re-enabled by software.
2274  * 4 - Disabled by system. Can only be set by hardware.
2275  * Access: RW
2276  */
2277 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
2278
2279 /* reg_paos_oper_status
2280  * Port operational state (the current state):
2281  * 1 - Up.
2282  * 2 - Down.
2283  * 3 - Down by port failure. This means that the device will not let the
2284  *     port up again until explicitly specified by software.
2285  * Access: RO
2286  */
2287 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
2288
2289 /* reg_paos_ase
2290  * Admin state update enabled.
2291  * Access: WO
2292  */
2293 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
2294
2295 /* reg_paos_ee
2296  * Event update enable. If this bit is set, event generation will be
2297  * updated based on the e field.
2298  * Access: WO
2299  */
2300 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
2301
2302 /* reg_paos_e
2303  * Event generation on operational state change:
2304  * 0 - Do not generate event.
2305  * 1 - Generate Event.
2306  * 2 - Generate Single Event.
2307  * Access: RW
2308  */
2309 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
2310
2311 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
2312                                        enum mlxsw_port_admin_status status)
2313 {
2314         MLXSW_REG_ZERO(paos, payload);
2315         mlxsw_reg_paos_swid_set(payload, 0);
2316         mlxsw_reg_paos_local_port_set(payload, local_port);
2317         mlxsw_reg_paos_admin_status_set(payload, status);
2318         mlxsw_reg_paos_oper_status_set(payload, 0);
2319         mlxsw_reg_paos_ase_set(payload, 1);
2320         mlxsw_reg_paos_ee_set(payload, 1);
2321         mlxsw_reg_paos_e_set(payload, 1);
2322 }
2323
2324 /* PFCC - Ports Flow Control Configuration Register
2325  * ------------------------------------------------
2326  * Configures and retrieves the per port flow control configuration.
2327  */
2328 #define MLXSW_REG_PFCC_ID 0x5007
2329 #define MLXSW_REG_PFCC_LEN 0x20
2330
2331 static const struct mlxsw_reg_info mlxsw_reg_pfcc = {
2332         .id = MLXSW_REG_PFCC_ID,
2333         .len = MLXSW_REG_PFCC_LEN,
2334 };
2335
2336 /* reg_pfcc_local_port
2337  * Local port number.
2338  * Access: Index
2339  */
2340 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
2341
2342 /* reg_pfcc_pnat
2343  * Port number access type. Determines the way local_port is interpreted:
2344  * 0 - Local port number.
2345  * 1 - IB / label port number.
2346  * Access: Index
2347  */
2348 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
2349
2350 /* reg_pfcc_shl_cap
2351  * Send to higher layers capabilities:
2352  * 0 - No capability of sending Pause and PFC frames to higher layers.
2353  * 1 - Device has capability of sending Pause and PFC frames to higher
2354  *     layers.
2355  * Access: RO
2356  */
2357 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
2358
2359 /* reg_pfcc_shl_opr
2360  * Send to higher layers operation:
2361  * 0 - Pause and PFC frames are handled by the port (default).
2362  * 1 - Pause and PFC frames are handled by the port and also sent to
2363  *     higher layers. Only valid if shl_cap = 1.
2364  * Access: RW
2365  */
2366 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
2367
2368 /* reg_pfcc_ppan
2369  * Pause policy auto negotiation.
2370  * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
2371  * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
2372  *     based on the auto-negotiation resolution.
2373  * Access: RW
2374  *
2375  * Note: The auto-negotiation advertisement is set according to pptx and
2376  * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
2377  */
2378 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
2379
2380 /* reg_pfcc_prio_mask_tx
2381  * Bit per priority indicating if Tx flow control policy should be
2382  * updated based on bit pfctx.
2383  * Access: WO
2384  */
2385 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
2386
2387 /* reg_pfcc_prio_mask_rx
2388  * Bit per priority indicating if Rx flow control policy should be
2389  * updated based on bit pfcrx.
2390  * Access: WO
2391  */
2392 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
2393
2394 /* reg_pfcc_pptx
2395  * Admin Pause policy on Tx.
2396  * 0 - Never generate Pause frames (default).
2397  * 1 - Generate Pause frames according to Rx buffer threshold.
2398  * Access: RW
2399  */
2400 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
2401
2402 /* reg_pfcc_aptx
2403  * Active (operational) Pause policy on Tx.
2404  * 0 - Never generate Pause frames.
2405  * 1 - Generate Pause frames according to Rx buffer threshold.
2406  * Access: RO
2407  */
2408 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
2409
2410 /* reg_pfcc_pfctx
2411  * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
2412  * 0 - Never generate priority Pause frames on the specified priority
2413  *     (default).
2414  * 1 - Generate priority Pause frames according to Rx buffer threshold on
2415  *     the specified priority.
2416  * Access: RW
2417  *
2418  * Note: pfctx and pptx must be mutually exclusive.
2419  */
2420 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
2421
2422 /* reg_pfcc_pprx
2423  * Admin Pause policy on Rx.
2424  * 0 - Ignore received Pause frames (default).
2425  * 1 - Respect received Pause frames.
2426  * Access: RW
2427  */
2428 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
2429
2430 /* reg_pfcc_aprx
2431  * Active (operational) Pause policy on Rx.
2432  * 0 - Ignore received Pause frames.
2433  * 1 - Respect received Pause frames.
2434  * Access: RO
2435  */
2436 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
2437
2438 /* reg_pfcc_pfcrx
2439  * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
2440  * 0 - Ignore incoming priority Pause frames on the specified priority
2441  *     (default).
2442  * 1 - Respect incoming priority Pause frames on the specified priority.
2443  * Access: RW
2444  */
2445 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
2446
2447 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
2448
2449 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
2450 {
2451         mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2452         mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2453         mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
2454         mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
2455 }
2456
2457 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
2458 {
2459         MLXSW_REG_ZERO(pfcc, payload);
2460         mlxsw_reg_pfcc_local_port_set(payload, local_port);
2461 }
2462
2463 /* PPCNT - Ports Performance Counters Register
2464  * -------------------------------------------
2465  * The PPCNT register retrieves per port performance counters.
2466  */
2467 #define MLXSW_REG_PPCNT_ID 0x5008
2468 #define MLXSW_REG_PPCNT_LEN 0x100
2469
2470 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
2471         .id = MLXSW_REG_PPCNT_ID,
2472         .len = MLXSW_REG_PPCNT_LEN,
2473 };
2474
2475 /* reg_ppcnt_swid
2476  * For HCA: must be always 0.
2477  * Switch partition ID to associate port with.
2478  * Switch partitions are numbered from 0 to 7 inclusively.
2479  * Switch partition 254 indicates stacking ports.
2480  * Switch partition 255 indicates all switch partitions.
2481  * Only valid on Set() operation with local_port=255.
2482  * Access: Index
2483  */
2484 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
2485
2486 /* reg_ppcnt_local_port
2487  * Local port number.
2488  * 255 indicates all ports on the device, and is only allowed
2489  * for Set() operation.
2490  * Access: Index
2491  */
2492 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
2493
2494 /* reg_ppcnt_pnat
2495  * Port number access type:
2496  * 0 - Local port number
2497  * 1 - IB port number
2498  * Access: Index
2499  */
2500 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
2501
2502 enum mlxsw_reg_ppcnt_grp {
2503         MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
2504         MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
2505 };
2506
2507 /* reg_ppcnt_grp
2508  * Performance counter group.
2509  * Group 63 indicates all groups. Only valid on Set() operation with
2510  * clr bit set.
2511  * 0x0: IEEE 802.3 Counters
2512  * 0x1: RFC 2863 Counters
2513  * 0x2: RFC 2819 Counters
2514  * 0x3: RFC 3635 Counters
2515  * 0x5: Ethernet Extended Counters
2516  * 0x8: Link Level Retransmission Counters
2517  * 0x10: Per Priority Counters
2518  * 0x11: Per Traffic Class Counters
2519  * 0x12: Physical Layer Counters
2520  * Access: Index
2521  */
2522 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
2523
2524 /* reg_ppcnt_clr
2525  * Clear counters. Setting the clr bit will reset the counter value
2526  * for all counters in the counter group. This bit can be set
2527  * for both Set() and Get() operation.
2528  * Access: OP
2529  */
2530 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
2531
2532 /* reg_ppcnt_prio_tc
2533  * Priority for counter set that support per priority, valid values: 0-7.
2534  * Traffic class for counter set that support per traffic class,
2535  * valid values: 0- cap_max_tclass-1 .
2536  * For HCA: cap_max_tclass is always 8.
2537  * Otherwise must be 0.
2538  * Access: Index
2539  */
2540 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
2541
2542 /* Ethernet IEEE 802.3 Counter Group */
2543
2544 /* reg_ppcnt_a_frames_transmitted_ok
2545  * Access: RO
2546  */
2547 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
2548              0x08 + 0x00, 0, 64);
2549
2550 /* reg_ppcnt_a_frames_received_ok
2551  * Access: RO
2552  */
2553 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
2554              0x08 + 0x08, 0, 64);
2555
2556 /* reg_ppcnt_a_frame_check_sequence_errors
2557  * Access: RO
2558  */
2559 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
2560              0x08 + 0x10, 0, 64);
2561
2562 /* reg_ppcnt_a_alignment_errors
2563  * Access: RO
2564  */
2565 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
2566              0x08 + 0x18, 0, 64);
2567
2568 /* reg_ppcnt_a_octets_transmitted_ok
2569  * Access: RO
2570  */
2571 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
2572              0x08 + 0x20, 0, 64);
2573
2574 /* reg_ppcnt_a_octets_received_ok
2575  * Access: RO
2576  */
2577 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
2578              0x08 + 0x28, 0, 64);
2579
2580 /* reg_ppcnt_a_multicast_frames_xmitted_ok
2581  * Access: RO
2582  */
2583 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
2584              0x08 + 0x30, 0, 64);
2585
2586 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
2587  * Access: RO
2588  */
2589 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
2590              0x08 + 0x38, 0, 64);
2591
2592 /* reg_ppcnt_a_multicast_frames_received_ok
2593  * Access: RO
2594  */
2595 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
2596              0x08 + 0x40, 0, 64);
2597
2598 /* reg_ppcnt_a_broadcast_frames_received_ok
2599  * Access: RO
2600  */
2601 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
2602              0x08 + 0x48, 0, 64);
2603
2604 /* reg_ppcnt_a_in_range_length_errors
2605  * Access: RO
2606  */
2607 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
2608              0x08 + 0x50, 0, 64);
2609
2610 /* reg_ppcnt_a_out_of_range_length_field
2611  * Access: RO
2612  */
2613 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
2614              0x08 + 0x58, 0, 64);
2615
2616 /* reg_ppcnt_a_frame_too_long_errors
2617  * Access: RO
2618  */
2619 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
2620              0x08 + 0x60, 0, 64);
2621
2622 /* reg_ppcnt_a_symbol_error_during_carrier
2623  * Access: RO
2624  */
2625 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
2626              0x08 + 0x68, 0, 64);
2627
2628 /* reg_ppcnt_a_mac_control_frames_transmitted
2629  * Access: RO
2630  */
2631 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
2632              0x08 + 0x70, 0, 64);
2633
2634 /* reg_ppcnt_a_mac_control_frames_received
2635  * Access: RO
2636  */
2637 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
2638              0x08 + 0x78, 0, 64);
2639
2640 /* reg_ppcnt_a_unsupported_opcodes_received
2641  * Access: RO
2642  */
2643 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
2644              0x08 + 0x80, 0, 64);
2645
2646 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
2647  * Access: RO
2648  */
2649 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
2650              0x08 + 0x88, 0, 64);
2651
2652 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
2653  * Access: RO
2654  */
2655 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
2656              0x08 + 0x90, 0, 64);
2657
2658 /* Ethernet Per Priority Group Counters */
2659
2660 /* reg_ppcnt_rx_octets
2661  * Access: RO
2662  */
2663 MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64);
2664
2665 /* reg_ppcnt_rx_frames
2666  * Access: RO
2667  */
2668 MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64);
2669
2670 /* reg_ppcnt_tx_octets
2671  * Access: RO
2672  */
2673 MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64);
2674
2675 /* reg_ppcnt_tx_frames
2676  * Access: RO
2677  */
2678 MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64);
2679
2680 /* reg_ppcnt_rx_pause
2681  * Access: RO
2682  */
2683 MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64);
2684
2685 /* reg_ppcnt_rx_pause_duration
2686  * Access: RO
2687  */
2688 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64);
2689
2690 /* reg_ppcnt_tx_pause
2691  * Access: RO
2692  */
2693 MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64);
2694
2695 /* reg_ppcnt_tx_pause_duration
2696  * Access: RO
2697  */
2698 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64);
2699
2700 /* reg_ppcnt_rx_pause_transition
2701  * Access: RO
2702  */
2703 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64);
2704
2705 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
2706                                         enum mlxsw_reg_ppcnt_grp grp,
2707                                         u8 prio_tc)
2708 {
2709         MLXSW_REG_ZERO(ppcnt, payload);
2710         mlxsw_reg_ppcnt_swid_set(payload, 0);
2711         mlxsw_reg_ppcnt_local_port_set(payload, local_port);
2712         mlxsw_reg_ppcnt_pnat_set(payload, 0);
2713         mlxsw_reg_ppcnt_grp_set(payload, grp);
2714         mlxsw_reg_ppcnt_clr_set(payload, 0);
2715         mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
2716 }
2717
2718 /* PPTB - Port Prio To Buffer Register
2719  * -----------------------------------
2720  * Configures the switch priority to buffer table.
2721  */
2722 #define MLXSW_REG_PPTB_ID 0x500B
2723 #define MLXSW_REG_PPTB_LEN 0x0C
2724
2725 static const struct mlxsw_reg_info mlxsw_reg_pptb = {
2726         .id = MLXSW_REG_PPTB_ID,
2727         .len = MLXSW_REG_PPTB_LEN,
2728 };
2729
2730 enum {
2731         MLXSW_REG_PPTB_MM_UM,
2732         MLXSW_REG_PPTB_MM_UNICAST,
2733         MLXSW_REG_PPTB_MM_MULTICAST,
2734 };
2735
2736 /* reg_pptb_mm
2737  * Mapping mode.
2738  * 0 - Map both unicast and multicast packets to the same buffer.
2739  * 1 - Map only unicast packets.
2740  * 2 - Map only multicast packets.
2741  * Access: Index
2742  *
2743  * Note: SwitchX-2 only supports the first option.
2744  */
2745 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
2746
2747 /* reg_pptb_local_port
2748  * Local port number.
2749  * Access: Index
2750  */
2751 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
2752
2753 /* reg_pptb_um
2754  * Enables the update of the untagged_buf field.
2755  * Access: RW
2756  */
2757 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
2758
2759 /* reg_pptb_pm
2760  * Enables the update of the prio_to_buff field.
2761  * Bit <i> is a flag for updating the mapping for switch priority <i>.
2762  * Access: RW
2763  */
2764 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
2765
2766 /* reg_pptb_prio_to_buff
2767  * Mapping of switch priority <i> to one of the allocated receive port
2768  * buffers.
2769  * Access: RW
2770  */
2771 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
2772
2773 /* reg_pptb_pm_msb
2774  * Enables the update of the prio_to_buff field.
2775  * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
2776  * Access: RW
2777  */
2778 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
2779
2780 /* reg_pptb_untagged_buff
2781  * Mapping of untagged frames to one of the allocated receive port buffers.
2782  * Access: RW
2783  *
2784  * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
2785  * Spectrum, as it maps untagged packets based on the default switch priority.
2786  */
2787 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
2788
2789 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
2790
2791 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
2792 {
2793         MLXSW_REG_ZERO(pptb, payload);
2794         mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
2795         mlxsw_reg_pptb_local_port_set(payload, local_port);
2796         mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2797 }
2798
2799 /* PBMC - Port Buffer Management Control Register
2800  * ----------------------------------------------
2801  * The PBMC register configures and retrieves the port packet buffer
2802  * allocation for different Prios, and the Pause threshold management.
2803  */
2804 #define MLXSW_REG_PBMC_ID 0x500C
2805 #define MLXSW_REG_PBMC_LEN 0x6C
2806
2807 static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
2808         .id = MLXSW_REG_PBMC_ID,
2809         .len = MLXSW_REG_PBMC_LEN,
2810 };
2811
2812 /* reg_pbmc_local_port
2813  * Local port number.
2814  * Access: Index
2815  */
2816 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
2817
2818 /* reg_pbmc_xoff_timer_value
2819  * When device generates a pause frame, it uses this value as the pause
2820  * timer (time for the peer port to pause in quota-512 bit time).
2821  * Access: RW
2822  */
2823 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
2824
2825 /* reg_pbmc_xoff_refresh
2826  * The time before a new pause frame should be sent to refresh the pause RW
2827  * state. Using the same units as xoff_timer_value above (in quota-512 bit
2828  * time).
2829  * Access: RW
2830  */
2831 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
2832
2833 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
2834
2835 /* reg_pbmc_buf_lossy
2836  * The field indicates if the buffer is lossy.
2837  * 0 - Lossless
2838  * 1 - Lossy
2839  * Access: RW
2840  */
2841 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
2842
2843 /* reg_pbmc_buf_epsb
2844  * Eligible for Port Shared buffer.
2845  * If epsb is set, packets assigned to buffer are allowed to insert the port
2846  * shared buffer.
2847  * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
2848  * Access: RW
2849  */
2850 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
2851
2852 /* reg_pbmc_buf_size
2853  * The part of the packet buffer array is allocated for the specific buffer.
2854  * Units are represented in cells.
2855  * Access: RW
2856  */
2857 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
2858
2859 /* reg_pbmc_buf_xoff_threshold
2860  * Once the amount of data in the buffer goes above this value, device
2861  * starts sending PFC frames for all priorities associated with the
2862  * buffer. Units are represented in cells. Reserved in case of lossy
2863  * buffer.
2864  * Access: RW
2865  *
2866  * Note: In Spectrum, reserved for buffer[9].
2867  */
2868 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
2869                      0x08, 0x04, false);
2870
2871 /* reg_pbmc_buf_xon_threshold
2872  * When the amount of data in the buffer goes below this value, device
2873  * stops sending PFC frames for the priorities associated with the
2874  * buffer. Units are represented in cells. Reserved in case of lossy
2875  * buffer.
2876  * Access: RW
2877  *
2878  * Note: In Spectrum, reserved for buffer[9].
2879  */
2880 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
2881                      0x08, 0x04, false);
2882
2883 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
2884                                        u16 xoff_timer_value, u16 xoff_refresh)
2885 {
2886         MLXSW_REG_ZERO(pbmc, payload);
2887         mlxsw_reg_pbmc_local_port_set(payload, local_port);
2888         mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
2889         mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
2890 }
2891
2892 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
2893                                                     int buf_index,
2894                                                     u16 size)
2895 {
2896         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
2897         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2898         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2899 }
2900
2901 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
2902                                                        int buf_index, u16 size,
2903                                                        u16 threshold)
2904 {
2905         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
2906         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2907         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2908         mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
2909         mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
2910 }
2911
2912 /* PSPA - Port Switch Partition Allocation
2913  * ---------------------------------------
2914  * Controls the association of a port with a switch partition and enables
2915  * configuring ports as stacking ports.
2916  */
2917 #define MLXSW_REG_PSPA_ID 0x500D
2918 #define MLXSW_REG_PSPA_LEN 0x8
2919
2920 static const struct mlxsw_reg_info mlxsw_reg_pspa = {
2921         .id = MLXSW_REG_PSPA_ID,
2922         .len = MLXSW_REG_PSPA_LEN,
2923 };
2924
2925 /* reg_pspa_swid
2926  * Switch partition ID.
2927  * Access: RW
2928  */
2929 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
2930
2931 /* reg_pspa_local_port
2932  * Local port number.
2933  * Access: Index
2934  */
2935 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
2936
2937 /* reg_pspa_sub_port
2938  * Virtual port within the local port. Set to 0 when virtual ports are
2939  * disabled on the local port.
2940  * Access: Index
2941  */
2942 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
2943
2944 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
2945 {
2946         MLXSW_REG_ZERO(pspa, payload);
2947         mlxsw_reg_pspa_swid_set(payload, swid);
2948         mlxsw_reg_pspa_local_port_set(payload, local_port);
2949         mlxsw_reg_pspa_sub_port_set(payload, 0);
2950 }
2951
2952 /* HTGT - Host Trap Group Table
2953  * ----------------------------
2954  * Configures the properties for forwarding to CPU.
2955  */
2956 #define MLXSW_REG_HTGT_ID 0x7002
2957 #define MLXSW_REG_HTGT_LEN 0x100
2958
2959 static const struct mlxsw_reg_info mlxsw_reg_htgt = {
2960         .id = MLXSW_REG_HTGT_ID,
2961         .len = MLXSW_REG_HTGT_LEN,
2962 };
2963
2964 /* reg_htgt_swid
2965  * Switch partition ID.
2966  * Access: Index
2967  */
2968 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
2969
2970 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0      /* For locally attached CPU */
2971
2972 /* reg_htgt_type
2973  * CPU path type.
2974  * Access: RW
2975  */
2976 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
2977
2978 enum mlxsw_reg_htgt_trap_group {
2979         MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
2980         MLXSW_REG_HTGT_TRAP_GROUP_RX,
2981         MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
2982 };
2983
2984 /* reg_htgt_trap_group
2985  * Trap group number. User defined number specifying which trap groups
2986  * should be forwarded to the CPU. The mapping between trap IDs and trap
2987  * groups is configured using HPKT register.
2988  * Access: Index
2989  */
2990 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
2991
2992 enum {
2993         MLXSW_REG_HTGT_POLICER_DISABLE,
2994         MLXSW_REG_HTGT_POLICER_ENABLE,
2995 };
2996
2997 /* reg_htgt_pide
2998  * Enable policer ID specified using 'pid' field.
2999  * Access: RW
3000  */
3001 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
3002
3003 /* reg_htgt_pid
3004  * Policer ID for the trap group.
3005  * Access: RW
3006  */
3007 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
3008
3009 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
3010
3011 /* reg_htgt_mirror_action
3012  * Mirror action to use.
3013  * 0 - Trap to CPU.
3014  * 1 - Trap to CPU and mirror to a mirroring agent.
3015  * 2 - Mirror to a mirroring agent and do not trap to CPU.
3016  * Access: RW
3017  *
3018  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
3019  */
3020 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
3021
3022 /* reg_htgt_mirroring_agent
3023  * Mirroring agent.
3024  * Access: RW
3025  */
3026 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
3027
3028 /* reg_htgt_priority
3029  * Trap group priority.
3030  * In case a packet matches multiple classification rules, the packet will
3031  * only be trapped once, based on the trap ID associated with the group (via
3032  * register HPKT) with the highest priority.
3033  * Supported values are 0-7, with 7 represnting the highest priority.
3034  * Access: RW
3035  *
3036  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
3037  * by the 'trap_group' field.
3038  */
3039 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
3040
3041 /* reg_htgt_local_path_cpu_tclass
3042  * CPU ingress traffic class for the trap group.
3043  * Access: RW
3044  */
3045 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
3046
3047 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD      0x15
3048 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX        0x14
3049 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL      0x13
3050
3051 /* reg_htgt_local_path_rdq
3052  * Receive descriptor queue (RDQ) to use for the trap group.
3053  * Access: RW
3054  */
3055 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
3056
3057 static inline void mlxsw_reg_htgt_pack(char *payload,
3058                                        enum mlxsw_reg_htgt_trap_group group)
3059 {
3060         u8 swid, rdq;
3061
3062         MLXSW_REG_ZERO(htgt, payload);
3063         switch (group) {
3064         case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
3065                 swid = MLXSW_PORT_SWID_ALL_SWIDS;
3066                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
3067                 break;
3068         case MLXSW_REG_HTGT_TRAP_GROUP_RX:
3069                 swid = 0;
3070                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
3071                 break;
3072         case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
3073                 swid = 0;
3074                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
3075                 break;
3076         }
3077         mlxsw_reg_htgt_swid_set(payload, swid);
3078         mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
3079         mlxsw_reg_htgt_trap_group_set(payload, group);
3080         mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
3081         mlxsw_reg_htgt_pid_set(payload, 0);
3082         mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
3083         mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
3084         mlxsw_reg_htgt_priority_set(payload, 0);
3085         mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
3086         mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
3087 }
3088
3089 /* HPKT - Host Packet Trap
3090  * -----------------------
3091  * Configures trap IDs inside trap groups.
3092  */
3093 #define MLXSW_REG_HPKT_ID 0x7003
3094 #define MLXSW_REG_HPKT_LEN 0x10
3095
3096 static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
3097         .id = MLXSW_REG_HPKT_ID,
3098         .len = MLXSW_REG_HPKT_LEN,
3099 };
3100
3101 enum {
3102         MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
3103         MLXSW_REG_HPKT_ACK_REQUIRED,
3104 };
3105
3106 /* reg_hpkt_ack
3107  * Require acknowledgements from the host for events.
3108  * If set, then the device will wait for the event it sent to be acknowledged
3109  * by the host. This option is only relevant for event trap IDs.
3110  * Access: RW
3111  *
3112  * Note: Currently not supported by firmware.
3113  */
3114 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
3115
3116 enum mlxsw_reg_hpkt_action {
3117         MLXSW_REG_HPKT_ACTION_FORWARD,
3118         MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
3119         MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
3120         MLXSW_REG_HPKT_ACTION_DISCARD,
3121         MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
3122         MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
3123 };
3124
3125 /* reg_hpkt_action
3126  * Action to perform on packet when trapped.
3127  * 0 - No action. Forward to CPU based on switching rules.
3128  * 1 - Trap to CPU (CPU receives sole copy).
3129  * 2 - Mirror to CPU (CPU receives a replica of the packet).
3130  * 3 - Discard.
3131  * 4 - Soft discard (allow other traps to act on the packet).
3132  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
3133  * Access: RW
3134  *
3135  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
3136  * addressed to the CPU.
3137  */
3138 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
3139
3140 /* reg_hpkt_trap_group
3141  * Trap group to associate the trap with.
3142  * Access: RW
3143  */
3144 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
3145
3146 /* reg_hpkt_trap_id
3147  * Trap ID.
3148  * Access: Index
3149  *
3150  * Note: A trap ID can only be associated with a single trap group. The device
3151  * will associate the trap ID with the last trap group configured.
3152  */
3153 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
3154
3155 enum {
3156         MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
3157         MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
3158         MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
3159 };
3160
3161 /* reg_hpkt_ctrl
3162  * Configure dedicated buffer resources for control packets.
3163  * 0 - Keep factory defaults.
3164  * 1 - Do not use control buffer for this trap ID.
3165  * 2 - Use control buffer for this trap ID.
3166  * Access: RW
3167  */
3168 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
3169
3170 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
3171 {
3172         enum mlxsw_reg_htgt_trap_group trap_group;
3173
3174         MLXSW_REG_ZERO(hpkt, payload);
3175         mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
3176         mlxsw_reg_hpkt_action_set(payload, action);
3177         switch (trap_id) {
3178         case MLXSW_TRAP_ID_ETHEMAD:
3179         case MLXSW_TRAP_ID_PUDE:
3180                 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
3181                 break;
3182         default:
3183                 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
3184                 break;
3185         }
3186         mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
3187         mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
3188         mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
3189 }
3190
3191 /* RGCR - Router General Configuration Register
3192  * --------------------------------------------
3193  * The register is used for setting up the router configuration.
3194  */
3195 #define MLXSW_REG_RGCR_ID 0x8001
3196 #define MLXSW_REG_RGCR_LEN 0x28
3197
3198 static const struct mlxsw_reg_info mlxsw_reg_rgcr = {
3199         .id = MLXSW_REG_RGCR_ID,
3200         .len = MLXSW_REG_RGCR_LEN,
3201 };
3202
3203 /* reg_rgcr_ipv4_en
3204  * IPv4 router enable.
3205  * Access: RW
3206  */
3207 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
3208
3209 /* reg_rgcr_ipv6_en
3210  * IPv6 router enable.
3211  * Access: RW
3212  */
3213 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
3214
3215 /* reg_rgcr_max_router_interfaces
3216  * Defines the maximum number of active router interfaces for all virtual
3217  * routers.
3218  * Access: RW
3219  */
3220 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
3221
3222 /* reg_rgcr_usp
3223  * Update switch priority and packet color.
3224  * 0 - Preserve the value of Switch Priority and packet color.
3225  * 1 - Recalculate the value of Switch Priority and packet color.
3226  * Access: RW
3227  *
3228  * Note: Not supported by SwitchX and SwitchX-2.
3229  */
3230 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
3231
3232 /* reg_rgcr_pcp_rw
3233  * Indicates how to handle the pcp_rewrite_en value:
3234  * 0 - Preserve the value of pcp_rewrite_en.
3235  * 2 - Disable PCP rewrite.
3236  * 3 - Enable PCP rewrite.
3237  * Access: RW
3238  *
3239  * Note: Not supported by SwitchX and SwitchX-2.
3240  */
3241 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
3242
3243 /* reg_rgcr_activity_dis
3244  * Activity disable:
3245  * 0 - Activity will be set when an entry is hit (default).
3246  * 1 - Activity will not be set when an entry is hit.
3247  *
3248  * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
3249  * (RALUE).
3250  * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
3251  * Entry (RAUHT).
3252  * Bits 2:7 are reserved.
3253  * Access: RW
3254  *
3255  * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
3256  */
3257 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
3258
3259 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en)
3260 {
3261         MLXSW_REG_ZERO(rgcr, payload);
3262         mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
3263 }
3264
3265 /* RITR - Router Interface Table Register
3266  * --------------------------------------
3267  * The register is used to configure the router interface table.
3268  */
3269 #define MLXSW_REG_RITR_ID 0x8002
3270 #define MLXSW_REG_RITR_LEN 0x40
3271
3272 static const struct mlxsw_reg_info mlxsw_reg_ritr = {
3273         .id = MLXSW_REG_RITR_ID,
3274         .len = MLXSW_REG_RITR_LEN,
3275 };
3276
3277 /* reg_ritr_enable
3278  * Enables routing on the router interface.
3279  * Access: RW
3280  */
3281 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
3282
3283 /* reg_ritr_ipv4
3284  * IPv4 routing enable. Enables routing of IPv4 traffic on the router
3285  * interface.
3286  * Access: RW
3287  */
3288 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
3289
3290 /* reg_ritr_ipv6
3291  * IPv6 routing enable. Enables routing of IPv6 traffic on the router
3292  * interface.
3293  * Access: RW
3294  */
3295 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
3296
3297 enum mlxsw_reg_ritr_if_type {
3298         MLXSW_REG_RITR_VLAN_IF,
3299         MLXSW_REG_RITR_FID_IF,
3300         MLXSW_REG_RITR_SP_IF,
3301 };
3302
3303 /* reg_ritr_type
3304  * Router interface type.
3305  * 0 - VLAN interface.
3306  * 1 - FID interface.
3307  * 2 - Sub-port interface.
3308  * Access: RW
3309  */
3310 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
3311
3312 enum {
3313         MLXSW_REG_RITR_RIF_CREATE,
3314         MLXSW_REG_RITR_RIF_DEL,
3315 };
3316
3317 /* reg_ritr_op
3318  * Opcode:
3319  * 0 - Create or edit RIF.
3320  * 1 - Delete RIF.
3321  * Reserved for SwitchX-2. For Spectrum, editing of interface properties
3322  * is not supported. An interface must be deleted and re-created in order
3323  * to update properties.
3324  * Access: WO
3325  */
3326 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
3327
3328 /* reg_ritr_rif
3329  * Router interface index. A pointer to the Router Interface Table.
3330  * Access: Index
3331  */
3332 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
3333
3334 /* reg_ritr_ipv4_fe
3335  * IPv4 Forwarding Enable.
3336  * Enables routing of IPv4 traffic on the router interface. When disabled,
3337  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3338  * Not supported in SwitchX-2.
3339  * Access: RW
3340  */
3341 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
3342
3343 /* reg_ritr_ipv6_fe
3344  * IPv6 Forwarding Enable.
3345  * Enables routing of IPv6 traffic on the router interface. When disabled,
3346  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3347  * Not supported in SwitchX-2.
3348  * Access: RW
3349  */
3350 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
3351
3352 /* reg_ritr_virtual_router
3353  * Virtual router ID associated with the router interface.
3354  * Access: RW
3355  */
3356 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
3357
3358 /* reg_ritr_mtu
3359  * Router interface MTU.
3360  * Access: RW
3361  */
3362 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
3363
3364 /* reg_ritr_if_swid
3365  * Switch partition ID.
3366  * Access: RW
3367  */
3368 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
3369
3370 /* reg_ritr_if_mac
3371  * Router interface MAC address.
3372  * In Spectrum, all MAC addresses must have the same 38 MSBits.
3373  * Access: RW
3374  */
3375 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
3376
3377 /* VLAN Interface */
3378
3379 /* reg_ritr_vlan_if_vid
3380  * VLAN ID.
3381  * Access: RW
3382  */
3383 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
3384
3385 /* FID Interface */
3386
3387 /* reg_ritr_fid_if_fid
3388  * Filtering ID. Used to connect a bridge to the router. Only FIDs from
3389  * the vFID range are supported.
3390  * Access: RW
3391  */
3392 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
3393
3394 static inline void mlxsw_reg_ritr_fid_set(char *payload,
3395                                           enum mlxsw_reg_ritr_if_type rif_type,
3396                                           u16 fid)
3397 {
3398         if (rif_type == MLXSW_REG_RITR_FID_IF)
3399                 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
3400         else
3401                 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
3402 }
3403
3404 /* Sub-port Interface */
3405
3406 /* reg_ritr_sp_if_lag
3407  * LAG indication. When this bit is set the system_port field holds the
3408  * LAG identifier.
3409  * Access: RW
3410  */
3411 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
3412
3413 /* reg_ritr_sp_system_port
3414  * Port unique indentifier. When lag bit is set, this field holds the
3415  * lag_id in bits 0:9.
3416  * Access: RW
3417  */
3418 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
3419
3420 /* reg_ritr_sp_if_vid
3421  * VLAN ID.
3422  * Access: RW
3423  */
3424 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
3425
3426 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
3427 {
3428         MLXSW_REG_ZERO(ritr, payload);
3429         mlxsw_reg_ritr_rif_set(payload, rif);
3430 }
3431
3432 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
3433                                              u16 system_port, u16 vid)
3434 {
3435         mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
3436         mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
3437         mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
3438 }
3439
3440 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
3441                                        enum mlxsw_reg_ritr_if_type type,
3442                                        u16 rif, u16 mtu, const char *mac)
3443 {
3444         bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
3445
3446         MLXSW_REG_ZERO(ritr, payload);
3447         mlxsw_reg_ritr_enable_set(payload, enable);
3448         mlxsw_reg_ritr_ipv4_set(payload, 1);
3449         mlxsw_reg_ritr_type_set(payload, type);
3450         mlxsw_reg_ritr_op_set(payload, op);
3451         mlxsw_reg_ritr_rif_set(payload, rif);
3452         mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
3453         mlxsw_reg_ritr_mtu_set(payload, mtu);
3454         mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
3455 }
3456
3457 /* RALTA - Router Algorithmic LPM Tree Allocation Register
3458  * -------------------------------------------------------
3459  * RALTA is used to allocate the LPM trees of the SHSPM method.
3460  */
3461 #define MLXSW_REG_RALTA_ID 0x8010
3462 #define MLXSW_REG_RALTA_LEN 0x04
3463
3464 static const struct mlxsw_reg_info mlxsw_reg_ralta = {
3465         .id = MLXSW_REG_RALTA_ID,
3466         .len = MLXSW_REG_RALTA_LEN,
3467 };
3468
3469 /* reg_ralta_op
3470  * opcode (valid for Write, must be 0 on Read)
3471  * 0 - allocate a tree
3472  * 1 - deallocate a tree
3473  * Access: OP
3474  */
3475 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
3476
3477 enum mlxsw_reg_ralxx_protocol {
3478         MLXSW_REG_RALXX_PROTOCOL_IPV4,
3479         MLXSW_REG_RALXX_PROTOCOL_IPV6,
3480 };
3481
3482 /* reg_ralta_protocol
3483  * Protocol.
3484  * Deallocation opcode: Reserved.
3485  * Access: RW
3486  */
3487 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
3488
3489 /* reg_ralta_tree_id
3490  * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
3491  * the tree identifier (managed by software).
3492  * Note that tree_id 0 is allocated for a default-route tree.
3493  * Access: Index
3494  */
3495 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
3496
3497 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
3498                                         enum mlxsw_reg_ralxx_protocol protocol,
3499                                         u8 tree_id)
3500 {
3501         MLXSW_REG_ZERO(ralta, payload);
3502         mlxsw_reg_ralta_op_set(payload, !alloc);
3503         mlxsw_reg_ralta_protocol_set(payload, protocol);
3504         mlxsw_reg_ralta_tree_id_set(payload, tree_id);
3505 }
3506
3507 /* MFCR - Management Fan Control Register
3508  * --------------------------------------
3509  * This register controls the settings of the Fan Speed PWM mechanism.
3510  */
3511 #define MLXSW_REG_MFCR_ID 0x9001
3512 #define MLXSW_REG_MFCR_LEN 0x08
3513
3514 static const struct mlxsw_reg_info mlxsw_reg_mfcr = {
3515         .id = MLXSW_REG_MFCR_ID,
3516         .len = MLXSW_REG_MFCR_LEN,
3517 };
3518
3519 enum mlxsw_reg_mfcr_pwm_frequency {
3520         MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
3521         MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
3522         MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
3523         MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
3524         MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
3525         MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
3526         MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
3527         MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
3528 };
3529
3530 /* reg_mfcr_pwm_frequency
3531  * Controls the frequency of the PWM signal.
3532  * Access: RW
3533  */
3534 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6);
3535
3536 #define MLXSW_MFCR_TACHOS_MAX 10
3537
3538 /* reg_mfcr_tacho_active
3539  * Indicates which of the tachometer is active (bit per tachometer).
3540  * Access: RO
3541  */
3542 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
3543
3544 #define MLXSW_MFCR_PWMS_MAX 5
3545
3546 /* reg_mfcr_pwm_active
3547  * Indicates which of the PWM control is active (bit per PWM).
3548  * Access: RO
3549  */
3550 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
3551
3552 static inline void
3553 mlxsw_reg_mfcr_pack(char *payload,
3554                     enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
3555 {
3556         MLXSW_REG_ZERO(mfcr, payload);
3557         mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
3558 }
3559
3560 static inline void
3561 mlxsw_reg_mfcr_unpack(char *payload,
3562                       enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
3563                       u16 *p_tacho_active, u8 *p_pwm_active)
3564 {
3565         *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
3566         *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
3567         *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
3568 }
3569
3570 /* MFSC - Management Fan Speed Control Register
3571  * --------------------------------------------
3572  * This register controls the settings of the Fan Speed PWM mechanism.
3573  */
3574 #define MLXSW_REG_MFSC_ID 0x9002
3575 #define MLXSW_REG_MFSC_LEN 0x08
3576
3577 static const struct mlxsw_reg_info mlxsw_reg_mfsc = {
3578         .id = MLXSW_REG_MFSC_ID,
3579         .len = MLXSW_REG_MFSC_LEN,
3580 };
3581
3582 /* reg_mfsc_pwm
3583  * Fan pwm to control / monitor.
3584  * Access: Index
3585  */
3586 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
3587
3588 /* reg_mfsc_pwm_duty_cycle
3589  * Controls the duty cycle of the PWM. Value range from 0..255 to
3590  * represent duty cycle of 0%...100%.
3591  * Access: RW
3592  */
3593 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
3594
3595 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
3596                                        u8 pwm_duty_cycle)
3597 {
3598         MLXSW_REG_ZERO(mfsc, payload);
3599         mlxsw_reg_mfsc_pwm_set(payload, pwm);
3600         mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
3601 }
3602
3603 /* MFSM - Management Fan Speed Measurement
3604  * ---------------------------------------
3605  * This register controls the settings of the Tacho measurements and
3606  * enables reading the Tachometer measurements.
3607  */
3608 #define MLXSW_REG_MFSM_ID 0x9003
3609 #define MLXSW_REG_MFSM_LEN 0x08
3610
3611 static const struct mlxsw_reg_info mlxsw_reg_mfsm = {
3612         .id = MLXSW_REG_MFSM_ID,
3613         .len = MLXSW_REG_MFSM_LEN,
3614 };
3615
3616 /* reg_mfsm_tacho
3617  * Fan tachometer index.
3618  * Access: Index
3619  */
3620 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
3621
3622 /* reg_mfsm_rpm
3623  * Fan speed (round per minute).
3624  * Access: RO
3625  */
3626 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
3627
3628 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
3629 {
3630         MLXSW_REG_ZERO(mfsm, payload);
3631         mlxsw_reg_mfsm_tacho_set(payload, tacho);
3632 }
3633
3634 /* MTCAP - Management Temperature Capabilities
3635  * -------------------------------------------
3636  * This register exposes the capabilities of the device and
3637  * system temperature sensing.
3638  */
3639 #define MLXSW_REG_MTCAP_ID 0x9009
3640 #define MLXSW_REG_MTCAP_LEN 0x08
3641
3642 static const struct mlxsw_reg_info mlxsw_reg_mtcap = {
3643         .id = MLXSW_REG_MTCAP_ID,
3644         .len = MLXSW_REG_MTCAP_LEN,
3645 };
3646
3647 /* reg_mtcap_sensor_count
3648  * Number of sensors supported by the device.
3649  * This includes the QSFP module sensors (if exists in the QSFP module).
3650  * Access: RO
3651  */
3652 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
3653
3654 /* MTMP - Management Temperature
3655  * -----------------------------
3656  * This register controls the settings of the temperature measurements
3657  * and enables reading the temperature measurements. Note that temperature
3658  * is in 0.125 degrees Celsius.
3659  */
3660 #define MLXSW_REG_MTMP_ID 0x900A
3661 #define MLXSW_REG_MTMP_LEN 0x20
3662
3663 static const struct mlxsw_reg_info mlxsw_reg_mtmp = {
3664         .id = MLXSW_REG_MTMP_ID,
3665         .len = MLXSW_REG_MTMP_LEN,
3666 };
3667
3668 /* reg_mtmp_sensor_index
3669  * Sensors index to access.
3670  * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
3671  * (module 0 is mapped to sensor_index 64).
3672  * Access: Index
3673  */
3674 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
3675
3676 /* Convert to milli degrees Celsius */
3677 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
3678
3679 /* reg_mtmp_temperature
3680  * Temperature reading from the sensor. Reading is in 0.125 Celsius
3681  * degrees units.
3682  * Access: RO
3683  */
3684 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
3685
3686 /* reg_mtmp_mte
3687  * Max Temperature Enable - enables measuring the max temperature on a sensor.
3688  * Access: RW
3689  */
3690 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
3691
3692 /* reg_mtmp_mtr
3693  * Max Temperature Reset - clears the value of the max temperature register.
3694  * Access: WO
3695  */
3696 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
3697
3698 /* reg_mtmp_max_temperature
3699  * The highest measured temperature from the sensor.
3700  * When the bit mte is cleared, the field max_temperature is reserved.
3701  * Access: RO
3702  */
3703 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
3704
3705 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
3706
3707 /* reg_mtmp_sensor_name
3708  * Sensor Name
3709  * Access: RO
3710  */
3711 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
3712
3713 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
3714                                        bool max_temp_enable,
3715                                        bool max_temp_reset)
3716 {
3717         MLXSW_REG_ZERO(mtmp, payload);
3718         mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
3719         mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
3720         mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
3721 }
3722
3723 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
3724                                          unsigned int *p_max_temp,
3725                                          char *sensor_name)
3726 {
3727         u16 temp;
3728
3729         if (p_temp) {
3730                 temp = mlxsw_reg_mtmp_temperature_get(payload);
3731                 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
3732         }
3733         if (p_max_temp) {
3734                 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
3735                 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
3736         }
3737         if (sensor_name)
3738                 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
3739 }
3740
3741 /* MLCR - Management LED Control Register
3742  * --------------------------------------
3743  * Controls the system LEDs.
3744  */
3745 #define MLXSW_REG_MLCR_ID 0x902B
3746 #define MLXSW_REG_MLCR_LEN 0x0C
3747
3748 static const struct mlxsw_reg_info mlxsw_reg_mlcr = {
3749         .id = MLXSW_REG_MLCR_ID,
3750         .len = MLXSW_REG_MLCR_LEN,
3751 };
3752
3753 /* reg_mlcr_local_port
3754  * Local port number.
3755  * Access: RW
3756  */
3757 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
3758
3759 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
3760
3761 /* reg_mlcr_beacon_duration
3762  * Duration of the beacon to be active, in seconds.
3763  * 0x0 - Will turn off the beacon.
3764  * 0xFFFF - Will turn on the beacon until explicitly turned off.
3765  * Access: RW
3766  */
3767 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
3768
3769 /* reg_mlcr_beacon_remain
3770  * Remaining duration of the beacon, in seconds.
3771  * 0xFFFF indicates an infinite amount of time.
3772  * Access: RO
3773  */
3774 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
3775
3776 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
3777                                        bool active)
3778 {
3779         MLXSW_REG_ZERO(mlcr, payload);
3780         mlxsw_reg_mlcr_local_port_set(payload, local_port);
3781         mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
3782                                            MLXSW_REG_MLCR_DURATION_MAX : 0);
3783 }
3784
3785 /* SBPR - Shared Buffer Pools Register
3786  * -----------------------------------
3787  * The SBPR configures and retrieves the shared buffer pools and configuration.
3788  */
3789 #define MLXSW_REG_SBPR_ID 0xB001
3790 #define MLXSW_REG_SBPR_LEN 0x14
3791
3792 static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
3793         .id = MLXSW_REG_SBPR_ID,
3794         .len = MLXSW_REG_SBPR_LEN,
3795 };
3796
3797 /* shared direstion enum for SBPR, SBCM, SBPM */
3798 enum mlxsw_reg_sbxx_dir {
3799         MLXSW_REG_SBXX_DIR_INGRESS,
3800         MLXSW_REG_SBXX_DIR_EGRESS,
3801 };
3802
3803 /* reg_sbpr_dir
3804  * Direction.
3805  * Access: Index
3806  */
3807 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
3808
3809 /* reg_sbpr_pool
3810  * Pool index.
3811  * Access: Index
3812  */
3813 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
3814
3815 /* reg_sbpr_size
3816  * Pool size in buffer cells.
3817  * Access: RW
3818  */
3819 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
3820
3821 enum mlxsw_reg_sbpr_mode {
3822         MLXSW_REG_SBPR_MODE_STATIC,
3823         MLXSW_REG_SBPR_MODE_DYNAMIC,
3824 };
3825
3826 /* reg_sbpr_mode
3827  * Pool quota calculation mode.
3828  * Access: RW
3829  */
3830 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
3831
3832 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
3833                                        enum mlxsw_reg_sbxx_dir dir,
3834                                        enum mlxsw_reg_sbpr_mode mode, u32 size)
3835 {
3836         MLXSW_REG_ZERO(sbpr, payload);
3837         mlxsw_reg_sbpr_pool_set(payload, pool);
3838         mlxsw_reg_sbpr_dir_set(payload, dir);
3839         mlxsw_reg_sbpr_mode_set(payload, mode);
3840         mlxsw_reg_sbpr_size_set(payload, size);
3841 }
3842
3843 /* SBCM - Shared Buffer Class Management Register
3844  * ----------------------------------------------
3845  * The SBCM register configures and retrieves the shared buffer allocation
3846  * and configuration according to Port-PG, including the binding to pool
3847  * and definition of the associated quota.
3848  */
3849 #define MLXSW_REG_SBCM_ID 0xB002
3850 #define MLXSW_REG_SBCM_LEN 0x28
3851
3852 static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
3853         .id = MLXSW_REG_SBCM_ID,
3854         .len = MLXSW_REG_SBCM_LEN,
3855 };
3856
3857 /* reg_sbcm_local_port
3858  * Local port number.
3859  * For Ingress: excludes CPU port and Router port
3860  * For Egress: excludes IP Router
3861  * Access: Index
3862  */
3863 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
3864
3865 /* reg_sbcm_pg_buff
3866  * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
3867  * For PG buffer: range is 0..cap_max_pg_buffers - 1
3868  * For traffic class: range is 0..cap_max_tclass - 1
3869  * Note that when traffic class is in MC aware mode then the traffic
3870  * classes which are MC aware cannot be configured.
3871  * Access: Index
3872  */
3873 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
3874
3875 /* reg_sbcm_dir
3876  * Direction.
3877  * Access: Index
3878  */
3879 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
3880
3881 /* reg_sbcm_min_buff
3882  * Minimum buffer size for the limiter, in cells.
3883  * Access: RW
3884  */
3885 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
3886
3887 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
3888 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
3889 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
3890
3891 /* reg_sbcm_max_buff
3892  * When the pool associated to the port-pg/tclass is configured to
3893  * static, Maximum buffer size for the limiter configured in cells.
3894  * When the pool associated to the port-pg/tclass is configured to
3895  * dynamic, the max_buff holds the "alpha" parameter, supporting
3896  * the following values:
3897  * 0: 0
3898  * i: (1/128)*2^(i-1), for i=1..14
3899  * 0xFF: Infinity
3900  * Access: RW
3901  */
3902 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
3903
3904 /* reg_sbcm_pool
3905  * Association of the port-priority to a pool.
3906  * Access: RW
3907  */
3908 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
3909
3910 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
3911                                        enum mlxsw_reg_sbxx_dir dir,
3912                                        u32 min_buff, u32 max_buff, u8 pool)
3913 {
3914         MLXSW_REG_ZERO(sbcm, payload);
3915         mlxsw_reg_sbcm_local_port_set(payload, local_port);
3916         mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
3917         mlxsw_reg_sbcm_dir_set(payload, dir);
3918         mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
3919         mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
3920         mlxsw_reg_sbcm_pool_set(payload, pool);
3921 }
3922
3923 /* SBPM - Shared Buffer Port Management Register
3924  * ---------------------------------------------
3925  * The SBPM register configures and retrieves the shared buffer allocation
3926  * and configuration according to Port-Pool, including the definition
3927  * of the associated quota.
3928  */
3929 #define MLXSW_REG_SBPM_ID 0xB003
3930 #define MLXSW_REG_SBPM_LEN 0x28
3931
3932 static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
3933         .id = MLXSW_REG_SBPM_ID,
3934         .len = MLXSW_REG_SBPM_LEN,
3935 };
3936
3937 /* reg_sbpm_local_port
3938  * Local port number.
3939  * For Ingress: excludes CPU port and Router port
3940  * For Egress: excludes IP Router
3941  * Access: Index
3942  */
3943 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
3944
3945 /* reg_sbpm_pool
3946  * The pool associated to quota counting on the local_port.
3947  * Access: Index
3948  */
3949 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
3950
3951 /* reg_sbpm_dir
3952  * Direction.
3953  * Access: Index
3954  */
3955 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
3956
3957 /* reg_sbpm_buff_occupancy
3958  * Current buffer occupancy in cells.
3959  * Access: RO
3960  */
3961 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
3962
3963 /* reg_sbpm_clr
3964  * Clear Max Buffer Occupancy
3965  * When this bit is set, max_buff_occupancy field is cleared (and a
3966  * new max value is tracked from the time the clear was performed).
3967  * Access: OP
3968  */
3969 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
3970
3971 /* reg_sbpm_max_buff_occupancy
3972  * Maximum value of buffer occupancy in cells monitored. Cleared by
3973  * writing to the clr field.
3974  * Access: RO
3975  */
3976 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
3977
3978 /* reg_sbpm_min_buff
3979  * Minimum buffer size for the limiter, in cells.
3980  * Access: RW
3981  */
3982 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
3983
3984 /* reg_sbpm_max_buff
3985  * When the pool associated to the port-pg/tclass is configured to
3986  * static, Maximum buffer size for the limiter configured in cells.
3987  * When the pool associated to the port-pg/tclass is configured to
3988  * dynamic, the max_buff holds the "alpha" parameter, supporting
3989  * the following values:
3990  * 0: 0
3991  * i: (1/128)*2^(i-1), for i=1..14
3992  * 0xFF: Infinity
3993  * Access: RW
3994  */
3995 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
3996
3997 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
3998                                        enum mlxsw_reg_sbxx_dir dir, bool clr,
3999                                        u32 min_buff, u32 max_buff)
4000 {
4001         MLXSW_REG_ZERO(sbpm, payload);
4002         mlxsw_reg_sbpm_local_port_set(payload, local_port);
4003         mlxsw_reg_sbpm_pool_set(payload, pool);
4004         mlxsw_reg_sbpm_dir_set(payload, dir);
4005         mlxsw_reg_sbpm_clr_set(payload, clr);
4006         mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
4007         mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
4008 }
4009
4010 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
4011                                          u32 *p_max_buff_occupancy)
4012 {
4013         *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
4014         *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
4015 }
4016
4017 /* SBMM - Shared Buffer Multicast Management Register
4018  * --------------------------------------------------
4019  * The SBMM register configures and retrieves the shared buffer allocation
4020  * and configuration for MC packets according to Switch-Priority, including
4021  * the binding to pool and definition of the associated quota.
4022  */
4023 #define MLXSW_REG_SBMM_ID 0xB004
4024 #define MLXSW_REG_SBMM_LEN 0x28
4025
4026 static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
4027         .id = MLXSW_REG_SBMM_ID,
4028         .len = MLXSW_REG_SBMM_LEN,
4029 };
4030
4031 /* reg_sbmm_prio
4032  * Switch Priority.
4033  * Access: Index
4034  */
4035 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
4036
4037 /* reg_sbmm_min_buff
4038  * Minimum buffer size for the limiter, in cells.
4039  * Access: RW
4040  */
4041 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
4042
4043 /* reg_sbmm_max_buff
4044  * When the pool associated to the port-pg/tclass is configured to
4045  * static, Maximum buffer size for the limiter configured in cells.
4046  * When the pool associated to the port-pg/tclass is configured to
4047  * dynamic, the max_buff holds the "alpha" parameter, supporting
4048  * the following values:
4049  * 0: 0
4050  * i: (1/128)*2^(i-1), for i=1..14
4051  * 0xFF: Infinity
4052  * Access: RW
4053  */
4054 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
4055
4056 /* reg_sbmm_pool
4057  * Association of the port-priority to a pool.
4058  * Access: RW
4059  */
4060 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
4061
4062 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
4063                                        u32 max_buff, u8 pool)
4064 {
4065         MLXSW_REG_ZERO(sbmm, payload);
4066         mlxsw_reg_sbmm_prio_set(payload, prio);
4067         mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
4068         mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
4069         mlxsw_reg_sbmm_pool_set(payload, pool);
4070 }
4071
4072 /* SBSR - Shared Buffer Status Register
4073  * ------------------------------------
4074  * The SBSR register retrieves the shared buffer occupancy according to
4075  * Port-Pool. Note that this register enables reading a large amount of data.
4076  * It is the user's responsibility to limit the amount of data to ensure the
4077  * response can match the maximum transfer unit. In case the response exceeds
4078  * the maximum transport unit, it will be truncated with no special notice.
4079  */
4080 #define MLXSW_REG_SBSR_ID 0xB005
4081 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
4082 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
4083 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
4084 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN +   \
4085                             MLXSW_REG_SBSR_REC_LEN *    \
4086                             MLXSW_REG_SBSR_REC_MAX_COUNT)
4087
4088 static const struct mlxsw_reg_info mlxsw_reg_sbsr = {
4089         .id = MLXSW_REG_SBSR_ID,
4090         .len = MLXSW_REG_SBSR_LEN,
4091 };
4092
4093 /* reg_sbsr_clr
4094  * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
4095  * field is cleared (and a new max value is tracked from the time the clear
4096  * was performed).
4097  * Access: OP
4098  */
4099 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
4100
4101 /* reg_sbsr_ingress_port_mask
4102  * Bit vector for all ingress network ports.
4103  * Indicates which of the ports (for which the relevant bit is set)
4104  * are affected by the set operation. Configuration of any other port
4105  * does not change.
4106  * Access: Index
4107  */
4108 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
4109
4110 /* reg_sbsr_pg_buff_mask
4111  * Bit vector for all switch priority groups.
4112  * Indicates which of the priorities (for which the relevant bit is set)
4113  * are affected by the set operation. Configuration of any other priority
4114  * does not change.
4115  * Range is 0..cap_max_pg_buffers - 1
4116  * Access: Index
4117  */
4118 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
4119
4120 /* reg_sbsr_egress_port_mask
4121  * Bit vector for all egress network ports.
4122  * Indicates which of the ports (for which the relevant bit is set)
4123  * are affected by the set operation. Configuration of any other port
4124  * does not change.
4125  * Access: Index
4126  */
4127 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
4128
4129 /* reg_sbsr_tclass_mask
4130  * Bit vector for all traffic classes.
4131  * Indicates which of the traffic classes (for which the relevant bit is
4132  * set) are affected by the set operation. Configuration of any other
4133  * traffic class does not change.
4134  * Range is 0..cap_max_tclass - 1
4135  * Access: Index
4136  */
4137 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
4138
4139 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
4140 {
4141         MLXSW_REG_ZERO(sbsr, payload);
4142         mlxsw_reg_sbsr_clr_set(payload, clr);
4143 }
4144
4145 /* reg_sbsr_rec_buff_occupancy
4146  * Current buffer occupancy in cells.
4147  * Access: RO
4148  */
4149 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
4150                      0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
4151
4152 /* reg_sbsr_rec_max_buff_occupancy
4153  * Maximum value of buffer occupancy in cells monitored. Cleared by
4154  * writing to the clr field.
4155  * Access: RO
4156  */
4157 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
4158                      0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
4159
4160 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
4161                                              u32 *p_buff_occupancy,
4162                                              u32 *p_max_buff_occupancy)
4163 {
4164         *p_buff_occupancy =
4165                 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
4166         *p_max_buff_occupancy =
4167                 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
4168 }
4169
4170 static inline const char *mlxsw_reg_id_str(u16 reg_id)
4171 {
4172         switch (reg_id) {
4173         case MLXSW_REG_SGCR_ID:
4174                 return "SGCR";
4175         case MLXSW_REG_SPAD_ID:
4176                 return "SPAD";
4177         case MLXSW_REG_SMID_ID:
4178                 return "SMID";
4179         case MLXSW_REG_SSPR_ID:
4180                 return "SSPR";
4181         case MLXSW_REG_SFDAT_ID:
4182                 return "SFDAT";
4183         case MLXSW_REG_SFD_ID:
4184                 return "SFD";
4185         case MLXSW_REG_SFN_ID:
4186                 return "SFN";
4187         case MLXSW_REG_SPMS_ID:
4188                 return "SPMS";
4189         case MLXSW_REG_SPVID_ID:
4190                 return "SPVID";
4191         case MLXSW_REG_SPVM_ID:
4192                 return "SPVM";
4193         case MLXSW_REG_SPAFT_ID:
4194                 return "SPAFT";
4195         case MLXSW_REG_SFGC_ID:
4196                 return "SFGC";
4197         case MLXSW_REG_SFTR_ID:
4198                 return "SFTR";
4199         case MLXSW_REG_SFDF_ID:
4200                 return "SFDF";
4201         case MLXSW_REG_SLDR_ID:
4202                 return "SLDR";
4203         case MLXSW_REG_SLCR_ID:
4204                 return "SLCR";
4205         case MLXSW_REG_SLCOR_ID:
4206                 return "SLCOR";
4207         case MLXSW_REG_SPMLR_ID:
4208                 return "SPMLR";
4209         case MLXSW_REG_SVFA_ID:
4210                 return "SVFA";
4211         case MLXSW_REG_SVPE_ID:
4212                 return "SVPE";
4213         case MLXSW_REG_SFMR_ID:
4214                 return "SFMR";
4215         case MLXSW_REG_SPVMLR_ID:
4216                 return "SPVMLR";
4217         case MLXSW_REG_QTCT_ID:
4218                 return "QTCT";
4219         case MLXSW_REG_QEEC_ID:
4220                 return "QEEC";
4221         case MLXSW_REG_PMLP_ID:
4222                 return "PMLP";
4223         case MLXSW_REG_PMTU_ID:
4224                 return "PMTU";
4225         case MLXSW_REG_PTYS_ID:
4226                 return "PTYS";
4227         case MLXSW_REG_PPAD_ID:
4228                 return "PPAD";
4229         case MLXSW_REG_PAOS_ID:
4230                 return "PAOS";
4231         case MLXSW_REG_PFCC_ID:
4232                 return "PFCC";
4233         case MLXSW_REG_PPCNT_ID:
4234                 return "PPCNT";
4235         case MLXSW_REG_PPTB_ID:
4236                 return "PPTB";
4237         case MLXSW_REG_PBMC_ID:
4238                 return "PBMC";
4239         case MLXSW_REG_PSPA_ID:
4240                 return "PSPA";
4241         case MLXSW_REG_HTGT_ID:
4242                 return "HTGT";
4243         case MLXSW_REG_HPKT_ID:
4244                 return "HPKT";
4245         case MLXSW_REG_RGCR_ID:
4246                 return "RGCR";
4247         case MLXSW_REG_RITR_ID:
4248                 return "RITR";
4249         case MLXSW_REG_RALTA_ID:
4250                 return "RALTA";
4251         case MLXSW_REG_MFCR_ID:
4252                 return "MFCR";
4253         case MLXSW_REG_MFSC_ID:
4254                 return "MFSC";
4255         case MLXSW_REG_MFSM_ID:
4256                 return "MFSM";
4257         case MLXSW_REG_MTCAP_ID:
4258                 return "MTCAP";
4259         case MLXSW_REG_MTMP_ID:
4260                 return "MTMP";
4261         case MLXSW_REG_MLCR_ID:
4262                 return "MLCR";
4263         case MLXSW_REG_SBPR_ID:
4264                 return "SBPR";
4265         case MLXSW_REG_SBCM_ID:
4266                 return "SBCM";
4267         case MLXSW_REG_SBPM_ID:
4268                 return "SBPM";
4269         case MLXSW_REG_SBMM_ID:
4270                 return "SBMM";
4271         case MLXSW_REG_SBSR_ID:
4272                 return "SBSR";
4273         default:
4274                 return "*UNKNOWN*";
4275         }
4276 }
4277
4278 /* PUDE - Port Up / Down Event
4279  * ---------------------------
4280  * Reports the operational state change of a port.
4281  */
4282 #define MLXSW_REG_PUDE_LEN 0x10
4283
4284 /* reg_pude_swid
4285  * Switch partition ID with which to associate the port.
4286  * Access: Index
4287  */
4288 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
4289
4290 /* reg_pude_local_port
4291  * Local port number.
4292  * Access: Index
4293  */
4294 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
4295
4296 /* reg_pude_admin_status
4297  * Port administrative state (the desired state).
4298  * 1 - Up.
4299  * 2 - Down.
4300  * 3 - Up once. This means that in case of link failure, the port won't go
4301  *     into polling mode, but will wait to be re-enabled by software.
4302  * 4 - Disabled by system. Can only be set by hardware.
4303  * Access: RO
4304  */
4305 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
4306
4307 /* reg_pude_oper_status
4308  * Port operatioanl state.
4309  * 1 - Up.
4310  * 2 - Down.
4311  * 3 - Down by port failure. This means that the device will not let the
4312  *     port up again until explicitly specified by software.
4313  * Access: RO
4314  */
4315 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
4316
4317 #endif