drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37 #include <linux/dcbnl.h>
  38 #include <linux/if_ether.h>
  39
  40 #include "spectrum.h"
  41 #include "core.h"
  42 #include "port.h"
  43 #include "reg.h"
  44
  45 struct mlxsw_sp_pb {
  46         u8 index;
  47         u16 size;
  48 };
  49
  50 #define MLXSW_SP_PB(_index, _size)      \
  51         {                               \
  52                 .index = _index,        \
  53                 .size = _size,          \
  54         }
  55
  56 static const struct mlxsw_sp_pb mlxsw_sp_pbs[] = {
  57         MLXSW_SP_PB(0, 2 * MLXSW_SP_BYTES_TO_CELLS(ETH_FRAME_LEN)),
  58         MLXSW_SP_PB(1, 0),
  59         MLXSW_SP_PB(2, 0),
  60         MLXSW_SP_PB(3, 0),
  61         MLXSW_SP_PB(4, 0),
  62         MLXSW_SP_PB(5, 0),
  63         MLXSW_SP_PB(6, 0),
  64         MLXSW_SP_PB(7, 0),
  65         MLXSW_SP_PB(9, 2 * MLXSW_SP_BYTES_TO_CELLS(MLXSW_PORT_MAX_MTU)),
  66 };
  67
  68 #define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)
  69
  70 static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
  71 {
  72         char pbmc_pl[MLXSW_REG_PBMC_LEN];
  73         int i;
  74
  75         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
  76                             0xffff, 0xffff / 2);
  77         for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
  78                 const struct mlxsw_sp_pb *pb;
  79
  80                 pb = &mlxsw_sp_pbs[i];
  81                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pb->index, pb->size);
  82         }
  83         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
  84                                MLXSW_REG(pbmc), pbmc_pl);
  85 }
  86
  87 static int mlxsw_sp_port_pb_prio_init(struct mlxsw_sp_port *mlxsw_sp_port)
  88 {
  89         char pptb_pl[MLXSW_REG_PPTB_LEN];
  90         int i;
  91
  92         mlxsw_reg_pptb_pack(pptb_pl, mlxsw_sp_port->local_port);
  93         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
  94                 mlxsw_reg_pptb_prio_to_buff_set(pptb_pl, i, 0);
  95         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pptb),
  96                                pptb_pl);
  97 }
  98
  99 static int mlxsw_sp_port_headroom_init(struct mlxsw_sp_port *mlxsw_sp_port)
 100 {
 101         int err;
 102
 103         err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
 104         if (err)
 105                 return err;
 106         return mlxsw_sp_port_pb_prio_init(mlxsw_sp_port);
 107 }
 108
 109 struct mlxsw_sp_sb_pool {
 110         u8 pool;
 111         enum mlxsw_reg_sbpr_dir dir;
 112         enum mlxsw_reg_sbpr_mode mode;
 113         u32 size;
 114 };
 115
 116 #define MLXSW_SP_SB_POOL_INGRESS_SIZE                           \
 117         (15000000 - (2 * 20000 * MLXSW_PORT_MAX_PORTS))
 118 #define MLXSW_SP_SB_POOL_EGRESS_SIZE                            \
 119         (14000000 - (8 * 1500 * MLXSW_PORT_MAX_PORTS))
 120
 121 #define MLXSW_SP_SB_POOL(_pool, _dir, _mode, _size)             \
 122         {                                                       \
 123                 .pool = _pool,                                  \
 124                 .dir = _dir,                                    \
 125                 .mode = _mode,                                  \
 126                 .size = _size,                                  \
 127         }
 128
 129 #define MLXSW_SP_SB_POOL_INGRESS(_pool, _size)                  \
 130         MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_INGRESS,     \
 131                          MLXSW_REG_SBPR_MODE_DYNAMIC, _size)
 132
 133 #define MLXSW_SP_SB_POOL_EGRESS(_pool, _size)                   \
 134         MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_EGRESS,      \
 135                          MLXSW_REG_SBPR_MODE_DYNAMIC, _size)
 136
 137 static const struct mlxsw_sp_sb_pool mlxsw_sp_sb_pools[] = {
 138         MLXSW_SP_SB_POOL_INGRESS(0, MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_POOL_INGRESS_SIZE)),
 139         MLXSW_SP_SB_POOL_INGRESS(1, 0),
 140         MLXSW_SP_SB_POOL_INGRESS(2, 0),
 141         MLXSW_SP_SB_POOL_INGRESS(3, 0),
 142         MLXSW_SP_SB_POOL_EGRESS(0, MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_POOL_EGRESS_SIZE)),
 143         MLXSW_SP_SB_POOL_EGRESS(1, 0),
 144         MLXSW_SP_SB_POOL_EGRESS(2, 0),
 145         MLXSW_SP_SB_POOL_EGRESS(2, MLXSW_SP_BYTES_TO_CELLS(MLXSW_SP_SB_POOL_EGRESS_SIZE)),
 146 };
 147
 148 #define MLXSW_SP_SB_POOLS_LEN ARRAY_SIZE(mlxsw_sp_sb_pools)
 149
 150 static int mlxsw_sp_sb_pools_init(struct mlxsw_sp *mlxsw_sp)
 151 {
 152         char sbpr_pl[MLXSW_REG_SBPR_LEN];
 153         int i;
 154         int err;
 155
 156         for (i = 0; i < MLXSW_SP_SB_POOLS_LEN; i++) {
 157                 const struct mlxsw_sp_sb_pool *pool;
 158
 159                 pool = &mlxsw_sp_sb_pools[i];
 160                 mlxsw_reg_sbpr_pack(sbpr_pl, pool->pool, pool->dir,
 161                                     pool->mode, pool->size);
 162                 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
 163                 if (err)
 164                         return err;
 165         }
 166         return 0;
 167 }
 168
 169 struct mlxsw_sp_sb_cm {
 170         union {
 171                 u8 pg;
 172                 u8 tc;
 173         } u;
 174         enum mlxsw_reg_sbcm_dir dir;
 175         u32 min_buff;
 176         u32 max_buff;
 177         u8 pool;
 178 };
 179
 180 #define MLXSW_SP_SB_CM(_pg_tc, _dir, _min_buff, _max_buff, _pool)       \
 181         {                                                               \
 182                 .u.pg = _pg_tc,                                         \
 183                 .dir = _dir,                                            \
 184                 .min_buff = _min_buff,                                  \
 185                 .max_buff = _max_buff,                                  \
 186                 .pool = _pool,                                          \
 187         }
 188
 189 #define MLXSW_SP_SB_CM_INGRESS(_pg, _min_buff, _max_buff)               \
 190         MLXSW_SP_SB_CM(_pg, MLXSW_REG_SBCM_DIR_INGRESS,                 \
 191                        _min_buff, _max_buff, 0)
 192
 193 #define MLXSW_SP_SB_CM_EGRESS(_tc, _min_buff, _max_buff)                \
 194         MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS,                  \
 195                        _min_buff, _max_buff, 0)
 196
 197 #define MLXSW_SP_CPU_PORT_SB_CM_EGRESS(_tc)                             \
 198         MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, 104, 2, 3)
 199
 200 static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms[] = {
 201         MLXSW_SP_SB_CM_INGRESS(0, MLXSW_SP_BYTES_TO_CELLS(10000), 8),
 202         MLXSW_SP_SB_CM_INGRESS(1, 0, 0),
 203         MLXSW_SP_SB_CM_INGRESS(2, 0, 0),
 204         MLXSW_SP_SB_CM_INGRESS(3, 0, 0),
 205         MLXSW_SP_SB_CM_INGRESS(4, 0, 0),
 206         MLXSW_SP_SB_CM_INGRESS(5, 0, 0),
 207         MLXSW_SP_SB_CM_INGRESS(6, 0, 0),
 208         MLXSW_SP_SB_CM_INGRESS(7, 0, 0),
 209         MLXSW_SP_SB_CM_INGRESS(9, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff),
 210         MLXSW_SP_SB_CM_EGRESS(0, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
 211         MLXSW_SP_SB_CM_EGRESS(1, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
 212         MLXSW_SP_SB_CM_EGRESS(2, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
 213         MLXSW_SP_SB_CM_EGRESS(3, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
 214         MLXSW_SP_SB_CM_EGRESS(4, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
 215         MLXSW_SP_SB_CM_EGRESS(5, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
 216         MLXSW_SP_SB_CM_EGRESS(6, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
 217         MLXSW_SP_SB_CM_EGRESS(7, MLXSW_SP_BYTES_TO_CELLS(1500), 9),
 218         MLXSW_SP_SB_CM_EGRESS(8, 0, 0),
 219         MLXSW_SP_SB_CM_EGRESS(9, 0, 0),
 220         MLXSW_SP_SB_CM_EGRESS(10, 0, 0),
 221         MLXSW_SP_SB_CM_EGRESS(11, 0, 0),
 222         MLXSW_SP_SB_CM_EGRESS(12, 0, 0),
 223         MLXSW_SP_SB_CM_EGRESS(13, 0, 0),
 224         MLXSW_SP_SB_CM_EGRESS(14, 0, 0),
 225         MLXSW_SP_SB_CM_EGRESS(15, 0, 0),
 226         MLXSW_SP_SB_CM_EGRESS(16, 1, 0xff),
 227 };
 228
 229 #define MLXSW_SP_SB_CMS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms)
 230
 231 static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
 232         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(0),
 233         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(1),
 234         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(2),
 235         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(3),
 236         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(4),
 237         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(5),
 238         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(6),
 239         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(7),
 240         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(8),
 241         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(9),
 242         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(10),
 243         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(11),
 244         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(12),
 245         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(13),
 246         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(14),
 247         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(15),
 248         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(16),
 249         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(17),
 250         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(18),
 251         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(19),
 252         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(20),
 253         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(21),
 254         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(22),
 255         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(23),
 256         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(24),
 257         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(25),
 258         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(26),
 259         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(27),
 260         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(28),
 261         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(29),
 262         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(30),
 263         MLXSW_SP_CPU_PORT_SB_CM_EGRESS(31),
 264 };
 265
 266 #define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
 267         ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)
 268
 269 static int mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 270                                 const struct mlxsw_sp_sb_cm *cms,
 271                                 size_t cms_len)
 272 {
 273         char sbcm_pl[MLXSW_REG_SBCM_LEN];
 274         int i;
 275         int err;
 276
 277         for (i = 0; i < cms_len; i++) {
 278                 const struct mlxsw_sp_sb_cm *cm;
 279
 280                 cm = &cms[i];
 281                 mlxsw_reg_sbcm_pack(sbcm_pl, local_port, cm->u.pg, cm->dir,
 282                                     cm->min_buff, cm->max_buff, cm->pool);
 283                 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
 284                 if (err)
 285                         return err;
 286         }
 287         return 0;
 288 }
 289
 290 static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
 291 {
 292         return mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
 293                                     mlxsw_sp_port->local_port, mlxsw_sp_sb_cms,
 294                                     MLXSW_SP_SB_CMS_LEN);
 295 }
 296
 297 static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
 298 {
 299         return mlxsw_sp_sb_cms_init(mlxsw_sp, 0, mlxsw_sp_cpu_port_sb_cms,
 300                                     MLXSW_SP_CPU_PORT_SB_MCS_LEN);
 301 }
 302
 303 struct mlxsw_sp_sb_pm {
 304         u8 pool;
 305         enum mlxsw_reg_sbpm_dir dir;
 306         u32 min_buff;
 307         u32 max_buff;
 308 };
 309
 310 #define MLXSW_SP_SB_PM(_pool, _dir, _min_buff, _max_buff)       \
 311         {                                                       \
 312                 .pool = _pool,                                  \
 313                 .dir = _dir,                                    \
 314                 .min_buff = _min_buff,                          \
 315                 .max_buff = _max_buff,                          \
 316         }
 317
 318 #define MLXSW_SP_SB_PM_INGRESS(_pool, _min_buff, _max_buff)     \
 319         MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_INGRESS,       \
 320                        _min_buff, _max_buff)
 321
 322 #define MLXSW_SP_SB_PM_EGRESS(_pool, _min_buff, _max_buff)      \
 323         MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_EGRESS,        \
 324                        _min_buff, _max_buff)
 325
 326 static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
 327         MLXSW_SP_SB_PM_INGRESS(0, 0, 0xff),
 328         MLXSW_SP_SB_PM_INGRESS(1, 0, 0),
 329         MLXSW_SP_SB_PM_INGRESS(2, 0, 0),
 330         MLXSW_SP_SB_PM_INGRESS(3, 0, 0),
 331         MLXSW_SP_SB_PM_EGRESS(0, 0, 7),
 332         MLXSW_SP_SB_PM_EGRESS(1, 0, 0),
 333         MLXSW_SP_SB_PM_EGRESS(2, 0, 0),
 334         MLXSW_SP_SB_PM_EGRESS(3, 0, 0),
 335 };
 336
 337 #define MLXSW_SP_SB_PMS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms)
 338
 339 static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
 340 {
 341         char sbpm_pl[MLXSW_REG_SBPM_LEN];
 342         int i;
 343         int err;
 344
 345         for (i = 0; i < MLXSW_SP_SB_PMS_LEN; i++) {
 346                 const struct mlxsw_sp_sb_pm *pm;
 347
 348                 pm = &mlxsw_sp_sb_pms[i];
 349                 mlxsw_reg_sbpm_pack(sbpm_pl, mlxsw_sp_port->local_port,
 350                                     pm->pool, pm->dir,
 351                                     pm->min_buff, pm->max_buff);
 352                 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
 353                                       MLXSW_REG(sbpm), sbpm_pl);
 354                 if (err)
 355                         return err;
 356         }
 357         return 0;
 358 }
 359
 360 struct mlxsw_sp_sb_mm {
 361         u8 prio;
 362         u32 min_buff;
 363         u32 max_buff;
 364         u8 pool;
 365 };
 366
 367 #define MLXSW_SP_SB_MM(_prio, _min_buff, _max_buff, _pool)      \
 368         {                                                       \
 369                 .prio = _prio,                                  \
 370                 .min_buff = _min_buff,                          \
 371                 .max_buff = _max_buff,                          \
 372                 .pool = _pool,                                  \
 373         }
 374
 375 static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
 376         MLXSW_SP_SB_MM(0, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 377         MLXSW_SP_SB_MM(1, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 378         MLXSW_SP_SB_MM(2, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 379         MLXSW_SP_SB_MM(3, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 380         MLXSW_SP_SB_MM(4, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 381         MLXSW_SP_SB_MM(5, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 382         MLXSW_SP_SB_MM(6, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 383         MLXSW_SP_SB_MM(7, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 384         MLXSW_SP_SB_MM(8, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 385         MLXSW_SP_SB_MM(9, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 386         MLXSW_SP_SB_MM(10, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 387         MLXSW_SP_SB_MM(11, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 388         MLXSW_SP_SB_MM(12, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 389         MLXSW_SP_SB_MM(13, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 390         MLXSW_SP_SB_MM(14, MLXSW_SP_BYTES_TO_CELLS(20000), 0xff, 0),
 391 };
 392
 393 #define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)
 394
 395 static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
 396 {
 397         char sbmm_pl[MLXSW_REG_SBMM_LEN];
 398         int i;
 399         int err;
 400
 401         for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
 402                 const struct mlxsw_sp_sb_mm *mc;
 403
 404                 mc = &mlxsw_sp_sb_mms[i];
 405                 mlxsw_reg_sbmm_pack(sbmm_pl, mc->prio, mc->min_buff,
 406                                     mc->max_buff, mc->pool);
 407                 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
 408                 if (err)
 409                         return err;
 410         }
 411         return 0;
 412 }
 413
 414 int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
 415 {
 416         int err;
 417
 418         err = mlxsw_sp_sb_pools_init(mlxsw_sp);
 419         if (err)
 420                 return err;
 421         err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
 422         if (err)
 423                 return err;
 424         err = mlxsw_sp_sb_mms_init(mlxsw_sp);
 425
 426         return err;
 427 }
 428
 429 int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
 430 {
 431         int err;
 432
 433         err = mlxsw_sp_port_headroom_init(mlxsw_sp_port);
 434         if (err)
 435                 return err;
 436         err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
 437         if (err)
 438                 return err;
 439         err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);
 440
 441         return err;
 442 }