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Merge branch 'tipc_net-next_v2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / net / ethernet / natsemi / natsemi.c
1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2 /*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
15
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
19 Annapolis MD 21403
20
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
23 [link no longer provides useful info -jgarzik]
24
25
26 TODO:
27 * big endian support with CFG:BEM instead of cpu_to_le32
28 */
29
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/string.h>
33 #include <linux/timer.h>
34 #include <linux/errno.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/init.h>
43 #include <linux/spinlock.h>
44 #include <linux/ethtool.h>
45 #include <linux/delay.h>
46 #include <linux/rtnetlink.h>
47 #include <linux/mii.h>
48 #include <linux/crc32.h>
49 #include <linux/bitops.h>
50 #include <linux/prefetch.h>
51 #include <asm/processor.h> /* Processor type for cache alignment. */
52 #include <asm/io.h>
53 #include <asm/irq.h>
54 #include <asm/uaccess.h>
55
56 #define DRV_NAME "natsemi"
57 #define DRV_VERSION "2.1"
58 #define DRV_RELDATE "Sept 11, 2006"
59
60 #define RX_OFFSET 2
61
62 /* Updated to recommendations in pci-skeleton v2.03. */
63
64 /* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
68 NETIF_MSG_LINK | \
69 NETIF_MSG_WOL | \
70 NETIF_MSG_RX_ERR | \
71 NETIF_MSG_TX_ERR)
72 static int debug = -1;
73
74 static int mtu;
75
76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
78 static const int multicast_filter_limit = 100;
79
80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82 static int rx_copybreak;
83
84 static int dspcfg_workaround = 1;
85
86 /* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
88 interoperability.
89 The media type is usually passed in 'options[]'.
90 */
91 #define MAX_UNITS 8 /* More are supported, limit only on options */
92 static int options[MAX_UNITS];
93 static int full_duplex[MAX_UNITS];
94
95 /* Operational parameters that are set at compile time. */
96
97 /* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102 #define TX_RING_SIZE 16
103 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104 #define RX_RING_SIZE 32
105
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (2*HZ)
109
110 #define NATSEMI_HW_TIMEOUT 400
111 #define NATSEMI_TIMER_FREQ 5*HZ
112 #define NATSEMI_PG0_NREGS 64
113 #define NATSEMI_RFDR_NREGS 8
114 #define NATSEMI_PG1_NREGS 4
115 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
116 NATSEMI_PG1_NREGS)
117 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
119
120 /* Buffer sizes:
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
123 */
124 #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125 #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126 #define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127 #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
128
129 /* These identify the driver base version and may not be removed. */
130 static const char version[] =
131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 " originally by Donald Becker <becker@scyld.com>\n"
134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
135
136 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138 MODULE_LICENSE("GPL");
139
140 module_param(mtu, int, 0);
141 module_param(debug, int, 0);
142 module_param(rx_copybreak, int, 0);
143 module_param(dspcfg_workaround, int, 0);
144 module_param_array(options, int, NULL, 0);
145 module_param_array(full_duplex, int, NULL, 0);
146 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147 MODULE_PARM_DESC(debug, "DP8381x default debug level");
148 MODULE_PARM_DESC(rx_copybreak,
149 "DP8381x copy breakpoint for copy-only-tiny-frames");
150 MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
151 MODULE_PARM_DESC(options,
152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
154
155 /*
156 Theory of Operation
157
158 I. Board Compatibility
159
160 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161 It also works with other chips in in the DP83810 series.
162
163 II. Board-specific settings
164
165 This driver requires the PCI interrupt line to be valid.
166 It honors the EEPROM-set values.
167
168 III. Driver operation
169
170 IIIa. Ring buffers
171
172 This driver uses two statically allocated fixed-size descriptor lists
173 formed into rings by a branch from the final descriptor to the beginning of
174 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175 The NatSemi design uses a 'next descriptor' pointer that the driver forms
176 into a list.
177
178 IIIb/c. Transmit/Receive Structure
179
180 This driver uses a zero-copy receive and transmit scheme.
181 The driver allocates full frame size skbuffs for the Rx ring buffers at
182 open() time and passes the skb->data field to the chip as receive data
183 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184 a fresh skbuff is allocated and the frame is copied to the new skbuff.
185 When the incoming frame is larger, the skbuff is passed directly up the
186 protocol stack. Buffers consumed this way are replaced by newly allocated
187 skbuffs in a later phase of receives.
188
189 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190 using a full-sized skbuff for small frames vs. the copying costs of larger
191 frames. New boards are typically used in generously configured machines
192 and the underfilled buffers have negligible impact compared to the benefit of
193 a single allocation size, so the default value of zero results in never
194 copying packets. When copying is done, the cost is usually mitigated by using
195 a combined copy/checksum routine. Copying also preloads the cache, which is
196 most useful with small frames.
197
198 A subtle aspect of the operation is that unaligned buffers are not permitted
199 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200 longword aligned for further processing. On copies frames are put into the
201 skbuff at an offset of "+2", 16-byte aligning the IP header.
202
203 IIId. Synchronization
204
205 Most operations are synchronized on the np->lock irq spinlock, except the
206 receive and transmit paths which are synchronised using a combination of
207 hardware descriptor ownership, disabling interrupts and NAPI poll scheduling.
208
209 IVb. References
210
211 http://www.scyld.com/expert/100mbps.html
212 http://www.scyld.com/expert/NWay.html
213 Datasheet is available from:
214 http://www.national.com/pf/DP/DP83815.html
215
216 IVc. Errata
217
218 None characterised.
219 */
220
221
222
223 /*
224 * Support for fibre connections on Am79C874:
225 * This phy needs a special setup when connected to a fibre cable.
226 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
227 */
228 #define PHYID_AM79C874 0x0022561b
229
230 enum {
231 MII_MCTRL = 0x15, /* mode control register */
232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
233 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
234 };
235
236 enum {
237 NATSEMI_FLAG_IGNORE_PHY = 0x1,
238 };
239
240 /* array of board data directly indexed by pci_tbl[x].driver_data */
241 static struct {
242 const char *name;
243 unsigned long flags;
244 unsigned int eeprom_size;
245 } natsemi_pci_info[] = {
246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
247 { "NatSemi DP8381[56]", 0, 24 },
248 };
249
250 static DEFINE_PCI_DEVICE_TABLE(natsemi_pci_tbl) = {
251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
253 { } /* terminate list */
254 };
255 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
256
257 /* Offsets to the device registers.
258 Unlike software-only systems, device drivers interact with complex hardware.
259 It's not useful to define symbolic names for every register bit in the
260 device.
261 */
262 enum register_offsets {
263 ChipCmd = 0x00,
264 ChipConfig = 0x04,
265 EECtrl = 0x08,
266 PCIBusCfg = 0x0C,
267 IntrStatus = 0x10,
268 IntrMask = 0x14,
269 IntrEnable = 0x18,
270 IntrHoldoff = 0x1C, /* DP83816 only */
271 TxRingPtr = 0x20,
272 TxConfig = 0x24,
273 RxRingPtr = 0x30,
274 RxConfig = 0x34,
275 ClkRun = 0x3C,
276 WOLCmd = 0x40,
277 PauseCmd = 0x44,
278 RxFilterAddr = 0x48,
279 RxFilterData = 0x4C,
280 BootRomAddr = 0x50,
281 BootRomData = 0x54,
282 SiliconRev = 0x58,
283 StatsCtrl = 0x5C,
284 StatsData = 0x60,
285 RxPktErrs = 0x60,
286 RxMissed = 0x68,
287 RxCRCErrs = 0x64,
288 BasicControl = 0x80,
289 BasicStatus = 0x84,
290 AnegAdv = 0x90,
291 AnegPeer = 0x94,
292 PhyStatus = 0xC0,
293 MIntrCtrl = 0xC4,
294 MIntrStatus = 0xC8,
295 PhyCtrl = 0xE4,
296
297 /* These are from the spec, around page 78... on a separate table.
298 * The meaning of these registers depend on the value of PGSEL. */
299 PGSEL = 0xCC,
300 PMDCSR = 0xE4,
301 TSTDAT = 0xFC,
302 DSPCFG = 0xF4,
303 SDCFG = 0xF8
304 };
305 /* the values for the 'magic' registers above (PGSEL=1) */
306 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
307 #define TSTDAT_VAL 0x0
308 #define DSPCFG_VAL 0x5040
309 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
310 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
311 #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
312 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
313
314 /* misc PCI space registers */
315 enum pci_register_offsets {
316 PCIPM = 0x44,
317 };
318
319 enum ChipCmd_bits {
320 ChipReset = 0x100,
321 RxReset = 0x20,
322 TxReset = 0x10,
323 RxOff = 0x08,
324 RxOn = 0x04,
325 TxOff = 0x02,
326 TxOn = 0x01,
327 };
328
329 enum ChipConfig_bits {
330 CfgPhyDis = 0x200,
331 CfgPhyRst = 0x400,
332 CfgExtPhy = 0x1000,
333 CfgAnegEnable = 0x2000,
334 CfgAneg100 = 0x4000,
335 CfgAnegFull = 0x8000,
336 CfgAnegDone = 0x8000000,
337 CfgFullDuplex = 0x20000000,
338 CfgSpeed100 = 0x40000000,
339 CfgLink = 0x80000000,
340 };
341
342 enum EECtrl_bits {
343 EE_ShiftClk = 0x04,
344 EE_DataIn = 0x01,
345 EE_ChipSelect = 0x08,
346 EE_DataOut = 0x02,
347 MII_Data = 0x10,
348 MII_Write = 0x20,
349 MII_ShiftClk = 0x40,
350 };
351
352 enum PCIBusCfg_bits {
353 EepromReload = 0x4,
354 };
355
356 /* Bits in the interrupt status/mask registers. */
357 enum IntrStatus_bits {
358 IntrRxDone = 0x0001,
359 IntrRxIntr = 0x0002,
360 IntrRxErr = 0x0004,
361 IntrRxEarly = 0x0008,
362 IntrRxIdle = 0x0010,
363 IntrRxOverrun = 0x0020,
364 IntrTxDone = 0x0040,
365 IntrTxIntr = 0x0080,
366 IntrTxErr = 0x0100,
367 IntrTxIdle = 0x0200,
368 IntrTxUnderrun = 0x0400,
369 StatsMax = 0x0800,
370 SWInt = 0x1000,
371 WOLPkt = 0x2000,
372 LinkChange = 0x4000,
373 IntrHighBits = 0x8000,
374 RxStatusFIFOOver = 0x10000,
375 IntrPCIErr = 0xf00000,
376 RxResetDone = 0x1000000,
377 TxResetDone = 0x2000000,
378 IntrAbnormalSummary = 0xCD20,
379 };
380
381 /*
382 * Default Interrupts:
383 * Rx OK, Rx Packet Error, Rx Overrun,
384 * Tx OK, Tx Packet Error, Tx Underrun,
385 * MIB Service, Phy Interrupt, High Bits,
386 * Rx Status FIFO overrun,
387 * Received Target Abort, Received Master Abort,
388 * Signalled System Error, Received Parity Error
389 */
390 #define DEFAULT_INTR 0x00f1cd65
391
392 enum TxConfig_bits {
393 TxDrthMask = 0x3f,
394 TxFlthMask = 0x3f00,
395 TxMxdmaMask = 0x700000,
396 TxMxdma_512 = 0x0,
397 TxMxdma_4 = 0x100000,
398 TxMxdma_8 = 0x200000,
399 TxMxdma_16 = 0x300000,
400 TxMxdma_32 = 0x400000,
401 TxMxdma_64 = 0x500000,
402 TxMxdma_128 = 0x600000,
403 TxMxdma_256 = 0x700000,
404 TxCollRetry = 0x800000,
405 TxAutoPad = 0x10000000,
406 TxMacLoop = 0x20000000,
407 TxHeartIgn = 0x40000000,
408 TxCarrierIgn = 0x80000000
409 };
410
411 /*
412 * Tx Configuration:
413 * - 256 byte DMA burst length
414 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
415 * - 64 bytes initial drain threshold (i.e. begin actual transmission
416 * when 64 byte are in the fifo)
417 * - on tx underruns, increase drain threshold by 64.
418 * - at most use a drain threshold of 1472 bytes: The sum of the fill
419 * threshold and the drain threshold must be less than 2016 bytes.
420 *
421 */
422 #define TX_FLTH_VAL ((512/32) << 8)
423 #define TX_DRTH_VAL_START (64/32)
424 #define TX_DRTH_VAL_INC 2
425 #define TX_DRTH_VAL_LIMIT (1472/32)
426
427 enum RxConfig_bits {
428 RxDrthMask = 0x3e,
429 RxMxdmaMask = 0x700000,
430 RxMxdma_512 = 0x0,
431 RxMxdma_4 = 0x100000,
432 RxMxdma_8 = 0x200000,
433 RxMxdma_16 = 0x300000,
434 RxMxdma_32 = 0x400000,
435 RxMxdma_64 = 0x500000,
436 RxMxdma_128 = 0x600000,
437 RxMxdma_256 = 0x700000,
438 RxAcceptLong = 0x8000000,
439 RxAcceptTx = 0x10000000,
440 RxAcceptRunt = 0x40000000,
441 RxAcceptErr = 0x80000000
442 };
443 #define RX_DRTH_VAL (128/8)
444
445 enum ClkRun_bits {
446 PMEEnable = 0x100,
447 PMEStatus = 0x8000,
448 };
449
450 enum WolCmd_bits {
451 WakePhy = 0x1,
452 WakeUnicast = 0x2,
453 WakeMulticast = 0x4,
454 WakeBroadcast = 0x8,
455 WakeArp = 0x10,
456 WakePMatch0 = 0x20,
457 WakePMatch1 = 0x40,
458 WakePMatch2 = 0x80,
459 WakePMatch3 = 0x100,
460 WakeMagic = 0x200,
461 WakeMagicSecure = 0x400,
462 SecureHack = 0x100000,
463 WokePhy = 0x400000,
464 WokeUnicast = 0x800000,
465 WokeMulticast = 0x1000000,
466 WokeBroadcast = 0x2000000,
467 WokeArp = 0x4000000,
468 WokePMatch0 = 0x8000000,
469 WokePMatch1 = 0x10000000,
470 WokePMatch2 = 0x20000000,
471 WokePMatch3 = 0x40000000,
472 WokeMagic = 0x80000000,
473 WakeOptsSummary = 0x7ff
474 };
475
476 enum RxFilterAddr_bits {
477 RFCRAddressMask = 0x3ff,
478 AcceptMulticast = 0x00200000,
479 AcceptMyPhys = 0x08000000,
480 AcceptAllPhys = 0x10000000,
481 AcceptAllMulticast = 0x20000000,
482 AcceptBroadcast = 0x40000000,
483 RxFilterEnable = 0x80000000
484 };
485
486 enum StatsCtrl_bits {
487 StatsWarn = 0x1,
488 StatsFreeze = 0x2,
489 StatsClear = 0x4,
490 StatsStrobe = 0x8,
491 };
492
493 enum MIntrCtrl_bits {
494 MICRIntEn = 0x2,
495 };
496
497 enum PhyCtrl_bits {
498 PhyAddrMask = 0x1f,
499 };
500
501 #define PHY_ADDR_NONE 32
502 #define PHY_ADDR_INTERNAL 1
503
504 /* values we might find in the silicon revision register */
505 #define SRR_DP83815_C 0x0302
506 #define SRR_DP83815_D 0x0403
507 #define SRR_DP83816_A4 0x0504
508 #define SRR_DP83816_A5 0x0505
509
510 /* The Rx and Tx buffer descriptors. */
511 /* Note that using only 32 bit fields simplifies conversion to big-endian
512 architectures. */
513 struct netdev_desc {
514 __le32 next_desc;
515 __le32 cmd_status;
516 __le32 addr;
517 __le32 software_use;
518 };
519
520 /* Bits in network_desc.status */
521 enum desc_status_bits {
522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
523 DescNoCRC=0x10000000, DescPktOK=0x08000000,
524 DescSizeMask=0xfff,
525
526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
530
531 DescRxAbort=0x04000000, DescRxOver=0x02000000,
532 DescRxDest=0x01800000, DescRxLong=0x00400000,
533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
534 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
535 DescRxLoop=0x00020000, DesRxColl=0x00010000,
536 };
537
538 struct netdev_private {
539 /* Descriptor rings first for alignment */
540 dma_addr_t ring_dma;
541 struct netdev_desc *rx_ring;
542 struct netdev_desc *tx_ring;
543 /* The addresses of receive-in-place skbuffs */
544 struct sk_buff *rx_skbuff[RX_RING_SIZE];
545 dma_addr_t rx_dma[RX_RING_SIZE];
546 /* address of a sent-in-place packet/buffer, for later free() */
547 struct sk_buff *tx_skbuff[TX_RING_SIZE];
548 dma_addr_t tx_dma[TX_RING_SIZE];
549 struct net_device *dev;
550 void __iomem *ioaddr;
551 struct napi_struct napi;
552 /* Media monitoring timer */
553 struct timer_list timer;
554 /* Frequently used values: keep some adjacent for cache effect */
555 struct pci_dev *pci_dev;
556 struct netdev_desc *rx_head_desc;
557 /* Producer/consumer ring indices */
558 unsigned int cur_rx, dirty_rx;
559 unsigned int cur_tx, dirty_tx;
560 /* Based on MTU+slack. */
561 unsigned int rx_buf_sz;
562 int oom;
563 /* Interrupt status */
564 u32 intr_status;
565 /* Do not touch the nic registers */
566 int hands_off;
567 /* Don't pay attention to the reported link state. */
568 int ignore_phy;
569 /* external phy that is used: only valid if dev->if_port != PORT_TP */
570 int mii;
571 int phy_addr_external;
572 unsigned int full_duplex;
573 /* Rx filter */
574 u32 cur_rx_mode;
575 u32 rx_filter[16];
576 /* FIFO and PCI burst thresholds */
577 u32 tx_config, rx_config;
578 /* original contents of ClkRun register */
579 u32 SavedClkRun;
580 /* silicon revision */
581 u32 srr;
582 /* expected DSPCFG value */
583 u16 dspcfg;
584 int dspcfg_workaround;
585 /* parms saved in ethtool format */
586 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
587 u8 duplex; /* Duplex, half or full */
588 u8 autoneg; /* Autonegotiation enabled */
589 /* MII transceiver section */
590 u16 advertising;
591 unsigned int iosize;
592 spinlock_t lock;
593 u32 msg_enable;
594 /* EEPROM data */
595 int eeprom_size;
596 };
597
598 static void move_int_phy(struct net_device *dev, int addr);
599 static int eeprom_read(void __iomem *ioaddr, int location);
600 static int mdio_read(struct net_device *dev, int reg);
601 static void mdio_write(struct net_device *dev, int reg, u16 data);
602 static void init_phy_fixup(struct net_device *dev);
603 static int miiport_read(struct net_device *dev, int phy_id, int reg);
604 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
605 static int find_mii(struct net_device *dev);
606 static void natsemi_reset(struct net_device *dev);
607 static void natsemi_reload_eeprom(struct net_device *dev);
608 static void natsemi_stop_rxtx(struct net_device *dev);
609 static int netdev_open(struct net_device *dev);
610 static void do_cable_magic(struct net_device *dev);
611 static void undo_cable_magic(struct net_device *dev);
612 static void check_link(struct net_device *dev);
613 static void netdev_timer(unsigned long data);
614 static void dump_ring(struct net_device *dev);
615 static void ns_tx_timeout(struct net_device *dev);
616 static int alloc_ring(struct net_device *dev);
617 static void refill_rx(struct net_device *dev);
618 static void init_ring(struct net_device *dev);
619 static void drain_tx(struct net_device *dev);
620 static void drain_ring(struct net_device *dev);
621 static void free_ring(struct net_device *dev);
622 static void reinit_ring(struct net_device *dev);
623 static void init_registers(struct net_device *dev);
624 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
625 static irqreturn_t intr_handler(int irq, void *dev_instance);
626 static void netdev_error(struct net_device *dev, int intr_status);
627 static int natsemi_poll(struct napi_struct *napi, int budget);
628 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
629 static void netdev_tx_done(struct net_device *dev);
630 static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
631 #ifdef CONFIG_NET_POLL_CONTROLLER
632 static void natsemi_poll_controller(struct net_device *dev);
633 #endif
634 static void __set_rx_mode(struct net_device *dev);
635 static void set_rx_mode(struct net_device *dev);
636 static void __get_stats(struct net_device *dev);
637 static struct net_device_stats *get_stats(struct net_device *dev);
638 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
639 static int netdev_set_wol(struct net_device *dev, u32 newval);
640 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
641 static int netdev_set_sopass(struct net_device *dev, u8 *newval);
642 static int netdev_get_sopass(struct net_device *dev, u8 *data);
643 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
644 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
645 static void enable_wol_mode(struct net_device *dev, int enable_intr);
646 static int netdev_close(struct net_device *dev);
647 static int netdev_get_regs(struct net_device *dev, u8 *buf);
648 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
649 static const struct ethtool_ops ethtool_ops;
650
651 #define NATSEMI_ATTR(_name) \
652 static ssize_t natsemi_show_##_name(struct device *dev, \
653 struct device_attribute *attr, char *buf); \
654 static ssize_t natsemi_set_##_name(struct device *dev, \
655 struct device_attribute *attr, \
656 const char *buf, size_t count); \
657 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
658
659 #define NATSEMI_CREATE_FILE(_dev, _name) \
660 device_create_file(&_dev->dev, &dev_attr_##_name)
661 #define NATSEMI_REMOVE_FILE(_dev, _name) \
662 device_remove_file(&_dev->dev, &dev_attr_##_name)
663
664 NATSEMI_ATTR(dspcfg_workaround);
665
666 static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
667 struct device_attribute *attr,
668 char *buf)
669 {
670 struct netdev_private *np = netdev_priv(to_net_dev(dev));
671
672 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
673 }
674
675 static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
676 struct device_attribute *attr,
677 const char *buf, size_t count)
678 {
679 struct netdev_private *np = netdev_priv(to_net_dev(dev));
680 int new_setting;
681 unsigned long flags;
682
683 /* Find out the new setting */
684 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
685 new_setting = 1;
686 else if (!strncmp("off", buf, count - 1) ||
687 !strncmp("0", buf, count - 1))
688 new_setting = 0;
689 else
690 return count;
691
692 spin_lock_irqsave(&np->lock, flags);
693
694 np->dspcfg_workaround = new_setting;
695
696 spin_unlock_irqrestore(&np->lock, flags);
697
698 return count;
699 }
700
701 static inline void __iomem *ns_ioaddr(struct net_device *dev)
702 {
703 struct netdev_private *np = netdev_priv(dev);
704
705 return np->ioaddr;
706 }
707
708 static inline void natsemi_irq_enable(struct net_device *dev)
709 {
710 writel(1, ns_ioaddr(dev) + IntrEnable);
711 readl(ns_ioaddr(dev) + IntrEnable);
712 }
713
714 static inline void natsemi_irq_disable(struct net_device *dev)
715 {
716 writel(0, ns_ioaddr(dev) + IntrEnable);
717 readl(ns_ioaddr(dev) + IntrEnable);
718 }
719
720 static void move_int_phy(struct net_device *dev, int addr)
721 {
722 struct netdev_private *np = netdev_priv(dev);
723 void __iomem *ioaddr = ns_ioaddr(dev);
724 int target = 31;
725
726 /*
727 * The internal phy is visible on the external mii bus. Therefore we must
728 * move it away before we can send commands to an external phy.
729 * There are two addresses we must avoid:
730 * - the address on the external phy that is used for transmission.
731 * - the address that we want to access. User space can access phys
732 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independent from the
733 * phy that is used for transmission.
734 */
735
736 if (target == addr)
737 target--;
738 if (target == np->phy_addr_external)
739 target--;
740 writew(target, ioaddr + PhyCtrl);
741 readw(ioaddr + PhyCtrl);
742 udelay(1);
743 }
744
745 static void natsemi_init_media(struct net_device *dev)
746 {
747 struct netdev_private *np = netdev_priv(dev);
748 u32 tmp;
749
750 if (np->ignore_phy)
751 netif_carrier_on(dev);
752 else
753 netif_carrier_off(dev);
754
755 /* get the initial settings from hardware */
756 tmp = mdio_read(dev, MII_BMCR);
757 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
758 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
759 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
760 np->advertising= mdio_read(dev, MII_ADVERTISE);
761
762 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL &&
763 netif_msg_probe(np)) {
764 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
765 "10%s %s duplex.\n",
766 pci_name(np->pci_dev),
767 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
768 "enabled, advertise" : "disabled, force",
769 (np->advertising &
770 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
771 "0" : "",
772 (np->advertising &
773 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
774 "full" : "half");
775 }
776 if (netif_msg_probe(np))
777 printk(KERN_INFO
778 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
779 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
780 np->advertising);
781
782 }
783
784 static const struct net_device_ops natsemi_netdev_ops = {
785 .ndo_open = netdev_open,
786 .ndo_stop = netdev_close,
787 .ndo_start_xmit = start_tx,
788 .ndo_get_stats = get_stats,
789 .ndo_set_rx_mode = set_rx_mode,
790 .ndo_change_mtu = natsemi_change_mtu,
791 .ndo_do_ioctl = netdev_ioctl,
792 .ndo_tx_timeout = ns_tx_timeout,
793 .ndo_set_mac_address = eth_mac_addr,
794 .ndo_validate_addr = eth_validate_addr,
795 #ifdef CONFIG_NET_POLL_CONTROLLER
796 .ndo_poll_controller = natsemi_poll_controller,
797 #endif
798 };
799
800 static int natsemi_probe1(struct pci_dev *pdev, const struct pci_device_id *ent)
801 {
802 struct net_device *dev;
803 struct netdev_private *np;
804 int i, option, irq, chip_idx = ent->driver_data;
805 static int find_cnt = -1;
806 resource_size_t iostart;
807 unsigned long iosize;
808 void __iomem *ioaddr;
809 const int pcibar = 1; /* PCI base address register */
810 int prev_eedata;
811 u32 tmp;
812
813 /* when built into the kernel, we only print version if device is found */
814 #ifndef MODULE
815 static int printed_version;
816 if (!printed_version++)
817 printk(version);
818 #endif
819
820 i = pci_enable_device(pdev);
821 if (i) return i;
822
823 /* natsemi has a non-standard PM control register
824 * in PCI config space. Some boards apparently need
825 * to be brought to D0 in this manner.
826 */
827 pci_read_config_dword(pdev, PCIPM, &tmp);
828 if (tmp & PCI_PM_CTRL_STATE_MASK) {
829 /* D0 state, disable PME assertion */
830 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
831 pci_write_config_dword(pdev, PCIPM, newtmp);
832 }
833
834 find_cnt++;
835 iostart = pci_resource_start(pdev, pcibar);
836 iosize = pci_resource_len(pdev, pcibar);
837 irq = pdev->irq;
838
839 pci_set_master(pdev);
840
841 dev = alloc_etherdev(sizeof (struct netdev_private));
842 if (!dev)
843 return -ENOMEM;
844 SET_NETDEV_DEV(dev, &pdev->dev);
845
846 i = pci_request_regions(pdev, DRV_NAME);
847 if (i)
848 goto err_pci_request_regions;
849
850 ioaddr = ioremap(iostart, iosize);
851 if (!ioaddr) {
852 i = -ENOMEM;
853 goto err_ioremap;
854 }
855
856 /* Work around the dropped serial bit. */
857 prev_eedata = eeprom_read(ioaddr, 6);
858 for (i = 0; i < 3; i++) {
859 int eedata = eeprom_read(ioaddr, i + 7);
860 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
861 dev->dev_addr[i*2+1] = eedata >> 7;
862 prev_eedata = eedata;
863 }
864
865 /* Store MAC Address in perm_addr */
866 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
867
868 np = netdev_priv(dev);
869 np->ioaddr = ioaddr;
870
871 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
872 np->dev = dev;
873
874 np->pci_dev = pdev;
875 pci_set_drvdata(pdev, dev);
876 np->iosize = iosize;
877 spin_lock_init(&np->lock);
878 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
879 np->hands_off = 0;
880 np->intr_status = 0;
881 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
882 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
883 np->ignore_phy = 1;
884 else
885 np->ignore_phy = 0;
886 np->dspcfg_workaround = dspcfg_workaround;
887
888 /* Initial port:
889 * - If configured to ignore the PHY set up for external.
890 * - If the nic was configured to use an external phy and if find_mii
891 * finds a phy: use external port, first phy that replies.
892 * - Otherwise: internal port.
893 * Note that the phy address for the internal phy doesn't matter:
894 * The address would be used to access a phy over the mii bus, but
895 * the internal phy is accessed through mapped registers.
896 */
897 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
898 dev->if_port = PORT_MII;
899 else
900 dev->if_port = PORT_TP;
901 /* Reset the chip to erase previous misconfiguration. */
902 natsemi_reload_eeprom(dev);
903 natsemi_reset(dev);
904
905 if (dev->if_port != PORT_TP) {
906 np->phy_addr_external = find_mii(dev);
907 /* If we're ignoring the PHY it doesn't matter if we can't
908 * find one. */
909 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
910 dev->if_port = PORT_TP;
911 np->phy_addr_external = PHY_ADDR_INTERNAL;
912 }
913 } else {
914 np->phy_addr_external = PHY_ADDR_INTERNAL;
915 }
916
917 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
918 /* The lower four bits are the media type. */
919 if (option) {
920 if (option & 0x200)
921 np->full_duplex = 1;
922 if (option & 15)
923 printk(KERN_INFO
924 "natsemi %s: ignoring user supplied media type %d",
925 pci_name(np->pci_dev), option & 15);
926 }
927 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
928 np->full_duplex = 1;
929
930 dev->netdev_ops = &natsemi_netdev_ops;
931 dev->watchdog_timeo = TX_TIMEOUT;
932
933 SET_ETHTOOL_OPS(dev, &ethtool_ops);
934
935 if (mtu)
936 dev->mtu = mtu;
937
938 natsemi_init_media(dev);
939
940 /* save the silicon revision for later querying */
941 np->srr = readl(ioaddr + SiliconRev);
942 if (netif_msg_hw(np))
943 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
944 pci_name(np->pci_dev), np->srr);
945
946 i = register_netdev(dev);
947 if (i)
948 goto err_register_netdev;
949 i = NATSEMI_CREATE_FILE(pdev, dspcfg_workaround);
950 if (i)
951 goto err_create_file;
952
953 if (netif_msg_drv(np)) {
954 printk(KERN_INFO "natsemi %s: %s at %#08llx "
955 "(%s), %pM, IRQ %d",
956 dev->name, natsemi_pci_info[chip_idx].name,
957 (unsigned long long)iostart, pci_name(np->pci_dev),
958 dev->dev_addr, irq);
959 if (dev->if_port == PORT_TP)
960 printk(", port TP.\n");
961 else if (np->ignore_phy)
962 printk(", port MII, ignoring PHY\n");
963 else
964 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
965 }
966 return 0;
967
968 err_create_file:
969 unregister_netdev(dev);
970
971 err_register_netdev:
972 iounmap(ioaddr);
973
974 err_ioremap:
975 pci_release_regions(pdev);
976 pci_set_drvdata(pdev, NULL);
977
978 err_pci_request_regions:
979 free_netdev(dev);
980 return i;
981 }
982
983
984 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
985 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
986
987 /* Delay between EEPROM clock transitions.
988 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
989 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
990 made udelay() unreliable.
991 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
992 deprecated.
993 */
994 #define eeprom_delay(ee_addr) readl(ee_addr)
995
996 #define EE_Write0 (EE_ChipSelect)
997 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
998
999 /* The EEPROM commands include the alway-set leading bit. */
1000 enum EEPROM_Cmds {
1001 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1002 };
1003
1004 static int eeprom_read(void __iomem *addr, int location)
1005 {
1006 int i;
1007 int retval = 0;
1008 void __iomem *ee_addr = addr + EECtrl;
1009 int read_cmd = location | EE_ReadCmd;
1010
1011 writel(EE_Write0, ee_addr);
1012
1013 /* Shift the read command bits out. */
1014 for (i = 10; i >= 0; i--) {
1015 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1016 writel(dataval, ee_addr);
1017 eeprom_delay(ee_addr);
1018 writel(dataval | EE_ShiftClk, ee_addr);
1019 eeprom_delay(ee_addr);
1020 }
1021 writel(EE_ChipSelect, ee_addr);
1022 eeprom_delay(ee_addr);
1023
1024 for (i = 0; i < 16; i++) {
1025 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1026 eeprom_delay(ee_addr);
1027 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1028 writel(EE_ChipSelect, ee_addr);
1029 eeprom_delay(ee_addr);
1030 }
1031
1032 /* Terminate the EEPROM access. */
1033 writel(EE_Write0, ee_addr);
1034 writel(0, ee_addr);
1035 return retval;
1036 }
1037
1038 /* MII transceiver control section.
1039 * The 83815 series has an internal transceiver, and we present the
1040 * internal management registers as if they were MII connected.
1041 * External Phy registers are referenced through the MII interface.
1042 */
1043
1044 /* clock transitions >= 20ns (25MHz)
1045 * One readl should be good to PCI @ 100MHz
1046 */
1047 #define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1048
1049 static int mii_getbit (struct net_device *dev)
1050 {
1051 int data;
1052 void __iomem *ioaddr = ns_ioaddr(dev);
1053
1054 writel(MII_ShiftClk, ioaddr + EECtrl);
1055 data = readl(ioaddr + EECtrl);
1056 writel(0, ioaddr + EECtrl);
1057 mii_delay(ioaddr);
1058 return (data & MII_Data)? 1 : 0;
1059 }
1060
1061 static void mii_send_bits (struct net_device *dev, u32 data, int len)
1062 {
1063 u32 i;
1064 void __iomem *ioaddr = ns_ioaddr(dev);
1065
1066 for (i = (1 << (len-1)); i; i >>= 1)
1067 {
1068 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1069 writel(mdio_val, ioaddr + EECtrl);
1070 mii_delay(ioaddr);
1071 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1072 mii_delay(ioaddr);
1073 }
1074 writel(0, ioaddr + EECtrl);
1075 mii_delay(ioaddr);
1076 }
1077
1078 static int miiport_read(struct net_device *dev, int phy_id, int reg)
1079 {
1080 u32 cmd;
1081 int i;
1082 u32 retval = 0;
1083
1084 /* Ensure sync */
1085 mii_send_bits (dev, 0xffffffff, 32);
1086 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1087 /* ST,OP = 0110'b for read operation */
1088 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1089 mii_send_bits (dev, cmd, 14);
1090 /* Turnaround */
1091 if (mii_getbit (dev))
1092 return 0;
1093 /* Read data */
1094 for (i = 0; i < 16; i++) {
1095 retval <<= 1;
1096 retval |= mii_getbit (dev);
1097 }
1098 /* End cycle */
1099 mii_getbit (dev);
1100 return retval;
1101 }
1102
1103 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1104 {
1105 u32 cmd;
1106
1107 /* Ensure sync */
1108 mii_send_bits (dev, 0xffffffff, 32);
1109 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1110 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1111 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1112 mii_send_bits (dev, cmd, 32);
1113 /* End cycle */
1114 mii_getbit (dev);
1115 }
1116
1117 static int mdio_read(struct net_device *dev, int reg)
1118 {
1119 struct netdev_private *np = netdev_priv(dev);
1120 void __iomem *ioaddr = ns_ioaddr(dev);
1121
1122 /* The 83815 series has two ports:
1123 * - an internal transceiver
1124 * - an external mii bus
1125 */
1126 if (dev->if_port == PORT_TP)
1127 return readw(ioaddr+BasicControl+(reg<<2));
1128 else
1129 return miiport_read(dev, np->phy_addr_external, reg);
1130 }
1131
1132 static void mdio_write(struct net_device *dev, int reg, u16 data)
1133 {
1134 struct netdev_private *np = netdev_priv(dev);
1135 void __iomem *ioaddr = ns_ioaddr(dev);
1136
1137 /* The 83815 series has an internal transceiver; handle separately */
1138 if (dev->if_port == PORT_TP)
1139 writew(data, ioaddr+BasicControl+(reg<<2));
1140 else
1141 miiport_write(dev, np->phy_addr_external, reg, data);
1142 }
1143
1144 static void init_phy_fixup(struct net_device *dev)
1145 {
1146 struct netdev_private *np = netdev_priv(dev);
1147 void __iomem *ioaddr = ns_ioaddr(dev);
1148 int i;
1149 u32 cfg;
1150 u16 tmp;
1151
1152 /* restore stuff lost when power was out */
1153 tmp = mdio_read(dev, MII_BMCR);
1154 if (np->autoneg == AUTONEG_ENABLE) {
1155 /* renegotiate if something changed */
1156 if ((tmp & BMCR_ANENABLE) == 0 ||
1157 np->advertising != mdio_read(dev, MII_ADVERTISE))
1158 {
1159 /* turn on autonegotiation and force negotiation */
1160 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1161 mdio_write(dev, MII_ADVERTISE, np->advertising);
1162 }
1163 } else {
1164 /* turn off auto negotiation, set speed and duplexity */
1165 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1166 if (np->speed == SPEED_100)
1167 tmp |= BMCR_SPEED100;
1168 if (np->duplex == DUPLEX_FULL)
1169 tmp |= BMCR_FULLDPLX;
1170 /*
1171 * Note: there is no good way to inform the link partner
1172 * that our capabilities changed. The user has to unplug
1173 * and replug the network cable after some changes, e.g.
1174 * after switching from 10HD, autoneg off to 100 HD,
1175 * autoneg off.
1176 */
1177 }
1178 mdio_write(dev, MII_BMCR, tmp);
1179 readl(ioaddr + ChipConfig);
1180 udelay(1);
1181
1182 /* find out what phy this is */
1183 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1184 + mdio_read(dev, MII_PHYSID2);
1185
1186 /* handle external phys here */
1187 switch (np->mii) {
1188 case PHYID_AM79C874:
1189 /* phy specific configuration for fibre/tp operation */
1190 tmp = mdio_read(dev, MII_MCTRL);
1191 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1192 if (dev->if_port == PORT_FIBRE)
1193 tmp |= MII_FX_SEL;
1194 else
1195 tmp |= MII_EN_SCRM;
1196 mdio_write(dev, MII_MCTRL, tmp);
1197 break;
1198 default:
1199 break;
1200 }
1201 cfg = readl(ioaddr + ChipConfig);
1202 if (cfg & CfgExtPhy)
1203 return;
1204
1205 /* On page 78 of the spec, they recommend some settings for "optimum
1206 performance" to be done in sequence. These settings optimize some
1207 of the 100Mbit autodetection circuitry. They say we only want to
1208 do this for rev C of the chip, but engineers at NSC (Bradley
1209 Kennedy) recommends always setting them. If you don't, you get
1210 errors on some autonegotiations that make the device unusable.
1211
1212 It seems that the DSP needs a few usec to reinitialize after
1213 the start of the phy. Just retry writing these values until they
1214 stick.
1215 */
1216 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1217
1218 int dspcfg;
1219 writew(1, ioaddr + PGSEL);
1220 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1221 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1222 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1223 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1224 writew(np->dspcfg, ioaddr + DSPCFG);
1225 writew(SDCFG_VAL, ioaddr + SDCFG);
1226 writew(0, ioaddr + PGSEL);
1227 readl(ioaddr + ChipConfig);
1228 udelay(10);
1229
1230 writew(1, ioaddr + PGSEL);
1231 dspcfg = readw(ioaddr + DSPCFG);
1232 writew(0, ioaddr + PGSEL);
1233 if (np->dspcfg == dspcfg)
1234 break;
1235 }
1236
1237 if (netif_msg_link(np)) {
1238 if (i==NATSEMI_HW_TIMEOUT) {
1239 printk(KERN_INFO
1240 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1241 dev->name, i*10);
1242 } else {
1243 printk(KERN_INFO
1244 "%s: DSPCFG accepted after %d usec.\n",
1245 dev->name, i*10);
1246 }
1247 }
1248 /*
1249 * Enable PHY Specific event based interrupts. Link state change
1250 * and Auto-Negotiation Completion are among the affected.
1251 * Read the intr status to clear it (needed for wake events).
1252 */
1253 readw(ioaddr + MIntrStatus);
1254 writew(MICRIntEn, ioaddr + MIntrCtrl);
1255 }
1256
1257 static int switch_port_external(struct net_device *dev)
1258 {
1259 struct netdev_private *np = netdev_priv(dev);
1260 void __iomem *ioaddr = ns_ioaddr(dev);
1261 u32 cfg;
1262
1263 cfg = readl(ioaddr + ChipConfig);
1264 if (cfg & CfgExtPhy)
1265 return 0;
1266
1267 if (netif_msg_link(np)) {
1268 printk(KERN_INFO "%s: switching to external transceiver.\n",
1269 dev->name);
1270 }
1271
1272 /* 1) switch back to external phy */
1273 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1274 readl(ioaddr + ChipConfig);
1275 udelay(1);
1276
1277 /* 2) reset the external phy: */
1278 /* resetting the external PHY has been known to cause a hub supplying
1279 * power over Ethernet to kill the power. We don't want to kill
1280 * power to this computer, so we avoid resetting the phy.
1281 */
1282
1283 /* 3) reinit the phy fixup, it got lost during power down. */
1284 move_int_phy(dev, np->phy_addr_external);
1285 init_phy_fixup(dev);
1286
1287 return 1;
1288 }
1289
1290 static int switch_port_internal(struct net_device *dev)
1291 {
1292 struct netdev_private *np = netdev_priv(dev);
1293 void __iomem *ioaddr = ns_ioaddr(dev);
1294 int i;
1295 u32 cfg;
1296 u16 bmcr;
1297
1298 cfg = readl(ioaddr + ChipConfig);
1299 if (!(cfg &CfgExtPhy))
1300 return 0;
1301
1302 if (netif_msg_link(np)) {
1303 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1304 dev->name);
1305 }
1306 /* 1) switch back to internal phy: */
1307 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1308 writel(cfg, ioaddr + ChipConfig);
1309 readl(ioaddr + ChipConfig);
1310 udelay(1);
1311
1312 /* 2) reset the internal phy: */
1313 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1314 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1315 readl(ioaddr + ChipConfig);
1316 udelay(10);
1317 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1318 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1319 if (!(bmcr & BMCR_RESET))
1320 break;
1321 udelay(10);
1322 }
1323 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1324 printk(KERN_INFO
1325 "%s: phy reset did not complete in %d usec.\n",
1326 dev->name, i*10);
1327 }
1328 /* 3) reinit the phy fixup, it got lost during power down. */
1329 init_phy_fixup(dev);
1330
1331 return 1;
1332 }
1333
1334 /* Scan for a PHY on the external mii bus.
1335 * There are two tricky points:
1336 * - Do not scan while the internal phy is enabled. The internal phy will
1337 * crash: e.g. reads from the DSPCFG register will return odd values and
1338 * the nasty random phy reset code will reset the nic every few seconds.
1339 * - The internal phy must be moved around, an external phy could
1340 * have the same address as the internal phy.
1341 */
1342 static int find_mii(struct net_device *dev)
1343 {
1344 struct netdev_private *np = netdev_priv(dev);
1345 int tmp;
1346 int i;
1347 int did_switch;
1348
1349 /* Switch to external phy */
1350 did_switch = switch_port_external(dev);
1351
1352 /* Scan the possible phy addresses:
1353 *
1354 * PHY address 0 means that the phy is in isolate mode. Not yet
1355 * supported due to lack of test hardware. User space should
1356 * handle it through ethtool.
1357 */
1358 for (i = 1; i <= 31; i++) {
1359 move_int_phy(dev, i);
1360 tmp = miiport_read(dev, i, MII_BMSR);
1361 if (tmp != 0xffff && tmp != 0x0000) {
1362 /* found something! */
1363 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1364 + mdio_read(dev, MII_PHYSID2);
1365 if (netif_msg_probe(np)) {
1366 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1367 pci_name(np->pci_dev), np->mii, i);
1368 }
1369 break;
1370 }
1371 }
1372 /* And switch back to internal phy: */
1373 if (did_switch)
1374 switch_port_internal(dev);
1375 return i;
1376 }
1377
1378 /* CFG bits [13:16] [18:23] */
1379 #define CFG_RESET_SAVE 0xfde000
1380 /* WCSR bits [0:4] [9:10] */
1381 #define WCSR_RESET_SAVE 0x61f
1382 /* RFCR bits [20] [22] [27:31] */
1383 #define RFCR_RESET_SAVE 0xf8500000
1384
1385 static void natsemi_reset(struct net_device *dev)
1386 {
1387 int i;
1388 u32 cfg;
1389 u32 wcsr;
1390 u32 rfcr;
1391 u16 pmatch[3];
1392 u16 sopass[3];
1393 struct netdev_private *np = netdev_priv(dev);
1394 void __iomem *ioaddr = ns_ioaddr(dev);
1395
1396 /*
1397 * Resetting the chip causes some registers to be lost.
1398 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1399 * we save the state that would have been loaded from EEPROM
1400 * on a normal power-up (see the spec EEPROM map). This assumes
1401 * whoever calls this will follow up with init_registers() eventually.
1402 */
1403
1404 /* CFG */
1405 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1406 /* WCSR */
1407 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1408 /* RFCR */
1409 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1410 /* PMATCH */
1411 for (i = 0; i < 3; i++) {
1412 writel(i*2, ioaddr + RxFilterAddr);
1413 pmatch[i] = readw(ioaddr + RxFilterData);
1414 }
1415 /* SOPAS */
1416 for (i = 0; i < 3; i++) {
1417 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1418 sopass[i] = readw(ioaddr + RxFilterData);
1419 }
1420
1421 /* now whack the chip */
1422 writel(ChipReset, ioaddr + ChipCmd);
1423 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1424 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1425 break;
1426 udelay(5);
1427 }
1428 if (i==NATSEMI_HW_TIMEOUT) {
1429 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1430 dev->name, i*5);
1431 } else if (netif_msg_hw(np)) {
1432 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1433 dev->name, i*5);
1434 }
1435
1436 /* restore CFG */
1437 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1438 /* turn on external phy if it was selected */
1439 if (dev->if_port == PORT_TP)
1440 cfg &= ~(CfgExtPhy | CfgPhyDis);
1441 else
1442 cfg |= (CfgExtPhy | CfgPhyDis);
1443 writel(cfg, ioaddr + ChipConfig);
1444 /* restore WCSR */
1445 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1446 writel(wcsr, ioaddr + WOLCmd);
1447 /* read RFCR */
1448 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1449 /* restore PMATCH */
1450 for (i = 0; i < 3; i++) {
1451 writel(i*2, ioaddr + RxFilterAddr);
1452 writew(pmatch[i], ioaddr + RxFilterData);
1453 }
1454 for (i = 0; i < 3; i++) {
1455 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1456 writew(sopass[i], ioaddr + RxFilterData);
1457 }
1458 /* restore RFCR */
1459 writel(rfcr, ioaddr + RxFilterAddr);
1460 }
1461
1462 static void reset_rx(struct net_device *dev)
1463 {
1464 int i;
1465 struct netdev_private *np = netdev_priv(dev);
1466 void __iomem *ioaddr = ns_ioaddr(dev);
1467
1468 np->intr_status &= ~RxResetDone;
1469
1470 writel(RxReset, ioaddr + ChipCmd);
1471
1472 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1473 np->intr_status |= readl(ioaddr + IntrStatus);
1474 if (np->intr_status & RxResetDone)
1475 break;
1476 udelay(15);
1477 }
1478 if (i==NATSEMI_HW_TIMEOUT) {
1479 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1480 dev->name, i*15);
1481 } else if (netif_msg_hw(np)) {
1482 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1483 dev->name, i*15);
1484 }
1485 }
1486
1487 static void natsemi_reload_eeprom(struct net_device *dev)
1488 {
1489 struct netdev_private *np = netdev_priv(dev);
1490 void __iomem *ioaddr = ns_ioaddr(dev);
1491 int i;
1492
1493 writel(EepromReload, ioaddr + PCIBusCfg);
1494 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1495 udelay(50);
1496 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1497 break;
1498 }
1499 if (i==NATSEMI_HW_TIMEOUT) {
1500 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1501 pci_name(np->pci_dev), i*50);
1502 } else if (netif_msg_hw(np)) {
1503 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1504 pci_name(np->pci_dev), i*50);
1505 }
1506 }
1507
1508 static void natsemi_stop_rxtx(struct net_device *dev)
1509 {
1510 void __iomem * ioaddr = ns_ioaddr(dev);
1511 struct netdev_private *np = netdev_priv(dev);
1512 int i;
1513
1514 writel(RxOff | TxOff, ioaddr + ChipCmd);
1515 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1516 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1517 break;
1518 udelay(5);
1519 }
1520 if (i==NATSEMI_HW_TIMEOUT) {
1521 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1522 dev->name, i*5);
1523 } else if (netif_msg_hw(np)) {
1524 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1525 dev->name, i*5);
1526 }
1527 }
1528
1529 static int netdev_open(struct net_device *dev)
1530 {
1531 struct netdev_private *np = netdev_priv(dev);
1532 void __iomem * ioaddr = ns_ioaddr(dev);
1533 const int irq = np->pci_dev->irq;
1534 int i;
1535
1536 /* Reset the chip, just in case. */
1537 natsemi_reset(dev);
1538
1539 i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
1540 if (i) return i;
1541
1542 if (netif_msg_ifup(np))
1543 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1544 dev->name, irq);
1545 i = alloc_ring(dev);
1546 if (i < 0) {
1547 free_irq(irq, dev);
1548 return i;
1549 }
1550 napi_enable(&np->napi);
1551
1552 init_ring(dev);
1553 spin_lock_irq(&np->lock);
1554 init_registers(dev);
1555 /* now set the MAC address according to dev->dev_addr */
1556 for (i = 0; i < 3; i++) {
1557 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1558
1559 writel(i*2, ioaddr + RxFilterAddr);
1560 writew(mac, ioaddr + RxFilterData);
1561 }
1562 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1563 spin_unlock_irq(&np->lock);
1564
1565 netif_start_queue(dev);
1566
1567 if (netif_msg_ifup(np))
1568 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1569 dev->name, (int)readl(ioaddr + ChipCmd));
1570
1571 /* Set the timer to check for link beat. */
1572 init_timer(&np->timer);
1573 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ);
1574 np->timer.data = (unsigned long)dev;
1575 np->timer.function = netdev_timer; /* timer handler */
1576 add_timer(&np->timer);
1577
1578 return 0;
1579 }
1580
1581 static void do_cable_magic(struct net_device *dev)
1582 {
1583 struct netdev_private *np = netdev_priv(dev);
1584 void __iomem *ioaddr = ns_ioaddr(dev);
1585
1586 if (dev->if_port != PORT_TP)
1587 return;
1588
1589 if (np->srr >= SRR_DP83816_A5)
1590 return;
1591
1592 /*
1593 * 100 MBit links with short cables can trip an issue with the chip.
1594 * The problem manifests as lots of CRC errors and/or flickering
1595 * activity LED while idle. This process is based on instructions
1596 * from engineers at National.
1597 */
1598 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1599 u16 data;
1600
1601 writew(1, ioaddr + PGSEL);
1602 /*
1603 * coefficient visibility should already be enabled via
1604 * DSPCFG | 0x1000
1605 */
1606 data = readw(ioaddr + TSTDAT) & 0xff;
1607 /*
1608 * the value must be negative, and within certain values
1609 * (these values all come from National)
1610 */
1611 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1612 np = netdev_priv(dev);
1613
1614 /* the bug has been triggered - fix the coefficient */
1615 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1616 /* lock the value */
1617 data = readw(ioaddr + DSPCFG);
1618 np->dspcfg = data | DSPCFG_LOCK;
1619 writew(np->dspcfg, ioaddr + DSPCFG);
1620 }
1621 writew(0, ioaddr + PGSEL);
1622 }
1623 }
1624
1625 static void undo_cable_magic(struct net_device *dev)
1626 {
1627 u16 data;
1628 struct netdev_private *np = netdev_priv(dev);
1629 void __iomem * ioaddr = ns_ioaddr(dev);
1630
1631 if (dev->if_port != PORT_TP)
1632 return;
1633
1634 if (np->srr >= SRR_DP83816_A5)
1635 return;
1636
1637 writew(1, ioaddr + PGSEL);
1638 /* make sure the lock bit is clear */
1639 data = readw(ioaddr + DSPCFG);
1640 np->dspcfg = data & ~DSPCFG_LOCK;
1641 writew(np->dspcfg, ioaddr + DSPCFG);
1642 writew(0, ioaddr + PGSEL);
1643 }
1644
1645 static void check_link(struct net_device *dev)
1646 {
1647 struct netdev_private *np = netdev_priv(dev);
1648 void __iomem * ioaddr = ns_ioaddr(dev);
1649 int duplex = np->duplex;
1650 u16 bmsr;
1651
1652 /* If we are ignoring the PHY then don't try reading it. */
1653 if (np->ignore_phy)
1654 goto propagate_state;
1655
1656 /* The link status field is latched: it remains low after a temporary
1657 * link failure until it's read. We need the current link status,
1658 * thus read twice.
1659 */
1660 mdio_read(dev, MII_BMSR);
1661 bmsr = mdio_read(dev, MII_BMSR);
1662
1663 if (!(bmsr & BMSR_LSTATUS)) {
1664 if (netif_carrier_ok(dev)) {
1665 if (netif_msg_link(np))
1666 printk(KERN_NOTICE "%s: link down.\n",
1667 dev->name);
1668 netif_carrier_off(dev);
1669 undo_cable_magic(dev);
1670 }
1671 return;
1672 }
1673 if (!netif_carrier_ok(dev)) {
1674 if (netif_msg_link(np))
1675 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1676 netif_carrier_on(dev);
1677 do_cable_magic(dev);
1678 }
1679
1680 duplex = np->full_duplex;
1681 if (!duplex) {
1682 if (bmsr & BMSR_ANEGCOMPLETE) {
1683 int tmp = mii_nway_result(
1684 np->advertising & mdio_read(dev, MII_LPA));
1685 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1686 duplex = 1;
1687 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1688 duplex = 1;
1689 }
1690
1691 propagate_state:
1692 /* if duplex is set then bit 28 must be set, too */
1693 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1694 if (netif_msg_link(np))
1695 printk(KERN_INFO
1696 "%s: Setting %s-duplex based on negotiated "
1697 "link capability.\n", dev->name,
1698 duplex ? "full" : "half");
1699 if (duplex) {
1700 np->rx_config |= RxAcceptTx;
1701 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1702 } else {
1703 np->rx_config &= ~RxAcceptTx;
1704 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1705 }
1706 writel(np->tx_config, ioaddr + TxConfig);
1707 writel(np->rx_config, ioaddr + RxConfig);
1708 }
1709 }
1710
1711 static void init_registers(struct net_device *dev)
1712 {
1713 struct netdev_private *np = netdev_priv(dev);
1714 void __iomem * ioaddr = ns_ioaddr(dev);
1715
1716 init_phy_fixup(dev);
1717
1718 /* clear any interrupts that are pending, such as wake events */
1719 readl(ioaddr + IntrStatus);
1720
1721 writel(np->ring_dma, ioaddr + RxRingPtr);
1722 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1723 ioaddr + TxRingPtr);
1724
1725 /* Initialize other registers.
1726 * Configure the PCI bus bursts and FIFO thresholds.
1727 * Configure for standard, in-spec Ethernet.
1728 * Start with half-duplex. check_link will update
1729 * to the correct settings.
1730 */
1731
1732 /* DRTH: 2: start tx if 64 bytes are in the fifo
1733 * FLTH: 0x10: refill with next packet if 512 bytes are free
1734 * MXDMA: 0: up to 256 byte bursts.
1735 * MXDMA must be <= FLTH
1736 * ECRETRY=1
1737 * ATP=1
1738 */
1739 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1740 TX_FLTH_VAL | TX_DRTH_VAL_START;
1741 writel(np->tx_config, ioaddr + TxConfig);
1742
1743 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1744 * MXDMA 0: up to 256 byte bursts
1745 */
1746 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1747 /* if receive ring now has bigger buffers than normal, enable jumbo */
1748 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1749 np->rx_config |= RxAcceptLong;
1750
1751 writel(np->rx_config, ioaddr + RxConfig);
1752
1753 /* Disable PME:
1754 * The PME bit is initialized from the EEPROM contents.
1755 * PCI cards probably have PME disabled, but motherboard
1756 * implementations may have PME set to enable WakeOnLan.
1757 * With PME set the chip will scan incoming packets but
1758 * nothing will be written to memory. */
1759 np->SavedClkRun = readl(ioaddr + ClkRun);
1760 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1761 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1762 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1763 dev->name, readl(ioaddr + WOLCmd));
1764 }
1765
1766 check_link(dev);
1767 __set_rx_mode(dev);
1768
1769 /* Enable interrupts by setting the interrupt mask. */
1770 writel(DEFAULT_INTR, ioaddr + IntrMask);
1771 natsemi_irq_enable(dev);
1772
1773 writel(RxOn | TxOn, ioaddr + ChipCmd);
1774 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1775 }
1776
1777 /*
1778 * netdev_timer:
1779 * Purpose:
1780 * 1) check for link changes. Usually they are handled by the MII interrupt
1781 * but it doesn't hurt to check twice.
1782 * 2) check for sudden death of the NIC:
1783 * It seems that a reference set for this chip went out with incorrect info,
1784 * and there exist boards that aren't quite right. An unexpected voltage
1785 * drop can cause the PHY to get itself in a weird state (basically reset).
1786 * NOTE: this only seems to affect revC chips. The user can disable
1787 * this check via dspcfg_workaround sysfs option.
1788 * 3) check of death of the RX path due to OOM
1789 */
1790 static void netdev_timer(unsigned long data)
1791 {
1792 struct net_device *dev = (struct net_device *)data;
1793 struct netdev_private *np = netdev_priv(dev);
1794 void __iomem * ioaddr = ns_ioaddr(dev);
1795 int next_tick = NATSEMI_TIMER_FREQ;
1796 const int irq = np->pci_dev->irq;
1797
1798 if (netif_msg_timer(np)) {
1799 /* DO NOT read the IntrStatus register,
1800 * a read clears any pending interrupts.
1801 */
1802 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1803 dev->name);
1804 }
1805
1806 if (dev->if_port == PORT_TP) {
1807 u16 dspcfg;
1808
1809 spin_lock_irq(&np->lock);
1810 /* check for a nasty random phy-reset - use dspcfg as a flag */
1811 writew(1, ioaddr+PGSEL);
1812 dspcfg = readw(ioaddr+DSPCFG);
1813 writew(0, ioaddr+PGSEL);
1814 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1815 if (!netif_queue_stopped(dev)) {
1816 spin_unlock_irq(&np->lock);
1817 if (netif_msg_drv(np))
1818 printk(KERN_NOTICE "%s: possible phy reset: "
1819 "re-initializing\n", dev->name);
1820 disable_irq(irq);
1821 spin_lock_irq(&np->lock);
1822 natsemi_stop_rxtx(dev);
1823 dump_ring(dev);
1824 reinit_ring(dev);
1825 init_registers(dev);
1826 spin_unlock_irq(&np->lock);
1827 enable_irq(irq);
1828 } else {
1829 /* hurry back */
1830 next_tick = HZ;
1831 spin_unlock_irq(&np->lock);
1832 }
1833 } else {
1834 /* init_registers() calls check_link() for the above case */
1835 check_link(dev);
1836 spin_unlock_irq(&np->lock);
1837 }
1838 } else {
1839 spin_lock_irq(&np->lock);
1840 check_link(dev);
1841 spin_unlock_irq(&np->lock);
1842 }
1843 if (np->oom) {
1844 disable_irq(irq);
1845 np->oom = 0;
1846 refill_rx(dev);
1847 enable_irq(irq);
1848 if (!np->oom) {
1849 writel(RxOn, ioaddr + ChipCmd);
1850 } else {
1851 next_tick = 1;
1852 }
1853 }
1854
1855 if (next_tick > 1)
1856 mod_timer(&np->timer, round_jiffies(jiffies + next_tick));
1857 else
1858 mod_timer(&np->timer, jiffies + next_tick);
1859 }
1860
1861 static void dump_ring(struct net_device *dev)
1862 {
1863 struct netdev_private *np = netdev_priv(dev);
1864
1865 if (netif_msg_pktdata(np)) {
1866 int i;
1867 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1868 for (i = 0; i < TX_RING_SIZE; i++) {
1869 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1870 i, np->tx_ring[i].next_desc,
1871 np->tx_ring[i].cmd_status,
1872 np->tx_ring[i].addr);
1873 }
1874 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1875 for (i = 0; i < RX_RING_SIZE; i++) {
1876 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1877 i, np->rx_ring[i].next_desc,
1878 np->rx_ring[i].cmd_status,
1879 np->rx_ring[i].addr);
1880 }
1881 }
1882 }
1883
1884 static void ns_tx_timeout(struct net_device *dev)
1885 {
1886 struct netdev_private *np = netdev_priv(dev);
1887 void __iomem * ioaddr = ns_ioaddr(dev);
1888 const int irq = np->pci_dev->irq;
1889
1890 disable_irq(irq);
1891 spin_lock_irq(&np->lock);
1892 if (!np->hands_off) {
1893 if (netif_msg_tx_err(np))
1894 printk(KERN_WARNING
1895 "%s: Transmit timed out, status %#08x,"
1896 " resetting...\n",
1897 dev->name, readl(ioaddr + IntrStatus));
1898 dump_ring(dev);
1899
1900 natsemi_reset(dev);
1901 reinit_ring(dev);
1902 init_registers(dev);
1903 } else {
1904 printk(KERN_WARNING
1905 "%s: tx_timeout while in hands_off state?\n",
1906 dev->name);
1907 }
1908 spin_unlock_irq(&np->lock);
1909 enable_irq(irq);
1910
1911 dev->trans_start = jiffies; /* prevent tx timeout */
1912 dev->stats.tx_errors++;
1913 netif_wake_queue(dev);
1914 }
1915
1916 static int alloc_ring(struct net_device *dev)
1917 {
1918 struct netdev_private *np = netdev_priv(dev);
1919 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1920 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1921 &np->ring_dma);
1922 if (!np->rx_ring)
1923 return -ENOMEM;
1924 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1925 return 0;
1926 }
1927
1928 static void refill_rx(struct net_device *dev)
1929 {
1930 struct netdev_private *np = netdev_priv(dev);
1931
1932 /* Refill the Rx ring buffers. */
1933 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1934 struct sk_buff *skb;
1935 int entry = np->dirty_rx % RX_RING_SIZE;
1936 if (np->rx_skbuff[entry] == NULL) {
1937 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1938 skb = netdev_alloc_skb(dev, buflen);
1939 np->rx_skbuff[entry] = skb;
1940 if (skb == NULL)
1941 break; /* Better luck next round. */
1942 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1943 skb->data, buflen, PCI_DMA_FROMDEVICE);
1944 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1945 }
1946 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1947 }
1948 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1949 if (netif_msg_rx_err(np))
1950 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1951 np->oom = 1;
1952 }
1953 }
1954
1955 static void set_bufsize(struct net_device *dev)
1956 {
1957 struct netdev_private *np = netdev_priv(dev);
1958 if (dev->mtu <= ETH_DATA_LEN)
1959 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1960 else
1961 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1962 }
1963
1964 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1965 static void init_ring(struct net_device *dev)
1966 {
1967 struct netdev_private *np = netdev_priv(dev);
1968 int i;
1969
1970 /* 1) TX ring */
1971 np->dirty_tx = np->cur_tx = 0;
1972 for (i = 0; i < TX_RING_SIZE; i++) {
1973 np->tx_skbuff[i] = NULL;
1974 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1975 +sizeof(struct netdev_desc)
1976 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1977 np->tx_ring[i].cmd_status = 0;
1978 }
1979
1980 /* 2) RX ring */
1981 np->dirty_rx = 0;
1982 np->cur_rx = RX_RING_SIZE;
1983 np->oom = 0;
1984 set_bufsize(dev);
1985
1986 np->rx_head_desc = &np->rx_ring[0];
1987
1988 /* Please be careful before changing this loop - at least gcc-2.95.1
1989 * miscompiles it otherwise.
1990 */
1991 /* Initialize all Rx descriptors. */
1992 for (i = 0; i < RX_RING_SIZE; i++) {
1993 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1994 +sizeof(struct netdev_desc)
1995 *((i+1)%RX_RING_SIZE));
1996 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1997 np->rx_skbuff[i] = NULL;
1998 }
1999 refill_rx(dev);
2000 dump_ring(dev);
2001 }
2002
2003 static void drain_tx(struct net_device *dev)
2004 {
2005 struct netdev_private *np = netdev_priv(dev);
2006 int i;
2007
2008 for (i = 0; i < TX_RING_SIZE; i++) {
2009 if (np->tx_skbuff[i]) {
2010 pci_unmap_single(np->pci_dev,
2011 np->tx_dma[i], np->tx_skbuff[i]->len,
2012 PCI_DMA_TODEVICE);
2013 dev_kfree_skb(np->tx_skbuff[i]);
2014 dev->stats.tx_dropped++;
2015 }
2016 np->tx_skbuff[i] = NULL;
2017 }
2018 }
2019
2020 static void drain_rx(struct net_device *dev)
2021 {
2022 struct netdev_private *np = netdev_priv(dev);
2023 unsigned int buflen = np->rx_buf_sz;
2024 int i;
2025
2026 /* Free all the skbuffs in the Rx queue. */
2027 for (i = 0; i < RX_RING_SIZE; i++) {
2028 np->rx_ring[i].cmd_status = 0;
2029 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
2030 if (np->rx_skbuff[i]) {
2031 pci_unmap_single(np->pci_dev, np->rx_dma[i],
2032 buflen + NATSEMI_PADDING,
2033 PCI_DMA_FROMDEVICE);
2034 dev_kfree_skb(np->rx_skbuff[i]);
2035 }
2036 np->rx_skbuff[i] = NULL;
2037 }
2038 }
2039
2040 static void drain_ring(struct net_device *dev)
2041 {
2042 drain_rx(dev);
2043 drain_tx(dev);
2044 }
2045
2046 static void free_ring(struct net_device *dev)
2047 {
2048 struct netdev_private *np = netdev_priv(dev);
2049 pci_free_consistent(np->pci_dev,
2050 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2051 np->rx_ring, np->ring_dma);
2052 }
2053
2054 static void reinit_rx(struct net_device *dev)
2055 {
2056 struct netdev_private *np = netdev_priv(dev);
2057 int i;
2058
2059 /* RX Ring */
2060 np->dirty_rx = 0;
2061 np->cur_rx = RX_RING_SIZE;
2062 np->rx_head_desc = &np->rx_ring[0];
2063 /* Initialize all Rx descriptors. */
2064 for (i = 0; i < RX_RING_SIZE; i++)
2065 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2066
2067 refill_rx(dev);
2068 }
2069
2070 static void reinit_ring(struct net_device *dev)
2071 {
2072 struct netdev_private *np = netdev_priv(dev);
2073 int i;
2074
2075 /* drain TX ring */
2076 drain_tx(dev);
2077 np->dirty_tx = np->cur_tx = 0;
2078 for (i=0;i<TX_RING_SIZE;i++)
2079 np->tx_ring[i].cmd_status = 0;
2080
2081 reinit_rx(dev);
2082 }
2083
2084 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
2085 {
2086 struct netdev_private *np = netdev_priv(dev);
2087 void __iomem * ioaddr = ns_ioaddr(dev);
2088 unsigned entry;
2089 unsigned long flags;
2090
2091 /* Note: Ordering is important here, set the field with the
2092 "ownership" bit last, and only then increment cur_tx. */
2093
2094 /* Calculate the next Tx descriptor entry. */
2095 entry = np->cur_tx % TX_RING_SIZE;
2096
2097 np->tx_skbuff[entry] = skb;
2098 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2099 skb->data,skb->len, PCI_DMA_TODEVICE);
2100
2101 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2102
2103 spin_lock_irqsave(&np->lock, flags);
2104
2105 if (!np->hands_off) {
2106 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2107 /* StrongARM: Explicitly cache flush np->tx_ring and
2108 * skb->data,skb->len. */
2109 wmb();
2110 np->cur_tx++;
2111 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2112 netdev_tx_done(dev);
2113 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2114 netif_stop_queue(dev);
2115 }
2116 /* Wake the potentially-idle transmit channel. */
2117 writel(TxOn, ioaddr + ChipCmd);
2118 } else {
2119 dev_kfree_skb_irq(skb);
2120 dev->stats.tx_dropped++;
2121 }
2122 spin_unlock_irqrestore(&np->lock, flags);
2123
2124 if (netif_msg_tx_queued(np)) {
2125 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2126 dev->name, np->cur_tx, entry);
2127 }
2128 return NETDEV_TX_OK;
2129 }
2130
2131 static void netdev_tx_done(struct net_device *dev)
2132 {
2133 struct netdev_private *np = netdev_priv(dev);
2134
2135 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2136 int entry = np->dirty_tx % TX_RING_SIZE;
2137 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2138 break;
2139 if (netif_msg_tx_done(np))
2140 printk(KERN_DEBUG
2141 "%s: tx frame #%d finished, status %#08x.\n",
2142 dev->name, np->dirty_tx,
2143 le32_to_cpu(np->tx_ring[entry].cmd_status));
2144 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2145 dev->stats.tx_packets++;
2146 dev->stats.tx_bytes += np->tx_skbuff[entry]->len;
2147 } else { /* Various Tx errors */
2148 int tx_status =
2149 le32_to_cpu(np->tx_ring[entry].cmd_status);
2150 if (tx_status & (DescTxAbort|DescTxExcColl))
2151 dev->stats.tx_aborted_errors++;
2152 if (tx_status & DescTxFIFO)
2153 dev->stats.tx_fifo_errors++;
2154 if (tx_status & DescTxCarrier)
2155 dev->stats.tx_carrier_errors++;
2156 if (tx_status & DescTxOOWCol)
2157 dev->stats.tx_window_errors++;
2158 dev->stats.tx_errors++;
2159 }
2160 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2161 np->tx_skbuff[entry]->len,
2162 PCI_DMA_TODEVICE);
2163 /* Free the original skb. */
2164 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2165 np->tx_skbuff[entry] = NULL;
2166 }
2167 if (netif_queue_stopped(dev) &&
2168 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2169 /* The ring is no longer full, wake queue. */
2170 netif_wake_queue(dev);
2171 }
2172 }
2173
2174 /* The interrupt handler doesn't actually handle interrupts itself, it
2175 * schedules a NAPI poll if there is anything to do. */
2176 static irqreturn_t intr_handler(int irq, void *dev_instance)
2177 {
2178 struct net_device *dev = dev_instance;
2179 struct netdev_private *np = netdev_priv(dev);
2180 void __iomem * ioaddr = ns_ioaddr(dev);
2181
2182 /* Reading IntrStatus automatically acknowledges so don't do
2183 * that while interrupts are disabled, (for example, while a
2184 * poll is scheduled). */
2185 if (np->hands_off || !readl(ioaddr + IntrEnable))
2186 return IRQ_NONE;
2187
2188 np->intr_status = readl(ioaddr + IntrStatus);
2189
2190 if (!np->intr_status)
2191 return IRQ_NONE;
2192
2193 if (netif_msg_intr(np))
2194 printk(KERN_DEBUG
2195 "%s: Interrupt, status %#08x, mask %#08x.\n",
2196 dev->name, np->intr_status,
2197 readl(ioaddr + IntrMask));
2198
2199 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2200
2201 if (napi_schedule_prep(&np->napi)) {
2202 /* Disable interrupts and register for poll */
2203 natsemi_irq_disable(dev);
2204 __napi_schedule(&np->napi);
2205 } else
2206 printk(KERN_WARNING
2207 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2208 dev->name, np->intr_status,
2209 readl(ioaddr + IntrMask));
2210
2211 return IRQ_HANDLED;
2212 }
2213
2214 /* This is the NAPI poll routine. As well as the standard RX handling
2215 * it also handles all other interrupts that the chip might raise.
2216 */
2217 static int natsemi_poll(struct napi_struct *napi, int budget)
2218 {
2219 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2220 struct net_device *dev = np->dev;
2221 void __iomem * ioaddr = ns_ioaddr(dev);
2222 int work_done = 0;
2223
2224 do {
2225 if (netif_msg_intr(np))
2226 printk(KERN_DEBUG
2227 "%s: Poll, status %#08x, mask %#08x.\n",
2228 dev->name, np->intr_status,
2229 readl(ioaddr + IntrMask));
2230
2231 /* netdev_rx() may read IntrStatus again if the RX state
2232 * machine falls over so do it first. */
2233 if (np->intr_status &
2234 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2235 IntrRxErr | IntrRxOverrun)) {
2236 netdev_rx(dev, &work_done, budget);
2237 }
2238
2239 if (np->intr_status &
2240 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2241 spin_lock(&np->lock);
2242 netdev_tx_done(dev);
2243 spin_unlock(&np->lock);
2244 }
2245
2246 /* Abnormal error summary/uncommon events handlers. */
2247 if (np->intr_status & IntrAbnormalSummary)
2248 netdev_error(dev, np->intr_status);
2249
2250 if (work_done >= budget)
2251 return work_done;
2252
2253 np->intr_status = readl(ioaddr + IntrStatus);
2254 } while (np->intr_status);
2255
2256 napi_complete(napi);
2257
2258 /* Reenable interrupts providing nothing is trying to shut
2259 * the chip down. */
2260 spin_lock(&np->lock);
2261 if (!np->hands_off)
2262 natsemi_irq_enable(dev);
2263 spin_unlock(&np->lock);
2264
2265 return work_done;
2266 }
2267
2268 /* This routine is logically part of the interrupt handler, but separated
2269 for clarity and better register allocation. */
2270 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
2271 {
2272 struct netdev_private *np = netdev_priv(dev);
2273 int entry = np->cur_rx % RX_RING_SIZE;
2274 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2275 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2276 unsigned int buflen = np->rx_buf_sz;
2277 void __iomem * ioaddr = ns_ioaddr(dev);
2278
2279 /* If the driver owns the next entry it's a new packet. Send it up. */
2280 while (desc_status < 0) { /* e.g. & DescOwn */
2281 int pkt_len;
2282 if (netif_msg_rx_status(np))
2283 printk(KERN_DEBUG
2284 " netdev_rx() entry %d status was %#08x.\n",
2285 entry, desc_status);
2286 if (--boguscnt < 0)
2287 break;
2288
2289 if (*work_done >= work_to_do)
2290 break;
2291
2292 (*work_done)++;
2293
2294 pkt_len = (desc_status & DescSizeMask) - 4;
2295 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2296 if (desc_status & DescMore) {
2297 unsigned long flags;
2298
2299 if (netif_msg_rx_err(np))
2300 printk(KERN_WARNING
2301 "%s: Oversized(?) Ethernet "
2302 "frame spanned multiple "
2303 "buffers, entry %#08x "
2304 "status %#08x.\n", dev->name,
2305 np->cur_rx, desc_status);
2306 dev->stats.rx_length_errors++;
2307
2308 /* The RX state machine has probably
2309 * locked up beneath us. Follow the
2310 * reset procedure documented in
2311 * AN-1287. */
2312
2313 spin_lock_irqsave(&np->lock, flags);
2314 reset_rx(dev);
2315 reinit_rx(dev);
2316 writel(np->ring_dma, ioaddr + RxRingPtr);
2317 check_link(dev);
2318 spin_unlock_irqrestore(&np->lock, flags);
2319
2320 /* We'll enable RX on exit from this
2321 * function. */
2322 break;
2323
2324 } else {
2325 /* There was an error. */
2326 dev->stats.rx_errors++;
2327 if (desc_status & (DescRxAbort|DescRxOver))
2328 dev->stats.rx_over_errors++;
2329 if (desc_status & (DescRxLong|DescRxRunt))
2330 dev->stats.rx_length_errors++;
2331 if (desc_status & (DescRxInvalid|DescRxAlign))
2332 dev->stats.rx_frame_errors++;
2333 if (desc_status & DescRxCRC)
2334 dev->stats.rx_crc_errors++;
2335 }
2336 } else if (pkt_len > np->rx_buf_sz) {
2337 /* if this is the tail of a double buffer
2338 * packet, we've already counted the error
2339 * on the first part. Ignore the second half.
2340 */
2341 } else {
2342 struct sk_buff *skb;
2343 /* Omit CRC size. */
2344 /* Check if the packet is long enough to accept
2345 * without copying to a minimally-sized skbuff. */
2346 if (pkt_len < rx_copybreak &&
2347 (skb = netdev_alloc_skb(dev, pkt_len + RX_OFFSET)) != NULL) {
2348 /* 16 byte align the IP header */
2349 skb_reserve(skb, RX_OFFSET);
2350 pci_dma_sync_single_for_cpu(np->pci_dev,
2351 np->rx_dma[entry],
2352 buflen,
2353 PCI_DMA_FROMDEVICE);
2354 skb_copy_to_linear_data(skb,
2355 np->rx_skbuff[entry]->data, pkt_len);
2356 skb_put(skb, pkt_len);
2357 pci_dma_sync_single_for_device(np->pci_dev,
2358 np->rx_dma[entry],
2359 buflen,
2360 PCI_DMA_FROMDEVICE);
2361 } else {
2362 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2363 buflen + NATSEMI_PADDING,
2364 PCI_DMA_FROMDEVICE);
2365 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2366 np->rx_skbuff[entry] = NULL;
2367 }
2368 skb->protocol = eth_type_trans(skb, dev);
2369 netif_receive_skb(skb);
2370 dev->stats.rx_packets++;
2371 dev->stats.rx_bytes += pkt_len;
2372 }
2373 entry = (++np->cur_rx) % RX_RING_SIZE;
2374 np->rx_head_desc = &np->rx_ring[entry];
2375 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2376 }
2377 refill_rx(dev);
2378
2379 /* Restart Rx engine if stopped. */
2380 if (np->oom)
2381 mod_timer(&np->timer, jiffies + 1);
2382 else
2383 writel(RxOn, ioaddr + ChipCmd);
2384 }
2385
2386 static void netdev_error(struct net_device *dev, int intr_status)
2387 {
2388 struct netdev_private *np = netdev_priv(dev);
2389 void __iomem * ioaddr = ns_ioaddr(dev);
2390
2391 spin_lock(&np->lock);
2392 if (intr_status & LinkChange) {
2393 u16 lpa = mdio_read(dev, MII_LPA);
2394 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE &&
2395 netif_msg_link(np)) {
2396 printk(KERN_INFO
2397 "%s: Autonegotiation advertising"
2398 " %#04x partner %#04x.\n", dev->name,
2399 np->advertising, lpa);
2400 }
2401
2402 /* read MII int status to clear the flag */
2403 readw(ioaddr + MIntrStatus);
2404 check_link(dev);
2405 }
2406 if (intr_status & StatsMax) {
2407 __get_stats(dev);
2408 }
2409 if (intr_status & IntrTxUnderrun) {
2410 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2411 np->tx_config += TX_DRTH_VAL_INC;
2412 if (netif_msg_tx_err(np))
2413 printk(KERN_NOTICE
2414 "%s: increased tx threshold, txcfg %#08x.\n",
2415 dev->name, np->tx_config);
2416 } else {
2417 if (netif_msg_tx_err(np))
2418 printk(KERN_NOTICE
2419 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2420 dev->name, np->tx_config);
2421 }
2422 writel(np->tx_config, ioaddr + TxConfig);
2423 }
2424 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2425 int wol_status = readl(ioaddr + WOLCmd);
2426 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2427 dev->name, wol_status);
2428 }
2429 if (intr_status & RxStatusFIFOOver) {
2430 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2431 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2432 dev->name);
2433 }
2434 dev->stats.rx_fifo_errors++;
2435 dev->stats.rx_errors++;
2436 }
2437 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2438 if (intr_status & IntrPCIErr) {
2439 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2440 intr_status & IntrPCIErr);
2441 dev->stats.tx_fifo_errors++;
2442 dev->stats.tx_errors++;
2443 dev->stats.rx_fifo_errors++;
2444 dev->stats.rx_errors++;
2445 }
2446 spin_unlock(&np->lock);
2447 }
2448
2449 static void __get_stats(struct net_device *dev)
2450 {
2451 void __iomem * ioaddr = ns_ioaddr(dev);
2452
2453 /* The chip only need report frame silently dropped. */
2454 dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2455 dev->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2456 }
2457
2458 static struct net_device_stats *get_stats(struct net_device *dev)
2459 {
2460 struct netdev_private *np = netdev_priv(dev);
2461
2462 /* The chip only need report frame silently dropped. */
2463 spin_lock_irq(&np->lock);
2464 if (netif_running(dev) && !np->hands_off)
2465 __get_stats(dev);
2466 spin_unlock_irq(&np->lock);
2467
2468 return &dev->stats;
2469 }
2470
2471 #ifdef CONFIG_NET_POLL_CONTROLLER
2472 static void natsemi_poll_controller(struct net_device *dev)
2473 {
2474 struct netdev_private *np = netdev_priv(dev);
2475 const int irq = np->pci_dev->irq;
2476
2477 disable_irq(irq);
2478 intr_handler(irq, dev);
2479 enable_irq(irq);
2480 }
2481 #endif
2482
2483 #define HASH_TABLE 0x200
2484 static void __set_rx_mode(struct net_device *dev)
2485 {
2486 void __iomem * ioaddr = ns_ioaddr(dev);
2487 struct netdev_private *np = netdev_priv(dev);
2488 u8 mc_filter[64]; /* Multicast hash filter */
2489 u32 rx_mode;
2490
2491 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2492 rx_mode = RxFilterEnable | AcceptBroadcast
2493 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2494 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2495 (dev->flags & IFF_ALLMULTI)) {
2496 rx_mode = RxFilterEnable | AcceptBroadcast
2497 | AcceptAllMulticast | AcceptMyPhys;
2498 } else {
2499 struct netdev_hw_addr *ha;
2500 int i;
2501
2502 memset(mc_filter, 0, sizeof(mc_filter));
2503 netdev_for_each_mc_addr(ha, dev) {
2504 int b = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x1ff;
2505 mc_filter[b/8] |= (1 << (b & 0x07));
2506 }
2507 rx_mode = RxFilterEnable | AcceptBroadcast
2508 | AcceptMulticast | AcceptMyPhys;
2509 for (i = 0; i < 64; i += 2) {
2510 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2511 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2512 ioaddr + RxFilterData);
2513 }
2514 }
2515 writel(rx_mode, ioaddr + RxFilterAddr);
2516 np->cur_rx_mode = rx_mode;
2517 }
2518
2519 static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2520 {
2521 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2522 return -EINVAL;
2523
2524 dev->mtu = new_mtu;
2525
2526 /* synchronized against open : rtnl_lock() held by caller */
2527 if (netif_running(dev)) {
2528 struct netdev_private *np = netdev_priv(dev);
2529 void __iomem * ioaddr = ns_ioaddr(dev);
2530 const int irq = np->pci_dev->irq;
2531
2532 disable_irq(irq);
2533 spin_lock(&np->lock);
2534 /* stop engines */
2535 natsemi_stop_rxtx(dev);
2536 /* drain rx queue */
2537 drain_rx(dev);
2538 /* change buffers */
2539 set_bufsize(dev);
2540 reinit_rx(dev);
2541 writel(np->ring_dma, ioaddr + RxRingPtr);
2542 /* restart engines */
2543 writel(RxOn | TxOn, ioaddr + ChipCmd);
2544 spin_unlock(&np->lock);
2545 enable_irq(irq);
2546 }
2547 return 0;
2548 }
2549
2550 static void set_rx_mode(struct net_device *dev)
2551 {
2552 struct netdev_private *np = netdev_priv(dev);
2553 spin_lock_irq(&np->lock);
2554 if (!np->hands_off)
2555 __set_rx_mode(dev);
2556 spin_unlock_irq(&np->lock);
2557 }
2558
2559 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2560 {
2561 struct netdev_private *np = netdev_priv(dev);
2562 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2563 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2564 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
2565 }
2566
2567 static int get_regs_len(struct net_device *dev)
2568 {
2569 return NATSEMI_REGS_SIZE;
2570 }
2571
2572 static int get_eeprom_len(struct net_device *dev)
2573 {
2574 struct netdev_private *np = netdev_priv(dev);
2575 return np->eeprom_size;
2576 }
2577
2578 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2579 {
2580 struct netdev_private *np = netdev_priv(dev);
2581 spin_lock_irq(&np->lock);
2582 netdev_get_ecmd(dev, ecmd);
2583 spin_unlock_irq(&np->lock);
2584 return 0;
2585 }
2586
2587 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2588 {
2589 struct netdev_private *np = netdev_priv(dev);
2590 int res;
2591 spin_lock_irq(&np->lock);
2592 res = netdev_set_ecmd(dev, ecmd);
2593 spin_unlock_irq(&np->lock);
2594 return res;
2595 }
2596
2597 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2598 {
2599 struct netdev_private *np = netdev_priv(dev);
2600 spin_lock_irq(&np->lock);
2601 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2602 netdev_get_sopass(dev, wol->sopass);
2603 spin_unlock_irq(&np->lock);
2604 }
2605
2606 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2607 {
2608 struct netdev_private *np = netdev_priv(dev);
2609 int res;
2610 spin_lock_irq(&np->lock);
2611 netdev_set_wol(dev, wol->wolopts);
2612 res = netdev_set_sopass(dev, wol->sopass);
2613 spin_unlock_irq(&np->lock);
2614 return res;
2615 }
2616
2617 static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2618 {
2619 struct netdev_private *np = netdev_priv(dev);
2620 regs->version = NATSEMI_REGS_VER;
2621 spin_lock_irq(&np->lock);
2622 netdev_get_regs(dev, buf);
2623 spin_unlock_irq(&np->lock);
2624 }
2625
2626 static u32 get_msglevel(struct net_device *dev)
2627 {
2628 struct netdev_private *np = netdev_priv(dev);
2629 return np->msg_enable;
2630 }
2631
2632 static void set_msglevel(struct net_device *dev, u32 val)
2633 {
2634 struct netdev_private *np = netdev_priv(dev);
2635 np->msg_enable = val;
2636 }
2637
2638 static int nway_reset(struct net_device *dev)
2639 {
2640 int tmp;
2641 int r = -EINVAL;
2642 /* if autoneg is off, it's an error */
2643 tmp = mdio_read(dev, MII_BMCR);
2644 if (tmp & BMCR_ANENABLE) {
2645 tmp |= (BMCR_ANRESTART);
2646 mdio_write(dev, MII_BMCR, tmp);
2647 r = 0;
2648 }
2649 return r;
2650 }
2651
2652 static u32 get_link(struct net_device *dev)
2653 {
2654 /* LSTATUS is latched low until a read - so read twice */
2655 mdio_read(dev, MII_BMSR);
2656 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2657 }
2658
2659 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2660 {
2661 struct netdev_private *np = netdev_priv(dev);
2662 u8 *eebuf;
2663 int res;
2664
2665 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2666 if (!eebuf)
2667 return -ENOMEM;
2668
2669 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2670 spin_lock_irq(&np->lock);
2671 res = netdev_get_eeprom(dev, eebuf);
2672 spin_unlock_irq(&np->lock);
2673 if (!res)
2674 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2675 kfree(eebuf);
2676 return res;
2677 }
2678
2679 static const struct ethtool_ops ethtool_ops = {
2680 .get_drvinfo = get_drvinfo,
2681 .get_regs_len = get_regs_len,
2682 .get_eeprom_len = get_eeprom_len,
2683 .get_settings = get_settings,
2684 .set_settings = set_settings,
2685 .get_wol = get_wol,
2686 .set_wol = set_wol,
2687 .get_regs = get_regs,
2688 .get_msglevel = get_msglevel,
2689 .set_msglevel = set_msglevel,
2690 .nway_reset = nway_reset,
2691 .get_link = get_link,
2692 .get_eeprom = get_eeprom,
2693 };
2694
2695 static int netdev_set_wol(struct net_device *dev, u32 newval)
2696 {
2697 struct netdev_private *np = netdev_priv(dev);
2698 void __iomem * ioaddr = ns_ioaddr(dev);
2699 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2700
2701 /* translate to bitmasks this chip understands */
2702 if (newval & WAKE_PHY)
2703 data |= WakePhy;
2704 if (newval & WAKE_UCAST)
2705 data |= WakeUnicast;
2706 if (newval & WAKE_MCAST)
2707 data |= WakeMulticast;
2708 if (newval & WAKE_BCAST)
2709 data |= WakeBroadcast;
2710 if (newval & WAKE_ARP)
2711 data |= WakeArp;
2712 if (newval & WAKE_MAGIC)
2713 data |= WakeMagic;
2714 if (np->srr >= SRR_DP83815_D) {
2715 if (newval & WAKE_MAGICSECURE) {
2716 data |= WakeMagicSecure;
2717 }
2718 }
2719
2720 writel(data, ioaddr + WOLCmd);
2721
2722 return 0;
2723 }
2724
2725 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2726 {
2727 struct netdev_private *np = netdev_priv(dev);
2728 void __iomem * ioaddr = ns_ioaddr(dev);
2729 u32 regval = readl(ioaddr + WOLCmd);
2730
2731 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2732 | WAKE_ARP | WAKE_MAGIC);
2733
2734 if (np->srr >= SRR_DP83815_D) {
2735 /* SOPASS works on revD and higher */
2736 *supported |= WAKE_MAGICSECURE;
2737 }
2738 *cur = 0;
2739
2740 /* translate from chip bitmasks */
2741 if (regval & WakePhy)
2742 *cur |= WAKE_PHY;
2743 if (regval & WakeUnicast)
2744 *cur |= WAKE_UCAST;
2745 if (regval & WakeMulticast)
2746 *cur |= WAKE_MCAST;
2747 if (regval & WakeBroadcast)
2748 *cur |= WAKE_BCAST;
2749 if (regval & WakeArp)
2750 *cur |= WAKE_ARP;
2751 if (regval & WakeMagic)
2752 *cur |= WAKE_MAGIC;
2753 if (regval & WakeMagicSecure) {
2754 /* this can be on in revC, but it's broken */
2755 *cur |= WAKE_MAGICSECURE;
2756 }
2757
2758 return 0;
2759 }
2760
2761 static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2762 {
2763 struct netdev_private *np = netdev_priv(dev);
2764 void __iomem * ioaddr = ns_ioaddr(dev);
2765 u16 *sval = (u16 *)newval;
2766 u32 addr;
2767
2768 if (np->srr < SRR_DP83815_D) {
2769 return 0;
2770 }
2771
2772 /* enable writing to these registers by disabling the RX filter */
2773 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2774 addr &= ~RxFilterEnable;
2775 writel(addr, ioaddr + RxFilterAddr);
2776
2777 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2778 writel(addr | 0xa, ioaddr + RxFilterAddr);
2779 writew(sval[0], ioaddr + RxFilterData);
2780
2781 writel(addr | 0xc, ioaddr + RxFilterAddr);
2782 writew(sval[1], ioaddr + RxFilterData);
2783
2784 writel(addr | 0xe, ioaddr + RxFilterAddr);
2785 writew(sval[2], ioaddr + RxFilterData);
2786
2787 /* re-enable the RX filter */
2788 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2789
2790 return 0;
2791 }
2792
2793 static int netdev_get_sopass(struct net_device *dev, u8 *data)
2794 {
2795 struct netdev_private *np = netdev_priv(dev);
2796 void __iomem * ioaddr = ns_ioaddr(dev);
2797 u16 *sval = (u16 *)data;
2798 u32 addr;
2799
2800 if (np->srr < SRR_DP83815_D) {
2801 sval[0] = sval[1] = sval[2] = 0;
2802 return 0;
2803 }
2804
2805 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2806 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2807
2808 writel(addr | 0xa, ioaddr + RxFilterAddr);
2809 sval[0] = readw(ioaddr + RxFilterData);
2810
2811 writel(addr | 0xc, ioaddr + RxFilterAddr);
2812 sval[1] = readw(ioaddr + RxFilterData);
2813
2814 writel(addr | 0xe, ioaddr + RxFilterAddr);
2815 sval[2] = readw(ioaddr + RxFilterData);
2816
2817 writel(addr, ioaddr + RxFilterAddr);
2818
2819 return 0;
2820 }
2821
2822 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2823 {
2824 struct netdev_private *np = netdev_priv(dev);
2825 u32 tmp;
2826
2827 ecmd->port = dev->if_port;
2828 ethtool_cmd_speed_set(ecmd, np->speed);
2829 ecmd->duplex = np->duplex;
2830 ecmd->autoneg = np->autoneg;
2831 ecmd->advertising = 0;
2832 if (np->advertising & ADVERTISE_10HALF)
2833 ecmd->advertising |= ADVERTISED_10baseT_Half;
2834 if (np->advertising & ADVERTISE_10FULL)
2835 ecmd->advertising |= ADVERTISED_10baseT_Full;
2836 if (np->advertising & ADVERTISE_100HALF)
2837 ecmd->advertising |= ADVERTISED_100baseT_Half;
2838 if (np->advertising & ADVERTISE_100FULL)
2839 ecmd->advertising |= ADVERTISED_100baseT_Full;
2840 ecmd->supported = (SUPPORTED_Autoneg |
2841 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2842 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2843 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2844 ecmd->phy_address = np->phy_addr_external;
2845 /*
2846 * We intentionally report the phy address of the external
2847 * phy, even if the internal phy is used. This is necessary
2848 * to work around a deficiency of the ethtool interface:
2849 * It's only possible to query the settings of the active
2850 * port. Therefore
2851 * # ethtool -s ethX port mii
2852 * actually sends an ioctl to switch to port mii with the
2853 * settings that are used for the current active port.
2854 * If we would report a different phy address in this
2855 * command, then
2856 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2857 * would unintentionally change the phy address.
2858 *
2859 * Fortunately the phy address doesn't matter with the
2860 * internal phy...
2861 */
2862
2863 /* set information based on active port type */
2864 switch (ecmd->port) {
2865 default:
2866 case PORT_TP:
2867 ecmd->advertising |= ADVERTISED_TP;
2868 ecmd->transceiver = XCVR_INTERNAL;
2869 break;
2870 case PORT_MII:
2871 ecmd->advertising |= ADVERTISED_MII;
2872 ecmd->transceiver = XCVR_EXTERNAL;
2873 break;
2874 case PORT_FIBRE:
2875 ecmd->advertising |= ADVERTISED_FIBRE;
2876 ecmd->transceiver = XCVR_EXTERNAL;
2877 break;
2878 }
2879
2880 /* if autonegotiation is on, try to return the active speed/duplex */
2881 if (ecmd->autoneg == AUTONEG_ENABLE) {
2882 ecmd->advertising |= ADVERTISED_Autoneg;
2883 tmp = mii_nway_result(
2884 np->advertising & mdio_read(dev, MII_LPA));
2885 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2886 ethtool_cmd_speed_set(ecmd, SPEED_100);
2887 else
2888 ethtool_cmd_speed_set(ecmd, SPEED_10);
2889 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2890 ecmd->duplex = DUPLEX_FULL;
2891 else
2892 ecmd->duplex = DUPLEX_HALF;
2893 }
2894
2895 /* ignore maxtxpkt, maxrxpkt for now */
2896
2897 return 0;
2898 }
2899
2900 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2901 {
2902 struct netdev_private *np = netdev_priv(dev);
2903
2904 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2905 return -EINVAL;
2906 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2907 return -EINVAL;
2908 if (ecmd->autoneg == AUTONEG_ENABLE) {
2909 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2910 ADVERTISED_10baseT_Full |
2911 ADVERTISED_100baseT_Half |
2912 ADVERTISED_100baseT_Full)) == 0) {
2913 return -EINVAL;
2914 }
2915 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2916 u32 speed = ethtool_cmd_speed(ecmd);
2917 if (speed != SPEED_10 && speed != SPEED_100)
2918 return -EINVAL;
2919 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2920 return -EINVAL;
2921 } else {
2922 return -EINVAL;
2923 }
2924
2925 /*
2926 * If we're ignoring the PHY then autoneg and the internal
2927 * transceiver are really not going to work so don't let the
2928 * user select them.
2929 */
2930 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2931 ecmd->port == PORT_TP))
2932 return -EINVAL;
2933
2934 /*
2935 * maxtxpkt, maxrxpkt: ignored for now.
2936 *
2937 * transceiver:
2938 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2939 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2940 * selects based on ecmd->port.
2941 *
2942 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2943 * phys that are connected to the mii bus. It's used to apply fibre
2944 * specific updates.
2945 */
2946
2947 /* WHEW! now lets bang some bits */
2948
2949 /* save the parms */
2950 dev->if_port = ecmd->port;
2951 np->autoneg = ecmd->autoneg;
2952 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2953 if (np->autoneg == AUTONEG_ENABLE) {
2954 /* advertise only what has been requested */
2955 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2956 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2957 np->advertising |= ADVERTISE_10HALF;
2958 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2959 np->advertising |= ADVERTISE_10FULL;
2960 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2961 np->advertising |= ADVERTISE_100HALF;
2962 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2963 np->advertising |= ADVERTISE_100FULL;
2964 } else {
2965 np->speed = ethtool_cmd_speed(ecmd);
2966 np->duplex = ecmd->duplex;
2967 /* user overriding the initial full duplex parm? */
2968 if (np->duplex == DUPLEX_HALF)
2969 np->full_duplex = 0;
2970 }
2971
2972 /* get the right phy enabled */
2973 if (ecmd->port == PORT_TP)
2974 switch_port_internal(dev);
2975 else
2976 switch_port_external(dev);
2977
2978 /* set parms and see how this affected our link status */
2979 init_phy_fixup(dev);
2980 check_link(dev);
2981 return 0;
2982 }
2983
2984 static int netdev_get_regs(struct net_device *dev, u8 *buf)
2985 {
2986 int i;
2987 int j;
2988 u32 rfcr;
2989 u32 *rbuf = (u32 *)buf;
2990 void __iomem * ioaddr = ns_ioaddr(dev);
2991
2992 /* read non-mii page 0 of registers */
2993 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2994 rbuf[i] = readl(ioaddr + i*4);
2995 }
2996
2997 /* read current mii registers */
2998 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2999 rbuf[i] = mdio_read(dev, i & 0x1f);
3000
3001 /* read only the 'magic' registers from page 1 */
3002 writew(1, ioaddr + PGSEL);
3003 rbuf[i++] = readw(ioaddr + PMDCSR);
3004 rbuf[i++] = readw(ioaddr + TSTDAT);
3005 rbuf[i++] = readw(ioaddr + DSPCFG);
3006 rbuf[i++] = readw(ioaddr + SDCFG);
3007 writew(0, ioaddr + PGSEL);
3008
3009 /* read RFCR indexed registers */
3010 rfcr = readl(ioaddr + RxFilterAddr);
3011 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3012 writel(j*2, ioaddr + RxFilterAddr);
3013 rbuf[i++] = readw(ioaddr + RxFilterData);
3014 }
3015 writel(rfcr, ioaddr + RxFilterAddr);
3016
3017 /* the interrupt status is clear-on-read - see if we missed any */
3018 if (rbuf[4] & rbuf[5]) {
3019 printk(KERN_WARNING
3020 "%s: shoot, we dropped an interrupt (%#08x)\n",
3021 dev->name, rbuf[4] & rbuf[5]);
3022 }
3023
3024 return 0;
3025 }
3026
3027 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3028 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3029 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3030 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3031 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3032 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3033 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3034 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3035
3036 static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3037 {
3038 int i;
3039 u16 *ebuf = (u16 *)buf;
3040 void __iomem * ioaddr = ns_ioaddr(dev);
3041 struct netdev_private *np = netdev_priv(dev);
3042
3043 /* eeprom_read reads 16 bits, and indexes by 16 bits */
3044 for (i = 0; i < np->eeprom_size/2; i++) {
3045 ebuf[i] = eeprom_read(ioaddr, i);
3046 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3047 * reads it back "sanely". So we swap it back here in order to
3048 * present it to userland as it is stored. */
3049 ebuf[i] = SWAP_BITS(ebuf[i]);
3050 }
3051 return 0;
3052 }
3053
3054 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3055 {
3056 struct mii_ioctl_data *data = if_mii(rq);
3057 struct netdev_private *np = netdev_priv(dev);
3058
3059 switch(cmd) {
3060 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3061 data->phy_id = np->phy_addr_external;
3062 /* Fall Through */
3063
3064 case SIOCGMIIREG: /* Read MII PHY register. */
3065 /* The phy_id is not enough to uniquely identify
3066 * the intended target. Therefore the command is sent to
3067 * the given mii on the current port.
3068 */
3069 if (dev->if_port == PORT_TP) {
3070 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3071 data->val_out = mdio_read(dev,
3072 data->reg_num & 0x1f);
3073 else
3074 data->val_out = 0;
3075 } else {
3076 move_int_phy(dev, data->phy_id & 0x1f);
3077 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3078 data->reg_num & 0x1f);
3079 }
3080 return 0;
3081
3082 case SIOCSMIIREG: /* Write MII PHY register. */
3083 if (dev->if_port == PORT_TP) {
3084 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3085 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3086 np->advertising = data->val_in;
3087 mdio_write(dev, data->reg_num & 0x1f,
3088 data->val_in);
3089 }
3090 } else {
3091 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3092 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3093 np->advertising = data->val_in;
3094 }
3095 move_int_phy(dev, data->phy_id & 0x1f);
3096 miiport_write(dev, data->phy_id & 0x1f,
3097 data->reg_num & 0x1f,
3098 data->val_in);
3099 }
3100 return 0;
3101 default:
3102 return -EOPNOTSUPP;
3103 }
3104 }
3105
3106 static void enable_wol_mode(struct net_device *dev, int enable_intr)
3107 {
3108 void __iomem * ioaddr = ns_ioaddr(dev);
3109 struct netdev_private *np = netdev_priv(dev);
3110
3111 if (netif_msg_wol(np))
3112 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3113 dev->name);
3114
3115 /* For WOL we must restart the rx process in silent mode.
3116 * Write NULL to the RxRingPtr. Only possible if
3117 * rx process is stopped
3118 */
3119 writel(0, ioaddr + RxRingPtr);
3120
3121 /* read WoL status to clear */
3122 readl(ioaddr + WOLCmd);
3123
3124 /* PME on, clear status */
3125 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3126
3127 /* and restart the rx process */
3128 writel(RxOn, ioaddr + ChipCmd);
3129
3130 if (enable_intr) {
3131 /* enable the WOL interrupt.
3132 * Could be used to send a netlink message.
3133 */
3134 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3135 natsemi_irq_enable(dev);
3136 }
3137 }
3138
3139 static int netdev_close(struct net_device *dev)
3140 {
3141 void __iomem * ioaddr = ns_ioaddr(dev);
3142 struct netdev_private *np = netdev_priv(dev);
3143 const int irq = np->pci_dev->irq;
3144
3145 if (netif_msg_ifdown(np))
3146 printk(KERN_DEBUG
3147 "%s: Shutting down ethercard, status was %#04x.\n",
3148 dev->name, (int)readl(ioaddr + ChipCmd));
3149 if (netif_msg_pktdata(np))
3150 printk(KERN_DEBUG
3151 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3152 dev->name, np->cur_tx, np->dirty_tx,
3153 np->cur_rx, np->dirty_rx);
3154
3155 napi_disable(&np->napi);
3156
3157 /*
3158 * FIXME: what if someone tries to close a device
3159 * that is suspended?
3160 * Should we reenable the nic to switch to
3161 * the final WOL settings?
3162 */
3163
3164 del_timer_sync(&np->timer);
3165 disable_irq(irq);
3166 spin_lock_irq(&np->lock);
3167 natsemi_irq_disable(dev);
3168 np->hands_off = 1;
3169 spin_unlock_irq(&np->lock);
3170 enable_irq(irq);
3171
3172 free_irq(irq, dev);
3173
3174 /* Interrupt disabled, interrupt handler released,
3175 * queue stopped, timer deleted, rtnl_lock held
3176 * All async codepaths that access the driver are disabled.
3177 */
3178 spin_lock_irq(&np->lock);
3179 np->hands_off = 0;
3180 readl(ioaddr + IntrMask);
3181 readw(ioaddr + MIntrStatus);
3182
3183 /* Freeze Stats */
3184 writel(StatsFreeze, ioaddr + StatsCtrl);
3185
3186 /* Stop the chip's Tx and Rx processes. */
3187 natsemi_stop_rxtx(dev);
3188
3189 __get_stats(dev);
3190 spin_unlock_irq(&np->lock);
3191
3192 /* clear the carrier last - an interrupt could reenable it otherwise */
3193 netif_carrier_off(dev);
3194 netif_stop_queue(dev);
3195
3196 dump_ring(dev);
3197 drain_ring(dev);
3198 free_ring(dev);
3199
3200 {
3201 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3202 if (wol) {
3203 /* restart the NIC in WOL mode.
3204 * The nic must be stopped for this.
3205 */
3206 enable_wol_mode(dev, 0);
3207 } else {
3208 /* Restore PME enable bit unmolested */
3209 writel(np->SavedClkRun, ioaddr + ClkRun);
3210 }
3211 }
3212 return 0;
3213 }
3214
3215
3216 static void natsemi_remove1(struct pci_dev *pdev)
3217 {
3218 struct net_device *dev = pci_get_drvdata(pdev);
3219 void __iomem * ioaddr = ns_ioaddr(dev);
3220
3221 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
3222 unregister_netdev (dev);
3223 pci_release_regions (pdev);
3224 iounmap(ioaddr);
3225 free_netdev (dev);
3226 pci_set_drvdata(pdev, NULL);
3227 }
3228
3229 #ifdef CONFIG_PM
3230
3231 /*
3232 * The ns83815 chip doesn't have explicit RxStop bits.
3233 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3234 * of the nic, thus this function must be very careful:
3235 *
3236 * suspend/resume synchronization:
3237 * entry points:
3238 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3239 * start_tx, ns_tx_timeout
3240 *
3241 * No function accesses the hardware without checking np->hands_off.
3242 * the check occurs under spin_lock_irq(&np->lock);
3243 * exceptions:
3244 * * netdev_ioctl: noncritical access.
3245 * * netdev_open: cannot happen due to the device_detach
3246 * * netdev_close: doesn't hurt.
3247 * * netdev_timer: timer stopped by natsemi_suspend.
3248 * * intr_handler: doesn't acquire the spinlock. suspend calls
3249 * disable_irq() to enforce synchronization.
3250 * * natsemi_poll: checks before reenabling interrupts. suspend
3251 * sets hands_off, disables interrupts and then waits with
3252 * napi_disable().
3253 *
3254 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3255 */
3256
3257 static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3258 {
3259 struct net_device *dev = pci_get_drvdata (pdev);
3260 struct netdev_private *np = netdev_priv(dev);
3261 void __iomem * ioaddr = ns_ioaddr(dev);
3262
3263 rtnl_lock();
3264 if (netif_running (dev)) {
3265 const int irq = np->pci_dev->irq;
3266
3267 del_timer_sync(&np->timer);
3268
3269 disable_irq(irq);
3270 spin_lock_irq(&np->lock);
3271
3272 natsemi_irq_disable(dev);
3273 np->hands_off = 1;
3274 natsemi_stop_rxtx(dev);
3275 netif_stop_queue(dev);
3276
3277 spin_unlock_irq(&np->lock);
3278 enable_irq(irq);
3279
3280 napi_disable(&np->napi);
3281
3282 /* Update the error counts. */
3283 __get_stats(dev);
3284
3285 /* pci_power_off(pdev, -1); */
3286 drain_ring(dev);
3287 {
3288 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3289 /* Restore PME enable bit */
3290 if (wol) {
3291 /* restart the NIC in WOL mode.
3292 * The nic must be stopped for this.
3293 * FIXME: use the WOL interrupt
3294 */
3295 enable_wol_mode(dev, 0);
3296 } else {
3297 /* Restore PME enable bit unmolested */
3298 writel(np->SavedClkRun, ioaddr + ClkRun);
3299 }
3300 }
3301 }
3302 netif_device_detach(dev);
3303 rtnl_unlock();
3304 return 0;
3305 }
3306
3307
3308 static int natsemi_resume (struct pci_dev *pdev)
3309 {
3310 struct net_device *dev = pci_get_drvdata (pdev);
3311 struct netdev_private *np = netdev_priv(dev);
3312 int ret = 0;
3313
3314 rtnl_lock();
3315 if (netif_device_present(dev))
3316 goto out;
3317 if (netif_running(dev)) {
3318 const int irq = np->pci_dev->irq;
3319
3320 BUG_ON(!np->hands_off);
3321 ret = pci_enable_device(pdev);
3322 if (ret < 0) {
3323 dev_err(&pdev->dev,
3324 "pci_enable_device() failed: %d\n", ret);
3325 goto out;
3326 }
3327 /* pci_power_on(pdev); */
3328
3329 napi_enable(&np->napi);
3330
3331 natsemi_reset(dev);
3332 init_ring(dev);
3333 disable_irq(irq);
3334 spin_lock_irq(&np->lock);
3335 np->hands_off = 0;
3336 init_registers(dev);
3337 netif_device_attach(dev);
3338 spin_unlock_irq(&np->lock);
3339 enable_irq(irq);
3340
3341 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ));
3342 }
3343 netif_device_attach(dev);
3344 out:
3345 rtnl_unlock();
3346 return ret;
3347 }
3348
3349 #endif /* CONFIG_PM */
3350
3351 static struct pci_driver natsemi_driver = {
3352 .name = DRV_NAME,
3353 .id_table = natsemi_pci_tbl,
3354 .probe = natsemi_probe1,
3355 .remove = natsemi_remove1,
3356 #ifdef CONFIG_PM
3357 .suspend = natsemi_suspend,
3358 .resume = natsemi_resume,
3359 #endif
3360 };
3361
3362 static int __init natsemi_init_mod (void)
3363 {
3364 /* when a module, this is printed whether or not devices are found in probe */
3365 #ifdef MODULE
3366 printk(version);
3367 #endif
3368
3369 return pci_register_driver(&natsemi_driver);
3370 }
3371
3372 static void __exit natsemi_exit_mod (void)
3373 {
3374 pci_unregister_driver (&natsemi_driver);
3375 }
3376
3377 module_init(natsemi_init_mod);
3378 module_exit(natsemi_exit_mod);
3379
Linux kernel - Deliverables
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