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Merge tag 'sound-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
[deliverable/linux.git] / drivers / net / ethernet / natsemi / ns83820.c
1 #define VERSION "0.23"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/workqueue.h>
108 #include <linux/init.h>
109 #include <linux/interrupt.h>
110 #include <linux/ip.h> /* for iph */
111 #include <linux/in.h> /* for IPPROTO_... */
112 #include <linux/compiler.h>
113 #include <linux/prefetch.h>
114 #include <linux/ethtool.h>
115 #include <linux/sched.h>
116 #include <linux/timer.h>
117 #include <linux/if_vlan.h>
118 #include <linux/rtnetlink.h>
119 #include <linux/jiffies.h>
120 #include <linux/slab.h>
121
122 #include <asm/io.h>
123 #include <asm/uaccess.h>
124
125 #define DRV_NAME "ns83820"
126
127 /* Global parameters. See module_param near the bottom. */
128 static int ihr = 2;
129 static int reset_phy = 0;
130 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
131
132 /* Dprintk is used for more interesting debug events */
133 #undef Dprintk
134 #define Dprintk dprintk
135
136 /* tunables */
137 #define RX_BUF_SIZE 1500 /* 8192 */
138 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
139 #define NS83820_VLAN_ACCEL_SUPPORT
140 #endif
141
142 /* Must not exceed ~65000. */
143 #define NR_RX_DESC 64
144 #define NR_TX_DESC 128
145
146 /* not tunable */
147 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
148
149 #define MIN_TX_DESC_FREE 8
150
151 /* register defines */
152 #define CFGCS 0x04
153
154 #define CR_TXE 0x00000001
155 #define CR_TXD 0x00000002
156 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
157 * The Receive engine skips one descriptor and moves
158 * onto the next one!! */
159 #define CR_RXE 0x00000004
160 #define CR_RXD 0x00000008
161 #define CR_TXR 0x00000010
162 #define CR_RXR 0x00000020
163 #define CR_SWI 0x00000080
164 #define CR_RST 0x00000100
165
166 #define PTSCR_EEBIST_FAIL 0x00000001
167 #define PTSCR_EEBIST_EN 0x00000002
168 #define PTSCR_EELOAD_EN 0x00000004
169 #define PTSCR_RBIST_FAIL 0x000001b8
170 #define PTSCR_RBIST_DONE 0x00000200
171 #define PTSCR_RBIST_EN 0x00000400
172 #define PTSCR_RBIST_RST 0x00002000
173
174 #define MEAR_EEDI 0x00000001
175 #define MEAR_EEDO 0x00000002
176 #define MEAR_EECLK 0x00000004
177 #define MEAR_EESEL 0x00000008
178 #define MEAR_MDIO 0x00000010
179 #define MEAR_MDDIR 0x00000020
180 #define MEAR_MDC 0x00000040
181
182 #define ISR_TXDESC3 0x40000000
183 #define ISR_TXDESC2 0x20000000
184 #define ISR_TXDESC1 0x10000000
185 #define ISR_TXDESC0 0x08000000
186 #define ISR_RXDESC3 0x04000000
187 #define ISR_RXDESC2 0x02000000
188 #define ISR_RXDESC1 0x01000000
189 #define ISR_RXDESC0 0x00800000
190 #define ISR_TXRCMP 0x00400000
191 #define ISR_RXRCMP 0x00200000
192 #define ISR_DPERR 0x00100000
193 #define ISR_SSERR 0x00080000
194 #define ISR_RMABT 0x00040000
195 #define ISR_RTABT 0x00020000
196 #define ISR_RXSOVR 0x00010000
197 #define ISR_HIBINT 0x00008000
198 #define ISR_PHY 0x00004000
199 #define ISR_PME 0x00002000
200 #define ISR_SWI 0x00001000
201 #define ISR_MIB 0x00000800
202 #define ISR_TXURN 0x00000400
203 #define ISR_TXIDLE 0x00000200
204 #define ISR_TXERR 0x00000100
205 #define ISR_TXDESC 0x00000080
206 #define ISR_TXOK 0x00000040
207 #define ISR_RXORN 0x00000020
208 #define ISR_RXIDLE 0x00000010
209 #define ISR_RXEARLY 0x00000008
210 #define ISR_RXERR 0x00000004
211 #define ISR_RXDESC 0x00000002
212 #define ISR_RXOK 0x00000001
213
214 #define TXCFG_CSI 0x80000000
215 #define TXCFG_HBI 0x40000000
216 #define TXCFG_MLB 0x20000000
217 #define TXCFG_ATP 0x10000000
218 #define TXCFG_ECRETRY 0x00800000
219 #define TXCFG_BRST_DIS 0x00080000
220 #define TXCFG_MXDMA1024 0x00000000
221 #define TXCFG_MXDMA512 0x00700000
222 #define TXCFG_MXDMA256 0x00600000
223 #define TXCFG_MXDMA128 0x00500000
224 #define TXCFG_MXDMA64 0x00400000
225 #define TXCFG_MXDMA32 0x00300000
226 #define TXCFG_MXDMA16 0x00200000
227 #define TXCFG_MXDMA8 0x00100000
228
229 #define CFG_LNKSTS 0x80000000
230 #define CFG_SPDSTS 0x60000000
231 #define CFG_SPDSTS1 0x40000000
232 #define CFG_SPDSTS0 0x20000000
233 #define CFG_DUPSTS 0x10000000
234 #define CFG_TBI_EN 0x01000000
235 #define CFG_MODE_1000 0x00400000
236 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
237 * Read the Phy response and then configure the MAC accordingly */
238 #define CFG_AUTO_1000 0x00200000
239 #define CFG_PINT_CTL 0x001c0000
240 #define CFG_PINT_DUPSTS 0x00100000
241 #define CFG_PINT_LNKSTS 0x00080000
242 #define CFG_PINT_SPDSTS 0x00040000
243 #define CFG_TMRTEST 0x00020000
244 #define CFG_MRM_DIS 0x00010000
245 #define CFG_MWI_DIS 0x00008000
246 #define CFG_T64ADDR 0x00004000
247 #define CFG_PCI64_DET 0x00002000
248 #define CFG_DATA64_EN 0x00001000
249 #define CFG_M64ADDR 0x00000800
250 #define CFG_PHY_RST 0x00000400
251 #define CFG_PHY_DIS 0x00000200
252 #define CFG_EXTSTS_EN 0x00000100
253 #define CFG_REQALG 0x00000080
254 #define CFG_SB 0x00000040
255 #define CFG_POW 0x00000020
256 #define CFG_EXD 0x00000010
257 #define CFG_PESEL 0x00000008
258 #define CFG_BROM_DIS 0x00000004
259 #define CFG_EXT_125 0x00000002
260 #define CFG_BEM 0x00000001
261
262 #define EXTSTS_UDPPKT 0x00200000
263 #define EXTSTS_TCPPKT 0x00080000
264 #define EXTSTS_IPPKT 0x00020000
265 #define EXTSTS_VPKT 0x00010000
266 #define EXTSTS_VTG_MASK 0x0000ffff
267
268 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
269
270 #define MIBC_MIBS 0x00000008
271 #define MIBC_ACLR 0x00000004
272 #define MIBC_FRZ 0x00000002
273 #define MIBC_WRN 0x00000001
274
275 #define PCR_PSEN (1 << 31)
276 #define PCR_PS_MCAST (1 << 30)
277 #define PCR_PS_DA (1 << 29)
278 #define PCR_STHI_8 (3 << 23)
279 #define PCR_STLO_4 (1 << 23)
280 #define PCR_FFHI_8K (3 << 21)
281 #define PCR_FFLO_4K (1 << 21)
282 #define PCR_PAUSE_CNT 0xFFFE
283
284 #define RXCFG_AEP 0x80000000
285 #define RXCFG_ARP 0x40000000
286 #define RXCFG_STRIPCRC 0x20000000
287 #define RXCFG_RX_FD 0x10000000
288 #define RXCFG_ALP 0x08000000
289 #define RXCFG_AIRL 0x04000000
290 #define RXCFG_MXDMA512 0x00700000
291 #define RXCFG_DRTH 0x0000003e
292 #define RXCFG_DRTH0 0x00000002
293
294 #define RFCR_RFEN 0x80000000
295 #define RFCR_AAB 0x40000000
296 #define RFCR_AAM 0x20000000
297 #define RFCR_AAU 0x10000000
298 #define RFCR_APM 0x08000000
299 #define RFCR_APAT 0x07800000
300 #define RFCR_APAT3 0x04000000
301 #define RFCR_APAT2 0x02000000
302 #define RFCR_APAT1 0x01000000
303 #define RFCR_APAT0 0x00800000
304 #define RFCR_AARP 0x00400000
305 #define RFCR_MHEN 0x00200000
306 #define RFCR_UHEN 0x00100000
307 #define RFCR_ULM 0x00080000
308
309 #define VRCR_RUDPE 0x00000080
310 #define VRCR_RTCPE 0x00000040
311 #define VRCR_RIPE 0x00000020
312 #define VRCR_IPEN 0x00000010
313 #define VRCR_DUTF 0x00000008
314 #define VRCR_DVTF 0x00000004
315 #define VRCR_VTREN 0x00000002
316 #define VRCR_VTDEN 0x00000001
317
318 #define VTCR_PPCHK 0x00000008
319 #define VTCR_GCHK 0x00000004
320 #define VTCR_VPPTI 0x00000002
321 #define VTCR_VGTI 0x00000001
322
323 #define CR 0x00
324 #define CFG 0x04
325 #define MEAR 0x08
326 #define PTSCR 0x0c
327 #define ISR 0x10
328 #define IMR 0x14
329 #define IER 0x18
330 #define IHR 0x1c
331 #define TXDP 0x20
332 #define TXDP_HI 0x24
333 #define TXCFG 0x28
334 #define GPIOR 0x2c
335 #define RXDP 0x30
336 #define RXDP_HI 0x34
337 #define RXCFG 0x38
338 #define PQCR 0x3c
339 #define WCSR 0x40
340 #define PCR 0x44
341 #define RFCR 0x48
342 #define RFDR 0x4c
343
344 #define SRR 0x58
345
346 #define VRCR 0xbc
347 #define VTCR 0xc0
348 #define VDR 0xc4
349 #define CCSR 0xcc
350
351 #define TBICR 0xe0
352 #define TBISR 0xe4
353 #define TANAR 0xe8
354 #define TANLPAR 0xec
355 #define TANER 0xf0
356 #define TESR 0xf4
357
358 #define TBICR_MR_AN_ENABLE 0x00001000
359 #define TBICR_MR_RESTART_AN 0x00000200
360
361 #define TBISR_MR_LINK_STATUS 0x00000020
362 #define TBISR_MR_AN_COMPLETE 0x00000004
363
364 #define TANAR_PS2 0x00000100
365 #define TANAR_PS1 0x00000080
366 #define TANAR_HALF_DUP 0x00000040
367 #define TANAR_FULL_DUP 0x00000020
368
369 #define GPIOR_GP5_OE 0x00000200
370 #define GPIOR_GP4_OE 0x00000100
371 #define GPIOR_GP3_OE 0x00000080
372 #define GPIOR_GP2_OE 0x00000040
373 #define GPIOR_GP1_OE 0x00000020
374 #define GPIOR_GP3_OUT 0x00000004
375 #define GPIOR_GP1_OUT 0x00000001
376
377 #define LINK_AUTONEGOTIATE 0x01
378 #define LINK_DOWN 0x02
379 #define LINK_UP 0x04
380
381 #define HW_ADDR_LEN sizeof(dma_addr_t)
382 #define desc_addr_set(desc, addr) \
383 do { \
384 ((desc)[0] = cpu_to_le32(addr)); \
385 if (HW_ADDR_LEN == 8) \
386 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
387 } while(0)
388 #define desc_addr_get(desc) \
389 (le32_to_cpu((desc)[0]) | \
390 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
391
392 #define DESC_LINK 0
393 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
394 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
395 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
396
397 #define CMDSTS_OWN 0x80000000
398 #define CMDSTS_MORE 0x40000000
399 #define CMDSTS_INTR 0x20000000
400 #define CMDSTS_ERR 0x10000000
401 #define CMDSTS_OK 0x08000000
402 #define CMDSTS_RUNT 0x00200000
403 #define CMDSTS_LEN_MASK 0x0000ffff
404
405 #define CMDSTS_DEST_MASK 0x01800000
406 #define CMDSTS_DEST_SELF 0x00800000
407 #define CMDSTS_DEST_MULTI 0x01000000
408
409 #define DESC_SIZE 8 /* Should be cache line sized */
410
411 struct rx_info {
412 spinlock_t lock;
413 int up;
414 unsigned long idle;
415
416 struct sk_buff *skbs[NR_RX_DESC];
417
418 __le32 *next_rx_desc;
419 u16 next_rx, next_empty;
420
421 __le32 *descs;
422 dma_addr_t phy_descs;
423 };
424
425
426 struct ns83820 {
427 u8 __iomem *base;
428
429 struct pci_dev *pci_dev;
430 struct net_device *ndev;
431
432 struct rx_info rx_info;
433 struct tasklet_struct rx_tasklet;
434
435 unsigned ihr;
436 struct work_struct tq_refill;
437
438 /* protects everything below. irqsave when using. */
439 spinlock_t misc_lock;
440
441 u32 CFG_cache;
442
443 u32 MEAR_cache;
444 u32 IMR_cache;
445
446 unsigned linkstate;
447
448 spinlock_t tx_lock;
449
450 u16 tx_done_idx;
451 u16 tx_idx;
452 volatile u16 tx_free_idx; /* idx of free desc chain */
453 u16 tx_intr_idx;
454
455 atomic_t nr_tx_skbs;
456 struct sk_buff *tx_skbs[NR_TX_DESC];
457
458 char pad[16] __attribute__((aligned(16)));
459 __le32 *tx_descs;
460 dma_addr_t tx_phy_descs;
461
462 struct timer_list tx_watchdog;
463 };
464
465 static inline struct ns83820 *PRIV(struct net_device *dev)
466 {
467 return netdev_priv(dev);
468 }
469
470 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
471
472 static inline void kick_rx(struct net_device *ndev)
473 {
474 struct ns83820 *dev = PRIV(ndev);
475 dprintk("kick_rx: maybe kicking\n");
476 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
477 dprintk("actually kicking\n");
478 writel(dev->rx_info.phy_descs +
479 (4 * DESC_SIZE * dev->rx_info.next_rx),
480 dev->base + RXDP);
481 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
482 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
483 ndev->name);
484 __kick_rx(dev);
485 }
486 }
487
488 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
489 #define start_tx_okay(dev) \
490 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
491
492 /* Packet Receiver
493 *
494 * The hardware supports linked lists of receive descriptors for
495 * which ownership is transferred back and forth by means of an
496 * ownership bit. While the hardware does support the use of a
497 * ring for receive descriptors, we only make use of a chain in
498 * an attempt to reduce bus traffic under heavy load scenarios.
499 * This will also make bugs a bit more obvious. The current code
500 * only makes use of a single rx chain; I hope to implement
501 * priority based rx for version 1.0. Goal: even under overload
502 * conditions, still route realtime traffic with as low jitter as
503 * possible.
504 */
505 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
506 {
507 desc_addr_set(desc + DESC_LINK, link);
508 desc_addr_set(desc + DESC_BUFPTR, buf);
509 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
510 mb();
511 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
512 }
513
514 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
515 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
516 {
517 unsigned next_empty;
518 u32 cmdsts;
519 __le32 *sg;
520 dma_addr_t buf;
521
522 next_empty = dev->rx_info.next_empty;
523
524 /* don't overrun last rx marker */
525 if (unlikely(nr_rx_empty(dev) <= 2)) {
526 kfree_skb(skb);
527 return 1;
528 }
529
530 #if 0
531 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
532 dev->rx_info.next_empty,
533 dev->rx_info.nr_used,
534 dev->rx_info.next_rx
535 );
536 #endif
537
538 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
539 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
540 dev->rx_info.skbs[next_empty] = skb;
541
542 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
543 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
544 buf = pci_map_single(dev->pci_dev, skb->data,
545 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
546 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
547 /* update link of previous rx */
548 if (likely(next_empty != dev->rx_info.next_rx))
549 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
550
551 return 0;
552 }
553
554 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
555 {
556 struct ns83820 *dev = PRIV(ndev);
557 unsigned i;
558 unsigned long flags = 0;
559
560 if (unlikely(nr_rx_empty(dev) <= 2))
561 return 0;
562
563 dprintk("rx_refill(%p)\n", ndev);
564 if (gfp == GFP_ATOMIC)
565 spin_lock_irqsave(&dev->rx_info.lock, flags);
566 for (i=0; i<NR_RX_DESC; i++) {
567 struct sk_buff *skb;
568 long res;
569
570 /* extra 16 bytes for alignment */
571 skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
572 if (unlikely(!skb))
573 break;
574
575 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
576 if (gfp != GFP_ATOMIC)
577 spin_lock_irqsave(&dev->rx_info.lock, flags);
578 res = ns83820_add_rx_skb(dev, skb);
579 if (gfp != GFP_ATOMIC)
580 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
581 if (res) {
582 i = 1;
583 break;
584 }
585 }
586 if (gfp == GFP_ATOMIC)
587 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
588
589 return i ? 0 : -ENOMEM;
590 }
591
592 static void rx_refill_atomic(struct net_device *ndev)
593 {
594 rx_refill(ndev, GFP_ATOMIC);
595 }
596
597 /* REFILL */
598 static inline void queue_refill(struct work_struct *work)
599 {
600 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
601 struct net_device *ndev = dev->ndev;
602
603 rx_refill(ndev, GFP_KERNEL);
604 if (dev->rx_info.up)
605 kick_rx(ndev);
606 }
607
608 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
609 {
610 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
611 }
612
613 static void phy_intr(struct net_device *ndev)
614 {
615 struct ns83820 *dev = PRIV(ndev);
616 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
617 u32 cfg, new_cfg;
618 u32 tbisr, tanar, tanlpar;
619 int speed, fullduplex, newlinkstate;
620
621 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
622
623 if (dev->CFG_cache & CFG_TBI_EN) {
624 /* we have an optical transceiver */
625 tbisr = readl(dev->base + TBISR);
626 tanar = readl(dev->base + TANAR);
627 tanlpar = readl(dev->base + TANLPAR);
628 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
629 tbisr, tanar, tanlpar);
630
631 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) &&
632 (tanar & TANAR_FULL_DUP)) ) {
633
634 /* both of us are full duplex */
635 writel(readl(dev->base + TXCFG)
636 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
637 dev->base + TXCFG);
638 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
639 dev->base + RXCFG);
640 /* Light up full duplex LED */
641 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
642 dev->base + GPIOR);
643
644 } else if (((tanlpar & TANAR_HALF_DUP) &&
645 (tanar & TANAR_HALF_DUP)) ||
646 ((tanlpar & TANAR_FULL_DUP) &&
647 (tanar & TANAR_HALF_DUP)) ||
648 ((tanlpar & TANAR_HALF_DUP) &&
649 (tanar & TANAR_FULL_DUP))) {
650
651 /* one or both of us are half duplex */
652 writel((readl(dev->base + TXCFG)
653 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
654 dev->base + TXCFG);
655 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
656 dev->base + RXCFG);
657 /* Turn off full duplex LED */
658 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
659 dev->base + GPIOR);
660 }
661
662 speed = 4; /* 1000F */
663
664 } else {
665 /* we have a copper transceiver */
666 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
667
668 if (cfg & CFG_SPDSTS1)
669 new_cfg |= CFG_MODE_1000;
670 else
671 new_cfg &= ~CFG_MODE_1000;
672
673 speed = ((cfg / CFG_SPDSTS0) & 3);
674 fullduplex = (cfg & CFG_DUPSTS);
675
676 if (fullduplex) {
677 new_cfg |= CFG_SB;
678 writel(readl(dev->base + TXCFG)
679 | TXCFG_CSI | TXCFG_HBI,
680 dev->base + TXCFG);
681 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
682 dev->base + RXCFG);
683 } else {
684 writel(readl(dev->base + TXCFG)
685 & ~(TXCFG_CSI | TXCFG_HBI),
686 dev->base + TXCFG);
687 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
688 dev->base + RXCFG);
689 }
690
691 if ((cfg & CFG_LNKSTS) &&
692 ((new_cfg ^ dev->CFG_cache) != 0)) {
693 writel(new_cfg, dev->base + CFG);
694 dev->CFG_cache = new_cfg;
695 }
696
697 dev->CFG_cache &= ~CFG_SPDSTS;
698 dev->CFG_cache |= cfg & CFG_SPDSTS;
699 }
700
701 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
702
703 if (newlinkstate & LINK_UP &&
704 dev->linkstate != newlinkstate) {
705 netif_start_queue(ndev);
706 netif_wake_queue(ndev);
707 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
708 ndev->name,
709 speeds[speed],
710 fullduplex ? "full" : "half");
711 } else if (newlinkstate & LINK_DOWN &&
712 dev->linkstate != newlinkstate) {
713 netif_stop_queue(ndev);
714 printk(KERN_INFO "%s: link now down.\n", ndev->name);
715 }
716
717 dev->linkstate = newlinkstate;
718 }
719
720 static int ns83820_setup_rx(struct net_device *ndev)
721 {
722 struct ns83820 *dev = PRIV(ndev);
723 unsigned i;
724 int ret;
725
726 dprintk("ns83820_setup_rx(%p)\n", ndev);
727
728 dev->rx_info.idle = 1;
729 dev->rx_info.next_rx = 0;
730 dev->rx_info.next_rx_desc = dev->rx_info.descs;
731 dev->rx_info.next_empty = 0;
732
733 for (i=0; i<NR_RX_DESC; i++)
734 clear_rx_desc(dev, i);
735
736 writel(0, dev->base + RXDP_HI);
737 writel(dev->rx_info.phy_descs, dev->base + RXDP);
738
739 ret = rx_refill(ndev, GFP_KERNEL);
740 if (!ret) {
741 dprintk("starting receiver\n");
742 /* prevent the interrupt handler from stomping on us */
743 spin_lock_irq(&dev->rx_info.lock);
744
745 writel(0x0001, dev->base + CCSR);
746 writel(0, dev->base + RFCR);
747 writel(0x7fc00000, dev->base + RFCR);
748 writel(0xffc00000, dev->base + RFCR);
749
750 dev->rx_info.up = 1;
751
752 phy_intr(ndev);
753
754 /* Okay, let it rip */
755 spin_lock(&dev->misc_lock);
756 dev->IMR_cache |= ISR_PHY;
757 dev->IMR_cache |= ISR_RXRCMP;
758 //dev->IMR_cache |= ISR_RXERR;
759 //dev->IMR_cache |= ISR_RXOK;
760 dev->IMR_cache |= ISR_RXORN;
761 dev->IMR_cache |= ISR_RXSOVR;
762 dev->IMR_cache |= ISR_RXDESC;
763 dev->IMR_cache |= ISR_RXIDLE;
764 dev->IMR_cache |= ISR_TXDESC;
765 dev->IMR_cache |= ISR_TXIDLE;
766
767 writel(dev->IMR_cache, dev->base + IMR);
768 writel(1, dev->base + IER);
769 spin_unlock(&dev->misc_lock);
770
771 kick_rx(ndev);
772
773 spin_unlock_irq(&dev->rx_info.lock);
774 }
775 return ret;
776 }
777
778 static void ns83820_cleanup_rx(struct ns83820 *dev)
779 {
780 unsigned i;
781 unsigned long flags;
782
783 dprintk("ns83820_cleanup_rx(%p)\n", dev);
784
785 /* disable receive interrupts */
786 spin_lock_irqsave(&dev->misc_lock, flags);
787 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
788 writel(dev->IMR_cache, dev->base + IMR);
789 spin_unlock_irqrestore(&dev->misc_lock, flags);
790
791 /* synchronize with the interrupt handler and kill it */
792 dev->rx_info.up = 0;
793 synchronize_irq(dev->pci_dev->irq);
794
795 /* touch the pci bus... */
796 readl(dev->base + IMR);
797
798 /* assumes the transmitter is already disabled and reset */
799 writel(0, dev->base + RXDP_HI);
800 writel(0, dev->base + RXDP);
801
802 for (i=0; i<NR_RX_DESC; i++) {
803 struct sk_buff *skb = dev->rx_info.skbs[i];
804 dev->rx_info.skbs[i] = NULL;
805 clear_rx_desc(dev, i);
806 kfree_skb(skb);
807 }
808 }
809
810 static void ns83820_rx_kick(struct net_device *ndev)
811 {
812 struct ns83820 *dev = PRIV(ndev);
813 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
814 if (dev->rx_info.up) {
815 rx_refill_atomic(ndev);
816 kick_rx(ndev);
817 }
818 }
819
820 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
821 schedule_work(&dev->tq_refill);
822 else
823 kick_rx(ndev);
824 if (dev->rx_info.idle)
825 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
826 }
827
828 /* rx_irq
829 *
830 */
831 static void rx_irq(struct net_device *ndev)
832 {
833 struct ns83820 *dev = PRIV(ndev);
834 struct rx_info *info = &dev->rx_info;
835 unsigned next_rx;
836 int rx_rc, len;
837 u32 cmdsts;
838 __le32 *desc;
839 unsigned long flags;
840 int nr = 0;
841
842 dprintk("rx_irq(%p)\n", ndev);
843 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
844 readl(dev->base + RXDP),
845 (long)(dev->rx_info.phy_descs),
846 (int)dev->rx_info.next_rx,
847 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
848 (int)dev->rx_info.next_empty,
849 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
850 );
851
852 spin_lock_irqsave(&info->lock, flags);
853 if (!info->up)
854 goto out;
855
856 dprintk("walking descs\n");
857 next_rx = info->next_rx;
858 desc = info->next_rx_desc;
859 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
860 (cmdsts != CMDSTS_OWN)) {
861 struct sk_buff *skb;
862 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
863 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
864
865 dprintk("cmdsts: %08x\n", cmdsts);
866 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
867 dprintk("extsts: %08x\n", extsts);
868
869 skb = info->skbs[next_rx];
870 info->skbs[next_rx] = NULL;
871 info->next_rx = (next_rx + 1) % NR_RX_DESC;
872
873 mb();
874 clear_rx_desc(dev, next_rx);
875
876 pci_unmap_single(dev->pci_dev, bufptr,
877 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
878 len = cmdsts & CMDSTS_LEN_MASK;
879 #ifdef NS83820_VLAN_ACCEL_SUPPORT
880 /* NH: As was mentioned below, this chip is kinda
881 * brain dead about vlan tag stripping. Frames
882 * that are 64 bytes with a vlan header appended
883 * like arp frames, or pings, are flagged as Runts
884 * when the tag is stripped and hardware. This
885 * also means that the OK bit in the descriptor
886 * is cleared when the frame comes in so we have
887 * to do a specific length check here to make sure
888 * the frame would have been ok, had we not stripped
889 * the tag.
890 */
891 if (likely((CMDSTS_OK & cmdsts) ||
892 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
893 #else
894 if (likely(CMDSTS_OK & cmdsts)) {
895 #endif
896 skb_put(skb, len);
897 if (unlikely(!skb))
898 goto netdev_mangle_me_harder_failed;
899 if (cmdsts & CMDSTS_DEST_MULTI)
900 ndev->stats.multicast++;
901 ndev->stats.rx_packets++;
902 ndev->stats.rx_bytes += len;
903 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
904 skb->ip_summed = CHECKSUM_UNNECESSARY;
905 } else {
906 skb_checksum_none_assert(skb);
907 }
908 skb->protocol = eth_type_trans(skb, ndev);
909 #ifdef NS83820_VLAN_ACCEL_SUPPORT
910 if(extsts & EXTSTS_VPKT) {
911 unsigned short tag;
912
913 tag = ntohs(extsts & EXTSTS_VTG_MASK);
914 __vlan_hwaccel_put_tag(skb, tag);
915 }
916 #endif
917 rx_rc = netif_rx(skb);
918 if (NET_RX_DROP == rx_rc) {
919 netdev_mangle_me_harder_failed:
920 ndev->stats.rx_dropped++;
921 }
922 } else {
923 kfree_skb(skb);
924 }
925
926 nr++;
927 next_rx = info->next_rx;
928 desc = info->descs + (DESC_SIZE * next_rx);
929 }
930 info->next_rx = next_rx;
931 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
932
933 out:
934 if (0 && !nr) {
935 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
936 }
937
938 spin_unlock_irqrestore(&info->lock, flags);
939 }
940
941 static void rx_action(unsigned long _dev)
942 {
943 struct net_device *ndev = (void *)_dev;
944 struct ns83820 *dev = PRIV(ndev);
945 rx_irq(ndev);
946 writel(ihr, dev->base + IHR);
947
948 spin_lock_irq(&dev->misc_lock);
949 dev->IMR_cache |= ISR_RXDESC;
950 writel(dev->IMR_cache, dev->base + IMR);
951 spin_unlock_irq(&dev->misc_lock);
952
953 rx_irq(ndev);
954 ns83820_rx_kick(ndev);
955 }
956
957 /* Packet Transmit code
958 */
959 static inline void kick_tx(struct ns83820 *dev)
960 {
961 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
962 dev, dev->tx_idx, dev->tx_free_idx);
963 writel(CR_TXE, dev->base + CR);
964 }
965
966 /* No spinlock needed on the transmit irq path as the interrupt handler is
967 * serialized.
968 */
969 static void do_tx_done(struct net_device *ndev)
970 {
971 struct ns83820 *dev = PRIV(ndev);
972 u32 cmdsts, tx_done_idx;
973 __le32 *desc;
974
975 dprintk("do_tx_done(%p)\n", ndev);
976 tx_done_idx = dev->tx_done_idx;
977 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
978
979 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
980 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
981 while ((tx_done_idx != dev->tx_free_idx) &&
982 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
983 struct sk_buff *skb;
984 unsigned len;
985 dma_addr_t addr;
986
987 if (cmdsts & CMDSTS_ERR)
988 ndev->stats.tx_errors++;
989 if (cmdsts & CMDSTS_OK)
990 ndev->stats.tx_packets++;
991 if (cmdsts & CMDSTS_OK)
992 ndev->stats.tx_bytes += cmdsts & 0xffff;
993
994 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
995 tx_done_idx, dev->tx_free_idx, cmdsts);
996 skb = dev->tx_skbs[tx_done_idx];
997 dev->tx_skbs[tx_done_idx] = NULL;
998 dprintk("done(%p)\n", skb);
999
1000 len = cmdsts & CMDSTS_LEN_MASK;
1001 addr = desc_addr_get(desc + DESC_BUFPTR);
1002 if (skb) {
1003 pci_unmap_single(dev->pci_dev,
1004 addr,
1005 len,
1006 PCI_DMA_TODEVICE);
1007 dev_kfree_skb_irq(skb);
1008 atomic_dec(&dev->nr_tx_skbs);
1009 } else
1010 pci_unmap_page(dev->pci_dev,
1011 addr,
1012 len,
1013 PCI_DMA_TODEVICE);
1014
1015 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1016 dev->tx_done_idx = tx_done_idx;
1017 desc[DESC_CMDSTS] = cpu_to_le32(0);
1018 mb();
1019 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1020 }
1021
1022 /* Allow network stack to resume queueing packets after we've
1023 * finished transmitting at least 1/4 of the packets in the queue.
1024 */
1025 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1026 dprintk("start_queue(%p)\n", ndev);
1027 netif_start_queue(ndev);
1028 netif_wake_queue(ndev);
1029 }
1030 }
1031
1032 static void ns83820_cleanup_tx(struct ns83820 *dev)
1033 {
1034 unsigned i;
1035
1036 for (i=0; i<NR_TX_DESC; i++) {
1037 struct sk_buff *skb = dev->tx_skbs[i];
1038 dev->tx_skbs[i] = NULL;
1039 if (skb) {
1040 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1041 pci_unmap_single(dev->pci_dev,
1042 desc_addr_get(desc + DESC_BUFPTR),
1043 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1044 PCI_DMA_TODEVICE);
1045 dev_kfree_skb_irq(skb);
1046 atomic_dec(&dev->nr_tx_skbs);
1047 }
1048 }
1049
1050 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1051 }
1052
1053 /* transmit routine. This code relies on the network layer serializing
1054 * its calls in, but will run happily in parallel with the interrupt
1055 * handler. This code currently has provisions for fragmenting tx buffers
1056 * while trying to track down a bug in either the zero copy code or
1057 * the tx fifo (hence the MAX_FRAG_LEN).
1058 */
1059 static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb,
1060 struct net_device *ndev)
1061 {
1062 struct ns83820 *dev = PRIV(ndev);
1063 u32 free_idx, cmdsts, extsts;
1064 int nr_free, nr_frags;
1065 unsigned tx_done_idx, last_idx;
1066 dma_addr_t buf;
1067 unsigned len;
1068 skb_frag_t *frag;
1069 int stopped = 0;
1070 int do_intr = 0;
1071 volatile __le32 *first_desc;
1072
1073 dprintk("ns83820_hard_start_xmit\n");
1074
1075 nr_frags = skb_shinfo(skb)->nr_frags;
1076 again:
1077 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1078 netif_stop_queue(ndev);
1079 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1080 return NETDEV_TX_BUSY;
1081 netif_start_queue(ndev);
1082 }
1083
1084 last_idx = free_idx = dev->tx_free_idx;
1085 tx_done_idx = dev->tx_done_idx;
1086 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1087 nr_free -= 1;
1088 if (nr_free <= nr_frags) {
1089 dprintk("stop_queue - not enough(%p)\n", ndev);
1090 netif_stop_queue(ndev);
1091
1092 /* Check again: we may have raced with a tx done irq */
1093 if (dev->tx_done_idx != tx_done_idx) {
1094 dprintk("restart queue(%p)\n", ndev);
1095 netif_start_queue(ndev);
1096 goto again;
1097 }
1098 return NETDEV_TX_BUSY;
1099 }
1100
1101 if (free_idx == dev->tx_intr_idx) {
1102 do_intr = 1;
1103 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1104 }
1105
1106 nr_free -= nr_frags;
1107 if (nr_free < MIN_TX_DESC_FREE) {
1108 dprintk("stop_queue - last entry(%p)\n", ndev);
1109 netif_stop_queue(ndev);
1110 stopped = 1;
1111 }
1112
1113 frag = skb_shinfo(skb)->frags;
1114 if (!nr_frags)
1115 frag = NULL;
1116 extsts = 0;
1117 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1118 extsts |= EXTSTS_IPPKT;
1119 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1120 extsts |= EXTSTS_TCPPKT;
1121 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1122 extsts |= EXTSTS_UDPPKT;
1123 }
1124
1125 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1126 if(vlan_tx_tag_present(skb)) {
1127 /* fetch the vlan tag info out of the
1128 * ancillary data if the vlan code
1129 * is using hw vlan acceleration
1130 */
1131 short tag = vlan_tx_tag_get(skb);
1132 extsts |= (EXTSTS_VPKT | htons(tag));
1133 }
1134 #endif
1135
1136 len = skb->len;
1137 if (nr_frags)
1138 len -= skb->data_len;
1139 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1140
1141 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1142
1143 for (;;) {
1144 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1145
1146 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1147 (unsigned long long)buf);
1148 last_idx = free_idx;
1149 free_idx = (free_idx + 1) % NR_TX_DESC;
1150 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1151 desc_addr_set(desc + DESC_BUFPTR, buf);
1152 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1153
1154 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1155 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1156 cmdsts |= len;
1157 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1158
1159 if (!nr_frags)
1160 break;
1161
1162 buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0,
1163 skb_frag_size(frag), DMA_TO_DEVICE);
1164 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1165 (long long)buf, (long) page_to_pfn(frag->page),
1166 frag->page_offset);
1167 len = skb_frag_size(frag);
1168 frag++;
1169 nr_frags--;
1170 }
1171 dprintk("done pkt\n");
1172
1173 spin_lock_irq(&dev->tx_lock);
1174 dev->tx_skbs[last_idx] = skb;
1175 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1176 dev->tx_free_idx = free_idx;
1177 atomic_inc(&dev->nr_tx_skbs);
1178 spin_unlock_irq(&dev->tx_lock);
1179
1180 kick_tx(dev);
1181
1182 /* Check again: we may have raced with a tx done irq */
1183 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1184 netif_start_queue(ndev);
1185
1186 return NETDEV_TX_OK;
1187 }
1188
1189 static void ns83820_update_stats(struct ns83820 *dev)
1190 {
1191 struct net_device *ndev = dev->ndev;
1192 u8 __iomem *base = dev->base;
1193
1194 /* the DP83820 will freeze counters, so we need to read all of them */
1195 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1196 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1197 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1198 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1199 /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1200 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1201 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1202 /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1203 /*ndev->stats.rx_pause_count += */ readl(base + 0x80);
1204 /*ndev->stats.tx_pause_count += */ readl(base + 0x84);
1205 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1206 }
1207
1208 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1209 {
1210 struct ns83820 *dev = PRIV(ndev);
1211
1212 /* somewhat overkill */
1213 spin_lock_irq(&dev->misc_lock);
1214 ns83820_update_stats(dev);
1215 spin_unlock_irq(&dev->misc_lock);
1216
1217 return &ndev->stats;
1218 }
1219
1220 /* Let ethtool retrieve info */
1221 static int ns83820_get_settings(struct net_device *ndev,
1222 struct ethtool_cmd *cmd)
1223 {
1224 struct ns83820 *dev = PRIV(ndev);
1225 u32 cfg, tanar, tbicr;
1226 int fullduplex = 0;
1227
1228 /*
1229 * Here's the list of available ethtool commands from other drivers:
1230 * cmd->advertising =
1231 * ethtool_cmd_speed_set(cmd, ...)
1232 * cmd->duplex =
1233 * cmd->port = 0;
1234 * cmd->phy_address =
1235 * cmd->transceiver = 0;
1236 * cmd->autoneg =
1237 * cmd->maxtxpkt = 0;
1238 * cmd->maxrxpkt = 0;
1239 */
1240
1241 /* read current configuration */
1242 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1243 tanar = readl(dev->base + TANAR);
1244 tbicr = readl(dev->base + TBICR);
1245
1246 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1247
1248 cmd->supported = SUPPORTED_Autoneg;
1249
1250 if (dev->CFG_cache & CFG_TBI_EN) {
1251 /* we have optical interface */
1252 cmd->supported |= SUPPORTED_1000baseT_Half |
1253 SUPPORTED_1000baseT_Full |
1254 SUPPORTED_FIBRE;
1255 cmd->port = PORT_FIBRE;
1256 } else {
1257 /* we have copper */
1258 cmd->supported |= SUPPORTED_10baseT_Half |
1259 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
1260 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half |
1261 SUPPORTED_1000baseT_Full |
1262 SUPPORTED_MII;
1263 cmd->port = PORT_MII;
1264 }
1265
1266 cmd->duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1267 switch (cfg / CFG_SPDSTS0 & 3) {
1268 case 2:
1269 ethtool_cmd_speed_set(cmd, SPEED_1000);
1270 break;
1271 case 1:
1272 ethtool_cmd_speed_set(cmd, SPEED_100);
1273 break;
1274 default:
1275 ethtool_cmd_speed_set(cmd, SPEED_10);
1276 break;
1277 }
1278 cmd->autoneg = (tbicr & TBICR_MR_AN_ENABLE)
1279 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1280 return 0;
1281 }
1282
1283 /* Let ethool change settings*/
1284 static int ns83820_set_settings(struct net_device *ndev,
1285 struct ethtool_cmd *cmd)
1286 {
1287 struct ns83820 *dev = PRIV(ndev);
1288 u32 cfg, tanar;
1289 int have_optical = 0;
1290 int fullduplex = 0;
1291
1292 /* read current configuration */
1293 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1294 tanar = readl(dev->base + TANAR);
1295
1296 if (dev->CFG_cache & CFG_TBI_EN) {
1297 /* we have optical */
1298 have_optical = 1;
1299 fullduplex = (tanar & TANAR_FULL_DUP);
1300
1301 } else {
1302 /* we have copper */
1303 fullduplex = cfg & CFG_DUPSTS;
1304 }
1305
1306 spin_lock_irq(&dev->misc_lock);
1307 spin_lock(&dev->tx_lock);
1308
1309 /* Set duplex */
1310 if (cmd->duplex != fullduplex) {
1311 if (have_optical) {
1312 /*set full duplex*/
1313 if (cmd->duplex == DUPLEX_FULL) {
1314 /* force full duplex */
1315 writel(readl(dev->base + TXCFG)
1316 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1317 dev->base + TXCFG);
1318 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1319 dev->base + RXCFG);
1320 /* Light up full duplex LED */
1321 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1322 dev->base + GPIOR);
1323 } else {
1324 /*TODO: set half duplex */
1325 }
1326
1327 } else {
1328 /*we have copper*/
1329 /* TODO: Set duplex for copper cards */
1330 }
1331 printk(KERN_INFO "%s: Duplex set via ethtool\n",
1332 ndev->name);
1333 }
1334
1335 /* Set autonegotiation */
1336 if (1) {
1337 if (cmd->autoneg == AUTONEG_ENABLE) {
1338 /* restart auto negotiation */
1339 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1340 dev->base + TBICR);
1341 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1342 dev->linkstate = LINK_AUTONEGOTIATE;
1343
1344 printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1345 ndev->name);
1346 } else {
1347 /* disable auto negotiation */
1348 writel(0x00000000, dev->base + TBICR);
1349 }
1350
1351 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1352 cmd->autoneg ? "ENABLED" : "DISABLED");
1353 }
1354
1355 phy_intr(ndev);
1356 spin_unlock(&dev->tx_lock);
1357 spin_unlock_irq(&dev->misc_lock);
1358
1359 return 0;
1360 }
1361 /* end ethtool get/set support -df */
1362
1363 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1364 {
1365 struct ns83820 *dev = PRIV(ndev);
1366 strlcpy(info->driver, "ns83820", sizeof(info->driver));
1367 strlcpy(info->version, VERSION, sizeof(info->version));
1368 strlcpy(info->bus_info, pci_name(dev->pci_dev), sizeof(info->bus_info));
1369 }
1370
1371 static u32 ns83820_get_link(struct net_device *ndev)
1372 {
1373 struct ns83820 *dev = PRIV(ndev);
1374 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1375 return cfg & CFG_LNKSTS ? 1 : 0;
1376 }
1377
1378 static const struct ethtool_ops ops = {
1379 .get_settings = ns83820_get_settings,
1380 .set_settings = ns83820_set_settings,
1381 .get_drvinfo = ns83820_get_drvinfo,
1382 .get_link = ns83820_get_link
1383 };
1384
1385 static inline void ns83820_disable_interrupts(struct ns83820 *dev)
1386 {
1387 writel(0, dev->base + IMR);
1388 writel(0, dev->base + IER);
1389 readl(dev->base + IER);
1390 }
1391
1392 /* this function is called in irq context from the ISR */
1393 static void ns83820_mib_isr(struct ns83820 *dev)
1394 {
1395 unsigned long flags;
1396 spin_lock_irqsave(&dev->misc_lock, flags);
1397 ns83820_update_stats(dev);
1398 spin_unlock_irqrestore(&dev->misc_lock, flags);
1399 }
1400
1401 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1402 static irqreturn_t ns83820_irq(int foo, void *data)
1403 {
1404 struct net_device *ndev = data;
1405 struct ns83820 *dev = PRIV(ndev);
1406 u32 isr;
1407 dprintk("ns83820_irq(%p)\n", ndev);
1408
1409 dev->ihr = 0;
1410
1411 isr = readl(dev->base + ISR);
1412 dprintk("irq: %08x\n", isr);
1413 ns83820_do_isr(ndev, isr);
1414 return IRQ_HANDLED;
1415 }
1416
1417 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1418 {
1419 struct ns83820 *dev = PRIV(ndev);
1420 unsigned long flags;
1421
1422 #ifdef DEBUG
1423 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1424 Dprintk("odd isr? 0x%08x\n", isr);
1425 #endif
1426
1427 if (ISR_RXIDLE & isr) {
1428 dev->rx_info.idle = 1;
1429 Dprintk("oh dear, we are idle\n");
1430 ns83820_rx_kick(ndev);
1431 }
1432
1433 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1434 prefetch(dev->rx_info.next_rx_desc);
1435
1436 spin_lock_irqsave(&dev->misc_lock, flags);
1437 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1438 writel(dev->IMR_cache, dev->base + IMR);
1439 spin_unlock_irqrestore(&dev->misc_lock, flags);
1440
1441 tasklet_schedule(&dev->rx_tasklet);
1442 //rx_irq(ndev);
1443 //writel(4, dev->base + IHR);
1444 }
1445
1446 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1447 ns83820_rx_kick(ndev);
1448
1449 if (unlikely(ISR_RXSOVR & isr)) {
1450 //printk("overrun: rxsovr\n");
1451 ndev->stats.rx_fifo_errors++;
1452 }
1453
1454 if (unlikely(ISR_RXORN & isr)) {
1455 //printk("overrun: rxorn\n");
1456 ndev->stats.rx_fifo_errors++;
1457 }
1458
1459 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1460 writel(CR_RXE, dev->base + CR);
1461
1462 if (ISR_TXIDLE & isr) {
1463 u32 txdp;
1464 txdp = readl(dev->base + TXDP);
1465 dprintk("txdp: %08x\n", txdp);
1466 txdp -= dev->tx_phy_descs;
1467 dev->tx_idx = txdp / (DESC_SIZE * 4);
1468 if (dev->tx_idx >= NR_TX_DESC) {
1469 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1470 dev->tx_idx = 0;
1471 }
1472 /* The may have been a race between a pci originated read
1473 * and the descriptor update from the cpu. Just in case,
1474 * kick the transmitter if the hardware thinks it is on a
1475 * different descriptor than we are.
1476 */
1477 if (dev->tx_idx != dev->tx_free_idx)
1478 kick_tx(dev);
1479 }
1480
1481 /* Defer tx ring processing until more than a minimum amount of
1482 * work has accumulated
1483 */
1484 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1485 spin_lock_irqsave(&dev->tx_lock, flags);
1486 do_tx_done(ndev);
1487 spin_unlock_irqrestore(&dev->tx_lock, flags);
1488
1489 /* Disable TxOk if there are no outstanding tx packets.
1490 */
1491 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1492 (dev->IMR_cache & ISR_TXOK)) {
1493 spin_lock_irqsave(&dev->misc_lock, flags);
1494 dev->IMR_cache &= ~ISR_TXOK;
1495 writel(dev->IMR_cache, dev->base + IMR);
1496 spin_unlock_irqrestore(&dev->misc_lock, flags);
1497 }
1498 }
1499
1500 /* The TxIdle interrupt can come in before the transmit has
1501 * completed. Normally we reap packets off of the combination
1502 * of TxDesc and TxIdle and leave TxOk disabled (since it
1503 * occurs on every packet), but when no further irqs of this
1504 * nature are expected, we must enable TxOk.
1505 */
1506 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1507 spin_lock_irqsave(&dev->misc_lock, flags);
1508 dev->IMR_cache |= ISR_TXOK;
1509 writel(dev->IMR_cache, dev->base + IMR);
1510 spin_unlock_irqrestore(&dev->misc_lock, flags);
1511 }
1512
1513 /* MIB interrupt: one of the statistics counters is about to overflow */
1514 if (unlikely(ISR_MIB & isr))
1515 ns83820_mib_isr(dev);
1516
1517 /* PHY: Link up/down/negotiation state change */
1518 if (unlikely(ISR_PHY & isr))
1519 phy_intr(ndev);
1520
1521 #if 0 /* Still working on the interrupt mitigation strategy */
1522 if (dev->ihr)
1523 writel(dev->ihr, dev->base + IHR);
1524 #endif
1525 }
1526
1527 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1528 {
1529 Dprintk("resetting chip...\n");
1530 writel(which, dev->base + CR);
1531 do {
1532 schedule();
1533 } while (readl(dev->base + CR) & which);
1534 Dprintk("okay!\n");
1535 }
1536
1537 static int ns83820_stop(struct net_device *ndev)
1538 {
1539 struct ns83820 *dev = PRIV(ndev);
1540
1541 /* FIXME: protect against interrupt handler? */
1542 del_timer_sync(&dev->tx_watchdog);
1543
1544 ns83820_disable_interrupts(dev);
1545
1546 dev->rx_info.up = 0;
1547 synchronize_irq(dev->pci_dev->irq);
1548
1549 ns83820_do_reset(dev, CR_RST);
1550
1551 synchronize_irq(dev->pci_dev->irq);
1552
1553 spin_lock_irq(&dev->misc_lock);
1554 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1555 spin_unlock_irq(&dev->misc_lock);
1556
1557 ns83820_cleanup_rx(dev);
1558 ns83820_cleanup_tx(dev);
1559
1560 return 0;
1561 }
1562
1563 static void ns83820_tx_timeout(struct net_device *ndev)
1564 {
1565 struct ns83820 *dev = PRIV(ndev);
1566 u32 tx_done_idx;
1567 __le32 *desc;
1568 unsigned long flags;
1569
1570 spin_lock_irqsave(&dev->tx_lock, flags);
1571
1572 tx_done_idx = dev->tx_done_idx;
1573 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1574
1575 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1576 ndev->name,
1577 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1578
1579 #if defined(DEBUG)
1580 {
1581 u32 isr;
1582 isr = readl(dev->base + ISR);
1583 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1584 ns83820_do_isr(ndev, isr);
1585 }
1586 #endif
1587
1588 do_tx_done(ndev);
1589
1590 tx_done_idx = dev->tx_done_idx;
1591 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1592
1593 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1594 ndev->name,
1595 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1596
1597 spin_unlock_irqrestore(&dev->tx_lock, flags);
1598 }
1599
1600 static void ns83820_tx_watch(unsigned long data)
1601 {
1602 struct net_device *ndev = (void *)data;
1603 struct ns83820 *dev = PRIV(ndev);
1604
1605 #if defined(DEBUG)
1606 printk("ns83820_tx_watch: %u %u %d\n",
1607 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1608 );
1609 #endif
1610
1611 if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) &&
1612 dev->tx_done_idx != dev->tx_free_idx) {
1613 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1614 ndev->name,
1615 dev->tx_done_idx, dev->tx_free_idx,
1616 atomic_read(&dev->nr_tx_skbs));
1617 ns83820_tx_timeout(ndev);
1618 }
1619
1620 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1621 }
1622
1623 static int ns83820_open(struct net_device *ndev)
1624 {
1625 struct ns83820 *dev = PRIV(ndev);
1626 unsigned i;
1627 u32 desc;
1628 int ret;
1629
1630 dprintk("ns83820_open\n");
1631
1632 writel(0, dev->base + PQCR);
1633
1634 ret = ns83820_setup_rx(ndev);
1635 if (ret)
1636 goto failed;
1637
1638 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1639 for (i=0; i<NR_TX_DESC; i++) {
1640 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1641 = cpu_to_le32(
1642 dev->tx_phy_descs
1643 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1644 }
1645
1646 dev->tx_idx = 0;
1647 dev->tx_done_idx = 0;
1648 desc = dev->tx_phy_descs;
1649 writel(0, dev->base + TXDP_HI);
1650 writel(desc, dev->base + TXDP);
1651
1652 init_timer(&dev->tx_watchdog);
1653 dev->tx_watchdog.data = (unsigned long)ndev;
1654 dev->tx_watchdog.function = ns83820_tx_watch;
1655 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1656
1657 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1658
1659 return 0;
1660
1661 failed:
1662 ns83820_stop(ndev);
1663 return ret;
1664 }
1665
1666 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1667 {
1668 unsigned i;
1669 for (i=0; i<3; i++) {
1670 u32 data;
1671
1672 /* Read from the perfect match memory: this is loaded by
1673 * the chip from the EEPROM via the EELOAD self test.
1674 */
1675 writel(i*2, dev->base + RFCR);
1676 data = readl(dev->base + RFDR);
1677
1678 *mac++ = data;
1679 *mac++ = data >> 8;
1680 }
1681 }
1682
1683 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1684 {
1685 if (new_mtu > RX_BUF_SIZE)
1686 return -EINVAL;
1687 ndev->mtu = new_mtu;
1688 return 0;
1689 }
1690
1691 static void ns83820_set_multicast(struct net_device *ndev)
1692 {
1693 struct ns83820 *dev = PRIV(ndev);
1694 u8 __iomem *rfcr = dev->base + RFCR;
1695 u32 and_mask = 0xffffffff;
1696 u32 or_mask = 0;
1697 u32 val;
1698
1699 if (ndev->flags & IFF_PROMISC)
1700 or_mask |= RFCR_AAU | RFCR_AAM;
1701 else
1702 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1703
1704 if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev))
1705 or_mask |= RFCR_AAM;
1706 else
1707 and_mask &= ~RFCR_AAM;
1708
1709 spin_lock_irq(&dev->misc_lock);
1710 val = (readl(rfcr) & and_mask) | or_mask;
1711 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1712 writel(val & ~RFCR_RFEN, rfcr);
1713 writel(val, rfcr);
1714 spin_unlock_irq(&dev->misc_lock);
1715 }
1716
1717 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1718 {
1719 struct ns83820 *dev = PRIV(ndev);
1720 int timed_out = 0;
1721 unsigned long start;
1722 u32 status;
1723 int loops = 0;
1724
1725 dprintk("%s: start %s\n", ndev->name, name);
1726
1727 start = jiffies;
1728
1729 writel(enable, dev->base + PTSCR);
1730 for (;;) {
1731 loops++;
1732 status = readl(dev->base + PTSCR);
1733 if (!(status & enable))
1734 break;
1735 if (status & done)
1736 break;
1737 if (status & fail)
1738 break;
1739 if (time_after_eq(jiffies, start + HZ)) {
1740 timed_out = 1;
1741 break;
1742 }
1743 schedule_timeout_uninterruptible(1);
1744 }
1745
1746 if (status & fail)
1747 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1748 ndev->name, name, status, fail);
1749 else if (timed_out)
1750 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1751 ndev->name, name, status);
1752
1753 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1754 }
1755
1756 #ifdef PHY_CODE_IS_FINISHED
1757 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1758 {
1759 /* drive MDC low */
1760 dev->MEAR_cache &= ~MEAR_MDC;
1761 writel(dev->MEAR_cache, dev->base + MEAR);
1762 readl(dev->base + MEAR);
1763
1764 /* enable output, set bit */
1765 dev->MEAR_cache |= MEAR_MDDIR;
1766 if (bit)
1767 dev->MEAR_cache |= MEAR_MDIO;
1768 else
1769 dev->MEAR_cache &= ~MEAR_MDIO;
1770
1771 /* set the output bit */
1772 writel(dev->MEAR_cache, dev->base + MEAR);
1773 readl(dev->base + MEAR);
1774
1775 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1776 udelay(1);
1777
1778 /* drive MDC high causing the data bit to be latched */
1779 dev->MEAR_cache |= MEAR_MDC;
1780 writel(dev->MEAR_cache, dev->base + MEAR);
1781 readl(dev->base + MEAR);
1782
1783 /* Wait again... */
1784 udelay(1);
1785 }
1786
1787 static int ns83820_mii_read_bit(struct ns83820 *dev)
1788 {
1789 int bit;
1790
1791 /* drive MDC low, disable output */
1792 dev->MEAR_cache &= ~MEAR_MDC;
1793 dev->MEAR_cache &= ~MEAR_MDDIR;
1794 writel(dev->MEAR_cache, dev->base + MEAR);
1795 readl(dev->base + MEAR);
1796
1797 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1798 udelay(1);
1799
1800 /* drive MDC high causing the data bit to be latched */
1801 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1802 dev->MEAR_cache |= MEAR_MDC;
1803 writel(dev->MEAR_cache, dev->base + MEAR);
1804
1805 /* Wait again... */
1806 udelay(1);
1807
1808 return bit;
1809 }
1810
1811 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1812 {
1813 unsigned data = 0;
1814 int i;
1815
1816 /* read some garbage so that we eventually sync up */
1817 for (i=0; i<64; i++)
1818 ns83820_mii_read_bit(dev);
1819
1820 ns83820_mii_write_bit(dev, 0); /* start */
1821 ns83820_mii_write_bit(dev, 1);
1822 ns83820_mii_write_bit(dev, 1); /* opcode read */
1823 ns83820_mii_write_bit(dev, 0);
1824
1825 /* write out the phy address: 5 bits, msb first */
1826 for (i=0; i<5; i++)
1827 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1828
1829 /* write out the register address, 5 bits, msb first */
1830 for (i=0; i<5; i++)
1831 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1832
1833 ns83820_mii_read_bit(dev); /* turn around cycles */
1834 ns83820_mii_read_bit(dev);
1835
1836 /* read in the register data, 16 bits msb first */
1837 for (i=0; i<16; i++) {
1838 data <<= 1;
1839 data |= ns83820_mii_read_bit(dev);
1840 }
1841
1842 return data;
1843 }
1844
1845 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1846 {
1847 int i;
1848
1849 /* read some garbage so that we eventually sync up */
1850 for (i=0; i<64; i++)
1851 ns83820_mii_read_bit(dev);
1852
1853 ns83820_mii_write_bit(dev, 0); /* start */
1854 ns83820_mii_write_bit(dev, 1);
1855 ns83820_mii_write_bit(dev, 0); /* opcode read */
1856 ns83820_mii_write_bit(dev, 1);
1857
1858 /* write out the phy address: 5 bits, msb first */
1859 for (i=0; i<5; i++)
1860 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1861
1862 /* write out the register address, 5 bits, msb first */
1863 for (i=0; i<5; i++)
1864 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1865
1866 ns83820_mii_read_bit(dev); /* turn around cycles */
1867 ns83820_mii_read_bit(dev);
1868
1869 /* read in the register data, 16 bits msb first */
1870 for (i=0; i<16; i++)
1871 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1872
1873 return data;
1874 }
1875
1876 static void ns83820_probe_phy(struct net_device *ndev)
1877 {
1878 struct ns83820 *dev = PRIV(ndev);
1879 static int first;
1880 int i;
1881 #define MII_PHYIDR1 0x02
1882 #define MII_PHYIDR2 0x03
1883
1884 #if 0
1885 if (!first) {
1886 unsigned tmp;
1887 ns83820_mii_read_reg(dev, 1, 0x09);
1888 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1889
1890 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1891 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1892 udelay(1300);
1893 ns83820_mii_read_reg(dev, 1, 0x09);
1894 }
1895 #endif
1896 first = 1;
1897
1898 for (i=1; i<2; i++) {
1899 int j;
1900 unsigned a, b;
1901 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1902 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1903
1904 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1905 // ndev->name, i, a, b);
1906
1907 for (j=0; j<0x16; j+=4) {
1908 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1909 ndev->name, j,
1910 ns83820_mii_read_reg(dev, i, 0 + j),
1911 ns83820_mii_read_reg(dev, i, 1 + j),
1912 ns83820_mii_read_reg(dev, i, 2 + j),
1913 ns83820_mii_read_reg(dev, i, 3 + j)
1914 );
1915 }
1916 }
1917 {
1918 unsigned a, b;
1919 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1920 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1921 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1922 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1923
1924 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1925 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1926 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1927 dprintk("version: 0x%04x 0x%04x\n", a, b);
1928 }
1929 }
1930 #endif
1931
1932 static const struct net_device_ops netdev_ops = {
1933 .ndo_open = ns83820_open,
1934 .ndo_stop = ns83820_stop,
1935 .ndo_start_xmit = ns83820_hard_start_xmit,
1936 .ndo_get_stats = ns83820_get_stats,
1937 .ndo_change_mtu = ns83820_change_mtu,
1938 .ndo_set_rx_mode = ns83820_set_multicast,
1939 .ndo_validate_addr = eth_validate_addr,
1940 .ndo_set_mac_address = eth_mac_addr,
1941 .ndo_tx_timeout = ns83820_tx_timeout,
1942 };
1943
1944 static int ns83820_init_one(struct pci_dev *pci_dev,
1945 const struct pci_device_id *id)
1946 {
1947 struct net_device *ndev;
1948 struct ns83820 *dev;
1949 long addr;
1950 int err;
1951 int using_dac = 0;
1952
1953 /* See if we can set the dma mask early on; failure is fatal. */
1954 if (sizeof(dma_addr_t) == 8 &&
1955 !pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
1956 using_dac = 1;
1957 } else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) {
1958 using_dac = 0;
1959 } else {
1960 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1961 return -ENODEV;
1962 }
1963
1964 ndev = alloc_etherdev(sizeof(struct ns83820));
1965 err = -ENOMEM;
1966 if (!ndev)
1967 goto out;
1968
1969 dev = PRIV(ndev);
1970 dev->ndev = ndev;
1971
1972 spin_lock_init(&dev->rx_info.lock);
1973 spin_lock_init(&dev->tx_lock);
1974 spin_lock_init(&dev->misc_lock);
1975 dev->pci_dev = pci_dev;
1976
1977 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1978
1979 INIT_WORK(&dev->tq_refill, queue_refill);
1980 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1981
1982 err = pci_enable_device(pci_dev);
1983 if (err) {
1984 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1985 goto out_free;
1986 }
1987
1988 pci_set_master(pci_dev);
1989 addr = pci_resource_start(pci_dev, 1);
1990 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1991 dev->tx_descs = pci_alloc_consistent(pci_dev,
1992 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1993 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1994 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1995 err = -ENOMEM;
1996 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1997 goto out_disable;
1998
1999 dprintk("%p: %08lx %p: %08lx\n",
2000 dev->tx_descs, (long)dev->tx_phy_descs,
2001 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
2002
2003 ns83820_disable_interrupts(dev);
2004
2005 dev->IMR_cache = 0;
2006
2007 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
2008 DRV_NAME, ndev);
2009 if (err) {
2010 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
2011 pci_dev->irq, err);
2012 goto out_disable;
2013 }
2014
2015 /*
2016 * FIXME: we are holding rtnl_lock() over obscenely long area only
2017 * because some of the setup code uses dev->name. It's Wrong(tm) -
2018 * we should be using driver-specific names for all that stuff.
2019 * For now that will do, but we really need to come back and kill
2020 * most of the dev_alloc_name() users later.
2021 */
2022 rtnl_lock();
2023 err = dev_alloc_name(ndev, ndev->name);
2024 if (err < 0) {
2025 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
2026 goto out_free_irq;
2027 }
2028
2029 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
2030 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
2031 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
2032
2033 ndev->netdev_ops = &netdev_ops;
2034 SET_ETHTOOL_OPS(ndev, &ops);
2035 ndev->watchdog_timeo = 5 * HZ;
2036 pci_set_drvdata(pci_dev, ndev);
2037
2038 ns83820_do_reset(dev, CR_RST);
2039
2040 /* Must reset the ram bist before running it */
2041 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2042 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
2043 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
2044 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
2045 PTSCR_EEBIST_FAIL);
2046 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
2047
2048 /* I love config registers */
2049 dev->CFG_cache = readl(dev->base + CFG);
2050
2051 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2052 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2053 ndev->name);
2054 /*dev->CFG_cache |= CFG_DATA64_EN;*/
2055 if (!(dev->CFG_cache & CFG_DATA64_EN))
2056 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2057 ndev->name);
2058 } else
2059 dev->CFG_cache &= ~(CFG_DATA64_EN);
2060
2061 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2062 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2063 CFG_M64ADDR);
2064 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2065 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
2066 dev->CFG_cache |= CFG_REQALG;
2067 dev->CFG_cache |= CFG_POW;
2068 dev->CFG_cache |= CFG_TMRTEST;
2069
2070 /* When compiled with 64 bit addressing, we must always enable
2071 * the 64 bit descriptor format.
2072 */
2073 if (sizeof(dma_addr_t) == 8)
2074 dev->CFG_cache |= CFG_M64ADDR;
2075 if (using_dac)
2076 dev->CFG_cache |= CFG_T64ADDR;
2077
2078 /* Big endian mode does not seem to do what the docs suggest */
2079 dev->CFG_cache &= ~CFG_BEM;
2080
2081 /* setup optical transceiver if we have one */
2082 if (dev->CFG_cache & CFG_TBI_EN) {
2083 printk(KERN_INFO "%s: enabling optical transceiver\n",
2084 ndev->name);
2085 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2086
2087 /* setup auto negotiation feature advertisement */
2088 writel(readl(dev->base + TANAR)
2089 | TANAR_HALF_DUP | TANAR_FULL_DUP,
2090 dev->base + TANAR);
2091
2092 /* start auto negotiation */
2093 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2094 dev->base + TBICR);
2095 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2096 dev->linkstate = LINK_AUTONEGOTIATE;
2097
2098 dev->CFG_cache |= CFG_MODE_1000;
2099 }
2100
2101 writel(dev->CFG_cache, dev->base + CFG);
2102 dprintk("CFG: %08x\n", dev->CFG_cache);
2103
2104 if (reset_phy) {
2105 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2106 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2107 msleep(10);
2108 writel(dev->CFG_cache, dev->base + CFG);
2109 }
2110
2111 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2112 * the PCI layer. FIXME.
2113 */
2114 if (readl(dev->base + SRR))
2115 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2116 #endif
2117
2118 /* Note! The DMA burst size interacts with packet
2119 * transmission, such that the largest packet that
2120 * can be transmitted is 8192 - FLTH - burst size.
2121 * If only the transmit fifo was larger...
2122 */
2123 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2124 * some DELL and COMPAQ SMP systems */
2125 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2126 | ((1600 / 32) * 0x100),
2127 dev->base + TXCFG);
2128
2129 /* Flush the interrupt holdoff timer */
2130 writel(0x000, dev->base + IHR);
2131 writel(0x100, dev->base + IHR);
2132 writel(0x000, dev->base + IHR);
2133
2134 /* Set Rx to full duplex, don't accept runt, errored, long or length
2135 * range errored packets. Use 512 byte DMA.
2136 */
2137 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2138 * some DELL and COMPAQ SMP systems
2139 * Turn on ALP, only we are accpeting Jumbo Packets */
2140 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2141 | RXCFG_STRIPCRC
2142 //| RXCFG_ALP
2143 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2144
2145 /* Disable priority queueing */
2146 writel(0, dev->base + PQCR);
2147
2148 /* Enable IP checksum validation and detetion of VLAN headers.
2149 * Note: do not set the reject options as at least the 0x102
2150 * revision of the chip does not properly accept IP fragments
2151 * at least for UDP.
2152 */
2153 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2154 * the MAC it calculates the packetsize AFTER stripping the VLAN
2155 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2156 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2157 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2158 * it discrards it!. These guys......
2159 * also turn on tag stripping if hardware acceleration is enabled
2160 */
2161 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2162 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2163 #else
2164 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2165 #endif
2166 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2167
2168 /* Enable per-packet TCP/UDP/IP checksumming
2169 * and per packet vlan tag insertion if
2170 * vlan hardware acceleration is enabled
2171 */
2172 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2173 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2174 #else
2175 #define VTCR_INIT_VALUE VTCR_PPCHK
2176 #endif
2177 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2178
2179 /* Ramit : Enable async and sync pause frames */
2180 /* writel(0, dev->base + PCR); */
2181 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2182 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2183 dev->base + PCR);
2184
2185 /* Disable Wake On Lan */
2186 writel(0, dev->base + WCSR);
2187
2188 ns83820_getmac(dev, ndev->dev_addr);
2189
2190 /* Yes, we support dumb IP checksum on transmit */
2191 ndev->features |= NETIF_F_SG;
2192 ndev->features |= NETIF_F_IP_CSUM;
2193
2194 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2195 /* We also support hardware vlan acceleration */
2196 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2197 #endif
2198
2199 if (using_dac) {
2200 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2201 ndev->name);
2202 ndev->features |= NETIF_F_HIGHDMA;
2203 }
2204
2205 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n",
2206 ndev->name,
2207 (unsigned)readl(dev->base + SRR) >> 8,
2208 (unsigned)readl(dev->base + SRR) & 0xff,
2209 ndev->dev_addr, addr, pci_dev->irq,
2210 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2211 );
2212
2213 #ifdef PHY_CODE_IS_FINISHED
2214 ns83820_probe_phy(ndev);
2215 #endif
2216
2217 err = register_netdevice(ndev);
2218 if (err) {
2219 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2220 goto out_cleanup;
2221 }
2222 rtnl_unlock();
2223
2224 return 0;
2225
2226 out_cleanup:
2227 ns83820_disable_interrupts(dev); /* paranoia */
2228 out_free_irq:
2229 rtnl_unlock();
2230 free_irq(pci_dev->irq, ndev);
2231 out_disable:
2232 if (dev->base)
2233 iounmap(dev->base);
2234 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2235 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2236 pci_disable_device(pci_dev);
2237 out_free:
2238 free_netdev(ndev);
2239 pci_set_drvdata(pci_dev, NULL);
2240 out:
2241 return err;
2242 }
2243
2244 static void ns83820_remove_one(struct pci_dev *pci_dev)
2245 {
2246 struct net_device *ndev = pci_get_drvdata(pci_dev);
2247 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2248
2249 if (!ndev) /* paranoia */
2250 return;
2251
2252 ns83820_disable_interrupts(dev); /* paranoia */
2253
2254 unregister_netdev(ndev);
2255 free_irq(dev->pci_dev->irq, ndev);
2256 iounmap(dev->base);
2257 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2258 dev->tx_descs, dev->tx_phy_descs);
2259 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2260 dev->rx_info.descs, dev->rx_info.phy_descs);
2261 pci_disable_device(dev->pci_dev);
2262 free_netdev(ndev);
2263 pci_set_drvdata(pci_dev, NULL);
2264 }
2265
2266 static DEFINE_PCI_DEVICE_TABLE(ns83820_pci_tbl) = {
2267 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2268 { 0, },
2269 };
2270
2271 static struct pci_driver driver = {
2272 .name = "ns83820",
2273 .id_table = ns83820_pci_tbl,
2274 .probe = ns83820_init_one,
2275 .remove = ns83820_remove_one,
2276 #if 0 /* FIXME: implement */
2277 .suspend = ,
2278 .resume = ,
2279 #endif
2280 };
2281
2282
2283 static int __init ns83820_init(void)
2284 {
2285 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2286 return pci_register_driver(&driver);
2287 }
2288
2289 static void __exit ns83820_exit(void)
2290 {
2291 pci_unregister_driver(&driver);
2292 }
2293
2294 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2295 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2296 MODULE_LICENSE("GPL");
2297
2298 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2299
2300 module_param(lnksts, int, 0);
2301 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2302
2303 module_param(ihr, int, 0);
2304 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2305
2306 module_param(reset_phy, int, 0);
2307 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2308
2309 module_init(ns83820_init);
2310 module_exit(ns83820_exit);
Linux kernel - Deliverables
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