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MAINTAINERS: Add phy-miphy28lp.c and phy-miphy365x.c to ARCH/STI architecture
[deliverable/linux.git] / drivers / net / ethernet / qlogic / netxen / netxen_nic.h
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 * The full GNU General Public License is included in this distribution
20 * in the file called "COPYING".
21 *
22 */
23
24 #ifndef _NETXEN_NIC_H_
25 #define _NETXEN_NIC_H_
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/types.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ip.h>
35 #include <linux/in.h>
36 #include <linux/tcp.h>
37 #include <linux/skbuff.h>
38 #include <linux/firmware.h>
39
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/timer.h>
43
44 #include <linux/vmalloc.h>
45
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48
49 #include "netxen_nic_hdr.h"
50 #include "netxen_nic_hw.h"
51
52 #define _NETXEN_NIC_LINUX_MAJOR 4
53 #define _NETXEN_NIC_LINUX_MINOR 0
54 #define _NETXEN_NIC_LINUX_SUBVERSION 82
55 #define NETXEN_NIC_LINUX_VERSIONID "4.0.82"
56
57 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
58 #define _major(v) (((v) >> 24) & 0xff)
59 #define _minor(v) (((v) >> 16) & 0xff)
60 #define _build(v) ((v) & 0xffff)
61
62 /* version in image has weird encoding:
63 * 7:0 - major
64 * 15:8 - minor
65 * 31:16 - build (little endian)
66 */
67 #define NETXEN_DECODE_VERSION(v) \
68 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
69
70 #define NETXEN_NUM_FLASH_SECTORS (64)
71 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
72 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
73 * NETXEN_FLASH_SECTOR_SIZE)
74
75 #define RCV_DESC_RINGSIZE(rds_ring) \
76 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
77 #define RCV_BUFF_RINGSIZE(rds_ring) \
78 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
79 #define STATUS_DESC_RINGSIZE(sds_ring) \
80 (sizeof(struct status_desc) * (sds_ring)->num_desc)
81 #define TX_BUFF_RINGSIZE(tx_ring) \
82 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
83 #define TX_DESC_RINGSIZE(tx_ring) \
84 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
85
86 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
87
88 #define NETXEN_RCV_PRODUCER_OFFSET 0
89 #define NETXEN_RCV_PEG_DB_ID 2
90 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
91 #define FLASH_SUCCESS 0
92
93 #define ADDR_IN_WINDOW1(off) \
94 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
95
96 #define ADDR_IN_RANGE(addr, low, high) \
97 (((addr) < (high)) && ((addr) >= (low)))
98
99 /*
100 * normalize a 64MB crb address to 32MB PCI window
101 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
102 */
103 #define NETXEN_CRB_NORMAL(reg) \
104 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
105
106 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
107 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
108
109 #define DB_NORMALIZE(adapter, off) \
110 (adapter->ahw.db_base + (off))
111
112 #define NX_P2_C0 0x24
113 #define NX_P2_C1 0x25
114 #define NX_P3_A0 0x30
115 #define NX_P3_A2 0x30
116 #define NX_P3_B0 0x40
117 #define NX_P3_B1 0x41
118 #define NX_P3_B2 0x42
119 #define NX_P3P_A0 0x50
120
121 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
122 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
123 #define NX_IS_REVISION_P3P(REVISION) (REVISION >= NX_P3P_A0)
124
125 #define FIRST_PAGE_GROUP_START 0
126 #define FIRST_PAGE_GROUP_END 0x100000
127
128 #define SECOND_PAGE_GROUP_START 0x6000000
129 #define SECOND_PAGE_GROUP_END 0x68BC000
130
131 #define THIRD_PAGE_GROUP_START 0x70E4000
132 #define THIRD_PAGE_GROUP_END 0x8000000
133
134 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
135 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
136 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
137
138 #define P2_MAX_MTU (8000)
139 #define P3_MAX_MTU (9600)
140 #define NX_ETHERMTU 1500
141 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
142
143 #define NX_P2_RX_BUF_MAX_LEN 1760
144 #define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
145 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
146 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
147 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
148 #define NX_LRO_BUFFER_EXTRA 2048
149
150 #define NX_RX_LRO_BUFFER_LENGTH (8060)
151
152 /*
153 * Maximum number of ring contexts
154 */
155 #define MAX_RING_CTX 1
156
157 /* Opcodes to be used with the commands */
158 #define TX_ETHER_PKT 0x01
159 #define TX_TCP_PKT 0x02
160 #define TX_UDP_PKT 0x03
161 #define TX_IP_PKT 0x04
162 #define TX_TCP_LSO 0x05
163 #define TX_TCP_LSO6 0x06
164 #define TX_IPSEC 0x07
165 #define TX_IPSEC_CMD 0x0a
166 #define TX_TCPV6_PKT 0x0b
167 #define TX_UDPV6_PKT 0x0c
168
169 /* The following opcodes are for internal consumption. */
170 #define NETXEN_CONTROL_OP 0x10
171 #define PEGNET_REQUEST 0x11
172
173 #define MAX_NUM_CARDS 4
174
175 #define NETXEN_MAX_FRAGS_PER_TX 14
176 #define MAX_TSO_HEADER_DESC 2
177 #define MGMT_CMD_DESC_RESV 4
178 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
179 + MGMT_CMD_DESC_RESV)
180 #define NX_MAX_TX_TIMEOUTS 2
181
182 /*
183 * Following are the states of the Phantom. Phantom will set them and
184 * Host will read to check if the fields are correct.
185 */
186 #define PHAN_INITIALIZE_START 0xff00
187 #define PHAN_INITIALIZE_FAILED 0xffff
188 #define PHAN_INITIALIZE_COMPLETE 0xff01
189
190 /* Host writes the following to notify that it has done the init-handshake */
191 #define PHAN_INITIALIZE_ACK 0xf00f
192
193 #define NUM_RCV_DESC_RINGS 3
194 #define NUM_STS_DESC_RINGS 4
195
196 #define RCV_RING_NORMAL 0
197 #define RCV_RING_JUMBO 1
198 #define RCV_RING_LRO 2
199
200 #define MIN_CMD_DESCRIPTORS 64
201 #define MIN_RCV_DESCRIPTORS 64
202 #define MIN_JUMBO_DESCRIPTORS 32
203
204 #define MAX_CMD_DESCRIPTORS 1024
205 #define MAX_RCV_DESCRIPTORS_1G 4096
206 #define MAX_RCV_DESCRIPTORS_10G 8192
207 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
208 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
209 #define MAX_LRO_RCV_DESCRIPTORS 8
210
211 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
212 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
213
214 #define NETXEN_CTX_SIGNATURE 0xdee0
215 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
216 #define NETXEN_CTX_RESET 0xbad0
217 #define NETXEN_CTX_D3_RESET 0xacc0
218 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
219
220 #define PHAN_PEG_RCV_INITIALIZED 0xff01
221 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
222
223 #define get_next_index(index, length) \
224 (((index) + 1) & ((length) - 1))
225
226 #define get_index_range(index,length,count) \
227 (((index) + (count)) & ((length) - 1))
228
229 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
230 #define MPORT_MULTI_FUNCTION_MODE 0x2222
231
232 #define NX_MAX_PCI_FUNC 8
233
234 /*
235 * NetXen host-peg signal message structure
236 *
237 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
238 * Bit 2 : priv_id => must be 1
239 * Bit 3-17 : count => for doorbell
240 * Bit 18-27 : ctx_id => Context id
241 * Bit 28-31 : opcode
242 */
243
244 typedef u32 netxen_ctx_msg;
245
246 #define netxen_set_msg_peg_id(config_word, val) \
247 ((config_word) &= ~3, (config_word) |= val & 3)
248 #define netxen_set_msg_privid(config_word) \
249 ((config_word) |= 1 << 2)
250 #define netxen_set_msg_count(config_word, val) \
251 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
252 #define netxen_set_msg_ctxid(config_word, val) \
253 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
254 #define netxen_set_msg_opcode(config_word, val) \
255 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
256
257 struct netxen_rcv_ring {
258 __le64 addr;
259 __le32 size;
260 __le32 rsrvd;
261 };
262
263 struct netxen_sts_ring {
264 __le64 addr;
265 __le32 size;
266 __le16 msi_index;
267 __le16 rsvd;
268 } ;
269
270 struct netxen_ring_ctx {
271
272 /* one command ring */
273 __le64 cmd_consumer_offset;
274 __le64 cmd_ring_addr;
275 __le32 cmd_ring_size;
276 __le32 rsrvd;
277
278 /* three receive rings */
279 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
280
281 __le64 sts_ring_addr;
282 __le32 sts_ring_size;
283
284 __le32 ctx_id;
285
286 __le64 rsrvd_2[3];
287 __le32 sts_ring_count;
288 __le32 rsrvd_3;
289 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
290
291 } __attribute__ ((aligned(64)));
292
293 /*
294 * Following data structures describe the descriptors that will be used.
295 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
296 * we are doing LSO (above the 1500 size packet) only.
297 */
298
299 /*
300 * The size of reference handle been changed to 16 bits to pass the MSS fields
301 * for the LSO packet
302 */
303
304 #define FLAGS_CHECKSUM_ENABLED 0x01
305 #define FLAGS_LSO_ENABLED 0x02
306 #define FLAGS_IPSEC_SA_ADD 0x04
307 #define FLAGS_IPSEC_SA_DELETE 0x08
308 #define FLAGS_VLAN_TAGGED 0x10
309 #define FLAGS_VLAN_OOB 0x40
310
311 #define netxen_set_tx_vlan_tci(cmd_desc, v) \
312 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
313
314 #define netxen_set_cmd_desc_port(cmd_desc, var) \
315 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
316 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
317 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
318
319 #define netxen_set_tx_port(_desc, _port) \
320 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
321
322 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
323 (_desc)->flags_opcode = \
324 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
325
326 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
327 (_desc)->nfrags__length = \
328 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
329
330 struct cmd_desc_type0 {
331 u8 tcp_hdr_offset; /* For LSO only */
332 u8 ip_hdr_offset; /* For LSO only */
333 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
334 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
335
336 __le64 addr_buffer2;
337
338 __le16 reference_handle;
339 __le16 mss;
340 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
341 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
342 __le16 conn_id; /* IPSec offoad only */
343
344 __le64 addr_buffer3;
345 __le64 addr_buffer1;
346
347 __le16 buffer_length[4];
348
349 __le64 addr_buffer4;
350
351 __le32 reserved2;
352 __le16 reserved;
353 __le16 vlan_TCI;
354
355 } __attribute__ ((aligned(64)));
356
357 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
358 struct rcv_desc {
359 __le16 reference_handle;
360 __le16 reserved;
361 __le32 buffer_length; /* allocated buffer length (usually 2K) */
362 __le64 addr_buffer;
363 };
364
365 /* opcode field in status_desc */
366 #define NETXEN_NIC_SYN_OFFLOAD 0x03
367 #define NETXEN_NIC_RXPKT_DESC 0x04
368 #define NETXEN_OLD_RXPKT_DESC 0x3f
369 #define NETXEN_NIC_RESPONSE_DESC 0x05
370 #define NETXEN_NIC_LRO_DESC 0x12
371
372 /* for status field in status_desc */
373 #define STATUS_NEED_CKSUM (1)
374 #define STATUS_CKSUM_OK (2)
375
376 /* owner bits of status_desc */
377 #define STATUS_OWNER_HOST (0x1ULL << 56)
378 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
379
380 /* Status descriptor:
381 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
382 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
383 53-55 desc_cnt, 56-57 owner, 58-63 opcode
384 */
385 #define netxen_get_sts_port(sts_data) \
386 ((sts_data) & 0x0F)
387 #define netxen_get_sts_status(sts_data) \
388 (((sts_data) >> 4) & 0x0F)
389 #define netxen_get_sts_type(sts_data) \
390 (((sts_data) >> 8) & 0x0F)
391 #define netxen_get_sts_totallength(sts_data) \
392 (((sts_data) >> 12) & 0xFFFF)
393 #define netxen_get_sts_refhandle(sts_data) \
394 (((sts_data) >> 28) & 0xFFFF)
395 #define netxen_get_sts_prot(sts_data) \
396 (((sts_data) >> 44) & 0x0F)
397 #define netxen_get_sts_pkt_offset(sts_data) \
398 (((sts_data) >> 48) & 0x1F)
399 #define netxen_get_sts_desc_cnt(sts_data) \
400 (((sts_data) >> 53) & 0x7)
401 #define netxen_get_sts_opcode(sts_data) \
402 (((sts_data) >> 58) & 0x03F)
403
404 #define netxen_get_lro_sts_refhandle(sts_data) \
405 ((sts_data) & 0x0FFFF)
406 #define netxen_get_lro_sts_length(sts_data) \
407 (((sts_data) >> 16) & 0x0FFFF)
408 #define netxen_get_lro_sts_l2_hdr_offset(sts_data) \
409 (((sts_data) >> 32) & 0x0FF)
410 #define netxen_get_lro_sts_l4_hdr_offset(sts_data) \
411 (((sts_data) >> 40) & 0x0FF)
412 #define netxen_get_lro_sts_timestamp(sts_data) \
413 (((sts_data) >> 48) & 0x1)
414 #define netxen_get_lro_sts_type(sts_data) \
415 (((sts_data) >> 49) & 0x7)
416 #define netxen_get_lro_sts_push_flag(sts_data) \
417 (((sts_data) >> 52) & 0x1)
418 #define netxen_get_lro_sts_seq_number(sts_data) \
419 ((sts_data) & 0x0FFFFFFFF)
420 #define netxen_get_lro_sts_mss(sts_data1) \
421 ((sts_data1 >> 32) & 0x0FFFF)
422
423
424 struct status_desc {
425 __le64 status_desc_data[2];
426 } __attribute__ ((aligned(16)));
427
428 /* UNIFIED ROMIMAGE *************************/
429 #define NX_UNI_DIR_SECT_PRODUCT_TBL 0x0
430 #define NX_UNI_DIR_SECT_BOOTLD 0x6
431 #define NX_UNI_DIR_SECT_FW 0x7
432
433 /*Offsets */
434 #define NX_UNI_CHIP_REV_OFF 10
435 #define NX_UNI_FLAGS_OFF 11
436 #define NX_UNI_BIOS_VERSION_OFF 12
437 #define NX_UNI_BOOTLD_IDX_OFF 27
438 #define NX_UNI_FIRMWARE_IDX_OFF 29
439
440 struct uni_table_desc{
441 uint32_t findex;
442 uint32_t num_entries;
443 uint32_t entry_size;
444 uint32_t reserved[5];
445 };
446
447 struct uni_data_desc{
448 uint32_t findex;
449 uint32_t size;
450 uint32_t reserved[5];
451 };
452
453 /* UNIFIED ROMIMAGE *************************/
454
455 /* The version of the main data structure */
456 #define NETXEN_BDINFO_VERSION 1
457
458 /* Magic number to let user know flash is programmed */
459 #define NETXEN_BDINFO_MAGIC 0x12345678
460
461 /* Max number of Gig ports on a Phantom board */
462 #define NETXEN_MAX_PORTS 4
463
464 #define NETXEN_BRDTYPE_P1_BD 0x0000
465 #define NETXEN_BRDTYPE_P1_SB 0x0001
466 #define NETXEN_BRDTYPE_P1_SMAX 0x0002
467 #define NETXEN_BRDTYPE_P1_SOCK 0x0003
468
469 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
470 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
471 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
472 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
473 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
474
475 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
476 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
477 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
478
479 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
480 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
481 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
482 #define NETXEN_BRDTYPE_P3_4_GB 0x0024
483 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
484 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
485 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
486 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
487 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
488 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
489 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
490 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
491 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
492 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
493
494 /* Flash memory map */
495 #define NETXEN_CRBINIT_START 0 /* crbinit section */
496 #define NETXEN_BRDCFG_START 0x4000 /* board config */
497 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
498 #define NETXEN_BOOTLD_START 0x10000 /* bootld */
499 #define NETXEN_IMAGE_START 0x43000 /* compressed image */
500 #define NETXEN_SECONDARY_START 0x200000 /* backup images */
501 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
502 #define NETXEN_USER_START 0x3E8000 /* Firmare info */
503 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
504 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */
505
506 #define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START)
507 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
508 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
509 #define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418)
510 #define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c)
511 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
512
513 #define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START)
514 #define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8)
515 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
516
517 #define NX_FW_MIN_SIZE (0x3fffff)
518 #define NX_P2_MN_ROMIMAGE 0
519 #define NX_P3_CT_ROMIMAGE 1
520 #define NX_P3_MN_ROMIMAGE 2
521 #define NX_UNIFIED_ROMIMAGE 3
522 #define NX_FLASH_ROMIMAGE 4
523 #define NX_UNKNOWN_ROMIMAGE 0xff
524
525 #define NX_P2_MN_ROMIMAGE_NAME "nxromimg.bin"
526 #define NX_P3_CT_ROMIMAGE_NAME "nx3fwct.bin"
527 #define NX_P3_MN_ROMIMAGE_NAME "nx3fwmn.bin"
528 #define NX_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
529 #define NX_FLASH_ROMIMAGE_NAME "flash"
530
531 extern char netxen_nic_driver_name[];
532
533 /* Number of status descriptors to handle per interrupt */
534 #define MAX_STATUS_HANDLE (64)
535
536 /*
537 * netxen_skb_frag{} is to contain mapping info for each SG list. This
538 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
539 */
540 struct netxen_skb_frag {
541 u64 dma;
542 u64 length;
543 };
544
545 struct netxen_recv_crb {
546 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
547 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
548 u32 sw_int_mask[NUM_STS_DESC_RINGS];
549 };
550
551 /* Following defines are for the state of the buffers */
552 #define NETXEN_BUFFER_FREE 0
553 #define NETXEN_BUFFER_BUSY 1
554
555 /*
556 * There will be one netxen_buffer per skb packet. These will be
557 * used to save the dma info for pci_unmap_page()
558 */
559 struct netxen_cmd_buffer {
560 struct sk_buff *skb;
561 struct netxen_skb_frag frag_array[MAX_SKB_FRAGS + 1];
562 u32 frag_count;
563 };
564
565 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
566 struct netxen_rx_buffer {
567 struct list_head list;
568 struct sk_buff *skb;
569 u64 dma;
570 u16 ref_handle;
571 u16 state;
572 };
573
574 /* Board types */
575 #define NETXEN_NIC_GBE 0x01
576 #define NETXEN_NIC_XGBE 0x02
577
578 /*
579 * One hardware_context{} per adapter
580 * contains interrupt info as well shared hardware info.
581 */
582 struct netxen_hardware_context {
583 void __iomem *pci_base0;
584 void __iomem *pci_base1;
585 void __iomem *pci_base2;
586 void __iomem *db_base;
587 void __iomem *ocm_win_crb;
588
589 unsigned long db_len;
590 unsigned long pci_len0;
591
592 u32 ocm_win;
593 u32 crb_win;
594
595 rwlock_t crb_lock;
596 spinlock_t mem_lock;
597
598 u8 cut_through;
599 u8 revision_id;
600 u8 pci_func;
601 u8 linkup;
602 u16 port_type;
603 u16 board_type;
604 };
605
606 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
607 #define ETHERNET_FCS_SIZE 4
608
609 struct netxen_adapter_stats {
610 u64 xmitcalled;
611 u64 xmitfinished;
612 u64 rxdropped;
613 u64 txdropped;
614 u64 csummed;
615 u64 rx_pkts;
616 u64 lro_pkts;
617 u64 rxbytes;
618 u64 txbytes;
619 };
620
621 /*
622 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
623 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
624 */
625 struct nx_host_rds_ring {
626 u32 producer;
627 u32 num_desc;
628 u32 dma_size;
629 u32 skb_size;
630 u32 flags;
631 void __iomem *crb_rcv_producer;
632 struct rcv_desc *desc_head;
633 struct netxen_rx_buffer *rx_buf_arr;
634 struct list_head free_list;
635 spinlock_t lock;
636 dma_addr_t phys_addr;
637 };
638
639 struct nx_host_sds_ring {
640 u32 consumer;
641 u32 num_desc;
642 void __iomem *crb_sts_consumer;
643 void __iomem *crb_intr_mask;
644
645 struct status_desc *desc_head;
646 struct netxen_adapter *adapter;
647 struct napi_struct napi;
648 struct list_head free_list[NUM_RCV_DESC_RINGS];
649
650 int irq;
651
652 dma_addr_t phys_addr;
653 char name[IFNAMSIZ+4];
654 };
655
656 struct nx_host_tx_ring {
657 u32 producer;
658 __le32 *hw_consumer;
659 u32 sw_consumer;
660 void __iomem *crb_cmd_producer;
661 void __iomem *crb_cmd_consumer;
662 u32 num_desc;
663
664 struct netdev_queue *txq;
665
666 struct netxen_cmd_buffer *cmd_buf_arr;
667 struct cmd_desc_type0 *desc_head;
668 dma_addr_t phys_addr;
669 };
670
671 /*
672 * Receive context. There is one such structure per instance of the
673 * receive processing. Any state information that is relevant to
674 * the receive, and is must be in this structure. The global data may be
675 * present elsewhere.
676 */
677 struct netxen_recv_context {
678 u32 state;
679 u16 context_id;
680 u16 virt_port;
681
682 struct nx_host_rds_ring *rds_rings;
683 struct nx_host_sds_ring *sds_rings;
684
685 struct netxen_ring_ctx *hwctx;
686 dma_addr_t phys_addr;
687 };
688
689 struct _cdrp_cmd {
690 u32 cmd;
691 u32 arg1;
692 u32 arg2;
693 u32 arg3;
694 };
695
696 struct netxen_cmd_args {
697 struct _cdrp_cmd req;
698 struct _cdrp_cmd rsp;
699 };
700
701 /* New HW context creation */
702
703 #define NX_OS_CRB_RETRY_COUNT 4000
704 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
705 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
706
707 #define NX_CDRP_CLEAR 0x00000000
708 #define NX_CDRP_CMD_BIT 0x80000000
709
710 /*
711 * All responses must have the NX_CDRP_CMD_BIT cleared
712 * in the crb NX_CDRP_CRB_OFFSET.
713 */
714 #define NX_CDRP_FORM_RSP(rsp) (rsp)
715 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
716
717 #define NX_CDRP_RSP_OK 0x00000001
718 #define NX_CDRP_RSP_FAIL 0x00000002
719 #define NX_CDRP_RSP_TIMEOUT 0x00000003
720
721 /*
722 * All commands must have the NX_CDRP_CMD_BIT set in
723 * the crb NX_CDRP_CRB_OFFSET.
724 */
725 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
726 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
727
728 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
729 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
730 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
731 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
732 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
733 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
734 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
735 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
736 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
737 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
738 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
739 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
740 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
741 #define NX_CDRP_CMD_SET_MTU 0x00000012
742 #define NX_CDRP_CMD_READ_PHY 0x00000013
743 #define NX_CDRP_CMD_WRITE_PHY 0x00000014
744 #define NX_CDRP_CMD_READ_HW_REG 0x00000015
745 #define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016
746 #define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017
747 #define NX_CDRP_CMD_READ_MAX_MTU 0x00000018
748 #define NX_CDRP_CMD_READ_MAX_LRO 0x00000019
749 #define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a
750 #define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b
751 #define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
752 #define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
753 #define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
754 #define NX_CDRP_CMD_CONFIG_GBE_PORT 0x0000001f
755 #define NX_CDRP_CMD_MAX 0x00000020
756
757 #define NX_RCODE_SUCCESS 0
758 #define NX_RCODE_NO_HOST_MEM 1
759 #define NX_RCODE_NO_HOST_RESOURCE 2
760 #define NX_RCODE_NO_CARD_CRB 3
761 #define NX_RCODE_NO_CARD_MEM 4
762 #define NX_RCODE_NO_CARD_RESOURCE 5
763 #define NX_RCODE_INVALID_ARGS 6
764 #define NX_RCODE_INVALID_ACTION 7
765 #define NX_RCODE_INVALID_STATE 8
766 #define NX_RCODE_NOT_SUPPORTED 9
767 #define NX_RCODE_NOT_PERMITTED 10
768 #define NX_RCODE_NOT_READY 11
769 #define NX_RCODE_DOES_NOT_EXIST 12
770 #define NX_RCODE_ALREADY_EXISTS 13
771 #define NX_RCODE_BAD_SIGNATURE 14
772 #define NX_RCODE_CMD_NOT_IMPL 15
773 #define NX_RCODE_CMD_INVALID 16
774 #define NX_RCODE_TIMEOUT 17
775 #define NX_RCODE_CMD_FAILED 18
776 #define NX_RCODE_MAX_EXCEEDED 19
777 #define NX_RCODE_MAX 20
778
779 #define NX_DESTROY_CTX_RESET 0
780 #define NX_DESTROY_CTX_D3_RESET 1
781 #define NX_DESTROY_CTX_MAX 2
782
783 /*
784 * Capabilities
785 */
786 #define NX_CAP_BIT(class, bit) (1 << bit)
787 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
788 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
789 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
790 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
791 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
792 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
793 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
794 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
795 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
796 #define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10)
797 #define NX_CAP0_HW_LRO_MSS NX_CAP_BIT(0, 21)
798
799 /*
800 * Context state
801 */
802 #define NX_HOST_CTX_STATE_FREED 0
803 #define NX_HOST_CTX_STATE_ALLOCATED 1
804 #define NX_HOST_CTX_STATE_ACTIVE 2
805 #define NX_HOST_CTX_STATE_DISABLED 3
806 #define NX_HOST_CTX_STATE_QUIESCED 4
807 #define NX_HOST_CTX_STATE_MAX 5
808
809 /*
810 * Rx context
811 */
812
813 typedef struct {
814 __le64 host_phys_addr; /* Ring base addr */
815 __le32 ring_size; /* Ring entries */
816 __le16 msi_index;
817 __le16 rsvd; /* Padding */
818 } nx_hostrq_sds_ring_t;
819
820 typedef struct {
821 __le64 host_phys_addr; /* Ring base addr */
822 __le64 buff_size; /* Packet buffer size */
823 __le32 ring_size; /* Ring entries */
824 __le32 ring_kind; /* Class of ring */
825 } nx_hostrq_rds_ring_t;
826
827 typedef struct {
828 __le64 host_rsp_dma_addr; /* Response dma'd here */
829 __le32 capabilities[4]; /* Flag bit vector */
830 __le32 host_int_crb_mode; /* Interrupt crb usage */
831 __le32 host_rds_crb_mode; /* RDS crb usage */
832 /* These ring offsets are relative to data[0] below */
833 __le32 rds_ring_offset; /* Offset to RDS config */
834 __le32 sds_ring_offset; /* Offset to SDS config */
835 __le16 num_rds_rings; /* Count of RDS rings */
836 __le16 num_sds_rings; /* Count of SDS rings */
837 __le16 rsvd1; /* Padding */
838 __le16 rsvd2; /* Padding */
839 u8 reserved[128]; /* reserve space for future expansion*/
840 /* MUST BE 64-bit aligned.
841 The following is packed:
842 - N hostrq_rds_rings
843 - N hostrq_sds_rings */
844 char data[0];
845 } nx_hostrq_rx_ctx_t;
846
847 typedef struct {
848 __le32 host_producer_crb; /* Crb to use */
849 __le32 rsvd1; /* Padding */
850 } nx_cardrsp_rds_ring_t;
851
852 typedef struct {
853 __le32 host_consumer_crb; /* Crb to use */
854 __le32 interrupt_crb; /* Crb to use */
855 } nx_cardrsp_sds_ring_t;
856
857 typedef struct {
858 /* These ring offsets are relative to data[0] below */
859 __le32 rds_ring_offset; /* Offset to RDS config */
860 __le32 sds_ring_offset; /* Offset to SDS config */
861 __le32 host_ctx_state; /* Starting State */
862 __le32 num_fn_per_port; /* How many PCI fn share the port */
863 __le16 num_rds_rings; /* Count of RDS rings */
864 __le16 num_sds_rings; /* Count of SDS rings */
865 __le16 context_id; /* Handle for context */
866 u8 phys_port; /* Physical id of port */
867 u8 virt_port; /* Virtual/Logical id of port */
868 u8 reserved[128]; /* save space for future expansion */
869 /* MUST BE 64-bit aligned.
870 The following is packed:
871 - N cardrsp_rds_rings
872 - N cardrs_sds_rings */
873 char data[0];
874 } nx_cardrsp_rx_ctx_t;
875
876 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
877 (sizeof(HOSTRQ_RX) + \
878 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
879 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
880
881 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
882 (sizeof(CARDRSP_RX) + \
883 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
884 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
885
886 /*
887 * Tx context
888 */
889
890 typedef struct {
891 __le64 host_phys_addr; /* Ring base addr */
892 __le32 ring_size; /* Ring entries */
893 __le32 rsvd; /* Padding */
894 } nx_hostrq_cds_ring_t;
895
896 typedef struct {
897 __le64 host_rsp_dma_addr; /* Response dma'd here */
898 __le64 cmd_cons_dma_addr; /* */
899 __le64 dummy_dma_addr; /* */
900 __le32 capabilities[4]; /* Flag bit vector */
901 __le32 host_int_crb_mode; /* Interrupt crb usage */
902 __le32 rsvd1; /* Padding */
903 __le16 rsvd2; /* Padding */
904 __le16 interrupt_ctl;
905 __le16 msi_index;
906 __le16 rsvd3; /* Padding */
907 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
908 u8 reserved[128]; /* future expansion */
909 } nx_hostrq_tx_ctx_t;
910
911 typedef struct {
912 __le32 host_producer_crb; /* Crb to use */
913 __le32 interrupt_crb; /* Crb to use */
914 } nx_cardrsp_cds_ring_t;
915
916 typedef struct {
917 __le32 host_ctx_state; /* Starting state */
918 __le16 context_id; /* Handle for context */
919 u8 phys_port; /* Physical id of port */
920 u8 virt_port; /* Virtual/Logical id of port */
921 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
922 u8 reserved[128]; /* future expansion */
923 } nx_cardrsp_tx_ctx_t;
924
925 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
926 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
927
928 /* CRB */
929
930 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
931 #define NX_HOST_RDS_CRB_MODE_SHARED 1
932 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
933 #define NX_HOST_RDS_CRB_MODE_MAX 3
934
935 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
936 #define NX_HOST_INT_CRB_MODE_SHARED 1
937 #define NX_HOST_INT_CRB_MODE_NORX 2
938 #define NX_HOST_INT_CRB_MODE_NOTX 3
939 #define NX_HOST_INT_CRB_MODE_NORXTX 4
940
941
942 /* MAC */
943
944 #define MC_COUNT_P2 16
945 #define MC_COUNT_P3 38
946
947 #define NETXEN_MAC_NOOP 0
948 #define NETXEN_MAC_ADD 1
949 #define NETXEN_MAC_DEL 2
950
951 typedef struct nx_mac_list_s {
952 struct list_head list;
953 uint8_t mac_addr[ETH_ALEN+2];
954 } nx_mac_list_t;
955
956 struct nx_ip_list {
957 struct list_head list;
958 __be32 ip_addr;
959 bool master;
960 };
961
962 /*
963 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
964 * adjusted based on configured MTU.
965 */
966 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
967 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
968 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
969 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
970
971 #define NETXEN_NIC_INTR_DEFAULT 0x04
972
973 typedef union {
974 struct {
975 uint16_t rx_packets;
976 uint16_t rx_time_us;
977 uint16_t tx_packets;
978 uint16_t tx_time_us;
979 } data;
980 uint64_t word;
981 } nx_nic_intr_coalesce_data_t;
982
983 typedef struct {
984 uint16_t stats_time_us;
985 uint16_t rate_sample_time;
986 uint16_t flags;
987 uint16_t rsvd_1;
988 uint32_t low_threshold;
989 uint32_t high_threshold;
990 nx_nic_intr_coalesce_data_t normal;
991 nx_nic_intr_coalesce_data_t low;
992 nx_nic_intr_coalesce_data_t high;
993 nx_nic_intr_coalesce_data_t irq;
994 } nx_nic_intr_coalesce_t;
995
996 #define NX_HOST_REQUEST 0x13
997 #define NX_NIC_REQUEST 0x14
998
999 #define NX_MAC_EVENT 0x1
1000
1001 #define NX_IP_UP 2
1002 #define NX_IP_DOWN 3
1003
1004 /*
1005 * Driver --> Firmware
1006 */
1007 #define NX_NIC_H2C_OPCODE_START 0
1008 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
1009 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
1010 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
1011 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
1012 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
1013 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
1014 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
1015 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
1016 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
1017 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
1018 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
1019 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
1020 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
1021 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
1022 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1023 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1024 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1025 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1026 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1027 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1028 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1029 #define NX_NIC_C2C_OPCODE 22
1030 #define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23
1031 #define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24
1032 #define NX_NIC_H2C_OPCODE_LAST 25
1033
1034 /*
1035 * Firmware --> Driver
1036 */
1037
1038 #define NX_NIC_C2H_OPCODE_START 128
1039 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1040 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1041 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1042 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1043 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1044 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1045 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1046 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1047 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1048 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1049 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1050 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1051 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1052 #define NX_NIC_C2H_OPCODE_LAST 142
1053
1054 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1055 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1056 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1057
1058 #define NX_NIC_LRO_REQUEST_FIRST 0
1059 #define NX_NIC_LRO_REQUEST_ADD_FLOW 1
1060 #define NX_NIC_LRO_REQUEST_DELETE_FLOW 2
1061 #define NX_NIC_LRO_REQUEST_TIMER 3
1062 #define NX_NIC_LRO_REQUEST_CLEANUP 4
1063 #define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5
1064 #define NX_TOE_LRO_REQUEST_ADD_FLOW 6
1065 #define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7
1066 #define NX_TOE_LRO_REQUEST_DELETE_FLOW 8
1067 #define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9
1068 #define NX_TOE_LRO_REQUEST_TIMER 10
1069 #define NX_NIC_LRO_REQUEST_LAST 11
1070
1071 #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1072 #define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1073 #define NX_FW_CAPABILITY_PEXQ (1 << 7)
1074 #define NX_FW_CAPABILITY_BDG (1 << 8)
1075 #define NX_FW_CAPABILITY_FVLANTX (1 << 9)
1076 #define NX_FW_CAPABILITY_HW_LRO (1 << 10)
1077 #define NX_FW_CAPABILITY_GBE_LINK_CFG (1 << 11)
1078 #define NX_FW_CAPABILITY_MORE_CAPS (1 << 31)
1079 #define NX_FW_CAPABILITY_2_LRO_MAX_TCP_SEG (1 << 2)
1080
1081 /* module types */
1082 #define LINKEVENT_MODULE_NOT_PRESENT 1
1083 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1084 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
1085 #define LINKEVENT_MODULE_OPTICAL_LRM 4
1086 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1087 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1088 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1089 #define LINKEVENT_MODULE_TWINAX 8
1090
1091 #define LINKSPEED_10GBPS 10000
1092 #define LINKSPEED_1GBPS 1000
1093 #define LINKSPEED_100MBPS 100
1094 #define LINKSPEED_10MBPS 10
1095
1096 #define LINKSPEED_ENCODED_10MBPS 0
1097 #define LINKSPEED_ENCODED_100MBPS 1
1098 #define LINKSPEED_ENCODED_1GBPS 2
1099
1100 #define LINKEVENT_AUTONEG_DISABLED 0
1101 #define LINKEVENT_AUTONEG_ENABLED 1
1102
1103 #define LINKEVENT_HALF_DUPLEX 0
1104 #define LINKEVENT_FULL_DUPLEX 1
1105
1106 #define LINKEVENT_LINKSPEED_MBPS 0
1107 #define LINKEVENT_LINKSPEED_ENCODED 1
1108
1109 #define AUTO_FW_RESET_ENABLED 0xEF10AF12
1110 #define AUTO_FW_RESET_DISABLED 0xDCBAAF12
1111
1112 /* firmware response header:
1113 * 63:58 - message type
1114 * 57:56 - owner
1115 * 55:53 - desc count
1116 * 52:48 - reserved
1117 * 47:40 - completion id
1118 * 39:32 - opcode
1119 * 31:16 - error code
1120 * 15:00 - reserved
1121 */
1122 #define netxen_get_nic_msgtype(msg_hdr) \
1123 ((msg_hdr >> 58) & 0x3F)
1124 #define netxen_get_nic_msg_compid(msg_hdr) \
1125 ((msg_hdr >> 40) & 0xFF)
1126 #define netxen_get_nic_msg_opcode(msg_hdr) \
1127 ((msg_hdr >> 32) & 0xFF)
1128 #define netxen_get_nic_msg_errcode(msg_hdr) \
1129 ((msg_hdr >> 16) & 0xFFFF)
1130
1131 typedef struct {
1132 union {
1133 struct {
1134 u64 hdr;
1135 u64 body[7];
1136 };
1137 u64 words[8];
1138 };
1139 } nx_fw_msg_t;
1140
1141 typedef struct {
1142 __le64 qhdr;
1143 __le64 req_hdr;
1144 __le64 words[6];
1145 } nx_nic_req_t;
1146
1147 typedef struct {
1148 u8 op;
1149 u8 tag;
1150 u8 mac_addr[6];
1151 } nx_mac_req_t;
1152
1153 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1154
1155 #define NETXEN_NIC_MSI_ENABLED 0x02
1156 #define NETXEN_NIC_MSIX_ENABLED 0x04
1157 #define NETXEN_NIC_LRO_ENABLED 0x08
1158 #define NETXEN_NIC_LRO_DISABLED 0x00
1159 #define NETXEN_NIC_BRIDGE_ENABLED 0X10
1160 #define NETXEN_NIC_DIAG_ENABLED 0x20
1161 #define NETXEN_FW_RESET_OWNER 0x40
1162 #define NETXEN_FW_MSS_CAP 0x80
1163 #define NETXEN_IS_MSI_FAMILY(adapter) \
1164 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1165
1166 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1167 #define NETXEN_MSIX_TBL_SPACE 8192
1168 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1169
1170 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1171
1172 #define NETXEN_ADAPTER_UP_MAGIC 777
1173 #define NETXEN_NIC_PEG_TUNE 0
1174
1175 #define __NX_FW_ATTACHED 0
1176 #define __NX_DEV_UP 1
1177 #define __NX_RESETTING 2
1178
1179 /* Mini Coredump FW supported version */
1180 #define NX_MD_SUPPORT_MAJOR 4
1181 #define NX_MD_SUPPORT_MINOR 0
1182 #define NX_MD_SUPPORT_SUBVERSION 579
1183
1184 #define LSW(x) ((uint16_t)(x))
1185 #define LSD(x) ((uint32_t)((uint64_t)(x)))
1186 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
1187
1188 /* Mini Coredump mask level */
1189 #define NX_DUMP_MASK_MIN 0x03
1190 #define NX_DUMP_MASK_DEF 0x1f
1191 #define NX_DUMP_MASK_MAX 0xff
1192
1193 /* Mini Coredump CDRP commands */
1194 #define NX_CDRP_CMD_TEMP_SIZE 0x0000002f
1195 #define NX_CDRP_CMD_GET_TEMP_HDR 0x00000030
1196
1197
1198 #define NX_DUMP_STATE_ARRAY_LEN 16
1199 #define NX_DUMP_CAP_SIZE_ARRAY_LEN 8
1200
1201 /* Mini Coredump sysfs entries flags*/
1202 #define NX_FORCE_FW_DUMP_KEY 0xdeadfeed
1203 #define NX_ENABLE_FW_DUMP 0xaddfeed
1204 #define NX_DISABLE_FW_DUMP 0xbadfeed
1205 #define NX_FORCE_FW_RESET 0xdeaddead
1206
1207
1208 /* Fw dump levels */
1209 static const u32 FW_DUMP_LEVELS[] = { 0x3, 0x7, 0xf, 0x1f, 0x3f, 0x7f, 0xff };
1210
1211 /* Flash read/write address */
1212 #define NX_FW_DUMP_REG1 0x00130060
1213 #define NX_FW_DUMP_REG2 0x001e0000
1214 #define NX_FLASH_SEM2_LK 0x0013C010
1215 #define NX_FLASH_SEM2_ULK 0x0013C014
1216 #define NX_FLASH_LOCK_ID 0x001B2100
1217 #define FLASH_ROM_WINDOW 0x42110030
1218 #define FLASH_ROM_DATA 0x42150000
1219
1220 /* Mini Coredump register read/write routine */
1221 #define NX_RD_DUMP_REG(addr, bar0, data) do { \
1222 writel((addr & 0xFFFF0000), (void __iomem *) (bar0 + \
1223 NX_FW_DUMP_REG1)); \
1224 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG1)); \
1225 *data = readl((void __iomem *) (bar0 + NX_FW_DUMP_REG2 + \
1226 LSW(addr))); \
1227 } while (0)
1228
1229 #define NX_WR_DUMP_REG(addr, bar0, data) do { \
1230 writel((addr & 0xFFFF0000), (void __iomem *) (bar0 + \
1231 NX_FW_DUMP_REG1)); \
1232 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG1)); \
1233 writel(data, (void __iomem *) (bar0 + NX_FW_DUMP_REG2 + LSW(addr)));\
1234 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG2 + LSW(addr))); \
1235 } while (0)
1236
1237
1238 /*
1239 Entry Type Defines
1240 */
1241
1242 #define RDNOP 0
1243 #define RDCRB 1
1244 #define RDMUX 2
1245 #define QUEUE 3
1246 #define BOARD 4
1247 #define RDSRE 5
1248 #define RDOCM 6
1249 #define PREGS 7
1250 #define L1DTG 8
1251 #define L1ITG 9
1252 #define CACHE 10
1253
1254 #define L1DAT 11
1255 #define L1INS 12
1256 #define RDSTK 13
1257 #define RDCON 14
1258
1259 #define L2DTG 21
1260 #define L2ITG 22
1261 #define L2DAT 23
1262 #define L2INS 24
1263 #define RDOC3 25
1264
1265 #define MEMBK 32
1266
1267 #define RDROM 71
1268 #define RDMEM 72
1269 #define RDMN 73
1270
1271 #define INFOR 81
1272 #define CNTRL 98
1273
1274 #define TLHDR 99
1275 #define RDEND 255
1276
1277 #define PRIMQ 103
1278 #define SQG2Q 104
1279 #define SQG3Q 105
1280
1281 /*
1282 * Opcodes for Control Entries.
1283 * These Flags are bit fields.
1284 */
1285 #define NX_DUMP_WCRB 0x01
1286 #define NX_DUMP_RWCRB 0x02
1287 #define NX_DUMP_ANDCRB 0x04
1288 #define NX_DUMP_ORCRB 0x08
1289 #define NX_DUMP_POLLCRB 0x10
1290 #define NX_DUMP_RD_SAVE 0x20
1291 #define NX_DUMP_WRT_SAVED 0x40
1292 #define NX_DUMP_MOD_SAVE_ST 0x80
1293
1294 /* Driver Flags */
1295 #define NX_DUMP_SKIP 0x80 /* driver skipped this entry */
1296 #define NX_DUMP_SIZE_ERR 0x40 /*entry size vs capture size mismatch*/
1297
1298 #define NX_PCI_READ_32(ADDR) readl((ADDR))
1299 #define NX_PCI_WRITE_32(DATA, ADDR) writel(DATA, (ADDR))
1300
1301
1302
1303 struct netxen_minidump {
1304 u32 pos; /* position in the dump buffer */
1305 u8 fw_supports_md; /* FW supports Mini cordump */
1306 u8 has_valid_dump; /* indicates valid dump */
1307 u8 md_capture_mask; /* driver capture mask */
1308 u8 md_enabled; /* Turn Mini Coredump on/off */
1309 u32 md_dump_size; /* Total FW Mini Coredump size */
1310 u32 md_capture_size; /* FW dump capture size */
1311 u32 md_template_size; /* FW template size */
1312 u32 md_template_ver; /* FW template version */
1313 u64 md_timestamp; /* FW Mini dump timestamp */
1314 void *md_template; /* FW template will be stored */
1315 void *md_capture_buff; /* FW dump will be stored */
1316 };
1317
1318
1319
1320 struct netxen_minidump_template_hdr {
1321 u32 entry_type;
1322 u32 first_entry_offset;
1323 u32 size_of_template;
1324 u32 capture_mask;
1325 u32 num_of_entries;
1326 u32 version;
1327 u32 driver_timestamp;
1328 u32 checksum;
1329 u32 driver_capture_mask;
1330 u32 driver_info_word2;
1331 u32 driver_info_word3;
1332 u32 driver_info_word4;
1333 u32 saved_state_array[NX_DUMP_STATE_ARRAY_LEN];
1334 u32 capture_size_array[NX_DUMP_CAP_SIZE_ARRAY_LEN];
1335 u32 rsvd[0];
1336 };
1337
1338 /* Common Entry Header: Common to All Entry Types */
1339 /*
1340 * Driver Code is for driver to write some info about the entry.
1341 * Currently not used.
1342 */
1343
1344 struct netxen_common_entry_hdr {
1345 u32 entry_type;
1346 u32 entry_size;
1347 u32 entry_capture_size;
1348 union {
1349 struct {
1350 u8 entry_capture_mask;
1351 u8 entry_code;
1352 u8 driver_code;
1353 u8 driver_flags;
1354 };
1355 u32 entry_ctrl_word;
1356 };
1357 };
1358
1359
1360 /* Generic Entry Including Header */
1361 struct netxen_minidump_entry {
1362 struct netxen_common_entry_hdr hdr;
1363 u32 entry_data00;
1364 u32 entry_data01;
1365 u32 entry_data02;
1366 u32 entry_data03;
1367 u32 entry_data04;
1368 u32 entry_data05;
1369 u32 entry_data06;
1370 u32 entry_data07;
1371 };
1372
1373 /* Read ROM Header */
1374 struct netxen_minidump_entry_rdrom {
1375 struct netxen_common_entry_hdr h;
1376 union {
1377 struct {
1378 u32 select_addr_reg;
1379 };
1380 u32 rsvd_0;
1381 };
1382 union {
1383 struct {
1384 u8 addr_stride;
1385 u8 addr_cnt;
1386 u16 data_size;
1387 };
1388 u32 rsvd_1;
1389 };
1390 union {
1391 struct {
1392 u32 op_count;
1393 };
1394 u32 rsvd_2;
1395 };
1396 union {
1397 struct {
1398 u32 read_addr_reg;
1399 };
1400 u32 rsvd_3;
1401 };
1402 union {
1403 struct {
1404 u32 write_mask;
1405 };
1406 u32 rsvd_4;
1407 };
1408 union {
1409 struct {
1410 u32 read_mask;
1411 };
1412 u32 rsvd_5;
1413 };
1414 u32 read_addr;
1415 u32 read_data_size;
1416 };
1417
1418
1419 /* Read CRB and Control Entry Header */
1420 struct netxen_minidump_entry_crb {
1421 struct netxen_common_entry_hdr h;
1422 u32 addr;
1423 union {
1424 struct {
1425 u8 addr_stride;
1426 u8 state_index_a;
1427 u16 poll_timeout;
1428 };
1429 u32 addr_cntrl;
1430 };
1431 u32 data_size;
1432 u32 op_count;
1433 union {
1434 struct {
1435 u8 opcode;
1436 u8 state_index_v;
1437 u8 shl;
1438 u8 shr;
1439 };
1440 u32 control_value;
1441 };
1442 u32 value_1;
1443 u32 value_2;
1444 u32 value_3;
1445 };
1446
1447 /* Read Memory and MN Header */
1448 struct netxen_minidump_entry_rdmem {
1449 struct netxen_common_entry_hdr h;
1450 union {
1451 struct {
1452 u32 select_addr_reg;
1453 };
1454 u32 rsvd_0;
1455 };
1456 union {
1457 struct {
1458 u8 addr_stride;
1459 u8 addr_cnt;
1460 u16 data_size;
1461 };
1462 u32 rsvd_1;
1463 };
1464 union {
1465 struct {
1466 u32 op_count;
1467 };
1468 u32 rsvd_2;
1469 };
1470 union {
1471 struct {
1472 u32 read_addr_reg;
1473 };
1474 u32 rsvd_3;
1475 };
1476 union {
1477 struct {
1478 u32 cntrl_addr_reg;
1479 };
1480 u32 rsvd_4;
1481 };
1482 union {
1483 struct {
1484 u8 wr_byte0;
1485 u8 wr_byte1;
1486 u8 poll_mask;
1487 u8 poll_cnt;
1488 };
1489 u32 rsvd_5;
1490 };
1491 u32 read_addr;
1492 u32 read_data_size;
1493 };
1494
1495 /* Read Cache L1 and L2 Header */
1496 struct netxen_minidump_entry_cache {
1497 struct netxen_common_entry_hdr h;
1498 u32 tag_reg_addr;
1499 union {
1500 struct {
1501 u16 tag_value_stride;
1502 u16 init_tag_value;
1503 };
1504 u32 select_addr_cntrl;
1505 };
1506 u32 data_size;
1507 u32 op_count;
1508 u32 control_addr;
1509 union {
1510 struct {
1511 u16 write_value;
1512 u8 poll_mask;
1513 u8 poll_wait;
1514 };
1515 u32 control_value;
1516 };
1517 u32 read_addr;
1518 union {
1519 struct {
1520 u8 read_addr_stride;
1521 u8 read_addr_cnt;
1522 u16 rsvd_1;
1523 };
1524 u32 read_addr_cntrl;
1525 };
1526 };
1527
1528 /* Read OCM Header */
1529 struct netxen_minidump_entry_rdocm {
1530 struct netxen_common_entry_hdr h;
1531 u32 rsvd_0;
1532 union {
1533 struct {
1534 u32 rsvd_1;
1535 };
1536 u32 select_addr_cntrl;
1537 };
1538 u32 data_size;
1539 u32 op_count;
1540 u32 rsvd_2;
1541 u32 rsvd_3;
1542 u32 read_addr;
1543 union {
1544 struct {
1545 u32 read_addr_stride;
1546 };
1547 u32 read_addr_cntrl;
1548 };
1549 };
1550
1551 /* Read MUX Header */
1552 struct netxen_minidump_entry_mux {
1553 struct netxen_common_entry_hdr h;
1554 u32 select_addr;
1555 union {
1556 struct {
1557 u32 rsvd_0;
1558 };
1559 u32 select_addr_cntrl;
1560 };
1561 u32 data_size;
1562 u32 op_count;
1563 u32 select_value;
1564 u32 select_value_stride;
1565 u32 read_addr;
1566 u32 rsvd_1;
1567 };
1568
1569 /* Read Queue Header */
1570 struct netxen_minidump_entry_queue {
1571 struct netxen_common_entry_hdr h;
1572 u32 select_addr;
1573 union {
1574 struct {
1575 u16 queue_id_stride;
1576 u16 rsvd_0;
1577 };
1578 u32 select_addr_cntrl;
1579 };
1580 u32 data_size;
1581 u32 op_count;
1582 u32 rsvd_1;
1583 u32 rsvd_2;
1584 u32 read_addr;
1585 union {
1586 struct {
1587 u8 read_addr_stride;
1588 u8 read_addr_cnt;
1589 u16 rsvd_3;
1590 };
1591 u32 read_addr_cntrl;
1592 };
1593 };
1594
1595 struct netxen_dummy_dma {
1596 void *addr;
1597 dma_addr_t phys_addr;
1598 };
1599
1600 struct netxen_adapter {
1601 struct netxen_hardware_context ahw;
1602
1603 struct net_device *netdev;
1604 struct pci_dev *pdev;
1605 struct list_head mac_list;
1606 struct list_head ip_list;
1607
1608 spinlock_t tx_clean_lock;
1609
1610 u16 num_txd;
1611 u16 num_rxd;
1612 u16 num_jumbo_rxd;
1613 u16 num_lro_rxd;
1614
1615 u8 max_rds_rings;
1616 u8 max_sds_rings;
1617 u8 driver_mismatch;
1618 u8 msix_supported;
1619 u8 __pad;
1620 u8 pci_using_dac;
1621 u8 portnum;
1622 u8 physical_port;
1623
1624 u8 mc_enabled;
1625 u8 max_mc_count;
1626 u8 rss_supported;
1627 u8 link_changed;
1628 u8 fw_wait_cnt;
1629 u8 fw_fail_cnt;
1630 u8 tx_timeo_cnt;
1631 u8 need_fw_reset;
1632
1633 u8 has_link_events;
1634 u8 fw_type;
1635 u16 tx_context_id;
1636 u16 mtu;
1637 u16 is_up;
1638
1639 u16 link_speed;
1640 u16 link_duplex;
1641 u16 link_autoneg;
1642 u16 module_type;
1643
1644 u32 capabilities;
1645 u32 flags;
1646 u32 irq;
1647 u32 temp;
1648
1649 u32 int_vec_bit;
1650 u32 heartbit;
1651
1652 u8 mac_addr[ETH_ALEN];
1653
1654 struct netxen_adapter_stats stats;
1655
1656 struct netxen_recv_context recv_ctx;
1657 struct nx_host_tx_ring *tx_ring;
1658
1659 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1660 int (*set_mtu) (struct netxen_adapter *, int);
1661 int (*set_promisc) (struct netxen_adapter *, u32);
1662 void (*set_multi) (struct net_device *);
1663 int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *);
1664 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val);
1665 int (*init_port) (struct netxen_adapter *, int);
1666 int (*stop_port) (struct netxen_adapter *);
1667
1668 u32 (*crb_read)(struct netxen_adapter *, ulong);
1669 int (*crb_write)(struct netxen_adapter *, ulong, u32);
1670
1671 int (*pci_mem_read)(struct netxen_adapter *, u64, u64 *);
1672 int (*pci_mem_write)(struct netxen_adapter *, u64, u64);
1673
1674 int (*pci_set_window)(struct netxen_adapter *, u64, u32 *);
1675
1676 u32 (*io_read)(struct netxen_adapter *, void __iomem *);
1677 void (*io_write)(struct netxen_adapter *, void __iomem *, u32);
1678
1679 void __iomem *tgt_mask_reg;
1680 void __iomem *pci_int_reg;
1681 void __iomem *tgt_status_reg;
1682 void __iomem *crb_int_state_reg;
1683 void __iomem *isr_int_vec;
1684
1685 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1686
1687 struct netxen_dummy_dma dummy_dma;
1688
1689 struct delayed_work fw_work;
1690
1691 struct work_struct tx_timeout_task;
1692
1693 nx_nic_intr_coalesce_t coal;
1694
1695 unsigned long state;
1696 __le32 file_prd_off; /*File fw product offset*/
1697 u32 fw_version;
1698 const struct firmware *fw;
1699 struct netxen_minidump mdump; /* mdump ptr */
1700 int fw_mdump_rdy; /* for mdump ready */
1701 };
1702
1703 int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val);
1704 int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val);
1705
1706 #define NXRD32(adapter, off) \
1707 (adapter->crb_read(adapter, off))
1708 #define NXWR32(adapter, off, val) \
1709 (adapter->crb_write(adapter, off, val))
1710 #define NXRDIO(adapter, addr) \
1711 (adapter->io_read(adapter, addr))
1712 #define NXWRIO(adapter, addr, val) \
1713 (adapter->io_write(adapter, addr, val))
1714
1715 int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32);
1716 void netxen_pcie_sem_unlock(struct netxen_adapter *, int);
1717
1718 #define netxen_rom_lock(a) \
1719 netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID)
1720 #define netxen_rom_unlock(a) \
1721 netxen_pcie_sem_unlock((a), 2)
1722 #define netxen_phy_lock(a) \
1723 netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID)
1724 #define netxen_phy_unlock(a) \
1725 netxen_pcie_sem_unlock((a), 3)
1726 #define netxen_api_lock(a) \
1727 netxen_pcie_sem_lock((a), 5, 0)
1728 #define netxen_api_unlock(a) \
1729 netxen_pcie_sem_unlock((a), 5)
1730 #define netxen_sw_lock(a) \
1731 netxen_pcie_sem_lock((a), 6, 0)
1732 #define netxen_sw_unlock(a) \
1733 netxen_pcie_sem_unlock((a), 6)
1734 #define crb_win_lock(a) \
1735 netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID)
1736 #define crb_win_unlock(a) \
1737 netxen_pcie_sem_unlock((a), 7)
1738
1739 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1740 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1741
1742 /* Functions from netxen_nic_init.c */
1743 int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1744 void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1745
1746 int netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter);
1747 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1748 int netxen_load_firmware(struct netxen_adapter *adapter);
1749 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1750 void netxen_request_firmware(struct netxen_adapter *adapter);
1751 void netxen_release_firmware(struct netxen_adapter *adapter);
1752 int netxen_pinit_from_rom(struct netxen_adapter *adapter);
1753
1754 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1755 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1756 u8 *bytes, size_t size);
1757 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1758 u8 *bytes, size_t size);
1759 int netxen_flash_unlock(struct netxen_adapter *adapter);
1760 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1761 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1762 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1763 void netxen_halt_pegs(struct netxen_adapter *adapter);
1764
1765 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1766
1767 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1768 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1769
1770 void netxen_setup_hwops(struct netxen_adapter *adapter);
1771 void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32);
1772
1773 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1774 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1775
1776 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1777 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1778
1779 int netxen_init_firmware(struct netxen_adapter *adapter);
1780 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1781 void netxen_watchdog_task(struct work_struct *work);
1782 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1783 struct nx_host_rds_ring *rds_ring);
1784 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1785 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1786
1787 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1788 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1789 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1790 int netxen_config_ipaddr(struct netxen_adapter *adapter, __be32 ip, int cmd);
1791 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1792 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1793 void netxen_pci_camqm_read_2M(struct netxen_adapter *, u64, u64 *);
1794 void netxen_pci_camqm_write_2M(struct netxen_adapter *, u64, u64);
1795
1796 int nx_fw_cmd_set_gbe_port(struct netxen_adapter *adapter,
1797 u32 speed, u32 duplex, u32 autoneg);
1798 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1799 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1800 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable);
1801 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable);
1802 int netxen_send_lro_cleanup(struct netxen_adapter *adapter);
1803 int netxen_setup_minidump(struct netxen_adapter *adapter);
1804 void netxen_dump_fw(struct netxen_adapter *adapter);
1805 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1806 struct nx_host_tx_ring *tx_ring);
1807
1808 /* Functions from netxen_nic_main.c */
1809 int netxen_nic_reset_context(struct netxen_adapter *);
1810
1811 int nx_dev_request_reset(struct netxen_adapter *adapter);
1812
1813 /*
1814 * NetXen Board information
1815 */
1816
1817 #define NETXEN_MAX_SHORT_NAME 32
1818 struct netxen_brdinfo {
1819 int brdtype; /* type of board */
1820 long ports; /* max no of physical ports */
1821 char short_name[NETXEN_MAX_SHORT_NAME];
1822 };
1823
1824 struct netxen_dimm_cfg {
1825 u8 presence;
1826 u8 mem_type;
1827 u8 dimm_type;
1828 u32 size;
1829 };
1830
1831 static const struct netxen_brdinfo netxen_boards[] = {
1832 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1833 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1834 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1835 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1836 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1837 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1838 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1839 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1840 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1841 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1842 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1843 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1844 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1845 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1846 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1847 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1848 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1849 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1850 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1851 };
1852
1853 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1854
1855 static inline int netxen_nic_get_brd_name_by_type(u32 type, char *name)
1856 {
1857 int i, found = 0;
1858 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1859 if (netxen_boards[i].brdtype == type) {
1860 strcpy(name, netxen_boards[i].short_name);
1861 found = 1;
1862 break;
1863 }
1864 }
1865
1866 if (!found) {
1867 strcpy(name, "Unknown");
1868 return -EINVAL;
1869 }
1870
1871 return 0;
1872 }
1873
1874 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1875 {
1876 smp_mb();
1877 return find_diff_among(tx_ring->producer,
1878 tx_ring->sw_consumer, tx_ring->num_desc);
1879
1880 }
1881
1882 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1883 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1884 void netxen_change_ringparam(struct netxen_adapter *adapter);
1885 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1886
1887 extern const struct ethtool_ops netxen_nic_ethtool_ops;
1888
1889 #endif /* __NETXEN_NIC_H_ */
Linux kernel - Deliverables
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