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netxen_nic: fix cdrp race condition
[deliverable/linux.git] / drivers / net / ethernet / qlogic / netxen / netxen_nic_ctx.c
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26 #include "netxen_nic_hw.h"
27 #include "netxen_nic.h"
28
29 #define NXHAL_VERSION 1
30
31 static u32
32 netxen_poll_rsp(struct netxen_adapter *adapter)
33 {
34 u32 rsp = NX_CDRP_RSP_OK;
35 int timeout = 0;
36
37 do {
38 /* give atleast 1ms for firmware to respond */
39 msleep(1);
40
41 if (++timeout > NX_OS_CRB_RETRY_COUNT)
42 return NX_CDRP_RSP_TIMEOUT;
43
44 rsp = NXRD32(adapter, NX_CDRP_CRB_OFFSET);
45 } while (!NX_CDRP_IS_RSP(rsp));
46
47 return rsp;
48 }
49
50 static u32
51 netxen_issue_cmd(struct netxen_adapter *adapter, struct netxen_cmd_args *cmd)
52 {
53 u32 rsp;
54 u32 signature = 0;
55 u32 rcode = NX_RCODE_SUCCESS;
56
57 signature = NX_CDRP_SIGNATURE_MAKE(adapter->ahw.pci_func,
58 NXHAL_VERSION);
59 /* Acquire semaphore before accessing CRB */
60 if (netxen_api_lock(adapter))
61 return NX_RCODE_TIMEOUT;
62
63 NXWR32(adapter, NX_SIGN_CRB_OFFSET, signature);
64
65 NXWR32(adapter, NX_ARG1_CRB_OFFSET, cmd->req.arg1);
66
67 NXWR32(adapter, NX_ARG2_CRB_OFFSET, cmd->req.arg2);
68
69 NXWR32(adapter, NX_ARG3_CRB_OFFSET, cmd->req.arg3);
70
71 NXWR32(adapter, NX_CDRP_CRB_OFFSET, NX_CDRP_FORM_CMD(cmd->req.cmd));
72
73 rsp = netxen_poll_rsp(adapter);
74
75 if (rsp == NX_CDRP_RSP_TIMEOUT) {
76 printk(KERN_ERR "%s: card response timeout.\n",
77 netxen_nic_driver_name);
78
79 rcode = NX_RCODE_TIMEOUT;
80 } else if (rsp == NX_CDRP_RSP_FAIL) {
81 rcode = NXRD32(adapter, NX_ARG1_CRB_OFFSET);
82
83 printk(KERN_ERR "%s: failed card response code:0x%x\n",
84 netxen_nic_driver_name, rcode);
85 } else if (rsp == NX_CDRP_RSP_OK) {
86 if (cmd->rsp.arg2)
87 cmd->rsp.arg2 = NXRD32(adapter, NX_ARG2_CRB_OFFSET);
88 if (cmd->rsp.arg3)
89 cmd->rsp.arg3 = NXRD32(adapter, NX_ARG3_CRB_OFFSET);
90 }
91
92 if (cmd->rsp.arg1)
93 cmd->rsp.arg1 = NXRD32(adapter, NX_ARG1_CRB_OFFSET);
94 /* Release semaphore */
95 netxen_api_unlock(adapter);
96
97 return rcode;
98 }
99
100 int
101 nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu)
102 {
103 u32 rcode = NX_RCODE_SUCCESS;
104 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
105 struct netxen_cmd_args cmd;
106
107 memset(&cmd, 0, sizeof(cmd));
108 cmd.req.cmd = NX_CDRP_CMD_SET_MTU;
109 cmd.req.arg1 = recv_ctx->context_id;
110 cmd.req.arg2 = mtu;
111 cmd.req.arg3 = 0;
112
113 if (recv_ctx->state == NX_HOST_CTX_STATE_ACTIVE)
114 netxen_issue_cmd(adapter, &cmd);
115
116 if (rcode != NX_RCODE_SUCCESS)
117 return -EIO;
118
119 return 0;
120 }
121
122 int
123 nx_fw_cmd_set_gbe_port(struct netxen_adapter *adapter,
124 u32 speed, u32 duplex, u32 autoneg)
125 {
126 struct netxen_cmd_args cmd;
127
128 memset(&cmd, 0, sizeof(cmd));
129 cmd.req.cmd = NX_CDRP_CMD_CONFIG_GBE_PORT;
130 cmd.req.arg1 = speed;
131 cmd.req.arg2 = duplex;
132 cmd.req.arg3 = autoneg;
133 return netxen_issue_cmd(adapter, &cmd);
134 }
135
136 static int
137 nx_fw_cmd_create_rx_ctx(struct netxen_adapter *adapter)
138 {
139 void *addr;
140 nx_hostrq_rx_ctx_t *prq;
141 nx_cardrsp_rx_ctx_t *prsp;
142 nx_hostrq_rds_ring_t *prq_rds;
143 nx_hostrq_sds_ring_t *prq_sds;
144 nx_cardrsp_rds_ring_t *prsp_rds;
145 nx_cardrsp_sds_ring_t *prsp_sds;
146 struct nx_host_rds_ring *rds_ring;
147 struct nx_host_sds_ring *sds_ring;
148 struct netxen_cmd_args cmd;
149
150 dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
151 u64 phys_addr;
152
153 int i, nrds_rings, nsds_rings;
154 size_t rq_size, rsp_size;
155 u32 cap, reg, val;
156
157 int err;
158
159 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
160
161 nrds_rings = adapter->max_rds_rings;
162 nsds_rings = adapter->max_sds_rings;
163
164 rq_size =
165 SIZEOF_HOSTRQ_RX(nx_hostrq_rx_ctx_t, nrds_rings, nsds_rings);
166 rsp_size =
167 SIZEOF_CARDRSP_RX(nx_cardrsp_rx_ctx_t, nrds_rings, nsds_rings);
168
169 addr = pci_alloc_consistent(adapter->pdev,
170 rq_size, &hostrq_phys_addr);
171 if (addr == NULL)
172 return -ENOMEM;
173 prq = addr;
174
175 addr = pci_alloc_consistent(adapter->pdev,
176 rsp_size, &cardrsp_phys_addr);
177 if (addr == NULL) {
178 err = -ENOMEM;
179 goto out_free_rq;
180 }
181 prsp = addr;
182
183 prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
184
185 cap = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN);
186 cap |= (NX_CAP0_JUMBO_CONTIGUOUS | NX_CAP0_LRO_CONTIGUOUS);
187
188 prq->capabilities[0] = cpu_to_le32(cap);
189 prq->host_int_crb_mode =
190 cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
191 prq->host_rds_crb_mode =
192 cpu_to_le32(NX_HOST_RDS_CRB_MODE_UNIQUE);
193
194 prq->num_rds_rings = cpu_to_le16(nrds_rings);
195 prq->num_sds_rings = cpu_to_le16(nsds_rings);
196 prq->rds_ring_offset = cpu_to_le32(0);
197
198 val = le32_to_cpu(prq->rds_ring_offset) +
199 (sizeof(nx_hostrq_rds_ring_t) * nrds_rings);
200 prq->sds_ring_offset = cpu_to_le32(val);
201
202 prq_rds = (nx_hostrq_rds_ring_t *)(prq->data +
203 le32_to_cpu(prq->rds_ring_offset));
204
205 for (i = 0; i < nrds_rings; i++) {
206
207 rds_ring = &recv_ctx->rds_rings[i];
208
209 prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
210 prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
211 prq_rds[i].ring_kind = cpu_to_le32(i);
212 prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
213 }
214
215 prq_sds = (nx_hostrq_sds_ring_t *)(prq->data +
216 le32_to_cpu(prq->sds_ring_offset));
217
218 for (i = 0; i < nsds_rings; i++) {
219
220 sds_ring = &recv_ctx->sds_rings[i];
221
222 prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
223 prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
224 prq_sds[i].msi_index = cpu_to_le16(i);
225 }
226
227 phys_addr = hostrq_phys_addr;
228 memset(&cmd, 0, sizeof(cmd));
229 cmd.req.arg1 = (u32)(phys_addr >> 32);
230 cmd.req.arg2 = (u32)(phys_addr & 0xffffffff);
231 cmd.req.arg3 = rq_size;
232 cmd.req.cmd = NX_CDRP_CMD_CREATE_RX_CTX;
233 err = netxen_issue_cmd(adapter, &cmd);
234 if (err) {
235 printk(KERN_WARNING
236 "Failed to create rx ctx in firmware%d\n", err);
237 goto out_free_rsp;
238 }
239
240
241 prsp_rds = ((nx_cardrsp_rds_ring_t *)
242 &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
243
244 for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
245 rds_ring = &recv_ctx->rds_rings[i];
246
247 reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
248 rds_ring->crb_rcv_producer = netxen_get_ioaddr(adapter,
249 NETXEN_NIC_REG(reg - 0x200));
250 }
251
252 prsp_sds = ((nx_cardrsp_sds_ring_t *)
253 &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
254
255 for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
256 sds_ring = &recv_ctx->sds_rings[i];
257
258 reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
259 sds_ring->crb_sts_consumer = netxen_get_ioaddr(adapter,
260 NETXEN_NIC_REG(reg - 0x200));
261
262 reg = le32_to_cpu(prsp_sds[i].interrupt_crb);
263 sds_ring->crb_intr_mask = netxen_get_ioaddr(adapter,
264 NETXEN_NIC_REG(reg - 0x200));
265 }
266
267 recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
268 recv_ctx->context_id = le16_to_cpu(prsp->context_id);
269 recv_ctx->virt_port = prsp->virt_port;
270
271 out_free_rsp:
272 pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr);
273 out_free_rq:
274 pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr);
275 return err;
276 }
277
278 static void
279 nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter)
280 {
281 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
282 struct netxen_cmd_args cmd;
283
284 memset(&cmd, 0, sizeof(cmd));
285 cmd.req.arg1 = recv_ctx->context_id;
286 cmd.req.arg2 = NX_DESTROY_CTX_RESET;
287 cmd.req.arg3 = 0;
288 cmd.req.cmd = NX_CDRP_CMD_DESTROY_RX_CTX;
289
290 if (netxen_issue_cmd(adapter, &cmd)) {
291 printk(KERN_WARNING
292 "%s: Failed to destroy rx ctx in firmware\n",
293 netxen_nic_driver_name);
294 }
295 }
296
297 static int
298 nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter)
299 {
300 nx_hostrq_tx_ctx_t *prq;
301 nx_hostrq_cds_ring_t *prq_cds;
302 nx_cardrsp_tx_ctx_t *prsp;
303 void *rq_addr, *rsp_addr;
304 size_t rq_size, rsp_size;
305 u32 temp;
306 int err = 0;
307 u64 offset, phys_addr;
308 dma_addr_t rq_phys_addr, rsp_phys_addr;
309 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
310 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
311 struct netxen_cmd_args cmd;
312
313 rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t);
314 rq_addr = pci_alloc_consistent(adapter->pdev,
315 rq_size, &rq_phys_addr);
316 if (!rq_addr)
317 return -ENOMEM;
318
319 rsp_size = SIZEOF_CARDRSP_TX(nx_cardrsp_tx_ctx_t);
320 rsp_addr = pci_alloc_consistent(adapter->pdev,
321 rsp_size, &rsp_phys_addr);
322 if (!rsp_addr) {
323 err = -ENOMEM;
324 goto out_free_rq;
325 }
326
327 memset(rq_addr, 0, rq_size);
328 prq = rq_addr;
329
330 memset(rsp_addr, 0, rsp_size);
331 prsp = rsp_addr;
332
333 prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
334
335 temp = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN | NX_CAP0_LSO);
336 prq->capabilities[0] = cpu_to_le32(temp);
337
338 prq->host_int_crb_mode =
339 cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
340
341 prq->interrupt_ctl = 0;
342 prq->msi_index = 0;
343
344 prq->dummy_dma_addr = cpu_to_le64(adapter->dummy_dma.phys_addr);
345
346 offset = recv_ctx->phys_addr + sizeof(struct netxen_ring_ctx);
347 prq->cmd_cons_dma_addr = cpu_to_le64(offset);
348
349 prq_cds = &prq->cds_ring;
350
351 prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
352 prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
353
354 phys_addr = rq_phys_addr;
355 memset(&cmd, 0, sizeof(cmd));
356 cmd.req.arg1 = (u32)(phys_addr >> 32);
357 cmd.req.arg2 = ((u32)phys_addr & 0xffffffff);
358 cmd.req.arg3 = rq_size;
359 cmd.req.cmd = NX_CDRP_CMD_CREATE_TX_CTX;
360 err = netxen_issue_cmd(adapter, &cmd);
361
362 if (err == NX_RCODE_SUCCESS) {
363 temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
364 tx_ring->crb_cmd_producer = netxen_get_ioaddr(adapter,
365 NETXEN_NIC_REG(temp - 0x200));
366 #if 0
367 adapter->tx_state =
368 le32_to_cpu(prsp->host_ctx_state);
369 #endif
370 adapter->tx_context_id =
371 le16_to_cpu(prsp->context_id);
372 } else {
373 printk(KERN_WARNING
374 "Failed to create tx ctx in firmware%d\n", err);
375 err = -EIO;
376 }
377
378 pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr);
379
380 out_free_rq:
381 pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr);
382
383 return err;
384 }
385
386 static void
387 nx_fw_cmd_destroy_tx_ctx(struct netxen_adapter *adapter)
388 {
389 struct netxen_cmd_args cmd;
390
391 memset(&cmd, 0, sizeof(cmd));
392 cmd.req.arg1 = adapter->tx_context_id;
393 cmd.req.arg2 = NX_DESTROY_CTX_RESET;
394 cmd.req.arg3 = 0;
395 cmd.req.cmd = NX_CDRP_CMD_DESTROY_TX_CTX;
396 if (netxen_issue_cmd(adapter, &cmd)) {
397 printk(KERN_WARNING
398 "%s: Failed to destroy tx ctx in firmware\n",
399 netxen_nic_driver_name);
400 }
401 }
402
403 int
404 nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val)
405 {
406 u32 rcode;
407 struct netxen_cmd_args cmd;
408
409 memset(&cmd, 0, sizeof(cmd));
410 cmd.req.arg1 = reg;
411 cmd.req.arg2 = 0;
412 cmd.req.arg3 = 0;
413 cmd.req.cmd = NX_CDRP_CMD_READ_PHY;
414 cmd.rsp.arg1 = 1;
415 rcode = netxen_issue_cmd(adapter, &cmd);
416 if (rcode != NX_RCODE_SUCCESS)
417 return -EIO;
418
419 return cmd.rsp.arg1;
420 }
421
422 int
423 nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val)
424 {
425 u32 rcode;
426 struct netxen_cmd_args cmd;
427
428 memset(&cmd, 0, sizeof(cmd));
429 cmd.req.arg1 = reg;
430 cmd.req.arg2 = val;
431 cmd.req.arg3 = 0;
432 cmd.req.cmd = NX_CDRP_CMD_WRITE_PHY;
433 rcode = netxen_issue_cmd(adapter, &cmd);
434 if (rcode != NX_RCODE_SUCCESS)
435 return -EIO;
436
437 return 0;
438 }
439
440 static u64 ctx_addr_sig_regs[][3] = {
441 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
442 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
443 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
444 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
445 };
446
447 #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
448 #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
449 #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
450
451 #define lower32(x) ((u32)((x) & 0xffffffff))
452 #define upper32(x) ((u32)(((u64)(x) >> 32) & 0xffffffff))
453
454 static struct netxen_recv_crb recv_crb_registers[] = {
455 /* Instance 0 */
456 {
457 /* crb_rcv_producer: */
458 {
459 NETXEN_NIC_REG(0x100),
460 /* Jumbo frames */
461 NETXEN_NIC_REG(0x110),
462 /* LRO */
463 NETXEN_NIC_REG(0x120)
464 },
465 /* crb_sts_consumer: */
466 {
467 NETXEN_NIC_REG(0x138),
468 NETXEN_NIC_REG_2(0x000),
469 NETXEN_NIC_REG_2(0x004),
470 NETXEN_NIC_REG_2(0x008),
471 },
472 /* sw_int_mask */
473 {
474 CRB_SW_INT_MASK_0,
475 NETXEN_NIC_REG_2(0x044),
476 NETXEN_NIC_REG_2(0x048),
477 NETXEN_NIC_REG_2(0x04c),
478 },
479 },
480 /* Instance 1 */
481 {
482 /* crb_rcv_producer: */
483 {
484 NETXEN_NIC_REG(0x144),
485 /* Jumbo frames */
486 NETXEN_NIC_REG(0x154),
487 /* LRO */
488 NETXEN_NIC_REG(0x164)
489 },
490 /* crb_sts_consumer: */
491 {
492 NETXEN_NIC_REG(0x17c),
493 NETXEN_NIC_REG_2(0x020),
494 NETXEN_NIC_REG_2(0x024),
495 NETXEN_NIC_REG_2(0x028),
496 },
497 /* sw_int_mask */
498 {
499 CRB_SW_INT_MASK_1,
500 NETXEN_NIC_REG_2(0x064),
501 NETXEN_NIC_REG_2(0x068),
502 NETXEN_NIC_REG_2(0x06c),
503 },
504 },
505 /* Instance 2 */
506 {
507 /* crb_rcv_producer: */
508 {
509 NETXEN_NIC_REG(0x1d8),
510 /* Jumbo frames */
511 NETXEN_NIC_REG(0x1f8),
512 /* LRO */
513 NETXEN_NIC_REG(0x208)
514 },
515 /* crb_sts_consumer: */
516 {
517 NETXEN_NIC_REG(0x220),
518 NETXEN_NIC_REG_2(0x03c),
519 NETXEN_NIC_REG_2(0x03c),
520 NETXEN_NIC_REG_2(0x03c),
521 },
522 /* sw_int_mask */
523 {
524 CRB_SW_INT_MASK_2,
525 NETXEN_NIC_REG_2(0x03c),
526 NETXEN_NIC_REG_2(0x03c),
527 NETXEN_NIC_REG_2(0x03c),
528 },
529 },
530 /* Instance 3 */
531 {
532 /* crb_rcv_producer: */
533 {
534 NETXEN_NIC_REG(0x22c),
535 /* Jumbo frames */
536 NETXEN_NIC_REG(0x23c),
537 /* LRO */
538 NETXEN_NIC_REG(0x24c)
539 },
540 /* crb_sts_consumer: */
541 {
542 NETXEN_NIC_REG(0x264),
543 NETXEN_NIC_REG_2(0x03c),
544 NETXEN_NIC_REG_2(0x03c),
545 NETXEN_NIC_REG_2(0x03c),
546 },
547 /* sw_int_mask */
548 {
549 CRB_SW_INT_MASK_3,
550 NETXEN_NIC_REG_2(0x03c),
551 NETXEN_NIC_REG_2(0x03c),
552 NETXEN_NIC_REG_2(0x03c),
553 },
554 },
555 };
556
557 static int
558 netxen_init_old_ctx(struct netxen_adapter *adapter)
559 {
560 struct netxen_recv_context *recv_ctx;
561 struct nx_host_rds_ring *rds_ring;
562 struct nx_host_sds_ring *sds_ring;
563 struct nx_host_tx_ring *tx_ring;
564 int ring;
565 int port = adapter->portnum;
566 struct netxen_ring_ctx *hwctx;
567 u32 signature;
568
569 tx_ring = adapter->tx_ring;
570 recv_ctx = &adapter->recv_ctx;
571 hwctx = recv_ctx->hwctx;
572
573 hwctx->cmd_ring_addr = cpu_to_le64(tx_ring->phys_addr);
574 hwctx->cmd_ring_size = cpu_to_le32(tx_ring->num_desc);
575
576
577 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
578 rds_ring = &recv_ctx->rds_rings[ring];
579
580 hwctx->rcv_rings[ring].addr =
581 cpu_to_le64(rds_ring->phys_addr);
582 hwctx->rcv_rings[ring].size =
583 cpu_to_le32(rds_ring->num_desc);
584 }
585
586 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
587 sds_ring = &recv_ctx->sds_rings[ring];
588
589 if (ring == 0) {
590 hwctx->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr);
591 hwctx->sts_ring_size = cpu_to_le32(sds_ring->num_desc);
592 }
593 hwctx->sts_rings[ring].addr = cpu_to_le64(sds_ring->phys_addr);
594 hwctx->sts_rings[ring].size = cpu_to_le32(sds_ring->num_desc);
595 hwctx->sts_rings[ring].msi_index = cpu_to_le16(ring);
596 }
597 hwctx->sts_ring_count = cpu_to_le32(adapter->max_sds_rings);
598
599 signature = (adapter->max_sds_rings > 1) ?
600 NETXEN_CTX_SIGNATURE_V2 : NETXEN_CTX_SIGNATURE;
601
602 NXWR32(adapter, CRB_CTX_ADDR_REG_LO(port),
603 lower32(recv_ctx->phys_addr));
604 NXWR32(adapter, CRB_CTX_ADDR_REG_HI(port),
605 upper32(recv_ctx->phys_addr));
606 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
607 signature | port);
608 return 0;
609 }
610
611 int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
612 {
613 void *addr;
614 int err = 0;
615 int ring;
616 struct netxen_recv_context *recv_ctx;
617 struct nx_host_rds_ring *rds_ring;
618 struct nx_host_sds_ring *sds_ring;
619 struct nx_host_tx_ring *tx_ring;
620
621 struct pci_dev *pdev = adapter->pdev;
622 struct net_device *netdev = adapter->netdev;
623 int port = adapter->portnum;
624
625 recv_ctx = &adapter->recv_ctx;
626 tx_ring = adapter->tx_ring;
627
628 addr = pci_alloc_consistent(pdev,
629 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
630 &recv_ctx->phys_addr);
631 if (addr == NULL) {
632 dev_err(&pdev->dev, "failed to allocate hw context\n");
633 return -ENOMEM;
634 }
635
636 memset(addr, 0, sizeof(struct netxen_ring_ctx));
637 recv_ctx->hwctx = addr;
638 recv_ctx->hwctx->ctx_id = cpu_to_le32(port);
639 recv_ctx->hwctx->cmd_consumer_offset =
640 cpu_to_le64(recv_ctx->phys_addr +
641 sizeof(struct netxen_ring_ctx));
642 tx_ring->hw_consumer =
643 (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx));
644
645 /* cmd desc ring */
646 addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring),
647 &tx_ring->phys_addr);
648
649 if (addr == NULL) {
650 dev_err(&pdev->dev, "%s: failed to allocate tx desc ring\n",
651 netdev->name);
652 err = -ENOMEM;
653 goto err_out_free;
654 }
655
656 tx_ring->desc_head = addr;
657
658 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
659 rds_ring = &recv_ctx->rds_rings[ring];
660 addr = pci_alloc_consistent(adapter->pdev,
661 RCV_DESC_RINGSIZE(rds_ring),
662 &rds_ring->phys_addr);
663 if (addr == NULL) {
664 dev_err(&pdev->dev,
665 "%s: failed to allocate rds ring [%d]\n",
666 netdev->name, ring);
667 err = -ENOMEM;
668 goto err_out_free;
669 }
670 rds_ring->desc_head = addr;
671
672 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
673 rds_ring->crb_rcv_producer =
674 netxen_get_ioaddr(adapter,
675 recv_crb_registers[port].crb_rcv_producer[ring]);
676 }
677
678 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
679 sds_ring = &recv_ctx->sds_rings[ring];
680
681 addr = pci_alloc_consistent(adapter->pdev,
682 STATUS_DESC_RINGSIZE(sds_ring),
683 &sds_ring->phys_addr);
684 if (addr == NULL) {
685 dev_err(&pdev->dev,
686 "%s: failed to allocate sds ring [%d]\n",
687 netdev->name, ring);
688 err = -ENOMEM;
689 goto err_out_free;
690 }
691 sds_ring->desc_head = addr;
692
693 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
694 sds_ring->crb_sts_consumer =
695 netxen_get_ioaddr(adapter,
696 recv_crb_registers[port].crb_sts_consumer[ring]);
697
698 sds_ring->crb_intr_mask =
699 netxen_get_ioaddr(adapter,
700 recv_crb_registers[port].sw_int_mask[ring]);
701 }
702 }
703
704
705 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
706 if (test_and_set_bit(__NX_FW_ATTACHED, &adapter->state))
707 goto done;
708 err = nx_fw_cmd_create_rx_ctx(adapter);
709 if (err)
710 goto err_out_free;
711 err = nx_fw_cmd_create_tx_ctx(adapter);
712 if (err)
713 goto err_out_free;
714 } else {
715 err = netxen_init_old_ctx(adapter);
716 if (err)
717 goto err_out_free;
718 }
719
720 done:
721 return 0;
722
723 err_out_free:
724 netxen_free_hw_resources(adapter);
725 return err;
726 }
727
728 void netxen_free_hw_resources(struct netxen_adapter *adapter)
729 {
730 struct netxen_recv_context *recv_ctx;
731 struct nx_host_rds_ring *rds_ring;
732 struct nx_host_sds_ring *sds_ring;
733 struct nx_host_tx_ring *tx_ring;
734 int ring;
735
736 int port = adapter->portnum;
737
738 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
739 if (!test_and_clear_bit(__NX_FW_ATTACHED, &adapter->state))
740 goto done;
741
742 nx_fw_cmd_destroy_rx_ctx(adapter);
743 nx_fw_cmd_destroy_tx_ctx(adapter);
744 } else {
745 netxen_api_lock(adapter);
746 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
747 NETXEN_CTX_D3_RESET | port);
748 netxen_api_unlock(adapter);
749 }
750
751 /* Allow dma queues to drain after context reset */
752 msleep(20);
753
754 done:
755 recv_ctx = &adapter->recv_ctx;
756
757 if (recv_ctx->hwctx != NULL) {
758 pci_free_consistent(adapter->pdev,
759 sizeof(struct netxen_ring_ctx) +
760 sizeof(uint32_t),
761 recv_ctx->hwctx,
762 recv_ctx->phys_addr);
763 recv_ctx->hwctx = NULL;
764 }
765
766 tx_ring = adapter->tx_ring;
767 if (tx_ring->desc_head != NULL) {
768 pci_free_consistent(adapter->pdev,
769 TX_DESC_RINGSIZE(tx_ring),
770 tx_ring->desc_head, tx_ring->phys_addr);
771 tx_ring->desc_head = NULL;
772 }
773
774 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
775 rds_ring = &recv_ctx->rds_rings[ring];
776
777 if (rds_ring->desc_head != NULL) {
778 pci_free_consistent(adapter->pdev,
779 RCV_DESC_RINGSIZE(rds_ring),
780 rds_ring->desc_head,
781 rds_ring->phys_addr);
782 rds_ring->desc_head = NULL;
783 }
784 }
785
786 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
787 sds_ring = &recv_ctx->sds_rings[ring];
788
789 if (sds_ring->desc_head != NULL) {
790 pci_free_consistent(adapter->pdev,
791 STATUS_DESC_RINGSIZE(sds_ring),
792 sds_ring->desc_head,
793 sds_ring->phys_addr);
794 sds_ring->desc_head = NULL;
795 }
796 }
797 }
798
Linux kernel - Deliverables
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