1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
18 #include <linux/mutex.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/string.h>
22 #include <linux/workqueue.h>
23 #include <linux/zlib.h>
24 #include <linux/hashtable.h>
25 #include <linux/qed/qed_if.h>
26 #include "qed_debug.h"
29 extern const struct qed_common_ops qed_common_ops_pass
;
30 #define DRV_MODULE_VERSION "8.10.9.20"
32 #define MAX_HWFNS_PER_DEVICE (4)
36 #define QED_WFQ_UNIT 100
39 enum qed_coalescing_mode
{
40 QED_COAL_MODE_DISABLE
,
44 struct qed_eth_cb_ops
;
46 union qed_mcp_protocol_stats
;
47 enum qed_mcp_protocol_type
;
50 static inline u32
qed_db_addr(u32 cid
, u32 DEMS
)
52 u32 db_addr
= FIELD_VALUE(DB_LEGACY_ADDR_DEMS
, DEMS
) |
53 FIELD_VALUE(DB_LEGACY_ADDR_ICID
, cid
);
58 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
59 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
60 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
62 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
64 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
65 (val == (cond1) ? true1 : \
66 (val == (cond2) ? true2 : def))
72 struct qed_sb_attn_info
;
74 struct qed_sb_sp_info
;
83 QED_MODE_L2GENEVE_TUNN
,
84 QED_MODE_IPGENEVE_TUNN
,
91 QED_TUNN_CLSS_MAC_VLAN
,
92 QED_TUNN_CLSS_MAC_VNI
,
93 QED_TUNN_CLSS_INNER_MAC_VLAN
,
94 QED_TUNN_CLSS_INNER_MAC_VNI
,
98 struct qed_tunn_start_params
{
99 unsigned long tunn_mode
;
102 u8 update_vxlan_udp_port
;
103 u8 update_geneve_udp_port
;
105 u8 tunn_clss_l2geneve
;
106 u8 tunn_clss_ipgeneve
;
111 struct qed_tunn_update_params
{
112 unsigned long tunn_mode_update_mask
;
113 unsigned long tunn_mode
;
116 u8 update_rx_pf_clss
;
117 u8 update_tx_pf_clss
;
118 u8 update_vxlan_udp_port
;
119 u8 update_geneve_udp_port
;
121 u8 tunn_clss_l2geneve
;
122 u8 tunn_clss_ipgeneve
;
127 /* The PCI personality is not quite synonymous to protocol ID:
128 * 1. All personalities need CORE connections
129 * 2. The Ethernet personality may support also the RoCE protocol
131 enum qed_pci_personality
{
135 QED_PCI_DEFAULT
/* default in shmem */
138 /* All VFs are symmetric, all counters are PF + all VFs */
165 QED_PORT_MODE_DE_2X40G
,
166 QED_PORT_MODE_DE_2X50G
,
167 QED_PORT_MODE_DE_1X100G
,
168 QED_PORT_MODE_DE_4X10G_F
,
169 QED_PORT_MODE_DE_4X10G_E
,
170 QED_PORT_MODE_DE_4X20G
,
171 QED_PORT_MODE_DE_1X40G
,
172 QED_PORT_MODE_DE_2X25G
,
173 QED_PORT_MODE_DE_1X25G
183 /* PCI personality */
184 enum qed_pci_personality personality
;
186 /* Resource Allocation scheme results */
187 u32 resc_start
[QED_MAX_RESC
];
188 u32 resc_num
[QED_MAX_RESC
];
189 u32 feat_num
[QED_MAX_FEATURES
];
191 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
192 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
193 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
194 RESC_NUM(_p_hwfn, resc))
195 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
206 unsigned char hw_mac_addr
[ETH_ALEN
];
208 struct qed_igu_info
*p_igu_info
;
212 unsigned long device_capabilities
;
215 struct qed_hw_cid_data
{
217 bool b_cid_allocated
;
219 /* Additional identifiers */
224 /* maximun size of read/write commands (HW limit) */
225 #define DMAE_MAX_RW_SIZE 0x2000
227 struct qed_dmae_info
{
228 /* Mutex for synchronizing access to functions */
233 dma_addr_t completion_word_phys_addr
;
235 /* The memory location where the DMAE writes the completion
236 * value when an operation is finished on this context.
238 u32
*p_completion_word
;
240 dma_addr_t intermediate_buffer_phys_addr
;
242 /* An intermediate buffer for DMAE operations that use virtual
243 * addresses - data is DMA'd to/from this buffer and then
244 * memcpy'd to/from the virtual address
246 u32
*p_intermediate_buffer
;
248 dma_addr_t dmae_cmd_phys_addr
;
249 struct dmae_cmd
*p_dmae_cmd
;
252 struct qed_wfq_data
{
253 /* when feature is configured for at least 1 vport */
259 struct init_qm_pq_params
*qm_pq_params
;
260 struct init_qm_vport_params
*qm_vport_params
;
261 struct init_qm_port_params
*qm_port_params
;
272 u8 max_phys_tcs_per_port
;
279 struct qed_wfq_data
*wfq_data
;
288 struct qed_storm_stats
{
289 struct storm_stats mstats
;
290 struct storm_stats pstats
;
291 struct storm_stats tstats
;
292 struct storm_stats ustats
;
296 struct fw_ver_info
*fw_ver_info
;
297 const u8
*modes_tree_buf
;
298 union init_op
*init_ops
;
303 struct qed_simd_fp_handler
{
305 void (*func
)(void *);
309 struct qed_dev
*cdev
;
310 u8 my_id
; /* ID inside the PF */
311 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
312 u8 rel_pf_id
; /* Relative to engine*/
314 #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
320 char name
[NAME_SIZE
];
322 bool first_on_engine
;
325 u8 num_funcs_on_engine
;
329 void __iomem
*regview
;
330 void __iomem
*doorbells
;
332 unsigned long db_size
;
335 struct qed_ptt_pool
*p_ptt_pool
;
338 struct qed_hw_info hw_info
;
340 /* rt_array (for init-tool) */
341 struct qed_rt_data rt_data
;
344 struct qed_spq
*p_spq
;
350 struct qed_consq
*p_consq
;
352 /* Slow-Path definitions */
353 struct tasklet_struct
*sp_dpc
;
354 bool b_sp_dpc_enabled
;
356 struct qed_ptt
*p_main_ptt
;
357 struct qed_ptt
*p_dpc_ptt
;
359 struct qed_sb_sp_info
*p_sp_sb
;
360 struct qed_sb_attn_info
*p_sb_attn
;
362 /* Protocol related */
363 struct qed_pf_params pf_params
;
365 bool b_rdma_enabled_in_prs
;
366 u32 rdma_prs_search_reg
;
368 /* Array of sb_info of all status blocks */
369 struct qed_sb_info
*sbs_info
[MAX_SB_PER_PF_MIMD
];
372 struct qed_cxt_mngr
*p_cxt_mngr
;
374 /* Flag indicating whether interrupts are enabled or not*/
376 bool b_int_requested
;
378 /* True if the driver requests for the link */
379 bool b_drv_link_init
;
381 struct qed_vf_iov
*vf_iov_info
;
382 struct qed_pf_iov
*pf_iov_info
;
383 struct qed_mcp_info
*mcp_info
;
385 struct qed_dcbx_info
*p_dcbx_info
;
387 struct qed_hw_cid_data
*p_tx_cids
;
388 struct qed_hw_cid_data
*p_rx_cids
;
390 struct qed_dmae_info dmae_info
;
393 struct qed_qm_info qm_info
;
394 struct qed_storm_stats storm_stats
;
396 /* Buffer for unzipping firmware data */
399 struct dbg_tools_data dbg_info
;
401 struct qed_simd_fp_handler simd_proto_handler
[64];
403 #ifdef CONFIG_QED_SRIOV
404 struct workqueue_struct
*iov_wq
;
405 struct delayed_work iov_task
;
406 unsigned long iov_task_flags
;
409 struct z_stream_s
*stream
;
415 unsigned long mem_start
;
416 unsigned long mem_end
;
421 struct qed_int_param
{
424 u8 min_msix_cnt
; /* for minimal functionality */
427 struct qed_int_params
{
428 struct qed_int_param in
;
429 struct qed_int_param out
;
430 struct msix_entry
*msix_table
;
436 struct qed_dbg_feature
{
437 struct dentry
*dentry
;
443 struct qed_dbg_params
{
444 struct qed_dbg_feature features
[DBG_FEATURE_NUM
];
452 char name
[NAME_SIZE
];
455 #define QED_DEV_TYPE_BB (0 << 0)
456 #define QED_DEV_TYPE_AH BIT(0)
457 /* Translate type/revision combo into the proper conditions */
458 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
459 #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
461 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
463 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
464 #define QED_IS_K2(dev) QED_IS_AH(dev)
466 #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
467 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
473 #define CHIP_NUM_MASK 0xffff
474 #define CHIP_NUM_SHIFT 16
477 #define CHIP_REV_MASK 0xf
478 #define CHIP_REV_SHIFT 12
479 #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
480 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
483 #define CHIP_METAL_MASK 0xff
484 #define CHIP_METAL_SHIFT 4
487 #define CHIP_BOND_ID_MASK 0xf
488 #define CHIP_BOND_ID_SHIFT 0
491 u8 num_ports_in_engines
;
492 u8 num_funcs_in_port
;
495 enum qed_mf_mode mf_mode
;
496 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
497 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
498 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
502 u8 ver_str
[VER_SIZE
];
504 /* Add MF related configuration */
511 enum qed_coalescing_mode int_coalescing_mode
;
512 u16 rx_coalesce_usecs
;
513 u16 tx_coalesce_usecs
;
515 /* Start Bar offset of first hwfn */
516 void __iomem
*regview
;
517 void __iomem
*doorbells
;
519 unsigned long db_size
;
525 const struct iro
*iro_arr
;
526 #define IRO (p_hwfn->cdev->iro_arr)
530 struct qed_hwfn hwfns
[MAX_HWFNS_PER_DEVICE
];
533 struct qed_hw_sriov_info
*p_iov_info
;
534 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
536 unsigned long tunn_mode
;
541 struct qed_eth_stats
*reset_stats
;
542 struct qed_fw_data
*fw_data
;
546 /* Linux specific here */
547 struct qede_dev
*edev
;
548 struct pci_dev
*pdev
;
551 struct pci_params pci_params
;
553 struct qed_int_params int_params
;
556 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
558 /* Callbacks to protocol driver */
560 struct qed_common_cb_ops
*common
;
561 struct qed_eth_cb_ops
*eth
;
565 struct qed_dbg_params dbg_params
;
567 const struct firmware
*firmware
;
570 #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB
571 #define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB
572 #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
573 #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
576 * @brief qed_concrete_to_sw_fid - get the sw function id from
577 * the concrete value.
579 * @param concrete_fid
583 static inline u8
qed_concrete_to_sw_fid(struct qed_dev
*cdev
,
586 u8 vfid
= GET_FIELD(concrete_fid
, PXP_CONCRETE_FID_VFID
);
587 u8 pfid
= GET_FIELD(concrete_fid
, PXP_CONCRETE_FID_PFID
);
588 u8 vf_valid
= GET_FIELD(concrete_fid
,
589 PXP_CONCRETE_FID_VFVALID
);
593 sw_fid
= vfid
+ MAX_NUM_PFS
;
603 int qed_configure_vport_wfq(struct qed_dev
*cdev
, u16 vp_id
, u32 rate
);
604 void qed_configure_vp_wfq_on_link_change(struct qed_dev
*cdev
, u32 min_pf_rate
);
606 void qed_clean_wfq_db(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
);
607 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
609 /* Other Linux specific common definitions */
610 #define DP_NAME(cdev) ((cdev)->name)
612 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
616 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
617 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
618 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
620 #define DOORBELL(cdev, db_addr, val) \
621 writel((u32)val, (void __iomem *)((u8 __iomem *)\
622 (cdev->doorbells) + (db_addr)))
625 int qed_fill_dev_info(struct qed_dev
*cdev
,
626 struct qed_dev_info
*dev_info
);
627 void qed_link_update(struct qed_hwfn
*hwfn
);
628 u32
qed_unzip_data(struct qed_hwfn
*p_hwfn
,
629 u32 input_len
, u8
*input_buf
,
630 u32 max_size
, u8
*unzip_buf
);
631 void qed_get_protocol_stats(struct qed_dev
*cdev
,
632 enum qed_mcp_protocol_type type
,
633 union qed_mcp_protocol_stats
*stats
);
634 int qed_slowpath_irq_req(struct qed_hwfn
*hwfn
);