drivers/net/ethernet/qlogic/qed/qed.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef _QED_H
  10 #define _QED_H
  11
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <linux/delay.h>
  15 #include <linux/firmware.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/list.h>
  18 #include <linux/mutex.h>
  19 #include <linux/pci.h>
  20 #include <linux/slab.h>
  21 #include <linux/string.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/zlib.h>
  24 #include <linux/hashtable.h>
  25 #include <linux/qed/qed_if.h>
  26 #include "qed_hsi.h"
  27
  28 extern const struct qed_common_ops qed_common_ops_pass;
  29 #define DRV_MODULE_VERSION "8.4.0.0"
  30
  31 #define MAX_HWFNS_PER_DEVICE    (4)
  32 #define NAME_SIZE 16
  33 #define VER_SIZE 16
  34
  35 /* cau states */
  36 enum qed_coalescing_mode {
  37         QED_COAL_MODE_DISABLE,
  38         QED_COAL_MODE_ENABLE
  39 };
  40
  41 struct qed_eth_cb_ops;
  42 struct qed_dev_info;
  43
  44 /* helpers */
  45 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
  46 {
  47         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
  48                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
  49
  50         return db_addr;
  51 }
  52
  53 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                                 \
  54         ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
  55          ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
  56
  57 #define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)
  58
  59 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
  60         (val == (cond1) ? true1 :                     \
  61          (val == (cond2) ? true2 : def))
  62
  63 /* forward */
  64 struct qed_ptt_pool;
  65 struct qed_spq;
  66 struct qed_sb_info;
  67 struct qed_sb_attn_info;
  68 struct qed_cxt_mngr;
  69 struct qed_sb_sp_info;
  70 struct qed_mcp_info;
  71
  72 struct qed_rt_data {
  73         u32 init_val;
  74         bool b_valid;
  75 };
  76
  77 /* The PCI personality is not quite synonymous to protocol ID:
  78  * 1. All personalities need CORE connections
  79  * 2. The Ethernet personality may support also the RoCE protocol
  80  */
  81 enum qed_pci_personality {
  82         QED_PCI_ETH,
  83         QED_PCI_DEFAULT /* default in shmem */
  84 };
  85
  86 /* All VFs are symmetric, all counters are PF + all VFs */
  87 struct qed_qm_iids {
  88         u32 cids;
  89         u32 vf_cids;
  90         u32 tids;
  91 };
  92
  93 enum QED_RESOURCES {
  94         QED_SB,
  95         QED_L2_QUEUE,
  96         QED_VPORT,
  97         QED_RSS_ENG,
  98         QED_PQ,
  99         QED_RL,
 100         QED_MAC,
 101         QED_VLAN,
 102         QED_ILT,
 103         QED_MAX_RESC,
 104 };
 105
 106 enum QED_FEATURE {
 107         QED_PF_L2_QUE,
 108         QED_MAX_FEATURES,
 109 };
 110
 111 enum QED_PORT_MODE {
 112         QED_PORT_MODE_DE_2X40G,
 113         QED_PORT_MODE_DE_2X50G,
 114         QED_PORT_MODE_DE_1X100G,
 115         QED_PORT_MODE_DE_4X10G_F,
 116         QED_PORT_MODE_DE_4X10G_E,
 117         QED_PORT_MODE_DE_4X20G,
 118         QED_PORT_MODE_DE_1X40G,
 119         QED_PORT_MODE_DE_2X25G,
 120         QED_PORT_MODE_DE_1X25G
 121 };
 122
 123 struct qed_hw_info {
 124         /* PCI personality */
 125         enum qed_pci_personality        personality;
 126
 127         /* Resource Allocation scheme results */
 128         u32                             resc_start[QED_MAX_RESC];
 129         u32                             resc_num[QED_MAX_RESC];
 130         u32                             feat_num[QED_MAX_FEATURES];
 131
 132 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 133 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 134 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 135
 136         u8                              num_tc;
 137         u8                              offload_tc;
 138         u8                              non_offload_tc;
 139
 140         u32                             concrete_fid;
 141         u16                             opaque_fid;
 142         u16                             ovlan;
 143         u32                             part_num[4];
 144
 145         u32                             vendor_id;
 146         u32                             device_id;
 147
 148         unsigned char                   hw_mac_addr[ETH_ALEN];
 149
 150         struct qed_igu_info             *p_igu_info;
 151
 152         u32                             port_mode;
 153         u32                             hw_mode;
 154 };
 155
 156 struct qed_hw_cid_data {
 157         u32     cid;
 158         bool    b_cid_allocated;
 159
 160         /* Additional identifiers */
 161         u16     opaque_fid;
 162         u8      vport_id;
 163 };
 164
 165 /* maximun size of read/write commands (HW limit) */
 166 #define DMAE_MAX_RW_SIZE        0x2000
 167
 168 struct qed_dmae_info {
 169         /* Mutex for synchronizing access to functions */
 170         struct mutex    mutex;
 171
 172         u8              channel;
 173
 174         dma_addr_t      completion_word_phys_addr;
 175
 176         /* The memory location where the DMAE writes the completion
 177          * value when an operation is finished on this context.
 178          */
 179         u32             *p_completion_word;
 180
 181         dma_addr_t      intermediate_buffer_phys_addr;
 182
 183         /* An intermediate buffer for DMAE operations that use virtual
 184          * addresses - data is DMA'd to/from this buffer and then
 185          * memcpy'd to/from the virtual address
 186          */
 187         u32             *p_intermediate_buffer;
 188
 189         dma_addr_t      dmae_cmd_phys_addr;
 190         struct dmae_cmd *p_dmae_cmd;
 191 };
 192
 193 struct qed_qm_info {
 194         struct init_qm_pq_params        *qm_pq_params;
 195         struct init_qm_vport_params     *qm_vport_params;
 196         struct init_qm_port_params      *qm_port_params;
 197         u16                             start_pq;
 198         u8                              start_vport;
 199         u8                              pure_lb_pq;
 200         u8                              offload_pq;
 201         u8                              pure_ack_pq;
 202         u8                              vf_queues_offset;
 203         u16                             num_pqs;
 204         u16                             num_vf_pqs;
 205         u8                              num_vports;
 206         u8                              max_phys_tcs_per_port;
 207         bool                            pf_rl_en;
 208         bool                            pf_wfq_en;
 209         bool                            vport_rl_en;
 210         bool                            vport_wfq_en;
 211         u8                              pf_wfq;
 212         u32                             pf_rl;
 213 };
 214
 215 struct storm_stats {
 216         u32     address;
 217         u32     len;
 218 };
 219
 220 struct qed_storm_stats {
 221         struct storm_stats mstats;
 222         struct storm_stats pstats;
 223         struct storm_stats tstats;
 224         struct storm_stats ustats;
 225 };
 226
 227 struct qed_fw_data {
 228         struct fw_ver_info      *fw_ver_info;
 229         const u8                *modes_tree_buf;
 230         union init_op           *init_ops;
 231         const u32               *arr_data;
 232         u32                     init_ops_size;
 233 };
 234
 235 struct qed_simd_fp_handler {
 236         void    *token;
 237         void    (*func)(void *);
 238 };
 239
 240 struct qed_hwfn {
 241         struct qed_dev                  *cdev;
 242         u8                              my_id;          /* ID inside the PF */
 243 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 244         u8                              rel_pf_id;      /* Relative to engine*/
 245         u8                              abs_pf_id;
 246 #define QED_PATH_ID(_p_hwfn)            ((_p_hwfn)->abs_pf_id & 1)
 247         u8                              port_id;
 248         bool                            b_active;
 249
 250         u32                             dp_module;
 251         u8                              dp_level;
 252         char                            name[NAME_SIZE];
 253
 254         bool                            first_on_engine;
 255         bool                            hw_init_done;
 256
 257         /* BAR access */
 258         void __iomem                    *regview;
 259         void __iomem                    *doorbells;
 260         u64                             db_phys_addr;
 261         unsigned long                   db_size;
 262
 263         /* PTT pool */
 264         struct qed_ptt_pool             *p_ptt_pool;
 265
 266         /* HW info */
 267         struct qed_hw_info              hw_info;
 268
 269         /* rt_array (for init-tool) */
 270         struct qed_rt_data              *rt_data;
 271
 272         /* SPQ */
 273         struct qed_spq                  *p_spq;
 274
 275         /* EQ */
 276         struct qed_eq                   *p_eq;
 277
 278         /* Consolidate Q*/
 279         struct qed_consq                *p_consq;
 280
 281         /* Slow-Path definitions */
 282         struct tasklet_struct           *sp_dpc;
 283         bool                            b_sp_dpc_enabled;
 284
 285         struct qed_ptt                  *p_main_ptt;
 286         struct qed_ptt                  *p_dpc_ptt;
 287
 288         struct qed_sb_sp_info           *p_sp_sb;
 289         struct qed_sb_attn_info         *p_sb_attn;
 290
 291         /* Protocol related */
 292         struct qed_pf_params            pf_params;
 293
 294         /* Array of sb_info of all status blocks */
 295         struct qed_sb_info              *sbs_info[MAX_SB_PER_PF_MIMD];
 296         u16                             num_sbs;
 297
 298         struct qed_cxt_mngr             *p_cxt_mngr;
 299
 300         /* Flag indicating whether interrupts are enabled or not*/
 301         bool                            b_int_enabled;
 302         bool                            b_int_requested;
 303
 304         struct qed_mcp_info             *mcp_info;
 305
 306         struct qed_hw_cid_data          *p_tx_cids;
 307         struct qed_hw_cid_data          *p_rx_cids;
 308
 309         struct qed_dmae_info            dmae_info;
 310
 311         /* QM init */
 312         struct qed_qm_info              qm_info;
 313         struct qed_storm_stats          storm_stats;
 314
 315         /* Buffer for unzipping firmware data */
 316         void                            *unzip_buf;
 317
 318         struct qed_simd_fp_handler      simd_proto_handler[64];
 319
 320         struct z_stream_s               *stream;
 321 };
 322
 323 struct pci_params {
 324         int             pm_cap;
 325
 326         unsigned long   mem_start;
 327         unsigned long   mem_end;
 328         unsigned int    irq;
 329         u8              pf_num;
 330 };
 331
 332 struct qed_int_param {
 333         u32     int_mode;
 334         u8      num_vectors;
 335         u8      min_msix_cnt; /* for minimal functionality */
 336 };
 337
 338 struct qed_int_params {
 339         struct qed_int_param    in;
 340         struct qed_int_param    out;
 341         struct msix_entry       *msix_table;
 342         bool                    fp_initialized;
 343         u8                      fp_msix_base;
 344         u8                      fp_msix_cnt;
 345 };
 346
 347 struct qed_dev {
 348         u32     dp_module;
 349         u8      dp_level;
 350         char    name[NAME_SIZE];
 351
 352         u8      type;
 353 #define QED_DEV_TYPE_BB_A0      (0 << 0)
 354 #define QED_DEV_TYPE_MASK       (0x3)
 355 #define QED_DEV_TYPE_SHIFT      (0)
 356
 357         u16     chip_num;
 358 #define CHIP_NUM_MASK                   0xffff
 359 #define CHIP_NUM_SHIFT                  16
 360
 361         u16     chip_rev;
 362 #define CHIP_REV_MASK                   0xf
 363 #define CHIP_REV_SHIFT                  12
 364
 365         u16                             chip_metal;
 366 #define CHIP_METAL_MASK                 0xff
 367 #define CHIP_METAL_SHIFT                4
 368
 369         u16                             chip_bond_id;
 370 #define CHIP_BOND_ID_MASK               0xf
 371 #define CHIP_BOND_ID_SHIFT              0
 372
 373         u8                              num_engines;
 374         u8                              num_ports_in_engines;
 375         u8                              num_funcs_in_port;
 376
 377         u8                              path_id;
 378         enum mf_mode                    mf_mode;
 379 #define IS_MF(_p_hwfn)          (((_p_hwfn)->cdev)->mf_mode != SF)
 380 #define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == MF_NPAR)
 381 #define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == MF_OVLAN)
 382
 383         int                             pcie_width;
 384         int                             pcie_speed;
 385         u8                              ver_str[VER_SIZE];
 386
 387         /* Add MF related configuration */
 388         u8                              mcp_rev;
 389         u8                              boot_mode;
 390
 391         u8                              wol;
 392
 393         u32                             int_mode;
 394         enum qed_coalescing_mode        int_coalescing_mode;
 395         u8                              rx_coalesce_usecs;
 396         u8                              tx_coalesce_usecs;
 397
 398         /* Start Bar offset of first hwfn */
 399         void __iomem                    *regview;
 400         void __iomem                    *doorbells;
 401         u64                             db_phys_addr;
 402         unsigned long                   db_size;
 403
 404         /* PCI */
 405         u8                              cache_shift;
 406
 407         /* Init */
 408         const struct iro                *iro_arr;
 409 #define IRO (p_hwfn->cdev->iro_arr)
 410
 411         /* HW functions */
 412         u8                              num_hwfns;
 413         struct qed_hwfn                 hwfns[MAX_HWFNS_PER_DEVICE];
 414
 415         u32                             drv_type;
 416
 417         struct qed_eth_stats            *reset_stats;
 418         struct qed_fw_data              *fw_data;
 419
 420         u32                             mcp_nvm_resp;
 421
 422         /* Linux specific here */
 423         struct  qede_dev                *edev;
 424         struct  pci_dev                 *pdev;
 425         int                             msg_enable;
 426
 427         struct pci_params               pci_params;
 428
 429         struct qed_int_params           int_params;
 430
 431         u8                              protocol;
 432 #define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
 433
 434         /* Callbacks to protocol driver */
 435         union {
 436                 struct qed_common_cb_ops        *common;
 437                 struct qed_eth_cb_ops           *eth;
 438         } protocol_ops;
 439         void                            *ops_cookie;
 440
 441         const struct firmware           *firmware;
 442 };
 443
 444 #define QED_GET_TYPE(dev)       (((dev)->type & QED_DEV_TYPE_MASK) >> \
 445                                  QED_DEV_TYPE_SHIFT)
 446 #define QED_IS_BB_A0(dev)       (QED_GET_TYPE(dev) == QED_DEV_TYPE_BB_A0)
 447 #define QED_IS_BB(dev)  (QED_IS_BB_A0(dev))
 448
 449 #define NUM_OF_SBS(dev)         MAX_SB_PER_PATH_BB
 450 #define NUM_OF_ENG_PFS(dev)     MAX_NUM_PFS_BB
 451
 452 /**
 453  * @brief qed_concrete_to_sw_fid - get the sw function id from
 454  *        the concrete value.
 455  *
 456  * @param concrete_fid
 457  *
 458  * @return inline u8
 459  */
 460 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
 461                                         u32 concrete_fid)
 462 {
 463         u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 464
 465         return pfid;
 466 }
 467
 468 #define PURE_LB_TC 8
 469
 470 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 471
 472 /* Other Linux specific common definitions */
 473 #define DP_NAME(cdev) ((cdev)->name)
 474
 475 #define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
 476                                                 (cdev->regview) + \
 477                                                          (offset))
 478
 479 #define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
 480 #define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
 481 #define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))
 482
 483 #define DOORBELL(cdev, db_addr, val)                     \
 484         writel((u32)val, (void __iomem *)((u8 __iomem *)\
 485                                           (cdev->doorbells) + (db_addr)))
 486
 487 /* Prototypes */
 488 int qed_fill_dev_info(struct qed_dev *cdev,
 489                       struct qed_dev_info *dev_info);
 490 void qed_link_update(struct qed_hwfn *hwfn);
 491 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
 492                    u32 input_len, u8 *input_buf,
 493                    u32 max_size, u8 *unzip_buf);
 494
 495 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
 496
 497 #define QED_ETH_INTERFACE_VERSION       300
 498
 499 #endif /* _QED_H */