1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #include <linux/types.h>
10 #include <asm/byteorder.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/etherdevice.h>
21 #include <linux/qed/qed_chain.h>
22 #include <linux/qed/qed_if.h>
25 #include "qed_dev_api.h"
28 #include "qed_init_ops.h"
31 #include "qed_reg_addr.h"
34 /* API common to all protocols */
36 BAR_ID_0
, /* used for GRC */
37 BAR_ID_1
/* Used for doorbells */
40 static u32
qed_hw_bar_size(struct qed_hwfn
*p_hwfn
,
43 u32 bar_reg
= (bar_id
== BAR_ID_0
?
44 PGLUE_B_REG_PF_BAR0_SIZE
: PGLUE_B_REG_PF_BAR1_SIZE
);
45 u32 val
= qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
, bar_reg
);
48 return 1 << (val
+ 15);
50 /* Old MFW initialized above registered only conditionally */
51 if (p_hwfn
->cdev
->num_hwfns
> 1) {
53 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
54 return BAR_ID_0
? 256 * 1024 : 512 * 1024;
57 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
62 void qed_init_dp(struct qed_dev
*cdev
,
63 u32 dp_module
, u8 dp_level
)
67 cdev
->dp_level
= dp_level
;
68 cdev
->dp_module
= dp_module
;
69 for (i
= 0; i
< MAX_HWFNS_PER_DEVICE
; i
++) {
70 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
72 p_hwfn
->dp_level
= dp_level
;
73 p_hwfn
->dp_module
= dp_module
;
77 void qed_init_struct(struct qed_dev
*cdev
)
81 for (i
= 0; i
< MAX_HWFNS_PER_DEVICE
; i
++) {
82 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
86 p_hwfn
->b_active
= false;
88 mutex_init(&p_hwfn
->dmae_info
.mutex
);
91 /* hwfn 0 is always active */
92 cdev
->hwfns
[0].b_active
= true;
94 /* set the default cache alignment to 128 */
95 cdev
->cache_shift
= 7;
98 static void qed_qm_info_free(struct qed_hwfn
*p_hwfn
)
100 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
102 kfree(qm_info
->qm_pq_params
);
103 qm_info
->qm_pq_params
= NULL
;
104 kfree(qm_info
->qm_vport_params
);
105 qm_info
->qm_vport_params
= NULL
;
106 kfree(qm_info
->qm_port_params
);
107 qm_info
->qm_port_params
= NULL
;
110 void qed_resc_free(struct qed_dev
*cdev
)
114 kfree(cdev
->fw_data
);
115 cdev
->fw_data
= NULL
;
117 kfree(cdev
->reset_stats
);
119 for_each_hwfn(cdev
, i
) {
120 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
122 kfree(p_hwfn
->p_tx_cids
);
123 p_hwfn
->p_tx_cids
= NULL
;
124 kfree(p_hwfn
->p_rx_cids
);
125 p_hwfn
->p_rx_cids
= NULL
;
128 for_each_hwfn(cdev
, i
) {
129 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
131 qed_cxt_mngr_free(p_hwfn
);
132 qed_qm_info_free(p_hwfn
);
133 qed_spq_free(p_hwfn
);
134 qed_eq_free(p_hwfn
, p_hwfn
->p_eq
);
135 qed_consq_free(p_hwfn
, p_hwfn
->p_consq
);
136 qed_int_free(p_hwfn
);
137 qed_dmae_info_free(p_hwfn
);
141 static int qed_init_qm_info(struct qed_hwfn
*p_hwfn
)
143 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
144 struct init_qm_port_params
*p_qm_port
;
145 u8 num_vports
, i
, vport_id
, num_ports
;
146 u16 num_pqs
, multi_cos_tcs
= 1;
148 memset(qm_info
, 0, sizeof(*qm_info
));
150 num_pqs
= multi_cos_tcs
+ 1; /* The '1' is for pure-LB */
151 num_vports
= (u8
)RESC_NUM(p_hwfn
, QED_VPORT
);
153 /* Sanity checking that setup requires legal number of resources */
154 if (num_pqs
> RESC_NUM(p_hwfn
, QED_PQ
)) {
156 "Need too many Physical queues - 0x%04x when only %04x are available\n",
157 num_pqs
, RESC_NUM(p_hwfn
, QED_PQ
));
161 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
163 qm_info
->qm_pq_params
= kzalloc(sizeof(*qm_info
->qm_pq_params
) *
164 num_pqs
, GFP_KERNEL
);
165 if (!qm_info
->qm_pq_params
)
168 qm_info
->qm_vport_params
= kzalloc(sizeof(*qm_info
->qm_vport_params
) *
169 num_vports
, GFP_KERNEL
);
170 if (!qm_info
->qm_vport_params
)
173 qm_info
->qm_port_params
= kzalloc(sizeof(*qm_info
->qm_port_params
) *
174 MAX_NUM_PORTS
, GFP_KERNEL
);
175 if (!qm_info
->qm_port_params
)
178 vport_id
= (u8
)RESC_START(p_hwfn
, QED_VPORT
);
180 /* First init per-TC PQs */
181 for (i
= 0; i
< multi_cos_tcs
; i
++) {
182 struct init_qm_pq_params
*params
= &qm_info
->qm_pq_params
[i
];
184 params
->vport_id
= vport_id
;
185 params
->tc_id
= p_hwfn
->hw_info
.non_offload_tc
;
186 params
->wrr_group
= 1;
189 /* Then init pure-LB PQ */
190 qm_info
->pure_lb_pq
= i
;
191 qm_info
->qm_pq_params
[i
].vport_id
= (u8
)RESC_START(p_hwfn
, QED_VPORT
);
192 qm_info
->qm_pq_params
[i
].tc_id
= PURE_LB_TC
;
193 qm_info
->qm_pq_params
[i
].wrr_group
= 1;
196 qm_info
->offload_pq
= 0;
197 qm_info
->num_pqs
= num_pqs
;
198 qm_info
->num_vports
= num_vports
;
200 /* Initialize qm port parameters */
201 num_ports
= p_hwfn
->cdev
->num_ports_in_engines
;
202 for (i
= 0; i
< num_ports
; i
++) {
203 p_qm_port
= &qm_info
->qm_port_params
[i
];
204 p_qm_port
->active
= 1;
205 p_qm_port
->num_active_phys_tcs
= 4;
206 p_qm_port
->num_pbf_cmd_lines
= PBF_MAX_CMD_LINES
/ num_ports
;
207 p_qm_port
->num_btb_blocks
= BTB_MAX_BLOCKS
/ num_ports
;
210 qm_info
->max_phys_tcs_per_port
= NUM_OF_PHYS_TCS
;
212 qm_info
->start_pq
= (u16
)RESC_START(p_hwfn
, QED_PQ
);
214 qm_info
->start_vport
= (u8
)RESC_START(p_hwfn
, QED_VPORT
);
218 qm_info
->vport_rl_en
= 1;
223 DP_NOTICE(p_hwfn
, "Failed to allocate memory for QM params\n");
224 kfree(qm_info
->qm_pq_params
);
225 kfree(qm_info
->qm_vport_params
);
226 kfree(qm_info
->qm_port_params
);
231 int qed_resc_alloc(struct qed_dev
*cdev
)
233 struct qed_consq
*p_consq
;
237 cdev
->fw_data
= kzalloc(sizeof(*cdev
->fw_data
), GFP_KERNEL
);
241 /* Allocate Memory for the Queue->CID mapping */
242 for_each_hwfn(cdev
, i
) {
243 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
244 int tx_size
= sizeof(struct qed_hw_cid_data
) *
245 RESC_NUM(p_hwfn
, QED_L2_QUEUE
);
246 int rx_size
= sizeof(struct qed_hw_cid_data
) *
247 RESC_NUM(p_hwfn
, QED_L2_QUEUE
);
249 p_hwfn
->p_tx_cids
= kzalloc(tx_size
, GFP_KERNEL
);
250 if (!p_hwfn
->p_tx_cids
) {
252 "Failed to allocate memory for Tx Cids\n");
257 p_hwfn
->p_rx_cids
= kzalloc(rx_size
, GFP_KERNEL
);
258 if (!p_hwfn
->p_rx_cids
) {
260 "Failed to allocate memory for Rx Cids\n");
266 for_each_hwfn(cdev
, i
) {
267 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
269 /* First allocate the context manager structure */
270 rc
= qed_cxt_mngr_alloc(p_hwfn
);
274 /* Set the HW cid/tid numbers (in the contest manager)
275 * Must be done prior to any further computations.
277 rc
= qed_cxt_set_pf_params(p_hwfn
);
281 /* Prepare and process QM requirements */
282 rc
= qed_init_qm_info(p_hwfn
);
286 /* Compute the ILT client partition */
287 rc
= qed_cxt_cfg_ilt_compute(p_hwfn
);
291 /* CID map / ILT shadow table / T2
292 * The talbes sizes are determined by the computations above
294 rc
= qed_cxt_tables_alloc(p_hwfn
);
298 /* SPQ, must follow ILT because initializes SPQ context */
299 rc
= qed_spq_alloc(p_hwfn
);
303 /* SP status block allocation */
304 p_hwfn
->p_dpc_ptt
= qed_get_reserved_ptt(p_hwfn
,
307 rc
= qed_int_alloc(p_hwfn
, p_hwfn
->p_main_ptt
);
312 p_eq
= qed_eq_alloc(p_hwfn
, 256);
319 p_consq
= qed_consq_alloc(p_hwfn
);
324 p_hwfn
->p_consq
= p_consq
;
326 /* DMA info initialization */
327 rc
= qed_dmae_info_alloc(p_hwfn
);
330 "Failed to allocate memory for dmae_info structure\n");
335 cdev
->reset_stats
= kzalloc(sizeof(*cdev
->reset_stats
), GFP_KERNEL
);
336 if (!cdev
->reset_stats
) {
337 DP_NOTICE(cdev
, "Failed to allocate reset statistics\n");
349 void qed_resc_setup(struct qed_dev
*cdev
)
353 for_each_hwfn(cdev
, i
) {
354 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
356 qed_cxt_mngr_setup(p_hwfn
);
357 qed_spq_setup(p_hwfn
);
358 qed_eq_setup(p_hwfn
, p_hwfn
->p_eq
);
359 qed_consq_setup(p_hwfn
, p_hwfn
->p_consq
);
361 /* Read shadow of current MFW mailbox */
362 qed_mcp_read_mb(p_hwfn
, p_hwfn
->p_main_ptt
);
363 memcpy(p_hwfn
->mcp_info
->mfw_mb_shadow
,
364 p_hwfn
->mcp_info
->mfw_mb_cur
,
365 p_hwfn
->mcp_info
->mfw_mb_length
);
367 qed_int_setup(p_hwfn
, p_hwfn
->p_main_ptt
);
371 #define FINAL_CLEANUP_POLL_CNT (100)
372 #define FINAL_CLEANUP_POLL_TIME (10)
373 int qed_final_cleanup(struct qed_hwfn
*p_hwfn
,
374 struct qed_ptt
*p_ptt
,
377 u32 command
= 0, addr
, count
= FINAL_CLEANUP_POLL_CNT
;
380 addr
= GTT_BAR0_MAP_REG_USDM_RAM
+
381 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn
->rel_pf_id
);
383 command
|= X_FINAL_CLEANUP_AGG_INT
<<
384 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT
;
385 command
|= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT
;
386 command
|= id
<< SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT
;
387 command
|= SDM_COMP_TYPE_AGG_INT
<< SDM_OP_GEN_COMP_TYPE_SHIFT
;
389 /* Make sure notification is not set before initiating final cleanup */
390 if (REG_RD(p_hwfn
, addr
)) {
393 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
394 REG_WR(p_hwfn
, addr
, 0);
397 DP_VERBOSE(p_hwfn
, QED_MSG_IOV
,
398 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
401 qed_wr(p_hwfn
, p_ptt
, XSDM_REG_OPERATION_GEN
, command
);
403 /* Poll until completion */
404 while (!REG_RD(p_hwfn
, addr
) && count
--)
405 msleep(FINAL_CLEANUP_POLL_TIME
);
407 if (REG_RD(p_hwfn
, addr
))
411 "Failed to receive FW final cleanup notification\n");
413 /* Cleanup afterwards */
414 REG_WR(p_hwfn
, addr
, 0);
419 static void qed_calc_hw_mode(struct qed_hwfn
*p_hwfn
)
423 hw_mode
= (1 << MODE_BB_A0
);
425 switch (p_hwfn
->cdev
->num_ports_in_engines
) {
427 hw_mode
|= 1 << MODE_PORTS_PER_ENG_1
;
430 hw_mode
|= 1 << MODE_PORTS_PER_ENG_2
;
433 hw_mode
|= 1 << MODE_PORTS_PER_ENG_4
;
436 DP_NOTICE(p_hwfn
, "num_ports_in_engine = %d not supported\n",
437 p_hwfn
->cdev
->num_ports_in_engines
);
441 switch (p_hwfn
->cdev
->mf_mode
) {
444 hw_mode
|= 1 << MODE_MF_SI
;
447 hw_mode
|= 1 << MODE_MF_SD
;
450 DP_NOTICE(p_hwfn
, "Unsupported MF mode, init as DEFAULT\n");
451 hw_mode
|= 1 << MODE_MF_SI
;
454 hw_mode
|= 1 << MODE_ASIC
;
456 p_hwfn
->hw_info
.hw_mode
= hw_mode
;
459 /* Init run time data for all PFs on an engine. */
460 static void qed_init_cau_rt_data(struct qed_dev
*cdev
)
462 u32 offset
= CAU_REG_SB_VAR_MEMORY_RT_OFFSET
;
465 for_each_hwfn(cdev
, i
) {
466 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
467 struct qed_igu_info
*p_igu_info
;
468 struct qed_igu_block
*p_block
;
469 struct cau_sb_entry sb_entry
;
471 p_igu_info
= p_hwfn
->hw_info
.p_igu_info
;
473 for (sb_id
= 0; sb_id
< QED_MAPPING_MEMORY_SIZE(cdev
);
475 p_block
= &p_igu_info
->igu_map
.igu_blocks
[sb_id
];
479 qed_init_cau_sb_entry(p_hwfn
, &sb_entry
,
480 p_block
->function_id
,
482 STORE_RT_REG_AGG(p_hwfn
, offset
+ sb_id
* 2,
488 static int qed_hw_init_common(struct qed_hwfn
*p_hwfn
,
489 struct qed_ptt
*p_ptt
,
492 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
493 struct qed_qm_common_rt_init_params params
;
494 struct qed_dev
*cdev
= p_hwfn
->cdev
;
497 qed_init_cau_rt_data(cdev
);
499 /* Program GTT windows */
500 qed_gtt_init(p_hwfn
);
502 if (p_hwfn
->mcp_info
) {
503 if (p_hwfn
->mcp_info
->func_info
.bandwidth_max
)
504 qm_info
->pf_rl_en
= 1;
505 if (p_hwfn
->mcp_info
->func_info
.bandwidth_min
)
506 qm_info
->pf_wfq_en
= 1;
509 memset(¶ms
, 0, sizeof(params
));
510 params
.max_ports_per_engine
= p_hwfn
->cdev
->num_ports_in_engines
;
511 params
.max_phys_tcs_per_port
= qm_info
->max_phys_tcs_per_port
;
512 params
.pf_rl_en
= qm_info
->pf_rl_en
;
513 params
.pf_wfq_en
= qm_info
->pf_wfq_en
;
514 params
.vport_rl_en
= qm_info
->vport_rl_en
;
515 params
.vport_wfq_en
= qm_info
->vport_wfq_en
;
516 params
.port_params
= qm_info
->qm_port_params
;
518 qed_qm_common_rt_init(p_hwfn
, ¶ms
);
520 qed_cxt_hw_init_common(p_hwfn
);
522 /* Close gate from NIG to BRB/Storm; By default they are open, but
523 * we close them to prevent NIG from passing data to reset blocks.
524 * Should have been done in the ENGINE phase, but init-tool lacks
525 * proper port-pretend capabilities.
527 qed_wr(p_hwfn
, p_ptt
, NIG_REG_RX_BRB_OUT_EN
, 0);
528 qed_wr(p_hwfn
, p_ptt
, NIG_REG_STORM_OUT_EN
, 0);
529 qed_port_pretend(p_hwfn
, p_ptt
, p_hwfn
->port_id
^ 1);
530 qed_wr(p_hwfn
, p_ptt
, NIG_REG_RX_BRB_OUT_EN
, 0);
531 qed_wr(p_hwfn
, p_ptt
, NIG_REG_STORM_OUT_EN
, 0);
532 qed_port_unpretend(p_hwfn
, p_ptt
);
534 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_ENGINE
, ANY_PHASE_ID
, hw_mode
);
538 qed_wr(p_hwfn
, p_ptt
, PSWRQ2_REG_L2P_VALIDATE_VFID
, 0);
539 qed_wr(p_hwfn
, p_ptt
, PGLUE_B_REG_USE_CLIENTID_IN_TAG
, 1);
541 /* Disable relaxed ordering in the PCI config space */
542 qed_wr(p_hwfn
, p_ptt
, 0x20b4,
543 qed_rd(p_hwfn
, p_ptt
, 0x20b4) & ~0x10);
548 static int qed_hw_init_port(struct qed_hwfn
*p_hwfn
,
549 struct qed_ptt
*p_ptt
,
554 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_PORT
, p_hwfn
->port_id
,
559 static int qed_hw_init_pf(struct qed_hwfn
*p_hwfn
,
560 struct qed_ptt
*p_ptt
,
563 enum qed_int_mode int_mode
,
564 bool allow_npar_tx_switch
)
566 u8 rel_pf_id
= p_hwfn
->rel_pf_id
;
569 if (p_hwfn
->mcp_info
) {
570 struct qed_mcp_function_info
*p_info
;
572 p_info
= &p_hwfn
->mcp_info
->func_info
;
573 if (p_info
->bandwidth_min
)
574 p_hwfn
->qm_info
.pf_wfq
= p_info
->bandwidth_min
;
576 /* Update rate limit once we'll actually have a link */
577 p_hwfn
->qm_info
.pf_rl
= 100;
580 qed_cxt_hw_init_pf(p_hwfn
);
582 qed_int_igu_init_rt(p_hwfn
);
584 /* Set VLAN in NIG if needed */
585 if (hw_mode
& (1 << MODE_MF_SD
)) {
586 DP_VERBOSE(p_hwfn
, NETIF_MSG_HW
, "Configuring LLH_FUNC_TAG\n");
587 STORE_RT_REG(p_hwfn
, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET
, 1);
588 STORE_RT_REG(p_hwfn
, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET
,
589 p_hwfn
->hw_info
.ovlan
);
592 /* Enable classification by MAC if needed */
593 if (hw_mode
& (1 << MODE_MF_SI
)) {
594 DP_VERBOSE(p_hwfn
, NETIF_MSG_HW
,
595 "Configuring TAGMAC_CLS_TYPE\n");
597 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET
, 1);
600 /* Protocl Configuration */
601 STORE_RT_REG(p_hwfn
, PRS_REG_SEARCH_TCP_RT_OFFSET
, 0);
602 STORE_RT_REG(p_hwfn
, PRS_REG_SEARCH_FCOE_RT_OFFSET
, 0);
603 STORE_RT_REG(p_hwfn
, PRS_REG_SEARCH_ROCE_RT_OFFSET
, 0);
605 /* Cleanup chip from previous driver if such remains exist */
606 rc
= qed_final_cleanup(p_hwfn
, p_ptt
, rel_pf_id
);
610 /* PF Init sequence */
611 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_PF
, rel_pf_id
, hw_mode
);
615 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
616 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_QM_PF
, rel_pf_id
, hw_mode
);
620 /* Pure runtime initializations - directly to the HW */
621 qed_int_igu_init_pure_rt(p_hwfn
, p_ptt
, true, true);
624 /* enable interrupts */
625 qed_int_igu_enable(p_hwfn
, p_ptt
, int_mode
);
627 /* send function start command */
628 rc
= qed_sp_pf_start(p_hwfn
, p_hwfn
->cdev
->mf_mode
);
630 DP_NOTICE(p_hwfn
, "Function start ramrod failed\n");
635 static int qed_change_pci_hwfn(struct qed_hwfn
*p_hwfn
,
636 struct qed_ptt
*p_ptt
,
639 u32 delay_idx
= 0, val
, set_val
= enable
? 1 : 0;
641 /* Change PF in PXP */
642 qed_wr(p_hwfn
, p_ptt
,
643 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, set_val
);
645 /* wait until value is set - try for 1 second every 50us */
646 for (delay_idx
= 0; delay_idx
< 20000; delay_idx
++) {
647 val
= qed_rd(p_hwfn
, p_ptt
,
648 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
652 usleep_range(50, 60);
655 if (val
!= set_val
) {
657 "PFID_ENABLE_MASTER wasn't changed after a second\n");
664 static void qed_reset_mb_shadow(struct qed_hwfn
*p_hwfn
,
665 struct qed_ptt
*p_main_ptt
)
667 /* Read shadow of current MFW mailbox */
668 qed_mcp_read_mb(p_hwfn
, p_main_ptt
);
669 memcpy(p_hwfn
->mcp_info
->mfw_mb_shadow
,
670 p_hwfn
->mcp_info
->mfw_mb_cur
,
671 p_hwfn
->mcp_info
->mfw_mb_length
);
674 int qed_hw_init(struct qed_dev
*cdev
,
676 enum qed_int_mode int_mode
,
677 bool allow_npar_tx_switch
,
678 const u8
*bin_fw_data
)
680 struct qed_storm_stats
*p_stat
;
681 u32 load_code
, param
, *p_address
;
685 rc
= qed_init_fw_data(cdev
, bin_fw_data
);
689 for_each_hwfn(cdev
, i
) {
690 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
692 rc
= qed_fw_vport(p_hwfn
, 0, &fw_vport
);
696 /* Enable DMAE in PXP */
697 rc
= qed_change_pci_hwfn(p_hwfn
, p_hwfn
->p_main_ptt
, true);
699 qed_calc_hw_mode(p_hwfn
);
701 rc
= qed_mcp_load_req(p_hwfn
, p_hwfn
->p_main_ptt
,
704 DP_NOTICE(p_hwfn
, "Failed sending LOAD_REQ command\n");
708 qed_reset_mb_shadow(p_hwfn
, p_hwfn
->p_main_ptt
);
710 DP_VERBOSE(p_hwfn
, QED_MSG_SP
,
711 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
714 p_hwfn
->first_on_engine
= (load_code
==
715 FW_MSG_CODE_DRV_LOAD_ENGINE
);
718 case FW_MSG_CODE_DRV_LOAD_ENGINE
:
719 rc
= qed_hw_init_common(p_hwfn
, p_hwfn
->p_main_ptt
,
720 p_hwfn
->hw_info
.hw_mode
);
724 case FW_MSG_CODE_DRV_LOAD_PORT
:
725 rc
= qed_hw_init_port(p_hwfn
, p_hwfn
->p_main_ptt
,
726 p_hwfn
->hw_info
.hw_mode
);
731 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
732 rc
= qed_hw_init_pf(p_hwfn
, p_hwfn
->p_main_ptt
,
733 p_hwfn
->hw_info
.hw_mode
,
734 b_hw_start
, int_mode
,
735 allow_npar_tx_switch
);
744 "init phase failed for loadcode 0x%x (rc %d)\n",
747 /* ACK mfw regardless of success or failure of initialization */
748 mfw_rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
749 DRV_MSG_CODE_LOAD_DONE
,
750 0, &load_code
, ¶m
);
754 DP_NOTICE(p_hwfn
, "Failed sending LOAD_DONE command\n");
758 p_hwfn
->hw_init_done
= true;
761 p_stat
= &p_hwfn
->storm_stats
;
762 p_stat
->mstats
.address
= BAR0_MAP_REG_MSDM_RAM
+
763 MSTORM_QUEUE_STAT_OFFSET(fw_vport
);
764 p_stat
->mstats
.len
= sizeof(struct eth_mstorm_per_queue_stat
);
766 p_stat
->ustats
.address
= BAR0_MAP_REG_USDM_RAM
+
767 USTORM_QUEUE_STAT_OFFSET(fw_vport
);
768 p_stat
->ustats
.len
= sizeof(struct eth_ustorm_per_queue_stat
);
770 p_stat
->pstats
.address
= BAR0_MAP_REG_PSDM_RAM
+
771 PSTORM_QUEUE_STAT_OFFSET(fw_vport
);
772 p_stat
->pstats
.len
= sizeof(struct eth_pstorm_per_queue_stat
);
774 p_address
= &p_stat
->tstats
.address
;
775 *p_address
= BAR0_MAP_REG_TSDM_RAM
+
776 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn
));
777 p_stat
->tstats
.len
= sizeof(struct tstorm_per_port_stat
);
783 #define QED_HW_STOP_RETRY_LIMIT (10)
784 int qed_hw_stop(struct qed_dev
*cdev
)
789 for_each_hwfn(cdev
, j
) {
790 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[j
];
791 struct qed_ptt
*p_ptt
= p_hwfn
->p_main_ptt
;
793 DP_VERBOSE(p_hwfn
, NETIF_MSG_IFDOWN
, "Stopping hw/fw\n");
795 /* mark the hw as uninitialized... */
796 p_hwfn
->hw_init_done
= false;
798 rc
= qed_sp_pf_stop(p_hwfn
);
802 qed_wr(p_hwfn
, p_ptt
,
803 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF
, 0x1);
805 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_TCP
, 0x0);
806 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_UDP
, 0x0);
807 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_FCOE
, 0x0);
808 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_ROCE
, 0x0);
809 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_OPENFLOW
, 0x0);
811 qed_wr(p_hwfn
, p_ptt
, TM_REG_PF_ENABLE_CONN
, 0x0);
812 qed_wr(p_hwfn
, p_ptt
, TM_REG_PF_ENABLE_TASK
, 0x0);
813 for (i
= 0; i
< QED_HW_STOP_RETRY_LIMIT
; i
++) {
814 if ((!qed_rd(p_hwfn
, p_ptt
,
815 TM_REG_PF_SCAN_ACTIVE_CONN
)) &&
816 (!qed_rd(p_hwfn
, p_ptt
,
817 TM_REG_PF_SCAN_ACTIVE_TASK
)))
820 usleep_range(1000, 2000);
822 if (i
== QED_HW_STOP_RETRY_LIMIT
)
824 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
825 (u8
)qed_rd(p_hwfn
, p_ptt
,
826 TM_REG_PF_SCAN_ACTIVE_CONN
),
827 (u8
)qed_rd(p_hwfn
, p_ptt
,
828 TM_REG_PF_SCAN_ACTIVE_TASK
));
830 /* Disable Attention Generation */
831 qed_int_igu_disable_int(p_hwfn
, p_ptt
);
833 qed_wr(p_hwfn
, p_ptt
, IGU_REG_LEADING_EDGE_LATCH
, 0);
834 qed_wr(p_hwfn
, p_ptt
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
836 qed_int_igu_init_pure_rt(p_hwfn
, p_ptt
, false, true);
838 /* Need to wait 1ms to guarantee SBs are cleared */
839 usleep_range(1000, 2000);
842 /* Disable DMAE in PXP - in CMT, this should only be done for
843 * first hw-function, and only after all transactions have
844 * stopped for all active hw-functions.
846 t_rc
= qed_change_pci_hwfn(&cdev
->hwfns
[0],
847 cdev
->hwfns
[0].p_main_ptt
,
855 void qed_hw_stop_fastpath(struct qed_dev
*cdev
)
859 for_each_hwfn(cdev
, j
) {
860 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[j
];
861 struct qed_ptt
*p_ptt
= p_hwfn
->p_main_ptt
;
865 "Shutting down the fastpath\n");
867 qed_wr(p_hwfn
, p_ptt
,
868 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF
, 0x1);
870 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_TCP
, 0x0);
871 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_UDP
, 0x0);
872 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_FCOE
, 0x0);
873 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_ROCE
, 0x0);
874 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_OPENFLOW
, 0x0);
876 qed_wr(p_hwfn
, p_ptt
, TM_REG_PF_ENABLE_CONN
, 0x0);
877 qed_wr(p_hwfn
, p_ptt
, TM_REG_PF_ENABLE_TASK
, 0x0);
878 for (i
= 0; i
< QED_HW_STOP_RETRY_LIMIT
; i
++) {
879 if ((!qed_rd(p_hwfn
, p_ptt
,
880 TM_REG_PF_SCAN_ACTIVE_CONN
)) &&
881 (!qed_rd(p_hwfn
, p_ptt
,
882 TM_REG_PF_SCAN_ACTIVE_TASK
)))
885 usleep_range(1000, 2000);
887 if (i
== QED_HW_STOP_RETRY_LIMIT
)
889 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
890 (u8
)qed_rd(p_hwfn
, p_ptt
,
891 TM_REG_PF_SCAN_ACTIVE_CONN
),
892 (u8
)qed_rd(p_hwfn
, p_ptt
,
893 TM_REG_PF_SCAN_ACTIVE_TASK
));
895 qed_int_igu_init_pure_rt(p_hwfn
, p_ptt
, false, false);
897 /* Need to wait 1ms to guarantee SBs are cleared */
898 usleep_range(1000, 2000);
902 void qed_hw_start_fastpath(struct qed_hwfn
*p_hwfn
)
904 /* Re-open incoming traffic */
905 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
906 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF
, 0x0);
909 static int qed_reg_assert(struct qed_hwfn
*hwfn
,
910 struct qed_ptt
*ptt
, u32 reg
,
913 u32 assert_val
= qed_rd(hwfn
, ptt
, reg
);
915 if (assert_val
!= expected
) {
916 DP_NOTICE(hwfn
, "Value at address 0x%x != 0x%08x\n",
924 int qed_hw_reset(struct qed_dev
*cdev
)
927 u32 unload_resp
, unload_param
;
930 for_each_hwfn(cdev
, i
) {
931 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
933 DP_VERBOSE(p_hwfn
, NETIF_MSG_IFDOWN
, "Resetting hw/fw\n");
935 /* Check for incorrect states */
936 qed_reg_assert(p_hwfn
, p_hwfn
->p_main_ptt
,
937 QM_REG_USG_CNT_PF_TX
, 0);
938 qed_reg_assert(p_hwfn
, p_hwfn
->p_main_ptt
,
939 QM_REG_USG_CNT_PF_OTHER
, 0);
941 /* Disable PF in HW blocks */
942 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, DORQ_REG_PF_DB_ENABLE
, 0);
943 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, QM_REG_PF_EN
, 0);
944 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
945 TCFC_REG_STRONG_ENABLE_PF
, 0);
946 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
947 CCFC_REG_STRONG_ENABLE_PF
, 0);
949 /* Send unload command to MCP */
950 rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
951 DRV_MSG_CODE_UNLOAD_REQ
,
952 DRV_MB_PARAM_UNLOAD_WOL_MCP
,
953 &unload_resp
, &unload_param
);
955 DP_NOTICE(p_hwfn
, "qed_hw_reset: UNLOAD_REQ failed\n");
956 unload_resp
= FW_MSG_CODE_DRV_UNLOAD_ENGINE
;
959 rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
960 DRV_MSG_CODE_UNLOAD_DONE
,
961 0, &unload_resp
, &unload_param
);
963 DP_NOTICE(p_hwfn
, "qed_hw_reset: UNLOAD_DONE failed\n");
971 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
972 static void qed_hw_hwfn_free(struct qed_hwfn
*p_hwfn
)
974 qed_ptt_pool_free(p_hwfn
);
975 kfree(p_hwfn
->hw_info
.p_igu_info
);
978 /* Setup bar access */
979 static int qed_hw_hwfn_prepare(struct qed_hwfn
*p_hwfn
)
983 /* Allocate PTT pool */
984 rc
= qed_ptt_pool_alloc(p_hwfn
);
988 /* Allocate the main PTT */
989 p_hwfn
->p_main_ptt
= qed_get_reserved_ptt(p_hwfn
, RESERVED_PTT_MAIN
);
991 /* clear indirect access */
992 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_88_F0
, 0);
993 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_8C_F0
, 0);
994 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_90_F0
, 0);
995 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_94_F0
, 0);
997 /* Clean Previous errors if such exist */
998 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
999 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR
,
1000 1 << p_hwfn
->abs_pf_id
);
1002 /* enable internal target-read */
1003 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1004 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1009 static void get_function_id(struct qed_hwfn
*p_hwfn
)
1012 p_hwfn
->hw_info
.opaque_fid
= (u16
)REG_RD(p_hwfn
, PXP_PF_ME_OPAQUE_ADDR
);
1014 p_hwfn
->hw_info
.concrete_fid
= REG_RD(p_hwfn
, PXP_PF_ME_CONCRETE_ADDR
);
1016 p_hwfn
->abs_pf_id
= (p_hwfn
->hw_info
.concrete_fid
>> 16) & 0xf;
1017 p_hwfn
->rel_pf_id
= GET_FIELD(p_hwfn
->hw_info
.concrete_fid
,
1018 PXP_CONCRETE_FID_PFID
);
1019 p_hwfn
->port_id
= GET_FIELD(p_hwfn
->hw_info
.concrete_fid
,
1020 PXP_CONCRETE_FID_PORT
);
1023 static void qed_hw_set_feat(struct qed_hwfn
*p_hwfn
)
1025 u32
*feat_num
= p_hwfn
->hw_info
.feat_num
;
1026 int num_features
= 1;
1028 feat_num
[QED_PF_L2_QUE
] = min_t(u32
, RESC_NUM(p_hwfn
, QED_SB
) /
1030 RESC_NUM(p_hwfn
, QED_L2_QUEUE
));
1031 DP_VERBOSE(p_hwfn
, NETIF_MSG_PROBE
,
1032 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1033 feat_num
[QED_PF_L2_QUE
], RESC_NUM(p_hwfn
, QED_SB
),
1037 static void qed_hw_get_resc(struct qed_hwfn
*p_hwfn
)
1039 u32
*resc_start
= p_hwfn
->hw_info
.resc_start
;
1040 u32
*resc_num
= p_hwfn
->hw_info
.resc_num
;
1041 struct qed_sb_cnt_info sb_cnt_info
;
1044 num_funcs
= MAX_NUM_PFS_BB
;
1046 memset(&sb_cnt_info
, 0, sizeof(sb_cnt_info
));
1047 qed_int_get_num_sbs(p_hwfn
, &sb_cnt_info
);
1049 resc_num
[QED_SB
] = min_t(u32
,
1050 (MAX_SB_PER_PATH_BB
/ num_funcs
),
1051 sb_cnt_info
.sb_cnt
);
1052 resc_num
[QED_L2_QUEUE
] = MAX_NUM_L2_QUEUES_BB
/ num_funcs
;
1053 resc_num
[QED_VPORT
] = MAX_NUM_VPORTS_BB
/ num_funcs
;
1054 resc_num
[QED_RSS_ENG
] = ETH_RSS_ENGINE_NUM_BB
/ num_funcs
;
1055 resc_num
[QED_PQ
] = MAX_QM_TX_QUEUES_BB
/ num_funcs
;
1056 resc_num
[QED_RL
] = 8;
1057 resc_num
[QED_MAC
] = ETH_NUM_MAC_FILTERS
/ num_funcs
;
1058 resc_num
[QED_VLAN
] = (ETH_NUM_VLAN_FILTERS
- 1 /*For vlan0*/) /
1060 resc_num
[QED_ILT
] = 950;
1062 for (i
= 0; i
< QED_MAX_RESC
; i
++)
1063 resc_start
[i
] = resc_num
[i
] * p_hwfn
->rel_pf_id
;
1065 qed_hw_set_feat(p_hwfn
);
1067 DP_VERBOSE(p_hwfn
, NETIF_MSG_PROBE
,
1068 "The numbers for each resource are:\n"
1069 "SB = %d start = %d\n"
1070 "L2_QUEUE = %d start = %d\n"
1071 "VPORT = %d start = %d\n"
1072 "PQ = %d start = %d\n"
1073 "RL = %d start = %d\n"
1074 "MAC = %d start = %d\n"
1075 "VLAN = %d start = %d\n"
1076 "ILT = %d start = %d\n",
1077 p_hwfn
->hw_info
.resc_num
[QED_SB
],
1078 p_hwfn
->hw_info
.resc_start
[QED_SB
],
1079 p_hwfn
->hw_info
.resc_num
[QED_L2_QUEUE
],
1080 p_hwfn
->hw_info
.resc_start
[QED_L2_QUEUE
],
1081 p_hwfn
->hw_info
.resc_num
[QED_VPORT
],
1082 p_hwfn
->hw_info
.resc_start
[QED_VPORT
],
1083 p_hwfn
->hw_info
.resc_num
[QED_PQ
],
1084 p_hwfn
->hw_info
.resc_start
[QED_PQ
],
1085 p_hwfn
->hw_info
.resc_num
[QED_RL
],
1086 p_hwfn
->hw_info
.resc_start
[QED_RL
],
1087 p_hwfn
->hw_info
.resc_num
[QED_MAC
],
1088 p_hwfn
->hw_info
.resc_start
[QED_MAC
],
1089 p_hwfn
->hw_info
.resc_num
[QED_VLAN
],
1090 p_hwfn
->hw_info
.resc_start
[QED_VLAN
],
1091 p_hwfn
->hw_info
.resc_num
[QED_ILT
],
1092 p_hwfn
->hw_info
.resc_start
[QED_ILT
]);
1095 static int qed_hw_get_nvm_info(struct qed_hwfn
*p_hwfn
,
1096 struct qed_ptt
*p_ptt
)
1098 u32 nvm_cfg1_offset
, mf_mode
, addr
, generic_cont0
, core_cfg
;
1099 u32 port_cfg_addr
, link_temp
, nvm_cfg_addr
, device_capabilities
;
1100 struct qed_mcp_link_params
*link
;
1102 /* Read global nvm_cfg address */
1103 nvm_cfg_addr
= qed_rd(p_hwfn
, p_ptt
, MISC_REG_GEN_PURP_CR0
);
1105 /* Verify MCP has initialized it */
1106 if (!nvm_cfg_addr
) {
1107 DP_NOTICE(p_hwfn
, "Shared memory not initialized\n");
1111 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1112 nvm_cfg1_offset
= qed_rd(p_hwfn
, p_ptt
, nvm_cfg_addr
+ 4);
1114 /* Read Vendor Id / Device Id */
1115 addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1116 offsetof(struct nvm_cfg1
, glob
) +
1117 offsetof(struct nvm_cfg1_glob
, pci_id
);
1118 p_hwfn
->hw_info
.vendor_id
= qed_rd(p_hwfn
, p_ptt
, addr
) &
1119 NVM_CFG1_GLOB_VENDOR_ID_MASK
;
1121 addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1122 offsetof(struct nvm_cfg1
, glob
) +
1123 offsetof(struct nvm_cfg1_glob
, core_cfg
);
1125 core_cfg
= qed_rd(p_hwfn
, p_ptt
, addr
);
1127 switch ((core_cfg
& NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK
) >>
1128 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET
) {
1129 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G
:
1130 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_2X40G
;
1132 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G
:
1133 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_2X50G
;
1135 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G
:
1136 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_1X100G
;
1138 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F
:
1139 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_4X10G_F
;
1141 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E
:
1142 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_4X10G_E
;
1144 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G
:
1145 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_4X20G
;
1147 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G
:
1148 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_1X40G
;
1150 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G
:
1151 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_2X25G
;
1153 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G
:
1154 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_1X25G
;
1157 DP_NOTICE(p_hwfn
, "Unknown port mode in 0x%08x\n",
1162 /* Read default link configuration */
1163 link
= &p_hwfn
->mcp_info
->link_input
;
1164 port_cfg_addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1165 offsetof(struct nvm_cfg1
, port
[MFW_PORT(p_hwfn
)]);
1166 link_temp
= qed_rd(p_hwfn
, p_ptt
,
1168 offsetof(struct nvm_cfg1_port
, speed_cap_mask
));
1169 link
->speed
.advertised_speeds
=
1170 link_temp
& NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK
;
1172 p_hwfn
->mcp_info
->link_capabilities
.speed_capabilities
=
1173 link
->speed
.advertised_speeds
;
1175 link_temp
= qed_rd(p_hwfn
, p_ptt
,
1177 offsetof(struct nvm_cfg1_port
, link_settings
));
1178 switch ((link_temp
& NVM_CFG1_PORT_DRV_LINK_SPEED_MASK
) >>
1179 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET
) {
1180 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG
:
1181 link
->speed
.autoneg
= true;
1183 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G
:
1184 link
->speed
.forced_speed
= 1000;
1186 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G
:
1187 link
->speed
.forced_speed
= 10000;
1189 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G
:
1190 link
->speed
.forced_speed
= 25000;
1192 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G
:
1193 link
->speed
.forced_speed
= 40000;
1195 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G
:
1196 link
->speed
.forced_speed
= 50000;
1198 case NVM_CFG1_PORT_DRV_LINK_SPEED_100G
:
1199 link
->speed
.forced_speed
= 100000;
1202 DP_NOTICE(p_hwfn
, "Unknown Speed in 0x%08x\n",
1206 link_temp
&= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK
;
1207 link_temp
>>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET
;
1208 link
->pause
.autoneg
= !!(link_temp
&
1209 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG
);
1210 link
->pause
.forced_rx
= !!(link_temp
&
1211 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX
);
1212 link
->pause
.forced_tx
= !!(link_temp
&
1213 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX
);
1214 link
->loopback_mode
= 0;
1216 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
1217 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1218 link
->speed
.forced_speed
, link
->speed
.advertised_speeds
,
1219 link
->speed
.autoneg
, link
->pause
.autoneg
);
1221 /* Read Multi-function information from shmem */
1222 addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1223 offsetof(struct nvm_cfg1
, glob
) +
1224 offsetof(struct nvm_cfg1_glob
, generic_cont0
);
1226 generic_cont0
= qed_rd(p_hwfn
, p_ptt
, addr
);
1228 mf_mode
= (generic_cont0
& NVM_CFG1_GLOB_MF_MODE_MASK
) >>
1229 NVM_CFG1_GLOB_MF_MODE_OFFSET
;
1232 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED
:
1233 p_hwfn
->cdev
->mf_mode
= QED_MF_OVLAN
;
1235 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0
:
1236 p_hwfn
->cdev
->mf_mode
= QED_MF_NPAR
;
1238 case NVM_CFG1_GLOB_MF_MODE_DEFAULT
:
1239 p_hwfn
->cdev
->mf_mode
= QED_MF_DEFAULT
;
1242 DP_INFO(p_hwfn
, "Multi function mode is %08x\n",
1243 p_hwfn
->cdev
->mf_mode
);
1245 /* Read Multi-function information from shmem */
1246 addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1247 offsetof(struct nvm_cfg1
, glob
) +
1248 offsetof(struct nvm_cfg1_glob
, device_capabilities
);
1250 device_capabilities
= qed_rd(p_hwfn
, p_ptt
, addr
);
1251 if (device_capabilities
& NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET
)
1252 __set_bit(QED_DEV_CAP_ETH
,
1253 &p_hwfn
->hw_info
.device_capabilities
);
1255 return qed_mcp_fill_shmem_func_info(p_hwfn
, p_ptt
);
1259 qed_get_hw_info(struct qed_hwfn
*p_hwfn
,
1260 struct qed_ptt
*p_ptt
,
1261 enum qed_pci_personality personality
)
1266 /* Read the port mode */
1267 port_mode
= qed_rd(p_hwfn
, p_ptt
,
1268 CNIG_REG_NW_PORT_MODE_BB_B0
);
1270 if (port_mode
< 3) {
1271 p_hwfn
->cdev
->num_ports_in_engines
= 1;
1272 } else if (port_mode
<= 5) {
1273 p_hwfn
->cdev
->num_ports_in_engines
= 2;
1275 DP_NOTICE(p_hwfn
, "PORT MODE: %d not supported\n",
1276 p_hwfn
->cdev
->num_ports_in_engines
);
1278 /* Default num_ports_in_engines to something */
1279 p_hwfn
->cdev
->num_ports_in_engines
= 1;
1282 qed_hw_get_nvm_info(p_hwfn
, p_ptt
);
1284 rc
= qed_int_igu_read_cam(p_hwfn
, p_ptt
);
1288 if (qed_mcp_is_init(p_hwfn
))
1289 ether_addr_copy(p_hwfn
->hw_info
.hw_mac_addr
,
1290 p_hwfn
->mcp_info
->func_info
.mac
);
1292 eth_random_addr(p_hwfn
->hw_info
.hw_mac_addr
);
1294 if (qed_mcp_is_init(p_hwfn
)) {
1295 if (p_hwfn
->mcp_info
->func_info
.ovlan
!= QED_MCP_VLAN_UNSET
)
1296 p_hwfn
->hw_info
.ovlan
=
1297 p_hwfn
->mcp_info
->func_info
.ovlan
;
1299 qed_mcp_cmd_port_init(p_hwfn
, p_ptt
);
1302 if (qed_mcp_is_init(p_hwfn
)) {
1303 enum qed_pci_personality protocol
;
1305 protocol
= p_hwfn
->mcp_info
->func_info
.protocol
;
1306 p_hwfn
->hw_info
.personality
= protocol
;
1309 qed_hw_get_resc(p_hwfn
);
1314 static void qed_get_dev_info(struct qed_dev
*cdev
)
1316 struct qed_hwfn
*p_hwfn
= QED_LEADING_HWFN(cdev
);
1319 /* Read Vendor Id / Device Id */
1320 pci_read_config_word(cdev
->pdev
, PCI_VENDOR_ID
,
1322 pci_read_config_word(cdev
->pdev
, PCI_DEVICE_ID
,
1324 cdev
->chip_num
= (u16
)qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1325 MISCS_REG_CHIP_NUM
);
1326 cdev
->chip_rev
= (u16
)qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1327 MISCS_REG_CHIP_REV
);
1328 MASK_FIELD(CHIP_REV
, cdev
->chip_rev
);
1330 cdev
->type
= QED_DEV_TYPE_BB
;
1331 /* Learn number of HW-functions */
1332 tmp
= qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1333 MISCS_REG_CMT_ENABLED_FOR_PAIR
);
1335 if (tmp
& (1 << p_hwfn
->rel_pf_id
)) {
1336 DP_NOTICE(cdev
->hwfns
, "device in CMT mode\n");
1337 cdev
->num_hwfns
= 2;
1339 cdev
->num_hwfns
= 1;
1342 cdev
->chip_bond_id
= qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1343 MISCS_REG_CHIP_TEST_REG
) >> 4;
1344 MASK_FIELD(CHIP_BOND_ID
, cdev
->chip_bond_id
);
1345 cdev
->chip_metal
= (u16
)qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1346 MISCS_REG_CHIP_METAL
);
1347 MASK_FIELD(CHIP_METAL
, cdev
->chip_metal
);
1349 DP_INFO(cdev
->hwfns
,
1350 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1351 cdev
->chip_num
, cdev
->chip_rev
,
1352 cdev
->chip_bond_id
, cdev
->chip_metal
);
1355 static int qed_hw_prepare_single(struct qed_hwfn
*p_hwfn
,
1356 void __iomem
*p_regview
,
1357 void __iomem
*p_doorbells
,
1358 enum qed_pci_personality personality
)
1362 /* Split PCI bars evenly between hwfns */
1363 p_hwfn
->regview
= p_regview
;
1364 p_hwfn
->doorbells
= p_doorbells
;
1366 /* Validate that chip access is feasible */
1367 if (REG_RD(p_hwfn
, PXP_PF_ME_OPAQUE_ADDR
) == 0xffffffff) {
1369 "Reading the ME register returns all Fs; Preventing further chip access\n");
1373 get_function_id(p_hwfn
);
1375 rc
= qed_hw_hwfn_prepare(p_hwfn
);
1377 DP_NOTICE(p_hwfn
, "Failed to prepare hwfn's hw\n");
1381 /* First hwfn learns basic information, e.g., number of hwfns */
1383 qed_get_dev_info(p_hwfn
->cdev
);
1385 /* Initialize MCP structure */
1386 rc
= qed_mcp_cmd_init(p_hwfn
, p_hwfn
->p_main_ptt
);
1388 DP_NOTICE(p_hwfn
, "Failed initializing mcp command\n");
1392 /* Read the device configuration information from the HW and SHMEM */
1393 rc
= qed_get_hw_info(p_hwfn
, p_hwfn
->p_main_ptt
, personality
);
1395 DP_NOTICE(p_hwfn
, "Failed to get HW information\n");
1399 /* Allocate the init RT array and initialize the init-ops engine */
1400 rc
= qed_init_alloc(p_hwfn
);
1402 DP_NOTICE(p_hwfn
, "Failed to allocate the init array\n");
1408 qed_mcp_free(p_hwfn
);
1410 qed_hw_hwfn_free(p_hwfn
);
1415 int qed_hw_prepare(struct qed_dev
*cdev
,
1418 struct qed_hwfn
*p_hwfn
= QED_LEADING_HWFN(cdev
);
1421 /* Store the precompiled init data ptrs */
1422 qed_init_iro_array(cdev
);
1424 /* Initialize the first hwfn - will learn number of hwfns */
1425 rc
= qed_hw_prepare_single(p_hwfn
,
1427 cdev
->doorbells
, personality
);
1431 personality
= p_hwfn
->hw_info
.personality
;
1433 /* Initialize the rest of the hwfns */
1434 if (cdev
->num_hwfns
> 1) {
1435 void __iomem
*p_regview
, *p_doorbell
;
1438 /* adjust bar offset for second engine */
1439 addr
= cdev
->regview
+ qed_hw_bar_size(p_hwfn
, BAR_ID_0
) / 2;
1442 /* adjust doorbell bar offset for second engine */
1443 addr
= cdev
->doorbells
+ qed_hw_bar_size(p_hwfn
, BAR_ID_1
) / 2;
1446 /* prepare second hw function */
1447 rc
= qed_hw_prepare_single(&cdev
->hwfns
[1], p_regview
,
1448 p_doorbell
, personality
);
1450 /* in case of error, need to free the previously
1451 * initiliazed hwfn 0.
1454 qed_init_free(p_hwfn
);
1455 qed_mcp_free(p_hwfn
);
1456 qed_hw_hwfn_free(p_hwfn
);
1463 void qed_hw_remove(struct qed_dev
*cdev
)
1467 for_each_hwfn(cdev
, i
) {
1468 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
1470 qed_init_free(p_hwfn
);
1471 qed_hw_hwfn_free(p_hwfn
);
1472 qed_mcp_free(p_hwfn
);
1476 int qed_chain_alloc(struct qed_dev
*cdev
,
1477 enum qed_chain_use_mode intended_use
,
1478 enum qed_chain_mode mode
,
1481 struct qed_chain
*p_chain
)
1483 dma_addr_t p_pbl_phys
= 0;
1484 void *p_pbl_virt
= NULL
;
1485 dma_addr_t p_phys
= 0;
1486 void *p_virt
= NULL
;
1490 if (mode
== QED_CHAIN_MODE_SINGLE
)
1493 page_cnt
= QED_CHAIN_PAGE_CNT(num_elems
, elem_size
, mode
);
1495 size
= page_cnt
* QED_CHAIN_PAGE_SIZE
;
1496 p_virt
= dma_alloc_coherent(&cdev
->pdev
->dev
,
1497 size
, &p_phys
, GFP_KERNEL
);
1499 DP_NOTICE(cdev
, "Failed to allocate chain mem\n");
1503 if (mode
== QED_CHAIN_MODE_PBL
) {
1504 size
= page_cnt
* QED_CHAIN_PBL_ENTRY_SIZE
;
1505 p_pbl_virt
= dma_alloc_coherent(&cdev
->pdev
->dev
,
1509 DP_NOTICE(cdev
, "Failed to allocate chain pbl mem\n");
1513 qed_chain_pbl_init(p_chain
, p_virt
, p_phys
, page_cnt
,
1514 (u8
)elem_size
, intended_use
,
1515 p_pbl_phys
, p_pbl_virt
);
1517 qed_chain_init(p_chain
, p_virt
, p_phys
, page_cnt
,
1518 (u8
)elem_size
, intended_use
, mode
);
1524 dma_free_coherent(&cdev
->pdev
->dev
,
1525 page_cnt
* QED_CHAIN_PAGE_SIZE
,
1527 dma_free_coherent(&cdev
->pdev
->dev
,
1528 page_cnt
* QED_CHAIN_PBL_ENTRY_SIZE
,
1529 p_pbl_virt
, p_pbl_phys
);
1534 void qed_chain_free(struct qed_dev
*cdev
,
1535 struct qed_chain
*p_chain
)
1539 if (!p_chain
->p_virt_addr
)
1542 if (p_chain
->mode
== QED_CHAIN_MODE_PBL
) {
1543 size
= p_chain
->page_cnt
* QED_CHAIN_PBL_ENTRY_SIZE
;
1544 dma_free_coherent(&cdev
->pdev
->dev
, size
,
1545 p_chain
->pbl
.p_virt_table
,
1546 p_chain
->pbl
.p_phys_table
);
1549 size
= p_chain
->page_cnt
* QED_CHAIN_PAGE_SIZE
;
1550 dma_free_coherent(&cdev
->pdev
->dev
, size
,
1551 p_chain
->p_virt_addr
,
1552 p_chain
->p_phys_addr
);
1555 static void __qed_get_vport_stats(struct qed_dev
*cdev
,
1556 struct qed_eth_stats
*stats
)
1560 memset(stats
, 0, sizeof(*stats
));
1562 for_each_hwfn(cdev
, i
) {
1563 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
1564 struct eth_mstorm_per_queue_stat mstats
;
1565 struct eth_ustorm_per_queue_stat ustats
;
1566 struct eth_pstorm_per_queue_stat pstats
;
1567 struct tstorm_per_port_stat tstats
;
1568 struct port_stats port_stats
;
1569 struct qed_ptt
*p_ptt
= qed_ptt_acquire(p_hwfn
);
1572 DP_ERR(p_hwfn
, "Failed to acquire ptt\n");
1576 memset(&mstats
, 0, sizeof(mstats
));
1577 qed_memcpy_from(p_hwfn
, p_ptt
, &mstats
,
1578 p_hwfn
->storm_stats
.mstats
.address
,
1579 p_hwfn
->storm_stats
.mstats
.len
);
1581 memset(&ustats
, 0, sizeof(ustats
));
1582 qed_memcpy_from(p_hwfn
, p_ptt
, &ustats
,
1583 p_hwfn
->storm_stats
.ustats
.address
,
1584 p_hwfn
->storm_stats
.ustats
.len
);
1586 memset(&pstats
, 0, sizeof(pstats
));
1587 qed_memcpy_from(p_hwfn
, p_ptt
, &pstats
,
1588 p_hwfn
->storm_stats
.pstats
.address
,
1589 p_hwfn
->storm_stats
.pstats
.len
);
1591 memset(&tstats
, 0, sizeof(tstats
));
1592 qed_memcpy_from(p_hwfn
, p_ptt
, &tstats
,
1593 p_hwfn
->storm_stats
.tstats
.address
,
1594 p_hwfn
->storm_stats
.tstats
.len
);
1596 memset(&port_stats
, 0, sizeof(port_stats
));
1598 if (p_hwfn
->mcp_info
)
1599 qed_memcpy_from(p_hwfn
, p_ptt
, &port_stats
,
1600 p_hwfn
->mcp_info
->port_addr
+
1601 offsetof(struct public_port
, stats
),
1602 sizeof(port_stats
));
1603 qed_ptt_release(p_hwfn
, p_ptt
);
1605 stats
->no_buff_discards
+=
1606 HILO_64_REGPAIR(mstats
.no_buff_discard
);
1607 stats
->packet_too_big_discard
+=
1608 HILO_64_REGPAIR(mstats
.packet_too_big_discard
);
1609 stats
->ttl0_discard
+=
1610 HILO_64_REGPAIR(mstats
.ttl0_discard
);
1611 stats
->tpa_coalesced_pkts
+=
1612 HILO_64_REGPAIR(mstats
.tpa_coalesced_pkts
);
1613 stats
->tpa_coalesced_events
+=
1614 HILO_64_REGPAIR(mstats
.tpa_coalesced_events
);
1615 stats
->tpa_aborts_num
+=
1616 HILO_64_REGPAIR(mstats
.tpa_aborts_num
);
1617 stats
->tpa_coalesced_bytes
+=
1618 HILO_64_REGPAIR(mstats
.tpa_coalesced_bytes
);
1620 stats
->rx_ucast_bytes
+=
1621 HILO_64_REGPAIR(ustats
.rcv_ucast_bytes
);
1622 stats
->rx_mcast_bytes
+=
1623 HILO_64_REGPAIR(ustats
.rcv_mcast_bytes
);
1624 stats
->rx_bcast_bytes
+=
1625 HILO_64_REGPAIR(ustats
.rcv_bcast_bytes
);
1626 stats
->rx_ucast_pkts
+=
1627 HILO_64_REGPAIR(ustats
.rcv_ucast_pkts
);
1628 stats
->rx_mcast_pkts
+=
1629 HILO_64_REGPAIR(ustats
.rcv_mcast_pkts
);
1630 stats
->rx_bcast_pkts
+=
1631 HILO_64_REGPAIR(ustats
.rcv_bcast_pkts
);
1633 stats
->mftag_filter_discards
+=
1634 HILO_64_REGPAIR(tstats
.mftag_filter_discard
);
1635 stats
->mac_filter_discards
+=
1636 HILO_64_REGPAIR(tstats
.eth_mac_filter_discard
);
1638 stats
->tx_ucast_bytes
+=
1639 HILO_64_REGPAIR(pstats
.sent_ucast_bytes
);
1640 stats
->tx_mcast_bytes
+=
1641 HILO_64_REGPAIR(pstats
.sent_mcast_bytes
);
1642 stats
->tx_bcast_bytes
+=
1643 HILO_64_REGPAIR(pstats
.sent_bcast_bytes
);
1644 stats
->tx_ucast_pkts
+=
1645 HILO_64_REGPAIR(pstats
.sent_ucast_pkts
);
1646 stats
->tx_mcast_pkts
+=
1647 HILO_64_REGPAIR(pstats
.sent_mcast_pkts
);
1648 stats
->tx_bcast_pkts
+=
1649 HILO_64_REGPAIR(pstats
.sent_bcast_pkts
);
1650 stats
->tx_err_drop_pkts
+=
1651 HILO_64_REGPAIR(pstats
.error_drop_pkts
);
1652 stats
->rx_64_byte_packets
+= port_stats
.pmm
.r64
;
1653 stats
->rx_127_byte_packets
+= port_stats
.pmm
.r127
;
1654 stats
->rx_255_byte_packets
+= port_stats
.pmm
.r255
;
1655 stats
->rx_511_byte_packets
+= port_stats
.pmm
.r511
;
1656 stats
->rx_1023_byte_packets
+= port_stats
.pmm
.r1023
;
1657 stats
->rx_1518_byte_packets
+= port_stats
.pmm
.r1518
;
1658 stats
->rx_1522_byte_packets
+= port_stats
.pmm
.r1522
;
1659 stats
->rx_2047_byte_packets
+= port_stats
.pmm
.r2047
;
1660 stats
->rx_4095_byte_packets
+= port_stats
.pmm
.r4095
;
1661 stats
->rx_9216_byte_packets
+= port_stats
.pmm
.r9216
;
1662 stats
->rx_16383_byte_packets
+= port_stats
.pmm
.r16383
;
1663 stats
->rx_crc_errors
+= port_stats
.pmm
.rfcs
;
1664 stats
->rx_mac_crtl_frames
+= port_stats
.pmm
.rxcf
;
1665 stats
->rx_pause_frames
+= port_stats
.pmm
.rxpf
;
1666 stats
->rx_pfc_frames
+= port_stats
.pmm
.rxpp
;
1667 stats
->rx_align_errors
+= port_stats
.pmm
.raln
;
1668 stats
->rx_carrier_errors
+= port_stats
.pmm
.rfcr
;
1669 stats
->rx_oversize_packets
+= port_stats
.pmm
.rovr
;
1670 stats
->rx_jabbers
+= port_stats
.pmm
.rjbr
;
1671 stats
->rx_undersize_packets
+= port_stats
.pmm
.rund
;
1672 stats
->rx_fragments
+= port_stats
.pmm
.rfrg
;
1673 stats
->tx_64_byte_packets
+= port_stats
.pmm
.t64
;
1674 stats
->tx_65_to_127_byte_packets
+= port_stats
.pmm
.t127
;
1675 stats
->tx_128_to_255_byte_packets
+= port_stats
.pmm
.t255
;
1676 stats
->tx_256_to_511_byte_packets
+= port_stats
.pmm
.t511
;
1677 stats
->tx_512_to_1023_byte_packets
+= port_stats
.pmm
.t1023
;
1678 stats
->tx_1024_to_1518_byte_packets
+= port_stats
.pmm
.t1518
;
1679 stats
->tx_1519_to_2047_byte_packets
+= port_stats
.pmm
.t2047
;
1680 stats
->tx_2048_to_4095_byte_packets
+= port_stats
.pmm
.t4095
;
1681 stats
->tx_4096_to_9216_byte_packets
+= port_stats
.pmm
.t9216
;
1682 stats
->tx_9217_to_16383_byte_packets
+= port_stats
.pmm
.t16383
;
1683 stats
->tx_pause_frames
+= port_stats
.pmm
.txpf
;
1684 stats
->tx_pfc_frames
+= port_stats
.pmm
.txpp
;
1685 stats
->tx_lpi_entry_count
+= port_stats
.pmm
.tlpiec
;
1686 stats
->tx_total_collisions
+= port_stats
.pmm
.tncl
;
1687 stats
->rx_mac_bytes
+= port_stats
.pmm
.rbyte
;
1688 stats
->rx_mac_uc_packets
+= port_stats
.pmm
.rxuca
;
1689 stats
->rx_mac_mc_packets
+= port_stats
.pmm
.rxmca
;
1690 stats
->rx_mac_bc_packets
+= port_stats
.pmm
.rxbca
;
1691 stats
->rx_mac_frames_ok
+= port_stats
.pmm
.rxpok
;
1692 stats
->tx_mac_bytes
+= port_stats
.pmm
.tbyte
;
1693 stats
->tx_mac_uc_packets
+= port_stats
.pmm
.txuca
;
1694 stats
->tx_mac_mc_packets
+= port_stats
.pmm
.txmca
;
1695 stats
->tx_mac_bc_packets
+= port_stats
.pmm
.txbca
;
1696 stats
->tx_mac_ctrl_frames
+= port_stats
.pmm
.txcf
;
1698 for (j
= 0; j
< 8; j
++) {
1699 stats
->brb_truncates
+= port_stats
.brb
.brb_truncate
[j
];
1700 stats
->brb_discards
+= port_stats
.brb
.brb_discard
[j
];
1705 void qed_get_vport_stats(struct qed_dev
*cdev
,
1706 struct qed_eth_stats
*stats
)
1711 memset(stats
, 0, sizeof(*stats
));
1715 __qed_get_vport_stats(cdev
, stats
);
1717 if (!cdev
->reset_stats
)
1720 /* Reduce the statistics baseline */
1721 for (i
= 0; i
< sizeof(struct qed_eth_stats
) / sizeof(u64
); i
++)
1722 ((u64
*)stats
)[i
] -= ((u64
*)cdev
->reset_stats
)[i
];
1725 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1726 void qed_reset_vport_stats(struct qed_dev
*cdev
)
1730 for_each_hwfn(cdev
, i
) {
1731 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
1732 struct eth_mstorm_per_queue_stat mstats
;
1733 struct eth_ustorm_per_queue_stat ustats
;
1734 struct eth_pstorm_per_queue_stat pstats
;
1735 struct qed_ptt
*p_ptt
= qed_ptt_acquire(p_hwfn
);
1738 DP_ERR(p_hwfn
, "Failed to acquire ptt\n");
1742 memset(&mstats
, 0, sizeof(mstats
));
1743 qed_memcpy_to(p_hwfn
, p_ptt
,
1744 p_hwfn
->storm_stats
.mstats
.address
,
1746 p_hwfn
->storm_stats
.mstats
.len
);
1748 memset(&ustats
, 0, sizeof(ustats
));
1749 qed_memcpy_to(p_hwfn
, p_ptt
,
1750 p_hwfn
->storm_stats
.ustats
.address
,
1752 p_hwfn
->storm_stats
.ustats
.len
);
1754 memset(&pstats
, 0, sizeof(pstats
));
1755 qed_memcpy_to(p_hwfn
, p_ptt
,
1756 p_hwfn
->storm_stats
.pstats
.address
,
1758 p_hwfn
->storm_stats
.pstats
.len
);
1760 qed_ptt_release(p_hwfn
, p_ptt
);
1763 /* PORT statistics are not necessarily reset, so we need to
1764 * read and create a baseline for future statistics.
1766 if (!cdev
->reset_stats
)
1767 DP_INFO(cdev
, "Reset stats not allocated\n");
1769 __qed_get_vport_stats(cdev
, cdev
->reset_stats
);
1772 int qed_fw_l2_queue(struct qed_hwfn
*p_hwfn
,
1773 u16 src_id
, u16
*dst_id
)
1775 if (src_id
>= RESC_NUM(p_hwfn
, QED_L2_QUEUE
)) {
1778 min
= (u16
)RESC_START(p_hwfn
, QED_L2_QUEUE
);
1779 max
= min
+ RESC_NUM(p_hwfn
, QED_L2_QUEUE
);
1781 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
1787 *dst_id
= RESC_START(p_hwfn
, QED_L2_QUEUE
) + src_id
;
1792 int qed_fw_vport(struct qed_hwfn
*p_hwfn
,
1793 u8 src_id
, u8
*dst_id
)
1795 if (src_id
>= RESC_NUM(p_hwfn
, QED_VPORT
)) {
1798 min
= (u8
)RESC_START(p_hwfn
, QED_VPORT
);
1799 max
= min
+ RESC_NUM(p_hwfn
, QED_VPORT
);
1801 "vport id [%d] is not valid, available indices [%d - %d]\n",
1807 *dst_id
= RESC_START(p_hwfn
, QED_VPORT
) + src_id
;
1812 int qed_fw_rss_eng(struct qed_hwfn
*p_hwfn
,
1813 u8 src_id
, u8
*dst_id
)
1815 if (src_id
>= RESC_NUM(p_hwfn
, QED_RSS_ENG
)) {
1818 min
= (u8
)RESC_START(p_hwfn
, QED_RSS_ENG
);
1819 max
= min
+ RESC_NUM(p_hwfn
, QED_RSS_ENG
);
1821 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
1827 *dst_id
= RESC_START(p_hwfn
, QED_RSS_ENG
) + src_id
;