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[deliverable/linux.git] / drivers / net / ethernet / qlogic / qed / qed_main.c
1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9 #include <linux/stddef.h>
10 #include <linux/pci.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/version.h>
14 #include <linux/delay.h>
15 #include <asm/byteorder.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/string.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/workqueue.h>
21 #include <linux/ethtool.h>
22 #include <linux/etherdevice.h>
23 #include <linux/vmalloc.h>
24 #include <linux/qed/qed_if.h>
25
26 #include "qed.h"
27 #include "qed_sriov.h"
28 #include "qed_sp.h"
29 #include "qed_dev_api.h"
30 #include "qed_mcp.h"
31 #include "qed_hw.h"
32 #include "qed_selftest.h"
33
34 static char version[] =
35 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
36
37 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
38 MODULE_LICENSE("GPL");
39 MODULE_VERSION(DRV_MODULE_VERSION);
40
41 #define FW_FILE_VERSION \
42 __stringify(FW_MAJOR_VERSION) "." \
43 __stringify(FW_MINOR_VERSION) "." \
44 __stringify(FW_REVISION_VERSION) "." \
45 __stringify(FW_ENGINEERING_VERSION)
46
47 #define QED_FW_FILE_NAME \
48 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
49
50 MODULE_FIRMWARE(QED_FW_FILE_NAME);
51
52 static int __init qed_init(void)
53 {
54 pr_notice("qed_init called\n");
55
56 pr_info("%s", version);
57
58 return 0;
59 }
60
61 static void __exit qed_cleanup(void)
62 {
63 pr_notice("qed_cleanup called\n");
64 }
65
66 module_init(qed_init);
67 module_exit(qed_cleanup);
68
69 /* Check if the DMA controller on the machine can properly handle the DMA
70 * addressing required by the device.
71 */
72 static int qed_set_coherency_mask(struct qed_dev *cdev)
73 {
74 struct device *dev = &cdev->pdev->dev;
75
76 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
77 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
78 DP_NOTICE(cdev,
79 "Can't request 64-bit consistent allocations\n");
80 return -EIO;
81 }
82 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
83 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
84 return -EIO;
85 }
86
87 return 0;
88 }
89
90 static void qed_free_pci(struct qed_dev *cdev)
91 {
92 struct pci_dev *pdev = cdev->pdev;
93
94 if (cdev->doorbells)
95 iounmap(cdev->doorbells);
96 if (cdev->regview)
97 iounmap(cdev->regview);
98 if (atomic_read(&pdev->enable_cnt) == 1)
99 pci_release_regions(pdev);
100
101 pci_disable_device(pdev);
102 }
103
104 #define PCI_REVISION_ID_ERROR_VAL 0xff
105
106 /* Performs PCI initializations as well as initializing PCI-related parameters
107 * in the device structrue. Returns 0 in case of success.
108 */
109 static int qed_init_pci(struct qed_dev *cdev,
110 struct pci_dev *pdev)
111 {
112 u8 rev_id;
113 int rc;
114
115 cdev->pdev = pdev;
116
117 rc = pci_enable_device(pdev);
118 if (rc) {
119 DP_NOTICE(cdev, "Cannot enable PCI device\n");
120 goto err0;
121 }
122
123 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
124 DP_NOTICE(cdev, "No memory region found in bar #0\n");
125 rc = -EIO;
126 goto err1;
127 }
128
129 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
130 DP_NOTICE(cdev, "No memory region found in bar #2\n");
131 rc = -EIO;
132 goto err1;
133 }
134
135 if (atomic_read(&pdev->enable_cnt) == 1) {
136 rc = pci_request_regions(pdev, "qed");
137 if (rc) {
138 DP_NOTICE(cdev,
139 "Failed to request PCI memory resources\n");
140 goto err1;
141 }
142 pci_set_master(pdev);
143 pci_save_state(pdev);
144 }
145
146 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
147 if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
148 DP_NOTICE(cdev,
149 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
150 rev_id);
151 rc = -ENODEV;
152 goto err2;
153 }
154 if (!pci_is_pcie(pdev)) {
155 DP_NOTICE(cdev, "The bus is not PCI Express\n");
156 rc = -EIO;
157 goto err2;
158 }
159
160 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
161 if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
162 DP_NOTICE(cdev, "Cannot find power management capability\n");
163
164 rc = qed_set_coherency_mask(cdev);
165 if (rc)
166 goto err2;
167
168 cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
169 cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
170 cdev->pci_params.irq = pdev->irq;
171
172 cdev->regview = pci_ioremap_bar(pdev, 0);
173 if (!cdev->regview) {
174 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
175 rc = -ENOMEM;
176 goto err2;
177 }
178
179 if (IS_PF(cdev)) {
180 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
181 cdev->db_size = pci_resource_len(cdev->pdev, 2);
182 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
183 if (!cdev->doorbells) {
184 DP_NOTICE(cdev, "Cannot map doorbell space\n");
185 return -ENOMEM;
186 }
187 }
188
189 return 0;
190
191 err2:
192 pci_release_regions(pdev);
193 err1:
194 pci_disable_device(pdev);
195 err0:
196 return rc;
197 }
198
199 int qed_fill_dev_info(struct qed_dev *cdev,
200 struct qed_dev_info *dev_info)
201 {
202 struct qed_ptt *ptt;
203
204 memset(dev_info, 0, sizeof(struct qed_dev_info));
205
206 dev_info->num_hwfns = cdev->num_hwfns;
207 dev_info->pci_mem_start = cdev->pci_params.mem_start;
208 dev_info->pci_mem_end = cdev->pci_params.mem_end;
209 dev_info->pci_irq = cdev->pci_params.irq;
210 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
211 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
212
213 if (IS_PF(cdev)) {
214 dev_info->fw_major = FW_MAJOR_VERSION;
215 dev_info->fw_minor = FW_MINOR_VERSION;
216 dev_info->fw_rev = FW_REVISION_VERSION;
217 dev_info->fw_eng = FW_ENGINEERING_VERSION;
218 dev_info->mf_mode = cdev->mf_mode;
219 dev_info->tx_switching = true;
220 } else {
221 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
222 &dev_info->fw_minor, &dev_info->fw_rev,
223 &dev_info->fw_eng);
224 }
225
226 if (IS_PF(cdev)) {
227 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
228 if (ptt) {
229 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
230 &dev_info->mfw_rev, NULL);
231
232 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
233 &dev_info->flash_size);
234
235 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
236 }
237 } else {
238 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
239 &dev_info->mfw_rev, NULL);
240 }
241
242 return 0;
243 }
244
245 static void qed_free_cdev(struct qed_dev *cdev)
246 {
247 kfree((void *)cdev);
248 }
249
250 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
251 {
252 struct qed_dev *cdev;
253
254 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
255 if (!cdev)
256 return cdev;
257
258 qed_init_struct(cdev);
259
260 return cdev;
261 }
262
263 /* Sets the requested power state */
264 static int qed_set_power_state(struct qed_dev *cdev,
265 pci_power_t state)
266 {
267 if (!cdev)
268 return -ENODEV;
269
270 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
271 return 0;
272 }
273
274 /* probing */
275 static struct qed_dev *qed_probe(struct pci_dev *pdev,
276 struct qed_probe_params *params)
277 {
278 struct qed_dev *cdev;
279 int rc;
280
281 cdev = qed_alloc_cdev(pdev);
282 if (!cdev)
283 goto err0;
284
285 cdev->protocol = params->protocol;
286
287 if (params->is_vf)
288 cdev->b_is_vf = true;
289
290 qed_init_dp(cdev, params->dp_module, params->dp_level);
291
292 rc = qed_init_pci(cdev, pdev);
293 if (rc) {
294 DP_ERR(cdev, "init pci failed\n");
295 goto err1;
296 }
297 DP_INFO(cdev, "PCI init completed successfully\n");
298
299 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
300 if (rc) {
301 DP_ERR(cdev, "hw prepare failed\n");
302 goto err2;
303 }
304
305 DP_INFO(cdev, "qed_probe completed successffuly\n");
306
307 return cdev;
308
309 err2:
310 qed_free_pci(cdev);
311 err1:
312 qed_free_cdev(cdev);
313 err0:
314 return NULL;
315 }
316
317 static void qed_remove(struct qed_dev *cdev)
318 {
319 if (!cdev)
320 return;
321
322 qed_hw_remove(cdev);
323
324 qed_free_pci(cdev);
325
326 qed_set_power_state(cdev, PCI_D3hot);
327
328 qed_free_cdev(cdev);
329 }
330
331 static void qed_disable_msix(struct qed_dev *cdev)
332 {
333 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
334 pci_disable_msix(cdev->pdev);
335 kfree(cdev->int_params.msix_table);
336 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
337 pci_disable_msi(cdev->pdev);
338 }
339
340 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
341 }
342
343 static int qed_enable_msix(struct qed_dev *cdev,
344 struct qed_int_params *int_params)
345 {
346 int i, rc, cnt;
347
348 cnt = int_params->in.num_vectors;
349
350 for (i = 0; i < cnt; i++)
351 int_params->msix_table[i].entry = i;
352
353 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
354 int_params->in.min_msix_cnt, cnt);
355 if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
356 (rc % cdev->num_hwfns)) {
357 pci_disable_msix(cdev->pdev);
358
359 /* If fastpath is initialized, we need at least one interrupt
360 * per hwfn [and the slow path interrupts]. New requested number
361 * should be a multiple of the number of hwfns.
362 */
363 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
364 DP_NOTICE(cdev,
365 "Trying to enable MSI-X with less vectors (%d out of %d)\n",
366 cnt, int_params->in.num_vectors);
367 rc = pci_enable_msix_exact(cdev->pdev,
368 int_params->msix_table, cnt);
369 if (!rc)
370 rc = cnt;
371 }
372
373 if (rc > 0) {
374 /* MSI-x configuration was achieved */
375 int_params->out.int_mode = QED_INT_MODE_MSIX;
376 int_params->out.num_vectors = rc;
377 rc = 0;
378 } else {
379 DP_NOTICE(cdev,
380 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
381 cnt, rc);
382 }
383
384 return rc;
385 }
386
387 /* This function outputs the int mode and the number of enabled msix vector */
388 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
389 {
390 struct qed_int_params *int_params = &cdev->int_params;
391 struct msix_entry *tbl;
392 int rc = 0, cnt;
393
394 switch (int_params->in.int_mode) {
395 case QED_INT_MODE_MSIX:
396 /* Allocate MSIX table */
397 cnt = int_params->in.num_vectors;
398 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
399 if (!int_params->msix_table) {
400 rc = -ENOMEM;
401 goto out;
402 }
403
404 /* Enable MSIX */
405 rc = qed_enable_msix(cdev, int_params);
406 if (!rc)
407 goto out;
408
409 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
410 kfree(int_params->msix_table);
411 if (force_mode)
412 goto out;
413 /* Fallthrough */
414
415 case QED_INT_MODE_MSI:
416 rc = pci_enable_msi(cdev->pdev);
417 if (!rc) {
418 int_params->out.int_mode = QED_INT_MODE_MSI;
419 goto out;
420 }
421
422 DP_NOTICE(cdev, "Failed to enable MSI\n");
423 if (force_mode)
424 goto out;
425 /* Fallthrough */
426
427 case QED_INT_MODE_INTA:
428 int_params->out.int_mode = QED_INT_MODE_INTA;
429 rc = 0;
430 goto out;
431 default:
432 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
433 int_params->in.int_mode);
434 rc = -EINVAL;
435 }
436
437 out:
438 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
439
440 return rc;
441 }
442
443 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
444 int index, void(*handler)(void *))
445 {
446 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
447 int relative_idx = index / cdev->num_hwfns;
448
449 hwfn->simd_proto_handler[relative_idx].func = handler;
450 hwfn->simd_proto_handler[relative_idx].token = token;
451 }
452
453 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
454 {
455 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
456 int relative_idx = index / cdev->num_hwfns;
457
458 memset(&hwfn->simd_proto_handler[relative_idx], 0,
459 sizeof(struct qed_simd_fp_handler));
460 }
461
462 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
463 {
464 tasklet_schedule((struct tasklet_struct *)tasklet);
465 return IRQ_HANDLED;
466 }
467
468 static irqreturn_t qed_single_int(int irq, void *dev_instance)
469 {
470 struct qed_dev *cdev = (struct qed_dev *)dev_instance;
471 struct qed_hwfn *hwfn;
472 irqreturn_t rc = IRQ_NONE;
473 u64 status;
474 int i, j;
475
476 for (i = 0; i < cdev->num_hwfns; i++) {
477 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
478
479 if (!status)
480 continue;
481
482 hwfn = &cdev->hwfns[i];
483
484 /* Slowpath interrupt */
485 if (unlikely(status & 0x1)) {
486 tasklet_schedule(hwfn->sp_dpc);
487 status &= ~0x1;
488 rc = IRQ_HANDLED;
489 }
490
491 /* Fastpath interrupts */
492 for (j = 0; j < 64; j++) {
493 if ((0x2ULL << j) & status) {
494 hwfn->simd_proto_handler[j].func(
495 hwfn->simd_proto_handler[j].token);
496 status &= ~(0x2ULL << j);
497 rc = IRQ_HANDLED;
498 }
499 }
500
501 if (unlikely(status))
502 DP_VERBOSE(hwfn, NETIF_MSG_INTR,
503 "got an unknown interrupt status 0x%llx\n",
504 status);
505 }
506
507 return rc;
508 }
509
510 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
511 {
512 struct qed_dev *cdev = hwfn->cdev;
513 int rc = 0;
514 u8 id;
515
516 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
517 id = hwfn->my_id;
518 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
519 id, cdev->pdev->bus->number,
520 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
521 rc = request_irq(cdev->int_params.msix_table[id].vector,
522 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
523 if (!rc)
524 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
525 "Requested slowpath MSI-X\n");
526 } else {
527 unsigned long flags = 0;
528
529 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
530 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
531 PCI_FUNC(cdev->pdev->devfn));
532
533 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
534 flags |= IRQF_SHARED;
535
536 rc = request_irq(cdev->pdev->irq, qed_single_int,
537 flags, cdev->name, cdev);
538 }
539
540 return rc;
541 }
542
543 static void qed_slowpath_irq_free(struct qed_dev *cdev)
544 {
545 int i;
546
547 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
548 for_each_hwfn(cdev, i) {
549 if (!cdev->hwfns[i].b_int_requested)
550 break;
551 synchronize_irq(cdev->int_params.msix_table[i].vector);
552 free_irq(cdev->int_params.msix_table[i].vector,
553 cdev->hwfns[i].sp_dpc);
554 }
555 } else {
556 if (QED_LEADING_HWFN(cdev)->b_int_requested)
557 free_irq(cdev->pdev->irq, cdev);
558 }
559 qed_int_disable_post_isr_release(cdev);
560 }
561
562 static int qed_nic_stop(struct qed_dev *cdev)
563 {
564 int i, rc;
565
566 rc = qed_hw_stop(cdev);
567
568 for (i = 0; i < cdev->num_hwfns; i++) {
569 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
570
571 if (p_hwfn->b_sp_dpc_enabled) {
572 tasklet_disable(p_hwfn->sp_dpc);
573 p_hwfn->b_sp_dpc_enabled = false;
574 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
575 "Disabled sp taskelt [hwfn %d] at %p\n",
576 i, p_hwfn->sp_dpc);
577 }
578 }
579
580 return rc;
581 }
582
583 static int qed_nic_reset(struct qed_dev *cdev)
584 {
585 int rc;
586
587 rc = qed_hw_reset(cdev);
588 if (rc)
589 return rc;
590
591 qed_resc_free(cdev);
592
593 return 0;
594 }
595
596 static int qed_nic_setup(struct qed_dev *cdev)
597 {
598 int rc;
599
600 rc = qed_resc_alloc(cdev);
601 if (rc)
602 return rc;
603
604 DP_INFO(cdev, "Allocated qed resources\n");
605
606 qed_resc_setup(cdev);
607
608 return rc;
609 }
610
611 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
612 {
613 int limit = 0;
614
615 /* Mark the fastpath as free/used */
616 cdev->int_params.fp_initialized = cnt ? true : false;
617
618 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
619 limit = cdev->num_hwfns * 63;
620 else if (cdev->int_params.fp_msix_cnt)
621 limit = cdev->int_params.fp_msix_cnt;
622
623 if (!limit)
624 return -ENOMEM;
625
626 return min_t(int, cnt, limit);
627 }
628
629 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
630 {
631 memset(info, 0, sizeof(struct qed_int_info));
632
633 if (!cdev->int_params.fp_initialized) {
634 DP_INFO(cdev,
635 "Protocol driver requested interrupt information, but its support is not yet configured\n");
636 return -EINVAL;
637 }
638
639 /* Need to expose only MSI-X information; Single IRQ is handled solely
640 * by qed.
641 */
642 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
643 int msix_base = cdev->int_params.fp_msix_base;
644
645 info->msix_cnt = cdev->int_params.fp_msix_cnt;
646 info->msix = &cdev->int_params.msix_table[msix_base];
647 }
648
649 return 0;
650 }
651
652 static int qed_slowpath_setup_int(struct qed_dev *cdev,
653 enum qed_int_mode int_mode)
654 {
655 struct qed_sb_cnt_info sb_cnt_info;
656 int rc;
657 int i;
658 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
659
660 cdev->int_params.in.int_mode = int_mode;
661 for_each_hwfn(cdev, i) {
662 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
663 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
664 cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt;
665 cdev->int_params.in.num_vectors++; /* slowpath */
666 }
667
668 /* We want a minimum of one slowpath and one fastpath vector per hwfn */
669 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
670
671 rc = qed_set_int_mode(cdev, false);
672 if (rc) {
673 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
674 return rc;
675 }
676
677 cdev->int_params.fp_msix_base = cdev->num_hwfns;
678 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
679 cdev->num_hwfns;
680
681 return 0;
682 }
683
684 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
685 {
686 int rc;
687
688 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
689 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
690
691 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
692 &cdev->int_params.in.num_vectors);
693 if (cdev->num_hwfns > 1) {
694 u8 vectors = 0;
695
696 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
697 cdev->int_params.in.num_vectors += vectors;
698 }
699
700 /* We want a minimum of one fastpath vector per vf hwfn */
701 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
702
703 rc = qed_set_int_mode(cdev, true);
704 if (rc)
705 return rc;
706
707 cdev->int_params.fp_msix_base = 0;
708 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
709
710 return 0;
711 }
712
713 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
714 u8 *input_buf, u32 max_size, u8 *unzip_buf)
715 {
716 int rc;
717
718 p_hwfn->stream->next_in = input_buf;
719 p_hwfn->stream->avail_in = input_len;
720 p_hwfn->stream->next_out = unzip_buf;
721 p_hwfn->stream->avail_out = max_size;
722
723 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
724
725 if (rc != Z_OK) {
726 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
727 rc);
728 return 0;
729 }
730
731 rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
732 zlib_inflateEnd(p_hwfn->stream);
733
734 if (rc != Z_OK && rc != Z_STREAM_END) {
735 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
736 p_hwfn->stream->msg, rc);
737 return 0;
738 }
739
740 return p_hwfn->stream->total_out / 4;
741 }
742
743 static int qed_alloc_stream_mem(struct qed_dev *cdev)
744 {
745 int i;
746 void *workspace;
747
748 for_each_hwfn(cdev, i) {
749 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
750
751 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
752 if (!p_hwfn->stream)
753 return -ENOMEM;
754
755 workspace = vzalloc(zlib_inflate_workspacesize());
756 if (!workspace)
757 return -ENOMEM;
758 p_hwfn->stream->workspace = workspace;
759 }
760
761 return 0;
762 }
763
764 static void qed_free_stream_mem(struct qed_dev *cdev)
765 {
766 int i;
767
768 for_each_hwfn(cdev, i) {
769 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
770
771 if (!p_hwfn->stream)
772 return;
773
774 vfree(p_hwfn->stream->workspace);
775 kfree(p_hwfn->stream);
776 }
777 }
778
779 static void qed_update_pf_params(struct qed_dev *cdev,
780 struct qed_pf_params *params)
781 {
782 int i;
783
784 for (i = 0; i < cdev->num_hwfns; i++) {
785 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
786
787 p_hwfn->pf_params = *params;
788 }
789 }
790
791 static int qed_slowpath_start(struct qed_dev *cdev,
792 struct qed_slowpath_params *params)
793 {
794 struct qed_tunn_start_params tunn_info;
795 struct qed_mcp_drv_version drv_version;
796 const u8 *data = NULL;
797 struct qed_hwfn *hwfn;
798 int rc = -EINVAL;
799
800 if (qed_iov_wq_start(cdev))
801 goto err;
802
803 if (IS_PF(cdev)) {
804 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
805 &cdev->pdev->dev);
806 if (rc) {
807 DP_NOTICE(cdev,
808 "Failed to find fw file - /lib/firmware/%s\n",
809 QED_FW_FILE_NAME);
810 goto err;
811 }
812 }
813
814 rc = qed_nic_setup(cdev);
815 if (rc)
816 goto err;
817
818 if (IS_PF(cdev))
819 rc = qed_slowpath_setup_int(cdev, params->int_mode);
820 else
821 rc = qed_slowpath_vf_setup_int(cdev);
822 if (rc)
823 goto err1;
824
825 if (IS_PF(cdev)) {
826 /* Allocate stream for unzipping */
827 rc = qed_alloc_stream_mem(cdev);
828 if (rc) {
829 DP_NOTICE(cdev, "Failed to allocate stream memory\n");
830 goto err2;
831 }
832
833 data = cdev->firmware->data;
834 }
835
836 memset(&tunn_info, 0, sizeof(tunn_info));
837 tunn_info.tunn_mode |= 1 << QED_MODE_VXLAN_TUNN |
838 1 << QED_MODE_L2GRE_TUNN |
839 1 << QED_MODE_IPGRE_TUNN |
840 1 << QED_MODE_L2GENEVE_TUNN |
841 1 << QED_MODE_IPGENEVE_TUNN;
842
843 tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN;
844 tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN;
845 tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN;
846
847 /* Start the slowpath */
848 rc = qed_hw_init(cdev, &tunn_info, true,
849 cdev->int_params.out.int_mode,
850 true, data);
851 if (rc)
852 goto err2;
853
854 DP_INFO(cdev,
855 "HW initialization and function start completed successfully\n");
856
857 if (IS_PF(cdev)) {
858 hwfn = QED_LEADING_HWFN(cdev);
859 drv_version.version = (params->drv_major << 24) |
860 (params->drv_minor << 16) |
861 (params->drv_rev << 8) |
862 (params->drv_eng);
863 strlcpy(drv_version.name, params->name,
864 MCP_DRV_VER_STR_SIZE - 4);
865 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
866 &drv_version);
867 if (rc) {
868 DP_NOTICE(cdev, "Failed sending drv version command\n");
869 return rc;
870 }
871 }
872
873 qed_reset_vport_stats(cdev);
874
875 return 0;
876
877 err2:
878 qed_hw_timers_stop_all(cdev);
879 if (IS_PF(cdev))
880 qed_slowpath_irq_free(cdev);
881 qed_free_stream_mem(cdev);
882 qed_disable_msix(cdev);
883 err1:
884 qed_resc_free(cdev);
885 err:
886 if (IS_PF(cdev))
887 release_firmware(cdev->firmware);
888
889 qed_iov_wq_stop(cdev, false);
890
891 return rc;
892 }
893
894 static int qed_slowpath_stop(struct qed_dev *cdev)
895 {
896 if (!cdev)
897 return -ENODEV;
898
899 if (IS_PF(cdev)) {
900 qed_free_stream_mem(cdev);
901 qed_sriov_disable(cdev, true);
902
903 qed_nic_stop(cdev);
904 qed_slowpath_irq_free(cdev);
905 }
906
907 qed_disable_msix(cdev);
908 qed_nic_reset(cdev);
909
910 qed_iov_wq_stop(cdev, true);
911
912 if (IS_PF(cdev))
913 release_firmware(cdev->firmware);
914
915 return 0;
916 }
917
918 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE],
919 char ver_str[VER_SIZE])
920 {
921 int i;
922
923 memcpy(cdev->name, name, NAME_SIZE);
924 for_each_hwfn(cdev, i)
925 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
926
927 memcpy(cdev->ver_str, ver_str, VER_SIZE);
928 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
929 }
930
931 static u32 qed_sb_init(struct qed_dev *cdev,
932 struct qed_sb_info *sb_info,
933 void *sb_virt_addr,
934 dma_addr_t sb_phy_addr, u16 sb_id,
935 enum qed_sb_type type)
936 {
937 struct qed_hwfn *p_hwfn;
938 int hwfn_index;
939 u16 rel_sb_id;
940 u8 n_hwfns;
941 u32 rc;
942
943 /* RoCE uses single engine and CMT uses two engines. When using both
944 * we force only a single engine. Storage uses only engine 0 too.
945 */
946 if (type == QED_SB_TYPE_L2_QUEUE)
947 n_hwfns = cdev->num_hwfns;
948 else
949 n_hwfns = 1;
950
951 hwfn_index = sb_id % n_hwfns;
952 p_hwfn = &cdev->hwfns[hwfn_index];
953 rel_sb_id = sb_id / n_hwfns;
954
955 DP_VERBOSE(cdev, NETIF_MSG_INTR,
956 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
957 hwfn_index, rel_sb_id, sb_id);
958
959 rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
960 sb_virt_addr, sb_phy_addr, rel_sb_id);
961
962 return rc;
963 }
964
965 static u32 qed_sb_release(struct qed_dev *cdev,
966 struct qed_sb_info *sb_info,
967 u16 sb_id)
968 {
969 struct qed_hwfn *p_hwfn;
970 int hwfn_index;
971 u16 rel_sb_id;
972 u32 rc;
973
974 hwfn_index = sb_id % cdev->num_hwfns;
975 p_hwfn = &cdev->hwfns[hwfn_index];
976 rel_sb_id = sb_id / cdev->num_hwfns;
977
978 DP_VERBOSE(cdev, NETIF_MSG_INTR,
979 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
980 hwfn_index, rel_sb_id, sb_id);
981
982 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
983
984 return rc;
985 }
986
987 static bool qed_can_link_change(struct qed_dev *cdev)
988 {
989 return true;
990 }
991
992 static int qed_set_link(struct qed_dev *cdev,
993 struct qed_link_params *params)
994 {
995 struct qed_hwfn *hwfn;
996 struct qed_mcp_link_params *link_params;
997 struct qed_ptt *ptt;
998 int rc;
999
1000 if (!cdev)
1001 return -ENODEV;
1002
1003 if (IS_VF(cdev))
1004 return 0;
1005
1006 /* The link should be set only once per PF */
1007 hwfn = &cdev->hwfns[0];
1008
1009 ptt = qed_ptt_acquire(hwfn);
1010 if (!ptt)
1011 return -EBUSY;
1012
1013 link_params = qed_mcp_get_link_params(hwfn);
1014 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1015 link_params->speed.autoneg = params->autoneg;
1016 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1017 link_params->speed.advertised_speeds = 0;
1018 if ((params->adv_speeds & SUPPORTED_1000baseT_Half) ||
1019 (params->adv_speeds & SUPPORTED_1000baseT_Full))
1020 link_params->speed.advertised_speeds |=
1021 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
1022 if (params->adv_speeds & SUPPORTED_10000baseKR_Full)
1023 link_params->speed.advertised_speeds |=
1024 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
1025 if (params->adv_speeds & SUPPORTED_40000baseLR4_Full)
1026 link_params->speed.advertised_speeds |=
1027 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
1028 if (params->adv_speeds & 0)
1029 link_params->speed.advertised_speeds |=
1030 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
1031 if (params->adv_speeds & 0)
1032 link_params->speed.advertised_speeds |=
1033 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G;
1034 }
1035 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1036 link_params->speed.forced_speed = params->forced_speed;
1037 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1038 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1039 link_params->pause.autoneg = true;
1040 else
1041 link_params->pause.autoneg = false;
1042 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1043 link_params->pause.forced_rx = true;
1044 else
1045 link_params->pause.forced_rx = false;
1046 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1047 link_params->pause.forced_tx = true;
1048 else
1049 link_params->pause.forced_tx = false;
1050 }
1051 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1052 switch (params->loopback_mode) {
1053 case QED_LINK_LOOPBACK_INT_PHY:
1054 link_params->loopback_mode = PMM_LOOPBACK_INT_PHY;
1055 break;
1056 case QED_LINK_LOOPBACK_EXT_PHY:
1057 link_params->loopback_mode = PMM_LOOPBACK_EXT_PHY;
1058 break;
1059 case QED_LINK_LOOPBACK_EXT:
1060 link_params->loopback_mode = PMM_LOOPBACK_EXT;
1061 break;
1062 case QED_LINK_LOOPBACK_MAC:
1063 link_params->loopback_mode = PMM_LOOPBACK_MAC;
1064 break;
1065 default:
1066 link_params->loopback_mode = PMM_LOOPBACK_NONE;
1067 break;
1068 }
1069 }
1070
1071 rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1072
1073 qed_ptt_release(hwfn, ptt);
1074
1075 return rc;
1076 }
1077
1078 static int qed_get_port_type(u32 media_type)
1079 {
1080 int port_type;
1081
1082 switch (media_type) {
1083 case MEDIA_SFPP_10G_FIBER:
1084 case MEDIA_SFP_1G_FIBER:
1085 case MEDIA_XFP_FIBER:
1086 case MEDIA_KR:
1087 port_type = PORT_FIBRE;
1088 break;
1089 case MEDIA_DA_TWINAX:
1090 port_type = PORT_DA;
1091 break;
1092 case MEDIA_BASE_T:
1093 port_type = PORT_TP;
1094 break;
1095 case MEDIA_NOT_PRESENT:
1096 port_type = PORT_NONE;
1097 break;
1098 case MEDIA_UNSPECIFIED:
1099 default:
1100 port_type = PORT_OTHER;
1101 break;
1102 }
1103 return port_type;
1104 }
1105
1106 static void qed_fill_link(struct qed_hwfn *hwfn,
1107 struct qed_link_output *if_link)
1108 {
1109 struct qed_mcp_link_params params;
1110 struct qed_mcp_link_state link;
1111 struct qed_mcp_link_capabilities link_caps;
1112 u32 media_type;
1113
1114 memset(if_link, 0, sizeof(*if_link));
1115
1116 /* Prepare source inputs */
1117 if (IS_PF(hwfn->cdev)) {
1118 memcpy(&params, qed_mcp_get_link_params(hwfn), sizeof(params));
1119 memcpy(&link, qed_mcp_get_link_state(hwfn), sizeof(link));
1120 memcpy(&link_caps, qed_mcp_get_link_capabilities(hwfn),
1121 sizeof(link_caps));
1122 } else {
1123 qed_vf_get_link_params(hwfn, &params);
1124 qed_vf_get_link_state(hwfn, &link);
1125 qed_vf_get_link_caps(hwfn, &link_caps);
1126 }
1127
1128 /* Set the link parameters to pass to protocol driver */
1129 if (link.link_up)
1130 if_link->link_up = true;
1131
1132 /* TODO - at the moment assume supported and advertised speed equal */
1133 if_link->supported_caps = SUPPORTED_FIBRE;
1134 if (params.speed.autoneg)
1135 if_link->supported_caps |= SUPPORTED_Autoneg;
1136 if (params.pause.autoneg ||
1137 (params.pause.forced_rx && params.pause.forced_tx))
1138 if_link->supported_caps |= SUPPORTED_Asym_Pause;
1139 if (params.pause.autoneg || params.pause.forced_rx ||
1140 params.pause.forced_tx)
1141 if_link->supported_caps |= SUPPORTED_Pause;
1142
1143 if_link->advertised_caps = if_link->supported_caps;
1144 if (params.speed.advertised_speeds &
1145 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1146 if_link->advertised_caps |= SUPPORTED_1000baseT_Half |
1147 SUPPORTED_1000baseT_Full;
1148 if (params.speed.advertised_speeds &
1149 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1150 if_link->advertised_caps |= SUPPORTED_10000baseKR_Full;
1151 if (params.speed.advertised_speeds &
1152 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1153 if_link->advertised_caps |= SUPPORTED_40000baseLR4_Full;
1154 if (params.speed.advertised_speeds &
1155 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1156 if_link->advertised_caps |= 0;
1157 if (params.speed.advertised_speeds &
1158 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G)
1159 if_link->advertised_caps |= 0;
1160
1161 if (link_caps.speed_capabilities &
1162 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1163 if_link->supported_caps |= SUPPORTED_1000baseT_Half |
1164 SUPPORTED_1000baseT_Full;
1165 if (link_caps.speed_capabilities &
1166 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1167 if_link->supported_caps |= SUPPORTED_10000baseKR_Full;
1168 if (link_caps.speed_capabilities &
1169 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1170 if_link->supported_caps |= SUPPORTED_40000baseLR4_Full;
1171 if (link_caps.speed_capabilities &
1172 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1173 if_link->supported_caps |= 0;
1174 if (link_caps.speed_capabilities &
1175 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G)
1176 if_link->supported_caps |= 0;
1177
1178 if (link.link_up)
1179 if_link->speed = link.speed;
1180
1181 /* TODO - fill duplex properly */
1182 if_link->duplex = DUPLEX_FULL;
1183 qed_mcp_get_media_type(hwfn->cdev, &media_type);
1184 if_link->port = qed_get_port_type(media_type);
1185
1186 if_link->autoneg = params.speed.autoneg;
1187
1188 if (params.pause.autoneg)
1189 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1190 if (params.pause.forced_rx)
1191 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1192 if (params.pause.forced_tx)
1193 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1194
1195 /* Link partner capabilities */
1196 if (link.partner_adv_speed &
1197 QED_LINK_PARTNER_SPEED_1G_HD)
1198 if_link->lp_caps |= SUPPORTED_1000baseT_Half;
1199 if (link.partner_adv_speed &
1200 QED_LINK_PARTNER_SPEED_1G_FD)
1201 if_link->lp_caps |= SUPPORTED_1000baseT_Full;
1202 if (link.partner_adv_speed &
1203 QED_LINK_PARTNER_SPEED_10G)
1204 if_link->lp_caps |= SUPPORTED_10000baseKR_Full;
1205 if (link.partner_adv_speed &
1206 QED_LINK_PARTNER_SPEED_40G)
1207 if_link->lp_caps |= SUPPORTED_40000baseLR4_Full;
1208 if (link.partner_adv_speed &
1209 QED_LINK_PARTNER_SPEED_50G)
1210 if_link->lp_caps |= 0;
1211 if (link.partner_adv_speed &
1212 QED_LINK_PARTNER_SPEED_100G)
1213 if_link->lp_caps |= 0;
1214
1215 if (link.an_complete)
1216 if_link->lp_caps |= SUPPORTED_Autoneg;
1217
1218 if (link.partner_adv_pause)
1219 if_link->lp_caps |= SUPPORTED_Pause;
1220 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1221 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1222 if_link->lp_caps |= SUPPORTED_Asym_Pause;
1223 }
1224
1225 static void qed_get_current_link(struct qed_dev *cdev,
1226 struct qed_link_output *if_link)
1227 {
1228 int i;
1229
1230 qed_fill_link(&cdev->hwfns[0], if_link);
1231
1232 for_each_hwfn(cdev, i)
1233 qed_inform_vf_link_state(&cdev->hwfns[i]);
1234 }
1235
1236 void qed_link_update(struct qed_hwfn *hwfn)
1237 {
1238 void *cookie = hwfn->cdev->ops_cookie;
1239 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1240 struct qed_link_output if_link;
1241
1242 qed_fill_link(hwfn, &if_link);
1243 qed_inform_vf_link_state(hwfn);
1244
1245 if (IS_LEAD_HWFN(hwfn) && cookie)
1246 op->link_update(cookie, &if_link);
1247 }
1248
1249 static int qed_drain(struct qed_dev *cdev)
1250 {
1251 struct qed_hwfn *hwfn;
1252 struct qed_ptt *ptt;
1253 int i, rc;
1254
1255 if (IS_VF(cdev))
1256 return 0;
1257
1258 for_each_hwfn(cdev, i) {
1259 hwfn = &cdev->hwfns[i];
1260 ptt = qed_ptt_acquire(hwfn);
1261 if (!ptt) {
1262 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1263 return -EBUSY;
1264 }
1265 rc = qed_mcp_drain(hwfn, ptt);
1266 if (rc)
1267 return rc;
1268 qed_ptt_release(hwfn, ptt);
1269 }
1270
1271 return 0;
1272 }
1273
1274 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
1275 {
1276 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1277 struct qed_ptt *ptt;
1278 int status = 0;
1279
1280 ptt = qed_ptt_acquire(hwfn);
1281 if (!ptt)
1282 return -EAGAIN;
1283
1284 status = qed_mcp_set_led(hwfn, ptt, mode);
1285
1286 qed_ptt_release(hwfn, ptt);
1287
1288 return status;
1289 }
1290
1291 struct qed_selftest_ops qed_selftest_ops_pass = {
1292 .selftest_memory = &qed_selftest_memory,
1293 .selftest_interrupt = &qed_selftest_interrupt,
1294 .selftest_register = &qed_selftest_register,
1295 .selftest_clock = &qed_selftest_clock,
1296 };
1297
1298 const struct qed_common_ops qed_common_ops_pass = {
1299 .selftest = &qed_selftest_ops_pass,
1300 .probe = &qed_probe,
1301 .remove = &qed_remove,
1302 .set_power_state = &qed_set_power_state,
1303 .set_id = &qed_set_id,
1304 .update_pf_params = &qed_update_pf_params,
1305 .slowpath_start = &qed_slowpath_start,
1306 .slowpath_stop = &qed_slowpath_stop,
1307 .set_fp_int = &qed_set_int_fp,
1308 .get_fp_int = &qed_get_int_fp,
1309 .sb_init = &qed_sb_init,
1310 .sb_release = &qed_sb_release,
1311 .simd_handler_config = &qed_simd_handler_config,
1312 .simd_handler_clean = &qed_simd_handler_clean,
1313 .can_link_change = &qed_can_link_change,
1314 .set_link = &qed_set_link,
1315 .get_link = &qed_get_current_link,
1316 .drain = &qed_drain,
1317 .update_msglvl = &qed_init_dp,
1318 .chain_alloc = &qed_chain_alloc,
1319 .chain_free = &qed_chain_free,
1320 .set_led = &qed_set_led,
1321 };
Linux kernel - Deliverables
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