1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
15 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
18 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
21 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
24 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
27 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
30 #define XSDM_REG_OPERATION_GEN \
32 #define NIG_REG_RX_BRB_OUT_EN \
34 #define NIG_REG_STORM_OUT_EN \
36 #define PSWRQ2_REG_L2P_VALIDATE_VFID \
38 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
40 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
42 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
44 #define PSWHST_REG_ZONE_PERMISSION_TABLE \
46 #define BAR0_MAP_REG_MSDM_RAM \
48 #define BAR0_MAP_REG_USDM_RAM \
50 #define BAR0_MAP_REG_PSDM_RAM \
52 #define BAR0_MAP_REG_TSDM_RAM \
54 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
56 #define PRS_REG_SEARCH_TCP \
58 #define PRS_REG_SEARCH_UDP \
60 #define PRS_REG_SEARCH_FCOE \
62 #define PRS_REG_SEARCH_ROCE \
64 #define PRS_REG_SEARCH_OPENFLOW \
66 #define TM_REG_PF_ENABLE_CONN \
68 #define TM_REG_PF_ENABLE_TASK \
70 #define TM_REG_PF_SCAN_ACTIVE_CONN \
72 #define TM_REG_PF_SCAN_ACTIVE_TASK \
74 #define IGU_REG_LEADING_EDGE_LATCH \
76 #define IGU_REG_TRAILING_EDGE_LATCH \
78 #define QM_REG_USG_CNT_PF_TX \
80 #define QM_REG_USG_CNT_PF_OTHER \
82 #define DORQ_REG_PF_DB_ENABLE \
84 #define DORQ_REG_VF_USAGE_CNT \
86 #define QM_REG_PF_EN \
88 #define TCFC_REG_STRONG_ENABLE_PF \
90 #define CCFC_REG_STRONG_ENABLE_PF \
92 #define PGLUE_B_REG_PGL_ADDR_88_F0 \
94 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \
96 #define PGLUE_B_REG_PGL_ADDR_90_F0 \
98 #define PGLUE_B_REG_PGL_ADDR_94_F0 \
100 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
102 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
104 #define MISC_REG_GEN_PURP_CR0 \
106 #define MCP_REG_SCRATCH \
108 #define CNIG_REG_NW_PORT_MODE_BB_B0 \
110 #define MISCS_REG_CHIP_NUM \
112 #define MISCS_REG_CHIP_REV \
114 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \
116 #define MISCS_REG_CHIP_TEST_REG \
118 #define MISCS_REG_CHIP_METAL \
120 #define MISCS_REG_FUNCTION_HIDE \
122 #define BRB_REG_HEADER_SIZE \
124 #define BTB_REG_HEADER_SIZE \
126 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \
128 #define CCFC_REG_ACTIVITY_COUNTER \
130 #define CCFC_REG_STRONG_ENABLE_VF \
132 #define CDU_REG_CID_ADDR_PARAMS \
134 #define DBG_REG_CLIENT_ENABLE \
136 #define DMAE_REG_INIT \
138 #define DORQ_REG_IFEN \
140 #define DORQ_REG_DB_DROP_REASON \
142 #define DORQ_REG_DB_DROP_DETAILS \
144 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
146 #define GRC_REG_TIMEOUT_EN \
148 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
150 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
152 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
154 #define IGU_REG_BLOCK_CONFIGURATION \
156 #define MCM_REG_INIT \
158 #define MCP2_REG_DBG_DWORD_ENABLE \
160 #define MISC_REG_PORT_MODE \
162 #define MISCS_REG_CLK_100G_MODE \
164 #define MSDM_REG_ENABLE_IN1 \
166 #define MSEM_REG_ENABLE_IN \
168 #define NIG_REG_CM_HDR \
170 #define NCSI_REG_CONFIG \
172 #define PBF_REG_INIT \
174 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
176 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
178 #define PTU_REG_ATC_INIT_ARRAY \
180 #define PCM_REG_INIT \
182 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \
184 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
186 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
188 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
190 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
192 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
194 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
196 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
198 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
200 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
202 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
204 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
206 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
208 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
210 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
212 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
214 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
216 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
218 #define PRM_REG_DISABLE_PRM \
220 #define PRS_REG_SOFT_RST \
222 #define PSDM_REG_ENABLE_IN1 \
224 #define PSEM_REG_ENABLE_IN \
226 #define PSWRQ_REG_DBG_SELECT \
228 #define PSWRQ2_REG_CDUT_P_SIZE \
230 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \
232 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
234 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
236 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
238 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
240 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
242 #define PSWRD_REG_DBG_SELECT \
244 #define PSWRD2_REG_CONF11 \
246 #define PSWWR_REG_USDM_FULL_TH \
248 #define PSWWR2_REG_CDU_FULL_TH2 \
250 #define QM_REG_MAXPQSIZE_0 \
252 #define RSS_REG_RSS_INIT_EN \
254 #define RDIF_REG_STOP_ON_ERROR \
256 #define SRC_REG_SOFT_RST \
258 #define TCFC_REG_ACTIVITY_COUNTER \
260 #define TCM_REG_INIT \
262 #define TM_REG_PXP_READ_DATA_FIFO_INIT \
264 #define TSDM_REG_ENABLE_IN1 \
266 #define TSEM_REG_ENABLE_IN \
268 #define TDIF_REG_STOP_ON_ERROR \
270 #define UCM_REG_INIT \
272 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
274 #define USDM_REG_ENABLE_IN1 \
276 #define USEM_REG_ENABLE_IN \
278 #define XCM_REG_INIT \
280 #define XSDM_REG_ENABLE_IN1 \
282 #define XSEM_REG_ENABLE_IN \
284 #define YCM_REG_INIT \
286 #define YSDM_REG_ENABLE_IN1 \
288 #define YSEM_REG_ENABLE_IN \
290 #define XYLD_REG_SCBD_STRICT_PRIO \
292 #define TMLD_REG_SCBD_STRICT_PRIO \
294 #define MULD_REG_SCBD_STRICT_PRIO \
296 #define YULD_REG_SCBD_STRICT_PRIO \
298 #define MISC_REG_SHARED_MEM_ADDR \
300 #define DMAE_REG_GO_C0 \
302 #define DMAE_REG_GO_C1 \
304 #define DMAE_REG_GO_C2 \
306 #define DMAE_REG_GO_C3 \
308 #define DMAE_REG_GO_C4 \
310 #define DMAE_REG_GO_C5 \
312 #define DMAE_REG_GO_C6 \
314 #define DMAE_REG_GO_C7 \
316 #define DMAE_REG_GO_C8 \
318 #define DMAE_REG_GO_C9 \
320 #define DMAE_REG_GO_C10 \
322 #define DMAE_REG_GO_C11 \
324 #define DMAE_REG_GO_C12 \
326 #define DMAE_REG_GO_C13 \
328 #define DMAE_REG_GO_C14 \
330 #define DMAE_REG_GO_C15 \
332 #define DMAE_REG_GO_C16 \
334 #define DMAE_REG_GO_C17 \
336 #define DMAE_REG_GO_C18 \
338 #define DMAE_REG_GO_C19 \
340 #define DMAE_REG_GO_C20 \
342 #define DMAE_REG_GO_C21 \
344 #define DMAE_REG_GO_C22 \
346 #define DMAE_REG_GO_C23 \
348 #define DMAE_REG_GO_C24 \
350 #define DMAE_REG_GO_C25 \
352 #define DMAE_REG_GO_C26 \
354 #define DMAE_REG_GO_C27 \
356 #define DMAE_REG_GO_C28 \
358 #define DMAE_REG_GO_C29 \
360 #define DMAE_REG_GO_C30 \
362 #define DMAE_REG_GO_C31 \
364 #define DMAE_REG_CMD_MEM \
366 #define QM_REG_MAXPQSIZETXSEL_0 \
368 #define QM_REG_SDMCMDREADY \
370 #define QM_REG_SDMCMDADDR \
372 #define QM_REG_SDMCMDDATALSB \
374 #define QM_REG_SDMCMDDATAMSB \
376 #define QM_REG_SDMCMDGO \
378 #define QM_REG_RLPFCRD \
380 #define QM_REG_RLPFINCVAL \
382 #define QM_REG_RLGLBLCRD \
384 #define QM_REG_RLGLBLINCVAL \
386 #define IGU_REG_ATTENTION_ENABLE \
388 #define IGU_REG_ATTN_MSG_ADDR_L \
390 #define IGU_REG_ATTN_MSG_ADDR_H \
392 #define MISC_REG_AEU_GENERAL_ATTN_0 \
394 #define CAU_REG_SB_ADDR_MEMORY \
396 #define CAU_REG_SB_VAR_MEMORY \
398 #define CAU_REG_PI_MEMORY \
400 #define IGU_REG_PF_CONFIGURATION \
402 #define IGU_REG_VF_CONFIGURATION \
404 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
406 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
408 #define MISC_REG_AEU_MASK_ATTN_IGU \
410 #define IGU_REG_CLEANUP_STATUS_0 \
412 #define IGU_REG_CLEANUP_STATUS_1 \
414 #define IGU_REG_CLEANUP_STATUS_2 \
416 #define IGU_REG_CLEANUP_STATUS_3 \
418 #define IGU_REG_CLEANUP_STATUS_4 \
420 #define IGU_REG_COMMAND_REG_32LSB_DATA \
422 #define IGU_REG_COMMAND_REG_CTRL \
424 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
426 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
428 #define IGU_REG_MAPPING_MEMORY \
430 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
432 #define IGU_REG_WRITE_DONE_PENDING \
434 #define MISCS_REG_GENERIC_POR_0 \
436 #define MCP_REG_NVM_CFG4 \
438 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
440 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
442 #define MCP_REG_CPU_STATE \
444 #define MCP_REG_CPU_EVENT_MASK \
446 #define PGLUE_B_REG_PF_BAR0_SIZE \
448 #define PGLUE_B_REG_PF_BAR1_SIZE \
450 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
451 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL
452 #define PRS_REG_VXLAN_PORT 0x1f0738UL
453 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
454 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
456 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
457 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
458 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)
459 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
460 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)
461 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
463 #define NIG_REG_VXLAN_PORT 0x50105cUL
464 #define PBF_REG_VXLAN_PORT 0xd80518UL
465 #define PBF_REG_NGE_PORT 0xd8051cUL
466 #define PRS_REG_NGE_PORT 0x1f086cUL
467 #define NIG_REG_NGE_PORT 0x508b38UL
469 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
470 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
471 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
472 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
473 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
475 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL
476 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
477 #define NIG_REG_NGE_COMP_VER 0x508b30UL
478 #define PBF_REG_NGE_COMP_VER 0xd80524UL
479 #define PRS_REG_NGE_COMP_VER 0x1f0878UL
481 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL
482 #define QM_REG_WFQVPWEIGHT 0x2fa000UL
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