1 /* QLogic qede NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
11 #include <linux/compiler.h>
12 #include <linux/version.h>
13 #include <linux/workqueue.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/bitmap.h>
17 #include <linux/kernel.h>
18 #include <linux/mutex.h>
20 #include <linux/qed/common_hsi.h>
21 #include <linux/qed/eth_common.h>
22 #include <linux/qed/qed_if.h>
23 #include <linux/qed/qed_chain.h>
24 #include <linux/qed/qed_eth_if.h>
26 #define QEDE_MAJOR_VERSION 8
27 #define QEDE_MINOR_VERSION 4
28 #define QEDE_REVISION_VERSION 0
29 #define QEDE_ENGINEERING_VERSION 0
30 #define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \
31 __stringify(QEDE_MINOR_VERSION) "." \
32 __stringify(QEDE_REVISION_VERSION) "." \
33 __stringify(QEDE_ENGINEERING_VERSION)
35 #define QEDE_ETH_INTERFACE_VERSION 300
37 #define DRV_MODULE_SYM qede
47 u64 mftag_filter_discards
;
48 u64 mac_filter_discards
;
58 u64 coalesced_aborts_num
;
59 u64 non_coalesced_pkts
;
63 u64 rx_64_byte_packets
;
64 u64 rx_127_byte_packets
;
65 u64 rx_255_byte_packets
;
66 u64 rx_511_byte_packets
;
67 u64 rx_1023_byte_packets
;
68 u64 rx_1518_byte_packets
;
69 u64 rx_1522_byte_packets
;
70 u64 rx_2047_byte_packets
;
71 u64 rx_4095_byte_packets
;
72 u64 rx_9216_byte_packets
;
73 u64 rx_16383_byte_packets
;
75 u64 rx_mac_crtl_frames
;
79 u64 rx_carrier_errors
;
80 u64 rx_oversize_packets
;
82 u64 rx_undersize_packets
;
84 u64 tx_64_byte_packets
;
85 u64 tx_65_to_127_byte_packets
;
86 u64 tx_128_to_255_byte_packets
;
87 u64 tx_256_to_511_byte_packets
;
88 u64 tx_512_to_1023_byte_packets
;
89 u64 tx_1024_to_1518_byte_packets
;
90 u64 tx_1519_to_2047_byte_packets
;
91 u64 tx_2048_to_4095_byte_packets
;
92 u64 tx_4096_to_9216_byte_packets
;
93 u64 tx_9217_to_16383_byte_packets
;
96 u64 tx_lpi_entry_count
;
97 u64 tx_total_collisions
;
100 u64 tx_mac_ctrl_frames
;
104 struct qed_dev
*cdev
;
105 struct net_device
*ndev
;
106 struct pci_dev
*pdev
;
111 const struct qed_eth_ops
*ops
;
113 struct qed_dev_eth_info dev_info
;
114 #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
115 #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \
116 (edev)->dev_info.num_tc)
118 struct qede_fastpath
*fp_array
;
122 #define QEDE_RSS_CNT(edev) ((edev)->num_rss)
123 #define QEDE_TSS_CNT(edev) ((edev)->num_rss * \
125 #define QEDE_TSS_IDX(edev, txqidx) ((txqidx) % (edev)->num_rss)
126 #define QEDE_TC_IDX(edev, txqidx) ((txqidx) / (edev)->num_rss)
127 #define QEDE_TX_QUEUE(edev, txqidx) \
128 (&(edev)->fp_array[QEDE_TSS_IDX((edev), (txqidx))].txqs[QEDE_TC_IDX( \
131 struct qed_int_info int_info
;
132 unsigned char primary_mac
[ETH_ALEN
];
134 /* Smaller private varaiant of the RTNL lock */
135 struct mutex qede_lock
;
136 u32 state
; /* Protected by qede_lock */
138 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
139 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
140 /* Max supported alignment is 256 (8 shift)
141 * minimal alignment shift 6 is optimal for 57xxx HW performance
143 #define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
144 /* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
145 * at the end of skb->data, to avoid wasting a full cache line.
146 * This reduces memory use (skb->truesize).
148 #define QEDE_FW_RX_ALIGN_END \
149 max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \
150 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
152 struct qede_stats stats
;
153 struct qed_update_vport_rss_params rss_params
;
154 u16 q_num_rx_buffers
; /* Must be a power of two */
155 u16 q_num_tx_buffers
; /* Must be a power of two */
157 struct delayed_work sp_task
;
158 unsigned long sp_flags
;
166 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
169 #define MAX_NUM_PRI 8
171 /* The driver supports the new build_skb() API:
172 * RX ring buffer contains pointer to kmalloc() data only,
173 * skb are built only after the frame was DMA-ed.
178 unsigned int page_offset
;
181 struct qede_rx_queue
{
183 struct sw_rx_data
*sw_rx_ring
;
186 struct qed_chain rx_bd_ring
;
187 struct qed_chain rx_comp_ring
;
188 void __iomem
*hw_rxq_prod_addr
;
191 unsigned int rx_buf_seg_size
;
201 struct eth_db_data data
;
208 /* Set on the first BD descriptor when there is a split BD */
209 #define QEDE_TSO_SPLIT_BD BIT(0)
212 struct qede_tx_queue
{
213 int index
; /* Queue index */
215 struct sw_tx_bd
*sw_tx_ring
;
218 struct qed_chain tx_pbl
;
219 void __iomem
*doorbell_addr
;
225 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \
226 le32_to_cpu((bd)->addr.lo))
227 #define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \
229 (bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \
230 (bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \
231 (bd)->nbytes = cpu_to_le16(len); \
233 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
235 struct qede_fastpath
{
236 struct qede_dev
*edev
;
238 struct napi_struct napi
;
239 struct qed_sb_info
*sb_info
;
240 struct qede_rx_queue
*rxq
;
241 struct qede_tx_queue
*txqs
;
243 #define VEC_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
244 char name
[VEC_NAME_SIZE
];
247 /* Debug print definitions */
248 #define DP_NAME(edev) ((edev)->ndev->name)
251 #define XMIT_L4_CSUM BIT(0)
252 #define XMIT_LSO BIT(1)
253 #define XMIT_ENC BIT(2)
255 #define QEDE_CSUM_ERROR BIT(0)
256 #define QEDE_CSUM_UNNECESSARY BIT(1)
258 #define QEDE_SP_RX_MODE 1
260 union qede_reload_args
{
264 void qede_config_debug(uint debug
, u32
*p_dp_module
, u8
*p_dp_level
);
265 void qede_set_ethtool_ops(struct net_device
*netdev
);
266 void qede_reload(struct qede_dev
*edev
,
267 void (*func
)(struct qede_dev
*edev
,
268 union qede_reload_args
*args
),
269 union qede_reload_args
*args
);
270 int qede_change_mtu(struct net_device
*dev
, int new_mtu
);
271 void qede_fill_by_demand_stats(struct qede_dev
*edev
);
273 #define RX_RING_SIZE_POW 13
274 #define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW))
275 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
276 #define NUM_RX_BDS_MIN 128
277 #define NUM_RX_BDS_DEF NUM_RX_BDS_MAX
279 #define TX_RING_SIZE_POW 13
280 #define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW))
281 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
282 #define NUM_TX_BDS_MIN 128
283 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
285 #define QEDE_RX_HDR_SIZE 256
286 #define for_each_rss(i) for (i = 0; i < edev->num_rss; i++)
288 #endif /* _QEDE_H_ */