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qlcnic: dcb: Add support for CEE Netlink interface.
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic.h
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23 #include <linux/ethtool.h>
24 #include <linux/mii.h>
25 #include <linux/timer.h>
26
27 #include <linux/vmalloc.h>
28
29 #include <linux/io.h>
30 #include <asm/byteorder.h>
31 #include <linux/bitops.h>
32 #include <linux/if_vlan.h>
33
34 #include "qlcnic_hdr.h"
35 #include "qlcnic_hw.h"
36 #include "qlcnic_83xx_hw.h"
37 #include "qlcnic_dcb.h"
38
39 #define _QLCNIC_LINUX_MAJOR 5
40 #define _QLCNIC_LINUX_MINOR 3
41 #define _QLCNIC_LINUX_SUBVERSION 48
42 #define QLCNIC_LINUX_VERSIONID "5.3.48"
43 #define QLCNIC_DRV_IDC_VER 0x01
44 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
45 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
46
47 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
48 #define _major(v) (((v) >> 24) & 0xff)
49 #define _minor(v) (((v) >> 16) & 0xff)
50 #define _build(v) ((v) & 0xffff)
51
52 /* version in image has weird encoding:
53 * 7:0 - major
54 * 15:8 - minor
55 * 31:16 - build (little endian)
56 */
57 #define QLCNIC_DECODE_VERSION(v) \
58 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
59
60 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
61 #define QLCNIC_NUM_FLASH_SECTORS (64)
62 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
63 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
64 * QLCNIC_FLASH_SECTOR_SIZE)
65
66 #define RCV_DESC_RINGSIZE(rds_ring) \
67 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
68 #define RCV_BUFF_RINGSIZE(rds_ring) \
69 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
70 #define STATUS_DESC_RINGSIZE(sds_ring) \
71 (sizeof(struct status_desc) * (sds_ring)->num_desc)
72 #define TX_BUFF_RINGSIZE(tx_ring) \
73 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
74 #define TX_DESC_RINGSIZE(tx_ring) \
75 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
76
77 #define QLCNIC_P3P_A0 0x50
78 #define QLCNIC_P3P_C0 0x58
79
80 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
81
82 #define FIRST_PAGE_GROUP_START 0
83 #define FIRST_PAGE_GROUP_END 0x100000
84
85 #define P3P_MAX_MTU (9600)
86 #define P3P_MIN_MTU (68)
87 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
88
89 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
90 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
91 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
92 #define QLCNIC_LRO_BUFFER_EXTRA 2048
93
94 /* Tx defines */
95 #define QLCNIC_MAX_FRAGS_PER_TX 14
96 #define MAX_TSO_HEADER_DESC 2
97 #define MGMT_CMD_DESC_RESV 4
98 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
99 + MGMT_CMD_DESC_RESV)
100 #define QLCNIC_MAX_TX_TIMEOUTS 2
101 #define QLCNIC_MAX_TX_RINGS 8
102 #define QLCNIC_MAX_SDS_RINGS 8
103
104 /*
105 * Following are the states of the Phantom. Phantom will set them and
106 * Host will read to check if the fields are correct.
107 */
108 #define PHAN_INITIALIZE_FAILED 0xffff
109 #define PHAN_INITIALIZE_COMPLETE 0xff01
110
111 /* Host writes the following to notify that it has done the init-handshake */
112 #define PHAN_INITIALIZE_ACK 0xf00f
113 #define PHAN_PEG_RCV_INITIALIZED 0xff01
114
115 #define NUM_RCV_DESC_RINGS 3
116
117 #define RCV_RING_NORMAL 0
118 #define RCV_RING_JUMBO 1
119
120 #define MIN_CMD_DESCRIPTORS 64
121 #define MIN_RCV_DESCRIPTORS 64
122 #define MIN_JUMBO_DESCRIPTORS 32
123
124 #define MAX_CMD_DESCRIPTORS 1024
125 #define MAX_RCV_DESCRIPTORS_1G 4096
126 #define MAX_RCV_DESCRIPTORS_10G 8192
127 #define MAX_RCV_DESCRIPTORS_VF 2048
128 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
129 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
130
131 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
132 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
133 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
134 #define MAX_RDS_RINGS 2
135
136 #define get_next_index(index, length) \
137 (((index) + 1) & ((length) - 1))
138
139 /*
140 * Following data structures describe the descriptors that will be used.
141 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
142 * we are doing LSO (above the 1500 size packet) only.
143 */
144 struct cmd_desc_type0 {
145 u8 tcp_hdr_offset; /* For LSO only */
146 u8 ip_hdr_offset; /* For LSO only */
147 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
148 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
149
150 __le64 addr_buffer2;
151
152 __le16 reference_handle;
153 __le16 mss;
154 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
155 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
156 __le16 conn_id; /* IPSec offoad only */
157
158 __le64 addr_buffer3;
159 __le64 addr_buffer1;
160
161 __le16 buffer_length[4];
162
163 __le64 addr_buffer4;
164
165 u8 eth_addr[ETH_ALEN];
166 __le16 vlan_TCI;
167
168 } __attribute__ ((aligned(64)));
169
170 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
171 struct rcv_desc {
172 __le16 reference_handle;
173 __le16 reserved;
174 __le32 buffer_length; /* allocated buffer length (usually 2K) */
175 __le64 addr_buffer;
176 } __packed;
177
178 struct status_desc {
179 __le64 status_desc_data[2];
180 } __attribute__ ((aligned(16)));
181
182 /* UNIFIED ROMIMAGE */
183 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
184 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
185 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
186 #define QLCNIC_UNI_DIR_SECT_FW 0x7
187
188 /*Offsets */
189 #define QLCNIC_UNI_CHIP_REV_OFF 10
190 #define QLCNIC_UNI_FLAGS_OFF 11
191 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
192 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
193 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
194
195 struct uni_table_desc{
196 __le32 findex;
197 __le32 num_entries;
198 __le32 entry_size;
199 __le32 reserved[5];
200 };
201
202 struct uni_data_desc{
203 __le32 findex;
204 __le32 size;
205 __le32 reserved[5];
206 };
207
208 /* Flash Defines and Structures */
209 #define QLCNIC_FLT_LOCATION 0x3F1000
210 #define QLCNIC_FDT_LOCATION 0x3F0000
211 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
212 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
213 #define QLCNIC_BOOTLD_REGION 0X72
214 struct qlcnic_flt_header {
215 u16 version;
216 u16 len;
217 u16 checksum;
218 u16 reserved;
219 };
220
221 struct qlcnic_flt_entry {
222 u8 region;
223 u8 reserved0;
224 u8 attrib;
225 u8 reserved1;
226 u32 size;
227 u32 start_addr;
228 u32 end_addr;
229 };
230
231 /* Flash Descriptor Table */
232 struct qlcnic_fdt {
233 u32 valid;
234 u16 ver;
235 u16 len;
236 u16 cksum;
237 u16 unused;
238 u8 model[16];
239 u16 mfg_id;
240 u16 id;
241 u8 flag;
242 u8 erase_cmd;
243 u8 alt_erase_cmd;
244 u8 write_enable_cmd;
245 u8 write_enable_bits;
246 u8 write_statusreg_cmd;
247 u8 unprotected_sec_cmd;
248 u8 read_manuf_cmd;
249 u32 block_size;
250 u32 alt_block_size;
251 u32 flash_size;
252 u32 write_enable_data;
253 u8 readid_addr_len;
254 u8 write_disable_bits;
255 u8 read_dev_id_len;
256 u8 chip_erase_cmd;
257 u16 read_timeo;
258 u8 protected_sec_cmd;
259 u8 resvd[65];
260 };
261 /* Magic number to let user know flash is programmed */
262 #define QLCNIC_BDINFO_MAGIC 0x12345678
263
264 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
265 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
266 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
267 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
268 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
269 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
270 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
271 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
272 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
273 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
274 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
275 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
276 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
277 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
278
279 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
280
281 /* Flash memory map */
282 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
283 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
284 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
285 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
286
287 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
288 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
289 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
290 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
291
292 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
293 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
294
295 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
296 #define QLCNIC_UNIFIED_ROMIMAGE 0
297 #define QLCNIC_FLASH_ROMIMAGE 1
298 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
299
300 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
301 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
302
303 extern char qlcnic_driver_name[];
304
305 extern int qlcnic_use_msi;
306 extern int qlcnic_use_msi_x;
307 extern int qlcnic_auto_fw_reset;
308 extern int qlcnic_load_fw_file;
309
310 /* Number of status descriptors to handle per interrupt */
311 #define MAX_STATUS_HANDLE (64)
312
313 /*
314 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
315 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
316 */
317 struct qlcnic_skb_frag {
318 u64 dma;
319 u64 length;
320 };
321
322 /* Following defines are for the state of the buffers */
323 #define QLCNIC_BUFFER_FREE 0
324 #define QLCNIC_BUFFER_BUSY 1
325
326 /*
327 * There will be one qlcnic_buffer per skb packet. These will be
328 * used to save the dma info for pci_unmap_page()
329 */
330 struct qlcnic_cmd_buffer {
331 struct sk_buff *skb;
332 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
333 u32 frag_count;
334 };
335
336 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
337 struct qlcnic_rx_buffer {
338 u16 ref_handle;
339 struct sk_buff *skb;
340 struct list_head list;
341 u64 dma;
342 };
343
344 /* Board types */
345 #define QLCNIC_GBE 0x01
346 #define QLCNIC_XGBE 0x02
347
348 /*
349 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
350 * adjusted based on configured MTU.
351 */
352 #define QLCNIC_INTR_COAL_TYPE_RX 1
353 #define QLCNIC_INTR_COAL_TYPE_TX 2
354
355 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3
356 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256
357
358 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64
359 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64
360
361 #define QLCNIC_INTR_DEFAULT 0x04
362 #define QLCNIC_CONFIG_INTR_COALESCE 3
363 #define QLCNIC_DEV_INFO_SIZE 1
364
365 struct qlcnic_nic_intr_coalesce {
366 u8 type;
367 u8 sts_ring_mask;
368 u16 rx_packets;
369 u16 rx_time_us;
370 u16 tx_packets;
371 u16 tx_time_us;
372 u16 flag;
373 u32 timer_out;
374 };
375
376 struct qlcnic_dump_template_hdr {
377 u32 type;
378 u32 offset;
379 u32 size;
380 u32 cap_mask;
381 u32 num_entries;
382 u32 version;
383 u32 timestamp;
384 u32 checksum;
385 u32 drv_cap_mask;
386 u32 sys_info[3];
387 u32 saved_state[16];
388 u32 cap_sizes[8];
389 u32 ocm_wnd_reg[16];
390 u32 rsvd[0];
391 };
392
393 struct qlcnic_fw_dump {
394 u8 clr; /* flag to indicate if dump is cleared */
395 u8 enable; /* enable/disable dump */
396 u32 size; /* total size of the dump */
397 void *data; /* dump data area */
398 struct qlcnic_dump_template_hdr *tmpl_hdr;
399 dma_addr_t phys_addr;
400 void *dma_buffer;
401 bool use_pex_dma;
402 };
403
404 /*
405 * One hardware_context{} per adapter
406 * contains interrupt info as well shared hardware info.
407 */
408 struct qlcnic_hardware_context {
409 void __iomem *pci_base0;
410 void __iomem *ocm_win_crb;
411
412 unsigned long pci_len0;
413
414 rwlock_t crb_lock;
415 struct mutex mem_lock;
416
417 u8 revision_id;
418 u8 pci_func;
419 u8 linkup;
420 u8 loopback_state;
421 u8 beacon_state;
422 u8 has_link_events;
423 u8 fw_type;
424 u8 physical_port;
425 u8 reset_context;
426 u8 msix_supported;
427 u8 max_mac_filters;
428 u8 mc_enabled;
429 u8 max_mc_count;
430 u8 diag_test;
431 u8 num_msix;
432 u8 nic_mode;
433 char diag_cnt;
434
435 u16 max_uc_count;
436 u16 port_type;
437 u16 board_type;
438 u16 supported_type;
439
440 u16 link_speed;
441 u16 link_duplex;
442 u16 link_autoneg;
443 u16 module_type;
444
445 u16 op_mode;
446 u16 switch_mode;
447 u16 max_tx_ques;
448 u16 max_rx_ques;
449 u16 max_mtu;
450 u32 msg_enable;
451 u16 act_pci_func;
452 u16 max_pci_func;
453
454 u32 capabilities;
455 u32 extra_capability[3];
456 u32 temp;
457 u32 int_vec_bit;
458 u32 fw_hal_version;
459 u32 port_config;
460 struct qlcnic_hardware_ops *hw_ops;
461 struct qlcnic_nic_intr_coalesce coal;
462 struct qlcnic_fw_dump fw_dump;
463 struct qlcnic_fdt fdt;
464 struct qlc_83xx_reset reset;
465 struct qlc_83xx_idc idc;
466 struct qlc_83xx_fw_info fw_info;
467 struct qlcnic_intrpt_config *intr_tbl;
468 struct qlcnic_sriov *sriov;
469 u32 *reg_tbl;
470 u32 *ext_reg_tbl;
471 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT];
472 u32 mbox_reg[4];
473 struct qlcnic_mailbox *mailbox;
474 u8 extend_lb_time;
475 u8 phys_port_id[ETH_ALEN];
476 };
477
478 struct qlcnic_adapter_stats {
479 u64 xmitcalled;
480 u64 xmitfinished;
481 u64 rxdropped;
482 u64 txdropped;
483 u64 csummed;
484 u64 rx_pkts;
485 u64 lro_pkts;
486 u64 rxbytes;
487 u64 txbytes;
488 u64 lrobytes;
489 u64 lso_frames;
490 u64 xmit_on;
491 u64 xmit_off;
492 u64 skb_alloc_failure;
493 u64 null_rxbuf;
494 u64 rx_dma_map_error;
495 u64 tx_dma_map_error;
496 u64 spurious_intr;
497 u64 mac_filter_limit_overrun;
498 };
499
500 /*
501 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
502 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
503 */
504 struct qlcnic_host_rds_ring {
505 void __iomem *crb_rcv_producer;
506 struct rcv_desc *desc_head;
507 struct qlcnic_rx_buffer *rx_buf_arr;
508 u32 num_desc;
509 u32 producer;
510 u32 dma_size;
511 u32 skb_size;
512 u32 flags;
513 struct list_head free_list;
514 spinlock_t lock;
515 dma_addr_t phys_addr;
516 } ____cacheline_internodealigned_in_smp;
517
518 struct qlcnic_host_sds_ring {
519 u32 consumer;
520 u32 num_desc;
521 void __iomem *crb_sts_consumer;
522
523 struct qlcnic_host_tx_ring *tx_ring;
524 struct status_desc *desc_head;
525 struct qlcnic_adapter *adapter;
526 struct napi_struct napi;
527 struct list_head free_list[NUM_RCV_DESC_RINGS];
528
529 void __iomem *crb_intr_mask;
530 int irq;
531
532 dma_addr_t phys_addr;
533 char name[IFNAMSIZ + 12];
534 } ____cacheline_internodealigned_in_smp;
535
536 struct qlcnic_host_tx_ring {
537 int irq;
538 void __iomem *crb_intr_mask;
539 char name[IFNAMSIZ + 12];
540 u16 ctx_id;
541
542 u32 state;
543 u32 producer;
544 u32 sw_consumer;
545 u32 num_desc;
546
547 u64 xmit_on;
548 u64 xmit_off;
549 u64 xmit_called;
550 u64 xmit_finished;
551
552 void __iomem *crb_cmd_producer;
553 struct cmd_desc_type0 *desc_head;
554 struct qlcnic_adapter *adapter;
555 struct napi_struct napi;
556 struct qlcnic_cmd_buffer *cmd_buf_arr;
557 __le32 *hw_consumer;
558
559 dma_addr_t phys_addr;
560 dma_addr_t hw_cons_phys_addr;
561 struct netdev_queue *txq;
562 } ____cacheline_internodealigned_in_smp;
563
564 /*
565 * Receive context. There is one such structure per instance of the
566 * receive processing. Any state information that is relevant to
567 * the receive, and is must be in this structure. The global data may be
568 * present elsewhere.
569 */
570 struct qlcnic_recv_context {
571 struct qlcnic_host_rds_ring *rds_rings;
572 struct qlcnic_host_sds_ring *sds_rings;
573 u32 state;
574 u16 context_id;
575 u16 virt_port;
576 };
577
578 /* HW context creation */
579
580 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
581
582 #define QLCNIC_CDRP_CMD_BIT 0x80000000
583
584 /*
585 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
586 * in the crb QLCNIC_CDRP_CRB_OFFSET.
587 */
588 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
589 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
590
591 #define QLCNIC_CDRP_RSP_OK 0x00000001
592 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
593 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
594
595 /*
596 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
597 * the crb QLCNIC_CDRP_CRB_OFFSET.
598 */
599 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
600
601 #define QLCNIC_RCODE_SUCCESS 0
602 #define QLCNIC_RCODE_INVALID_ARGS 6
603 #define QLCNIC_RCODE_NOT_SUPPORTED 9
604 #define QLCNIC_RCODE_NOT_PERMITTED 10
605 #define QLCNIC_RCODE_NOT_IMPL 15
606 #define QLCNIC_RCODE_INVALID 16
607 #define QLCNIC_RCODE_TIMEOUT 17
608 #define QLCNIC_DESTROY_CTX_RESET 0
609
610 /*
611 * Capabilities Announced
612 */
613 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
614 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
615 #define QLCNIC_CAP0_LSO (1 << 6)
616 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
617 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
618 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
619 #define QLCNIC_CAP0_LRO_MSS (1 << 21)
620 #define QLCNIC_CAP0_TX_MULTI (1 << 22)
621
622 /*
623 * Context state
624 */
625 #define QLCNIC_HOST_CTX_STATE_FREED 0
626 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
627
628 /*
629 * Rx context
630 */
631
632 struct qlcnic_hostrq_sds_ring {
633 __le64 host_phys_addr; /* Ring base addr */
634 __le32 ring_size; /* Ring entries */
635 __le16 msi_index;
636 __le16 rsvd; /* Padding */
637 } __packed;
638
639 struct qlcnic_hostrq_rds_ring {
640 __le64 host_phys_addr; /* Ring base addr */
641 __le64 buff_size; /* Packet buffer size */
642 __le32 ring_size; /* Ring entries */
643 __le32 ring_kind; /* Class of ring */
644 } __packed;
645
646 struct qlcnic_hostrq_rx_ctx {
647 __le64 host_rsp_dma_addr; /* Response dma'd here */
648 __le32 capabilities[4]; /* Flag bit vector */
649 __le32 host_int_crb_mode; /* Interrupt crb usage */
650 __le32 host_rds_crb_mode; /* RDS crb usage */
651 /* These ring offsets are relative to data[0] below */
652 __le32 rds_ring_offset; /* Offset to RDS config */
653 __le32 sds_ring_offset; /* Offset to SDS config */
654 __le16 num_rds_rings; /* Count of RDS rings */
655 __le16 num_sds_rings; /* Count of SDS rings */
656 __le16 valid_field_offset;
657 u8 txrx_sds_binding;
658 u8 msix_handler;
659 u8 reserved[128]; /* reserve space for future expansion*/
660 /* MUST BE 64-bit aligned.
661 The following is packed:
662 - N hostrq_rds_rings
663 - N hostrq_sds_rings */
664 char data[0];
665 } __packed;
666
667 struct qlcnic_cardrsp_rds_ring{
668 __le32 host_producer_crb; /* Crb to use */
669 __le32 rsvd1; /* Padding */
670 } __packed;
671
672 struct qlcnic_cardrsp_sds_ring {
673 __le32 host_consumer_crb; /* Crb to use */
674 __le32 interrupt_crb; /* Crb to use */
675 } __packed;
676
677 struct qlcnic_cardrsp_rx_ctx {
678 /* These ring offsets are relative to data[0] below */
679 __le32 rds_ring_offset; /* Offset to RDS config */
680 __le32 sds_ring_offset; /* Offset to SDS config */
681 __le32 host_ctx_state; /* Starting State */
682 __le32 num_fn_per_port; /* How many PCI fn share the port */
683 __le16 num_rds_rings; /* Count of RDS rings */
684 __le16 num_sds_rings; /* Count of SDS rings */
685 __le16 context_id; /* Handle for context */
686 u8 phys_port; /* Physical id of port */
687 u8 virt_port; /* Virtual/Logical id of port */
688 u8 reserved[128]; /* save space for future expansion */
689 /* MUST BE 64-bit aligned.
690 The following is packed:
691 - N cardrsp_rds_rings
692 - N cardrs_sds_rings */
693 char data[0];
694 } __packed;
695
696 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
697 (sizeof(HOSTRQ_RX) + \
698 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
699 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
700
701 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
702 (sizeof(CARDRSP_RX) + \
703 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
704 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
705
706 /*
707 * Tx context
708 */
709
710 struct qlcnic_hostrq_cds_ring {
711 __le64 host_phys_addr; /* Ring base addr */
712 __le32 ring_size; /* Ring entries */
713 __le32 rsvd; /* Padding */
714 } __packed;
715
716 struct qlcnic_hostrq_tx_ctx {
717 __le64 host_rsp_dma_addr; /* Response dma'd here */
718 __le64 cmd_cons_dma_addr; /* */
719 __le64 dummy_dma_addr; /* */
720 __le32 capabilities[4]; /* Flag bit vector */
721 __le32 host_int_crb_mode; /* Interrupt crb usage */
722 __le32 rsvd1; /* Padding */
723 __le16 rsvd2; /* Padding */
724 __le16 interrupt_ctl;
725 __le16 msi_index;
726 __le16 rsvd3; /* Padding */
727 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
728 u8 reserved[128]; /* future expansion */
729 } __packed;
730
731 struct qlcnic_cardrsp_cds_ring {
732 __le32 host_producer_crb; /* Crb to use */
733 __le32 interrupt_crb; /* Crb to use */
734 } __packed;
735
736 struct qlcnic_cardrsp_tx_ctx {
737 __le32 host_ctx_state; /* Starting state */
738 __le16 context_id; /* Handle for context */
739 u8 phys_port; /* Physical id of port */
740 u8 virt_port; /* Virtual/Logical id of port */
741 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
742 u8 reserved[128]; /* future expansion */
743 } __packed;
744
745 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
746 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
747
748 /* CRB */
749
750 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
751 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
752 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
753 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
754
755 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
756 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
757 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
758 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
759 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
760
761
762 /* MAC */
763
764 #define MC_COUNT_P3P 38
765
766 #define QLCNIC_MAC_NOOP 0
767 #define QLCNIC_MAC_ADD 1
768 #define QLCNIC_MAC_DEL 2
769 #define QLCNIC_MAC_VLAN_ADD 3
770 #define QLCNIC_MAC_VLAN_DEL 4
771
772 struct qlcnic_mac_list_s {
773 struct list_head list;
774 uint8_t mac_addr[ETH_ALEN+2];
775 };
776
777 /* MAC Learn */
778 #define NO_MAC_LEARN 0
779 #define DRV_MAC_LEARN 1
780 #define FDB_MAC_LEARN 2
781
782 #define QLCNIC_HOST_REQUEST 0x13
783 #define QLCNIC_REQUEST 0x14
784
785 #define QLCNIC_MAC_EVENT 0x1
786
787 #define QLCNIC_IP_UP 2
788 #define QLCNIC_IP_DOWN 3
789
790 #define QLCNIC_ILB_MODE 0x1
791 #define QLCNIC_ELB_MODE 0x2
792
793 #define QLCNIC_LINKEVENT 0x1
794 #define QLCNIC_LB_RESPONSE 0x2
795 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
796 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
797
798 /*
799 * Driver --> Firmware
800 */
801 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
802 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
803 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
804 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
805 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
806 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
807
808 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
809 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
810 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
811 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
812
813 /*
814 * Firmware --> Driver
815 */
816
817 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
818 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D
819 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90
820
821 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
822 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
823 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
824
825 #define QLCNIC_LRO_REQUEST_CLEANUP 4
826
827 /* Capabilites received */
828 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
829 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
830 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
831 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
832 #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4
833 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
834 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31
835
836 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
837 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3
838 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
839 #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7
840
841 /* module types */
842 #define LINKEVENT_MODULE_NOT_PRESENT 1
843 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
844 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
845 #define LINKEVENT_MODULE_OPTICAL_LRM 4
846 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
847 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
848 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
849 #define LINKEVENT_MODULE_TWINAX 8
850
851 #define LINKSPEED_10GBPS 10000
852 #define LINKSPEED_1GBPS 1000
853 #define LINKSPEED_100MBPS 100
854 #define LINKSPEED_10MBPS 10
855
856 #define LINKSPEED_ENCODED_10MBPS 0
857 #define LINKSPEED_ENCODED_100MBPS 1
858 #define LINKSPEED_ENCODED_1GBPS 2
859
860 #define LINKEVENT_AUTONEG_DISABLED 0
861 #define LINKEVENT_AUTONEG_ENABLED 1
862
863 #define LINKEVENT_HALF_DUPLEX 0
864 #define LINKEVENT_FULL_DUPLEX 1
865
866 #define LINKEVENT_LINKSPEED_MBPS 0
867 #define LINKEVENT_LINKSPEED_ENCODED 1
868
869 /* firmware response header:
870 * 63:58 - message type
871 * 57:56 - owner
872 * 55:53 - desc count
873 * 52:48 - reserved
874 * 47:40 - completion id
875 * 39:32 - opcode
876 * 31:16 - error code
877 * 15:00 - reserved
878 */
879 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
880 ((msg_hdr >> 32) & 0xFF)
881
882 struct qlcnic_fw_msg {
883 union {
884 struct {
885 u64 hdr;
886 u64 body[7];
887 };
888 u64 words[8];
889 };
890 };
891
892 struct qlcnic_nic_req {
893 __le64 qhdr;
894 __le64 req_hdr;
895 __le64 words[6];
896 } __packed;
897
898 struct qlcnic_mac_req {
899 u8 op;
900 u8 tag;
901 u8 mac_addr[6];
902 };
903
904 struct qlcnic_vlan_req {
905 __le16 vlan_id;
906 __le16 rsvd[3];
907 } __packed;
908
909 struct qlcnic_ipaddr {
910 __be32 ipv4;
911 __be32 ipv6[4];
912 };
913
914 #define QLCNIC_MSI_ENABLED 0x02
915 #define QLCNIC_MSIX_ENABLED 0x04
916 #define QLCNIC_LRO_ENABLED 0x01
917 #define QLCNIC_LRO_DISABLED 0x00
918 #define QLCNIC_BRIDGE_ENABLED 0X10
919 #define QLCNIC_DIAG_ENABLED 0x20
920 #define QLCNIC_ESWITCH_ENABLED 0x40
921 #define QLCNIC_ADAPTER_INITIALIZED 0x80
922 #define QLCNIC_TAGGING_ENABLED 0x100
923 #define QLCNIC_MACSPOOF 0x200
924 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
925 #define QLCNIC_PROMISC_DISABLED 0x800
926 #define QLCNIC_NEED_FLR 0x1000
927 #define QLCNIC_FW_RESET_OWNER 0x2000
928 #define QLCNIC_FW_HANG 0x4000
929 #define QLCNIC_FW_LRO_MSS_CAP 0x8000
930 #define QLCNIC_TX_INTR_SHARED 0x10000
931 #define QLCNIC_APP_CHANGED_FLAGS 0x20000
932 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000
933
934 #define QLCNIC_IS_MSI_FAMILY(adapter) \
935 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
936 #define QLCNIC_IS_TSO_CAPABLE(adapter) \
937 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
938
939 #define QLCNIC_BEACON_EANBLE 0xC
940 #define QLCNIC_BEACON_DISABLE 0xD
941
942 #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4
943 #define QLCNIC_DEF_NUM_TX_RINGS 4
944 #define QLCNIC_MSIX_TBL_SPACE 8192
945 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
946 #define QLCNIC_MSIX_TBL_PGSIZE 4096
947
948 #define QLCNIC_NETDEV_WEIGHT 128
949 #define QLCNIC_ADAPTER_UP_MAGIC 777
950
951 #define __QLCNIC_FW_ATTACHED 0
952 #define __QLCNIC_DEV_UP 1
953 #define __QLCNIC_RESETTING 2
954 #define __QLCNIC_START_FW 4
955 #define __QLCNIC_AER 5
956 #define __QLCNIC_DIAG_RES_ALLOC 6
957 #define __QLCNIC_LED_ENABLE 7
958 #define __QLCNIC_ELB_INPROGRESS 8
959 #define __QLCNIC_MULTI_TX_UNIQUE 9
960 #define __QLCNIC_SRIOV_ENABLE 10
961 #define __QLCNIC_SRIOV_CAPABLE 11
962 #define __QLCNIC_MBX_POLL_ENABLE 12
963 #define __QLCNIC_DIAG_MODE 13
964 #define __QLCNIC_DCB_STATE 14
965 #define __QLCNIC_DCB_IN_AEN 15
966
967 #define QLCNIC_INTERRUPT_TEST 1
968 #define QLCNIC_LOOPBACK_TEST 2
969 #define QLCNIC_LED_TEST 3
970
971 #define QLCNIC_FILTER_AGE 80
972 #define QLCNIC_READD_AGE 20
973 #define QLCNIC_LB_MAX_FILTERS 64
974 #define QLCNIC_LB_BUCKET_SIZE 32
975 #define QLCNIC_ILB_MAX_RCV_LOOP 10
976
977 struct qlcnic_filter {
978 struct hlist_node fnode;
979 u8 faddr[ETH_ALEN];
980 u16 vlan_id;
981 unsigned long ftime;
982 };
983
984 struct qlcnic_filter_hash {
985 struct hlist_head *fhead;
986 u8 fnum;
987 u16 fmax;
988 u16 fbucket_size;
989 };
990
991 /* Mailbox specific data structures */
992 struct qlcnic_mailbox {
993 struct workqueue_struct *work_q;
994 struct qlcnic_adapter *adapter;
995 struct qlcnic_mbx_ops *ops;
996 struct work_struct work;
997 struct completion completion;
998 struct list_head cmd_q;
999 unsigned long status;
1000 spinlock_t queue_lock; /* Mailbox queue lock */
1001 spinlock_t aen_lock; /* Mailbox response/AEN lock */
1002 atomic_t rsp_status;
1003 u32 num_cmds;
1004 };
1005
1006 struct qlcnic_adapter {
1007 struct qlcnic_hardware_context *ahw;
1008 struct qlcnic_recv_context *recv_ctx;
1009 struct qlcnic_host_tx_ring *tx_ring;
1010 struct net_device *netdev;
1011 struct pci_dev *pdev;
1012
1013 unsigned long state;
1014 u32 flags;
1015
1016 int max_drv_tx_rings;
1017 u16 num_txd;
1018 u16 num_rxd;
1019 u16 num_jumbo_rxd;
1020 u16 max_rxd;
1021 u16 max_jumbo_rxd;
1022
1023 u8 max_rds_rings;
1024 u8 max_sds_rings;
1025 u8 rx_csum;
1026 u8 portnum;
1027
1028 u8 fw_wait_cnt;
1029 u8 fw_fail_cnt;
1030 u8 tx_timeo_cnt;
1031 u8 need_fw_reset;
1032 u8 reset_ctx_cnt;
1033
1034 u16 is_up;
1035 u16 rx_pvid;
1036 u16 tx_pvid;
1037
1038 u32 irq;
1039 u32 heartbeat;
1040
1041 u8 dev_state;
1042 u8 reset_ack_timeo;
1043 u8 dev_init_timeo;
1044
1045 u8 mac_addr[ETH_ALEN];
1046
1047 u64 dev_rst_time;
1048 bool drv_mac_learn;
1049 bool fdb_mac_learn;
1050 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1051 u8 flash_mfg_id;
1052 struct qlcnic_npar_info *npars;
1053 struct qlcnic_eswitch *eswitch;
1054 struct qlcnic_nic_template *nic_ops;
1055
1056 struct qlcnic_adapter_stats stats;
1057 struct list_head mac_list;
1058
1059 void __iomem *tgt_mask_reg;
1060 void __iomem *tgt_status_reg;
1061 void __iomem *crb_int_state_reg;
1062 void __iomem *isr_int_vec;
1063
1064 struct msix_entry *msix_entries;
1065 struct workqueue_struct *qlcnic_wq;
1066 struct delayed_work fw_work;
1067 struct delayed_work idc_aen_work;
1068 struct delayed_work mbx_poll_work;
1069 struct qlcnic_dcb *dcb;
1070
1071 struct qlcnic_filter_hash fhash;
1072 struct qlcnic_filter_hash rx_fhash;
1073 struct list_head vf_mc_list;
1074
1075 spinlock_t tx_clean_lock;
1076 spinlock_t mac_learn_lock;
1077 /* spinlock for catching rcv filters for eswitch traffic */
1078 spinlock_t rx_mac_learn_lock;
1079 u32 file_prd_off; /*File fw product offset*/
1080 u32 fw_version;
1081 u32 offload_flags;
1082 const struct firmware *fw;
1083 };
1084
1085 struct qlcnic_info_le {
1086 __le16 pci_func;
1087 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1088 __le16 phys_port;
1089 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1090
1091 __le32 capabilities;
1092 u8 max_mac_filters;
1093 u8 reserved1;
1094 __le16 max_mtu;
1095
1096 __le16 max_tx_ques;
1097 __le16 max_rx_ques;
1098 __le16 min_tx_bw;
1099 __le16 max_tx_bw;
1100 __le32 op_type;
1101 __le16 max_bw_reg_offset;
1102 __le16 max_linkspeed_reg_offset;
1103 __le32 capability1;
1104 __le32 capability2;
1105 __le32 capability3;
1106 __le16 max_tx_mac_filters;
1107 __le16 max_rx_mcast_mac_filters;
1108 __le16 max_rx_ucast_mac_filters;
1109 __le16 max_rx_ip_addr;
1110 __le16 max_rx_lro_flow;
1111 __le16 max_rx_status_rings;
1112 __le16 max_rx_buf_rings;
1113 __le16 max_tx_vlan_keys;
1114 u8 total_pf;
1115 u8 total_rss_engines;
1116 __le16 max_vports;
1117 __le16 linkstate_reg_offset;
1118 __le16 bit_offsets;
1119 __le16 max_local_ipv6_addrs;
1120 __le16 max_remote_ipv6_addrs;
1121 u8 reserved2[56];
1122 } __packed;
1123
1124 struct qlcnic_info {
1125 u16 pci_func;
1126 u16 op_mode;
1127 u16 phys_port;
1128 u16 switch_mode;
1129 u32 capabilities;
1130 u8 max_mac_filters;
1131 u16 max_mtu;
1132 u16 max_tx_ques;
1133 u16 max_rx_ques;
1134 u16 min_tx_bw;
1135 u16 max_tx_bw;
1136 u32 op_type;
1137 u16 max_bw_reg_offset;
1138 u16 max_linkspeed_reg_offset;
1139 u32 capability1;
1140 u32 capability2;
1141 u32 capability3;
1142 u16 max_tx_mac_filters;
1143 u16 max_rx_mcast_mac_filters;
1144 u16 max_rx_ucast_mac_filters;
1145 u16 max_rx_ip_addr;
1146 u16 max_rx_lro_flow;
1147 u16 max_rx_status_rings;
1148 u16 max_rx_buf_rings;
1149 u16 max_tx_vlan_keys;
1150 u8 total_pf;
1151 u8 total_rss_engines;
1152 u16 max_vports;
1153 u16 linkstate_reg_offset;
1154 u16 bit_offsets;
1155 u16 max_local_ipv6_addrs;
1156 u16 max_remote_ipv6_addrs;
1157 };
1158
1159 struct qlcnic_pci_info_le {
1160 __le16 id; /* pci function id */
1161 __le16 active; /* 1 = Enabled */
1162 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1163 __le16 default_port; /* default port number */
1164
1165 __le16 tx_min_bw; /* Multiple of 100mbpc */
1166 __le16 tx_max_bw;
1167 __le16 reserved1[2];
1168
1169 u8 mac[ETH_ALEN];
1170 __le16 func_count;
1171 u8 reserved2[104];
1172
1173 } __packed;
1174
1175 struct qlcnic_pci_info {
1176 u16 id;
1177 u16 active;
1178 u16 type;
1179 u16 default_port;
1180 u16 tx_min_bw;
1181 u16 tx_max_bw;
1182 u8 mac[ETH_ALEN];
1183 u16 func_count;
1184 };
1185
1186 struct qlcnic_npar_info {
1187 u16 pvid;
1188 u16 min_bw;
1189 u16 max_bw;
1190 u8 phy_port;
1191 u8 type;
1192 u8 active;
1193 u8 enable_pm;
1194 u8 dest_npar;
1195 u8 discard_tagged;
1196 u8 mac_override;
1197 u8 mac_anti_spoof;
1198 u8 promisc_mode;
1199 u8 offload_flags;
1200 u8 pci_func;
1201 };
1202
1203 struct qlcnic_eswitch {
1204 u8 port;
1205 u8 active_vports;
1206 u8 active_vlans;
1207 u8 active_ucast_filters;
1208 u8 max_ucast_filters;
1209 u8 max_active_vlans;
1210
1211 u32 flags;
1212 #define QLCNIC_SWITCH_ENABLE BIT_1
1213 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1214 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1215 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1216 };
1217
1218
1219 /* Return codes for Error handling */
1220 #define QL_STATUS_INVALID_PARAM -1
1221
1222 #define MAX_BW 100 /* % of link speed */
1223 #define MAX_VLAN_ID 4095
1224 #define MIN_VLAN_ID 2
1225 #define DEFAULT_MAC_LEARN 1
1226
1227 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1228 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1229
1230 struct qlcnic_pci_func_cfg {
1231 u16 func_type;
1232 u16 min_bw;
1233 u16 max_bw;
1234 u16 port_num;
1235 u8 pci_func;
1236 u8 func_state;
1237 u8 def_mac_addr[6];
1238 };
1239
1240 struct qlcnic_npar_func_cfg {
1241 u32 fw_capab;
1242 u16 port_num;
1243 u16 min_bw;
1244 u16 max_bw;
1245 u16 max_tx_queues;
1246 u16 max_rx_queues;
1247 u8 pci_func;
1248 u8 op_mode;
1249 };
1250
1251 struct qlcnic_pm_func_cfg {
1252 u8 pci_func;
1253 u8 action;
1254 u8 dest_npar;
1255 u8 reserved[5];
1256 };
1257
1258 struct qlcnic_esw_func_cfg {
1259 u16 vlan_id;
1260 u8 op_mode;
1261 u8 op_type;
1262 u8 pci_func;
1263 u8 host_vlan_tag;
1264 u8 promisc_mode;
1265 u8 discard_tagged;
1266 u8 mac_override;
1267 u8 mac_anti_spoof;
1268 u8 offload_flags;
1269 u8 reserved[5];
1270 };
1271
1272 #define QLCNIC_STATS_VERSION 1
1273 #define QLCNIC_STATS_PORT 1
1274 #define QLCNIC_STATS_ESWITCH 2
1275 #define QLCNIC_QUERY_RX_COUNTER 0
1276 #define QLCNIC_QUERY_TX_COUNTER 1
1277 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1278 #define QLCNIC_FILL_STATS(VAL1) \
1279 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1280 #define QLCNIC_MAC_STATS 1
1281 #define QLCNIC_ESW_STATS 2
1282
1283 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1284 do { \
1285 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1286 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1287 (VAL1) = (VAL2); \
1288 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1289 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1290 (VAL1) += (VAL2); \
1291 } while (0)
1292
1293 struct qlcnic_mac_statistics_le {
1294 __le64 mac_tx_frames;
1295 __le64 mac_tx_bytes;
1296 __le64 mac_tx_mcast_pkts;
1297 __le64 mac_tx_bcast_pkts;
1298 __le64 mac_tx_pause_cnt;
1299 __le64 mac_tx_ctrl_pkt;
1300 __le64 mac_tx_lt_64b_pkts;
1301 __le64 mac_tx_lt_127b_pkts;
1302 __le64 mac_tx_lt_255b_pkts;
1303 __le64 mac_tx_lt_511b_pkts;
1304 __le64 mac_tx_lt_1023b_pkts;
1305 __le64 mac_tx_lt_1518b_pkts;
1306 __le64 mac_tx_gt_1518b_pkts;
1307 __le64 rsvd1[3];
1308
1309 __le64 mac_rx_frames;
1310 __le64 mac_rx_bytes;
1311 __le64 mac_rx_mcast_pkts;
1312 __le64 mac_rx_bcast_pkts;
1313 __le64 mac_rx_pause_cnt;
1314 __le64 mac_rx_ctrl_pkt;
1315 __le64 mac_rx_lt_64b_pkts;
1316 __le64 mac_rx_lt_127b_pkts;
1317 __le64 mac_rx_lt_255b_pkts;
1318 __le64 mac_rx_lt_511b_pkts;
1319 __le64 mac_rx_lt_1023b_pkts;
1320 __le64 mac_rx_lt_1518b_pkts;
1321 __le64 mac_rx_gt_1518b_pkts;
1322 __le64 rsvd2[3];
1323
1324 __le64 mac_rx_length_error;
1325 __le64 mac_rx_length_small;
1326 __le64 mac_rx_length_large;
1327 __le64 mac_rx_jabber;
1328 __le64 mac_rx_dropped;
1329 __le64 mac_rx_crc_error;
1330 __le64 mac_align_error;
1331 } __packed;
1332
1333 struct qlcnic_mac_statistics {
1334 u64 mac_tx_frames;
1335 u64 mac_tx_bytes;
1336 u64 mac_tx_mcast_pkts;
1337 u64 mac_tx_bcast_pkts;
1338 u64 mac_tx_pause_cnt;
1339 u64 mac_tx_ctrl_pkt;
1340 u64 mac_tx_lt_64b_pkts;
1341 u64 mac_tx_lt_127b_pkts;
1342 u64 mac_tx_lt_255b_pkts;
1343 u64 mac_tx_lt_511b_pkts;
1344 u64 mac_tx_lt_1023b_pkts;
1345 u64 mac_tx_lt_1518b_pkts;
1346 u64 mac_tx_gt_1518b_pkts;
1347 u64 rsvd1[3];
1348 u64 mac_rx_frames;
1349 u64 mac_rx_bytes;
1350 u64 mac_rx_mcast_pkts;
1351 u64 mac_rx_bcast_pkts;
1352 u64 mac_rx_pause_cnt;
1353 u64 mac_rx_ctrl_pkt;
1354 u64 mac_rx_lt_64b_pkts;
1355 u64 mac_rx_lt_127b_pkts;
1356 u64 mac_rx_lt_255b_pkts;
1357 u64 mac_rx_lt_511b_pkts;
1358 u64 mac_rx_lt_1023b_pkts;
1359 u64 mac_rx_lt_1518b_pkts;
1360 u64 mac_rx_gt_1518b_pkts;
1361 u64 rsvd2[3];
1362 u64 mac_rx_length_error;
1363 u64 mac_rx_length_small;
1364 u64 mac_rx_length_large;
1365 u64 mac_rx_jabber;
1366 u64 mac_rx_dropped;
1367 u64 mac_rx_crc_error;
1368 u64 mac_align_error;
1369 };
1370
1371 struct qlcnic_esw_stats_le {
1372 __le16 context_id;
1373 __le16 version;
1374 __le16 size;
1375 __le16 unused;
1376 __le64 unicast_frames;
1377 __le64 multicast_frames;
1378 __le64 broadcast_frames;
1379 __le64 dropped_frames;
1380 __le64 errors;
1381 __le64 local_frames;
1382 __le64 numbytes;
1383 __le64 rsvd[3];
1384 } __packed;
1385
1386 struct __qlcnic_esw_statistics {
1387 u16 context_id;
1388 u16 version;
1389 u16 size;
1390 u16 unused;
1391 u64 unicast_frames;
1392 u64 multicast_frames;
1393 u64 broadcast_frames;
1394 u64 dropped_frames;
1395 u64 errors;
1396 u64 local_frames;
1397 u64 numbytes;
1398 u64 rsvd[3];
1399 };
1400
1401 struct qlcnic_esw_statistics {
1402 struct __qlcnic_esw_statistics rx;
1403 struct __qlcnic_esw_statistics tx;
1404 };
1405
1406 #define QLCNIC_DUMP_MASK_DEF 0x1f
1407 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1408 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1409 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1410 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1411 #define QLCNIC_SET_QUIESCENT 0xadd00010
1412 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1413
1414 struct _cdrp_cmd {
1415 u32 num;
1416 u32 *arg;
1417 };
1418
1419 struct qlcnic_cmd_args {
1420 struct completion completion;
1421 struct list_head list;
1422 struct _cdrp_cmd req;
1423 struct _cdrp_cmd rsp;
1424 atomic_t rsp_status;
1425 int pay_size;
1426 u32 rsp_opcode;
1427 u32 total_cmds;
1428 u32 op_type;
1429 u32 type;
1430 u32 cmd_op;
1431 u32 *hdr; /* Back channel message header */
1432 u32 *pay; /* Back channel message payload */
1433 u8 func_num;
1434 };
1435
1436 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1437 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1438 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1439 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1440 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1441 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1442
1443 #define ADDR_IN_RANGE(addr, low, high) \
1444 (((addr) < (high)) && ((addr) >= (low)))
1445
1446 #define QLCRD32(adapter, off, err) \
1447 (adapter->ahw->hw_ops->read_reg)(adapter, off, err)
1448
1449 #define QLCWR32(adapter, off, val) \
1450 adapter->ahw->hw_ops->write_reg(adapter, off, val)
1451
1452 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1453 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1454
1455 #define qlcnic_rom_lock(a) \
1456 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1457 #define qlcnic_rom_unlock(a) \
1458 qlcnic_pcie_sem_unlock((a), 2)
1459 #define qlcnic_phy_lock(a) \
1460 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1461 #define qlcnic_phy_unlock(a) \
1462 qlcnic_pcie_sem_unlock((a), 3)
1463 #define qlcnic_sw_lock(a) \
1464 qlcnic_pcie_sem_lock((a), 6, 0)
1465 #define qlcnic_sw_unlock(a) \
1466 qlcnic_pcie_sem_unlock((a), 6)
1467 #define crb_win_lock(a) \
1468 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1469 #define crb_win_unlock(a) \
1470 qlcnic_pcie_sem_unlock((a), 7)
1471
1472 #define __QLCNIC_MAX_LED_RATE 0xf
1473 #define __QLCNIC_MAX_LED_STATE 0x2
1474
1475 #define MAX_CTL_CHECK 1000
1476
1477 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1478 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1479 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1480 int qlcnic_dump_fw(struct qlcnic_adapter *);
1481
1482 /* Functions from qlcnic_init.c */
1483 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int);
1484 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1485 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1486 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1487 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1488 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1489 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1490 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1491
1492 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1493 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1494 u8 *bytes, size_t size);
1495 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1496 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1497
1498 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32);
1499
1500 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1501 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1502
1503 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1504 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1505
1506 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1507 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1508 void qlcnic_release_tx_buffers(struct qlcnic_adapter *,
1509 struct qlcnic_host_tx_ring *);
1510
1511 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1512 void qlcnic_watchdog_task(struct work_struct *work);
1513 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1514 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id);
1515 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1516 void qlcnic_set_multi(struct net_device *netdev);
1517 void __qlcnic_set_multi(struct net_device *, u16);
1518 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16);
1519 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *);
1520 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter);
1521 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *);
1522
1523 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1524 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32);
1525 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1526 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1527 netdev_features_t features);
1528 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1529 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1530 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1531 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *);
1532
1533 /* Functions from qlcnic_ethtool.c */
1534 int qlcnic_check_loopback_buff(unsigned char *, u8 []);
1535 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8);
1536 int qlcnic_loopback_test(struct net_device *, u8);
1537
1538 /* Functions from qlcnic_main.c */
1539 int qlcnic_reset_context(struct qlcnic_adapter *);
1540 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1541 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1542 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1543 int qlcnic_set_max_rss(struct qlcnic_adapter *, u8, int);
1544 int qlcnic_validate_max_rss(struct qlcnic_adapter *, __u32);
1545 int qlcnic_validate_max_tx_rings(struct qlcnic_adapter *, int);
1546 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1547 void qlcnic_82xx_set_mac_filter_count(struct qlcnic_adapter *);
1548 int qlcnic_enable_msix(struct qlcnic_adapter *, u32);
1549 void qlcnic_set_drv_version(struct qlcnic_adapter *);
1550
1551 /* eSwitch management functions */
1552 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1553 struct qlcnic_esw_func_cfg *);
1554
1555 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1556 struct qlcnic_esw_func_cfg *);
1557 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1558 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1559 struct __qlcnic_esw_statistics *);
1560 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1561 struct __qlcnic_esw_statistics *);
1562 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1563 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1564
1565 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd);
1566
1567 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);
1568 void qlcnic_free_sds_rings(struct qlcnic_recv_context *);
1569 void qlcnic_advert_link_change(struct qlcnic_adapter *, int);
1570 void qlcnic_free_tx_rings(struct qlcnic_adapter *);
1571 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);
1572 void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1573
1574 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
1575 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
1576 void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter);
1577 void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter);
1578 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter);
1579 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter);
1580 int qlcnic_82xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *);
1581
1582 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
1583 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
1584 void qlcnic_set_vlan_config(struct qlcnic_adapter *,
1585 struct qlcnic_esw_func_cfg *);
1586 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *,
1587 struct qlcnic_esw_func_cfg *);
1588
1589 void qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1590 int qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1591 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1592 void qlcnic_detach(struct qlcnic_adapter *);
1593 void qlcnic_teardown_intr(struct qlcnic_adapter *);
1594 int qlcnic_attach(struct qlcnic_adapter *);
1595 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1596 void qlcnic_restore_indev_addr(struct net_device *, unsigned long);
1597
1598 int qlcnic_check_temp(struct qlcnic_adapter *);
1599 int qlcnic_init_pci_info(struct qlcnic_adapter *);
1600 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *);
1601 int qlcnic_reset_npar_config(struct qlcnic_adapter *);
1602 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *);
1603 void qlcnic_add_lb_filter(struct qlcnic_adapter *, struct sk_buff *, int, u16);
1604 int qlcnic_get_beacon_state(struct qlcnic_adapter *, u8 *);
1605 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
1606 int qlcnic_read_mac_addr(struct qlcnic_adapter *);
1607 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int);
1608 void qlcnic_set_netdev_features(struct qlcnic_adapter *,
1609 struct qlcnic_esw_func_cfg *);
1610 void qlcnic_sriov_vf_schedule_multi(struct net_device *);
1611 void qlcnic_vf_add_mc_list(struct net_device *, u16);
1612
1613 /*
1614 * QLOGIC Board information
1615 */
1616
1617 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1618 struct qlcnic_board_info {
1619 unsigned short vendor;
1620 unsigned short device;
1621 unsigned short sub_vendor;
1622 unsigned short sub_device;
1623 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1624 };
1625
1626 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1627 {
1628 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1629 return tx_ring->sw_consumer - tx_ring->producer;
1630 else
1631 return tx_ring->sw_consumer + tx_ring->num_desc -
1632 tx_ring->producer;
1633 }
1634
1635 static inline int qlcnic_set_real_num_queues(struct qlcnic_adapter *adapter,
1636 struct net_device *netdev)
1637 {
1638 int err, tx_q;
1639
1640 tx_q = adapter->max_drv_tx_rings;
1641
1642 netdev->num_tx_queues = tx_q;
1643 netdev->real_num_tx_queues = tx_q;
1644
1645 err = netif_set_real_num_tx_queues(netdev, tx_q);
1646 if (err)
1647 dev_err(&adapter->pdev->dev, "failed to set %d Tx queues\n",
1648 tx_q);
1649 else
1650 dev_info(&adapter->pdev->dev, "set %d Tx queues\n", tx_q);
1651
1652 return err;
1653 }
1654
1655 struct qlcnic_nic_template {
1656 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1657 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1658 int (*start_firmware) (struct qlcnic_adapter *);
1659 int (*init_driver) (struct qlcnic_adapter *);
1660 void (*request_reset) (struct qlcnic_adapter *, u32);
1661 void (*cancel_idc_work) (struct qlcnic_adapter *);
1662 int (*napi_add)(struct qlcnic_adapter *, struct net_device *);
1663 void (*napi_del)(struct qlcnic_adapter *);
1664 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int);
1665 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *);
1666 int (*shutdown)(struct pci_dev *);
1667 int (*resume)(struct qlcnic_adapter *);
1668 };
1669
1670 struct qlcnic_mbx_ops {
1671 int (*enqueue_cmd) (struct qlcnic_adapter *,
1672 struct qlcnic_cmd_args *, unsigned long *);
1673 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1674 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1675 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1676 void (*nofity_fw) (struct qlcnic_adapter *, u8);
1677 };
1678
1679 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *);
1680 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *);
1681 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx);
1682 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx);
1683
1684 /* Adapter hardware abstraction */
1685 struct qlcnic_hardware_ops {
1686 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1687 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1688 int (*read_reg) (struct qlcnic_adapter *, ulong, int *);
1689 int (*write_reg) (struct qlcnic_adapter *, ulong, u32);
1690 void (*get_ocm_win) (struct qlcnic_hardware_context *);
1691 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8);
1692 int (*setup_intr) (struct qlcnic_adapter *, u8, int);
1693 int (*alloc_mbx_args)(struct qlcnic_cmd_args *,
1694 struct qlcnic_adapter *, u32);
1695 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1696 void (*get_func_no) (struct qlcnic_adapter *);
1697 int (*api_lock) (struct qlcnic_adapter *);
1698 void (*api_unlock) (struct qlcnic_adapter *);
1699 void (*add_sysfs) (struct qlcnic_adapter *);
1700 void (*remove_sysfs) (struct qlcnic_adapter *);
1701 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *);
1702 int (*create_rx_ctx) (struct qlcnic_adapter *);
1703 int (*create_tx_ctx) (struct qlcnic_adapter *,
1704 struct qlcnic_host_tx_ring *, int);
1705 void (*del_rx_ctx) (struct qlcnic_adapter *);
1706 void (*del_tx_ctx) (struct qlcnic_adapter *,
1707 struct qlcnic_host_tx_ring *);
1708 int (*setup_link_event) (struct qlcnic_adapter *, int);
1709 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8);
1710 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *);
1711 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *);
1712 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8);
1713 void (*napi_enable) (struct qlcnic_adapter *);
1714 void (*napi_disable) (struct qlcnic_adapter *);
1715 void (*config_intr_coal) (struct qlcnic_adapter *);
1716 int (*config_rss) (struct qlcnic_adapter *, int);
1717 int (*config_hw_lro) (struct qlcnic_adapter *, int);
1718 int (*config_loopback) (struct qlcnic_adapter *, u8);
1719 int (*clear_loopback) (struct qlcnic_adapter *, u8);
1720 int (*config_promisc_mode) (struct qlcnic_adapter *, u32);
1721 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16);
1722 int (*get_board_info) (struct qlcnic_adapter *);
1723 void (*set_mac_filter_count) (struct qlcnic_adapter *);
1724 void (*free_mac_list) (struct qlcnic_adapter *);
1725 int (*read_phys_port_id) (struct qlcnic_adapter *);
1726 };
1727
1728 extern struct qlcnic_nic_template qlcnic_vf_ops;
1729
1730 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter)
1731 {
1732 return adapter->nic_ops->start_firmware(adapter);
1733 }
1734
1735 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf,
1736 loff_t offset, size_t size)
1737 {
1738 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size);
1739 }
1740
1741 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf,
1742 loff_t offset, size_t size)
1743 {
1744 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size);
1745 }
1746
1747 static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter,
1748 ulong off, u32 data)
1749 {
1750 return adapter->ahw->hw_ops->write_reg(adapter, off, data);
1751 }
1752
1753 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter,
1754 u8 *mac, u8 function)
1755 {
1756 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function);
1757 }
1758
1759 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter,
1760 u8 num_intr, int txq)
1761 {
1762 return adapter->ahw->hw_ops->setup_intr(adapter, num_intr, txq);
1763 }
1764
1765 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
1766 struct qlcnic_adapter *adapter, u32 arg)
1767 {
1768 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg);
1769 }
1770
1771 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1772 struct qlcnic_cmd_args *cmd)
1773 {
1774 if (adapter->ahw->hw_ops->mbx_cmd)
1775 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd);
1776
1777 return -EIO;
1778 }
1779
1780 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter)
1781 {
1782 adapter->ahw->hw_ops->get_func_no(adapter);
1783 }
1784
1785 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter)
1786 {
1787 return adapter->ahw->hw_ops->api_lock(adapter);
1788 }
1789
1790 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter)
1791 {
1792 adapter->ahw->hw_ops->api_unlock(adapter);
1793 }
1794
1795 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter)
1796 {
1797 if (adapter->ahw->hw_ops->add_sysfs)
1798 adapter->ahw->hw_ops->add_sysfs(adapter);
1799 }
1800
1801 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter)
1802 {
1803 if (adapter->ahw->hw_ops->remove_sysfs)
1804 adapter->ahw->hw_ops->remove_sysfs(adapter);
1805 }
1806
1807 static inline void
1808 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
1809 {
1810 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring);
1811 }
1812
1813 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
1814 {
1815 return adapter->ahw->hw_ops->create_rx_ctx(adapter);
1816 }
1817
1818 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
1819 struct qlcnic_host_tx_ring *ptr,
1820 int ring)
1821 {
1822 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring);
1823 }
1824
1825 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
1826 {
1827 return adapter->ahw->hw_ops->del_rx_ctx(adapter);
1828 }
1829
1830 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
1831 struct qlcnic_host_tx_ring *ptr)
1832 {
1833 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr);
1834 }
1835
1836 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter,
1837 int enable)
1838 {
1839 return adapter->ahw->hw_ops->setup_link_event(adapter, enable);
1840 }
1841
1842 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter,
1843 struct qlcnic_info *info, u8 id)
1844 {
1845 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id);
1846 }
1847
1848 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter,
1849 struct qlcnic_pci_info *info)
1850 {
1851 return adapter->ahw->hw_ops->get_pci_info(adapter, info);
1852 }
1853
1854 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter,
1855 struct qlcnic_info *info)
1856 {
1857 return adapter->ahw->hw_ops->set_nic_info(adapter, info);
1858 }
1859
1860 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter,
1861 u8 *addr, u16 id, u8 cmd)
1862 {
1863 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd);
1864 }
1865
1866 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter,
1867 struct net_device *netdev)
1868 {
1869 return adapter->nic_ops->napi_add(adapter, netdev);
1870 }
1871
1872 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter)
1873 {
1874 adapter->nic_ops->napi_del(adapter);
1875 }
1876
1877 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter)
1878 {
1879 adapter->ahw->hw_ops->napi_enable(adapter);
1880 }
1881
1882 static inline int __qlcnic_shutdown(struct pci_dev *pdev)
1883 {
1884 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1885
1886 return adapter->nic_ops->shutdown(pdev);
1887 }
1888
1889 static inline int __qlcnic_resume(struct qlcnic_adapter *adapter)
1890 {
1891 return adapter->nic_ops->resume(adapter);
1892 }
1893
1894 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter)
1895 {
1896 adapter->ahw->hw_ops->napi_disable(adapter);
1897 }
1898
1899 static inline void qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
1900 {
1901 adapter->ahw->hw_ops->config_intr_coal(adapter);
1902 }
1903
1904 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
1905 {
1906 return adapter->ahw->hw_ops->config_rss(adapter, enable);
1907 }
1908
1909 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter,
1910 int enable)
1911 {
1912 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable);
1913 }
1914
1915 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1916 {
1917 return adapter->ahw->hw_ops->config_loopback(adapter, mode);
1918 }
1919
1920 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1921 {
1922 return adapter->ahw->hw_ops->clear_loopback(adapter, mode);
1923 }
1924
1925 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter,
1926 u32 mode)
1927 {
1928 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode);
1929 }
1930
1931 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter,
1932 u64 *addr, u16 id)
1933 {
1934 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id);
1935 }
1936
1937 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1938 {
1939 return adapter->ahw->hw_ops->get_board_info(adapter);
1940 }
1941
1942 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
1943 {
1944 return adapter->ahw->hw_ops->free_mac_list(adapter);
1945 }
1946
1947 static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter)
1948 {
1949 if (adapter->ahw->hw_ops->set_mac_filter_count)
1950 adapter->ahw->hw_ops->set_mac_filter_count(adapter);
1951 }
1952
1953 static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter)
1954 {
1955 if (adapter->ahw->hw_ops->read_phys_port_id)
1956 adapter->ahw->hw_ops->read_phys_port_id(adapter);
1957 }
1958
1959 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter,
1960 u32 key)
1961 {
1962 if (adapter->nic_ops->request_reset)
1963 adapter->nic_ops->request_reset(adapter, key);
1964 }
1965
1966 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter)
1967 {
1968 if (adapter->nic_ops->cancel_idc_work)
1969 adapter->nic_ops->cancel_idc_work(adapter);
1970 }
1971
1972 static inline irqreturn_t
1973 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter)
1974 {
1975 return adapter->nic_ops->clear_legacy_intr(adapter);
1976 }
1977
1978 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state,
1979 u32 rate)
1980 {
1981 return adapter->nic_ops->config_led(adapter, state, rate);
1982 }
1983
1984 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter,
1985 __be32 ip, int cmd)
1986 {
1987 adapter->nic_ops->config_ipaddr(adapter, ip, cmd);
1988 }
1989
1990 static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter)
1991 {
1992 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
1993 }
1994
1995 static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter)
1996 {
1997 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
1998 adapter->max_drv_tx_rings = 1;
1999 }
2000
2001 /* When operating in a muti tx mode, driver needs to write 0x1
2002 * to src register, instead of 0x0 to disable receiving interrupt.
2003 */
2004 static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring)
2005 {
2006 struct qlcnic_adapter *adapter = sds_ring->adapter;
2007
2008 if (qlcnic_check_multi_tx(adapter) &&
2009 !adapter->ahw->diag_test &&
2010 (adapter->flags & QLCNIC_MSIX_ENABLED))
2011 writel(0x1, sds_ring->crb_intr_mask);
2012 else
2013 writel(0, sds_ring->crb_intr_mask);
2014 }
2015
2016 /* When operating in a muti tx mode, driver needs to write 0x0
2017 * to src register, instead of 0x1 to enable receiving interrupts.
2018 */
2019 static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring)
2020 {
2021 struct qlcnic_adapter *adapter = sds_ring->adapter;
2022
2023 if (qlcnic_check_multi_tx(adapter) &&
2024 !adapter->ahw->diag_test &&
2025 (adapter->flags & QLCNIC_MSIX_ENABLED))
2026 writel(0, sds_ring->crb_intr_mask);
2027 else
2028 writel(0x1, sds_ring->crb_intr_mask);
2029
2030 if (!QLCNIC_IS_MSI_FAMILY(adapter))
2031 writel(0xfbff, adapter->tgt_mask_reg);
2032 }
2033
2034 static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter)
2035 {
2036 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2037 }
2038
2039 static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter)
2040 {
2041 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2042 }
2043
2044 static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter)
2045 {
2046 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2047 }
2048
2049 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops;
2050 extern const struct ethtool_ops qlcnic_ethtool_ops;
2051 extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
2052
2053 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
2054 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \
2055 printk(KERN_INFO "%s: %s: " _fmt, \
2056 dev_name(&adapter->pdev->dev), \
2057 __func__, ##_args); \
2058 } while (0)
2059
2060 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020
2061 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030
2062 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430
2063 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040
2064 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440
2065
2066 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter)
2067 {
2068 unsigned short device = adapter->pdev->device;
2069 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false;
2070 }
2071
2072 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter)
2073 {
2074 unsigned short device = adapter->pdev->device;
2075 bool status;
2076
2077 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) ||
2078 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2079 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) ||
2080 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false;
2081
2082 return status;
2083 }
2084
2085 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter)
2086 {
2087 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false;
2088 }
2089
2090 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter)
2091 {
2092 unsigned short device = adapter->pdev->device;
2093 bool status;
2094
2095 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2096 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2097
2098 return status;
2099 }
2100
2101 static inline int qlcnic_dcb_get_hw_capability(struct qlcnic_adapter *adapter)
2102 {
2103 struct qlcnic_dcb *dcb = adapter->dcb;
2104
2105 if (dcb && dcb->ops->get_hw_capability)
2106 return dcb->ops->get_hw_capability(adapter);
2107
2108 return 0;
2109 }
2110
2111 static inline void qlcnic_dcb_free(struct qlcnic_adapter *adapter)
2112 {
2113 struct qlcnic_dcb *dcb = adapter->dcb;
2114
2115 if (dcb && dcb->ops->free)
2116 dcb->ops->free(adapter);
2117 }
2118
2119 static inline int qlcnic_dcb_attach(struct qlcnic_adapter *adapter)
2120 {
2121 struct qlcnic_dcb *dcb = adapter->dcb;
2122
2123 if (dcb && dcb->ops->attach)
2124 return dcb->ops->attach(adapter);
2125
2126 return 0;
2127 }
2128
2129 static inline int
2130 qlcnic_dcb_query_hw_capability(struct qlcnic_adapter *adapter, char *buf)
2131 {
2132 struct qlcnic_dcb *dcb = adapter->dcb;
2133
2134 if (dcb && dcb->ops->query_hw_capability)
2135 return dcb->ops->query_hw_capability(adapter, buf);
2136
2137 return 0;
2138 }
2139
2140 static inline void qlcnic_dcb_get_info(struct qlcnic_adapter *adapter)
2141 {
2142 struct qlcnic_dcb *dcb = adapter->dcb;
2143
2144 if (dcb && dcb->ops->get_info)
2145 dcb->ops->get_info(adapter);
2146 }
2147
2148 static inline int
2149 qlcnic_dcb_query_cee_param(struct qlcnic_adapter *adapter, char *buf, u8 type)
2150 {
2151 struct qlcnic_dcb *dcb = adapter->dcb;
2152
2153 if (dcb && dcb->ops->query_cee_param)
2154 return dcb->ops->query_cee_param(adapter, buf, type);
2155
2156 return 0;
2157 }
2158
2159 static inline int qlcnic_dcb_get_cee_cfg(struct qlcnic_adapter *adapter)
2160 {
2161 struct qlcnic_dcb *dcb = adapter->dcb;
2162
2163 if (dcb && dcb->ops->get_cee_cfg)
2164 return dcb->ops->get_cee_cfg(adapter);
2165
2166 return 0;
2167 }
2168
2169 static inline void
2170 qlcnic_dcb_register_aen(struct qlcnic_adapter *adapter, u8 flag)
2171 {
2172 struct qlcnic_dcb *dcb = adapter->dcb;
2173
2174 if (dcb && dcb->ops->register_aen)
2175 dcb->ops->register_aen(adapter, flag);
2176 }
2177
2178 static inline void qlcnic_dcb_handle_aen(struct qlcnic_adapter *adapter,
2179 void *msg)
2180 {
2181 struct qlcnic_dcb *dcb = adapter->dcb;
2182
2183 if (dcb && dcb->ops->handle_aen)
2184 dcb->ops->handle_aen(adapter, msg);
2185 }
2186
2187 static inline void qlcnic_dcb_init_dcbnl_ops(struct qlcnic_adapter *adapter)
2188 {
2189 struct qlcnic_dcb *dcb = adapter->dcb;
2190
2191 if (dcb && dcb->ops->init_dcbnl_ops)
2192 dcb->ops->init_dcbnl_ops(adapter);
2193 }
2194 #endif /* __QLCNIC_H_ */
Linux kernel - Deliverables
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