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iommu/exynos: Fix checkpatch warning
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic.h
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23 #include <linux/ethtool.h>
24 #include <linux/mii.h>
25 #include <linux/timer.h>
26 #include <linux/irq.h>
27
28 #include <linux/vmalloc.h>
29
30 #include <linux/io.h>
31 #include <asm/byteorder.h>
32 #include <linux/bitops.h>
33 #include <linux/if_vlan.h>
34
35 #include "qlcnic_hdr.h"
36 #include "qlcnic_hw.h"
37 #include "qlcnic_83xx_hw.h"
38 #include "qlcnic_dcb.h"
39
40 #define _QLCNIC_LINUX_MAJOR 5
41 #define _QLCNIC_LINUX_MINOR 3
42 #define _QLCNIC_LINUX_SUBVERSION 57
43 #define QLCNIC_LINUX_VERSIONID "5.3.57"
44 #define QLCNIC_DRV_IDC_VER 0x01
45 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
46 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
47
48 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
49 #define _major(v) (((v) >> 24) & 0xff)
50 #define _minor(v) (((v) >> 16) & 0xff)
51 #define _build(v) ((v) & 0xffff)
52
53 /* version in image has weird encoding:
54 * 7:0 - major
55 * 15:8 - minor
56 * 31:16 - build (little endian)
57 */
58 #define QLCNIC_DECODE_VERSION(v) \
59 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
60
61 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
62 #define QLCNIC_NUM_FLASH_SECTORS (64)
63 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
64 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
65 * QLCNIC_FLASH_SECTOR_SIZE)
66
67 #define RCV_DESC_RINGSIZE(rds_ring) \
68 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
69 #define RCV_BUFF_RINGSIZE(rds_ring) \
70 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
71 #define STATUS_DESC_RINGSIZE(sds_ring) \
72 (sizeof(struct status_desc) * (sds_ring)->num_desc)
73 #define TX_BUFF_RINGSIZE(tx_ring) \
74 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
75 #define TX_DESC_RINGSIZE(tx_ring) \
76 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
77
78 #define QLCNIC_P3P_A0 0x50
79 #define QLCNIC_P3P_C0 0x58
80
81 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
82
83 #define FIRST_PAGE_GROUP_START 0
84 #define FIRST_PAGE_GROUP_END 0x100000
85
86 #define P3P_MAX_MTU (9600)
87 #define P3P_MIN_MTU (68)
88 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
89
90 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
91 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
92 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
93 #define QLCNIC_LRO_BUFFER_EXTRA 2048
94
95 /* Tx defines */
96 #define QLCNIC_MAX_FRAGS_PER_TX 14
97 #define MAX_TSO_HEADER_DESC 2
98 #define MGMT_CMD_DESC_RESV 4
99 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
100 + MGMT_CMD_DESC_RESV)
101 #define QLCNIC_MAX_TX_TIMEOUTS 2
102
103 /* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */
104 #define QLCNIC_SINGLE_RING 1
105 #define QLCNIC_DEF_SDS_RINGS 4
106 #define QLCNIC_DEF_TX_RINGS 4
107 #define QLCNIC_MAX_VNIC_TX_RINGS 4
108 #define QLCNIC_MAX_VNIC_SDS_RINGS 4
109 #define QLCNIC_83XX_MINIMUM_VECTOR 3
110 #define QLCNIC_82XX_MINIMUM_VECTOR 2
111
112 enum qlcnic_queue_type {
113 QLCNIC_TX_QUEUE = 1,
114 QLCNIC_RX_QUEUE,
115 };
116
117 /* Operational mode for driver */
118 #define QLCNIC_VNIC_MODE 0xFF
119 #define QLCNIC_DEFAULT_MODE 0x0
120
121 /* Virtual NIC function count */
122 #define QLC_DEFAULT_VNIC_COUNT 8
123 #define QLC_84XX_VNIC_COUNT 16
124
125 /*
126 * Following are the states of the Phantom. Phantom will set them and
127 * Host will read to check if the fields are correct.
128 */
129 #define PHAN_INITIALIZE_FAILED 0xffff
130 #define PHAN_INITIALIZE_COMPLETE 0xff01
131
132 /* Host writes the following to notify that it has done the init-handshake */
133 #define PHAN_INITIALIZE_ACK 0xf00f
134 #define PHAN_PEG_RCV_INITIALIZED 0xff01
135
136 #define NUM_RCV_DESC_RINGS 3
137
138 #define RCV_RING_NORMAL 0
139 #define RCV_RING_JUMBO 1
140
141 #define MIN_CMD_DESCRIPTORS 64
142 #define MIN_RCV_DESCRIPTORS 64
143 #define MIN_JUMBO_DESCRIPTORS 32
144
145 #define MAX_CMD_DESCRIPTORS 1024
146 #define MAX_RCV_DESCRIPTORS_1G 4096
147 #define MAX_RCV_DESCRIPTORS_10G 8192
148 #define MAX_RCV_DESCRIPTORS_VF 2048
149 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
150 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
151
152 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
153 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
154 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
155 #define MAX_RDS_RINGS 2
156
157 #define get_next_index(index, length) \
158 (((index) + 1) & ((length) - 1))
159
160 /*
161 * Following data structures describe the descriptors that will be used.
162 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
163 * we are doing LSO (above the 1500 size packet) only.
164 */
165 struct cmd_desc_type0 {
166 u8 tcp_hdr_offset; /* For LSO only */
167 u8 ip_hdr_offset; /* For LSO only */
168 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
169 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
170
171 __le64 addr_buffer2;
172
173 __le16 encap_descr; /* 15:10 offset of outer L3 header,
174 * 9:6 number of 32bit words in outer L3 header,
175 * 5 offload outer L4 checksum,
176 * 4 offload outer L3 checksum,
177 * 3 Inner L4 type, TCP=0, UDP=1,
178 * 2 Inner L3 type, IPv4=0, IPv6=1,
179 * 1 Outer L3 type,IPv4=0, IPv6=1,
180 * 0 type of encapsulation, GRE=0, VXLAN=1
181 */
182 __le16 mss;
183 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
184 u8 hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
185 u8 outer_hdr_length; /* Encapsulation only */
186 u8 rsvd1;
187
188 __le64 addr_buffer3;
189 __le64 addr_buffer1;
190
191 __le16 buffer_length[4];
192
193 __le64 addr_buffer4;
194
195 u8 eth_addr[ETH_ALEN];
196 __le16 vlan_TCI; /* In case of encapsulation,
197 * this is for outer VLAN
198 */
199
200 } __attribute__ ((aligned(64)));
201
202 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
203 struct rcv_desc {
204 __le16 reference_handle;
205 __le16 reserved;
206 __le32 buffer_length; /* allocated buffer length (usually 2K) */
207 __le64 addr_buffer;
208 } __packed;
209
210 struct status_desc {
211 __le64 status_desc_data[2];
212 } __attribute__ ((aligned(16)));
213
214 /* UNIFIED ROMIMAGE */
215 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
216 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
217 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
218 #define QLCNIC_UNI_DIR_SECT_FW 0x7
219
220 /*Offsets */
221 #define QLCNIC_UNI_CHIP_REV_OFF 10
222 #define QLCNIC_UNI_FLAGS_OFF 11
223 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
224 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
225 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
226
227 struct uni_table_desc{
228 __le32 findex;
229 __le32 num_entries;
230 __le32 entry_size;
231 __le32 reserved[5];
232 };
233
234 struct uni_data_desc{
235 __le32 findex;
236 __le32 size;
237 __le32 reserved[5];
238 };
239
240 /* Flash Defines and Structures */
241 #define QLCNIC_FLT_LOCATION 0x3F1000
242 #define QLCNIC_FDT_LOCATION 0x3F0000
243 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
244 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
245 #define QLCNIC_BOOTLD_REGION 0X72
246 struct qlcnic_flt_header {
247 u16 version;
248 u16 len;
249 u16 checksum;
250 u16 reserved;
251 };
252
253 struct qlcnic_flt_entry {
254 u8 region;
255 u8 reserved0;
256 u8 attrib;
257 u8 reserved1;
258 u32 size;
259 u32 start_addr;
260 u32 end_addr;
261 };
262
263 /* Flash Descriptor Table */
264 struct qlcnic_fdt {
265 u32 valid;
266 u16 ver;
267 u16 len;
268 u16 cksum;
269 u16 unused;
270 u8 model[16];
271 u16 mfg_id;
272 u16 id;
273 u8 flag;
274 u8 erase_cmd;
275 u8 alt_erase_cmd;
276 u8 write_enable_cmd;
277 u8 write_enable_bits;
278 u8 write_statusreg_cmd;
279 u8 unprotected_sec_cmd;
280 u8 read_manuf_cmd;
281 u32 block_size;
282 u32 alt_block_size;
283 u32 flash_size;
284 u32 write_enable_data;
285 u8 readid_addr_len;
286 u8 write_disable_bits;
287 u8 read_dev_id_len;
288 u8 chip_erase_cmd;
289 u16 read_timeo;
290 u8 protected_sec_cmd;
291 u8 resvd[65];
292 };
293 /* Magic number to let user know flash is programmed */
294 #define QLCNIC_BDINFO_MAGIC 0x12345678
295
296 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
297 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
298 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
299 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
300 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
301 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
302 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
303 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
304 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
305 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
306 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
307 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
308 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
309 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
310
311 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
312
313 /* Flash memory map */
314 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
315 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
316 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
317 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
318
319 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
320 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
321 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
322 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
323
324 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
325 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
326
327 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
328 #define QLCNIC_UNIFIED_ROMIMAGE 0
329 #define QLCNIC_FLASH_ROMIMAGE 1
330 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
331
332 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
333 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
334
335 extern char qlcnic_driver_name[];
336
337 extern int qlcnic_use_msi;
338 extern int qlcnic_use_msi_x;
339 extern int qlcnic_auto_fw_reset;
340 extern int qlcnic_load_fw_file;
341
342 /* Number of status descriptors to handle per interrupt */
343 #define MAX_STATUS_HANDLE (64)
344
345 /*
346 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
347 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
348 */
349 struct qlcnic_skb_frag {
350 u64 dma;
351 u64 length;
352 };
353
354 /* Following defines are for the state of the buffers */
355 #define QLCNIC_BUFFER_FREE 0
356 #define QLCNIC_BUFFER_BUSY 1
357
358 /*
359 * There will be one qlcnic_buffer per skb packet. These will be
360 * used to save the dma info for pci_unmap_page()
361 */
362 struct qlcnic_cmd_buffer {
363 struct sk_buff *skb;
364 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
365 u32 frag_count;
366 };
367
368 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
369 struct qlcnic_rx_buffer {
370 u16 ref_handle;
371 struct sk_buff *skb;
372 struct list_head list;
373 u64 dma;
374 };
375
376 /* Board types */
377 #define QLCNIC_GBE 0x01
378 #define QLCNIC_XGBE 0x02
379
380 /*
381 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
382 * adjusted based on configured MTU.
383 */
384 #define QLCNIC_INTR_COAL_TYPE_RX 1
385 #define QLCNIC_INTR_COAL_TYPE_TX 2
386 #define QLCNIC_INTR_COAL_TYPE_RX_TX 3
387
388 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3
389 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256
390
391 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64
392 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64
393
394 #define QLCNIC_INTR_DEFAULT 0x04
395 #define QLCNIC_CONFIG_INTR_COALESCE 3
396 #define QLCNIC_DEV_INFO_SIZE 2
397
398 struct qlcnic_nic_intr_coalesce {
399 u8 type;
400 u8 sts_ring_mask;
401 u16 rx_packets;
402 u16 rx_time_us;
403 u16 tx_packets;
404 u16 tx_time_us;
405 u16 flag;
406 u32 timer_out;
407 };
408
409 struct qlcnic_83xx_dump_template_hdr {
410 u32 type;
411 u32 offset;
412 u32 size;
413 u32 cap_mask;
414 u32 num_entries;
415 u32 version;
416 u32 timestamp;
417 u32 checksum;
418 u32 drv_cap_mask;
419 u32 sys_info[3];
420 u32 saved_state[16];
421 u32 cap_sizes[8];
422 u32 ocm_wnd_reg[16];
423 u32 rsvd[0];
424 };
425
426 struct qlcnic_82xx_dump_template_hdr {
427 u32 type;
428 u32 offset;
429 u32 size;
430 u32 cap_mask;
431 u32 num_entries;
432 u32 version;
433 u32 timestamp;
434 u32 checksum;
435 u32 drv_cap_mask;
436 u32 sys_info[3];
437 u32 saved_state[16];
438 u32 cap_sizes[8];
439 u32 rsvd[7];
440 u32 capabilities;
441 u32 rsvd1[0];
442 };
443
444 struct qlcnic_fw_dump {
445 u8 clr; /* flag to indicate if dump is cleared */
446 bool enable; /* enable/disable dump */
447 u32 size; /* total size of the dump */
448 u32 cap_mask; /* Current capture mask */
449 void *data; /* dump data area */
450 void *tmpl_hdr;
451 dma_addr_t phys_addr;
452 void *dma_buffer;
453 bool use_pex_dma;
454 /* Read only elements which are common between 82xx and 83xx
455 * template header. Update these values immediately after we read
456 * template header from Firmware
457 */
458 u32 tmpl_hdr_size;
459 u32 version;
460 u32 num_entries;
461 u32 offset;
462 };
463
464 /*
465 * One hardware_context{} per adapter
466 * contains interrupt info as well shared hardware info.
467 */
468 struct qlcnic_hardware_context {
469 void __iomem *pci_base0;
470 void __iomem *ocm_win_crb;
471
472 unsigned long pci_len0;
473
474 rwlock_t crb_lock;
475 struct mutex mem_lock;
476
477 u8 revision_id;
478 u8 pci_func;
479 u8 linkup;
480 u8 loopback_state;
481 u8 beacon_state;
482 u8 has_link_events;
483 u8 fw_type;
484 u8 physical_port;
485 u8 reset_context;
486 u8 msix_supported;
487 u8 max_mac_filters;
488 u8 mc_enabled;
489 u8 max_mc_count;
490 u8 diag_test;
491 u8 num_msix;
492 u8 nic_mode;
493 int diag_cnt;
494
495 u16 max_uc_count;
496 u16 port_type;
497 u16 board_type;
498 u16 supported_type;
499
500 u16 link_speed;
501 u16 link_duplex;
502 u16 link_autoneg;
503 u16 module_type;
504
505 u16 op_mode;
506 u16 switch_mode;
507 u16 max_tx_ques;
508 u16 max_rx_ques;
509 u16 max_mtu;
510 u32 msg_enable;
511 u16 total_nic_func;
512 u16 max_pci_func;
513 u32 max_vnic_func;
514 u32 total_pci_func;
515
516 u32 capabilities;
517 u32 extra_capability[3];
518 u32 temp;
519 u32 int_vec_bit;
520 u32 fw_hal_version;
521 u32 port_config;
522 struct qlcnic_hardware_ops *hw_ops;
523 struct qlcnic_nic_intr_coalesce coal;
524 struct qlcnic_fw_dump fw_dump;
525 struct qlcnic_fdt fdt;
526 struct qlc_83xx_reset reset;
527 struct qlc_83xx_idc idc;
528 struct qlc_83xx_fw_info *fw_info;
529 struct qlcnic_intrpt_config *intr_tbl;
530 struct qlcnic_sriov *sriov;
531 u32 *reg_tbl;
532 u32 *ext_reg_tbl;
533 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT];
534 u32 mbox_reg[4];
535 struct qlcnic_mailbox *mailbox;
536 u8 extend_lb_time;
537 u8 phys_port_id[ETH_ALEN];
538 u8 lb_mode;
539 u16 vxlan_port;
540 };
541
542 struct qlcnic_adapter_stats {
543 u64 xmitcalled;
544 u64 xmitfinished;
545 u64 rxdropped;
546 u64 txdropped;
547 u64 csummed;
548 u64 rx_pkts;
549 u64 lro_pkts;
550 u64 rxbytes;
551 u64 txbytes;
552 u64 lrobytes;
553 u64 lso_frames;
554 u64 encap_lso_frames;
555 u64 encap_tx_csummed;
556 u64 encap_rx_csummed;
557 u64 xmit_on;
558 u64 xmit_off;
559 u64 skb_alloc_failure;
560 u64 null_rxbuf;
561 u64 rx_dma_map_error;
562 u64 tx_dma_map_error;
563 u64 spurious_intr;
564 u64 mac_filter_limit_overrun;
565 };
566
567 /*
568 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
569 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
570 */
571 struct qlcnic_host_rds_ring {
572 void __iomem *crb_rcv_producer;
573 struct rcv_desc *desc_head;
574 struct qlcnic_rx_buffer *rx_buf_arr;
575 u32 num_desc;
576 u32 producer;
577 u32 dma_size;
578 u32 skb_size;
579 u32 flags;
580 struct list_head free_list;
581 spinlock_t lock;
582 dma_addr_t phys_addr;
583 } ____cacheline_internodealigned_in_smp;
584
585 struct qlcnic_host_sds_ring {
586 u32 consumer;
587 u32 num_desc;
588 void __iomem *crb_sts_consumer;
589
590 struct qlcnic_host_tx_ring *tx_ring;
591 struct status_desc *desc_head;
592 struct qlcnic_adapter *adapter;
593 struct napi_struct napi;
594 struct list_head free_list[NUM_RCV_DESC_RINGS];
595
596 void __iomem *crb_intr_mask;
597 int irq;
598
599 dma_addr_t phys_addr;
600 char name[IFNAMSIZ + 12];
601 } ____cacheline_internodealigned_in_smp;
602
603 struct qlcnic_tx_queue_stats {
604 u64 xmit_on;
605 u64 xmit_off;
606 u64 xmit_called;
607 u64 xmit_finished;
608 u64 tx_bytes;
609 };
610
611 struct qlcnic_host_tx_ring {
612 int irq;
613 void __iomem *crb_intr_mask;
614 char name[IFNAMSIZ + 12];
615 u16 ctx_id;
616
617 u32 state;
618 u32 producer;
619 u32 sw_consumer;
620 u32 num_desc;
621
622 struct qlcnic_tx_queue_stats tx_stats;
623
624 void __iomem *crb_cmd_producer;
625 struct cmd_desc_type0 *desc_head;
626 struct qlcnic_adapter *adapter;
627 struct napi_struct napi;
628 struct qlcnic_cmd_buffer *cmd_buf_arr;
629 __le32 *hw_consumer;
630
631 dma_addr_t phys_addr;
632 dma_addr_t hw_cons_phys_addr;
633 struct netdev_queue *txq;
634 /* Lock to protect Tx descriptors cleanup */
635 spinlock_t tx_clean_lock;
636 } ____cacheline_internodealigned_in_smp;
637
638 /*
639 * Receive context. There is one such structure per instance of the
640 * receive processing. Any state information that is relevant to
641 * the receive, and is must be in this structure. The global data may be
642 * present elsewhere.
643 */
644 struct qlcnic_recv_context {
645 struct qlcnic_host_rds_ring *rds_rings;
646 struct qlcnic_host_sds_ring *sds_rings;
647 u32 state;
648 u16 context_id;
649 u16 virt_port;
650 };
651
652 /* HW context creation */
653
654 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
655
656 #define QLCNIC_CDRP_CMD_BIT 0x80000000
657
658 /*
659 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
660 * in the crb QLCNIC_CDRP_CRB_OFFSET.
661 */
662 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
663 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
664
665 #define QLCNIC_CDRP_RSP_OK 0x00000001
666 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
667 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
668
669 /*
670 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
671 * the crb QLCNIC_CDRP_CRB_OFFSET.
672 */
673 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
674
675 #define QLCNIC_RCODE_SUCCESS 0
676 #define QLCNIC_RCODE_INVALID_ARGS 6
677 #define QLCNIC_RCODE_NOT_SUPPORTED 9
678 #define QLCNIC_RCODE_NOT_PERMITTED 10
679 #define QLCNIC_RCODE_NOT_IMPL 15
680 #define QLCNIC_RCODE_INVALID 16
681 #define QLCNIC_RCODE_TIMEOUT 17
682 #define QLCNIC_DESTROY_CTX_RESET 0
683
684 /*
685 * Capabilities Announced
686 */
687 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
688 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
689 #define QLCNIC_CAP0_LSO (1 << 6)
690 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
691 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
692 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
693 #define QLCNIC_CAP0_LRO_MSS (1 << 21)
694 #define QLCNIC_CAP0_TX_MULTI (1 << 22)
695
696 /*
697 * Context state
698 */
699 #define QLCNIC_HOST_CTX_STATE_FREED 0
700 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
701
702 /*
703 * Rx context
704 */
705
706 struct qlcnic_hostrq_sds_ring {
707 __le64 host_phys_addr; /* Ring base addr */
708 __le32 ring_size; /* Ring entries */
709 __le16 msi_index;
710 __le16 rsvd; /* Padding */
711 } __packed;
712
713 struct qlcnic_hostrq_rds_ring {
714 __le64 host_phys_addr; /* Ring base addr */
715 __le64 buff_size; /* Packet buffer size */
716 __le32 ring_size; /* Ring entries */
717 __le32 ring_kind; /* Class of ring */
718 } __packed;
719
720 struct qlcnic_hostrq_rx_ctx {
721 __le64 host_rsp_dma_addr; /* Response dma'd here */
722 __le32 capabilities[4]; /* Flag bit vector */
723 __le32 host_int_crb_mode; /* Interrupt crb usage */
724 __le32 host_rds_crb_mode; /* RDS crb usage */
725 /* These ring offsets are relative to data[0] below */
726 __le32 rds_ring_offset; /* Offset to RDS config */
727 __le32 sds_ring_offset; /* Offset to SDS config */
728 __le16 num_rds_rings; /* Count of RDS rings */
729 __le16 num_sds_rings; /* Count of SDS rings */
730 __le16 valid_field_offset;
731 u8 txrx_sds_binding;
732 u8 msix_handler;
733 u8 reserved[128]; /* reserve space for future expansion*/
734 /* MUST BE 64-bit aligned.
735 The following is packed:
736 - N hostrq_rds_rings
737 - N hostrq_sds_rings */
738 char data[0];
739 } __packed;
740
741 struct qlcnic_cardrsp_rds_ring{
742 __le32 host_producer_crb; /* Crb to use */
743 __le32 rsvd1; /* Padding */
744 } __packed;
745
746 struct qlcnic_cardrsp_sds_ring {
747 __le32 host_consumer_crb; /* Crb to use */
748 __le32 interrupt_crb; /* Crb to use */
749 } __packed;
750
751 struct qlcnic_cardrsp_rx_ctx {
752 /* These ring offsets are relative to data[0] below */
753 __le32 rds_ring_offset; /* Offset to RDS config */
754 __le32 sds_ring_offset; /* Offset to SDS config */
755 __le32 host_ctx_state; /* Starting State */
756 __le32 num_fn_per_port; /* How many PCI fn share the port */
757 __le16 num_rds_rings; /* Count of RDS rings */
758 __le16 num_sds_rings; /* Count of SDS rings */
759 __le16 context_id; /* Handle for context */
760 u8 phys_port; /* Physical id of port */
761 u8 virt_port; /* Virtual/Logical id of port */
762 u8 reserved[128]; /* save space for future expansion */
763 /* MUST BE 64-bit aligned.
764 The following is packed:
765 - N cardrsp_rds_rings
766 - N cardrs_sds_rings */
767 char data[0];
768 } __packed;
769
770 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
771 (sizeof(HOSTRQ_RX) + \
772 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
773 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
774
775 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
776 (sizeof(CARDRSP_RX) + \
777 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
778 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
779
780 /*
781 * Tx context
782 */
783
784 struct qlcnic_hostrq_cds_ring {
785 __le64 host_phys_addr; /* Ring base addr */
786 __le32 ring_size; /* Ring entries */
787 __le32 rsvd; /* Padding */
788 } __packed;
789
790 struct qlcnic_hostrq_tx_ctx {
791 __le64 host_rsp_dma_addr; /* Response dma'd here */
792 __le64 cmd_cons_dma_addr; /* */
793 __le64 dummy_dma_addr; /* */
794 __le32 capabilities[4]; /* Flag bit vector */
795 __le32 host_int_crb_mode; /* Interrupt crb usage */
796 __le32 rsvd1; /* Padding */
797 __le16 rsvd2; /* Padding */
798 __le16 interrupt_ctl;
799 __le16 msi_index;
800 __le16 rsvd3; /* Padding */
801 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
802 u8 reserved[128]; /* future expansion */
803 } __packed;
804
805 struct qlcnic_cardrsp_cds_ring {
806 __le32 host_producer_crb; /* Crb to use */
807 __le32 interrupt_crb; /* Crb to use */
808 } __packed;
809
810 struct qlcnic_cardrsp_tx_ctx {
811 __le32 host_ctx_state; /* Starting state */
812 __le16 context_id; /* Handle for context */
813 u8 phys_port; /* Physical id of port */
814 u8 virt_port; /* Virtual/Logical id of port */
815 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
816 u8 reserved[128]; /* future expansion */
817 } __packed;
818
819 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
820 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
821
822 /* CRB */
823
824 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
825 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
826 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
827 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
828
829 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
830 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
831 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
832 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
833 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
834
835
836 /* MAC */
837
838 #define MC_COUNT_P3P 38
839
840 #define QLCNIC_MAC_NOOP 0
841 #define QLCNIC_MAC_ADD 1
842 #define QLCNIC_MAC_DEL 2
843 #define QLCNIC_MAC_VLAN_ADD 3
844 #define QLCNIC_MAC_VLAN_DEL 4
845
846 struct qlcnic_mac_vlan_list {
847 struct list_head list;
848 uint8_t mac_addr[ETH_ALEN+2];
849 u16 vlan_id;
850 };
851
852 /* MAC Learn */
853 #define NO_MAC_LEARN 0
854 #define DRV_MAC_LEARN 1
855 #define FDB_MAC_LEARN 2
856
857 #define QLCNIC_HOST_REQUEST 0x13
858 #define QLCNIC_REQUEST 0x14
859
860 #define QLCNIC_MAC_EVENT 0x1
861
862 #define QLCNIC_IP_UP 2
863 #define QLCNIC_IP_DOWN 3
864
865 #define QLCNIC_ILB_MODE 0x1
866 #define QLCNIC_ELB_MODE 0x2
867 #define QLCNIC_LB_MODE_MASK 0x3
868
869 #define QLCNIC_LINKEVENT 0x1
870 #define QLCNIC_LB_RESPONSE 0x2
871 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
872 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
873
874 /*
875 * Driver --> Firmware
876 */
877 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
878 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
879 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
880 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
881 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
882 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
883
884 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
885 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
886 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
887 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
888
889 /*
890 * Firmware --> Driver
891 */
892
893 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
894 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D
895 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90
896
897 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
898 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
899 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
900
901 #define QLCNIC_LRO_REQUEST_CLEANUP 4
902
903 /* Capabilites received */
904 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
905 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
906 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
907 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
908 #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4
909 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
910 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31
911
912 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
913 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3
914 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
915 #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7
916 #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9
917
918 #define QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD BIT_0
919 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1
920 #define QLCNIC_83XX_FW_CAPAB_ENCAP_CKO_OFFLOAD BIT_4
921
922 /* module types */
923 #define LINKEVENT_MODULE_NOT_PRESENT 1
924 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
925 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
926 #define LINKEVENT_MODULE_OPTICAL_LRM 4
927 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
928 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
929 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
930 #define LINKEVENT_MODULE_TWINAX 8
931
932 #define LINKSPEED_10GBPS 10000
933 #define LINKSPEED_1GBPS 1000
934 #define LINKSPEED_100MBPS 100
935 #define LINKSPEED_10MBPS 10
936
937 #define LINKSPEED_ENCODED_10MBPS 0
938 #define LINKSPEED_ENCODED_100MBPS 1
939 #define LINKSPEED_ENCODED_1GBPS 2
940
941 #define LINKEVENT_AUTONEG_DISABLED 0
942 #define LINKEVENT_AUTONEG_ENABLED 1
943
944 #define LINKEVENT_HALF_DUPLEX 0
945 #define LINKEVENT_FULL_DUPLEX 1
946
947 #define LINKEVENT_LINKSPEED_MBPS 0
948 #define LINKEVENT_LINKSPEED_ENCODED 1
949
950 /* firmware response header:
951 * 63:58 - message type
952 * 57:56 - owner
953 * 55:53 - desc count
954 * 52:48 - reserved
955 * 47:40 - completion id
956 * 39:32 - opcode
957 * 31:16 - error code
958 * 15:00 - reserved
959 */
960 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
961 ((msg_hdr >> 32) & 0xFF)
962
963 struct qlcnic_fw_msg {
964 union {
965 struct {
966 u64 hdr;
967 u64 body[7];
968 };
969 u64 words[8];
970 };
971 };
972
973 struct qlcnic_nic_req {
974 __le64 qhdr;
975 __le64 req_hdr;
976 __le64 words[6];
977 } __packed;
978
979 struct qlcnic_mac_req {
980 u8 op;
981 u8 tag;
982 u8 mac_addr[6];
983 };
984
985 struct qlcnic_vlan_req {
986 __le16 vlan_id;
987 __le16 rsvd[3];
988 } __packed;
989
990 struct qlcnic_ipaddr {
991 __be32 ipv4;
992 __be32 ipv6[4];
993 };
994
995 #define QLCNIC_MSI_ENABLED 0x02
996 #define QLCNIC_MSIX_ENABLED 0x04
997 #define QLCNIC_LRO_ENABLED 0x01
998 #define QLCNIC_LRO_DISABLED 0x00
999 #define QLCNIC_BRIDGE_ENABLED 0X10
1000 #define QLCNIC_DIAG_ENABLED 0x20
1001 #define QLCNIC_ESWITCH_ENABLED 0x40
1002 #define QLCNIC_ADAPTER_INITIALIZED 0x80
1003 #define QLCNIC_TAGGING_ENABLED 0x100
1004 #define QLCNIC_MACSPOOF 0x200
1005 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
1006 #define QLCNIC_PROMISC_DISABLED 0x800
1007 #define QLCNIC_NEED_FLR 0x1000
1008 #define QLCNIC_FW_RESET_OWNER 0x2000
1009 #define QLCNIC_FW_HANG 0x4000
1010 #define QLCNIC_FW_LRO_MSS_CAP 0x8000
1011 #define QLCNIC_TX_INTR_SHARED 0x10000
1012 #define QLCNIC_APP_CHANGED_FLAGS 0x20000
1013 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000
1014 #define QLCNIC_TSS_RSS 0x80000
1015
1016 #ifdef CONFIG_QLCNIC_VXLAN
1017 #define QLCNIC_ADD_VXLAN_PORT 0x100000
1018 #define QLCNIC_DEL_VXLAN_PORT 0x200000
1019 #endif
1020
1021 #define QLCNIC_IS_MSI_FAMILY(adapter) \
1022 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
1023 #define QLCNIC_IS_TSO_CAPABLE(adapter) \
1024 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
1025
1026 #define QLCNIC_BEACON_EANBLE 0xC
1027 #define QLCNIC_BEACON_DISABLE 0xD
1028
1029 #define QLCNIC_BEACON_ON 2
1030 #define QLCNIC_BEACON_OFF 0
1031
1032 #define QLCNIC_MSIX_TBL_SPACE 8192
1033 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
1034 #define QLCNIC_MSIX_TBL_PGSIZE 4096
1035
1036 #define QLCNIC_ADAPTER_UP_MAGIC 777
1037
1038 #define __QLCNIC_FW_ATTACHED 0
1039 #define __QLCNIC_DEV_UP 1
1040 #define __QLCNIC_RESETTING 2
1041 #define __QLCNIC_START_FW 4
1042 #define __QLCNIC_AER 5
1043 #define __QLCNIC_DIAG_RES_ALLOC 6
1044 #define __QLCNIC_LED_ENABLE 7
1045 #define __QLCNIC_ELB_INPROGRESS 8
1046 #define __QLCNIC_MULTI_TX_UNIQUE 9
1047 #define __QLCNIC_SRIOV_ENABLE 10
1048 #define __QLCNIC_SRIOV_CAPABLE 11
1049 #define __QLCNIC_MBX_POLL_ENABLE 12
1050 #define __QLCNIC_DIAG_MODE 13
1051 #define __QLCNIC_MAINTENANCE_MODE 16
1052
1053 #define QLCNIC_INTERRUPT_TEST 1
1054 #define QLCNIC_LOOPBACK_TEST 2
1055 #define QLCNIC_LED_TEST 3
1056
1057 #define QLCNIC_FILTER_AGE 80
1058 #define QLCNIC_READD_AGE 20
1059 #define QLCNIC_LB_MAX_FILTERS 64
1060 #define QLCNIC_LB_BUCKET_SIZE 32
1061 #define QLCNIC_ILB_MAX_RCV_LOOP 10
1062
1063 struct qlcnic_filter {
1064 struct hlist_node fnode;
1065 u8 faddr[ETH_ALEN];
1066 u16 vlan_id;
1067 unsigned long ftime;
1068 };
1069
1070 struct qlcnic_filter_hash {
1071 struct hlist_head *fhead;
1072 u8 fnum;
1073 u16 fmax;
1074 u16 fbucket_size;
1075 };
1076
1077 /* Mailbox specific data structures */
1078 struct qlcnic_mailbox {
1079 struct workqueue_struct *work_q;
1080 struct qlcnic_adapter *adapter;
1081 struct qlcnic_mbx_ops *ops;
1082 struct work_struct work;
1083 struct completion completion;
1084 struct list_head cmd_q;
1085 unsigned long status;
1086 spinlock_t queue_lock; /* Mailbox queue lock */
1087 spinlock_t aen_lock; /* Mailbox response/AEN lock */
1088 atomic_t rsp_status;
1089 u32 num_cmds;
1090 };
1091
1092 struct qlcnic_adapter {
1093 struct qlcnic_hardware_context *ahw;
1094 struct qlcnic_recv_context *recv_ctx;
1095 struct qlcnic_host_tx_ring *tx_ring;
1096 struct net_device *netdev;
1097 struct pci_dev *pdev;
1098
1099 unsigned long state;
1100 u32 flags;
1101
1102 u16 num_txd;
1103 u16 num_rxd;
1104 u16 num_jumbo_rxd;
1105 u16 max_rxd;
1106 u16 max_jumbo_rxd;
1107
1108 u8 max_rds_rings;
1109
1110 u8 max_sds_rings; /* max sds rings supported by adapter */
1111 u8 max_tx_rings; /* max tx rings supported by adapter */
1112
1113 u8 drv_tx_rings; /* max tx rings supported by driver */
1114 u8 drv_sds_rings; /* max sds rings supported by driver */
1115
1116 u8 drv_tss_rings; /* tss ring input */
1117 u8 drv_rss_rings; /* rss ring input */
1118
1119 u8 rx_csum;
1120 u8 portnum;
1121
1122 u8 fw_wait_cnt;
1123 u8 fw_fail_cnt;
1124 u8 tx_timeo_cnt;
1125 u8 need_fw_reset;
1126 u8 reset_ctx_cnt;
1127
1128 u16 is_up;
1129 u16 rx_pvid;
1130 u16 tx_pvid;
1131
1132 u32 irq;
1133 u32 heartbeat;
1134
1135 u8 dev_state;
1136 u8 reset_ack_timeo;
1137 u8 dev_init_timeo;
1138
1139 u8 mac_addr[ETH_ALEN];
1140
1141 u64 dev_rst_time;
1142 bool drv_mac_learn;
1143 bool fdb_mac_learn;
1144 bool rx_mac_learn;
1145 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1146 u8 flash_mfg_id;
1147 struct qlcnic_npar_info *npars;
1148 struct qlcnic_eswitch *eswitch;
1149 struct qlcnic_nic_template *nic_ops;
1150
1151 struct qlcnic_adapter_stats stats;
1152 struct list_head mac_list;
1153
1154 void __iomem *tgt_mask_reg;
1155 void __iomem *tgt_status_reg;
1156 void __iomem *crb_int_state_reg;
1157 void __iomem *isr_int_vec;
1158
1159 struct msix_entry *msix_entries;
1160 struct workqueue_struct *qlcnic_wq;
1161 struct delayed_work fw_work;
1162 struct delayed_work idc_aen_work;
1163 struct delayed_work mbx_poll_work;
1164 struct qlcnic_dcb *dcb;
1165
1166 struct qlcnic_filter_hash fhash;
1167 struct qlcnic_filter_hash rx_fhash;
1168 struct list_head vf_mc_list;
1169
1170 spinlock_t mac_learn_lock;
1171 /* spinlock for catching rcv filters for eswitch traffic */
1172 spinlock_t rx_mac_learn_lock;
1173 u32 file_prd_off; /*File fw product offset*/
1174 u32 fw_version;
1175 u32 offload_flags;
1176 const struct firmware *fw;
1177 };
1178
1179 struct qlcnic_info_le {
1180 __le16 pci_func;
1181 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1182 __le16 phys_port;
1183 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1184
1185 __le32 capabilities;
1186 u8 max_mac_filters;
1187 u8 reserved1;
1188 __le16 max_mtu;
1189
1190 __le16 max_tx_ques;
1191 __le16 max_rx_ques;
1192 __le16 min_tx_bw;
1193 __le16 max_tx_bw;
1194 __le32 op_type;
1195 __le16 max_bw_reg_offset;
1196 __le16 max_linkspeed_reg_offset;
1197 __le32 capability1;
1198 __le32 capability2;
1199 __le32 capability3;
1200 __le16 max_tx_mac_filters;
1201 __le16 max_rx_mcast_mac_filters;
1202 __le16 max_rx_ucast_mac_filters;
1203 __le16 max_rx_ip_addr;
1204 __le16 max_rx_lro_flow;
1205 __le16 max_rx_status_rings;
1206 __le16 max_rx_buf_rings;
1207 __le16 max_tx_vlan_keys;
1208 u8 total_pf;
1209 u8 total_rss_engines;
1210 __le16 max_vports;
1211 __le16 linkstate_reg_offset;
1212 __le16 bit_offsets;
1213 __le16 max_local_ipv6_addrs;
1214 __le16 max_remote_ipv6_addrs;
1215 u8 reserved2[56];
1216 } __packed;
1217
1218 struct qlcnic_info {
1219 u16 pci_func;
1220 u16 op_mode;
1221 u16 phys_port;
1222 u16 switch_mode;
1223 u32 capabilities;
1224 u8 max_mac_filters;
1225 u16 max_mtu;
1226 u16 max_tx_ques;
1227 u16 max_rx_ques;
1228 u16 min_tx_bw;
1229 u16 max_tx_bw;
1230 u32 op_type;
1231 u16 max_bw_reg_offset;
1232 u16 max_linkspeed_reg_offset;
1233 u32 capability1;
1234 u32 capability2;
1235 u32 capability3;
1236 u16 max_tx_mac_filters;
1237 u16 max_rx_mcast_mac_filters;
1238 u16 max_rx_ucast_mac_filters;
1239 u16 max_rx_ip_addr;
1240 u16 max_rx_lro_flow;
1241 u16 max_rx_status_rings;
1242 u16 max_rx_buf_rings;
1243 u16 max_tx_vlan_keys;
1244 u8 total_pf;
1245 u8 total_rss_engines;
1246 u16 max_vports;
1247 u16 linkstate_reg_offset;
1248 u16 bit_offsets;
1249 u16 max_local_ipv6_addrs;
1250 u16 max_remote_ipv6_addrs;
1251 };
1252
1253 struct qlcnic_pci_info_le {
1254 __le16 id; /* pci function id */
1255 __le16 active; /* 1 = Enabled */
1256 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1257 __le16 default_port; /* default port number */
1258
1259 __le16 tx_min_bw; /* Multiple of 100mbpc */
1260 __le16 tx_max_bw;
1261 __le16 reserved1[2];
1262
1263 u8 mac[ETH_ALEN];
1264 __le16 func_count;
1265 u8 reserved2[104];
1266
1267 } __packed;
1268
1269 struct qlcnic_pci_info {
1270 u16 id;
1271 u16 active;
1272 u16 type;
1273 u16 default_port;
1274 u16 tx_min_bw;
1275 u16 tx_max_bw;
1276 u8 mac[ETH_ALEN];
1277 u16 func_count;
1278 };
1279
1280 struct qlcnic_npar_info {
1281 bool eswitch_status;
1282 u16 pvid;
1283 u16 min_bw;
1284 u16 max_bw;
1285 u8 phy_port;
1286 u8 type;
1287 u8 active;
1288 u8 enable_pm;
1289 u8 dest_npar;
1290 u8 discard_tagged;
1291 u8 mac_override;
1292 u8 mac_anti_spoof;
1293 u8 promisc_mode;
1294 u8 offload_flags;
1295 u8 pci_func;
1296 u8 mac[ETH_ALEN];
1297 };
1298
1299 struct qlcnic_eswitch {
1300 u8 port;
1301 u8 active_vports;
1302 u8 active_vlans;
1303 u8 active_ucast_filters;
1304 u8 max_ucast_filters;
1305 u8 max_active_vlans;
1306
1307 u32 flags;
1308 #define QLCNIC_SWITCH_ENABLE BIT_1
1309 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1310 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1311 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1312 };
1313
1314
1315 /* Return codes for Error handling */
1316 #define QL_STATUS_INVALID_PARAM -1
1317
1318 #define MAX_BW 100 /* % of link speed */
1319 #define MAX_VLAN_ID 4095
1320 #define MIN_VLAN_ID 2
1321 #define DEFAULT_MAC_LEARN 1
1322
1323 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1324 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1325
1326 struct qlcnic_pci_func_cfg {
1327 u16 func_type;
1328 u16 min_bw;
1329 u16 max_bw;
1330 u16 port_num;
1331 u8 pci_func;
1332 u8 func_state;
1333 u8 def_mac_addr[ETH_ALEN];
1334 };
1335
1336 struct qlcnic_npar_func_cfg {
1337 u32 fw_capab;
1338 u16 port_num;
1339 u16 min_bw;
1340 u16 max_bw;
1341 u16 max_tx_queues;
1342 u16 max_rx_queues;
1343 u8 pci_func;
1344 u8 op_mode;
1345 };
1346
1347 struct qlcnic_pm_func_cfg {
1348 u8 pci_func;
1349 u8 action;
1350 u8 dest_npar;
1351 u8 reserved[5];
1352 };
1353
1354 struct qlcnic_esw_func_cfg {
1355 u16 vlan_id;
1356 u8 op_mode;
1357 u8 op_type;
1358 u8 pci_func;
1359 u8 host_vlan_tag;
1360 u8 promisc_mode;
1361 u8 discard_tagged;
1362 u8 mac_override;
1363 u8 mac_anti_spoof;
1364 u8 offload_flags;
1365 u8 reserved[5];
1366 };
1367
1368 #define QLCNIC_STATS_VERSION 1
1369 #define QLCNIC_STATS_PORT 1
1370 #define QLCNIC_STATS_ESWITCH 2
1371 #define QLCNIC_QUERY_RX_COUNTER 0
1372 #define QLCNIC_QUERY_TX_COUNTER 1
1373 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1374 #define QLCNIC_FILL_STATS(VAL1) \
1375 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1376 #define QLCNIC_MAC_STATS 1
1377 #define QLCNIC_ESW_STATS 2
1378
1379 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1380 do { \
1381 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1382 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1383 (VAL1) = (VAL2); \
1384 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1385 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1386 (VAL1) += (VAL2); \
1387 } while (0)
1388
1389 struct qlcnic_mac_statistics_le {
1390 __le64 mac_tx_frames;
1391 __le64 mac_tx_bytes;
1392 __le64 mac_tx_mcast_pkts;
1393 __le64 mac_tx_bcast_pkts;
1394 __le64 mac_tx_pause_cnt;
1395 __le64 mac_tx_ctrl_pkt;
1396 __le64 mac_tx_lt_64b_pkts;
1397 __le64 mac_tx_lt_127b_pkts;
1398 __le64 mac_tx_lt_255b_pkts;
1399 __le64 mac_tx_lt_511b_pkts;
1400 __le64 mac_tx_lt_1023b_pkts;
1401 __le64 mac_tx_lt_1518b_pkts;
1402 __le64 mac_tx_gt_1518b_pkts;
1403 __le64 rsvd1[3];
1404
1405 __le64 mac_rx_frames;
1406 __le64 mac_rx_bytes;
1407 __le64 mac_rx_mcast_pkts;
1408 __le64 mac_rx_bcast_pkts;
1409 __le64 mac_rx_pause_cnt;
1410 __le64 mac_rx_ctrl_pkt;
1411 __le64 mac_rx_lt_64b_pkts;
1412 __le64 mac_rx_lt_127b_pkts;
1413 __le64 mac_rx_lt_255b_pkts;
1414 __le64 mac_rx_lt_511b_pkts;
1415 __le64 mac_rx_lt_1023b_pkts;
1416 __le64 mac_rx_lt_1518b_pkts;
1417 __le64 mac_rx_gt_1518b_pkts;
1418 __le64 rsvd2[3];
1419
1420 __le64 mac_rx_length_error;
1421 __le64 mac_rx_length_small;
1422 __le64 mac_rx_length_large;
1423 __le64 mac_rx_jabber;
1424 __le64 mac_rx_dropped;
1425 __le64 mac_rx_crc_error;
1426 __le64 mac_align_error;
1427 } __packed;
1428
1429 struct qlcnic_mac_statistics {
1430 u64 mac_tx_frames;
1431 u64 mac_tx_bytes;
1432 u64 mac_tx_mcast_pkts;
1433 u64 mac_tx_bcast_pkts;
1434 u64 mac_tx_pause_cnt;
1435 u64 mac_tx_ctrl_pkt;
1436 u64 mac_tx_lt_64b_pkts;
1437 u64 mac_tx_lt_127b_pkts;
1438 u64 mac_tx_lt_255b_pkts;
1439 u64 mac_tx_lt_511b_pkts;
1440 u64 mac_tx_lt_1023b_pkts;
1441 u64 mac_tx_lt_1518b_pkts;
1442 u64 mac_tx_gt_1518b_pkts;
1443 u64 rsvd1[3];
1444 u64 mac_rx_frames;
1445 u64 mac_rx_bytes;
1446 u64 mac_rx_mcast_pkts;
1447 u64 mac_rx_bcast_pkts;
1448 u64 mac_rx_pause_cnt;
1449 u64 mac_rx_ctrl_pkt;
1450 u64 mac_rx_lt_64b_pkts;
1451 u64 mac_rx_lt_127b_pkts;
1452 u64 mac_rx_lt_255b_pkts;
1453 u64 mac_rx_lt_511b_pkts;
1454 u64 mac_rx_lt_1023b_pkts;
1455 u64 mac_rx_lt_1518b_pkts;
1456 u64 mac_rx_gt_1518b_pkts;
1457 u64 rsvd2[3];
1458 u64 mac_rx_length_error;
1459 u64 mac_rx_length_small;
1460 u64 mac_rx_length_large;
1461 u64 mac_rx_jabber;
1462 u64 mac_rx_dropped;
1463 u64 mac_rx_crc_error;
1464 u64 mac_align_error;
1465 };
1466
1467 struct qlcnic_esw_stats_le {
1468 __le16 context_id;
1469 __le16 version;
1470 __le16 size;
1471 __le16 unused;
1472 __le64 unicast_frames;
1473 __le64 multicast_frames;
1474 __le64 broadcast_frames;
1475 __le64 dropped_frames;
1476 __le64 errors;
1477 __le64 local_frames;
1478 __le64 numbytes;
1479 __le64 rsvd[3];
1480 } __packed;
1481
1482 struct __qlcnic_esw_statistics {
1483 u16 context_id;
1484 u16 version;
1485 u16 size;
1486 u16 unused;
1487 u64 unicast_frames;
1488 u64 multicast_frames;
1489 u64 broadcast_frames;
1490 u64 dropped_frames;
1491 u64 errors;
1492 u64 local_frames;
1493 u64 numbytes;
1494 u64 rsvd[3];
1495 };
1496
1497 struct qlcnic_esw_statistics {
1498 struct __qlcnic_esw_statistics rx;
1499 struct __qlcnic_esw_statistics tx;
1500 };
1501
1502 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1503 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1504 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1505 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1506 #define QLCNIC_SET_QUIESCENT 0xadd00010
1507 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1508
1509 struct _cdrp_cmd {
1510 u32 num;
1511 u32 *arg;
1512 };
1513
1514 struct qlcnic_cmd_args {
1515 struct completion completion;
1516 struct list_head list;
1517 struct _cdrp_cmd req;
1518 struct _cdrp_cmd rsp;
1519 atomic_t rsp_status;
1520 int pay_size;
1521 u32 rsp_opcode;
1522 u32 total_cmds;
1523 u32 op_type;
1524 u32 type;
1525 u32 cmd_op;
1526 u32 *hdr; /* Back channel message header */
1527 u32 *pay; /* Back channel message payload */
1528 u8 func_num;
1529 };
1530
1531 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1532 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1533 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1534 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1535
1536 #define ADDR_IN_RANGE(addr, low, high) \
1537 (((addr) < (high)) && ((addr) >= (low)))
1538
1539 #define QLCRD32(adapter, off, err) \
1540 (adapter->ahw->hw_ops->read_reg)(adapter, off, err)
1541
1542 #define QLCWR32(adapter, off, val) \
1543 adapter->ahw->hw_ops->write_reg(adapter, off, val)
1544
1545 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1546 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1547
1548 #define qlcnic_rom_lock(a) \
1549 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1550 #define qlcnic_rom_unlock(a) \
1551 qlcnic_pcie_sem_unlock((a), 2)
1552 #define qlcnic_phy_lock(a) \
1553 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1554 #define qlcnic_phy_unlock(a) \
1555 qlcnic_pcie_sem_unlock((a), 3)
1556 #define qlcnic_sw_lock(a) \
1557 qlcnic_pcie_sem_lock((a), 6, 0)
1558 #define qlcnic_sw_unlock(a) \
1559 qlcnic_pcie_sem_unlock((a), 6)
1560 #define crb_win_lock(a) \
1561 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1562 #define crb_win_unlock(a) \
1563 qlcnic_pcie_sem_unlock((a), 7)
1564
1565 #define __QLCNIC_MAX_LED_RATE 0xf
1566 #define __QLCNIC_MAX_LED_STATE 0x2
1567
1568 #define MAX_CTL_CHECK 1000
1569
1570 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1571 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1572 int qlcnic_dump_fw(struct qlcnic_adapter *);
1573 int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *);
1574 bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *);
1575
1576 /* Functions from qlcnic_init.c */
1577 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int);
1578 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1579 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1580 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1581 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1582 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1583 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1584 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1585
1586 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1587 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1588 u8 *bytes, size_t size);
1589 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1590 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1591
1592 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32);
1593
1594 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1595 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1596
1597 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1598 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1599
1600 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1601 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1602 void qlcnic_release_tx_buffers(struct qlcnic_adapter *,
1603 struct qlcnic_host_tx_ring *);
1604
1605 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1606 void qlcnic_watchdog_task(struct work_struct *work);
1607 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1608 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id);
1609 void qlcnic_set_multi(struct net_device *netdev);
1610 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16);
1611 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *);
1612 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter);
1613 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *);
1614
1615 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1616 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32);
1617 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1618 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1619 netdev_features_t features);
1620 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1621 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1622 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *);
1623
1624 /* Functions from qlcnic_ethtool.c */
1625 int qlcnic_check_loopback_buff(unsigned char *, u8 []);
1626 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8);
1627
1628 /* Functions from qlcnic_main.c */
1629 int qlcnic_reset_context(struct qlcnic_adapter *);
1630 void qlcnic_diag_free_res(struct net_device *netdev, int);
1631 int qlcnic_diag_alloc_res(struct net_device *netdev, int);
1632 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *);
1633 void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8);
1634 void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8);
1635 int qlcnic_setup_rings(struct qlcnic_adapter *);
1636 int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int);
1637 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1638 int qlcnic_enable_msix(struct qlcnic_adapter *, u32);
1639 void qlcnic_set_drv_version(struct qlcnic_adapter *);
1640
1641 /* eSwitch management functions */
1642 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1643 struct qlcnic_esw_func_cfg *);
1644
1645 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1646 struct qlcnic_esw_func_cfg *);
1647 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1648 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1649 struct __qlcnic_esw_statistics *);
1650 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1651 struct __qlcnic_esw_statistics *);
1652 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1653 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1654
1655 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd);
1656
1657 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);
1658 void qlcnic_free_sds_rings(struct qlcnic_recv_context *);
1659 void qlcnic_advert_link_change(struct qlcnic_adapter *, int);
1660 void qlcnic_free_tx_rings(struct qlcnic_adapter *);
1661 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);
1662 void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1663
1664 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
1665 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
1666 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter);
1667 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter);
1668
1669 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
1670 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
1671 void qlcnic_set_vlan_config(struct qlcnic_adapter *,
1672 struct qlcnic_esw_func_cfg *);
1673 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *,
1674 struct qlcnic_esw_func_cfg *);
1675 int qlcnic_setup_tss_rss_intr(struct qlcnic_adapter *);
1676 void qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1677 int qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1678 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1679 void qlcnic_detach(struct qlcnic_adapter *);
1680 void qlcnic_teardown_intr(struct qlcnic_adapter *);
1681 int qlcnic_attach(struct qlcnic_adapter *);
1682 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1683 void qlcnic_restore_indev_addr(struct net_device *, unsigned long);
1684
1685 int qlcnic_check_temp(struct qlcnic_adapter *);
1686 int qlcnic_init_pci_info(struct qlcnic_adapter *);
1687 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *);
1688 int qlcnic_reset_npar_config(struct qlcnic_adapter *);
1689 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *);
1690 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
1691 int qlcnic_read_mac_addr(struct qlcnic_adapter *);
1692 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int);
1693 void qlcnic_set_netdev_features(struct qlcnic_adapter *,
1694 struct qlcnic_esw_func_cfg *);
1695 void qlcnic_sriov_vf_schedule_multi(struct net_device *);
1696 int qlcnic_is_valid_nic_func(struct qlcnic_adapter *, u8);
1697 int qlcnic_get_pci_func_type(struct qlcnic_adapter *, u16, u16 *, u16 *,
1698 u16 *);
1699
1700 /*
1701 * QLOGIC Board information
1702 */
1703
1704 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1705 struct qlcnic_board_info {
1706 unsigned short vendor;
1707 unsigned short device;
1708 unsigned short sub_vendor;
1709 unsigned short sub_device;
1710 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1711 };
1712
1713 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1714 {
1715 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1716 return tx_ring->sw_consumer - tx_ring->producer;
1717 else
1718 return tx_ring->sw_consumer + tx_ring->num_desc -
1719 tx_ring->producer;
1720 }
1721
1722 static inline int qlcnic_set_real_num_queues(struct qlcnic_adapter *adapter,
1723 struct net_device *netdev)
1724 {
1725 int err;
1726
1727 netdev->num_tx_queues = adapter->drv_tx_rings;
1728 netdev->real_num_tx_queues = adapter->drv_tx_rings;
1729
1730 err = netif_set_real_num_tx_queues(netdev, adapter->drv_tx_rings);
1731 if (err)
1732 netdev_err(netdev, "failed to set %d Tx queues\n",
1733 adapter->drv_tx_rings);
1734
1735 return err;
1736 }
1737
1738 struct qlcnic_nic_template {
1739 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1740 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1741 int (*start_firmware) (struct qlcnic_adapter *);
1742 int (*init_driver) (struct qlcnic_adapter *);
1743 void (*request_reset) (struct qlcnic_adapter *, u32);
1744 void (*cancel_idc_work) (struct qlcnic_adapter *);
1745 int (*napi_add)(struct qlcnic_adapter *, struct net_device *);
1746 void (*napi_del)(struct qlcnic_adapter *);
1747 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int);
1748 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *);
1749 int (*shutdown)(struct pci_dev *);
1750 int (*resume)(struct qlcnic_adapter *);
1751 };
1752
1753 struct qlcnic_mbx_ops {
1754 int (*enqueue_cmd) (struct qlcnic_adapter *,
1755 struct qlcnic_cmd_args *, unsigned long *);
1756 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1757 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1758 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1759 void (*nofity_fw) (struct qlcnic_adapter *, u8);
1760 };
1761
1762 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *);
1763 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *);
1764 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx);
1765 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx);
1766 void qlcnic_update_stats(struct qlcnic_adapter *);
1767
1768 /* Adapter hardware abstraction */
1769 struct qlcnic_hardware_ops {
1770 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1771 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1772 int (*read_reg) (struct qlcnic_adapter *, ulong, int *);
1773 int (*write_reg) (struct qlcnic_adapter *, ulong, u32);
1774 void (*get_ocm_win) (struct qlcnic_hardware_context *);
1775 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8);
1776 int (*setup_intr) (struct qlcnic_adapter *);
1777 int (*alloc_mbx_args)(struct qlcnic_cmd_args *,
1778 struct qlcnic_adapter *, u32);
1779 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1780 void (*get_func_no) (struct qlcnic_adapter *);
1781 int (*api_lock) (struct qlcnic_adapter *);
1782 void (*api_unlock) (struct qlcnic_adapter *);
1783 void (*add_sysfs) (struct qlcnic_adapter *);
1784 void (*remove_sysfs) (struct qlcnic_adapter *);
1785 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *);
1786 int (*create_rx_ctx) (struct qlcnic_adapter *);
1787 int (*create_tx_ctx) (struct qlcnic_adapter *,
1788 struct qlcnic_host_tx_ring *, int);
1789 void (*del_rx_ctx) (struct qlcnic_adapter *);
1790 void (*del_tx_ctx) (struct qlcnic_adapter *,
1791 struct qlcnic_host_tx_ring *);
1792 int (*setup_link_event) (struct qlcnic_adapter *, int);
1793 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8);
1794 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *);
1795 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *);
1796 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8);
1797 void (*napi_enable) (struct qlcnic_adapter *);
1798 void (*napi_disable) (struct qlcnic_adapter *);
1799 int (*config_intr_coal) (struct qlcnic_adapter *,
1800 struct ethtool_coalesce *);
1801 int (*config_rss) (struct qlcnic_adapter *, int);
1802 int (*config_hw_lro) (struct qlcnic_adapter *, int);
1803 int (*config_loopback) (struct qlcnic_adapter *, u8);
1804 int (*clear_loopback) (struct qlcnic_adapter *, u8);
1805 int (*config_promisc_mode) (struct qlcnic_adapter *, u32);
1806 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16);
1807 int (*get_board_info) (struct qlcnic_adapter *);
1808 void (*set_mac_filter_count) (struct qlcnic_adapter *);
1809 void (*free_mac_list) (struct qlcnic_adapter *);
1810 int (*read_phys_port_id) (struct qlcnic_adapter *);
1811 pci_ers_result_t (*io_error_detected) (struct pci_dev *,
1812 pci_channel_state_t);
1813 pci_ers_result_t (*io_slot_reset) (struct pci_dev *);
1814 void (*io_resume) (struct pci_dev *);
1815 void (*get_beacon_state)(struct qlcnic_adapter *);
1816 void (*enable_sds_intr) (struct qlcnic_adapter *,
1817 struct qlcnic_host_sds_ring *);
1818 void (*disable_sds_intr) (struct qlcnic_adapter *,
1819 struct qlcnic_host_sds_ring *);
1820 void (*enable_tx_intr) (struct qlcnic_adapter *,
1821 struct qlcnic_host_tx_ring *);
1822 void (*disable_tx_intr) (struct qlcnic_adapter *,
1823 struct qlcnic_host_tx_ring *);
1824 u32 (*get_saved_state)(void *, u32);
1825 void (*set_saved_state)(void *, u32, u32);
1826 void (*cache_tmpl_hdr_values)(struct qlcnic_fw_dump *);
1827 u32 (*get_cap_size)(void *, int);
1828 void (*set_sys_info)(void *, int, u32);
1829 void (*store_cap_mask)(void *, u32);
1830 };
1831
1832 extern struct qlcnic_nic_template qlcnic_vf_ops;
1833
1834 static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter)
1835 {
1836 return adapter->ahw->extra_capability[0] &
1837 QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD;
1838 }
1839
1840 static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter)
1841 {
1842 return adapter->ahw->extra_capability[0] &
1843 QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD;
1844 }
1845
1846 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter)
1847 {
1848 return adapter->nic_ops->start_firmware(adapter);
1849 }
1850
1851 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf,
1852 loff_t offset, size_t size)
1853 {
1854 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size);
1855 }
1856
1857 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf,
1858 loff_t offset, size_t size)
1859 {
1860 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size);
1861 }
1862
1863 static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter,
1864 ulong off, u32 data)
1865 {
1866 return adapter->ahw->hw_ops->write_reg(adapter, off, data);
1867 }
1868
1869 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter,
1870 u8 *mac, u8 function)
1871 {
1872 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function);
1873 }
1874
1875 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter)
1876 {
1877 return adapter->ahw->hw_ops->setup_intr(adapter);
1878 }
1879
1880 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
1881 struct qlcnic_adapter *adapter, u32 arg)
1882 {
1883 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg);
1884 }
1885
1886 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1887 struct qlcnic_cmd_args *cmd)
1888 {
1889 if (adapter->ahw->hw_ops->mbx_cmd)
1890 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd);
1891
1892 return -EIO;
1893 }
1894
1895 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter)
1896 {
1897 adapter->ahw->hw_ops->get_func_no(adapter);
1898 }
1899
1900 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter)
1901 {
1902 return adapter->ahw->hw_ops->api_lock(adapter);
1903 }
1904
1905 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter)
1906 {
1907 adapter->ahw->hw_ops->api_unlock(adapter);
1908 }
1909
1910 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter)
1911 {
1912 if (adapter->ahw->hw_ops->add_sysfs)
1913 adapter->ahw->hw_ops->add_sysfs(adapter);
1914 }
1915
1916 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter)
1917 {
1918 if (adapter->ahw->hw_ops->remove_sysfs)
1919 adapter->ahw->hw_ops->remove_sysfs(adapter);
1920 }
1921
1922 static inline void
1923 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
1924 {
1925 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring);
1926 }
1927
1928 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
1929 {
1930 return adapter->ahw->hw_ops->create_rx_ctx(adapter);
1931 }
1932
1933 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
1934 struct qlcnic_host_tx_ring *ptr,
1935 int ring)
1936 {
1937 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring);
1938 }
1939
1940 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
1941 {
1942 return adapter->ahw->hw_ops->del_rx_ctx(adapter);
1943 }
1944
1945 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
1946 struct qlcnic_host_tx_ring *ptr)
1947 {
1948 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr);
1949 }
1950
1951 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter,
1952 int enable)
1953 {
1954 return adapter->ahw->hw_ops->setup_link_event(adapter, enable);
1955 }
1956
1957 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter,
1958 struct qlcnic_info *info, u8 id)
1959 {
1960 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id);
1961 }
1962
1963 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter,
1964 struct qlcnic_pci_info *info)
1965 {
1966 return adapter->ahw->hw_ops->get_pci_info(adapter, info);
1967 }
1968
1969 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter,
1970 struct qlcnic_info *info)
1971 {
1972 return adapter->ahw->hw_ops->set_nic_info(adapter, info);
1973 }
1974
1975 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter,
1976 u8 *addr, u16 id, u8 cmd)
1977 {
1978 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd);
1979 }
1980
1981 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter,
1982 struct net_device *netdev)
1983 {
1984 return adapter->nic_ops->napi_add(adapter, netdev);
1985 }
1986
1987 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter)
1988 {
1989 adapter->nic_ops->napi_del(adapter);
1990 }
1991
1992 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter)
1993 {
1994 adapter->ahw->hw_ops->napi_enable(adapter);
1995 }
1996
1997 static inline int __qlcnic_shutdown(struct pci_dev *pdev)
1998 {
1999 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
2000
2001 return adapter->nic_ops->shutdown(pdev);
2002 }
2003
2004 static inline int __qlcnic_resume(struct qlcnic_adapter *adapter)
2005 {
2006 return adapter->nic_ops->resume(adapter);
2007 }
2008
2009 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter)
2010 {
2011 adapter->ahw->hw_ops->napi_disable(adapter);
2012 }
2013
2014 static inline int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter,
2015 struct ethtool_coalesce *ethcoal)
2016 {
2017 return adapter->ahw->hw_ops->config_intr_coal(adapter, ethcoal);
2018 }
2019
2020 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
2021 {
2022 return adapter->ahw->hw_ops->config_rss(adapter, enable);
2023 }
2024
2025 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter,
2026 int enable)
2027 {
2028 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable);
2029 }
2030
2031 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
2032 {
2033 return adapter->ahw->hw_ops->config_loopback(adapter, mode);
2034 }
2035
2036 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
2037 {
2038 return adapter->ahw->hw_ops->clear_loopback(adapter, mode);
2039 }
2040
2041 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter,
2042 u32 mode)
2043 {
2044 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode);
2045 }
2046
2047 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter,
2048 u64 *addr, u16 id)
2049 {
2050 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id);
2051 }
2052
2053 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
2054 {
2055 return adapter->ahw->hw_ops->get_board_info(adapter);
2056 }
2057
2058 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
2059 {
2060 return adapter->ahw->hw_ops->free_mac_list(adapter);
2061 }
2062
2063 static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter)
2064 {
2065 if (adapter->ahw->hw_ops->set_mac_filter_count)
2066 adapter->ahw->hw_ops->set_mac_filter_count(adapter);
2067 }
2068
2069 static inline void qlcnic_get_beacon_state(struct qlcnic_adapter *adapter)
2070 {
2071 adapter->ahw->hw_ops->get_beacon_state(adapter);
2072 }
2073
2074 static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter)
2075 {
2076 if (adapter->ahw->hw_ops->read_phys_port_id)
2077 adapter->ahw->hw_ops->read_phys_port_id(adapter);
2078 }
2079
2080 static inline u32 qlcnic_get_saved_state(struct qlcnic_adapter *adapter,
2081 void *t_hdr, u32 index)
2082 {
2083 return adapter->ahw->hw_ops->get_saved_state(t_hdr, index);
2084 }
2085
2086 static inline void qlcnic_set_saved_state(struct qlcnic_adapter *adapter,
2087 void *t_hdr, u32 index, u32 value)
2088 {
2089 adapter->ahw->hw_ops->set_saved_state(t_hdr, index, value);
2090 }
2091
2092 static inline void qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter *adapter,
2093 struct qlcnic_fw_dump *fw_dump)
2094 {
2095 adapter->ahw->hw_ops->cache_tmpl_hdr_values(fw_dump);
2096 }
2097
2098 static inline u32 qlcnic_get_cap_size(struct qlcnic_adapter *adapter,
2099 void *tmpl_hdr, int index)
2100 {
2101 return adapter->ahw->hw_ops->get_cap_size(tmpl_hdr, index);
2102 }
2103
2104 static inline void qlcnic_set_sys_info(struct qlcnic_adapter *adapter,
2105 void *tmpl_hdr, int idx, u32 value)
2106 {
2107 adapter->ahw->hw_ops->set_sys_info(tmpl_hdr, idx, value);
2108 }
2109
2110 static inline void qlcnic_store_cap_mask(struct qlcnic_adapter *adapter,
2111 void *tmpl_hdr, u32 mask)
2112 {
2113 adapter->ahw->hw_ops->store_cap_mask(tmpl_hdr, mask);
2114 }
2115
2116 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter,
2117 u32 key)
2118 {
2119 if (adapter->nic_ops->request_reset)
2120 adapter->nic_ops->request_reset(adapter, key);
2121 }
2122
2123 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter)
2124 {
2125 if (adapter->nic_ops->cancel_idc_work)
2126 adapter->nic_ops->cancel_idc_work(adapter);
2127 }
2128
2129 static inline irqreturn_t
2130 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter)
2131 {
2132 return adapter->nic_ops->clear_legacy_intr(adapter);
2133 }
2134
2135 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state,
2136 u32 rate)
2137 {
2138 return adapter->nic_ops->config_led(adapter, state, rate);
2139 }
2140
2141 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter,
2142 __be32 ip, int cmd)
2143 {
2144 adapter->nic_ops->config_ipaddr(adapter, ip, cmd);
2145 }
2146
2147 static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter)
2148 {
2149 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2150 }
2151
2152 static inline void
2153 qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2154 struct qlcnic_host_tx_ring *tx_ring)
2155 {
2156 if (qlcnic_check_multi_tx(adapter) &&
2157 !adapter->ahw->diag_test)
2158 writel(0x0, tx_ring->crb_intr_mask);
2159 }
2160
2161 static inline void
2162 qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2163 struct qlcnic_host_tx_ring *tx_ring)
2164 {
2165 if (qlcnic_check_multi_tx(adapter) &&
2166 !adapter->ahw->diag_test)
2167 writel(1, tx_ring->crb_intr_mask);
2168 }
2169
2170 static inline void
2171 qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2172 struct qlcnic_host_tx_ring *tx_ring)
2173 {
2174 writel(0, tx_ring->crb_intr_mask);
2175 }
2176
2177 static inline void
2178 qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2179 struct qlcnic_host_tx_ring *tx_ring)
2180 {
2181 writel(1, tx_ring->crb_intr_mask);
2182 }
2183
2184 /* Enable MSI-x and INT-x interrupts */
2185 static inline void
2186 qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2187 struct qlcnic_host_sds_ring *sds_ring)
2188 {
2189 writel(0, sds_ring->crb_intr_mask);
2190 }
2191
2192 /* Disable MSI-x and INT-x interrupts */
2193 static inline void
2194 qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2195 struct qlcnic_host_sds_ring *sds_ring)
2196 {
2197 writel(1, sds_ring->crb_intr_mask);
2198 }
2199
2200 static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter)
2201 {
2202 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2203 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
2204 }
2205
2206 /* When operating in a muti tx mode, driver needs to write 0x1
2207 * to src register, instead of 0x0 to disable receiving interrupt.
2208 */
2209 static inline void
2210 qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2211 struct qlcnic_host_sds_ring *sds_ring)
2212 {
2213 if (qlcnic_check_multi_tx(adapter) &&
2214 !adapter->ahw->diag_test &&
2215 (adapter->flags & QLCNIC_MSIX_ENABLED))
2216 writel(0x1, sds_ring->crb_intr_mask);
2217 else
2218 writel(0, sds_ring->crb_intr_mask);
2219 }
2220
2221 static inline void qlcnic_enable_sds_intr(struct qlcnic_adapter *adapter,
2222 struct qlcnic_host_sds_ring *sds_ring)
2223 {
2224 if (adapter->ahw->hw_ops->enable_sds_intr)
2225 adapter->ahw->hw_ops->enable_sds_intr(adapter, sds_ring);
2226 }
2227
2228 static inline void
2229 qlcnic_disable_sds_intr(struct qlcnic_adapter *adapter,
2230 struct qlcnic_host_sds_ring *sds_ring)
2231 {
2232 if (adapter->ahw->hw_ops->disable_sds_intr)
2233 adapter->ahw->hw_ops->disable_sds_intr(adapter, sds_ring);
2234 }
2235
2236 static inline void qlcnic_enable_tx_intr(struct qlcnic_adapter *adapter,
2237 struct qlcnic_host_tx_ring *tx_ring)
2238 {
2239 if (adapter->ahw->hw_ops->enable_tx_intr)
2240 adapter->ahw->hw_ops->enable_tx_intr(adapter, tx_ring);
2241 }
2242
2243 static inline void qlcnic_disable_tx_intr(struct qlcnic_adapter *adapter,
2244 struct qlcnic_host_tx_ring *tx_ring)
2245 {
2246 if (adapter->ahw->hw_ops->disable_tx_intr)
2247 adapter->ahw->hw_ops->disable_tx_intr(adapter, tx_ring);
2248 }
2249
2250 /* When operating in a muti tx mode, driver needs to write 0x0
2251 * to src register, instead of 0x1 to enable receiving interrupts.
2252 */
2253 static inline void
2254 qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2255 struct qlcnic_host_sds_ring *sds_ring)
2256 {
2257 if (qlcnic_check_multi_tx(adapter) &&
2258 !adapter->ahw->diag_test &&
2259 (adapter->flags & QLCNIC_MSIX_ENABLED))
2260 writel(0, sds_ring->crb_intr_mask);
2261 else
2262 writel(0x1, sds_ring->crb_intr_mask);
2263
2264 if (!QLCNIC_IS_MSI_FAMILY(adapter))
2265 writel(0xfbff, adapter->tgt_mask_reg);
2266 }
2267
2268 static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter)
2269 {
2270 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2271 }
2272
2273 static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter)
2274 {
2275 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2276 }
2277
2278 static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter)
2279 {
2280 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2281 }
2282
2283 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops;
2284 extern const struct ethtool_ops qlcnic_ethtool_ops;
2285 extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
2286
2287 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
2288 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \
2289 printk(KERN_INFO "%s: %s: " _fmt, \
2290 dev_name(&adapter->pdev->dev), \
2291 __func__, ##_args); \
2292 } while (0)
2293
2294 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020
2295 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030
2296 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430
2297 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040
2298 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440
2299
2300 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter)
2301 {
2302 unsigned short device = adapter->pdev->device;
2303 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false;
2304 }
2305
2306 static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter)
2307 {
2308 unsigned short device = adapter->pdev->device;
2309
2310 return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2311 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2312 }
2313
2314 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter)
2315 {
2316 unsigned short device = adapter->pdev->device;
2317 bool status;
2318
2319 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) ||
2320 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2321 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) ||
2322 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false;
2323
2324 return status;
2325 }
2326
2327 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter)
2328 {
2329 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false;
2330 }
2331
2332 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter)
2333 {
2334 unsigned short device = adapter->pdev->device;
2335 bool status;
2336
2337 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2338 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2339
2340 return status;
2341 }
2342
2343 static inline bool qlcnic_83xx_pf_check(struct qlcnic_adapter *adapter)
2344 {
2345 unsigned short device = adapter->pdev->device;
2346
2347 return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false;
2348 }
2349
2350 static inline bool qlcnic_83xx_vf_check(struct qlcnic_adapter *adapter)
2351 {
2352 unsigned short device = adapter->pdev->device;
2353
2354 return (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ? true : false;
2355 }
2356
2357 static inline u32 qlcnic_get_vnic_func_count(struct qlcnic_adapter *adapter)
2358 {
2359 if (qlcnic_84xx_check(adapter))
2360 return QLC_84XX_VNIC_COUNT;
2361 else
2362 return QLC_DEFAULT_VNIC_COUNT;
2363 }
2364 #endif /* __QLCNIC_H_ */
Linux kernel - Deliverables
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