projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'pci/resource' into next
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/aer.h>
15
16 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
17 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
18 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
19 struct qlcnic_cmd_args *);
20 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
21 static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
22 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
23 pci_channel_state_t);
24 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
25 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
26 static void qlcnic_83xx_io_resume(struct pci_dev *);
27 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
28 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
29 static int qlcnic_83xx_resume(struct qlcnic_adapter *);
30 static int qlcnic_83xx_shutdown(struct pci_dev *);
31 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
32
33 #define RSS_HASHTYPE_IP_TCP 0x3
34 #define QLC_83XX_FW_MBX_CMD 0
35 #define QLC_SKIP_INACTIVE_PCI_REGS 7
36
37 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
38 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
39 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
40 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
41 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
42 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
43 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
44 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
45 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
46 {QLCNIC_CMD_SET_MTU, 3, 1},
47 {QLCNIC_CMD_READ_PHY, 4, 2},
48 {QLCNIC_CMD_WRITE_PHY, 5, 1},
49 {QLCNIC_CMD_READ_HW_REG, 4, 1},
50 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
51 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
52 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
53 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
54 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
55 {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
56 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
57 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
58 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
59 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
60 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
61 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
62 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
63 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
64 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
65 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
66 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
67 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
68 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
69 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
70 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
71 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
72 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
73 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
74 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
75 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
76 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
77 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
78 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
79 {QLCNIC_CMD_IDC_ACK, 5, 1},
80 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
81 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
82 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
83 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
84 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
85 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
86 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
87 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
88 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
89 {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
90 };
91
92 const u32 qlcnic_83xx_ext_reg_tbl[] = {
93 0x38CC, /* Global Reset */
94 0x38F0, /* Wildcard */
95 0x38FC, /* Informant */
96 0x3038, /* Host MBX ctrl */
97 0x303C, /* FW MBX ctrl */
98 0x355C, /* BOOT LOADER ADDRESS REG */
99 0x3560, /* BOOT LOADER SIZE REG */
100 0x3564, /* FW IMAGE ADDR REG */
101 0x1000, /* MBX intr enable */
102 0x1200, /* Default Intr mask */
103 0x1204, /* Default Interrupt ID */
104 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
105 0x3784, /* QLC_83XX_IDC_DEV_STATE */
106 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
107 0x378C, /* QLC_83XX_IDC_DRV_ACK */
108 0x3790, /* QLC_83XX_IDC_CTRL */
109 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
110 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
111 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
112 0x37A0, /* QLC_83XX_IDC_PF_0 */
113 0x37A4, /* QLC_83XX_IDC_PF_1 */
114 0x37A8, /* QLC_83XX_IDC_PF_2 */
115 0x37AC, /* QLC_83XX_IDC_PF_3 */
116 0x37B0, /* QLC_83XX_IDC_PF_4 */
117 0x37B4, /* QLC_83XX_IDC_PF_5 */
118 0x37B8, /* QLC_83XX_IDC_PF_6 */
119 0x37BC, /* QLC_83XX_IDC_PF_7 */
120 0x37C0, /* QLC_83XX_IDC_PF_8 */
121 0x37C4, /* QLC_83XX_IDC_PF_9 */
122 0x37C8, /* QLC_83XX_IDC_PF_10 */
123 0x37CC, /* QLC_83XX_IDC_PF_11 */
124 0x37D0, /* QLC_83XX_IDC_PF_12 */
125 0x37D4, /* QLC_83XX_IDC_PF_13 */
126 0x37D8, /* QLC_83XX_IDC_PF_14 */
127 0x37DC, /* QLC_83XX_IDC_PF_15 */
128 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
129 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
130 0x37F0, /* QLC_83XX_DRV_OP_MODE */
131 0x37F4, /* QLC_83XX_VNIC_STATE */
132 0x3868, /* QLC_83XX_DRV_LOCK */
133 0x386C, /* QLC_83XX_DRV_UNLOCK */
134 0x3504, /* QLC_83XX_DRV_LOCK_ID */
135 0x34A4, /* QLC_83XX_ASIC_TEMP */
136 };
137
138 const u32 qlcnic_83xx_reg_tbl[] = {
139 0x34A8, /* PEG_HALT_STAT1 */
140 0x34AC, /* PEG_HALT_STAT2 */
141 0x34B0, /* FW_HEARTBEAT */
142 0x3500, /* FLASH LOCK_ID */
143 0x3528, /* FW_CAPABILITIES */
144 0x3538, /* Driver active, DRV_REG0 */
145 0x3540, /* Device state, DRV_REG1 */
146 0x3544, /* Driver state, DRV_REG2 */
147 0x3548, /* Driver scratch, DRV_REG3 */
148 0x354C, /* Device partiton info, DRV_REG4 */
149 0x3524, /* Driver IDC ver, DRV_REG5 */
150 0x3550, /* FW_VER_MAJOR */
151 0x3554, /* FW_VER_MINOR */
152 0x3558, /* FW_VER_SUB */
153 0x359C, /* NPAR STATE */
154 0x35FC, /* FW_IMG_VALID */
155 0x3650, /* CMD_PEG_STATE */
156 0x373C, /* RCV_PEG_STATE */
157 0x37B4, /* ASIC TEMP */
158 0x356C, /* FW API */
159 0x3570, /* DRV OP MODE */
160 0x3850, /* FLASH LOCK */
161 0x3854, /* FLASH UNLOCK */
162 };
163
164 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
165 .read_crb = qlcnic_83xx_read_crb,
166 .write_crb = qlcnic_83xx_write_crb,
167 .read_reg = qlcnic_83xx_rd_reg_indirect,
168 .write_reg = qlcnic_83xx_wrt_reg_indirect,
169 .get_mac_address = qlcnic_83xx_get_mac_address,
170 .setup_intr = qlcnic_83xx_setup_intr,
171 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
172 .mbx_cmd = qlcnic_83xx_issue_cmd,
173 .get_func_no = qlcnic_83xx_get_func_no,
174 .api_lock = qlcnic_83xx_cam_lock,
175 .api_unlock = qlcnic_83xx_cam_unlock,
176 .add_sysfs = qlcnic_83xx_add_sysfs,
177 .remove_sysfs = qlcnic_83xx_remove_sysfs,
178 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
179 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
180 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
181 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
182 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
183 .setup_link_event = qlcnic_83xx_setup_link_event,
184 .get_nic_info = qlcnic_83xx_get_nic_info,
185 .get_pci_info = qlcnic_83xx_get_pci_info,
186 .set_nic_info = qlcnic_83xx_set_nic_info,
187 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
188 .napi_enable = qlcnic_83xx_napi_enable,
189 .napi_disable = qlcnic_83xx_napi_disable,
190 .config_intr_coal = qlcnic_83xx_config_intr_coal,
191 .config_rss = qlcnic_83xx_config_rss,
192 .config_hw_lro = qlcnic_83xx_config_hw_lro,
193 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
194 .change_l2_filter = qlcnic_83xx_change_l2_filter,
195 .get_board_info = qlcnic_83xx_get_port_info,
196 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
197 .free_mac_list = qlcnic_82xx_free_mac_list,
198 .io_error_detected = qlcnic_83xx_io_error_detected,
199 .io_slot_reset = qlcnic_83xx_io_slot_reset,
200 .io_resume = qlcnic_83xx_io_resume,
201 .get_beacon_state = qlcnic_83xx_get_beacon_state,
202 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
203 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
204 .enable_tx_intr = qlcnic_83xx_enable_tx_intr,
205 .disable_tx_intr = qlcnic_83xx_disable_tx_intr,
206
207 };
208
209 static struct qlcnic_nic_template qlcnic_83xx_ops = {
210 .config_bridged_mode = qlcnic_config_bridged_mode,
211 .config_led = qlcnic_config_led,
212 .request_reset = qlcnic_83xx_idc_request_reset,
213 .cancel_idc_work = qlcnic_83xx_idc_exit,
214 .napi_add = qlcnic_83xx_napi_add,
215 .napi_del = qlcnic_83xx_napi_del,
216 .config_ipaddr = qlcnic_83xx_config_ipaddr,
217 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
218 .shutdown = qlcnic_83xx_shutdown,
219 .resume = qlcnic_83xx_resume,
220 };
221
222 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
223 {
224 ahw->hw_ops = &qlcnic_83xx_hw_ops;
225 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
226 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
227 }
228
229 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
230 {
231 u32 fw_major, fw_minor, fw_build;
232 struct pci_dev *pdev = adapter->pdev;
233
234 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
235 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
236 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
237 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
238
239 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
240 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
241
242 return adapter->fw_version;
243 }
244
245 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
246 {
247 void __iomem *base;
248 u32 val;
249
250 base = adapter->ahw->pci_base0 +
251 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
252 writel(addr, base);
253 val = readl(base);
254 if (val != addr)
255 return -EIO;
256
257 return 0;
258 }
259
260 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
261 int *err)
262 {
263 struct qlcnic_hardware_context *ahw = adapter->ahw;
264
265 *err = __qlcnic_set_win_base(adapter, (u32) addr);
266 if (!*err) {
267 return QLCRDX(ahw, QLCNIC_WILDCARD);
268 } else {
269 dev_err(&adapter->pdev->dev,
270 "%s failed, addr = 0x%lx\n", __func__, addr);
271 return -EIO;
272 }
273 }
274
275 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
276 u32 data)
277 {
278 int err;
279 struct qlcnic_hardware_context *ahw = adapter->ahw;
280
281 err = __qlcnic_set_win_base(adapter, (u32) addr);
282 if (!err) {
283 QLCWRX(ahw, QLCNIC_WILDCARD, data);
284 return 0;
285 } else {
286 dev_err(&adapter->pdev->dev,
287 "%s failed, addr = 0x%x data = 0x%x\n",
288 __func__, (int)addr, data);
289 return err;
290 }
291 }
292
293 static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter)
294 {
295 struct qlcnic_hardware_context *ahw = adapter->ahw;
296
297 /* MSI-X enablement failed, use legacy interrupt */
298 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
299 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
300 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
301 adapter->msix_entries[0].vector = adapter->pdev->irq;
302 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
303 }
304
305 static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter)
306 {
307 int num_msix;
308
309 num_msix = adapter->drv_sds_rings;
310
311 /* account for AEN interrupt MSI-X based interrupts */
312 num_msix += 1;
313
314 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
315 num_msix += adapter->drv_tx_rings;
316
317 return num_msix;
318 }
319
320 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
321 {
322 struct qlcnic_hardware_context *ahw = adapter->ahw;
323 int err, i, num_msix;
324
325 if (adapter->flags & QLCNIC_TSS_RSS) {
326 err = qlcnic_setup_tss_rss_intr(adapter);
327 if (err < 0)
328 return err;
329 num_msix = ahw->num_msix;
330 } else {
331 num_msix = qlcnic_83xx_calculate_msix_vector(adapter);
332
333 err = qlcnic_enable_msix(adapter, num_msix);
334 if (err == -ENOMEM)
335 return err;
336
337 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
338 num_msix = ahw->num_msix;
339 } else {
340 if (qlcnic_sriov_vf_check(adapter))
341 return -EINVAL;
342 num_msix = 1;
343 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
344 }
345 }
346
347 /* setup interrupt mapping table for fw */
348 ahw->intr_tbl = vzalloc(num_msix *
349 sizeof(struct qlcnic_intrpt_config));
350 if (!ahw->intr_tbl)
351 return -ENOMEM;
352
353 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
354 qlcnic_83xx_enable_legacy(adapter);
355
356 for (i = 0; i < num_msix; i++) {
357 if (adapter->flags & QLCNIC_MSIX_ENABLED)
358 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
359 else
360 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
361 ahw->intr_tbl[i].id = i;
362 ahw->intr_tbl[i].src = 0;
363 }
364
365 return 0;
366 }
367
368 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
369 {
370 writel(0, adapter->tgt_mask_reg);
371 }
372
373 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
374 {
375 if (adapter->tgt_mask_reg)
376 writel(1, adapter->tgt_mask_reg);
377 }
378
379 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
380 *adapter)
381 {
382 u32 mask;
383
384 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
385 * source register. We could be here before contexts are created
386 * and sds_ring->crb_intr_mask has not been initialized, calculate
387 * BAR offset for Interrupt Source Register
388 */
389 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
390 writel(0, adapter->ahw->pci_base0 + mask);
391 }
392
393 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
394 {
395 u32 mask;
396
397 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
398 writel(1, adapter->ahw->pci_base0 + mask);
399 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
400 }
401
402 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
403 struct qlcnic_cmd_args *cmd)
404 {
405 int i;
406
407 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
408 return;
409
410 for (i = 0; i < cmd->rsp.num; i++)
411 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
412 }
413
414 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
415 {
416 u32 intr_val;
417 struct qlcnic_hardware_context *ahw = adapter->ahw;
418 int retries = 0;
419
420 intr_val = readl(adapter->tgt_status_reg);
421
422 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
423 return IRQ_NONE;
424
425 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
426 adapter->stats.spurious_intr++;
427 return IRQ_NONE;
428 }
429 /* The barrier is required to ensure writes to the registers */
430 wmb();
431
432 /* clear the interrupt trigger control register */
433 writel(0, adapter->isr_int_vec);
434 intr_val = readl(adapter->isr_int_vec);
435 do {
436 intr_val = readl(adapter->tgt_status_reg);
437 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
438 break;
439 retries++;
440 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
441 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
442
443 return IRQ_HANDLED;
444 }
445
446 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
447 {
448 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
449 complete(&mbx->completion);
450 }
451
452 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
453 {
454 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
455 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
456 unsigned long flags;
457
458 spin_lock_irqsave(&mbx->aen_lock, flags);
459 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
460 if (!(resp & QLCNIC_SET_OWNER))
461 goto out;
462
463 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
464 if (event & QLCNIC_MBX_ASYNC_EVENT) {
465 __qlcnic_83xx_process_aen(adapter);
466 } else {
467 if (atomic_read(&mbx->rsp_status) != rsp_status)
468 qlcnic_83xx_notify_mbx_response(mbx);
469 }
470 out:
471 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
472 spin_unlock_irqrestore(&mbx->aen_lock, flags);
473 }
474
475 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
476 {
477 struct qlcnic_adapter *adapter = data;
478 struct qlcnic_host_sds_ring *sds_ring;
479 struct qlcnic_hardware_context *ahw = adapter->ahw;
480
481 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
482 return IRQ_NONE;
483
484 qlcnic_83xx_poll_process_aen(adapter);
485
486 if (ahw->diag_test) {
487 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
488 ahw->diag_cnt++;
489 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
490 return IRQ_HANDLED;
491 }
492
493 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
494 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
495 } else {
496 sds_ring = &adapter->recv_ctx->sds_rings[0];
497 napi_schedule(&sds_ring->napi);
498 }
499
500 return IRQ_HANDLED;
501 }
502
503 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
504 {
505 struct qlcnic_host_sds_ring *sds_ring = data;
506 struct qlcnic_adapter *adapter = sds_ring->adapter;
507
508 if (adapter->flags & QLCNIC_MSIX_ENABLED)
509 goto done;
510
511 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
512 return IRQ_NONE;
513
514 done:
515 adapter->ahw->diag_cnt++;
516 qlcnic_enable_sds_intr(adapter, sds_ring);
517
518 return IRQ_HANDLED;
519 }
520
521 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
522 {
523 u32 num_msix;
524
525 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
526 qlcnic_83xx_set_legacy_intr_mask(adapter);
527
528 qlcnic_83xx_disable_mbx_intr(adapter);
529
530 if (adapter->flags & QLCNIC_MSIX_ENABLED)
531 num_msix = adapter->ahw->num_msix - 1;
532 else
533 num_msix = 0;
534
535 msleep(20);
536
537 if (adapter->msix_entries) {
538 synchronize_irq(adapter->msix_entries[num_msix].vector);
539 free_irq(adapter->msix_entries[num_msix].vector, adapter);
540 }
541 }
542
543 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
544 {
545 irq_handler_t handler;
546 u32 val;
547 int err = 0;
548 unsigned long flags = 0;
549
550 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
551 !(adapter->flags & QLCNIC_MSIX_ENABLED))
552 flags |= IRQF_SHARED;
553
554 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
555 handler = qlcnic_83xx_handle_aen;
556 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
557 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
558 if (err) {
559 dev_err(&adapter->pdev->dev,
560 "failed to register MBX interrupt\n");
561 return err;
562 }
563 } else {
564 handler = qlcnic_83xx_intr;
565 val = adapter->msix_entries[0].vector;
566 err = request_irq(val, handler, flags, "qlcnic", adapter);
567 if (err) {
568 dev_err(&adapter->pdev->dev,
569 "failed to register INTx interrupt\n");
570 return err;
571 }
572 qlcnic_83xx_clear_legacy_intr_mask(adapter);
573 }
574
575 /* Enable mailbox interrupt */
576 qlcnic_83xx_enable_mbx_interrupt(adapter);
577
578 return err;
579 }
580
581 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
582 {
583 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
584 adapter->ahw->pci_func = (val >> 24) & 0xff;
585 }
586
587 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
588 {
589 void __iomem *addr;
590 u32 val, limit = 0;
591
592 struct qlcnic_hardware_context *ahw = adapter->ahw;
593
594 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
595 do {
596 val = readl(addr);
597 if (val) {
598 /* write the function number to register */
599 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
600 ahw->pci_func);
601 return 0;
602 }
603 usleep_range(1000, 2000);
604 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
605
606 return -EIO;
607 }
608
609 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
610 {
611 void __iomem *addr;
612 u32 val;
613 struct qlcnic_hardware_context *ahw = adapter->ahw;
614
615 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
616 val = readl(addr);
617 }
618
619 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
620 loff_t offset, size_t size)
621 {
622 int ret = 0;
623 u32 data;
624
625 if (qlcnic_api_lock(adapter)) {
626 dev_err(&adapter->pdev->dev,
627 "%s: failed to acquire lock. addr offset 0x%x\n",
628 __func__, (u32)offset);
629 return;
630 }
631
632 data = QLCRD32(adapter, (u32) offset, &ret);
633 qlcnic_api_unlock(adapter);
634
635 if (ret == -EIO) {
636 dev_err(&adapter->pdev->dev,
637 "%s: failed. addr offset 0x%x\n",
638 __func__, (u32)offset);
639 return;
640 }
641 memcpy(buf, &data, size);
642 }
643
644 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
645 loff_t offset, size_t size)
646 {
647 u32 data;
648
649 memcpy(&data, buf, size);
650 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
651 }
652
653 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
654 {
655 int status;
656
657 status = qlcnic_83xx_get_port_config(adapter);
658 if (status) {
659 dev_err(&adapter->pdev->dev,
660 "Get Port Info failed\n");
661 } else {
662 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
663 adapter->ahw->port_type = QLCNIC_XGBE;
664 else
665 adapter->ahw->port_type = QLCNIC_GBE;
666
667 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
668 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
669 }
670 return status;
671 }
672
673 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
674 {
675 struct qlcnic_hardware_context *ahw = adapter->ahw;
676 u16 act_pci_fn = ahw->total_nic_func;
677 u16 count;
678
679 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
680 if (act_pci_fn <= 2)
681 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
682 act_pci_fn;
683 else
684 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
685 act_pci_fn;
686 ahw->max_uc_count = count;
687 }
688
689 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
690 {
691 u32 val;
692
693 if (adapter->flags & QLCNIC_MSIX_ENABLED)
694 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
695 else
696 val = BIT_2;
697
698 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
699 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
700 }
701
702 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
703 const struct pci_device_id *ent)
704 {
705 u32 op_mode, priv_level;
706 struct qlcnic_hardware_context *ahw = adapter->ahw;
707
708 ahw->fw_hal_version = 2;
709 qlcnic_get_func_no(adapter);
710
711 if (qlcnic_sriov_vf_check(adapter)) {
712 qlcnic_sriov_vf_set_ops(adapter);
713 return;
714 }
715
716 /* Determine function privilege level */
717 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
718 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
719 priv_level = QLCNIC_MGMT_FUNC;
720 else
721 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
722 ahw->pci_func);
723
724 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
725 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
726 dev_info(&adapter->pdev->dev,
727 "HAL Version: %d Non Privileged function\n",
728 ahw->fw_hal_version);
729 adapter->nic_ops = &qlcnic_vf_ops;
730 } else {
731 if (pci_find_ext_capability(adapter->pdev,
732 PCI_EXT_CAP_ID_SRIOV))
733 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
734 adapter->nic_ops = &qlcnic_83xx_ops;
735 }
736 }
737
738 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
739 u32 data[]);
740 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
741 u32 data[]);
742
743 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
744 struct qlcnic_cmd_args *cmd)
745 {
746 int i;
747
748 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
749 return;
750
751 dev_info(&adapter->pdev->dev,
752 "Host MBX regs(%d)\n", cmd->req.num);
753 for (i = 0; i < cmd->req.num; i++) {
754 if (i && !(i % 8))
755 pr_info("\n");
756 pr_info("%08x ", cmd->req.arg[i]);
757 }
758 pr_info("\n");
759 dev_info(&adapter->pdev->dev,
760 "FW MBX regs(%d)\n", cmd->rsp.num);
761 for (i = 0; i < cmd->rsp.num; i++) {
762 if (i && !(i % 8))
763 pr_info("\n");
764 pr_info("%08x ", cmd->rsp.arg[i]);
765 }
766 pr_info("\n");
767 }
768
769 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
770 struct qlcnic_cmd_args *cmd)
771 {
772 struct qlcnic_hardware_context *ahw = adapter->ahw;
773 int opcode = LSW(cmd->req.arg[0]);
774 unsigned long max_loops;
775
776 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
777
778 for (; max_loops; max_loops--) {
779 if (atomic_read(&cmd->rsp_status) ==
780 QLC_83XX_MBX_RESPONSE_ARRIVED)
781 return;
782
783 udelay(1);
784 }
785
786 dev_err(&adapter->pdev->dev,
787 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
788 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
789 flush_workqueue(ahw->mailbox->work_q);
790 return;
791 }
792
793 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
794 struct qlcnic_cmd_args *cmd)
795 {
796 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
797 struct qlcnic_hardware_context *ahw = adapter->ahw;
798 int cmd_type, err, opcode;
799 unsigned long timeout;
800
801 if (!mbx)
802 return -EIO;
803
804 opcode = LSW(cmd->req.arg[0]);
805 cmd_type = cmd->type;
806 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
807 if (err) {
808 dev_err(&adapter->pdev->dev,
809 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
810 __func__, opcode, cmd->type, ahw->pci_func,
811 ahw->op_mode);
812 return err;
813 }
814
815 switch (cmd_type) {
816 case QLC_83XX_MBX_CMD_WAIT:
817 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
818 dev_err(&adapter->pdev->dev,
819 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
820 __func__, opcode, cmd_type, ahw->pci_func,
821 ahw->op_mode);
822 flush_workqueue(mbx->work_q);
823 }
824 break;
825 case QLC_83XX_MBX_CMD_NO_WAIT:
826 return 0;
827 case QLC_83XX_MBX_CMD_BUSY_WAIT:
828 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
829 break;
830 default:
831 dev_err(&adapter->pdev->dev,
832 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
833 __func__, opcode, cmd_type, ahw->pci_func,
834 ahw->op_mode);
835 qlcnic_83xx_detach_mailbox_work(adapter);
836 }
837
838 return cmd->rsp_opcode;
839 }
840
841 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
842 struct qlcnic_adapter *adapter, u32 type)
843 {
844 int i, size;
845 u32 temp;
846 const struct qlcnic_mailbox_metadata *mbx_tbl;
847
848 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
849 mbx_tbl = qlcnic_83xx_mbx_tbl;
850 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
851 for (i = 0; i < size; i++) {
852 if (type == mbx_tbl[i].cmd) {
853 mbx->op_type = QLC_83XX_FW_MBX_CMD;
854 mbx->req.num = mbx_tbl[i].in_args;
855 mbx->rsp.num = mbx_tbl[i].out_args;
856 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
857 GFP_ATOMIC);
858 if (!mbx->req.arg)
859 return -ENOMEM;
860 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
861 GFP_ATOMIC);
862 if (!mbx->rsp.arg) {
863 kfree(mbx->req.arg);
864 mbx->req.arg = NULL;
865 return -ENOMEM;
866 }
867 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
868 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
869 temp = adapter->ahw->fw_hal_version << 29;
870 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
871 mbx->cmd_op = type;
872 return 0;
873 }
874 }
875 return -EINVAL;
876 }
877
878 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
879 {
880 struct qlcnic_adapter *adapter;
881 struct qlcnic_cmd_args cmd;
882 int i, err = 0;
883
884 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
885 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
886 if (err)
887 return;
888
889 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
890 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
891
892 err = qlcnic_issue_cmd(adapter, &cmd);
893 if (err)
894 dev_info(&adapter->pdev->dev,
895 "%s: Mailbox IDC ACK failed.\n", __func__);
896 qlcnic_free_mbx_args(&cmd);
897 }
898
899 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
900 u32 data[])
901 {
902 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
903 QLCNIC_MBX_RSP(data[0]));
904 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
905 return;
906 }
907
908 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
909 {
910 struct qlcnic_hardware_context *ahw = adapter->ahw;
911 u32 event[QLC_83XX_MBX_AEN_CNT];
912 int i;
913
914 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
915 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
916
917 switch (QLCNIC_MBX_RSP(event[0])) {
918
919 case QLCNIC_MBX_LINK_EVENT:
920 qlcnic_83xx_handle_link_aen(adapter, event);
921 break;
922 case QLCNIC_MBX_COMP_EVENT:
923 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
924 break;
925 case QLCNIC_MBX_REQUEST_EVENT:
926 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
927 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
928 queue_delayed_work(adapter->qlcnic_wq,
929 &adapter->idc_aen_work, 0);
930 break;
931 case QLCNIC_MBX_TIME_EXTEND_EVENT:
932 ahw->extend_lb_time = event[1] >> 8 & 0xf;
933 break;
934 case QLCNIC_MBX_BC_EVENT:
935 qlcnic_sriov_handle_bc_event(adapter, event[1]);
936 break;
937 case QLCNIC_MBX_SFP_INSERT_EVENT:
938 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
939 QLCNIC_MBX_RSP(event[0]));
940 break;
941 case QLCNIC_MBX_SFP_REMOVE_EVENT:
942 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
943 QLCNIC_MBX_RSP(event[0]));
944 break;
945 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
946 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
947 break;
948 default:
949 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
950 QLCNIC_MBX_RSP(event[0]));
951 break;
952 }
953
954 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
955 }
956
957 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
958 {
959 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
960 struct qlcnic_hardware_context *ahw = adapter->ahw;
961 struct qlcnic_mailbox *mbx = ahw->mailbox;
962 unsigned long flags;
963
964 spin_lock_irqsave(&mbx->aen_lock, flags);
965 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
966 if (resp & QLCNIC_SET_OWNER) {
967 event = readl(QLCNIC_MBX_FW(ahw, 0));
968 if (event & QLCNIC_MBX_ASYNC_EVENT) {
969 __qlcnic_83xx_process_aen(adapter);
970 } else {
971 if (atomic_read(&mbx->rsp_status) != rsp_status)
972 qlcnic_83xx_notify_mbx_response(mbx);
973 }
974 }
975 spin_unlock_irqrestore(&mbx->aen_lock, flags);
976 }
977
978 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
979 {
980 struct qlcnic_adapter *adapter;
981
982 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
983
984 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
985 return;
986
987 qlcnic_83xx_process_aen(adapter);
988 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
989 (HZ / 10));
990 }
991
992 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
993 {
994 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
995 return;
996
997 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
998 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
999 }
1000
1001 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
1002 {
1003 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1004 return;
1005 cancel_delayed_work_sync(&adapter->mbx_poll_work);
1006 }
1007
1008 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
1009 {
1010 int index, i, err, sds_mbx_size;
1011 u32 *buf, intrpt_id, intr_mask;
1012 u16 context_id;
1013 u8 num_sds;
1014 struct qlcnic_cmd_args cmd;
1015 struct qlcnic_host_sds_ring *sds;
1016 struct qlcnic_sds_mbx sds_mbx;
1017 struct qlcnic_add_rings_mbx_out *mbx_out;
1018 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1019 struct qlcnic_hardware_context *ahw = adapter->ahw;
1020
1021 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1022 context_id = recv_ctx->context_id;
1023 num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
1024 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1025 QLCNIC_CMD_ADD_RCV_RINGS);
1026 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1027
1028 /* set up status rings, mbx 2-81 */
1029 index = 2;
1030 for (i = 8; i < adapter->drv_sds_rings; i++) {
1031 memset(&sds_mbx, 0, sds_mbx_size);
1032 sds = &recv_ctx->sds_rings[i];
1033 sds->consumer = 0;
1034 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1035 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1036 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1037 sds_mbx.sds_ring_size = sds->num_desc;
1038
1039 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1040 intrpt_id = ahw->intr_tbl[i].id;
1041 else
1042 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1043
1044 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1045 sds_mbx.intrpt_id = intrpt_id;
1046 else
1047 sds_mbx.intrpt_id = 0xffff;
1048 sds_mbx.intrpt_val = 0;
1049 buf = &cmd.req.arg[index];
1050 memcpy(buf, &sds_mbx, sds_mbx_size);
1051 index += sds_mbx_size / sizeof(u32);
1052 }
1053
1054 /* send the mailbox command */
1055 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1056 if (err) {
1057 dev_err(&adapter->pdev->dev,
1058 "Failed to add rings %d\n", err);
1059 goto out;
1060 }
1061
1062 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1063 index = 0;
1064 /* status descriptor ring */
1065 for (i = 8; i < adapter->drv_sds_rings; i++) {
1066 sds = &recv_ctx->sds_rings[i];
1067 sds->crb_sts_consumer = ahw->pci_base0 +
1068 mbx_out->host_csmr[index];
1069 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1070 intr_mask = ahw->intr_tbl[i].src;
1071 else
1072 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1073
1074 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1075 index++;
1076 }
1077 out:
1078 qlcnic_free_mbx_args(&cmd);
1079 return err;
1080 }
1081
1082 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1083 {
1084 int err;
1085 u32 temp = 0;
1086 struct qlcnic_cmd_args cmd;
1087 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1088
1089 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1090 return;
1091
1092 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1093 cmd.req.arg[0] |= (0x3 << 29);
1094
1095 if (qlcnic_sriov_pf_check(adapter))
1096 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1097
1098 cmd.req.arg[1] = recv_ctx->context_id | temp;
1099 err = qlcnic_issue_cmd(adapter, &cmd);
1100 if (err)
1101 dev_err(&adapter->pdev->dev,
1102 "Failed to destroy rx ctx in firmware\n");
1103
1104 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1105 qlcnic_free_mbx_args(&cmd);
1106 }
1107
1108 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1109 {
1110 int i, err, index, sds_mbx_size, rds_mbx_size;
1111 u8 num_sds, num_rds;
1112 u32 *buf, intrpt_id, intr_mask, cap = 0;
1113 struct qlcnic_host_sds_ring *sds;
1114 struct qlcnic_host_rds_ring *rds;
1115 struct qlcnic_sds_mbx sds_mbx;
1116 struct qlcnic_rds_mbx rds_mbx;
1117 struct qlcnic_cmd_args cmd;
1118 struct qlcnic_rcv_mbx_out *mbx_out;
1119 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1120 struct qlcnic_hardware_context *ahw = adapter->ahw;
1121 num_rds = adapter->max_rds_rings;
1122
1123 if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1124 num_sds = adapter->drv_sds_rings;
1125 else
1126 num_sds = QLCNIC_MAX_SDS_RINGS;
1127
1128 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1129 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1130 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1131
1132 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1133 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1134
1135 /* set mailbox hdr and capabilities */
1136 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1137 QLCNIC_CMD_CREATE_RX_CTX);
1138 if (err)
1139 return err;
1140
1141 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1142 cmd.req.arg[0] |= (0x3 << 29);
1143
1144 cmd.req.arg[1] = cap;
1145 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1146 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1147
1148 if (qlcnic_sriov_pf_check(adapter))
1149 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1150 &cmd.req.arg[6]);
1151 /* set up status rings, mbx 8-57/87 */
1152 index = QLC_83XX_HOST_SDS_MBX_IDX;
1153 for (i = 0; i < num_sds; i++) {
1154 memset(&sds_mbx, 0, sds_mbx_size);
1155 sds = &recv_ctx->sds_rings[i];
1156 sds->consumer = 0;
1157 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1158 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1159 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1160 sds_mbx.sds_ring_size = sds->num_desc;
1161 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1162 intrpt_id = ahw->intr_tbl[i].id;
1163 else
1164 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1165 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1166 sds_mbx.intrpt_id = intrpt_id;
1167 else
1168 sds_mbx.intrpt_id = 0xffff;
1169 sds_mbx.intrpt_val = 0;
1170 buf = &cmd.req.arg[index];
1171 memcpy(buf, &sds_mbx, sds_mbx_size);
1172 index += sds_mbx_size / sizeof(u32);
1173 }
1174 /* set up receive rings, mbx 88-111/135 */
1175 index = QLCNIC_HOST_RDS_MBX_IDX;
1176 rds = &recv_ctx->rds_rings[0];
1177 rds->producer = 0;
1178 memset(&rds_mbx, 0, rds_mbx_size);
1179 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1180 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1181 rds_mbx.reg_ring_sz = rds->dma_size;
1182 rds_mbx.reg_ring_len = rds->num_desc;
1183 /* Jumbo ring */
1184 rds = &recv_ctx->rds_rings[1];
1185 rds->producer = 0;
1186 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1187 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1188 rds_mbx.jmb_ring_sz = rds->dma_size;
1189 rds_mbx.jmb_ring_len = rds->num_desc;
1190 buf = &cmd.req.arg[index];
1191 memcpy(buf, &rds_mbx, rds_mbx_size);
1192
1193 /* send the mailbox command */
1194 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1195 if (err) {
1196 dev_err(&adapter->pdev->dev,
1197 "Failed to create Rx ctx in firmware%d\n", err);
1198 goto out;
1199 }
1200 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1201 recv_ctx->context_id = mbx_out->ctx_id;
1202 recv_ctx->state = mbx_out->state;
1203 recv_ctx->virt_port = mbx_out->vport_id;
1204 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1205 recv_ctx->context_id, recv_ctx->state);
1206 /* Receive descriptor ring */
1207 /* Standard ring */
1208 rds = &recv_ctx->rds_rings[0];
1209 rds->crb_rcv_producer = ahw->pci_base0 +
1210 mbx_out->host_prod[0].reg_buf;
1211 /* Jumbo ring */
1212 rds = &recv_ctx->rds_rings[1];
1213 rds->crb_rcv_producer = ahw->pci_base0 +
1214 mbx_out->host_prod[0].jmb_buf;
1215 /* status descriptor ring */
1216 for (i = 0; i < num_sds; i++) {
1217 sds = &recv_ctx->sds_rings[i];
1218 sds->crb_sts_consumer = ahw->pci_base0 +
1219 mbx_out->host_csmr[i];
1220 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1221 intr_mask = ahw->intr_tbl[i].src;
1222 else
1223 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1224 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1225 }
1226
1227 if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1228 err = qlcnic_83xx_add_rings(adapter);
1229 out:
1230 qlcnic_free_mbx_args(&cmd);
1231 return err;
1232 }
1233
1234 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1235 struct qlcnic_host_tx_ring *tx_ring)
1236 {
1237 struct qlcnic_cmd_args cmd;
1238 u32 temp = 0;
1239
1240 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1241 return;
1242
1243 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1244 cmd.req.arg[0] |= (0x3 << 29);
1245
1246 if (qlcnic_sriov_pf_check(adapter))
1247 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1248
1249 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1250 if (qlcnic_issue_cmd(adapter, &cmd))
1251 dev_err(&adapter->pdev->dev,
1252 "Failed to destroy tx ctx in firmware\n");
1253 qlcnic_free_mbx_args(&cmd);
1254 }
1255
1256 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1257 struct qlcnic_host_tx_ring *tx, int ring)
1258 {
1259 int err;
1260 u16 msix_id;
1261 u32 *buf, intr_mask, temp = 0;
1262 struct qlcnic_cmd_args cmd;
1263 struct qlcnic_tx_mbx mbx;
1264 struct qlcnic_tx_mbx_out *mbx_out;
1265 struct qlcnic_hardware_context *ahw = adapter->ahw;
1266 u32 msix_vector;
1267
1268 /* Reset host resources */
1269 tx->producer = 0;
1270 tx->sw_consumer = 0;
1271 *(tx->hw_consumer) = 0;
1272
1273 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1274
1275 /* setup mailbox inbox registerss */
1276 mbx.phys_addr_low = LSD(tx->phys_addr);
1277 mbx.phys_addr_high = MSD(tx->phys_addr);
1278 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1279 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1280 mbx.size = tx->num_desc;
1281 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1282 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1283 msix_vector = adapter->drv_sds_rings + ring;
1284 else
1285 msix_vector = adapter->drv_sds_rings - 1;
1286 msix_id = ahw->intr_tbl[msix_vector].id;
1287 } else {
1288 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1289 }
1290
1291 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1292 mbx.intr_id = msix_id;
1293 else
1294 mbx.intr_id = 0xffff;
1295 mbx.src = 0;
1296
1297 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1298 if (err)
1299 return err;
1300
1301 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1302 cmd.req.arg[0] |= (0x3 << 29);
1303
1304 if (qlcnic_sriov_pf_check(adapter))
1305 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1306
1307 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1308 cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1309
1310 buf = &cmd.req.arg[6];
1311 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1312 /* send the mailbox command*/
1313 err = qlcnic_issue_cmd(adapter, &cmd);
1314 if (err) {
1315 netdev_err(adapter->netdev,
1316 "Failed to create Tx ctx in firmware 0x%x\n", err);
1317 goto out;
1318 }
1319 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1320 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1321 tx->ctx_id = mbx_out->ctx_id;
1322 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1323 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1324 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1325 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1326 }
1327 netdev_info(adapter->netdev,
1328 "Tx Context[0x%x] Created, state:0x%x\n",
1329 tx->ctx_id, mbx_out->state);
1330 out:
1331 qlcnic_free_mbx_args(&cmd);
1332 return err;
1333 }
1334
1335 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1336 u8 num_sds_ring)
1337 {
1338 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1339 struct qlcnic_host_sds_ring *sds_ring;
1340 struct qlcnic_host_rds_ring *rds_ring;
1341 u16 adapter_state = adapter->is_up;
1342 u8 ring;
1343 int ret;
1344
1345 netif_device_detach(netdev);
1346
1347 if (netif_running(netdev))
1348 __qlcnic_down(adapter, netdev);
1349
1350 qlcnic_detach(adapter);
1351
1352 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1353 adapter->ahw->diag_test = test;
1354 adapter->ahw->linkup = 0;
1355
1356 ret = qlcnic_attach(adapter);
1357 if (ret) {
1358 netif_device_attach(netdev);
1359 return ret;
1360 }
1361
1362 ret = qlcnic_fw_create_ctx(adapter);
1363 if (ret) {
1364 qlcnic_detach(adapter);
1365 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1366 adapter->drv_sds_rings = num_sds_ring;
1367 qlcnic_attach(adapter);
1368 }
1369 netif_device_attach(netdev);
1370 return ret;
1371 }
1372
1373 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1374 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1375 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1376 }
1377
1378 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1379 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1380 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1381 qlcnic_enable_sds_intr(adapter, sds_ring);
1382 }
1383 }
1384
1385 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1386 adapter->ahw->loopback_state = 0;
1387 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1388 }
1389
1390 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1391 return 0;
1392 }
1393
1394 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1395 u8 drv_sds_rings)
1396 {
1397 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1398 struct qlcnic_host_sds_ring *sds_ring;
1399 int ring;
1400
1401 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1402 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1403 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1404 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1405 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1406 qlcnic_disable_sds_intr(adapter, sds_ring);
1407 }
1408 }
1409
1410 qlcnic_fw_destroy_ctx(adapter);
1411 qlcnic_detach(adapter);
1412
1413 adapter->ahw->diag_test = 0;
1414 adapter->drv_sds_rings = drv_sds_rings;
1415
1416 if (qlcnic_attach(adapter))
1417 goto out;
1418
1419 if (netif_running(netdev))
1420 __qlcnic_up(adapter, netdev);
1421
1422 out:
1423 netif_device_attach(netdev);
1424 }
1425
1426 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
1427 {
1428 struct qlcnic_hardware_context *ahw = adapter->ahw;
1429 struct qlcnic_cmd_args cmd;
1430 u8 beacon_state;
1431 int err = 0;
1432
1433 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1434 if (!err) {
1435 err = qlcnic_issue_cmd(adapter, &cmd);
1436 if (!err) {
1437 beacon_state = cmd.rsp.arg[4];
1438 if (beacon_state == QLCNIC_BEACON_DISABLE)
1439 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1440 else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1441 ahw->beacon_state = QLC_83XX_BEACON_ON;
1442 }
1443 } else {
1444 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1445 err);
1446 }
1447
1448 qlcnic_free_mbx_args(&cmd);
1449
1450 return;
1451 }
1452
1453 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1454 u32 beacon)
1455 {
1456 struct qlcnic_cmd_args cmd;
1457 u32 mbx_in;
1458 int i, status = 0;
1459
1460 if (state) {
1461 /* Get LED configuration */
1462 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1463 QLCNIC_CMD_GET_LED_CONFIG);
1464 if (status)
1465 return status;
1466
1467 status = qlcnic_issue_cmd(adapter, &cmd);
1468 if (status) {
1469 dev_err(&adapter->pdev->dev,
1470 "Get led config failed.\n");
1471 goto mbx_err;
1472 } else {
1473 for (i = 0; i < 4; i++)
1474 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1475 }
1476 qlcnic_free_mbx_args(&cmd);
1477 /* Set LED Configuration */
1478 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1479 LSW(QLC_83XX_LED_CONFIG);
1480 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1481 QLCNIC_CMD_SET_LED_CONFIG);
1482 if (status)
1483 return status;
1484
1485 cmd.req.arg[1] = mbx_in;
1486 cmd.req.arg[2] = mbx_in;
1487 cmd.req.arg[3] = mbx_in;
1488 if (beacon)
1489 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1490 status = qlcnic_issue_cmd(adapter, &cmd);
1491 if (status) {
1492 dev_err(&adapter->pdev->dev,
1493 "Set led config failed.\n");
1494 }
1495 mbx_err:
1496 qlcnic_free_mbx_args(&cmd);
1497 return status;
1498
1499 } else {
1500 /* Restoring default LED configuration */
1501 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1502 QLCNIC_CMD_SET_LED_CONFIG);
1503 if (status)
1504 return status;
1505
1506 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1507 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1508 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1509 if (beacon)
1510 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1511 status = qlcnic_issue_cmd(adapter, &cmd);
1512 if (status)
1513 dev_err(&adapter->pdev->dev,
1514 "Restoring led config failed.\n");
1515 qlcnic_free_mbx_args(&cmd);
1516 return status;
1517 }
1518 }
1519
1520 int qlcnic_83xx_set_led(struct net_device *netdev,
1521 enum ethtool_phys_id_state state)
1522 {
1523 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1524 int err = -EIO, active = 1;
1525
1526 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1527 netdev_warn(netdev,
1528 "LED test is not supported in non-privileged mode\n");
1529 return -EOPNOTSUPP;
1530 }
1531
1532 switch (state) {
1533 case ETHTOOL_ID_ACTIVE:
1534 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1535 return -EBUSY;
1536
1537 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1538 break;
1539
1540 err = qlcnic_83xx_config_led(adapter, active, 0);
1541 if (err)
1542 netdev_err(netdev, "Failed to set LED blink state\n");
1543 break;
1544 case ETHTOOL_ID_INACTIVE:
1545 active = 0;
1546
1547 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1548 break;
1549
1550 err = qlcnic_83xx_config_led(adapter, active, 0);
1551 if (err)
1552 netdev_err(netdev, "Failed to reset LED blink state\n");
1553 break;
1554
1555 default:
1556 return -EINVAL;
1557 }
1558
1559 if (!active || err)
1560 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1561
1562 return err;
1563 }
1564
1565 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1566 {
1567 struct qlcnic_cmd_args cmd;
1568 int status;
1569
1570 if (qlcnic_sriov_vf_check(adapter))
1571 return;
1572
1573 if (enable)
1574 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1575 QLCNIC_CMD_INIT_NIC_FUNC);
1576 else
1577 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1578 QLCNIC_CMD_STOP_NIC_FUNC);
1579
1580 if (status)
1581 return;
1582
1583 cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1584
1585 if (adapter->dcb)
1586 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1587
1588 status = qlcnic_issue_cmd(adapter, &cmd);
1589 if (status)
1590 dev_err(&adapter->pdev->dev,
1591 "Failed to %s in NIC IDC function event.\n",
1592 (enable ? "register" : "unregister"));
1593
1594 qlcnic_free_mbx_args(&cmd);
1595 }
1596
1597 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1598 {
1599 struct qlcnic_cmd_args cmd;
1600 int err;
1601
1602 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1603 if (err)
1604 return err;
1605
1606 cmd.req.arg[1] = adapter->ahw->port_config;
1607 err = qlcnic_issue_cmd(adapter, &cmd);
1608 if (err)
1609 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1610 qlcnic_free_mbx_args(&cmd);
1611 return err;
1612 }
1613
1614 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1615 {
1616 struct qlcnic_cmd_args cmd;
1617 int err;
1618
1619 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1620 if (err)
1621 return err;
1622
1623 err = qlcnic_issue_cmd(adapter, &cmd);
1624 if (err)
1625 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1626 else
1627 adapter->ahw->port_config = cmd.rsp.arg[1];
1628 qlcnic_free_mbx_args(&cmd);
1629 return err;
1630 }
1631
1632 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1633 {
1634 int err;
1635 u32 temp;
1636 struct qlcnic_cmd_args cmd;
1637
1638 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1639 if (err)
1640 return err;
1641
1642 temp = adapter->recv_ctx->context_id << 16;
1643 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1644 err = qlcnic_issue_cmd(adapter, &cmd);
1645 if (err)
1646 dev_info(&adapter->pdev->dev,
1647 "Setup linkevent mailbox failed\n");
1648 qlcnic_free_mbx_args(&cmd);
1649 return err;
1650 }
1651
1652 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1653 u32 *interface_id)
1654 {
1655 if (qlcnic_sriov_pf_check(adapter)) {
1656 qlcnic_alloc_lb_filters_mem(adapter);
1657 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1658 adapter->rx_mac_learn = true;
1659 } else {
1660 if (!qlcnic_sriov_vf_check(adapter))
1661 *interface_id = adapter->recv_ctx->context_id << 16;
1662 }
1663 }
1664
1665 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1666 {
1667 struct qlcnic_cmd_args *cmd = NULL;
1668 u32 temp = 0;
1669 int err;
1670
1671 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1672 return -EIO;
1673
1674 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1675 if (!cmd)
1676 return -ENOMEM;
1677
1678 err = qlcnic_alloc_mbx_args(cmd, adapter,
1679 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1680 if (err)
1681 goto out;
1682
1683 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1684 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1685
1686 if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1687 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1688
1689 cmd->req.arg[1] = mode | temp;
1690 err = qlcnic_issue_cmd(adapter, cmd);
1691 if (!err)
1692 return err;
1693
1694 qlcnic_free_mbx_args(cmd);
1695
1696 out:
1697 kfree(cmd);
1698 return err;
1699 }
1700
1701 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1702 {
1703 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1704 struct qlcnic_hardware_context *ahw = adapter->ahw;
1705 u8 drv_sds_rings = adapter->drv_sds_rings;
1706 u8 drv_tx_rings = adapter->drv_tx_rings;
1707 int ret = 0, loop = 0;
1708
1709 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1710 netdev_warn(netdev,
1711 "Loopback test not supported in non privileged mode\n");
1712 return -ENOTSUPP;
1713 }
1714
1715 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1716 netdev_info(netdev, "Device is resetting\n");
1717 return -EBUSY;
1718 }
1719
1720 if (qlcnic_get_diag_lock(adapter)) {
1721 netdev_info(netdev, "Device is in diagnostics mode\n");
1722 return -EBUSY;
1723 }
1724
1725 netdev_info(netdev, "%s loopback test in progress\n",
1726 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1727
1728 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1729 drv_sds_rings);
1730 if (ret)
1731 goto fail_diag_alloc;
1732
1733 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1734 if (ret)
1735 goto free_diag_res;
1736
1737 /* Poll for link up event before running traffic */
1738 do {
1739 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1740
1741 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1742 netdev_info(netdev,
1743 "Device is resetting, free LB test resources\n");
1744 ret = -EBUSY;
1745 goto free_diag_res;
1746 }
1747 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1748 netdev_info(netdev,
1749 "Firmware didn't sent link up event to loopback request\n");
1750 ret = -ETIMEDOUT;
1751 qlcnic_83xx_clear_lb_mode(adapter, mode);
1752 goto free_diag_res;
1753 }
1754 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1755
1756 ret = qlcnic_do_lb_test(adapter, mode);
1757
1758 qlcnic_83xx_clear_lb_mode(adapter, mode);
1759
1760 free_diag_res:
1761 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1762
1763 fail_diag_alloc:
1764 adapter->drv_sds_rings = drv_sds_rings;
1765 adapter->drv_tx_rings = drv_tx_rings;
1766 qlcnic_release_diag_lock(adapter);
1767 return ret;
1768 }
1769
1770 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1771 u32 *max_wait_count)
1772 {
1773 struct qlcnic_hardware_context *ahw = adapter->ahw;
1774 int temp;
1775
1776 netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1777 ahw->extend_lb_time);
1778 temp = ahw->extend_lb_time * 1000;
1779 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1780 ahw->extend_lb_time = 0;
1781 }
1782
1783 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1784 {
1785 struct qlcnic_hardware_context *ahw = adapter->ahw;
1786 struct net_device *netdev = adapter->netdev;
1787 u32 config, max_wait_count;
1788 int status = 0, loop = 0;
1789
1790 ahw->extend_lb_time = 0;
1791 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1792 status = qlcnic_83xx_get_port_config(adapter);
1793 if (status)
1794 return status;
1795
1796 config = ahw->port_config;
1797
1798 /* Check if port is already in loopback mode */
1799 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1800 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1801 netdev_err(netdev,
1802 "Port already in Loopback mode.\n");
1803 return -EINPROGRESS;
1804 }
1805
1806 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1807
1808 if (mode == QLCNIC_ILB_MODE)
1809 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1810 if (mode == QLCNIC_ELB_MODE)
1811 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1812
1813 status = qlcnic_83xx_set_port_config(adapter);
1814 if (status) {
1815 netdev_err(netdev,
1816 "Failed to Set Loopback Mode = 0x%x.\n",
1817 ahw->port_config);
1818 ahw->port_config = config;
1819 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1820 return status;
1821 }
1822
1823 /* Wait for Link and IDC Completion AEN */
1824 do {
1825 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1826
1827 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1828 netdev_info(netdev,
1829 "Device is resetting, free LB test resources\n");
1830 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1831 return -EBUSY;
1832 }
1833
1834 if (ahw->extend_lb_time)
1835 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1836 &max_wait_count);
1837
1838 if (loop++ > max_wait_count) {
1839 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1840 __func__);
1841 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1842 qlcnic_83xx_clear_lb_mode(adapter, mode);
1843 return -ETIMEDOUT;
1844 }
1845 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1846
1847 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1848 QLCNIC_MAC_ADD);
1849 return status;
1850 }
1851
1852 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1853 {
1854 struct qlcnic_hardware_context *ahw = adapter->ahw;
1855 u32 config = ahw->port_config, max_wait_count;
1856 struct net_device *netdev = adapter->netdev;
1857 int status = 0, loop = 0;
1858
1859 ahw->extend_lb_time = 0;
1860 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1861 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1862 if (mode == QLCNIC_ILB_MODE)
1863 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1864 if (mode == QLCNIC_ELB_MODE)
1865 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1866
1867 status = qlcnic_83xx_set_port_config(adapter);
1868 if (status) {
1869 netdev_err(netdev,
1870 "Failed to Clear Loopback Mode = 0x%x.\n",
1871 ahw->port_config);
1872 ahw->port_config = config;
1873 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1874 return status;
1875 }
1876
1877 /* Wait for Link and IDC Completion AEN */
1878 do {
1879 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1880
1881 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1882 netdev_info(netdev,
1883 "Device is resetting, free LB test resources\n");
1884 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1885 return -EBUSY;
1886 }
1887
1888 if (ahw->extend_lb_time)
1889 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1890 &max_wait_count);
1891
1892 if (loop++ > max_wait_count) {
1893 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1894 __func__);
1895 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1896 return -ETIMEDOUT;
1897 }
1898 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1899
1900 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1901 QLCNIC_MAC_DEL);
1902 return status;
1903 }
1904
1905 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1906 u32 *interface_id)
1907 {
1908 if (qlcnic_sriov_pf_check(adapter)) {
1909 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1910 } else {
1911 if (!qlcnic_sriov_vf_check(adapter))
1912 *interface_id = adapter->recv_ctx->context_id << 16;
1913 }
1914 }
1915
1916 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1917 int mode)
1918 {
1919 int err;
1920 u32 temp = 0, temp_ip;
1921 struct qlcnic_cmd_args cmd;
1922
1923 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1924 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1925 if (err)
1926 return;
1927
1928 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1929
1930 if (mode == QLCNIC_IP_UP)
1931 cmd.req.arg[1] = 1 | temp;
1932 else
1933 cmd.req.arg[1] = 2 | temp;
1934
1935 /*
1936 * Adapter needs IP address in network byte order.
1937 * But hardware mailbox registers go through writel(), hence IP address
1938 * gets swapped on big endian architecture.
1939 * To negate swapping of writel() on big endian architecture
1940 * use swab32(value).
1941 */
1942
1943 temp_ip = swab32(ntohl(ip));
1944 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1945 err = qlcnic_issue_cmd(adapter, &cmd);
1946 if (err != QLCNIC_RCODE_SUCCESS)
1947 dev_err(&adapter->netdev->dev,
1948 "could not notify %s IP 0x%x request\n",
1949 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1950
1951 qlcnic_free_mbx_args(&cmd);
1952 }
1953
1954 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1955 {
1956 int err;
1957 u32 temp, arg1;
1958 struct qlcnic_cmd_args cmd;
1959 int lro_bit_mask;
1960
1961 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1962
1963 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1964 return 0;
1965
1966 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1967 if (err)
1968 return err;
1969
1970 temp = adapter->recv_ctx->context_id << 16;
1971 arg1 = lro_bit_mask | temp;
1972 cmd.req.arg[1] = arg1;
1973
1974 err = qlcnic_issue_cmd(adapter, &cmd);
1975 if (err)
1976 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1977 qlcnic_free_mbx_args(&cmd);
1978
1979 return err;
1980 }
1981
1982 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1983 {
1984 int err;
1985 u32 word;
1986 struct qlcnic_cmd_args cmd;
1987 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1988 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1989 0x255b0ec26d5a56daULL };
1990
1991 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1992 if (err)
1993 return err;
1994 /*
1995 * RSS request:
1996 * bits 3-0: Rsvd
1997 * 5-4: hash_type_ipv4
1998 * 7-6: hash_type_ipv6
1999 * 8: enable
2000 * 9: use indirection table
2001 * 16-31: indirection table mask
2002 */
2003 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
2004 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
2005 ((u32)(enable & 0x1) << 8) |
2006 ((0x7ULL) << 16);
2007 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
2008 cmd.req.arg[2] = word;
2009 memcpy(&cmd.req.arg[4], key, sizeof(key));
2010
2011 err = qlcnic_issue_cmd(adapter, &cmd);
2012
2013 if (err)
2014 dev_info(&adapter->pdev->dev, "RSS config failed\n");
2015 qlcnic_free_mbx_args(&cmd);
2016
2017 return err;
2018
2019 }
2020
2021 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
2022 u32 *interface_id)
2023 {
2024 if (qlcnic_sriov_pf_check(adapter)) {
2025 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
2026 } else {
2027 if (!qlcnic_sriov_vf_check(adapter))
2028 *interface_id = adapter->recv_ctx->context_id << 16;
2029 }
2030 }
2031
2032 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
2033 u16 vlan_id, u8 op)
2034 {
2035 struct qlcnic_cmd_args *cmd = NULL;
2036 struct qlcnic_macvlan_mbx mv;
2037 u32 *buf, temp = 0;
2038 int err;
2039
2040 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2041 return -EIO;
2042
2043 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2044 if (!cmd)
2045 return -ENOMEM;
2046
2047 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2048 if (err)
2049 goto out;
2050
2051 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2052
2053 if (vlan_id)
2054 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2055 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2056
2057 cmd->req.arg[1] = op | (1 << 8);
2058 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2059 cmd->req.arg[1] |= temp;
2060 mv.vlan = vlan_id;
2061 mv.mac_addr0 = addr[0];
2062 mv.mac_addr1 = addr[1];
2063 mv.mac_addr2 = addr[2];
2064 mv.mac_addr3 = addr[3];
2065 mv.mac_addr4 = addr[4];
2066 mv.mac_addr5 = addr[5];
2067 buf = &cmd->req.arg[2];
2068 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2069 err = qlcnic_issue_cmd(adapter, cmd);
2070 if (!err)
2071 return err;
2072
2073 qlcnic_free_mbx_args(cmd);
2074 out:
2075 kfree(cmd);
2076 return err;
2077 }
2078
2079 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2080 u16 vlan_id)
2081 {
2082 u8 mac[ETH_ALEN];
2083 memcpy(&mac, addr, ETH_ALEN);
2084 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2085 }
2086
2087 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2088 u8 type, struct qlcnic_cmd_args *cmd)
2089 {
2090 switch (type) {
2091 case QLCNIC_SET_STATION_MAC:
2092 case QLCNIC_SET_FAC_DEF_MAC:
2093 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2094 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2095 break;
2096 }
2097 cmd->req.arg[1] = type;
2098 }
2099
2100 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2101 u8 function)
2102 {
2103 int err, i;
2104 struct qlcnic_cmd_args cmd;
2105 u32 mac_low, mac_high;
2106
2107 function = 0;
2108 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2109 if (err)
2110 return err;
2111
2112 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2113 err = qlcnic_issue_cmd(adapter, &cmd);
2114
2115 if (err == QLCNIC_RCODE_SUCCESS) {
2116 mac_low = cmd.rsp.arg[1];
2117 mac_high = cmd.rsp.arg[2];
2118
2119 for (i = 0; i < 2; i++)
2120 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2121 for (i = 2; i < 6; i++)
2122 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2123 } else {
2124 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2125 err);
2126 err = -EIO;
2127 }
2128 qlcnic_free_mbx_args(&cmd);
2129 return err;
2130 }
2131
2132 static int qlcnic_83xx_set_rx_intr_coal(struct qlcnic_adapter *adapter)
2133 {
2134 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2135 struct qlcnic_cmd_args cmd;
2136 u16 temp;
2137 int err;
2138
2139 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2140 if (err)
2141 return err;
2142
2143 temp = adapter->recv_ctx->context_id;
2144 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2145 temp = coal->rx_time_us;
2146 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2147 cmd.req.arg[3] = coal->flag;
2148
2149 err = qlcnic_issue_cmd(adapter, &cmd);
2150 if (err != QLCNIC_RCODE_SUCCESS)
2151 netdev_err(adapter->netdev,
2152 "failed to set interrupt coalescing parameters\n");
2153
2154 qlcnic_free_mbx_args(&cmd);
2155
2156 return err;
2157 }
2158
2159 static int qlcnic_83xx_set_tx_intr_coal(struct qlcnic_adapter *adapter)
2160 {
2161 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2162 struct qlcnic_cmd_args cmd;
2163 u16 temp;
2164 int err;
2165
2166 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2167 if (err)
2168 return err;
2169
2170 temp = adapter->tx_ring->ctx_id;
2171 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2172 temp = coal->tx_time_us;
2173 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2174 cmd.req.arg[3] = coal->flag;
2175
2176 err = qlcnic_issue_cmd(adapter, &cmd);
2177 if (err != QLCNIC_RCODE_SUCCESS)
2178 netdev_err(adapter->netdev,
2179 "failed to set interrupt coalescing parameters\n");
2180
2181 qlcnic_free_mbx_args(&cmd);
2182
2183 return err;
2184 }
2185
2186 int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *adapter)
2187 {
2188 int err = 0;
2189
2190 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2191 if (err)
2192 netdev_err(adapter->netdev,
2193 "failed to set Rx coalescing parameters\n");
2194
2195 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2196 if (err)
2197 netdev_err(adapter->netdev,
2198 "failed to set Tx coalescing parameters\n");
2199
2200 return err;
2201 }
2202
2203 int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter,
2204 struct ethtool_coalesce *ethcoal)
2205 {
2206 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2207 u32 rx_coalesce_usecs, rx_max_frames;
2208 u32 tx_coalesce_usecs, tx_max_frames;
2209 int err;
2210
2211 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2212 return -EIO;
2213
2214 tx_coalesce_usecs = ethcoal->tx_coalesce_usecs;
2215 tx_max_frames = ethcoal->tx_max_coalesced_frames;
2216 rx_coalesce_usecs = ethcoal->rx_coalesce_usecs;
2217 rx_max_frames = ethcoal->rx_max_coalesced_frames;
2218 coal->flag = QLCNIC_INTR_DEFAULT;
2219
2220 if ((coal->rx_time_us == rx_coalesce_usecs) &&
2221 (coal->rx_packets == rx_max_frames)) {
2222 coal->type = QLCNIC_INTR_COAL_TYPE_TX;
2223 coal->tx_time_us = tx_coalesce_usecs;
2224 coal->tx_packets = tx_max_frames;
2225 } else if ((coal->tx_time_us == tx_coalesce_usecs) &&
2226 (coal->tx_packets == tx_max_frames)) {
2227 coal->type = QLCNIC_INTR_COAL_TYPE_RX;
2228 coal->rx_time_us = rx_coalesce_usecs;
2229 coal->rx_packets = rx_max_frames;
2230 } else {
2231 coal->type = QLCNIC_INTR_COAL_TYPE_RX_TX;
2232 coal->rx_time_us = rx_coalesce_usecs;
2233 coal->rx_packets = rx_max_frames;
2234 coal->tx_time_us = tx_coalesce_usecs;
2235 coal->tx_packets = tx_max_frames;
2236 }
2237
2238 switch (coal->type) {
2239 case QLCNIC_INTR_COAL_TYPE_RX:
2240 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2241 break;
2242 case QLCNIC_INTR_COAL_TYPE_TX:
2243 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2244 break;
2245 case QLCNIC_INTR_COAL_TYPE_RX_TX:
2246 err = qlcnic_83xx_set_rx_tx_intr_coal(adapter);
2247 break;
2248 default:
2249 err = -EINVAL;
2250 netdev_err(adapter->netdev,
2251 "Invalid Interrupt coalescing type\n");
2252 break;
2253 }
2254
2255 return err;
2256 }
2257
2258 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2259 u32 data[])
2260 {
2261 struct qlcnic_hardware_context *ahw = adapter->ahw;
2262 u8 link_status, duplex;
2263 /* link speed */
2264 link_status = LSB(data[3]) & 1;
2265 if (link_status) {
2266 ahw->link_speed = MSW(data[2]);
2267 duplex = LSB(MSW(data[3]));
2268 if (duplex)
2269 ahw->link_duplex = DUPLEX_FULL;
2270 else
2271 ahw->link_duplex = DUPLEX_HALF;
2272 } else {
2273 ahw->link_speed = SPEED_UNKNOWN;
2274 ahw->link_duplex = DUPLEX_UNKNOWN;
2275 }
2276
2277 ahw->link_autoneg = MSB(MSW(data[3]));
2278 ahw->module_type = MSB(LSW(data[3]));
2279 ahw->has_link_events = 1;
2280 ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2281 qlcnic_advert_link_change(adapter, link_status);
2282 }
2283
2284 static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2285 {
2286 struct qlcnic_adapter *adapter = data;
2287 struct qlcnic_mailbox *mbx;
2288 u32 mask, resp, event;
2289 unsigned long flags;
2290
2291 mbx = adapter->ahw->mailbox;
2292 spin_lock_irqsave(&mbx->aen_lock, flags);
2293 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2294 if (!(resp & QLCNIC_SET_OWNER))
2295 goto out;
2296
2297 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2298 if (event & QLCNIC_MBX_ASYNC_EVENT)
2299 __qlcnic_83xx_process_aen(adapter);
2300 else
2301 qlcnic_83xx_notify_mbx_response(mbx);
2302
2303 out:
2304 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2305 writel(0, adapter->ahw->pci_base0 + mask);
2306 spin_unlock_irqrestore(&mbx->aen_lock, flags);
2307 return IRQ_HANDLED;
2308 }
2309
2310 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2311 struct qlcnic_info *nic)
2312 {
2313 int i, err = -EIO;
2314 struct qlcnic_cmd_args cmd;
2315
2316 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2317 dev_err(&adapter->pdev->dev,
2318 "%s: Error, invoked by non management func\n",
2319 __func__);
2320 return err;
2321 }
2322
2323 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2324 if (err)
2325 return err;
2326
2327 cmd.req.arg[1] = (nic->pci_func << 16);
2328 cmd.req.arg[2] = 0x1 << 16;
2329 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2330 cmd.req.arg[4] = nic->capabilities;
2331 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2332 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2333 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2334 for (i = 8; i < 32; i++)
2335 cmd.req.arg[i] = 0;
2336
2337 err = qlcnic_issue_cmd(adapter, &cmd);
2338
2339 if (err != QLCNIC_RCODE_SUCCESS) {
2340 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2341 err);
2342 err = -EIO;
2343 }
2344
2345 qlcnic_free_mbx_args(&cmd);
2346
2347 return err;
2348 }
2349
2350 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2351 struct qlcnic_info *npar_info, u8 func_id)
2352 {
2353 int err;
2354 u32 temp;
2355 u8 op = 0;
2356 struct qlcnic_cmd_args cmd;
2357 struct qlcnic_hardware_context *ahw = adapter->ahw;
2358
2359 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2360 if (err)
2361 return err;
2362
2363 if (func_id != ahw->pci_func) {
2364 temp = func_id << 16;
2365 cmd.req.arg[1] = op | BIT_31 | temp;
2366 } else {
2367 cmd.req.arg[1] = ahw->pci_func << 16;
2368 }
2369 err = qlcnic_issue_cmd(adapter, &cmd);
2370 if (err) {
2371 dev_info(&adapter->pdev->dev,
2372 "Failed to get nic info %d\n", err);
2373 goto out;
2374 }
2375
2376 npar_info->op_type = cmd.rsp.arg[1];
2377 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2378 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2379 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2380 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2381 npar_info->capabilities = cmd.rsp.arg[4];
2382 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2383 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2384 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2385 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2386 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2387 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2388 if (cmd.rsp.arg[8] & 0x1)
2389 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2390 if (cmd.rsp.arg[8] & 0x10000) {
2391 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2392 npar_info->max_linkspeed_reg_offset = temp;
2393 }
2394
2395 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2396 sizeof(ahw->extra_capability));
2397
2398 out:
2399 qlcnic_free_mbx_args(&cmd);
2400 return err;
2401 }
2402
2403 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2404 u16 *nic, u16 *fcoe, u16 *iscsi)
2405 {
2406 struct device *dev = &adapter->pdev->dev;
2407 int err = 0;
2408
2409 switch (type) {
2410 case QLCNIC_TYPE_NIC:
2411 (*nic)++;
2412 break;
2413 case QLCNIC_TYPE_FCOE:
2414 (*fcoe)++;
2415 break;
2416 case QLCNIC_TYPE_ISCSI:
2417 (*iscsi)++;
2418 break;
2419 default:
2420 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2421 __func__, type);
2422 err = -EIO;
2423 }
2424
2425 return err;
2426 }
2427
2428 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2429 struct qlcnic_pci_info *pci_info)
2430 {
2431 struct qlcnic_hardware_context *ahw = adapter->ahw;
2432 struct device *dev = &adapter->pdev->dev;
2433 u16 nic = 0, fcoe = 0, iscsi = 0;
2434 struct qlcnic_cmd_args cmd;
2435 int i, err = 0, j = 0;
2436 u32 temp;
2437
2438 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2439 if (err)
2440 return err;
2441
2442 err = qlcnic_issue_cmd(adapter, &cmd);
2443
2444 ahw->total_nic_func = 0;
2445 if (err == QLCNIC_RCODE_SUCCESS) {
2446 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2447 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2448 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2449 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2450 i++;
2451 if (!pci_info->active) {
2452 i += QLC_SKIP_INACTIVE_PCI_REGS;
2453 continue;
2454 }
2455 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2456 err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2457 &nic, &fcoe, &iscsi);
2458 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2459 pci_info->default_port = temp;
2460 i++;
2461 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2462 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2463 pci_info->tx_max_bw = temp;
2464 i = i + 2;
2465 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2466 i++;
2467 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2468 i = i + 3;
2469 }
2470 } else {
2471 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2472 err = -EIO;
2473 }
2474
2475 ahw->total_nic_func = nic;
2476 ahw->total_pci_func = nic + fcoe + iscsi;
2477 if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2478 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2479 __func__, ahw->total_nic_func, ahw->total_pci_func);
2480 err = -EIO;
2481 }
2482 qlcnic_free_mbx_args(&cmd);
2483
2484 return err;
2485 }
2486
2487 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2488 {
2489 int i, index, err;
2490 u8 max_ints;
2491 u32 val, temp, type;
2492 struct qlcnic_cmd_args cmd;
2493
2494 max_ints = adapter->ahw->num_msix - 1;
2495 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2496 if (err)
2497 return err;
2498
2499 cmd.req.arg[1] = max_ints;
2500
2501 if (qlcnic_sriov_vf_check(adapter))
2502 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2503
2504 for (i = 0, index = 2; i < max_ints; i++) {
2505 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2506 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2507 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2508 val |= (adapter->ahw->intr_tbl[i].id << 16);
2509 cmd.req.arg[index++] = val;
2510 }
2511 err = qlcnic_issue_cmd(adapter, &cmd);
2512 if (err) {
2513 dev_err(&adapter->pdev->dev,
2514 "Failed to configure interrupts 0x%x\n", err);
2515 goto out;
2516 }
2517
2518 max_ints = cmd.rsp.arg[1];
2519 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2520 val = cmd.rsp.arg[index];
2521 if (LSB(val)) {
2522 dev_info(&adapter->pdev->dev,
2523 "Can't configure interrupt %d\n",
2524 adapter->ahw->intr_tbl[i].id);
2525 continue;
2526 }
2527 if (op_type) {
2528 adapter->ahw->intr_tbl[i].id = MSW(val);
2529 adapter->ahw->intr_tbl[i].enabled = 1;
2530 temp = cmd.rsp.arg[index + 1];
2531 adapter->ahw->intr_tbl[i].src = temp;
2532 } else {
2533 adapter->ahw->intr_tbl[i].id = i;
2534 adapter->ahw->intr_tbl[i].enabled = 0;
2535 adapter->ahw->intr_tbl[i].src = 0;
2536 }
2537 }
2538 out:
2539 qlcnic_free_mbx_args(&cmd);
2540 return err;
2541 }
2542
2543 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2544 {
2545 int id, timeout = 0;
2546 u32 status = 0;
2547
2548 while (status == 0) {
2549 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2550 if (status)
2551 break;
2552
2553 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2554 id = QLC_SHARED_REG_RD32(adapter,
2555 QLCNIC_FLASH_LOCK_OWNER);
2556 dev_err(&adapter->pdev->dev,
2557 "%s: failed, lock held by %d\n", __func__, id);
2558 return -EIO;
2559 }
2560 usleep_range(1000, 2000);
2561 }
2562
2563 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2564 return 0;
2565 }
2566
2567 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2568 {
2569 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2570 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2571 }
2572
2573 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2574 u32 flash_addr, u8 *p_data,
2575 int count)
2576 {
2577 u32 word, range, flash_offset, addr = flash_addr, ret;
2578 ulong indirect_add, direct_window;
2579 int i, err = 0;
2580
2581 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2582 if (addr & 0x3) {
2583 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2584 return -EIO;
2585 }
2586
2587 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2588 (addr));
2589
2590 range = flash_offset + (count * sizeof(u32));
2591 /* Check if data is spread across multiple sectors */
2592 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2593
2594 /* Multi sector read */
2595 for (i = 0; i < count; i++) {
2596 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2597 ret = QLCRD32(adapter, indirect_add, &err);
2598 if (err == -EIO)
2599 return err;
2600
2601 word = ret;
2602 *(u32 *)p_data = word;
2603 p_data = p_data + 4;
2604 addr = addr + 4;
2605 flash_offset = flash_offset + 4;
2606
2607 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2608 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2609 /* This write is needed once for each sector */
2610 qlcnic_83xx_wrt_reg_indirect(adapter,
2611 direct_window,
2612 (addr));
2613 flash_offset = 0;
2614 }
2615 }
2616 } else {
2617 /* Single sector read */
2618 for (i = 0; i < count; i++) {
2619 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2620 ret = QLCRD32(adapter, indirect_add, &err);
2621 if (err == -EIO)
2622 return err;
2623
2624 word = ret;
2625 *(u32 *)p_data = word;
2626 p_data = p_data + 4;
2627 addr = addr + 4;
2628 }
2629 }
2630
2631 return 0;
2632 }
2633
2634 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2635 {
2636 u32 status;
2637 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2638 int err = 0;
2639
2640 do {
2641 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2642 if (err == -EIO)
2643 return err;
2644
2645 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2646 QLC_83XX_FLASH_STATUS_READY)
2647 break;
2648
2649 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2650 } while (--retries);
2651
2652 if (!retries)
2653 return -EIO;
2654
2655 return 0;
2656 }
2657
2658 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2659 {
2660 int ret;
2661 u32 cmd;
2662 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2663 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2664 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2665 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2666 adapter->ahw->fdt.write_enable_bits);
2667 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2668 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2669 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2670 if (ret)
2671 return -EIO;
2672
2673 return 0;
2674 }
2675
2676 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2677 {
2678 int ret;
2679
2680 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2681 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2682 adapter->ahw->fdt.write_statusreg_cmd));
2683 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2684 adapter->ahw->fdt.write_disable_bits);
2685 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2686 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2687 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2688 if (ret)
2689 return -EIO;
2690
2691 return 0;
2692 }
2693
2694 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2695 {
2696 int ret, err = 0;
2697 u32 mfg_id;
2698
2699 if (qlcnic_83xx_lock_flash(adapter))
2700 return -EIO;
2701
2702 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2703 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2704 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2705 QLC_83XX_FLASH_READ_CTRL);
2706 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2707 if (ret) {
2708 qlcnic_83xx_unlock_flash(adapter);
2709 return -EIO;
2710 }
2711
2712 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2713 if (err == -EIO) {
2714 qlcnic_83xx_unlock_flash(adapter);
2715 return err;
2716 }
2717
2718 adapter->flash_mfg_id = (mfg_id & 0xFF);
2719 qlcnic_83xx_unlock_flash(adapter);
2720
2721 return 0;
2722 }
2723
2724 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2725 {
2726 int count, fdt_size, ret = 0;
2727
2728 fdt_size = sizeof(struct qlcnic_fdt);
2729 count = fdt_size / sizeof(u32);
2730
2731 if (qlcnic_83xx_lock_flash(adapter))
2732 return -EIO;
2733
2734 memset(&adapter->ahw->fdt, 0, fdt_size);
2735 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2736 (u8 *)&adapter->ahw->fdt,
2737 count);
2738
2739 qlcnic_83xx_unlock_flash(adapter);
2740 return ret;
2741 }
2742
2743 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2744 u32 sector_start_addr)
2745 {
2746 u32 reversed_addr, addr1, addr2, cmd;
2747 int ret = -EIO;
2748
2749 if (qlcnic_83xx_lock_flash(adapter) != 0)
2750 return -EIO;
2751
2752 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2753 ret = qlcnic_83xx_enable_flash_write(adapter);
2754 if (ret) {
2755 qlcnic_83xx_unlock_flash(adapter);
2756 dev_err(&adapter->pdev->dev,
2757 "%s failed at %d\n",
2758 __func__, __LINE__);
2759 return ret;
2760 }
2761 }
2762
2763 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2764 if (ret) {
2765 qlcnic_83xx_unlock_flash(adapter);
2766 dev_err(&adapter->pdev->dev,
2767 "%s: failed at %d\n", __func__, __LINE__);
2768 return -EIO;
2769 }
2770
2771 addr1 = (sector_start_addr & 0xFF) << 16;
2772 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2773 reversed_addr = addr1 | addr2;
2774
2775 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2776 reversed_addr);
2777 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2778 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2779 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2780 else
2781 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2782 QLC_83XX_FLASH_OEM_ERASE_SIG);
2783 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2784 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2785
2786 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2787 if (ret) {
2788 qlcnic_83xx_unlock_flash(adapter);
2789 dev_err(&adapter->pdev->dev,
2790 "%s: failed at %d\n", __func__, __LINE__);
2791 return -EIO;
2792 }
2793
2794 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2795 ret = qlcnic_83xx_disable_flash_write(adapter);
2796 if (ret) {
2797 qlcnic_83xx_unlock_flash(adapter);
2798 dev_err(&adapter->pdev->dev,
2799 "%s: failed at %d\n", __func__, __LINE__);
2800 return ret;
2801 }
2802 }
2803
2804 qlcnic_83xx_unlock_flash(adapter);
2805
2806 return 0;
2807 }
2808
2809 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2810 u32 *p_data)
2811 {
2812 int ret = -EIO;
2813 u32 addr1 = 0x00800000 | (addr >> 2);
2814
2815 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2816 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2817 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2818 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2819 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2820 if (ret) {
2821 dev_err(&adapter->pdev->dev,
2822 "%s: failed at %d\n", __func__, __LINE__);
2823 return -EIO;
2824 }
2825
2826 return 0;
2827 }
2828
2829 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2830 u32 *p_data, int count)
2831 {
2832 u32 temp;
2833 int ret = -EIO, err = 0;
2834
2835 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2836 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2837 dev_err(&adapter->pdev->dev,
2838 "%s: Invalid word count\n", __func__);
2839 return -EIO;
2840 }
2841
2842 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2843 if (err == -EIO)
2844 return err;
2845
2846 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2847 (temp | QLC_83XX_FLASH_SPI_CTRL));
2848 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2849 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2850
2851 /* First DWORD write */
2852 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2853 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2854 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2855 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2856 if (ret) {
2857 dev_err(&adapter->pdev->dev,
2858 "%s: failed at %d\n", __func__, __LINE__);
2859 return -EIO;
2860 }
2861
2862 count--;
2863 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2864 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2865 /* Second to N-1 DWORD writes */
2866 while (count != 1) {
2867 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2868 *p_data++);
2869 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2870 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2871 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2872 if (ret) {
2873 dev_err(&adapter->pdev->dev,
2874 "%s: failed at %d\n", __func__, __LINE__);
2875 return -EIO;
2876 }
2877 count--;
2878 }
2879
2880 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2881 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2882 (addr >> 2));
2883 /* Last DWORD write */
2884 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2885 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2886 QLC_83XX_FLASH_LAST_MS_PATTERN);
2887 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2888 if (ret) {
2889 dev_err(&adapter->pdev->dev,
2890 "%s: failed at %d\n", __func__, __LINE__);
2891 return -EIO;
2892 }
2893
2894 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2895 if (err == -EIO)
2896 return err;
2897
2898 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2899 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2900 __func__, __LINE__);
2901 /* Operation failed, clear error bit */
2902 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2903 if (err == -EIO)
2904 return err;
2905
2906 qlcnic_83xx_wrt_reg_indirect(adapter,
2907 QLC_83XX_FLASH_SPI_CONTROL,
2908 (temp | QLC_83XX_FLASH_SPI_CTRL));
2909 }
2910
2911 return 0;
2912 }
2913
2914 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2915 {
2916 u32 val, id;
2917
2918 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2919
2920 /* Check if recovery need to be performed by the calling function */
2921 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2922 val = val & ~0x3F;
2923 val = val | ((adapter->portnum << 2) |
2924 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2925 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2926 dev_info(&adapter->pdev->dev,
2927 "%s: lock recovery initiated\n", __func__);
2928 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2929 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2930 id = ((val >> 2) & 0xF);
2931 if (id == adapter->portnum) {
2932 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2933 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2934 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2935 /* Force release the lock */
2936 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2937 /* Clear recovery bits */
2938 val = val & ~0x3F;
2939 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2940 dev_info(&adapter->pdev->dev,
2941 "%s: lock recovery completed\n", __func__);
2942 } else {
2943 dev_info(&adapter->pdev->dev,
2944 "%s: func %d to resume lock recovery process\n",
2945 __func__, id);
2946 }
2947 } else {
2948 dev_info(&adapter->pdev->dev,
2949 "%s: lock recovery initiated by other functions\n",
2950 __func__);
2951 }
2952 }
2953
2954 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2955 {
2956 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2957 int max_attempt = 0;
2958
2959 while (status == 0) {
2960 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2961 if (status)
2962 break;
2963
2964 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2965 i++;
2966
2967 if (i == 1)
2968 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2969
2970 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2971 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2972 if (val == temp) {
2973 id = val & 0xFF;
2974 dev_info(&adapter->pdev->dev,
2975 "%s: lock to be recovered from %d\n",
2976 __func__, id);
2977 qlcnic_83xx_recover_driver_lock(adapter);
2978 i = 0;
2979 max_attempt++;
2980 } else {
2981 dev_err(&adapter->pdev->dev,
2982 "%s: failed to get lock\n", __func__);
2983 return -EIO;
2984 }
2985 }
2986
2987 /* Force exit from while loop after few attempts */
2988 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2989 dev_err(&adapter->pdev->dev,
2990 "%s: failed to get lock\n", __func__);
2991 return -EIO;
2992 }
2993 }
2994
2995 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2996 lock_alive_counter = val >> 8;
2997 lock_alive_counter++;
2998 val = lock_alive_counter << 8 | adapter->portnum;
2999 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3000
3001 return 0;
3002 }
3003
3004 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
3005 {
3006 u32 val, lock_alive_counter, id;
3007
3008 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3009 id = val & 0xFF;
3010 lock_alive_counter = val >> 8;
3011
3012 if (id != adapter->portnum)
3013 dev_err(&adapter->pdev->dev,
3014 "%s:Warning func %d is unlocking lock owned by %d\n",
3015 __func__, adapter->portnum, id);
3016
3017 val = (lock_alive_counter << 8) | 0xFF;
3018 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3019 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3020 }
3021
3022 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
3023 u32 *data, u32 count)
3024 {
3025 int i, j, ret = 0;
3026 u32 temp;
3027 int err = 0;
3028
3029 /* Check alignment */
3030 if (addr & 0xF)
3031 return -EIO;
3032
3033 mutex_lock(&adapter->ahw->mem_lock);
3034 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
3035
3036 for (i = 0; i < count; i++, addr += 16) {
3037 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
3038 QLCNIC_ADDR_QDR_NET_MAX)) ||
3039 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
3040 QLCNIC_ADDR_DDR_NET_MAX)))) {
3041 mutex_unlock(&adapter->ahw->mem_lock);
3042 return -EIO;
3043 }
3044
3045 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
3046 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
3047 *data++);
3048 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
3049 *data++);
3050 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
3051 *data++);
3052 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
3053 *data++);
3054 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
3055 QLCNIC_TA_WRITE_ENABLE);
3056 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
3057 QLCNIC_TA_WRITE_START);
3058
3059 for (j = 0; j < MAX_CTL_CHECK; j++) {
3060 temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
3061 if (err == -EIO) {
3062 mutex_unlock(&adapter->ahw->mem_lock);
3063 return err;
3064 }
3065
3066 if ((temp & TA_CTL_BUSY) == 0)
3067 break;
3068 }
3069
3070 /* Status check failure */
3071 if (j >= MAX_CTL_CHECK) {
3072 printk_ratelimited(KERN_WARNING
3073 "MS memory write failed\n");
3074 mutex_unlock(&adapter->ahw->mem_lock);
3075 return -EIO;
3076 }
3077 }
3078
3079 mutex_unlock(&adapter->ahw->mem_lock);
3080
3081 return ret;
3082 }
3083
3084 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
3085 u8 *p_data, int count)
3086 {
3087 u32 word, addr = flash_addr, ret;
3088 ulong indirect_addr;
3089 int i, err = 0;
3090
3091 if (qlcnic_83xx_lock_flash(adapter) != 0)
3092 return -EIO;
3093
3094 if (addr & 0x3) {
3095 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
3096 qlcnic_83xx_unlock_flash(adapter);
3097 return -EIO;
3098 }
3099
3100 for (i = 0; i < count; i++) {
3101 if (qlcnic_83xx_wrt_reg_indirect(adapter,
3102 QLC_83XX_FLASH_DIRECT_WINDOW,
3103 (addr))) {
3104 qlcnic_83xx_unlock_flash(adapter);
3105 return -EIO;
3106 }
3107
3108 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
3109 ret = QLCRD32(adapter, indirect_addr, &err);
3110 if (err == -EIO)
3111 return err;
3112
3113 word = ret;
3114 *(u32 *)p_data = word;
3115 p_data = p_data + 4;
3116 addr = addr + 4;
3117 }
3118
3119 qlcnic_83xx_unlock_flash(adapter);
3120
3121 return 0;
3122 }
3123
3124 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3125 {
3126 u8 pci_func;
3127 int err;
3128 u32 config = 0, state;
3129 struct qlcnic_cmd_args cmd;
3130 struct qlcnic_hardware_context *ahw = adapter->ahw;
3131
3132 if (qlcnic_sriov_vf_check(adapter))
3133 pci_func = adapter->portnum;
3134 else
3135 pci_func = ahw->pci_func;
3136
3137 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3138 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3139 dev_info(&adapter->pdev->dev, "link state down\n");
3140 return config;
3141 }
3142
3143 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3144 if (err)
3145 return err;
3146
3147 err = qlcnic_issue_cmd(adapter, &cmd);
3148 if (err) {
3149 dev_info(&adapter->pdev->dev,
3150 "Get Link Status Command failed: 0x%x\n", err);
3151 goto out;
3152 } else {
3153 config = cmd.rsp.arg[1];
3154 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3155 case QLC_83XX_10M_LINK:
3156 ahw->link_speed = SPEED_10;
3157 break;
3158 case QLC_83XX_100M_LINK:
3159 ahw->link_speed = SPEED_100;
3160 break;
3161 case QLC_83XX_1G_LINK:
3162 ahw->link_speed = SPEED_1000;
3163 break;
3164 case QLC_83XX_10G_LINK:
3165 ahw->link_speed = SPEED_10000;
3166 break;
3167 default:
3168 ahw->link_speed = 0;
3169 break;
3170 }
3171 config = cmd.rsp.arg[3];
3172 if (QLC_83XX_SFP_PRESENT(config)) {
3173 switch (ahw->module_type) {
3174 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3175 case LINKEVENT_MODULE_OPTICAL_SRLR:
3176 case LINKEVENT_MODULE_OPTICAL_LRM:
3177 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3178 ahw->supported_type = PORT_FIBRE;
3179 break;
3180 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3181 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3182 case LINKEVENT_MODULE_TWINAX:
3183 ahw->supported_type = PORT_TP;
3184 break;
3185 default:
3186 ahw->supported_type = PORT_OTHER;
3187 }
3188 }
3189 if (config & 1)
3190 err = 1;
3191 }
3192 out:
3193 qlcnic_free_mbx_args(&cmd);
3194 return config;
3195 }
3196
3197 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3198 struct ethtool_cmd *ecmd)
3199 {
3200 u32 config = 0;
3201 int status = 0;
3202 struct qlcnic_hardware_context *ahw = adapter->ahw;
3203
3204 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3205 /* Get port configuration info */
3206 status = qlcnic_83xx_get_port_info(adapter);
3207 /* Get Link Status related info */
3208 config = qlcnic_83xx_test_link(adapter);
3209 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3210 }
3211
3212 /* hard code until there is a way to get it from flash */
3213 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3214
3215 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3216 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3217 ecmd->duplex = ahw->link_duplex;
3218 ecmd->autoneg = ahw->link_autoneg;
3219 } else {
3220 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3221 ecmd->duplex = DUPLEX_UNKNOWN;
3222 ecmd->autoneg = AUTONEG_DISABLE;
3223 }
3224
3225 if (ahw->port_type == QLCNIC_XGBE) {
3226 ecmd->supported = SUPPORTED_10000baseT_Full;
3227 ecmd->advertising = ADVERTISED_10000baseT_Full;
3228 } else {
3229 ecmd->supported = (SUPPORTED_10baseT_Half |
3230 SUPPORTED_10baseT_Full |
3231 SUPPORTED_100baseT_Half |
3232 SUPPORTED_100baseT_Full |
3233 SUPPORTED_1000baseT_Half |
3234 SUPPORTED_1000baseT_Full);
3235 ecmd->advertising = (ADVERTISED_100baseT_Half |
3236 ADVERTISED_100baseT_Full |
3237 ADVERTISED_1000baseT_Half |
3238 ADVERTISED_1000baseT_Full);
3239 }
3240
3241 switch (ahw->supported_type) {
3242 case PORT_FIBRE:
3243 ecmd->supported |= SUPPORTED_FIBRE;
3244 ecmd->advertising |= ADVERTISED_FIBRE;
3245 ecmd->port = PORT_FIBRE;
3246 ecmd->transceiver = XCVR_EXTERNAL;
3247 break;
3248 case PORT_TP:
3249 ecmd->supported |= SUPPORTED_TP;
3250 ecmd->advertising |= ADVERTISED_TP;
3251 ecmd->port = PORT_TP;
3252 ecmd->transceiver = XCVR_INTERNAL;
3253 break;
3254 default:
3255 ecmd->supported |= SUPPORTED_FIBRE;
3256 ecmd->advertising |= ADVERTISED_FIBRE;
3257 ecmd->port = PORT_OTHER;
3258 ecmd->transceiver = XCVR_EXTERNAL;
3259 break;
3260 }
3261 ecmd->phy_address = ahw->physical_port;
3262 return status;
3263 }
3264
3265 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3266 struct ethtool_cmd *ecmd)
3267 {
3268 int status = 0;
3269 u32 config = adapter->ahw->port_config;
3270
3271 if (ecmd->autoneg)
3272 adapter->ahw->port_config |= BIT_15;
3273
3274 switch (ethtool_cmd_speed(ecmd)) {
3275 case SPEED_10:
3276 adapter->ahw->port_config |= BIT_8;
3277 break;
3278 case SPEED_100:
3279 adapter->ahw->port_config |= BIT_9;
3280 break;
3281 case SPEED_1000:
3282 adapter->ahw->port_config |= BIT_10;
3283 break;
3284 case SPEED_10000:
3285 adapter->ahw->port_config |= BIT_11;
3286 break;
3287 default:
3288 return -EINVAL;
3289 }
3290
3291 status = qlcnic_83xx_set_port_config(adapter);
3292 if (status) {
3293 dev_info(&adapter->pdev->dev,
3294 "Failed to Set Link Speed and autoneg.\n");
3295 adapter->ahw->port_config = config;
3296 }
3297 return status;
3298 }
3299
3300 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3301 u64 *data, int index)
3302 {
3303 u32 low, hi;
3304 u64 val;
3305
3306 low = cmd->rsp.arg[index];
3307 hi = cmd->rsp.arg[index + 1];
3308 val = (((u64) low) | (((u64) hi) << 32));
3309 *data++ = val;
3310 return data;
3311 }
3312
3313 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3314 struct qlcnic_cmd_args *cmd, u64 *data,
3315 int type, int *ret)
3316 {
3317 int err, k, total_regs;
3318
3319 *ret = 0;
3320 err = qlcnic_issue_cmd(adapter, cmd);
3321 if (err != QLCNIC_RCODE_SUCCESS) {
3322 dev_info(&adapter->pdev->dev,
3323 "Error in get statistics mailbox command\n");
3324 *ret = -EIO;
3325 return data;
3326 }
3327 total_regs = cmd->rsp.num;
3328 switch (type) {
3329 case QLC_83XX_STAT_MAC:
3330 /* fill in MAC tx counters */
3331 for (k = 2; k < 28; k += 2)
3332 data = qlcnic_83xx_copy_stats(cmd, data, k);
3333 /* skip 24 bytes of reserved area */
3334 /* fill in MAC rx counters */
3335 for (k += 6; k < 60; k += 2)
3336 data = qlcnic_83xx_copy_stats(cmd, data, k);
3337 /* skip 24 bytes of reserved area */
3338 /* fill in MAC rx frame stats */
3339 for (k += 6; k < 80; k += 2)
3340 data = qlcnic_83xx_copy_stats(cmd, data, k);
3341 /* fill in eSwitch stats */
3342 for (; k < total_regs; k += 2)
3343 data = qlcnic_83xx_copy_stats(cmd, data, k);
3344 break;
3345 case QLC_83XX_STAT_RX:
3346 for (k = 2; k < 8; k += 2)
3347 data = qlcnic_83xx_copy_stats(cmd, data, k);
3348 /* skip 8 bytes of reserved data */
3349 for (k += 2; k < 24; k += 2)
3350 data = qlcnic_83xx_copy_stats(cmd, data, k);
3351 /* skip 8 bytes containing RE1FBQ error data */
3352 for (k += 2; k < total_regs; k += 2)
3353 data = qlcnic_83xx_copy_stats(cmd, data, k);
3354 break;
3355 case QLC_83XX_STAT_TX:
3356 for (k = 2; k < 10; k += 2)
3357 data = qlcnic_83xx_copy_stats(cmd, data, k);
3358 /* skip 8 bytes of reserved data */
3359 for (k += 2; k < total_regs; k += 2)
3360 data = qlcnic_83xx_copy_stats(cmd, data, k);
3361 break;
3362 default:
3363 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3364 *ret = -EIO;
3365 }
3366 return data;
3367 }
3368
3369 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3370 {
3371 struct qlcnic_cmd_args cmd;
3372 struct net_device *netdev = adapter->netdev;
3373 int ret = 0;
3374
3375 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3376 if (ret)
3377 return;
3378 /* Get Tx stats */
3379 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3380 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3381 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3382 QLC_83XX_STAT_TX, &ret);
3383 if (ret) {
3384 netdev_err(netdev, "Error getting Tx stats\n");
3385 goto out;
3386 }
3387 /* Get MAC stats */
3388 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3389 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3390 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3391 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3392 QLC_83XX_STAT_MAC, &ret);
3393 if (ret) {
3394 netdev_err(netdev, "Error getting MAC stats\n");
3395 goto out;
3396 }
3397 /* Get Rx stats */
3398 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3399 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3400 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3401 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3402 QLC_83XX_STAT_RX, &ret);
3403 if (ret)
3404 netdev_err(netdev, "Error getting Rx stats\n");
3405 out:
3406 qlcnic_free_mbx_args(&cmd);
3407 }
3408
3409 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3410 {
3411 u32 major, minor, sub;
3412
3413 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3414 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3415 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3416
3417 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3418 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3419 __func__);
3420 return 1;
3421 }
3422 return 0;
3423 }
3424
3425 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3426 {
3427 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3428 sizeof(*adapter->ahw->ext_reg_tbl)) +
3429 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3430 sizeof(*adapter->ahw->reg_tbl));
3431 }
3432
3433 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3434 {
3435 int i, j = 0;
3436
3437 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3438 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3439 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3440
3441 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3442 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3443 return i;
3444 }
3445
3446 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3447 {
3448 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3449 struct qlcnic_hardware_context *ahw = adapter->ahw;
3450 struct qlcnic_cmd_args cmd;
3451 u8 val, drv_sds_rings = adapter->drv_sds_rings;
3452 u8 drv_tx_rings = adapter->drv_tx_rings;
3453 u32 data;
3454 u16 intrpt_id, id;
3455 int ret;
3456
3457 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3458 netdev_info(netdev, "Device is resetting\n");
3459 return -EBUSY;
3460 }
3461
3462 if (qlcnic_get_diag_lock(adapter)) {
3463 netdev_info(netdev, "Device in diagnostics mode\n");
3464 return -EBUSY;
3465 }
3466
3467 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3468 drv_sds_rings);
3469 if (ret)
3470 goto fail_diag_irq;
3471
3472 ahw->diag_cnt = 0;
3473 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3474 if (ret)
3475 goto fail_diag_irq;
3476
3477 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3478 intrpt_id = ahw->intr_tbl[0].id;
3479 else
3480 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3481
3482 cmd.req.arg[1] = 1;
3483 cmd.req.arg[2] = intrpt_id;
3484 cmd.req.arg[3] = BIT_0;
3485
3486 ret = qlcnic_issue_cmd(adapter, &cmd);
3487 data = cmd.rsp.arg[2];
3488 id = LSW(data);
3489 val = LSB(MSW(data));
3490 if (id != intrpt_id)
3491 dev_info(&adapter->pdev->dev,
3492 "Interrupt generated: 0x%x, requested:0x%x\n",
3493 id, intrpt_id);
3494 if (val)
3495 dev_err(&adapter->pdev->dev,
3496 "Interrupt test error: 0x%x\n", val);
3497 if (ret)
3498 goto done;
3499
3500 msleep(20);
3501 ret = !ahw->diag_cnt;
3502
3503 done:
3504 qlcnic_free_mbx_args(&cmd);
3505 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3506
3507 fail_diag_irq:
3508 adapter->drv_sds_rings = drv_sds_rings;
3509 adapter->drv_tx_rings = drv_tx_rings;
3510 qlcnic_release_diag_lock(adapter);
3511 return ret;
3512 }
3513
3514 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3515 struct ethtool_pauseparam *pause)
3516 {
3517 struct qlcnic_hardware_context *ahw = adapter->ahw;
3518 int status = 0;
3519 u32 config;
3520
3521 status = qlcnic_83xx_get_port_config(adapter);
3522 if (status) {
3523 dev_err(&adapter->pdev->dev,
3524 "%s: Get Pause Config failed\n", __func__);
3525 return;
3526 }
3527 config = ahw->port_config;
3528 if (config & QLC_83XX_CFG_STD_PAUSE) {
3529 switch (MSW(config)) {
3530 case QLC_83XX_TX_PAUSE:
3531 pause->tx_pause = 1;
3532 break;
3533 case QLC_83XX_RX_PAUSE:
3534 pause->rx_pause = 1;
3535 break;
3536 case QLC_83XX_TX_RX_PAUSE:
3537 default:
3538 /* Backward compatibility for existing
3539 * flash definitions
3540 */
3541 pause->tx_pause = 1;
3542 pause->rx_pause = 1;
3543 }
3544 }
3545
3546 if (QLC_83XX_AUTONEG(config))
3547 pause->autoneg = 1;
3548 }
3549
3550 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3551 struct ethtool_pauseparam *pause)
3552 {
3553 struct qlcnic_hardware_context *ahw = adapter->ahw;
3554 int status = 0;
3555 u32 config;
3556
3557 status = qlcnic_83xx_get_port_config(adapter);
3558 if (status) {
3559 dev_err(&adapter->pdev->dev,
3560 "%s: Get Pause Config failed.\n", __func__);
3561 return status;
3562 }
3563 config = ahw->port_config;
3564
3565 if (ahw->port_type == QLCNIC_GBE) {
3566 if (pause->autoneg)
3567 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3568 if (!pause->autoneg)
3569 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3570 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3571 return -EOPNOTSUPP;
3572 }
3573
3574 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3575 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3576
3577 if (pause->rx_pause && pause->tx_pause) {
3578 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3579 } else if (pause->rx_pause && !pause->tx_pause) {
3580 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3581 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3582 } else if (pause->tx_pause && !pause->rx_pause) {
3583 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3584 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3585 } else if (!pause->rx_pause && !pause->tx_pause) {
3586 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3587 QLC_83XX_CFG_STD_PAUSE);
3588 }
3589 status = qlcnic_83xx_set_port_config(adapter);
3590 if (status) {
3591 dev_err(&adapter->pdev->dev,
3592 "%s: Set Pause Config failed.\n", __func__);
3593 ahw->port_config = config;
3594 }
3595 return status;
3596 }
3597
3598 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3599 {
3600 int ret, err = 0;
3601 u32 temp;
3602
3603 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3604 QLC_83XX_FLASH_OEM_READ_SIG);
3605 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3606 QLC_83XX_FLASH_READ_CTRL);
3607 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3608 if (ret)
3609 return -EIO;
3610
3611 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3612 if (err == -EIO)
3613 return err;
3614
3615 return temp & 0xFF;
3616 }
3617
3618 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3619 {
3620 int status;
3621
3622 status = qlcnic_83xx_read_flash_status_reg(adapter);
3623 if (status == -EIO) {
3624 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3625 __func__);
3626 return 1;
3627 }
3628 return 0;
3629 }
3630
3631 static int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3632 {
3633 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3634 struct net_device *netdev = adapter->netdev;
3635 int retval;
3636
3637 netif_device_detach(netdev);
3638 qlcnic_cancel_idc_work(adapter);
3639
3640 if (netif_running(netdev))
3641 qlcnic_down(adapter, netdev);
3642
3643 qlcnic_83xx_disable_mbx_intr(adapter);
3644 cancel_delayed_work_sync(&adapter->idc_aen_work);
3645
3646 retval = pci_save_state(pdev);
3647 if (retval)
3648 return retval;
3649
3650 return 0;
3651 }
3652
3653 static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3654 {
3655 struct qlcnic_hardware_context *ahw = adapter->ahw;
3656 struct qlc_83xx_idc *idc = &ahw->idc;
3657 int err = 0;
3658
3659 err = qlcnic_83xx_idc_init(adapter);
3660 if (err)
3661 return err;
3662
3663 if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3664 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3665 qlcnic_83xx_set_vnic_opmode(adapter);
3666 } else {
3667 err = qlcnic_83xx_check_vnic_state(adapter);
3668 if (err)
3669 return err;
3670 }
3671 }
3672
3673 err = qlcnic_83xx_idc_reattach_driver(adapter);
3674 if (err)
3675 return err;
3676
3677 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3678 idc->delay);
3679 return err;
3680 }
3681
3682 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3683 {
3684 reinit_completion(&mbx->completion);
3685 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3686 }
3687
3688 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3689 {
3690 if (!mbx)
3691 return;
3692
3693 destroy_workqueue(mbx->work_q);
3694 kfree(mbx);
3695 }
3696
3697 static inline void
3698 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3699 struct qlcnic_cmd_args *cmd)
3700 {
3701 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3702
3703 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3704 qlcnic_free_mbx_args(cmd);
3705 kfree(cmd);
3706 return;
3707 }
3708 complete(&cmd->completion);
3709 }
3710
3711 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3712 {
3713 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3714 struct list_head *head = &mbx->cmd_q;
3715 struct qlcnic_cmd_args *cmd = NULL;
3716
3717 spin_lock(&mbx->queue_lock);
3718
3719 while (!list_empty(head)) {
3720 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3721 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3722 __func__, cmd->cmd_op);
3723 list_del(&cmd->list);
3724 mbx->num_cmds--;
3725 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3726 }
3727
3728 spin_unlock(&mbx->queue_lock);
3729 }
3730
3731 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3732 {
3733 struct qlcnic_hardware_context *ahw = adapter->ahw;
3734 struct qlcnic_mailbox *mbx = ahw->mailbox;
3735 u32 host_mbx_ctrl;
3736
3737 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3738 return -EBUSY;
3739
3740 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3741 if (host_mbx_ctrl) {
3742 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3743 ahw->idc.collect_dump = 1;
3744 return -EIO;
3745 }
3746
3747 return 0;
3748 }
3749
3750 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3751 u8 issue_cmd)
3752 {
3753 if (issue_cmd)
3754 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3755 else
3756 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3757 }
3758
3759 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3760 struct qlcnic_cmd_args *cmd)
3761 {
3762 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3763
3764 spin_lock(&mbx->queue_lock);
3765
3766 list_del(&cmd->list);
3767 mbx->num_cmds--;
3768
3769 spin_unlock(&mbx->queue_lock);
3770
3771 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3772 }
3773
3774 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3775 struct qlcnic_cmd_args *cmd)
3776 {
3777 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3778 struct qlcnic_hardware_context *ahw = adapter->ahw;
3779 int i, j;
3780
3781 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3782 mbx_cmd = cmd->req.arg[0];
3783 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3784 for (i = 1; i < cmd->req.num; i++)
3785 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3786 } else {
3787 fw_hal_version = ahw->fw_hal_version;
3788 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3789 total_size = cmd->pay_size + hdr_size;
3790 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3791 mbx_cmd = tmp | fw_hal_version << 29;
3792 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3793
3794 /* Back channel specific operations bits */
3795 mbx_cmd = 0x1 | 1 << 4;
3796
3797 if (qlcnic_sriov_pf_check(adapter))
3798 mbx_cmd |= cmd->func_num << 5;
3799
3800 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3801
3802 for (i = 2, j = 0; j < hdr_size; i++, j++)
3803 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3804 for (j = 0; j < cmd->pay_size; j++, i++)
3805 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3806 }
3807 }
3808
3809 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3810 {
3811 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3812
3813 if (!mbx)
3814 return;
3815
3816 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3817 complete(&mbx->completion);
3818 cancel_work_sync(&mbx->work);
3819 flush_workqueue(mbx->work_q);
3820 qlcnic_83xx_flush_mbx_queue(adapter);
3821 }
3822
3823 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3824 struct qlcnic_cmd_args *cmd,
3825 unsigned long *timeout)
3826 {
3827 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3828
3829 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3830 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3831 init_completion(&cmd->completion);
3832 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3833
3834 spin_lock(&mbx->queue_lock);
3835
3836 list_add_tail(&cmd->list, &mbx->cmd_q);
3837 mbx->num_cmds++;
3838 cmd->total_cmds = mbx->num_cmds;
3839 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3840 queue_work(mbx->work_q, &mbx->work);
3841
3842 spin_unlock(&mbx->queue_lock);
3843
3844 return 0;
3845 }
3846
3847 return -EBUSY;
3848 }
3849
3850 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3851 struct qlcnic_cmd_args *cmd)
3852 {
3853 u8 mac_cmd_rcode;
3854 u32 fw_data;
3855
3856 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3857 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3858 mac_cmd_rcode = (u8)fw_data;
3859 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3860 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3861 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3862 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3863 return QLCNIC_RCODE_SUCCESS;
3864 }
3865 }
3866
3867 return -EINVAL;
3868 }
3869
3870 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3871 struct qlcnic_cmd_args *cmd)
3872 {
3873 struct qlcnic_hardware_context *ahw = adapter->ahw;
3874 struct device *dev = &adapter->pdev->dev;
3875 u8 mbx_err_code;
3876 u32 fw_data;
3877
3878 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3879 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3880 qlcnic_83xx_get_mbx_data(adapter, cmd);
3881
3882 switch (mbx_err_code) {
3883 case QLCNIC_MBX_RSP_OK:
3884 case QLCNIC_MBX_PORT_RSP_OK:
3885 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3886 break;
3887 default:
3888 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3889 break;
3890
3891 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3892 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3893 ahw->op_mode, mbx_err_code);
3894 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3895 qlcnic_dump_mbx(adapter, cmd);
3896 }
3897
3898 return;
3899 }
3900
3901 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
3902 {
3903 struct qlcnic_hardware_context *ahw = adapter->ahw;
3904 u32 offset;
3905
3906 offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
3907 dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
3908 readl(ahw->pci_base0 + offset),
3909 QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
3910 QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
3911 QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
3912 }
3913
3914 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3915 {
3916 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3917 work);
3918 struct qlcnic_adapter *adapter = mbx->adapter;
3919 struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3920 struct device *dev = &adapter->pdev->dev;
3921 atomic_t *rsp_status = &mbx->rsp_status;
3922 struct list_head *head = &mbx->cmd_q;
3923 struct qlcnic_hardware_context *ahw;
3924 struct qlcnic_cmd_args *cmd = NULL;
3925
3926 ahw = adapter->ahw;
3927
3928 while (true) {
3929 if (qlcnic_83xx_check_mbx_status(adapter)) {
3930 qlcnic_83xx_flush_mbx_queue(adapter);
3931 return;
3932 }
3933
3934 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3935
3936 spin_lock(&mbx->queue_lock);
3937
3938 if (list_empty(head)) {
3939 spin_unlock(&mbx->queue_lock);
3940 return;
3941 }
3942 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3943
3944 spin_unlock(&mbx->queue_lock);
3945
3946 mbx_ops->encode_cmd(adapter, cmd);
3947 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3948
3949 if (wait_for_completion_timeout(&mbx->completion,
3950 QLC_83XX_MBX_TIMEOUT)) {
3951 mbx_ops->decode_resp(adapter, cmd);
3952 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3953 } else {
3954 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3955 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3956 ahw->op_mode);
3957 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3958 qlcnic_dump_mailbox_registers(adapter);
3959 qlcnic_83xx_get_mbx_data(adapter, cmd);
3960 qlcnic_dump_mbx(adapter, cmd);
3961 qlcnic_83xx_idc_request_reset(adapter,
3962 QLCNIC_FORCE_FW_DUMP_KEY);
3963 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3964 }
3965 mbx_ops->dequeue_cmd(adapter, cmd);
3966 }
3967 }
3968
3969 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3970 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
3971 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
3972 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
3973 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
3974 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
3975 };
3976
3977 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3978 {
3979 struct qlcnic_hardware_context *ahw = adapter->ahw;
3980 struct qlcnic_mailbox *mbx;
3981
3982 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3983 if (!ahw->mailbox)
3984 return -ENOMEM;
3985
3986 mbx = ahw->mailbox;
3987 mbx->ops = &qlcnic_83xx_mbx_ops;
3988 mbx->adapter = adapter;
3989
3990 spin_lock_init(&mbx->queue_lock);
3991 spin_lock_init(&mbx->aen_lock);
3992 INIT_LIST_HEAD(&mbx->cmd_q);
3993 init_completion(&mbx->completion);
3994
3995 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3996 if (mbx->work_q == NULL) {
3997 kfree(mbx);
3998 return -ENOMEM;
3999 }
4000
4001 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
4002 set_bit(QLC_83XX_MBX_READY, &mbx->status);
4003 return 0;
4004 }
4005
4006 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
4007 pci_channel_state_t state)
4008 {
4009 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4010
4011 if (state == pci_channel_io_perm_failure)
4012 return PCI_ERS_RESULT_DISCONNECT;
4013
4014 if (state == pci_channel_io_normal)
4015 return PCI_ERS_RESULT_RECOVERED;
4016
4017 set_bit(__QLCNIC_AER, &adapter->state);
4018 set_bit(__QLCNIC_RESETTING, &adapter->state);
4019
4020 qlcnic_83xx_aer_stop_poll_work(adapter);
4021
4022 pci_save_state(pdev);
4023 pci_disable_device(pdev);
4024
4025 return PCI_ERS_RESULT_NEED_RESET;
4026 }
4027
4028 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
4029 {
4030 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4031 int err = 0;
4032
4033 pdev->error_state = pci_channel_io_normal;
4034 err = pci_enable_device(pdev);
4035 if (err)
4036 goto disconnect;
4037
4038 pci_set_power_state(pdev, PCI_D0);
4039 pci_set_master(pdev);
4040 pci_restore_state(pdev);
4041
4042 err = qlcnic_83xx_aer_reset(adapter);
4043 if (err == 0)
4044 return PCI_ERS_RESULT_RECOVERED;
4045 disconnect:
4046 clear_bit(__QLCNIC_AER, &adapter->state);
4047 clear_bit(__QLCNIC_RESETTING, &adapter->state);
4048 return PCI_ERS_RESULT_DISCONNECT;
4049 }
4050
4051 static void qlcnic_83xx_io_resume(struct pci_dev *pdev)
4052 {
4053 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4054
4055 pci_cleanup_aer_uncorrect_error_status(pdev);
4056 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
4057 qlcnic_83xx_aer_start_poll_work(adapter);
4058 }
Linux kernel - Deliverables
This page took 0.122126 seconds and 5 git commands to generate.