drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #ifndef __QLCNIC_83XX_HW_H
   9 #define __QLCNIC_83XX_HW_H
  10
  11 #include <linux/types.h>
  12 #include <linux/etherdevice.h>
  13 #include "qlcnic_hw.h"
  14
  15 /* Directly mapped registers */
  16 #define QLC_83XX_CRB_WIN_BASE           0x3800
  17 #define QLC_83XX_CRB_WIN_FUNC(f)        (QLC_83XX_CRB_WIN_BASE+((f)*4))
  18 #define QLC_83XX_SEM_LOCK_BASE          0x3840
  19 #define QLC_83XX_SEM_UNLOCK_BASE        0x3844
  20 #define QLC_83XX_SEM_LOCK_FUNC(f)       (QLC_83XX_SEM_LOCK_BASE+((f)*8))
  21 #define QLC_83XX_SEM_UNLOCK_FUNC(f)     (QLC_83XX_SEM_UNLOCK_BASE+((f)*8))
  22 #define QLC_83XX_LINK_STATE(f)          (0x3698+((f) > 7 ? 4 : 0))
  23 #define QLC_83XX_LINK_SPEED(f)          (0x36E0+(((f) >> 2) * 4))
  24 #define QLC_83XX_LINK_SPEED_FACTOR      10
  25 #define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4)))
  26 #define QLC_83XX_INTX_PTR               0x38C0
  27 #define QLC_83XX_INTX_TRGR              0x38C4
  28 #define QLC_83XX_INTX_MASK              0x38C8
  29
  30 #define QLC_83XX_DRV_LOCK_WAIT_COUNTER                  100
  31 #define QLC_83XX_DRV_LOCK_WAIT_DELAY                    20
  32 #define QLC_83XX_NEED_DRV_LOCK_RECOVERY         1
  33 #define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS          2
  34 #define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT          3
  35 #define QLC_83XX_DRV_LOCK_RECOVERY_DELAY                200
  36 #define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK          0x3
  37
  38 #define QLC_83XX_NO_NIC_RESOURCE        0x5
  39 #define QLC_83XX_MAC_PRESENT            0xC
  40 #define QLC_83XX_MAC_ABSENT             0xD
  41
  42
  43 #define QLC_83XX_FLASH_SECTOR_SIZE              (64 * 1024)
  44
  45 /* PEG status definitions */
  46 #define QLC_83XX_CMDPEG_COMPLETE                0xff01
  47 #define QLC_83XX_VALID_INTX_BIT30(val)          ((val) & BIT_30)
  48 #define QLC_83XX_VALID_INTX_BIT31(val)          ((val) & BIT_31)
  49 #define QLC_83XX_INTX_FUNC(val)         ((val) & 0xFF)
  50 #define QLC_83XX_LEGACY_INTX_MAX_RETRY          100
  51 #define QLC_83XX_LEGACY_INTX_DELAY              4
  52 #define QLC_83XX_REG_DESC                       1
  53 #define QLC_83XX_LRO_DESC                       2
  54 #define QLC_83XX_CTRL_DESC                      3
  55 #define QLC_83XX_FW_CAPABILITY_TSO              BIT_6
  56 #define QLC_83XX_FW_CAP_LRO_MSS         BIT_17
  57 #define QLC_83XX_HOST_RDS_MODE_UNIQUE           0
  58 #define QLC_83XX_HOST_SDS_MBX_IDX               8
  59
  60 #define QLCNIC_HOST_RDS_MBX_IDX                 88
  61 #define QLCNIC_MAX_RING_SETS                    8
  62
  63 /* Pause control registers */
  64 #define QLC_83XX_SRE_SHIM_REG           0x0D200284
  65 #define QLC_83XX_PORT0_THRESHOLD        0x0B2003A4
  66 #define QLC_83XX_PORT1_THRESHOLD        0x0B2013A4
  67 #define QLC_83XX_PORT0_TC_MC_REG        0x0B200388
  68 #define QLC_83XX_PORT1_TC_MC_REG        0x0B201388
  69 #define QLC_83XX_PORT0_TC_STATS         0x0B20039C
  70 #define QLC_83XX_PORT1_TC_STATS         0x0B20139C
  71 #define QLC_83XX_PORT2_IFB_THRESHOLD    0x0B200704
  72 #define QLC_83XX_PORT3_IFB_THRESHOLD    0x0B201704
  73
  74 /* Peg PC status registers */
  75 #define QLC_83XX_CRB_PEG_NET_0          0x3400003c
  76 #define QLC_83XX_CRB_PEG_NET_1          0x3410003c
  77 #define QLC_83XX_CRB_PEG_NET_2          0x3420003c
  78 #define QLC_83XX_CRB_PEG_NET_3          0x3430003c
  79 #define QLC_83XX_CRB_PEG_NET_4          0x34b0003c
  80
  81 /* Firmware image definitions */
  82 #define QLC_83XX_BOOTLOADER_FLASH_ADDR  0x10000
  83 #define QLC_83XX_FW_FILE_NAME           "83xx_fw.bin"
  84 #define QLC_83XX_BOOT_FROM_FLASH        0
  85 #define QLC_83XX_BOOT_FROM_FILE         0x12345678
  86
  87 #define QLC_83XX_MAX_RESET_SEQ_ENTRIES  16
  88
  89 struct qlcnic_intrpt_config {
  90         u8      type;
  91         u8      enabled;
  92         u16     id;
  93         u32     src;
  94 };
  95
  96 struct qlcnic_macvlan_mbx {
  97         u8      mac[ETH_ALEN];
  98         u16     vlan;
  99 };
 100
 101 struct qlc_83xx_fw_info {
 102         const struct firmware   *fw;
 103         u16     major_fw_version;
 104         u8      minor_fw_version;
 105         u8      sub_fw_version;
 106         u8      fw_build_num;
 107         u8      load_from_file;
 108 };
 109
 110 struct qlc_83xx_reset {
 111         struct qlc_83xx_reset_hdr *hdr;
 112         int     seq_index;
 113         int     seq_error;
 114         int     array_index;
 115         u32     array[QLC_83XX_MAX_RESET_SEQ_ENTRIES];
 116         u8      *buff;
 117         u8      *stop_offset;
 118         u8      *start_offset;
 119         u8      *init_offset;
 120         u8      seq_end;
 121         u8      template_end;
 122 };
 123
 124 #define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY          0x1
 125 #define QLC_83XX_IDC_GRACEFULL_RESET                    0x2
 126 #define QLC_83XX_IDC_TIMESTAMP                          0
 127 #define QLC_83XX_IDC_DURATION                           1
 128 #define QLC_83XX_IDC_INIT_TIMEOUT_SECS                  30
 129 #define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS             10
 130 #define QLC_83XX_IDC_RESET_TIMEOUT_SECS         10
 131 #define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS           20
 132 #define QLC_83XX_IDC_FW_POLL_DELAY                      (1 * HZ)
 133 #define QLC_83XX_IDC_FW_FAIL_THRESH                     2
 134 #define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO        8
 135 #define QLC_83XX_IDC_MAX_CNA_FUNCTIONS                  16
 136 #define QLC_83XX_IDC_MAJOR_VERSION                      1
 137 #define QLC_83XX_IDC_MINOR_VERSION                      0
 138 #define QLC_83XX_IDC_FLASH_PARAM_ADDR                   0x3e8020
 139
 140 struct qlcnic_adapter;
 141 struct qlc_83xx_idc {
 142         int (*state_entry) (struct qlcnic_adapter *);
 143         u64             sec_counter;
 144         u64             delay;
 145         unsigned long   status;
 146         int             err_code;
 147         int             collect_dump;
 148         u8              curr_state;
 149         u8              prev_state;
 150         u8              vnic_state;
 151         u8              vnic_wait_limit;
 152         u8              quiesce_req;
 153         char            **name;
 154 };
 155
 156 #define QLCNIC_MBX_RSP(reg)             LSW(reg)
 157 #define QLCNIC_MBX_NUM_REGS(reg)        (MSW(reg) & 0x1FF)
 158 #define QLCNIC_MBX_STATUS(reg)          (((reg) >> 25) & 0x7F)
 159 #define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4))
 160 #define QLCNIC_MBX_FW(ahw, i)           ((ahw)->pci_base0 + 0x800 + ((i) * 4))
 161
 162 /* Mailbox process AEN count */
 163 #define QLC_83XX_IDC_COMP_AEN                   3
 164 #define QLC_83XX_MBX_AEN_CNT                    5
 165 #define QLC_83XX_MODULE_LOADED                  1
 166 #define QLC_83XX_MBX_READY                      2
 167 #define QLC_83XX_MBX_AEN_ACK                    3
 168 #define QLC_83XX_SFP_PRESENT(data)              ((data) & 3)
 169 #define QLC_83XX_SFP_ERR(data)                  (((data) >> 2) & 3)
 170 #define QLC_83XX_SFP_MODULE_TYPE(data)          (((data) >> 4) & 0x1F)
 171 #define QLC_83XX_SFP_CU_LENGTH(data)            (LSB((data) >> 16))
 172 #define QLC_83XX_SFP_TX_FAULT(data)             ((data) & BIT_10)
 173 #define QLC_83XX_SFP_10G_CAPABLE(data)          ((data) & BIT_11)
 174 #define QLC_83XX_LINK_STATS(data)               ((data) & BIT_0)
 175 #define QLC_83XX_CURRENT_LINK_SPEED(data)       (((data) >> 3) & 7)
 176 #define QLC_83XX_LINK_PAUSE(data)               (((data) >> 6) & 3)
 177 #define QLC_83XX_LINK_LB(data)                  (((data) >> 8) & 7)
 178 #define QLC_83XX_LINK_FEC(data)         ((data) & BIT_12)
 179 #define QLC_83XX_LINK_EEE(data)         ((data) & BIT_13)
 180 #define QLC_83XX_DCBX(data)                     (((data) >> 28) & 7)
 181 #define QLC_83XX_AUTONEG(data)                  ((data) & BIT_15)
 182 #define QLC_83XX_CFG_STD_PAUSE                  (1 << 5)
 183 #define QLC_83XX_CFG_STD_TX_PAUSE               (1 << 20)
 184 #define QLC_83XX_CFG_STD_RX_PAUSE               (2 << 20)
 185 #define QLC_83XX_CFG_STD_TX_RX_PAUSE            (3 << 20)
 186 #define QLC_83XX_ENABLE_AUTONEG         (1 << 15)
 187 #define QLC_83XX_CFG_LOOPBACK_HSS               (2 << 1)
 188 #define QLC_83XX_CFG_LOOPBACK_PHY               (3 << 1)
 189 #define QLC_83XX_CFG_LOOPBACK_EXT               (4 << 1)
 190
 191 /* LED configuration settings */
 192 #define QLC_83XX_ENABLE_BEACON          0xe
 193 #define QLC_83XX_LED_RATE               0xff
 194 #define QLC_83XX_LED_ACT                (1 << 10)
 195 #define QLC_83XX_LED_MOD                (0 << 13)
 196 #define QLC_83XX_LED_CONFIG     (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \
 197                                  QLC_83XX_LED_MOD)
 198
 199 #define QLC_83XX_10M_LINK       1
 200 #define QLC_83XX_100M_LINK      2
 201 #define QLC_83XX_1G_LINK        3
 202 #define QLC_83XX_10G_LINK       4
 203 #define QLC_83XX_STAT_TX        3
 204 #define QLC_83XX_STAT_RX        2
 205 #define QLC_83XX_STAT_MAC       1
 206 #define QLC_83XX_TX_STAT_REGS   14
 207 #define QLC_83XX_RX_STAT_REGS   40
 208 #define QLC_83XX_MAC_STAT_REGS  80
 209
 210 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN)    (0x3 & ((VAL) >> (FN * 2)))
 211 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN)       ((VAL) << (FN * 2))
 212 #define QLC_83XX_DEFAULT_OPMODE                 0x55555555
 213 #define QLC_83XX_PRIVLEGED_FUNC                 0x1
 214 #define QLC_83XX_VIRTUAL_FUNC                           0x2
 215
 216 #define QLC_83XX_LB_MAX_FILTERS                 2048
 217 #define QLC_83XX_LB_BUCKET_SIZE                 256
 218 #define QLC_83XX_MINIMUM_VECTOR                 3
 219
 220 #define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val)      (val & 0x80000000)
 221 #define QLC_83XX_GET_LRO_CAPABILITY(val)                (val & 0x20)
 222 #define QLC_83XX_GET_LSO_CAPABILITY(val)                (val & 0x40)
 223 #define QLC_83XX_GET_LSO_CAPABILITY(val)                (val & 0x40)
 224 #define QLC_83XX_GET_HW_LRO_CAPABILITY(val)             (val & 0x400)
 225 #define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000)
 226 #define QLC_83XX_VIRTUAL_NIC_MODE                       0xFF
 227 #define QLC_83XX_DEFAULT_MODE                           0x0
 228 #define QLCNIC_BRDTYPE_83XX_10G                 0x0083
 229
 230 #define QLC_83XX_FLASH_SPI_STATUS               0x2808E010
 231 #define QLC_83XX_FLASH_SPI_CONTROL              0x2808E014
 232 #define QLC_83XX_FLASH_STATUS                   0x42100004
 233 #define QLC_83XX_FLASH_CONTROL                  0x42110004
 234 #define QLC_83XX_FLASH_ADDR                     0x42110008
 235 #define QLC_83XX_FLASH_WRDATA                   0x4211000C
 236 #define QLC_83XX_FLASH_RDDATA                   0x42110018
 237 #define QLC_83XX_FLASH_DIRECT_WINDOW            0x42110030
 238 #define QLC_83XX_FLASH_DIRECT_DATA(DATA)        (0x42150000 | (0x0000FFFF&DATA))
 239 #define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
 240 #define QLC_83XX_FLASH_WRITE_CMD                0xdacdacda
 241 #define QLC_83XX_FLASH_BULK_WRITE_CMD           0xcadcadca
 242 #define QLC_83XX_FLASH_READ_RETRY_COUNT 5000
 243 #define QLC_83XX_FLASH_STATUS_READY             0x6
 244 #define QLC_83XX_FLASH_BULK_WRITE_MIN           2
 245 #define QLC_83XX_FLASH_BULK_WRITE_MAX           64
 246 #define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY    1
 247 #define QLC_83XX_ERASE_MODE                     1
 248 #define QLC_83XX_WRITE_MODE                     2
 249 #define QLC_83XX_BULK_WRITE_MODE                3
 250 #define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG        0xFD0100
 251 #define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG        0xFD0300
 252 #define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL      0xFD009F
 253 #define QLC_83XX_FLASH_OEM_ERASE_SIG            0xFD03D8
 254 #define QLC_83XX_FLASH_OEM_WRITE_SIG            0xFD0101
 255 #define QLC_83XX_FLASH_OEM_READ_SIG             0xFD0005
 256 #define QLC_83XX_FLASH_ADDR_TEMP_VAL            0x00800000
 257 #define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL     0x00800001
 258 #define QLC_83XX_FLASH_WRDATA_DEF               0x0
 259 #define QLC_83XX_FLASH_READ_CTRL                0x3F
 260 #define QLC_83XX_FLASH_SPI_CTRL         0x4
 261 #define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL       0x2
 262 #define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL      0x5
 263 #define QLC_83XX_FLASH_LAST_ERASE_MS_VAL        0x3D
 264 #define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43
 265 #define QLC_83XX_FLASH_SECOND_MS_PATTERN        0x7F
 266 #define QLC_83XX_FLASH_LAST_MS_PATTERN          0x7D
 267 #define QLC_83xx_FLASH_MAX_WAIT_USEC            100
 268 #define QLC_83XX_FLASH_LOCK_TIMEOUT             10000
 269
 270 /* Additional registers in 83xx */
 271 enum qlc_83xx_ext_regs {
 272         QLCNIC_GLOBAL_RESET = 0,
 273         QLCNIC_WILDCARD,
 274         QLCNIC_INFORMANT,
 275         QLCNIC_HOST_MBX_CTRL,
 276         QLCNIC_FW_MBX_CTRL,
 277         QLCNIC_BOOTLOADER_ADDR,
 278         QLCNIC_BOOTLOADER_SIZE,
 279         QLCNIC_FW_IMAGE_ADDR,
 280         QLCNIC_MBX_INTR_ENBL,
 281         QLCNIC_DEF_INT_MASK,
 282         QLCNIC_DEF_INT_ID,
 283         QLC_83XX_IDC_MAJ_VERSION,
 284         QLC_83XX_IDC_DEV_STATE,
 285         QLC_83XX_IDC_DRV_PRESENCE,
 286         QLC_83XX_IDC_DRV_ACK,
 287         QLC_83XX_IDC_CTRL,
 288         QLC_83XX_IDC_DRV_AUDIT,
 289         QLC_83XX_IDC_MIN_VERSION,
 290         QLC_83XX_RECOVER_DRV_LOCK,
 291         QLC_83XX_IDC_PF_0,
 292         QLC_83XX_IDC_PF_1,
 293         QLC_83XX_IDC_PF_2,
 294         QLC_83XX_IDC_PF_3,
 295         QLC_83XX_IDC_PF_4,
 296         QLC_83XX_IDC_PF_5,
 297         QLC_83XX_IDC_PF_6,
 298         QLC_83XX_IDC_PF_7,
 299         QLC_83XX_IDC_PF_8,
 300         QLC_83XX_IDC_PF_9,
 301         QLC_83XX_IDC_PF_10,
 302         QLC_83XX_IDC_PF_11,
 303         QLC_83XX_IDC_PF_12,
 304         QLC_83XX_IDC_PF_13,
 305         QLC_83XX_IDC_PF_14,
 306         QLC_83XX_IDC_PF_15,
 307         QLC_83XX_IDC_DEV_PARTITION_INFO_1,
 308         QLC_83XX_IDC_DEV_PARTITION_INFO_2,
 309         QLC_83XX_DRV_OP_MODE,
 310         QLC_83XX_VNIC_STATE,
 311         QLC_83XX_DRV_LOCK,
 312         QLC_83XX_DRV_UNLOCK,
 313         QLC_83XX_DRV_LOCK_ID,
 314         QLC_83XX_ASIC_TEMP,
 315 };
 316
 317 /* 83xx funcitons */
 318 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *);
 319 int qlcnic_83xx_mbx_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
 320 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8);
 321 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *);
 322 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *);
 323 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *);
 324 int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32);
 325 void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *);
 326 void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *);
 327 void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
 328 void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
 329 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong);
 330 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32);
 331 void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []);
 332 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32);
 333 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
 334 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
 335 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int);
 336 int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int);
 337 int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *);
 338 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, __le16);
 339 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *);
 340 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
 341 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int);
 342
 343 int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *);
 344 void qlcnic_83xx_napi_del(struct qlcnic_adapter *);
 345 void qlcnic_83xx_napi_enable(struct qlcnic_adapter *);
 346 void qlcnic_83xx_napi_disable(struct qlcnic_adapter *);
 347 int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32);
 348 void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32);
 349 int qlcnic_ind_rd(struct qlcnic_adapter *, u32);
 350 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *);
 351 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *,
 352                               struct qlcnic_host_tx_ring *, int);
 353 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
 354 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int);
 355 void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *);
 356 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool);
 357 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, __le16, u8);
 358 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *);
 359 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
 360                                struct qlcnic_cmd_args *);
 361 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *,
 362                                struct qlcnic_adapter *, u32);
 363 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *);
 364 void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *,
 365                           struct qlcnic_info *);
 366 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *);
 367 irqreturn_t qlcnic_83xx_handle_aen(int, void *);
 368 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *);
 369 void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *);
 370 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *);
 371 irqreturn_t qlcnic_83xx_intr(int, void *);
 372 irqreturn_t qlcnic_83xx_tmp_intr(int, void *);
 373 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *,
 374                              struct qlcnic_host_sds_ring *);
 375 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *,
 376                              struct qlcnic_host_sds_ring *);
 377 void qlcnic_83xx_check_vf(struct qlcnic_adapter *,
 378                           const struct pci_device_id *);
 379 void qlcnic_83xx_process_aen(struct qlcnic_adapter *);
 380 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
 381 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
 382 int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8);
 383 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *);
 384 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *);
 385 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *);
 386 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);
 387 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);
 388 void qlcnic_83xx_idc_aen_work(struct work_struct *);
 389 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);
 390
 391 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32);
 392 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int);
 393 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *);
 394 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *);
 395 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *);
 396 int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *);
 397 int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int);
 398 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *);
 399 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *);
 400 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int);
 401 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *,
 402                                       u32, u8 *, int);
 403 int qlcnic_83xx_init(struct qlcnic_adapter *);
 404 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *);
 405 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev);
 406 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *);
 407 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *);
 408 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *);
 409 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32);
 410 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *);
 411 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *);
 412 int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *);
 413 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32);
 414 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *);
 415 int qlcnic_83xx_enable_vnic_mode(struct qlcnic_adapter *, int);
 416 int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int);
 417 int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *);
 418 int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *,
 419                                     struct qlcnic_info *, u8);
 420 int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *);
 421
 422 void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *);
 423 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data);
 424 int qlcnic_83xx_get_settings(struct qlcnic_adapter *);
 425 int qlcnic_83xx_set_settings(struct qlcnic_adapter *, struct ethtool_cmd *);
 426 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *,
 427                                 struct ethtool_pauseparam *);
 428 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *,
 429                                struct ethtool_pauseparam *);
 430 int qlcnic_83xx_test_link(struct qlcnic_adapter *);
 431 int qlcnic_83xx_reg_test(struct qlcnic_adapter *);
 432 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *);
 433 int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *);
 434 int qlcnic_83xx_loopback_test(struct net_device *, u8);
 435 int qlcnic_83xx_interrupt_test(struct net_device *);
 436 int qlcnic_83xx_flash_test(struct qlcnic_adapter *);
 437 #endif