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51716ab8739ad9fc2009f6939d2661b1b37f906c
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_hw.c
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9 #include "qlcnic_hdr.h"
10
11 #include <linux/slab.h>
12 #include <net/ip.h>
13 #include <linux/bitops.h>
14
15 #define MASK(n) ((1ULL<<(n))-1)
16 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
17
18 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
19
20 #define CRB_BLK(off) ((off >> 20) & 0x3f)
21 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
22 #define CRB_WINDOW_2M (0x130060)
23 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
24 #define CRB_INDIRECT_2M (0x1e0000UL)
25
26 struct qlcnic_ms_reg_ctrl {
27 u32 ocm_window;
28 u32 control;
29 u32 hi;
30 u32 low;
31 u32 rd[4];
32 u32 wd[4];
33 u64 off;
34 };
35
36 #ifndef readq
37 static inline u64 readq(void __iomem *addr)
38 {
39 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
40 }
41 #endif
42
43 #ifndef writeq
44 static inline void writeq(u64 val, void __iomem *addr)
45 {
46 writel(((u32) (val)), (addr));
47 writel(((u32) (val >> 32)), (addr + 4));
48 }
49 #endif
50
51 static struct crb_128M_2M_block_map
52 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
53 {{{0, 0, 0, 0} } }, /* 0: PCI */
54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
55 {1, 0x0110000, 0x0120000, 0x130000},
56 {1, 0x0120000, 0x0122000, 0x124000},
57 {1, 0x0130000, 0x0132000, 0x126000},
58 {1, 0x0140000, 0x0142000, 0x128000},
59 {1, 0x0150000, 0x0152000, 0x12a000},
60 {1, 0x0160000, 0x0170000, 0x110000},
61 {1, 0x0170000, 0x0172000, 0x12e000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {1, 0x01e0000, 0x01e0800, 0x122000},
69 {0, 0x0000000, 0x0000000, 0x000000} } },
70 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
71 {{{0, 0, 0, 0} } }, /* 3: */
72 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
73 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
76 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {1, 0x08f0000, 0x08f2000, 0x172000} } },
92 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x09f0000, 0x09f2000, 0x176000} } },
108 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
124 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
145 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
146 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
147 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
148 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
149 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
150 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
151 {{{0, 0, 0, 0} } }, /* 23: */
152 {{{0, 0, 0, 0} } }, /* 24: */
153 {{{0, 0, 0, 0} } }, /* 25: */
154 {{{0, 0, 0, 0} } }, /* 26: */
155 {{{0, 0, 0, 0} } }, /* 27: */
156 {{{0, 0, 0, 0} } }, /* 28: */
157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
160 {{{0} } }, /* 32: PCI */
161 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
162 {1, 0x2110000, 0x2120000, 0x130000},
163 {1, 0x2120000, 0x2122000, 0x124000},
164 {1, 0x2130000, 0x2132000, 0x126000},
165 {1, 0x2140000, 0x2142000, 0x128000},
166 {1, 0x2150000, 0x2152000, 0x12a000},
167 {1, 0x2160000, 0x2170000, 0x110000},
168 {1, 0x2170000, 0x2172000, 0x12e000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000} } },
177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
178 {{{0} } }, /* 35: */
179 {{{0} } }, /* 36: */
180 {{{0} } }, /* 37: */
181 {{{0} } }, /* 38: */
182 {{{0} } }, /* 39: */
183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
195 {{{0} } }, /* 52: */
196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
202 {{{0} } }, /* 59: I2C0 */
203 {{{0} } }, /* 60: I2C1 */
204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
207 };
208
209 /*
210 * top 12 bits of crb internal address (hub, agent)
211 */
212 static const unsigned crb_hub_agt[64] = {
213 0,
214 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
215 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
216 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
217 0,
218 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
219 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
223 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
240 0,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
243 0,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
245 0,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
248 0,
249 0,
250 0,
251 0,
252 0,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
254 0,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
260 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
265 0,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
270 0,
271 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
274 0,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
276 0,
277 };
278
279 static const u32 msi_tgt_status[8] = {
280 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
281 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
282 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
283 ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
284 };
285
286 /* PCI Windowing for DDR regions. */
287
288 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
289
290 static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
291 {
292 u32 dest;
293 void __iomem *val;
294
295 dest = addr & 0xFFFF0000;
296 val = bar0 + QLCNIC_FW_DUMP_REG1;
297 writel(dest, val);
298 readl(val);
299 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
300 *data = readl(val);
301 }
302
303 static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
304 {
305 u32 dest;
306 void __iomem *val;
307
308 dest = addr & 0xFFFF0000;
309 val = bar0 + QLCNIC_FW_DUMP_REG1;
310 writel(dest, val);
311 readl(val);
312 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
313 writel(data, val);
314 readl(val);
315 }
316
317 int
318 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
319 {
320 int done = 0, timeout = 0;
321
322 while (!done) {
323 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
324 if (done == 1)
325 break;
326 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
327 dev_err(&adapter->pdev->dev,
328 "Failed to acquire sem=%d lock; holdby=%d\n",
329 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
330 return -EIO;
331 }
332 msleep(1);
333 }
334
335 if (id_reg)
336 QLCWR32(adapter, id_reg, adapter->portnum);
337
338 return 0;
339 }
340
341 void
342 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
343 {
344 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
345 }
346
347 int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
348 {
349 u32 data;
350
351 if (qlcnic_82xx_check(adapter))
352 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
353 else {
354 data = qlcnic_83xx_rd_reg_indirect(adapter, addr);
355 if (data == -EIO)
356 return -EIO;
357 }
358 return data;
359 }
360
361 void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
362 {
363 if (qlcnic_82xx_check(adapter))
364 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
365 else
366 qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
367 }
368
369 static int
370 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
371 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
372 {
373 u32 i, producer;
374 struct qlcnic_cmd_buffer *pbuf;
375 struct cmd_desc_type0 *cmd_desc;
376 struct qlcnic_host_tx_ring *tx_ring;
377
378 i = 0;
379
380 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
381 return -EIO;
382
383 tx_ring = adapter->tx_ring;
384 __netif_tx_lock_bh(tx_ring->txq);
385
386 producer = tx_ring->producer;
387
388 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
389 netif_tx_stop_queue(tx_ring->txq);
390 smp_mb();
391 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
392 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
393 netif_tx_wake_queue(tx_ring->txq);
394 } else {
395 adapter->stats.xmit_off++;
396 __netif_tx_unlock_bh(tx_ring->txq);
397 return -EBUSY;
398 }
399 }
400
401 do {
402 cmd_desc = &cmd_desc_arr[i];
403
404 pbuf = &tx_ring->cmd_buf_arr[producer];
405 pbuf->skb = NULL;
406 pbuf->frag_count = 0;
407
408 memcpy(&tx_ring->desc_head[producer],
409 cmd_desc, sizeof(struct cmd_desc_type0));
410
411 producer = get_next_index(producer, tx_ring->num_desc);
412 i++;
413
414 } while (i != nr_desc);
415
416 tx_ring->producer = producer;
417
418 qlcnic_update_cmd_producer(tx_ring);
419
420 __netif_tx_unlock_bh(tx_ring->txq);
421
422 return 0;
423 }
424
425 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
426 __le16 vlan_id, u8 op)
427 {
428 struct qlcnic_nic_req req;
429 struct qlcnic_mac_req *mac_req;
430 struct qlcnic_vlan_req *vlan_req;
431 u64 word;
432
433 memset(&req, 0, sizeof(struct qlcnic_nic_req));
434 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
435
436 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
437 req.req_hdr = cpu_to_le64(word);
438
439 mac_req = (struct qlcnic_mac_req *)&req.words[0];
440 mac_req->op = op;
441 memcpy(mac_req->mac_addr, addr, 6);
442
443 vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
444 vlan_req->vlan_id = vlan_id;
445
446 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
447 }
448
449 int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
450 {
451 struct list_head *head;
452 struct qlcnic_mac_list_s *cur;
453 int err = -EINVAL;
454
455 /* Delete MAC from the existing list */
456 list_for_each(head, &adapter->mac_list) {
457 cur = list_entry(head, struct qlcnic_mac_list_s, list);
458 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
459 err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
460 0, QLCNIC_MAC_DEL);
461 if (err)
462 return err;
463 list_del(&cur->list);
464 kfree(cur);
465 return err;
466 }
467 }
468 return err;
469 }
470
471 int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr)
472 {
473 struct list_head *head;
474 struct qlcnic_mac_list_s *cur;
475
476 /* look up if already exists */
477 list_for_each(head, &adapter->mac_list) {
478 cur = list_entry(head, struct qlcnic_mac_list_s, list);
479 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
480 return 0;
481 }
482
483 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
484 if (cur == NULL)
485 return -ENOMEM;
486
487 memcpy(cur->mac_addr, addr, ETH_ALEN);
488
489 if (qlcnic_sre_macaddr_change(adapter,
490 cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
491 kfree(cur);
492 return -EIO;
493 }
494
495 list_add_tail(&cur->list, &adapter->mac_list);
496 return 0;
497 }
498
499 void qlcnic_set_multi(struct net_device *netdev)
500 {
501 struct qlcnic_adapter *adapter = netdev_priv(netdev);
502 struct netdev_hw_addr *ha;
503 static const u8 bcast_addr[ETH_ALEN] = {
504 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
505 };
506 u32 mode = VPORT_MISS_MODE_DROP;
507
508 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
509 return;
510
511 qlcnic_nic_add_mac(adapter, adapter->mac_addr);
512 qlcnic_nic_add_mac(adapter, bcast_addr);
513
514 if (netdev->flags & IFF_PROMISC) {
515 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
516 mode = VPORT_MISS_MODE_ACCEPT_ALL;
517 goto send_fw_cmd;
518 }
519
520 if ((netdev->flags & IFF_ALLMULTI) ||
521 (netdev_mc_count(netdev) > adapter->ahw->max_mc_count)) {
522 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
523 goto send_fw_cmd;
524 }
525
526 if (!netdev_mc_empty(netdev)) {
527 netdev_for_each_mc_addr(ha, netdev) {
528 qlcnic_nic_add_mac(adapter, ha->addr);
529 }
530 }
531
532 send_fw_cmd:
533 if (mode == VPORT_MISS_MODE_ACCEPT_ALL && !adapter->fdb_mac_learn) {
534 qlcnic_alloc_lb_filters_mem(adapter);
535 adapter->drv_mac_learn = true;
536 } else {
537 adapter->drv_mac_learn = false;
538 }
539
540 qlcnic_nic_set_promisc(adapter, mode);
541 }
542
543 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
544 {
545 struct qlcnic_nic_req req;
546 u64 word;
547
548 memset(&req, 0, sizeof(struct qlcnic_nic_req));
549
550 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
551
552 word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
553 ((u64)adapter->portnum << 16);
554 req.req_hdr = cpu_to_le64(word);
555
556 req.words[0] = cpu_to_le64(mode);
557
558 return qlcnic_send_cmd_descs(adapter,
559 (struct cmd_desc_type0 *)&req, 1);
560 }
561
562 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
563 {
564 struct qlcnic_mac_list_s *cur;
565 struct list_head *head = &adapter->mac_list;
566
567 while (!list_empty(head)) {
568 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
569 qlcnic_sre_macaddr_change(adapter,
570 cur->mac_addr, 0, QLCNIC_MAC_DEL);
571 list_del(&cur->list);
572 kfree(cur);
573 }
574 }
575
576 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
577 {
578 struct qlcnic_filter *tmp_fil;
579 struct hlist_node *tmp_hnode, *n;
580 struct hlist_head *head;
581 int i, time;
582 u8 cmd;
583
584 for (i = 0; i < adapter->fhash.fbucket_size; i++) {
585 head = &(adapter->fhash.fhead[i]);
586 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
587 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
588 QLCNIC_MAC_DEL;
589 time = tmp_fil->ftime;
590 if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
591 qlcnic_sre_macaddr_change(adapter,
592 tmp_fil->faddr,
593 tmp_fil->vlan_id,
594 cmd);
595 spin_lock_bh(&adapter->mac_learn_lock);
596 adapter->fhash.fnum--;
597 hlist_del(&tmp_fil->fnode);
598 spin_unlock_bh(&adapter->mac_learn_lock);
599 kfree(tmp_fil);
600 }
601 }
602 }
603 }
604
605 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
606 {
607 struct qlcnic_filter *tmp_fil;
608 struct hlist_node *tmp_hnode, *n;
609 struct hlist_head *head;
610 int i;
611 u8 cmd;
612
613 for (i = 0; i < adapter->fhash.fbucket_size; i++) {
614 head = &(adapter->fhash.fhead[i]);
615 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
616 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
617 QLCNIC_MAC_DEL;
618 qlcnic_sre_macaddr_change(adapter,
619 tmp_fil->faddr,
620 tmp_fil->vlan_id,
621 cmd);
622 spin_lock_bh(&adapter->mac_learn_lock);
623 adapter->fhash.fnum--;
624 hlist_del(&tmp_fil->fnode);
625 spin_unlock_bh(&adapter->mac_learn_lock);
626 kfree(tmp_fil);
627 }
628 }
629 }
630
631 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
632 {
633 struct qlcnic_nic_req req;
634 int rv;
635
636 memset(&req, 0, sizeof(struct qlcnic_nic_req));
637
638 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
639 req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
640 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
641
642 req.words[0] = cpu_to_le64(flag);
643
644 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
645 if (rv != 0)
646 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
647 flag ? "Set" : "Reset");
648 return rv;
649 }
650
651 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
652 {
653 if (qlcnic_set_fw_loopback(adapter, mode))
654 return -EIO;
655
656 if (qlcnic_nic_set_promisc(adapter,
657 VPORT_MISS_MODE_ACCEPT_ALL)) {
658 qlcnic_set_fw_loopback(adapter, 0);
659 return -EIO;
660 }
661
662 msleep(1000);
663 return 0;
664 }
665
666 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
667 {
668 struct net_device *netdev = adapter->netdev;
669
670 mode = VPORT_MISS_MODE_DROP;
671 qlcnic_set_fw_loopback(adapter, 0);
672
673 if (netdev->flags & IFF_PROMISC)
674 mode = VPORT_MISS_MODE_ACCEPT_ALL;
675 else if (netdev->flags & IFF_ALLMULTI)
676 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
677
678 qlcnic_nic_set_promisc(adapter, mode);
679 msleep(1000);
680 return 0;
681 }
682
683 /*
684 * Send the interrupt coalescing parameter set by ethtool to the card.
685 */
686 void qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter)
687 {
688 struct qlcnic_nic_req req;
689 int rv;
690
691 memset(&req, 0, sizeof(struct qlcnic_nic_req));
692
693 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
694
695 req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
696 ((u64) adapter->portnum << 16));
697
698 req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
699 req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
700 ((u64) adapter->ahw->coal.rx_time_us) << 16);
701 req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
702 ((u64) adapter->ahw->coal.type) << 32 |
703 ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
704 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
705 if (rv != 0)
706 dev_err(&adapter->netdev->dev,
707 "Could not send interrupt coalescing parameters\n");
708 }
709
710 #define QLCNIC_ENABLE_IPV4_LRO 1
711 #define QLCNIC_ENABLE_IPV6_LRO 2
712 #define QLCNIC_NO_DEST_IPV4_CHECK (1 << 8)
713 #define QLCNIC_NO_DEST_IPV6_CHECK (2 << 8)
714
715 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
716 {
717 struct qlcnic_nic_req req;
718 u64 word;
719 int rv;
720
721 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
722 return 0;
723
724 memset(&req, 0, sizeof(struct qlcnic_nic_req));
725
726 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
727
728 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
729 req.req_hdr = cpu_to_le64(word);
730
731 word = 0;
732 if (enable) {
733 word = QLCNIC_ENABLE_IPV4_LRO | QLCNIC_NO_DEST_IPV4_CHECK;
734 if (adapter->ahw->capabilities2 & QLCNIC_FW_CAP2_HW_LRO_IPV6)
735 word |= QLCNIC_ENABLE_IPV6_LRO |
736 QLCNIC_NO_DEST_IPV6_CHECK;
737 }
738
739 req.words[0] = cpu_to_le64(word);
740
741 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
742 if (rv != 0)
743 dev_err(&adapter->netdev->dev,
744 "Could not send configure hw lro request\n");
745
746 return rv;
747 }
748
749 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
750 {
751 struct qlcnic_nic_req req;
752 u64 word;
753 int rv;
754
755 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
756 return 0;
757
758 memset(&req, 0, sizeof(struct qlcnic_nic_req));
759
760 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
761
762 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
763 ((u64)adapter->portnum << 16);
764 req.req_hdr = cpu_to_le64(word);
765
766 req.words[0] = cpu_to_le64(enable);
767
768 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
769 if (rv != 0)
770 dev_err(&adapter->netdev->dev,
771 "Could not send configure bridge mode request\n");
772
773 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
774
775 return rv;
776 }
777
778
779 #define QLCNIC_RSS_HASHTYPE_IP_TCP 0x3
780 #define QLCNIC_ENABLE_TYPE_C_RSS BIT_10
781 #define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
782 #define QLCNIC_RSS_IND_TABLE_MASK 0x7ULL
783
784 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
785 {
786 struct qlcnic_nic_req req;
787 u64 word;
788 int i, rv;
789
790 static const u64 key[] = {
791 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
792 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
793 0x255b0ec26d5a56daULL
794 };
795
796 memset(&req, 0, sizeof(struct qlcnic_nic_req));
797 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
798
799 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
800 req.req_hdr = cpu_to_le64(word);
801
802 /*
803 * RSS request:
804 * bits 3-0: hash_method
805 * 5-4: hash_type_ipv4
806 * 7-6: hash_type_ipv6
807 * 8: enable
808 * 9: use indirection table
809 * 10: type-c rss
810 * 11: udp rss
811 * 47-12: reserved
812 * 62-48: indirection table mask
813 * 63: feature flag
814 */
815 word = ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
816 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
817 ((u64)(enable & 0x1) << 8) |
818 ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
819 (u64)QLCNIC_ENABLE_TYPE_C_RSS |
820 (u64)QLCNIC_RSS_FEATURE_FLAG;
821
822 req.words[0] = cpu_to_le64(word);
823 for (i = 0; i < 5; i++)
824 req.words[i+1] = cpu_to_le64(key[i]);
825
826 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
827 if (rv != 0)
828 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
829
830 return rv;
831 }
832
833 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
834 __be32 ip, int cmd)
835 {
836 struct qlcnic_nic_req req;
837 struct qlcnic_ipaddr *ipa;
838 u64 word;
839 int rv;
840
841 memset(&req, 0, sizeof(struct qlcnic_nic_req));
842 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
843
844 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
845 req.req_hdr = cpu_to_le64(word);
846
847 req.words[0] = cpu_to_le64(cmd);
848 ipa = (struct qlcnic_ipaddr *)&req.words[1];
849 ipa->ipv4 = ip;
850
851 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
852 if (rv != 0)
853 dev_err(&adapter->netdev->dev,
854 "could not notify %s IP 0x%x reuqest\n",
855 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
856 }
857
858 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
859 {
860 struct qlcnic_nic_req req;
861 u64 word;
862 int rv;
863 memset(&req, 0, sizeof(struct qlcnic_nic_req));
864 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
865
866 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
867 req.req_hdr = cpu_to_le64(word);
868 req.words[0] = cpu_to_le64(enable | (enable << 8));
869 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
870 if (rv != 0)
871 dev_err(&adapter->netdev->dev,
872 "could not configure link notification\n");
873
874 return rv;
875 }
876
877 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
878 {
879 struct qlcnic_nic_req req;
880 u64 word;
881 int rv;
882
883 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
884 return 0;
885
886 memset(&req, 0, sizeof(struct qlcnic_nic_req));
887 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
888
889 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
890 ((u64)adapter->portnum << 16) |
891 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
892
893 req.req_hdr = cpu_to_le64(word);
894
895 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
896 if (rv != 0)
897 dev_err(&adapter->netdev->dev,
898 "could not cleanup lro flows\n");
899
900 return rv;
901 }
902
903 /*
904 * qlcnic_change_mtu - Change the Maximum Transfer Unit
905 * @returns 0 on success, negative on failure
906 */
907
908 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
909 {
910 struct qlcnic_adapter *adapter = netdev_priv(netdev);
911 int rc = 0;
912
913 if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
914 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
915 " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
916 return -EINVAL;
917 }
918
919 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
920
921 if (!rc)
922 netdev->mtu = mtu;
923
924 return rc;
925 }
926
927
928 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
929 netdev_features_t features)
930 {
931 struct qlcnic_adapter *adapter = netdev_priv(netdev);
932
933 if ((adapter->flags & QLCNIC_ESWITCH_ENABLED) &&
934 qlcnic_82xx_check(adapter)) {
935 netdev_features_t changed = features ^ netdev->features;
936 features ^= changed & (NETIF_F_ALL_CSUM | NETIF_F_RXCSUM);
937 }
938
939 if (!(features & NETIF_F_RXCSUM))
940 features &= ~NETIF_F_LRO;
941
942 return features;
943 }
944
945
946 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
947 {
948 struct qlcnic_adapter *adapter = netdev_priv(netdev);
949 netdev_features_t changed = netdev->features ^ features;
950 int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
951
952 if (!(changed & NETIF_F_LRO))
953 return 0;
954
955 netdev->features ^= NETIF_F_LRO;
956
957 if (qlcnic_config_hw_lro(adapter, hw_lro))
958 return -EIO;
959
960 if (!hw_lro && qlcnic_82xx_check(adapter)) {
961 if (qlcnic_send_lro_cleanup(adapter))
962 return -EIO;
963 }
964
965 return 0;
966 }
967
968 /*
969 * Changes the CRB window to the specified window.
970 */
971 /* Returns < 0 if off is not valid,
972 * 1 if window access is needed. 'off' is set to offset from
973 * CRB space in 128M pci map
974 * 0 if no window access is needed. 'off' is set to 2M addr
975 * In: 'off' is offset from base in 128M pci map
976 */
977 static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
978 ulong off, void __iomem **addr)
979 {
980 const struct crb_128M_2M_sub_block_map *m;
981
982 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
983 return -EINVAL;
984
985 off -= QLCNIC_PCI_CRBSPACE;
986
987 /*
988 * Try direct map
989 */
990 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
991
992 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
993 *addr = ahw->pci_base0 + m->start_2M +
994 (off - m->start_128M);
995 return 0;
996 }
997
998 /*
999 * Not in direct map, use crb window
1000 */
1001 *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
1002 return 1;
1003 }
1004
1005 /*
1006 * In: 'off' is offset from CRB space in 128M pci map
1007 * Out: 'off' is 2M pci map addr
1008 * side effect: lock crb window
1009 */
1010 static int
1011 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1012 {
1013 u32 window;
1014 void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
1015
1016 off -= QLCNIC_PCI_CRBSPACE;
1017
1018 window = CRB_HI(off);
1019 if (window == 0) {
1020 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1021 return -EIO;
1022 }
1023
1024 writel(window, addr);
1025 if (readl(addr) != window) {
1026 if (printk_ratelimit())
1027 dev_warn(&adapter->pdev->dev,
1028 "failed to set CRB window to %d off 0x%lx\n",
1029 window, off);
1030 return -EIO;
1031 }
1032 return 0;
1033 }
1034
1035 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1036 u32 data)
1037 {
1038 unsigned long flags;
1039 int rv;
1040 void __iomem *addr = NULL;
1041
1042 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1043
1044 if (rv == 0) {
1045 writel(data, addr);
1046 return 0;
1047 }
1048
1049 if (rv > 0) {
1050 /* indirect access */
1051 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1052 crb_win_lock(adapter);
1053 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1054 if (!rv)
1055 writel(data, addr);
1056 crb_win_unlock(adapter);
1057 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1058 return rv;
1059 }
1060
1061 dev_err(&adapter->pdev->dev,
1062 "%s: invalid offset: 0x%016lx\n", __func__, off);
1063 dump_stack();
1064 return -EIO;
1065 }
1066
1067 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
1068 {
1069 unsigned long flags;
1070 int rv;
1071 u32 data = -1;
1072 void __iomem *addr = NULL;
1073
1074 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1075
1076 if (rv == 0)
1077 return readl(addr);
1078
1079 if (rv > 0) {
1080 /* indirect access */
1081 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1082 crb_win_lock(adapter);
1083 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1084 data = readl(addr);
1085 crb_win_unlock(adapter);
1086 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1087 return data;
1088 }
1089
1090 dev_err(&adapter->pdev->dev,
1091 "%s: invalid offset: 0x%016lx\n", __func__, off);
1092 dump_stack();
1093 return -1;
1094 }
1095
1096 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1097 u32 offset)
1098 {
1099 void __iomem *addr = NULL;
1100
1101 WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
1102
1103 return addr;
1104 }
1105
1106 static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1107 u32 window, u64 off, u64 *data, int op)
1108 {
1109 void __iomem *addr;
1110 u32 start;
1111
1112 mutex_lock(&adapter->ahw->mem_lock);
1113
1114 writel(window, adapter->ahw->ocm_win_crb);
1115 /* read back to flush */
1116 readl(adapter->ahw->ocm_win_crb);
1117 start = QLCNIC_PCI_OCM0_2M + off;
1118
1119 addr = adapter->ahw->pci_base0 + start;
1120
1121 if (op == 0) /* read */
1122 *data = readq(addr);
1123 else /* write */
1124 writeq(*data, addr);
1125
1126 /* Set window to 0 */
1127 writel(0, adapter->ahw->ocm_win_crb);
1128 readl(adapter->ahw->ocm_win_crb);
1129
1130 mutex_unlock(&adapter->ahw->mem_lock);
1131 return 0;
1132 }
1133
1134 void
1135 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1136 {
1137 void __iomem *addr = adapter->ahw->pci_base0 +
1138 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1139
1140 mutex_lock(&adapter->ahw->mem_lock);
1141 *data = readq(addr);
1142 mutex_unlock(&adapter->ahw->mem_lock);
1143 }
1144
1145 void
1146 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1147 {
1148 void __iomem *addr = adapter->ahw->pci_base0 +
1149 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1150
1151 mutex_lock(&adapter->ahw->mem_lock);
1152 writeq(data, addr);
1153 mutex_unlock(&adapter->ahw->mem_lock);
1154 }
1155
1156
1157
1158 /* Set MS memory control data for different adapters */
1159 static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1160 struct qlcnic_ms_reg_ctrl *ms)
1161 {
1162 ms->control = QLCNIC_MS_CTRL;
1163 ms->low = QLCNIC_MS_ADDR_LO;
1164 ms->hi = QLCNIC_MS_ADDR_HI;
1165 if (off & 0xf) {
1166 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1167 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1168 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1169 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1170 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1171 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1172 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1173 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1174 } else {
1175 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1176 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1177 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1178 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1179 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1180 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1181 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1182 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1183 }
1184
1185 ms->ocm_window = OCM_WIN_P3P(off);
1186 ms->off = GET_MEM_OFFS_2M(off);
1187 }
1188
1189 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1190 {
1191 int j, ret = 0;
1192 u32 temp, off8;
1193 struct qlcnic_ms_reg_ctrl ms;
1194
1195 /* Only 64-bit aligned access */
1196 if (off & 7)
1197 return -EIO;
1198
1199 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1200 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1201 QLCNIC_ADDR_QDR_NET_MAX) ||
1202 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1203 QLCNIC_ADDR_DDR_NET_MAX)))
1204 return -EIO;
1205
1206 qlcnic_set_ms_controls(adapter, off, &ms);
1207
1208 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1209 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1210 ms.off, &data, 1);
1211
1212 off8 = off & ~0xf;
1213
1214 mutex_lock(&adapter->ahw->mem_lock);
1215
1216 qlcnic_ind_wr(adapter, ms.low, off8);
1217 qlcnic_ind_wr(adapter, ms.hi, 0);
1218
1219 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1220 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1221
1222 for (j = 0; j < MAX_CTL_CHECK; j++) {
1223 temp = qlcnic_ind_rd(adapter, ms.control);
1224 if ((temp & TA_CTL_BUSY) == 0)
1225 break;
1226 }
1227
1228 if (j >= MAX_CTL_CHECK) {
1229 ret = -EIO;
1230 goto done;
1231 }
1232
1233 /* This is the modify part of read-modify-write */
1234 qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1235 qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1236 /* This is the write part of read-modify-write */
1237 qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1238 qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
1239
1240 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1241 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
1242
1243 for (j = 0; j < MAX_CTL_CHECK; j++) {
1244 temp = qlcnic_ind_rd(adapter, ms.control);
1245 if ((temp & TA_CTL_BUSY) == 0)
1246 break;
1247 }
1248
1249 if (j >= MAX_CTL_CHECK) {
1250 if (printk_ratelimit())
1251 dev_err(&adapter->pdev->dev,
1252 "failed to write through agent\n");
1253 ret = -EIO;
1254 } else
1255 ret = 0;
1256
1257 done:
1258 mutex_unlock(&adapter->ahw->mem_lock);
1259
1260 return ret;
1261 }
1262
1263 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1264 {
1265 int j, ret;
1266 u32 temp, off8;
1267 u64 val;
1268 struct qlcnic_ms_reg_ctrl ms;
1269
1270 /* Only 64-bit aligned access */
1271 if (off & 7)
1272 return -EIO;
1273 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1274 QLCNIC_ADDR_QDR_NET_MAX) ||
1275 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1276 QLCNIC_ADDR_DDR_NET_MAX)))
1277 return -EIO;
1278
1279 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1280 qlcnic_set_ms_controls(adapter, off, &ms);
1281
1282 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1283 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1284 ms.off, data, 0);
1285
1286 mutex_lock(&adapter->ahw->mem_lock);
1287
1288 off8 = off & ~0xf;
1289
1290 qlcnic_ind_wr(adapter, ms.low, off8);
1291 qlcnic_ind_wr(adapter, ms.hi, 0);
1292
1293 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1294 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1295
1296 for (j = 0; j < MAX_CTL_CHECK; j++) {
1297 temp = qlcnic_ind_rd(adapter, ms.control);
1298 if ((temp & TA_CTL_BUSY) == 0)
1299 break;
1300 }
1301
1302 if (j >= MAX_CTL_CHECK) {
1303 if (printk_ratelimit())
1304 dev_err(&adapter->pdev->dev,
1305 "failed to read through agent\n");
1306 ret = -EIO;
1307 } else {
1308
1309 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
1310 val = (u64)temp << 32;
1311 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
1312 *data = val;
1313 ret = 0;
1314 }
1315
1316 mutex_unlock(&adapter->ahw->mem_lock);
1317
1318 return ret;
1319 }
1320
1321 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
1322 {
1323 int offset, board_type, magic;
1324 struct pci_dev *pdev = adapter->pdev;
1325
1326 offset = QLCNIC_FW_MAGIC_OFFSET;
1327 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1328 return -EIO;
1329
1330 if (magic != QLCNIC_BDINFO_MAGIC) {
1331 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1332 magic);
1333 return -EIO;
1334 }
1335
1336 offset = QLCNIC_BRDTYPE_OFFSET;
1337 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1338 return -EIO;
1339
1340 adapter->ahw->board_type = board_type;
1341
1342 if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1343 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1344 if ((gpio & 0x8000) == 0)
1345 board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1346 }
1347
1348 switch (board_type) {
1349 case QLCNIC_BRDTYPE_P3P_HMEZ:
1350 case QLCNIC_BRDTYPE_P3P_XG_LOM:
1351 case QLCNIC_BRDTYPE_P3P_10G_CX4:
1352 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1353 case QLCNIC_BRDTYPE_P3P_IMEZ:
1354 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1355 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1356 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1357 case QLCNIC_BRDTYPE_P3P_10G_XFP:
1358 case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1359 adapter->ahw->port_type = QLCNIC_XGBE;
1360 break;
1361 case QLCNIC_BRDTYPE_P3P_REF_QG:
1362 case QLCNIC_BRDTYPE_P3P_4_GB:
1363 case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1364 adapter->ahw->port_type = QLCNIC_GBE;
1365 break;
1366 case QLCNIC_BRDTYPE_P3P_10G_TP:
1367 adapter->ahw->port_type = (adapter->portnum < 2) ?
1368 QLCNIC_XGBE : QLCNIC_GBE;
1369 break;
1370 default:
1371 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1372 adapter->ahw->port_type = QLCNIC_XGBE;
1373 break;
1374 }
1375
1376 return 0;
1377 }
1378
1379 int
1380 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1381 {
1382 u32 wol_cfg;
1383
1384 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1385 if (wol_cfg & (1UL << adapter->portnum)) {
1386 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1387 if (wol_cfg & (1 << adapter->portnum))
1388 return 1;
1389 }
1390
1391 return 0;
1392 }
1393
1394 int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1395 {
1396 struct qlcnic_nic_req req;
1397 int rv;
1398 u64 word;
1399
1400 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1401 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1402
1403 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1404 req.req_hdr = cpu_to_le64(word);
1405
1406 req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
1407 req.words[1] = cpu_to_le64(state);
1408
1409 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1410 if (rv)
1411 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1412
1413 return rv;
1414 }
1415
1416 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1417 {
1418 void __iomem *msix_base_addr;
1419 u32 func;
1420 u32 msix_base;
1421
1422 pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1423 msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1424 msix_base = readl(msix_base_addr);
1425 func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1426 adapter->ahw->pci_func = func;
1427 }
1428
1429 void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1430 loff_t offset, size_t size)
1431 {
1432 u32 data;
1433 u64 qmdata;
1434
1435 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1436 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1437 memcpy(buf, &qmdata, size);
1438 } else {
1439 data = QLCRD32(adapter, offset);
1440 memcpy(buf, &data, size);
1441 }
1442 }
1443
1444 void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1445 loff_t offset, size_t size)
1446 {
1447 u32 data;
1448 u64 qmdata;
1449
1450 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1451 memcpy(&qmdata, buf, size);
1452 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1453 } else {
1454 memcpy(&data, buf, size);
1455 QLCWR32(adapter, offset, data);
1456 }
1457 }
1458
1459 int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1460 {
1461 return qlcnic_pcie_sem_lock(adapter, 5, 0);
1462 }
1463
1464 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1465 {
1466 qlcnic_pcie_sem_unlock(adapter, 5);
1467 }
Linux kernel - Deliverables
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