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[deliverable/linux.git] / drivers / net / ethernet / qlogic / qlge / qlge_main.c
1 /*
2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
7 */
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/bitops.h>
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/list.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/pagemap.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/kthread.h>
23 #include <linux/interrupt.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/in.h>
27 #include <linux/ip.h>
28 #include <linux/ipv6.h>
29 #include <net/ipv6.h>
30 #include <linux/tcp.h>
31 #include <linux/udp.h>
32 #include <linux/if_arp.h>
33 #include <linux/if_ether.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/ethtool.h>
37 #include <linux/if_vlan.h>
38 #include <linux/skbuff.h>
39 #include <linux/delay.h>
40 #include <linux/mm.h>
41 #include <linux/vmalloc.h>
42 #include <linux/prefetch.h>
43 #include <net/ip6_checksum.h>
44
45 #include "qlge.h"
46
47 char qlge_driver_name[] = DRV_NAME;
48 const char qlge_driver_version[] = DRV_VERSION;
49
50 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
51 MODULE_DESCRIPTION(DRV_STRING " ");
52 MODULE_LICENSE("GPL");
53 MODULE_VERSION(DRV_VERSION);
54
55 static const u32 default_msg =
56 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
57 /* NETIF_MSG_TIMER | */
58 NETIF_MSG_IFDOWN |
59 NETIF_MSG_IFUP |
60 NETIF_MSG_RX_ERR |
61 NETIF_MSG_TX_ERR |
62 /* NETIF_MSG_TX_QUEUED | */
63 /* NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
64 /* NETIF_MSG_PKTDATA | */
65 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
66
67 static int debug = -1; /* defaults above */
68 module_param(debug, int, 0664);
69 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71 #define MSIX_IRQ 0
72 #define MSI_IRQ 1
73 #define LEG_IRQ 2
74 static int qlge_irq_type = MSIX_IRQ;
75 module_param(qlge_irq_type, int, 0664);
76 MODULE_PARM_DESC(qlge_irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
77
78 static int qlge_mpi_coredump;
79 module_param(qlge_mpi_coredump, int, 0);
80 MODULE_PARM_DESC(qlge_mpi_coredump,
81 "Option to enable MPI firmware dump. "
82 "Default is OFF - Do Not allocate memory. ");
83
84 static int qlge_force_coredump;
85 module_param(qlge_force_coredump, int, 0);
86 MODULE_PARM_DESC(qlge_force_coredump,
87 "Option to allow force of firmware core dump. "
88 "Default is OFF - Do not allow.");
89
90 static DEFINE_PCI_DEVICE_TABLE(qlge_pci_tbl) = {
91 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
92 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
93 /* required last entry */
94 {0,}
95 };
96
97 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
98
99 static int ql_wol(struct ql_adapter *);
100 static void qlge_set_multicast_list(struct net_device *);
101 static int ql_adapter_down(struct ql_adapter *);
102 static int ql_adapter_up(struct ql_adapter *);
103
104 /* This hardware semaphore causes exclusive access to
105 * resources shared between the NIC driver, MPI firmware,
106 * FCOE firmware and the FC driver.
107 */
108 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
109 {
110 u32 sem_bits = 0;
111
112 switch (sem_mask) {
113 case SEM_XGMAC0_MASK:
114 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
115 break;
116 case SEM_XGMAC1_MASK:
117 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
118 break;
119 case SEM_ICB_MASK:
120 sem_bits = SEM_SET << SEM_ICB_SHIFT;
121 break;
122 case SEM_MAC_ADDR_MASK:
123 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
124 break;
125 case SEM_FLASH_MASK:
126 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
127 break;
128 case SEM_PROBE_MASK:
129 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
130 break;
131 case SEM_RT_IDX_MASK:
132 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
133 break;
134 case SEM_PROC_REG_MASK:
135 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
136 break;
137 default:
138 netif_alert(qdev, probe, qdev->ndev, "bad Semaphore mask!.\n");
139 return -EINVAL;
140 }
141
142 ql_write32(qdev, SEM, sem_bits | sem_mask);
143 return !(ql_read32(qdev, SEM) & sem_bits);
144 }
145
146 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
147 {
148 unsigned int wait_count = 30;
149 do {
150 if (!ql_sem_trylock(qdev, sem_mask))
151 return 0;
152 udelay(100);
153 } while (--wait_count);
154 return -ETIMEDOUT;
155 }
156
157 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
158 {
159 ql_write32(qdev, SEM, sem_mask);
160 ql_read32(qdev, SEM); /* flush */
161 }
162
163 /* This function waits for a specific bit to come ready
164 * in a given register. It is used mostly by the initialize
165 * process, but is also used in kernel thread API such as
166 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
167 */
168 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
169 {
170 u32 temp;
171 int count = UDELAY_COUNT;
172
173 while (count) {
174 temp = ql_read32(qdev, reg);
175
176 /* check for errors */
177 if (temp & err_bit) {
178 netif_alert(qdev, probe, qdev->ndev,
179 "register 0x%.08x access error, value = 0x%.08x!.\n",
180 reg, temp);
181 return -EIO;
182 } else if (temp & bit)
183 return 0;
184 udelay(UDELAY_DELAY);
185 count--;
186 }
187 netif_alert(qdev, probe, qdev->ndev,
188 "Timed out waiting for reg %x to come ready.\n", reg);
189 return -ETIMEDOUT;
190 }
191
192 /* The CFG register is used to download TX and RX control blocks
193 * to the chip. This function waits for an operation to complete.
194 */
195 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
196 {
197 int count = UDELAY_COUNT;
198 u32 temp;
199
200 while (count) {
201 temp = ql_read32(qdev, CFG);
202 if (temp & CFG_LE)
203 return -EIO;
204 if (!(temp & bit))
205 return 0;
206 udelay(UDELAY_DELAY);
207 count--;
208 }
209 return -ETIMEDOUT;
210 }
211
212
213 /* Used to issue init control blocks to hw. Maps control block,
214 * sets address, triggers download, waits for completion.
215 */
216 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
217 u16 q_id)
218 {
219 u64 map;
220 int status = 0;
221 int direction;
222 u32 mask;
223 u32 value;
224
225 direction =
226 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
227 PCI_DMA_FROMDEVICE;
228
229 map = pci_map_single(qdev->pdev, ptr, size, direction);
230 if (pci_dma_mapping_error(qdev->pdev, map)) {
231 netif_err(qdev, ifup, qdev->ndev, "Couldn't map DMA area.\n");
232 return -ENOMEM;
233 }
234
235 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
236 if (status)
237 return status;
238
239 status = ql_wait_cfg(qdev, bit);
240 if (status) {
241 netif_err(qdev, ifup, qdev->ndev,
242 "Timed out waiting for CFG to come ready.\n");
243 goto exit;
244 }
245
246 ql_write32(qdev, ICB_L, (u32) map);
247 ql_write32(qdev, ICB_H, (u32) (map >> 32));
248
249 mask = CFG_Q_MASK | (bit << 16);
250 value = bit | (q_id << CFG_Q_SHIFT);
251 ql_write32(qdev, CFG, (mask | value));
252
253 /*
254 * Wait for the bit to clear after signaling hw.
255 */
256 status = ql_wait_cfg(qdev, bit);
257 exit:
258 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
259 pci_unmap_single(qdev->pdev, map, size, direction);
260 return status;
261 }
262
263 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
264 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
265 u32 *value)
266 {
267 u32 offset = 0;
268 int status;
269
270 switch (type) {
271 case MAC_ADDR_TYPE_MULTI_MAC:
272 case MAC_ADDR_TYPE_CAM_MAC:
273 {
274 status =
275 ql_wait_reg_rdy(qdev,
276 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
277 if (status)
278 goto exit;
279 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
280 (index << MAC_ADDR_IDX_SHIFT) | /* index */
281 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
282 status =
283 ql_wait_reg_rdy(qdev,
284 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
285 if (status)
286 goto exit;
287 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
288 status =
289 ql_wait_reg_rdy(qdev,
290 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
291 if (status)
292 goto exit;
293 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
294 (index << MAC_ADDR_IDX_SHIFT) | /* index */
295 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
296 status =
297 ql_wait_reg_rdy(qdev,
298 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
299 if (status)
300 goto exit;
301 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
302 if (type == MAC_ADDR_TYPE_CAM_MAC) {
303 status =
304 ql_wait_reg_rdy(qdev,
305 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
306 if (status)
307 goto exit;
308 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
309 (index << MAC_ADDR_IDX_SHIFT) | /* index */
310 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
311 status =
312 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
313 MAC_ADDR_MR, 0);
314 if (status)
315 goto exit;
316 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
317 }
318 break;
319 }
320 case MAC_ADDR_TYPE_VLAN:
321 case MAC_ADDR_TYPE_MULTI_FLTR:
322 default:
323 netif_crit(qdev, ifup, qdev->ndev,
324 "Address type %d not yet supported.\n", type);
325 status = -EPERM;
326 }
327 exit:
328 return status;
329 }
330
331 /* Set up a MAC, multicast or VLAN address for the
332 * inbound frame matching.
333 */
334 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
335 u16 index)
336 {
337 u32 offset = 0;
338 int status = 0;
339
340 switch (type) {
341 case MAC_ADDR_TYPE_MULTI_MAC:
342 {
343 u32 upper = (addr[0] << 8) | addr[1];
344 u32 lower = (addr[2] << 24) | (addr[3] << 16) |
345 (addr[4] << 8) | (addr[5]);
346
347 status =
348 ql_wait_reg_rdy(qdev,
349 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
350 if (status)
351 goto exit;
352 ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
353 (index << MAC_ADDR_IDX_SHIFT) |
354 type | MAC_ADDR_E);
355 ql_write32(qdev, MAC_ADDR_DATA, lower);
356 status =
357 ql_wait_reg_rdy(qdev,
358 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
359 if (status)
360 goto exit;
361 ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
362 (index << MAC_ADDR_IDX_SHIFT) |
363 type | MAC_ADDR_E);
364
365 ql_write32(qdev, MAC_ADDR_DATA, upper);
366 status =
367 ql_wait_reg_rdy(qdev,
368 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
369 if (status)
370 goto exit;
371 break;
372 }
373 case MAC_ADDR_TYPE_CAM_MAC:
374 {
375 u32 cam_output;
376 u32 upper = (addr[0] << 8) | addr[1];
377 u32 lower =
378 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
379 (addr[5]);
380 status =
381 ql_wait_reg_rdy(qdev,
382 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
383 if (status)
384 goto exit;
385 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
386 (index << MAC_ADDR_IDX_SHIFT) | /* index */
387 type); /* type */
388 ql_write32(qdev, MAC_ADDR_DATA, lower);
389 status =
390 ql_wait_reg_rdy(qdev,
391 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
392 if (status)
393 goto exit;
394 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
395 (index << MAC_ADDR_IDX_SHIFT) | /* index */
396 type); /* type */
397 ql_write32(qdev, MAC_ADDR_DATA, upper);
398 status =
399 ql_wait_reg_rdy(qdev,
400 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
401 if (status)
402 goto exit;
403 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
404 (index << MAC_ADDR_IDX_SHIFT) | /* index */
405 type); /* type */
406 /* This field should also include the queue id
407 and possibly the function id. Right now we hardcode
408 the route field to NIC core.
409 */
410 cam_output = (CAM_OUT_ROUTE_NIC |
411 (qdev->
412 func << CAM_OUT_FUNC_SHIFT) |
413 (0 << CAM_OUT_CQ_ID_SHIFT));
414 if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
415 cam_output |= CAM_OUT_RV;
416 /* route to NIC core */
417 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
418 break;
419 }
420 case MAC_ADDR_TYPE_VLAN:
421 {
422 u32 enable_bit = *((u32 *) &addr[0]);
423 /* For VLAN, the addr actually holds a bit that
424 * either enables or disables the vlan id we are
425 * addressing. It's either MAC_ADDR_E on or off.
426 * That's bit-27 we're talking about.
427 */
428 status =
429 ql_wait_reg_rdy(qdev,
430 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
431 if (status)
432 goto exit;
433 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
434 (index << MAC_ADDR_IDX_SHIFT) | /* index */
435 type | /* type */
436 enable_bit); /* enable/disable */
437 break;
438 }
439 case MAC_ADDR_TYPE_MULTI_FLTR:
440 default:
441 netif_crit(qdev, ifup, qdev->ndev,
442 "Address type %d not yet supported.\n", type);
443 status = -EPERM;
444 }
445 exit:
446 return status;
447 }
448
449 /* Set or clear MAC address in hardware. We sometimes
450 * have to clear it to prevent wrong frame routing
451 * especially in a bonding environment.
452 */
453 static int ql_set_mac_addr(struct ql_adapter *qdev, int set)
454 {
455 int status;
456 char zero_mac_addr[ETH_ALEN];
457 char *addr;
458
459 if (set) {
460 addr = &qdev->current_mac_addr[0];
461 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
462 "Set Mac addr %pM\n", addr);
463 } else {
464 memset(zero_mac_addr, 0, ETH_ALEN);
465 addr = &zero_mac_addr[0];
466 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
467 "Clearing MAC address\n");
468 }
469 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
470 if (status)
471 return status;
472 status = ql_set_mac_addr_reg(qdev, (u8 *) addr,
473 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
474 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
475 if (status)
476 netif_err(qdev, ifup, qdev->ndev,
477 "Failed to init mac address.\n");
478 return status;
479 }
480
481 void ql_link_on(struct ql_adapter *qdev)
482 {
483 netif_err(qdev, link, qdev->ndev, "Link is up.\n");
484 netif_carrier_on(qdev->ndev);
485 ql_set_mac_addr(qdev, 1);
486 }
487
488 void ql_link_off(struct ql_adapter *qdev)
489 {
490 netif_err(qdev, link, qdev->ndev, "Link is down.\n");
491 netif_carrier_off(qdev->ndev);
492 ql_set_mac_addr(qdev, 0);
493 }
494
495 /* Get a specific frame routing value from the CAM.
496 * Used for debug and reg dump.
497 */
498 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
499 {
500 int status = 0;
501
502 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
503 if (status)
504 goto exit;
505
506 ql_write32(qdev, RT_IDX,
507 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
508 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
509 if (status)
510 goto exit;
511 *value = ql_read32(qdev, RT_DATA);
512 exit:
513 return status;
514 }
515
516 /* The NIC function for this chip has 16 routing indexes. Each one can be used
517 * to route different frame types to various inbound queues. We send broadcast/
518 * multicast/error frames to the default queue for slow handling,
519 * and CAM hit/RSS frames to the fast handling queues.
520 */
521 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
522 int enable)
523 {
524 int status = -EINVAL; /* Return error if no mask match. */
525 u32 value = 0;
526
527 switch (mask) {
528 case RT_IDX_CAM_HIT:
529 {
530 value = RT_IDX_DST_CAM_Q | /* dest */
531 RT_IDX_TYPE_NICQ | /* type */
532 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
533 break;
534 }
535 case RT_IDX_VALID: /* Promiscuous Mode frames. */
536 {
537 value = RT_IDX_DST_DFLT_Q | /* dest */
538 RT_IDX_TYPE_NICQ | /* type */
539 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
540 break;
541 }
542 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
543 {
544 value = RT_IDX_DST_DFLT_Q | /* dest */
545 RT_IDX_TYPE_NICQ | /* type */
546 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
547 break;
548 }
549 case RT_IDX_IP_CSUM_ERR: /* Pass up IP CSUM error frames. */
550 {
551 value = RT_IDX_DST_DFLT_Q | /* dest */
552 RT_IDX_TYPE_NICQ | /* type */
553 (RT_IDX_IP_CSUM_ERR_SLOT <<
554 RT_IDX_IDX_SHIFT); /* index */
555 break;
556 }
557 case RT_IDX_TU_CSUM_ERR: /* Pass up TCP/UDP CSUM error frames. */
558 {
559 value = RT_IDX_DST_DFLT_Q | /* dest */
560 RT_IDX_TYPE_NICQ | /* type */
561 (RT_IDX_TCP_UDP_CSUM_ERR_SLOT <<
562 RT_IDX_IDX_SHIFT); /* index */
563 break;
564 }
565 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
566 {
567 value = RT_IDX_DST_DFLT_Q | /* dest */
568 RT_IDX_TYPE_NICQ | /* type */
569 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
570 break;
571 }
572 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
573 {
574 value = RT_IDX_DST_DFLT_Q | /* dest */
575 RT_IDX_TYPE_NICQ | /* type */
576 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
577 break;
578 }
579 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
580 {
581 value = RT_IDX_DST_DFLT_Q | /* dest */
582 RT_IDX_TYPE_NICQ | /* type */
583 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
584 break;
585 }
586 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
587 {
588 value = RT_IDX_DST_RSS | /* dest */
589 RT_IDX_TYPE_NICQ | /* type */
590 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
591 break;
592 }
593 case 0: /* Clear the E-bit on an entry. */
594 {
595 value = RT_IDX_DST_DFLT_Q | /* dest */
596 RT_IDX_TYPE_NICQ | /* type */
597 (index << RT_IDX_IDX_SHIFT);/* index */
598 break;
599 }
600 default:
601 netif_err(qdev, ifup, qdev->ndev,
602 "Mask type %d not yet supported.\n", mask);
603 status = -EPERM;
604 goto exit;
605 }
606
607 if (value) {
608 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
609 if (status)
610 goto exit;
611 value |= (enable ? RT_IDX_E : 0);
612 ql_write32(qdev, RT_IDX, value);
613 ql_write32(qdev, RT_DATA, enable ? mask : 0);
614 }
615 exit:
616 return status;
617 }
618
619 static void ql_enable_interrupts(struct ql_adapter *qdev)
620 {
621 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
622 }
623
624 static void ql_disable_interrupts(struct ql_adapter *qdev)
625 {
626 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
627 }
628
629 /* If we're running with multiple MSI-X vectors then we enable on the fly.
630 * Otherwise, we may have multiple outstanding workers and don't want to
631 * enable until the last one finishes. In this case, the irq_cnt gets
632 * incremented every time we queue a worker and decremented every time
633 * a worker finishes. Once it hits zero we enable the interrupt.
634 */
635 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
636 {
637 u32 var = 0;
638 unsigned long hw_flags = 0;
639 struct intr_context *ctx = qdev->intr_context + intr;
640
641 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
642 /* Always enable if we're MSIX multi interrupts and
643 * it's not the default (zeroeth) interrupt.
644 */
645 ql_write32(qdev, INTR_EN,
646 ctx->intr_en_mask);
647 var = ql_read32(qdev, STS);
648 return var;
649 }
650
651 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
652 if (atomic_dec_and_test(&ctx->irq_cnt)) {
653 ql_write32(qdev, INTR_EN,
654 ctx->intr_en_mask);
655 var = ql_read32(qdev, STS);
656 }
657 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
658 return var;
659 }
660
661 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
662 {
663 u32 var = 0;
664 struct intr_context *ctx;
665
666 /* HW disables for us if we're MSIX multi interrupts and
667 * it's not the default (zeroeth) interrupt.
668 */
669 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
670 return 0;
671
672 ctx = qdev->intr_context + intr;
673 spin_lock(&qdev->hw_lock);
674 if (!atomic_read(&ctx->irq_cnt)) {
675 ql_write32(qdev, INTR_EN,
676 ctx->intr_dis_mask);
677 var = ql_read32(qdev, STS);
678 }
679 atomic_inc(&ctx->irq_cnt);
680 spin_unlock(&qdev->hw_lock);
681 return var;
682 }
683
684 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
685 {
686 int i;
687 for (i = 0; i < qdev->intr_count; i++) {
688 /* The enable call does a atomic_dec_and_test
689 * and enables only if the result is zero.
690 * So we precharge it here.
691 */
692 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
693 i == 0))
694 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
695 ql_enable_completion_interrupt(qdev, i);
696 }
697
698 }
699
700 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
701 {
702 int status, i;
703 u16 csum = 0;
704 __le16 *flash = (__le16 *)&qdev->flash;
705
706 status = strncmp((char *)&qdev->flash, str, 4);
707 if (status) {
708 netif_err(qdev, ifup, qdev->ndev, "Invalid flash signature.\n");
709 return status;
710 }
711
712 for (i = 0; i < size; i++)
713 csum += le16_to_cpu(*flash++);
714
715 if (csum)
716 netif_err(qdev, ifup, qdev->ndev,
717 "Invalid flash checksum, csum = 0x%.04x.\n", csum);
718
719 return csum;
720 }
721
722 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
723 {
724 int status = 0;
725 /* wait for reg to come ready */
726 status = ql_wait_reg_rdy(qdev,
727 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
728 if (status)
729 goto exit;
730 /* set up for reg read */
731 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
732 /* wait for reg to come ready */
733 status = ql_wait_reg_rdy(qdev,
734 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
735 if (status)
736 goto exit;
737 /* This data is stored on flash as an array of
738 * __le32. Since ql_read32() returns cpu endian
739 * we need to swap it back.
740 */
741 *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
742 exit:
743 return status;
744 }
745
746 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
747 {
748 u32 i, size;
749 int status;
750 __le32 *p = (__le32 *)&qdev->flash;
751 u32 offset;
752 u8 mac_addr[6];
753
754 /* Get flash offset for function and adjust
755 * for dword access.
756 */
757 if (!qdev->port)
758 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
759 else
760 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
761
762 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
763 return -ETIMEDOUT;
764
765 size = sizeof(struct flash_params_8000) / sizeof(u32);
766 for (i = 0; i < size; i++, p++) {
767 status = ql_read_flash_word(qdev, i+offset, p);
768 if (status) {
769 netif_err(qdev, ifup, qdev->ndev,
770 "Error reading flash.\n");
771 goto exit;
772 }
773 }
774
775 status = ql_validate_flash(qdev,
776 sizeof(struct flash_params_8000) / sizeof(u16),
777 "8000");
778 if (status) {
779 netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n");
780 status = -EINVAL;
781 goto exit;
782 }
783
784 /* Extract either manufacturer or BOFM modified
785 * MAC address.
786 */
787 if (qdev->flash.flash_params_8000.data_type1 == 2)
788 memcpy(mac_addr,
789 qdev->flash.flash_params_8000.mac_addr1,
790 qdev->ndev->addr_len);
791 else
792 memcpy(mac_addr,
793 qdev->flash.flash_params_8000.mac_addr,
794 qdev->ndev->addr_len);
795
796 if (!is_valid_ether_addr(mac_addr)) {
797 netif_err(qdev, ifup, qdev->ndev, "Invalid MAC address.\n");
798 status = -EINVAL;
799 goto exit;
800 }
801
802 memcpy(qdev->ndev->dev_addr,
803 mac_addr,
804 qdev->ndev->addr_len);
805
806 exit:
807 ql_sem_unlock(qdev, SEM_FLASH_MASK);
808 return status;
809 }
810
811 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
812 {
813 int i;
814 int status;
815 __le32 *p = (__le32 *)&qdev->flash;
816 u32 offset = 0;
817 u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
818
819 /* Second function's parameters follow the first
820 * function's.
821 */
822 if (qdev->port)
823 offset = size;
824
825 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
826 return -ETIMEDOUT;
827
828 for (i = 0; i < size; i++, p++) {
829 status = ql_read_flash_word(qdev, i+offset, p);
830 if (status) {
831 netif_err(qdev, ifup, qdev->ndev,
832 "Error reading flash.\n");
833 goto exit;
834 }
835
836 }
837
838 status = ql_validate_flash(qdev,
839 sizeof(struct flash_params_8012) / sizeof(u16),
840 "8012");
841 if (status) {
842 netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n");
843 status = -EINVAL;
844 goto exit;
845 }
846
847 if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
848 status = -EINVAL;
849 goto exit;
850 }
851
852 memcpy(qdev->ndev->dev_addr,
853 qdev->flash.flash_params_8012.mac_addr,
854 qdev->ndev->addr_len);
855
856 exit:
857 ql_sem_unlock(qdev, SEM_FLASH_MASK);
858 return status;
859 }
860
861 /* xgmac register are located behind the xgmac_addr and xgmac_data
862 * register pair. Each read/write requires us to wait for the ready
863 * bit before reading/writing the data.
864 */
865 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
866 {
867 int status;
868 /* wait for reg to come ready */
869 status = ql_wait_reg_rdy(qdev,
870 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
871 if (status)
872 return status;
873 /* write the data to the data reg */
874 ql_write32(qdev, XGMAC_DATA, data);
875 /* trigger the write */
876 ql_write32(qdev, XGMAC_ADDR, reg);
877 return status;
878 }
879
880 /* xgmac register are located behind the xgmac_addr and xgmac_data
881 * register pair. Each read/write requires us to wait for the ready
882 * bit before reading/writing the data.
883 */
884 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
885 {
886 int status = 0;
887 /* wait for reg to come ready */
888 status = ql_wait_reg_rdy(qdev,
889 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
890 if (status)
891 goto exit;
892 /* set up for reg read */
893 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
894 /* wait for reg to come ready */
895 status = ql_wait_reg_rdy(qdev,
896 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
897 if (status)
898 goto exit;
899 /* get the data */
900 *data = ql_read32(qdev, XGMAC_DATA);
901 exit:
902 return status;
903 }
904
905 /* This is used for reading the 64-bit statistics regs. */
906 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
907 {
908 int status = 0;
909 u32 hi = 0;
910 u32 lo = 0;
911
912 status = ql_read_xgmac_reg(qdev, reg, &lo);
913 if (status)
914 goto exit;
915
916 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
917 if (status)
918 goto exit;
919
920 *data = (u64) lo | ((u64) hi << 32);
921
922 exit:
923 return status;
924 }
925
926 static int ql_8000_port_initialize(struct ql_adapter *qdev)
927 {
928 int status;
929 /*
930 * Get MPI firmware version for driver banner
931 * and ethool info.
932 */
933 status = ql_mb_about_fw(qdev);
934 if (status)
935 goto exit;
936 status = ql_mb_get_fw_state(qdev);
937 if (status)
938 goto exit;
939 /* Wake up a worker to get/set the TX/RX frame sizes. */
940 queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
941 exit:
942 return status;
943 }
944
945 /* Take the MAC Core out of reset.
946 * Enable statistics counting.
947 * Take the transmitter/receiver out of reset.
948 * This functionality may be done in the MPI firmware at a
949 * later date.
950 */
951 static int ql_8012_port_initialize(struct ql_adapter *qdev)
952 {
953 int status = 0;
954 u32 data;
955
956 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
957 /* Another function has the semaphore, so
958 * wait for the port init bit to come ready.
959 */
960 netif_info(qdev, link, qdev->ndev,
961 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
962 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
963 if (status) {
964 netif_crit(qdev, link, qdev->ndev,
965 "Port initialize timed out.\n");
966 }
967 return status;
968 }
969
970 netif_info(qdev, link, qdev->ndev, "Got xgmac semaphore!.\n");
971 /* Set the core reset. */
972 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
973 if (status)
974 goto end;
975 data |= GLOBAL_CFG_RESET;
976 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
977 if (status)
978 goto end;
979
980 /* Clear the core reset and turn on jumbo for receiver. */
981 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
982 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
983 data |= GLOBAL_CFG_TX_STAT_EN;
984 data |= GLOBAL_CFG_RX_STAT_EN;
985 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
986 if (status)
987 goto end;
988
989 /* Enable transmitter, and clear it's reset. */
990 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
991 if (status)
992 goto end;
993 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
994 data |= TX_CFG_EN; /* Enable the transmitter. */
995 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
996 if (status)
997 goto end;
998
999 /* Enable receiver and clear it's reset. */
1000 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
1001 if (status)
1002 goto end;
1003 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
1004 data |= RX_CFG_EN; /* Enable the receiver. */
1005 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
1006 if (status)
1007 goto end;
1008
1009 /* Turn on jumbo. */
1010 status =
1011 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
1012 if (status)
1013 goto end;
1014 status =
1015 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
1016 if (status)
1017 goto end;
1018
1019 /* Signal to the world that the port is enabled. */
1020 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
1021 end:
1022 ql_sem_unlock(qdev, qdev->xg_sem_mask);
1023 return status;
1024 }
1025
1026 static inline unsigned int ql_lbq_block_size(struct ql_adapter *qdev)
1027 {
1028 return PAGE_SIZE << qdev->lbq_buf_order;
1029 }
1030
1031 /* Get the next large buffer. */
1032 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
1033 {
1034 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
1035 rx_ring->lbq_curr_idx++;
1036 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
1037 rx_ring->lbq_curr_idx = 0;
1038 rx_ring->lbq_free_cnt++;
1039 return lbq_desc;
1040 }
1041
1042 static struct bq_desc *ql_get_curr_lchunk(struct ql_adapter *qdev,
1043 struct rx_ring *rx_ring)
1044 {
1045 struct bq_desc *lbq_desc = ql_get_curr_lbuf(rx_ring);
1046
1047 pci_dma_sync_single_for_cpu(qdev->pdev,
1048 dma_unmap_addr(lbq_desc, mapaddr),
1049 rx_ring->lbq_buf_size,
1050 PCI_DMA_FROMDEVICE);
1051
1052 /* If it's the last chunk of our master page then
1053 * we unmap it.
1054 */
1055 if ((lbq_desc->p.pg_chunk.offset + rx_ring->lbq_buf_size)
1056 == ql_lbq_block_size(qdev))
1057 pci_unmap_page(qdev->pdev,
1058 lbq_desc->p.pg_chunk.map,
1059 ql_lbq_block_size(qdev),
1060 PCI_DMA_FROMDEVICE);
1061 return lbq_desc;
1062 }
1063
1064 /* Get the next small buffer. */
1065 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
1066 {
1067 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
1068 rx_ring->sbq_curr_idx++;
1069 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
1070 rx_ring->sbq_curr_idx = 0;
1071 rx_ring->sbq_free_cnt++;
1072 return sbq_desc;
1073 }
1074
1075 /* Update an rx ring index. */
1076 static void ql_update_cq(struct rx_ring *rx_ring)
1077 {
1078 rx_ring->cnsmr_idx++;
1079 rx_ring->curr_entry++;
1080 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
1081 rx_ring->cnsmr_idx = 0;
1082 rx_ring->curr_entry = rx_ring->cq_base;
1083 }
1084 }
1085
1086 static void ql_write_cq_idx(struct rx_ring *rx_ring)
1087 {
1088 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
1089 }
1090
1091 static int ql_get_next_chunk(struct ql_adapter *qdev, struct rx_ring *rx_ring,
1092 struct bq_desc *lbq_desc)
1093 {
1094 if (!rx_ring->pg_chunk.page) {
1095 u64 map;
1096 rx_ring->pg_chunk.page = alloc_pages(__GFP_COLD | __GFP_COMP |
1097 GFP_ATOMIC,
1098 qdev->lbq_buf_order);
1099 if (unlikely(!rx_ring->pg_chunk.page)) {
1100 netif_err(qdev, drv, qdev->ndev,
1101 "page allocation failed.\n");
1102 return -ENOMEM;
1103 }
1104 rx_ring->pg_chunk.offset = 0;
1105 map = pci_map_page(qdev->pdev, rx_ring->pg_chunk.page,
1106 0, ql_lbq_block_size(qdev),
1107 PCI_DMA_FROMDEVICE);
1108 if (pci_dma_mapping_error(qdev->pdev, map)) {
1109 __free_pages(rx_ring->pg_chunk.page,
1110 qdev->lbq_buf_order);
1111 rx_ring->pg_chunk.page = NULL;
1112 netif_err(qdev, drv, qdev->ndev,
1113 "PCI mapping failed.\n");
1114 return -ENOMEM;
1115 }
1116 rx_ring->pg_chunk.map = map;
1117 rx_ring->pg_chunk.va = page_address(rx_ring->pg_chunk.page);
1118 }
1119
1120 /* Copy the current master pg_chunk info
1121 * to the current descriptor.
1122 */
1123 lbq_desc->p.pg_chunk = rx_ring->pg_chunk;
1124
1125 /* Adjust the master page chunk for next
1126 * buffer get.
1127 */
1128 rx_ring->pg_chunk.offset += rx_ring->lbq_buf_size;
1129 if (rx_ring->pg_chunk.offset == ql_lbq_block_size(qdev)) {
1130 rx_ring->pg_chunk.page = NULL;
1131 lbq_desc->p.pg_chunk.last_flag = 1;
1132 } else {
1133 rx_ring->pg_chunk.va += rx_ring->lbq_buf_size;
1134 get_page(rx_ring->pg_chunk.page);
1135 lbq_desc->p.pg_chunk.last_flag = 0;
1136 }
1137 return 0;
1138 }
1139 /* Process (refill) a large buffer queue. */
1140 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1141 {
1142 u32 clean_idx = rx_ring->lbq_clean_idx;
1143 u32 start_idx = clean_idx;
1144 struct bq_desc *lbq_desc;
1145 u64 map;
1146 int i;
1147
1148 while (rx_ring->lbq_free_cnt > 32) {
1149 for (i = (rx_ring->lbq_clean_idx % 16); i < 16; i++) {
1150 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1151 "lbq: try cleaning clean_idx = %d.\n",
1152 clean_idx);
1153 lbq_desc = &rx_ring->lbq[clean_idx];
1154 if (ql_get_next_chunk(qdev, rx_ring, lbq_desc)) {
1155 rx_ring->lbq_clean_idx = clean_idx;
1156 netif_err(qdev, ifup, qdev->ndev,
1157 "Could not get a page chunk, i=%d, clean_idx =%d .\n",
1158 i, clean_idx);
1159 return;
1160 }
1161
1162 map = lbq_desc->p.pg_chunk.map +
1163 lbq_desc->p.pg_chunk.offset;
1164 dma_unmap_addr_set(lbq_desc, mapaddr, map);
1165 dma_unmap_len_set(lbq_desc, maplen,
1166 rx_ring->lbq_buf_size);
1167 *lbq_desc->addr = cpu_to_le64(map);
1168
1169 pci_dma_sync_single_for_device(qdev->pdev, map,
1170 rx_ring->lbq_buf_size,
1171 PCI_DMA_FROMDEVICE);
1172 clean_idx++;
1173 if (clean_idx == rx_ring->lbq_len)
1174 clean_idx = 0;
1175 }
1176
1177 rx_ring->lbq_clean_idx = clean_idx;
1178 rx_ring->lbq_prod_idx += 16;
1179 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1180 rx_ring->lbq_prod_idx = 0;
1181 rx_ring->lbq_free_cnt -= 16;
1182 }
1183
1184 if (start_idx != clean_idx) {
1185 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1186 "lbq: updating prod idx = %d.\n",
1187 rx_ring->lbq_prod_idx);
1188 ql_write_db_reg(rx_ring->lbq_prod_idx,
1189 rx_ring->lbq_prod_idx_db_reg);
1190 }
1191 }
1192
1193 /* Process (refill) a small buffer queue. */
1194 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1195 {
1196 u32 clean_idx = rx_ring->sbq_clean_idx;
1197 u32 start_idx = clean_idx;
1198 struct bq_desc *sbq_desc;
1199 u64 map;
1200 int i;
1201
1202 while (rx_ring->sbq_free_cnt > 16) {
1203 for (i = (rx_ring->sbq_clean_idx % 16); i < 16; i++) {
1204 sbq_desc = &rx_ring->sbq[clean_idx];
1205 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1206 "sbq: try cleaning clean_idx = %d.\n",
1207 clean_idx);
1208 if (sbq_desc->p.skb == NULL) {
1209 netif_printk(qdev, rx_status, KERN_DEBUG,
1210 qdev->ndev,
1211 "sbq: getting new skb for index %d.\n",
1212 sbq_desc->index);
1213 sbq_desc->p.skb =
1214 netdev_alloc_skb(qdev->ndev,
1215 SMALL_BUFFER_SIZE);
1216 if (sbq_desc->p.skb == NULL) {
1217 rx_ring->sbq_clean_idx = clean_idx;
1218 return;
1219 }
1220 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1221 map = pci_map_single(qdev->pdev,
1222 sbq_desc->p.skb->data,
1223 rx_ring->sbq_buf_size,
1224 PCI_DMA_FROMDEVICE);
1225 if (pci_dma_mapping_error(qdev->pdev, map)) {
1226 netif_err(qdev, ifup, qdev->ndev,
1227 "PCI mapping failed.\n");
1228 rx_ring->sbq_clean_idx = clean_idx;
1229 dev_kfree_skb_any(sbq_desc->p.skb);
1230 sbq_desc->p.skb = NULL;
1231 return;
1232 }
1233 dma_unmap_addr_set(sbq_desc, mapaddr, map);
1234 dma_unmap_len_set(sbq_desc, maplen,
1235 rx_ring->sbq_buf_size);
1236 *sbq_desc->addr = cpu_to_le64(map);
1237 }
1238
1239 clean_idx++;
1240 if (clean_idx == rx_ring->sbq_len)
1241 clean_idx = 0;
1242 }
1243 rx_ring->sbq_clean_idx = clean_idx;
1244 rx_ring->sbq_prod_idx += 16;
1245 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1246 rx_ring->sbq_prod_idx = 0;
1247 rx_ring->sbq_free_cnt -= 16;
1248 }
1249
1250 if (start_idx != clean_idx) {
1251 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1252 "sbq: updating prod idx = %d.\n",
1253 rx_ring->sbq_prod_idx);
1254 ql_write_db_reg(rx_ring->sbq_prod_idx,
1255 rx_ring->sbq_prod_idx_db_reg);
1256 }
1257 }
1258
1259 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1260 struct rx_ring *rx_ring)
1261 {
1262 ql_update_sbq(qdev, rx_ring);
1263 ql_update_lbq(qdev, rx_ring);
1264 }
1265
1266 /* Unmaps tx buffers. Can be called from send() if a pci mapping
1267 * fails at some stage, or from the interrupt when a tx completes.
1268 */
1269 static void ql_unmap_send(struct ql_adapter *qdev,
1270 struct tx_ring_desc *tx_ring_desc, int mapped)
1271 {
1272 int i;
1273 for (i = 0; i < mapped; i++) {
1274 if (i == 0 || (i == 7 && mapped > 7)) {
1275 /*
1276 * Unmap the skb->data area, or the
1277 * external sglist (AKA the Outbound
1278 * Address List (OAL)).
1279 * If its the zeroeth element, then it's
1280 * the skb->data area. If it's the 7th
1281 * element and there is more than 6 frags,
1282 * then its an OAL.
1283 */
1284 if (i == 7) {
1285 netif_printk(qdev, tx_done, KERN_DEBUG,
1286 qdev->ndev,
1287 "unmapping OAL area.\n");
1288 }
1289 pci_unmap_single(qdev->pdev,
1290 dma_unmap_addr(&tx_ring_desc->map[i],
1291 mapaddr),
1292 dma_unmap_len(&tx_ring_desc->map[i],
1293 maplen),
1294 PCI_DMA_TODEVICE);
1295 } else {
1296 netif_printk(qdev, tx_done, KERN_DEBUG, qdev->ndev,
1297 "unmapping frag %d.\n", i);
1298 pci_unmap_page(qdev->pdev,
1299 dma_unmap_addr(&tx_ring_desc->map[i],
1300 mapaddr),
1301 dma_unmap_len(&tx_ring_desc->map[i],
1302 maplen), PCI_DMA_TODEVICE);
1303 }
1304 }
1305
1306 }
1307
1308 /* Map the buffers for this transmit. This will return
1309 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1310 */
1311 static int ql_map_send(struct ql_adapter *qdev,
1312 struct ob_mac_iocb_req *mac_iocb_ptr,
1313 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1314 {
1315 int len = skb_headlen(skb);
1316 dma_addr_t map;
1317 int frag_idx, err, map_idx = 0;
1318 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1319 int frag_cnt = skb_shinfo(skb)->nr_frags;
1320
1321 if (frag_cnt) {
1322 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
1323 "frag_cnt = %d.\n", frag_cnt);
1324 }
1325 /*
1326 * Map the skb buffer first.
1327 */
1328 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1329
1330 err = pci_dma_mapping_error(qdev->pdev, map);
1331 if (err) {
1332 netif_err(qdev, tx_queued, qdev->ndev,
1333 "PCI mapping failed with error: %d\n", err);
1334
1335 return NETDEV_TX_BUSY;
1336 }
1337
1338 tbd->len = cpu_to_le32(len);
1339 tbd->addr = cpu_to_le64(map);
1340 dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1341 dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1342 map_idx++;
1343
1344 /*
1345 * This loop fills the remainder of the 8 address descriptors
1346 * in the IOCB. If there are more than 7 fragments, then the
1347 * eighth address desc will point to an external list (OAL).
1348 * When this happens, the remainder of the frags will be stored
1349 * in this list.
1350 */
1351 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1352 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1353 tbd++;
1354 if (frag_idx == 6 && frag_cnt > 7) {
1355 /* Let's tack on an sglist.
1356 * Our control block will now
1357 * look like this:
1358 * iocb->seg[0] = skb->data
1359 * iocb->seg[1] = frag[0]
1360 * iocb->seg[2] = frag[1]
1361 * iocb->seg[3] = frag[2]
1362 * iocb->seg[4] = frag[3]
1363 * iocb->seg[5] = frag[4]
1364 * iocb->seg[6] = frag[5]
1365 * iocb->seg[7] = ptr to OAL (external sglist)
1366 * oal->seg[0] = frag[6]
1367 * oal->seg[1] = frag[7]
1368 * oal->seg[2] = frag[8]
1369 * oal->seg[3] = frag[9]
1370 * oal->seg[4] = frag[10]
1371 * etc...
1372 */
1373 /* Tack on the OAL in the eighth segment of IOCB. */
1374 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1375 sizeof(struct oal),
1376 PCI_DMA_TODEVICE);
1377 err = pci_dma_mapping_error(qdev->pdev, map);
1378 if (err) {
1379 netif_err(qdev, tx_queued, qdev->ndev,
1380 "PCI mapping outbound address list with error: %d\n",
1381 err);
1382 goto map_error;
1383 }
1384
1385 tbd->addr = cpu_to_le64(map);
1386 /*
1387 * The length is the number of fragments
1388 * that remain to be mapped times the length
1389 * of our sglist (OAL).
1390 */
1391 tbd->len =
1392 cpu_to_le32((sizeof(struct tx_buf_desc) *
1393 (frag_cnt - frag_idx)) | TX_DESC_C);
1394 dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1395 map);
1396 dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1397 sizeof(struct oal));
1398 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1399 map_idx++;
1400 }
1401
1402 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
1403 DMA_TO_DEVICE);
1404
1405 err = dma_mapping_error(&qdev->pdev->dev, map);
1406 if (err) {
1407 netif_err(qdev, tx_queued, qdev->ndev,
1408 "PCI mapping frags failed with error: %d.\n",
1409 err);
1410 goto map_error;
1411 }
1412
1413 tbd->addr = cpu_to_le64(map);
1414 tbd->len = cpu_to_le32(skb_frag_size(frag));
1415 dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1416 dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1417 skb_frag_size(frag));
1418
1419 }
1420 /* Save the number of segments we've mapped. */
1421 tx_ring_desc->map_cnt = map_idx;
1422 /* Terminate the last segment. */
1423 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1424 return NETDEV_TX_OK;
1425
1426 map_error:
1427 /*
1428 * If the first frag mapping failed, then i will be zero.
1429 * This causes the unmap of the skb->data area. Otherwise
1430 * we pass in the number of frags that mapped successfully
1431 * so they can be umapped.
1432 */
1433 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1434 return NETDEV_TX_BUSY;
1435 }
1436
1437 /* Categorizing receive firmware frame errors */
1438 static void ql_categorize_rx_err(struct ql_adapter *qdev, u8 rx_err,
1439 struct rx_ring *rx_ring)
1440 {
1441 struct nic_stats *stats = &qdev->nic_stats;
1442
1443 stats->rx_err_count++;
1444 rx_ring->rx_errors++;
1445
1446 switch (rx_err & IB_MAC_IOCB_RSP_ERR_MASK) {
1447 case IB_MAC_IOCB_RSP_ERR_CODE_ERR:
1448 stats->rx_code_err++;
1449 break;
1450 case IB_MAC_IOCB_RSP_ERR_OVERSIZE:
1451 stats->rx_oversize_err++;
1452 break;
1453 case IB_MAC_IOCB_RSP_ERR_UNDERSIZE:
1454 stats->rx_undersize_err++;
1455 break;
1456 case IB_MAC_IOCB_RSP_ERR_PREAMBLE:
1457 stats->rx_preamble_err++;
1458 break;
1459 case IB_MAC_IOCB_RSP_ERR_FRAME_LEN:
1460 stats->rx_frame_len_err++;
1461 break;
1462 case IB_MAC_IOCB_RSP_ERR_CRC:
1463 stats->rx_crc_err++;
1464 default:
1465 break;
1466 }
1467 }
1468
1469 /**
1470 * ql_update_mac_hdr_len - helper routine to update the mac header length
1471 * based on vlan tags if present
1472 */
1473 static void ql_update_mac_hdr_len(struct ql_adapter *qdev,
1474 struct ib_mac_iocb_rsp *ib_mac_rsp,
1475 void *page, size_t *len)
1476 {
1477 u16 *tags;
1478
1479 if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
1480 return;
1481 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) {
1482 tags = (u16 *)page;
1483 /* Look for stacked vlan tags in ethertype field */
1484 if (tags[6] == ETH_P_8021Q &&
1485 tags[8] == ETH_P_8021Q)
1486 *len += 2 * VLAN_HLEN;
1487 else
1488 *len += VLAN_HLEN;
1489 }
1490 }
1491
1492 /* Process an inbound completion from an rx ring. */
1493 static void ql_process_mac_rx_gro_page(struct ql_adapter *qdev,
1494 struct rx_ring *rx_ring,
1495 struct ib_mac_iocb_rsp *ib_mac_rsp,
1496 u32 length,
1497 u16 vlan_id)
1498 {
1499 struct sk_buff *skb;
1500 struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1501 struct napi_struct *napi = &rx_ring->napi;
1502
1503 /* Frame error, so drop the packet. */
1504 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1505 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1506 put_page(lbq_desc->p.pg_chunk.page);
1507 return;
1508 }
1509 napi->dev = qdev->ndev;
1510
1511 skb = napi_get_frags(napi);
1512 if (!skb) {
1513 netif_err(qdev, drv, qdev->ndev,
1514 "Couldn't get an skb, exiting.\n");
1515 rx_ring->rx_dropped++;
1516 put_page(lbq_desc->p.pg_chunk.page);
1517 return;
1518 }
1519 prefetch(lbq_desc->p.pg_chunk.va);
1520 __skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1521 lbq_desc->p.pg_chunk.page,
1522 lbq_desc->p.pg_chunk.offset,
1523 length);
1524
1525 skb->len += length;
1526 skb->data_len += length;
1527 skb->truesize += length;
1528 skb_shinfo(skb)->nr_frags++;
1529
1530 rx_ring->rx_packets++;
1531 rx_ring->rx_bytes += length;
1532 skb->ip_summed = CHECKSUM_UNNECESSARY;
1533 skb_record_rx_queue(skb, rx_ring->cq_id);
1534 if (vlan_id != 0xffff)
1535 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1536 napi_gro_frags(napi);
1537 }
1538
1539 /* Process an inbound completion from an rx ring. */
1540 static void ql_process_mac_rx_page(struct ql_adapter *qdev,
1541 struct rx_ring *rx_ring,
1542 struct ib_mac_iocb_rsp *ib_mac_rsp,
1543 u32 length,
1544 u16 vlan_id)
1545 {
1546 struct net_device *ndev = qdev->ndev;
1547 struct sk_buff *skb = NULL;
1548 void *addr;
1549 struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1550 struct napi_struct *napi = &rx_ring->napi;
1551 size_t hlen = ETH_HLEN;
1552
1553 skb = netdev_alloc_skb(ndev, length);
1554 if (!skb) {
1555 rx_ring->rx_dropped++;
1556 put_page(lbq_desc->p.pg_chunk.page);
1557 return;
1558 }
1559
1560 addr = lbq_desc->p.pg_chunk.va;
1561 prefetch(addr);
1562
1563 /* Frame error, so drop the packet. */
1564 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1565 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1566 goto err_out;
1567 }
1568
1569 /* Update the MAC header length*/
1570 ql_update_mac_hdr_len(qdev, ib_mac_rsp, addr, &hlen);
1571
1572 /* The max framesize filter on this chip is set higher than
1573 * MTU since FCoE uses 2k frames.
1574 */
1575 if (skb->len > ndev->mtu + hlen) {
1576 netif_err(qdev, drv, qdev->ndev,
1577 "Segment too small, dropping.\n");
1578 rx_ring->rx_dropped++;
1579 goto err_out;
1580 }
1581 memcpy(skb_put(skb, hlen), addr, hlen);
1582 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1583 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n",
1584 length);
1585 skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
1586 lbq_desc->p.pg_chunk.offset + hlen,
1587 length - hlen);
1588 skb->len += length - hlen;
1589 skb->data_len += length - hlen;
1590 skb->truesize += length - hlen;
1591
1592 rx_ring->rx_packets++;
1593 rx_ring->rx_bytes += skb->len;
1594 skb->protocol = eth_type_trans(skb, ndev);
1595 skb_checksum_none_assert(skb);
1596
1597 if ((ndev->features & NETIF_F_RXCSUM) &&
1598 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1599 /* TCP frame. */
1600 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1601 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1602 "TCP checksum done!\n");
1603 skb->ip_summed = CHECKSUM_UNNECESSARY;
1604 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1605 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1606 /* Unfragmented ipv4 UDP frame. */
1607 struct iphdr *iph =
1608 (struct iphdr *)((u8 *)addr + hlen);
1609 if (!(iph->frag_off &
1610 htons(IP_MF|IP_OFFSET))) {
1611 skb->ip_summed = CHECKSUM_UNNECESSARY;
1612 netif_printk(qdev, rx_status, KERN_DEBUG,
1613 qdev->ndev,
1614 "UDP checksum done!\n");
1615 }
1616 }
1617 }
1618
1619 skb_record_rx_queue(skb, rx_ring->cq_id);
1620 if (vlan_id != 0xffff)
1621 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1622 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
1623 napi_gro_receive(napi, skb);
1624 else
1625 netif_receive_skb(skb);
1626 return;
1627 err_out:
1628 dev_kfree_skb_any(skb);
1629 put_page(lbq_desc->p.pg_chunk.page);
1630 }
1631
1632 /* Process an inbound completion from an rx ring. */
1633 static void ql_process_mac_rx_skb(struct ql_adapter *qdev,
1634 struct rx_ring *rx_ring,
1635 struct ib_mac_iocb_rsp *ib_mac_rsp,
1636 u32 length,
1637 u16 vlan_id)
1638 {
1639 struct net_device *ndev = qdev->ndev;
1640 struct sk_buff *skb = NULL;
1641 struct sk_buff *new_skb = NULL;
1642 struct bq_desc *sbq_desc = ql_get_curr_sbuf(rx_ring);
1643
1644 skb = sbq_desc->p.skb;
1645 /* Allocate new_skb and copy */
1646 new_skb = netdev_alloc_skb(qdev->ndev, length + NET_IP_ALIGN);
1647 if (new_skb == NULL) {
1648 rx_ring->rx_dropped++;
1649 return;
1650 }
1651 skb_reserve(new_skb, NET_IP_ALIGN);
1652 memcpy(skb_put(new_skb, length), skb->data, length);
1653 skb = new_skb;
1654
1655 /* Frame error, so drop the packet. */
1656 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1657 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1658 dev_kfree_skb_any(skb);
1659 return;
1660 }
1661
1662 /* loopback self test for ethtool */
1663 if (test_bit(QL_SELFTEST, &qdev->flags)) {
1664 ql_check_lb_frame(qdev, skb);
1665 dev_kfree_skb_any(skb);
1666 return;
1667 }
1668
1669 /* The max framesize filter on this chip is set higher than
1670 * MTU since FCoE uses 2k frames.
1671 */
1672 if (skb->len > ndev->mtu + ETH_HLEN) {
1673 dev_kfree_skb_any(skb);
1674 rx_ring->rx_dropped++;
1675 return;
1676 }
1677
1678 prefetch(skb->data);
1679 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1680 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1681 "%s Multicast.\n",
1682 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1683 IB_MAC_IOCB_RSP_M_HASH ? "Hash" :
1684 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1685 IB_MAC_IOCB_RSP_M_REG ? "Registered" :
1686 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1687 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1688 }
1689 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P)
1690 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1691 "Promiscuous Packet.\n");
1692
1693 rx_ring->rx_packets++;
1694 rx_ring->rx_bytes += skb->len;
1695 skb->protocol = eth_type_trans(skb, ndev);
1696 skb_checksum_none_assert(skb);
1697
1698 /* If rx checksum is on, and there are no
1699 * csum or frame errors.
1700 */
1701 if ((ndev->features & NETIF_F_RXCSUM) &&
1702 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1703 /* TCP frame. */
1704 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1705 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1706 "TCP checksum done!\n");
1707 skb->ip_summed = CHECKSUM_UNNECESSARY;
1708 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1709 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1710 /* Unfragmented ipv4 UDP frame. */
1711 struct iphdr *iph = (struct iphdr *) skb->data;
1712 if (!(iph->frag_off &
1713 htons(IP_MF|IP_OFFSET))) {
1714 skb->ip_summed = CHECKSUM_UNNECESSARY;
1715 netif_printk(qdev, rx_status, KERN_DEBUG,
1716 qdev->ndev,
1717 "UDP checksum done!\n");
1718 }
1719 }
1720 }
1721
1722 skb_record_rx_queue(skb, rx_ring->cq_id);
1723 if (vlan_id != 0xffff)
1724 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1725 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
1726 napi_gro_receive(&rx_ring->napi, skb);
1727 else
1728 netif_receive_skb(skb);
1729 }
1730
1731 static void ql_realign_skb(struct sk_buff *skb, int len)
1732 {
1733 void *temp_addr = skb->data;
1734
1735 /* Undo the skb_reserve(skb,32) we did before
1736 * giving to hardware, and realign data on
1737 * a 2-byte boundary.
1738 */
1739 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1740 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1741 skb_copy_to_linear_data(skb, temp_addr,
1742 (unsigned int)len);
1743 }
1744
1745 /*
1746 * This function builds an skb for the given inbound
1747 * completion. It will be rewritten for readability in the near
1748 * future, but for not it works well.
1749 */
1750 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1751 struct rx_ring *rx_ring,
1752 struct ib_mac_iocb_rsp *ib_mac_rsp)
1753 {
1754 struct bq_desc *lbq_desc;
1755 struct bq_desc *sbq_desc;
1756 struct sk_buff *skb = NULL;
1757 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1758 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1759 size_t hlen = ETH_HLEN;
1760
1761 /*
1762 * Handle the header buffer if present.
1763 */
1764 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1765 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1766 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1767 "Header of %d bytes in small buffer.\n", hdr_len);
1768 /*
1769 * Headers fit nicely into a small buffer.
1770 */
1771 sbq_desc = ql_get_curr_sbuf(rx_ring);
1772 pci_unmap_single(qdev->pdev,
1773 dma_unmap_addr(sbq_desc, mapaddr),
1774 dma_unmap_len(sbq_desc, maplen),
1775 PCI_DMA_FROMDEVICE);
1776 skb = sbq_desc->p.skb;
1777 ql_realign_skb(skb, hdr_len);
1778 skb_put(skb, hdr_len);
1779 sbq_desc->p.skb = NULL;
1780 }
1781
1782 /*
1783 * Handle the data buffer(s).
1784 */
1785 if (unlikely(!length)) { /* Is there data too? */
1786 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1787 "No Data buffer in this packet.\n");
1788 return skb;
1789 }
1790
1791 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1792 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1793 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1794 "Headers in small, data of %d bytes in small, combine them.\n",
1795 length);
1796 /*
1797 * Data is less than small buffer size so it's
1798 * stuffed in a small buffer.
1799 * For this case we append the data
1800 * from the "data" small buffer to the "header" small
1801 * buffer.
1802 */
1803 sbq_desc = ql_get_curr_sbuf(rx_ring);
1804 pci_dma_sync_single_for_cpu(qdev->pdev,
1805 dma_unmap_addr
1806 (sbq_desc, mapaddr),
1807 dma_unmap_len
1808 (sbq_desc, maplen),
1809 PCI_DMA_FROMDEVICE);
1810 memcpy(skb_put(skb, length),
1811 sbq_desc->p.skb->data, length);
1812 pci_dma_sync_single_for_device(qdev->pdev,
1813 dma_unmap_addr
1814 (sbq_desc,
1815 mapaddr),
1816 dma_unmap_len
1817 (sbq_desc,
1818 maplen),
1819 PCI_DMA_FROMDEVICE);
1820 } else {
1821 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1822 "%d bytes in a single small buffer.\n",
1823 length);
1824 sbq_desc = ql_get_curr_sbuf(rx_ring);
1825 skb = sbq_desc->p.skb;
1826 ql_realign_skb(skb, length);
1827 skb_put(skb, length);
1828 pci_unmap_single(qdev->pdev,
1829 dma_unmap_addr(sbq_desc,
1830 mapaddr),
1831 dma_unmap_len(sbq_desc,
1832 maplen),
1833 PCI_DMA_FROMDEVICE);
1834 sbq_desc->p.skb = NULL;
1835 }
1836 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1837 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1838 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1839 "Header in small, %d bytes in large. Chain large to small!\n",
1840 length);
1841 /*
1842 * The data is in a single large buffer. We
1843 * chain it to the header buffer's skb and let
1844 * it rip.
1845 */
1846 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1847 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1848 "Chaining page at offset = %d, for %d bytes to skb.\n",
1849 lbq_desc->p.pg_chunk.offset, length);
1850 skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
1851 lbq_desc->p.pg_chunk.offset,
1852 length);
1853 skb->len += length;
1854 skb->data_len += length;
1855 skb->truesize += length;
1856 } else {
1857 /*
1858 * The headers and data are in a single large buffer. We
1859 * copy it to a new skb and let it go. This can happen with
1860 * jumbo mtu on a non-TCP/UDP frame.
1861 */
1862 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1863 skb = netdev_alloc_skb(qdev->ndev, length);
1864 if (skb == NULL) {
1865 netif_printk(qdev, probe, KERN_DEBUG, qdev->ndev,
1866 "No skb available, drop the packet.\n");
1867 return NULL;
1868 }
1869 pci_unmap_page(qdev->pdev,
1870 dma_unmap_addr(lbq_desc,
1871 mapaddr),
1872 dma_unmap_len(lbq_desc, maplen),
1873 PCI_DMA_FROMDEVICE);
1874 skb_reserve(skb, NET_IP_ALIGN);
1875 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1876 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n",
1877 length);
1878 skb_fill_page_desc(skb, 0,
1879 lbq_desc->p.pg_chunk.page,
1880 lbq_desc->p.pg_chunk.offset,
1881 length);
1882 skb->len += length;
1883 skb->data_len += length;
1884 skb->truesize += length;
1885 length -= length;
1886 ql_update_mac_hdr_len(qdev, ib_mac_rsp,
1887 lbq_desc->p.pg_chunk.va,
1888 &hlen);
1889 __pskb_pull_tail(skb, hlen);
1890 }
1891 } else {
1892 /*
1893 * The data is in a chain of large buffers
1894 * pointed to by a small buffer. We loop
1895 * thru and chain them to the our small header
1896 * buffer's skb.
1897 * frags: There are 18 max frags and our small
1898 * buffer will hold 32 of them. The thing is,
1899 * we'll use 3 max for our 9000 byte jumbo
1900 * frames. If the MTU goes up we could
1901 * eventually be in trouble.
1902 */
1903 int size, i = 0;
1904 sbq_desc = ql_get_curr_sbuf(rx_ring);
1905 pci_unmap_single(qdev->pdev,
1906 dma_unmap_addr(sbq_desc, mapaddr),
1907 dma_unmap_len(sbq_desc, maplen),
1908 PCI_DMA_FROMDEVICE);
1909 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1910 /*
1911 * This is an non TCP/UDP IP frame, so
1912 * the headers aren't split into a small
1913 * buffer. We have to use the small buffer
1914 * that contains our sg list as our skb to
1915 * send upstairs. Copy the sg list here to
1916 * a local buffer and use it to find the
1917 * pages to chain.
1918 */
1919 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1920 "%d bytes of headers & data in chain of large.\n",
1921 length);
1922 skb = sbq_desc->p.skb;
1923 sbq_desc->p.skb = NULL;
1924 skb_reserve(skb, NET_IP_ALIGN);
1925 }
1926 while (length > 0) {
1927 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1928 size = (length < rx_ring->lbq_buf_size) ? length :
1929 rx_ring->lbq_buf_size;
1930
1931 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1932 "Adding page %d to skb for %d bytes.\n",
1933 i, size);
1934 skb_fill_page_desc(skb, i,
1935 lbq_desc->p.pg_chunk.page,
1936 lbq_desc->p.pg_chunk.offset,
1937 size);
1938 skb->len += size;
1939 skb->data_len += size;
1940 skb->truesize += size;
1941 length -= size;
1942 i++;
1943 }
1944 ql_update_mac_hdr_len(qdev, ib_mac_rsp, lbq_desc->p.pg_chunk.va,
1945 &hlen);
1946 __pskb_pull_tail(skb, hlen);
1947 }
1948 return skb;
1949 }
1950
1951 /* Process an inbound completion from an rx ring. */
1952 static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev,
1953 struct rx_ring *rx_ring,
1954 struct ib_mac_iocb_rsp *ib_mac_rsp,
1955 u16 vlan_id)
1956 {
1957 struct net_device *ndev = qdev->ndev;
1958 struct sk_buff *skb = NULL;
1959
1960 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1961
1962 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1963 if (unlikely(!skb)) {
1964 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1965 "No skb available, drop packet.\n");
1966 rx_ring->rx_dropped++;
1967 return;
1968 }
1969
1970 /* Frame error, so drop the packet. */
1971 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1972 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1973 dev_kfree_skb_any(skb);
1974 return;
1975 }
1976
1977 /* The max framesize filter on this chip is set higher than
1978 * MTU since FCoE uses 2k frames.
1979 */
1980 if (skb->len > ndev->mtu + ETH_HLEN) {
1981 dev_kfree_skb_any(skb);
1982 rx_ring->rx_dropped++;
1983 return;
1984 }
1985
1986 /* loopback self test for ethtool */
1987 if (test_bit(QL_SELFTEST, &qdev->flags)) {
1988 ql_check_lb_frame(qdev, skb);
1989 dev_kfree_skb_any(skb);
1990 return;
1991 }
1992
1993 prefetch(skb->data);
1994 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1995 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, "%s Multicast.\n",
1996 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1997 IB_MAC_IOCB_RSP_M_HASH ? "Hash" :
1998 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1999 IB_MAC_IOCB_RSP_M_REG ? "Registered" :
2000 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2001 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
2002 rx_ring->rx_multicast++;
2003 }
2004 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
2005 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2006 "Promiscuous Packet.\n");
2007 }
2008
2009 skb->protocol = eth_type_trans(skb, ndev);
2010 skb_checksum_none_assert(skb);
2011
2012 /* If rx checksum is on, and there are no
2013 * csum or frame errors.
2014 */
2015 if ((ndev->features & NETIF_F_RXCSUM) &&
2016 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
2017 /* TCP frame. */
2018 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
2019 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2020 "TCP checksum done!\n");
2021 skb->ip_summed = CHECKSUM_UNNECESSARY;
2022 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
2023 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
2024 /* Unfragmented ipv4 UDP frame. */
2025 struct iphdr *iph = (struct iphdr *) skb->data;
2026 if (!(iph->frag_off &
2027 htons(IP_MF|IP_OFFSET))) {
2028 skb->ip_summed = CHECKSUM_UNNECESSARY;
2029 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2030 "TCP checksum done!\n");
2031 }
2032 }
2033 }
2034
2035 rx_ring->rx_packets++;
2036 rx_ring->rx_bytes += skb->len;
2037 skb_record_rx_queue(skb, rx_ring->cq_id);
2038 if (vlan_id != 0xffff)
2039 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
2040 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
2041 napi_gro_receive(&rx_ring->napi, skb);
2042 else
2043 netif_receive_skb(skb);
2044 }
2045
2046 /* Process an inbound completion from an rx ring. */
2047 static unsigned long ql_process_mac_rx_intr(struct ql_adapter *qdev,
2048 struct rx_ring *rx_ring,
2049 struct ib_mac_iocb_rsp *ib_mac_rsp)
2050 {
2051 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
2052 u16 vlan_id = ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
2053 (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)) ?
2054 ((le16_to_cpu(ib_mac_rsp->vlan_id) &
2055 IB_MAC_IOCB_RSP_VLAN_MASK)) : 0xffff;
2056
2057 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
2058
2059 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) {
2060 /* The data and headers are split into
2061 * separate buffers.
2062 */
2063 ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
2064 vlan_id);
2065 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
2066 /* The data fit in a single small buffer.
2067 * Allocate a new skb, copy the data and
2068 * return the buffer to the free pool.
2069 */
2070 ql_process_mac_rx_skb(qdev, rx_ring, ib_mac_rsp,
2071 length, vlan_id);
2072 } else if ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) &&
2073 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK) &&
2074 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T)) {
2075 /* TCP packet in a page chunk that's been checksummed.
2076 * Tack it on to our GRO skb and let it go.
2077 */
2078 ql_process_mac_rx_gro_page(qdev, rx_ring, ib_mac_rsp,
2079 length, vlan_id);
2080 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
2081 /* Non-TCP packet in a page chunk. Allocate an
2082 * skb, tack it on frags, and send it up.
2083 */
2084 ql_process_mac_rx_page(qdev, rx_ring, ib_mac_rsp,
2085 length, vlan_id);
2086 } else {
2087 /* Non-TCP/UDP large frames that span multiple buffers
2088 * can be processed corrrectly by the split frame logic.
2089 */
2090 ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
2091 vlan_id);
2092 }
2093
2094 return (unsigned long)length;
2095 }
2096
2097 /* Process an outbound completion from an rx ring. */
2098 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
2099 struct ob_mac_iocb_rsp *mac_rsp)
2100 {
2101 struct tx_ring *tx_ring;
2102 struct tx_ring_desc *tx_ring_desc;
2103
2104 QL_DUMP_OB_MAC_RSP(mac_rsp);
2105 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
2106 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
2107 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
2108 tx_ring->tx_bytes += (tx_ring_desc->skb)->len;
2109 tx_ring->tx_packets++;
2110 dev_kfree_skb(tx_ring_desc->skb);
2111 tx_ring_desc->skb = NULL;
2112
2113 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
2114 OB_MAC_IOCB_RSP_S |
2115 OB_MAC_IOCB_RSP_L |
2116 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
2117 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
2118 netif_warn(qdev, tx_done, qdev->ndev,
2119 "Total descriptor length did not match transfer length.\n");
2120 }
2121 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
2122 netif_warn(qdev, tx_done, qdev->ndev,
2123 "Frame too short to be valid, not sent.\n");
2124 }
2125 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
2126 netif_warn(qdev, tx_done, qdev->ndev,
2127 "Frame too long, but sent anyway.\n");
2128 }
2129 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
2130 netif_warn(qdev, tx_done, qdev->ndev,
2131 "PCI backplane error. Frame not sent.\n");
2132 }
2133 }
2134 atomic_inc(&tx_ring->tx_count);
2135 }
2136
2137 /* Fire up a handler to reset the MPI processor. */
2138 void ql_queue_fw_error(struct ql_adapter *qdev)
2139 {
2140 ql_link_off(qdev);
2141 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
2142 }
2143
2144 void ql_queue_asic_error(struct ql_adapter *qdev)
2145 {
2146 ql_link_off(qdev);
2147 ql_disable_interrupts(qdev);
2148 /* Clear adapter up bit to signal the recovery
2149 * process that it shouldn't kill the reset worker
2150 * thread
2151 */
2152 clear_bit(QL_ADAPTER_UP, &qdev->flags);
2153 /* Set asic recovery bit to indicate reset process that we are
2154 * in fatal error recovery process rather than normal close
2155 */
2156 set_bit(QL_ASIC_RECOVERY, &qdev->flags);
2157 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
2158 }
2159
2160 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
2161 struct ib_ae_iocb_rsp *ib_ae_rsp)
2162 {
2163 switch (ib_ae_rsp->event) {
2164 case MGMT_ERR_EVENT:
2165 netif_err(qdev, rx_err, qdev->ndev,
2166 "Management Processor Fatal Error.\n");
2167 ql_queue_fw_error(qdev);
2168 return;
2169
2170 case CAM_LOOKUP_ERR_EVENT:
2171 netdev_err(qdev->ndev, "Multiple CAM hits lookup occurred.\n");
2172 netdev_err(qdev->ndev, "This event shouldn't occur.\n");
2173 ql_queue_asic_error(qdev);
2174 return;
2175
2176 case SOFT_ECC_ERROR_EVENT:
2177 netdev_err(qdev->ndev, "Soft ECC error detected.\n");
2178 ql_queue_asic_error(qdev);
2179 break;
2180
2181 case PCI_ERR_ANON_BUF_RD:
2182 netdev_err(qdev->ndev, "PCI error occurred when reading "
2183 "anonymous buffers from rx_ring %d.\n",
2184 ib_ae_rsp->q_id);
2185 ql_queue_asic_error(qdev);
2186 break;
2187
2188 default:
2189 netif_err(qdev, drv, qdev->ndev, "Unexpected event %d.\n",
2190 ib_ae_rsp->event);
2191 ql_queue_asic_error(qdev);
2192 break;
2193 }
2194 }
2195
2196 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
2197 {
2198 struct ql_adapter *qdev = rx_ring->qdev;
2199 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2200 struct ob_mac_iocb_rsp *net_rsp = NULL;
2201 int count = 0;
2202
2203 struct tx_ring *tx_ring;
2204 /* While there are entries in the completion queue. */
2205 while (prod != rx_ring->cnsmr_idx) {
2206
2207 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2208 "cq_id = %d, prod = %d, cnsmr = %d.\n.",
2209 rx_ring->cq_id, prod, rx_ring->cnsmr_idx);
2210
2211 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
2212 rmb();
2213 switch (net_rsp->opcode) {
2214
2215 case OPCODE_OB_MAC_TSO_IOCB:
2216 case OPCODE_OB_MAC_IOCB:
2217 ql_process_mac_tx_intr(qdev, net_rsp);
2218 break;
2219 default:
2220 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2221 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
2222 net_rsp->opcode);
2223 }
2224 count++;
2225 ql_update_cq(rx_ring);
2226 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2227 }
2228 if (!net_rsp)
2229 return 0;
2230 ql_write_cq_idx(rx_ring);
2231 tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
2232 if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id)) {
2233 if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
2234 /*
2235 * The queue got stopped because the tx_ring was full.
2236 * Wake it up, because it's now at least 25% empty.
2237 */
2238 netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
2239 }
2240
2241 return count;
2242 }
2243
2244 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
2245 {
2246 struct ql_adapter *qdev = rx_ring->qdev;
2247 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2248 struct ql_net_rsp_iocb *net_rsp;
2249 int count = 0;
2250
2251 /* While there are entries in the completion queue. */
2252 while (prod != rx_ring->cnsmr_idx) {
2253
2254 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2255 "cq_id = %d, prod = %d, cnsmr = %d.\n.",
2256 rx_ring->cq_id, prod, rx_ring->cnsmr_idx);
2257
2258 net_rsp = rx_ring->curr_entry;
2259 rmb();
2260 switch (net_rsp->opcode) {
2261 case OPCODE_IB_MAC_IOCB:
2262 ql_process_mac_rx_intr(qdev, rx_ring,
2263 (struct ib_mac_iocb_rsp *)
2264 net_rsp);
2265 break;
2266
2267 case OPCODE_IB_AE_IOCB:
2268 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
2269 net_rsp);
2270 break;
2271 default:
2272 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2273 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
2274 net_rsp->opcode);
2275 break;
2276 }
2277 count++;
2278 ql_update_cq(rx_ring);
2279 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2280 if (count == budget)
2281 break;
2282 }
2283 ql_update_buffer_queues(qdev, rx_ring);
2284 ql_write_cq_idx(rx_ring);
2285 return count;
2286 }
2287
2288 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
2289 {
2290 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
2291 struct ql_adapter *qdev = rx_ring->qdev;
2292 struct rx_ring *trx_ring;
2293 int i, work_done = 0;
2294 struct intr_context *ctx = &qdev->intr_context[rx_ring->cq_id];
2295
2296 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2297 "Enter, NAPI POLL cq_id = %d.\n", rx_ring->cq_id);
2298
2299 /* Service the TX rings first. They start
2300 * right after the RSS rings. */
2301 for (i = qdev->rss_ring_count; i < qdev->rx_ring_count; i++) {
2302 trx_ring = &qdev->rx_ring[i];
2303 /* If this TX completion ring belongs to this vector and
2304 * it's not empty then service it.
2305 */
2306 if ((ctx->irq_mask & (1 << trx_ring->cq_id)) &&
2307 (ql_read_sh_reg(trx_ring->prod_idx_sh_reg) !=
2308 trx_ring->cnsmr_idx)) {
2309 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2310 "%s: Servicing TX completion ring %d.\n",
2311 __func__, trx_ring->cq_id);
2312 ql_clean_outbound_rx_ring(trx_ring);
2313 }
2314 }
2315
2316 /*
2317 * Now service the RSS ring if it's active.
2318 */
2319 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
2320 rx_ring->cnsmr_idx) {
2321 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2322 "%s: Servicing RX completion ring %d.\n",
2323 __func__, rx_ring->cq_id);
2324 work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
2325 }
2326
2327 if (work_done < budget) {
2328 napi_complete(napi);
2329 ql_enable_completion_interrupt(qdev, rx_ring->irq);
2330 }
2331 return work_done;
2332 }
2333
2334 static void qlge_vlan_mode(struct net_device *ndev, netdev_features_t features)
2335 {
2336 struct ql_adapter *qdev = netdev_priv(ndev);
2337
2338 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2339 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
2340 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
2341 } else {
2342 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
2343 }
2344 }
2345
2346 /**
2347 * qlge_update_hw_vlan_features - helper routine to reinitialize the adapter
2348 * based on the features to enable/disable hardware vlan accel
2349 */
2350 static int qlge_update_hw_vlan_features(struct net_device *ndev,
2351 netdev_features_t features)
2352 {
2353 struct ql_adapter *qdev = netdev_priv(ndev);
2354 int status = 0;
2355
2356 status = ql_adapter_down(qdev);
2357 if (status) {
2358 netif_err(qdev, link, qdev->ndev,
2359 "Failed to bring down the adapter\n");
2360 return status;
2361 }
2362
2363 /* update the features with resent change */
2364 ndev->features = features;
2365
2366 status = ql_adapter_up(qdev);
2367 if (status) {
2368 netif_err(qdev, link, qdev->ndev,
2369 "Failed to bring up the adapter\n");
2370 return status;
2371 }
2372 return status;
2373 }
2374
2375 static netdev_features_t qlge_fix_features(struct net_device *ndev,
2376 netdev_features_t features)
2377 {
2378 int err;
2379 /*
2380 * Since there is no support for separate rx/tx vlan accel
2381 * enable/disable make sure tx flag is always in same state as rx.
2382 */
2383 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2384 features |= NETIF_F_HW_VLAN_CTAG_TX;
2385 else
2386 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2387
2388 /* Update the behavior of vlan accel in the adapter */
2389 err = qlge_update_hw_vlan_features(ndev, features);
2390 if (err)
2391 return err;
2392
2393 return features;
2394 }
2395
2396 static int qlge_set_features(struct net_device *ndev,
2397 netdev_features_t features)
2398 {
2399 netdev_features_t changed = ndev->features ^ features;
2400
2401 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2402 qlge_vlan_mode(ndev, features);
2403
2404 return 0;
2405 }
2406
2407 static int __qlge_vlan_rx_add_vid(struct ql_adapter *qdev, u16 vid)
2408 {
2409 u32 enable_bit = MAC_ADDR_E;
2410 int err;
2411
2412 err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit,
2413 MAC_ADDR_TYPE_VLAN, vid);
2414 if (err)
2415 netif_err(qdev, ifup, qdev->ndev,
2416 "Failed to init vlan address.\n");
2417 return err;
2418 }
2419
2420 static int qlge_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
2421 {
2422 struct ql_adapter *qdev = netdev_priv(ndev);
2423 int status;
2424 int err;
2425
2426 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2427 if (status)
2428 return status;
2429
2430 err = __qlge_vlan_rx_add_vid(qdev, vid);
2431 set_bit(vid, qdev->active_vlans);
2432
2433 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2434
2435 return err;
2436 }
2437
2438 static int __qlge_vlan_rx_kill_vid(struct ql_adapter *qdev, u16 vid)
2439 {
2440 u32 enable_bit = 0;
2441 int err;
2442
2443 err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit,
2444 MAC_ADDR_TYPE_VLAN, vid);
2445 if (err)
2446 netif_err(qdev, ifup, qdev->ndev,
2447 "Failed to clear vlan address.\n");
2448 return err;
2449 }
2450
2451 static int qlge_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
2452 {
2453 struct ql_adapter *qdev = netdev_priv(ndev);
2454 int status;
2455 int err;
2456
2457 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2458 if (status)
2459 return status;
2460
2461 err = __qlge_vlan_rx_kill_vid(qdev, vid);
2462 clear_bit(vid, qdev->active_vlans);
2463
2464 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2465
2466 return err;
2467 }
2468
2469 static void qlge_restore_vlan(struct ql_adapter *qdev)
2470 {
2471 int status;
2472 u16 vid;
2473
2474 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2475 if (status)
2476 return;
2477
2478 for_each_set_bit(vid, qdev->active_vlans, VLAN_N_VID)
2479 __qlge_vlan_rx_add_vid(qdev, vid);
2480
2481 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2482 }
2483
2484 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
2485 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
2486 {
2487 struct rx_ring *rx_ring = dev_id;
2488 napi_schedule(&rx_ring->napi);
2489 return IRQ_HANDLED;
2490 }
2491
2492 /* This handles a fatal error, MPI activity, and the default
2493 * rx_ring in an MSI-X multiple vector environment.
2494 * In MSI/Legacy environment it also process the rest of
2495 * the rx_rings.
2496 */
2497 static irqreturn_t qlge_isr(int irq, void *dev_id)
2498 {
2499 struct rx_ring *rx_ring = dev_id;
2500 struct ql_adapter *qdev = rx_ring->qdev;
2501 struct intr_context *intr_context = &qdev->intr_context[0];
2502 u32 var;
2503 int work_done = 0;
2504
2505 spin_lock(&qdev->hw_lock);
2506 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
2507 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2508 "Shared Interrupt, Not ours!\n");
2509 spin_unlock(&qdev->hw_lock);
2510 return IRQ_NONE;
2511 }
2512 spin_unlock(&qdev->hw_lock);
2513
2514 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
2515
2516 /*
2517 * Check for fatal error.
2518 */
2519 if (var & STS_FE) {
2520 ql_queue_asic_error(qdev);
2521 netdev_err(qdev->ndev, "Got fatal error, STS = %x.\n", var);
2522 var = ql_read32(qdev, ERR_STS);
2523 netdev_err(qdev->ndev, "Resetting chip. "
2524 "Error Status Register = 0x%x\n", var);
2525 return IRQ_HANDLED;
2526 }
2527
2528 /*
2529 * Check MPI processor activity.
2530 */
2531 if ((var & STS_PI) &&
2532 (ql_read32(qdev, INTR_MASK) & INTR_MASK_PI)) {
2533 /*
2534 * We've got an async event or mailbox completion.
2535 * Handle it and clear the source of the interrupt.
2536 */
2537 netif_err(qdev, intr, qdev->ndev,
2538 "Got MPI processor interrupt.\n");
2539 ql_disable_completion_interrupt(qdev, intr_context->intr);
2540 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
2541 queue_delayed_work_on(smp_processor_id(),
2542 qdev->workqueue, &qdev->mpi_work, 0);
2543 work_done++;
2544 }
2545
2546 /*
2547 * Get the bit-mask that shows the active queues for this
2548 * pass. Compare it to the queues that this irq services
2549 * and call napi if there's a match.
2550 */
2551 var = ql_read32(qdev, ISR1);
2552 if (var & intr_context->irq_mask) {
2553 netif_info(qdev, intr, qdev->ndev,
2554 "Waking handler for rx_ring[0].\n");
2555 ql_disable_completion_interrupt(qdev, intr_context->intr);
2556 napi_schedule(&rx_ring->napi);
2557 work_done++;
2558 }
2559 ql_enable_completion_interrupt(qdev, intr_context->intr);
2560 return work_done ? IRQ_HANDLED : IRQ_NONE;
2561 }
2562
2563 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2564 {
2565
2566 if (skb_is_gso(skb)) {
2567 int err;
2568 if (skb_header_cloned(skb)) {
2569 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2570 if (err)
2571 return err;
2572 }
2573
2574 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2575 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
2576 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2577 mac_iocb_ptr->total_hdrs_len =
2578 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
2579 mac_iocb_ptr->net_trans_offset =
2580 cpu_to_le16(skb_network_offset(skb) |
2581 skb_transport_offset(skb)
2582 << OB_MAC_TRANSPORT_HDR_SHIFT);
2583 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
2584 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
2585 if (likely(skb->protocol == htons(ETH_P_IP))) {
2586 struct iphdr *iph = ip_hdr(skb);
2587 iph->check = 0;
2588 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2589 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2590 iph->daddr, 0,
2591 IPPROTO_TCP,
2592 0);
2593 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2594 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2595 tcp_hdr(skb)->check =
2596 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2597 &ipv6_hdr(skb)->daddr,
2598 0, IPPROTO_TCP, 0);
2599 }
2600 return 1;
2601 }
2602 return 0;
2603 }
2604
2605 static void ql_hw_csum_setup(struct sk_buff *skb,
2606 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2607 {
2608 int len;
2609 struct iphdr *iph = ip_hdr(skb);
2610 __sum16 *check;
2611 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2612 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2613 mac_iocb_ptr->net_trans_offset =
2614 cpu_to_le16(skb_network_offset(skb) |
2615 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2616
2617 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2618 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2619 if (likely(iph->protocol == IPPROTO_TCP)) {
2620 check = &(tcp_hdr(skb)->check);
2621 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2622 mac_iocb_ptr->total_hdrs_len =
2623 cpu_to_le16(skb_transport_offset(skb) +
2624 (tcp_hdr(skb)->doff << 2));
2625 } else {
2626 check = &(udp_hdr(skb)->check);
2627 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2628 mac_iocb_ptr->total_hdrs_len =
2629 cpu_to_le16(skb_transport_offset(skb) +
2630 sizeof(struct udphdr));
2631 }
2632 *check = ~csum_tcpudp_magic(iph->saddr,
2633 iph->daddr, len, iph->protocol, 0);
2634 }
2635
2636 static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev)
2637 {
2638 struct tx_ring_desc *tx_ring_desc;
2639 struct ob_mac_iocb_req *mac_iocb_ptr;
2640 struct ql_adapter *qdev = netdev_priv(ndev);
2641 int tso;
2642 struct tx_ring *tx_ring;
2643 u32 tx_ring_idx = (u32) skb->queue_mapping;
2644
2645 tx_ring = &qdev->tx_ring[tx_ring_idx];
2646
2647 if (skb_padto(skb, ETH_ZLEN))
2648 return NETDEV_TX_OK;
2649
2650 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2651 netif_info(qdev, tx_queued, qdev->ndev,
2652 "%s: BUG! shutting down tx queue %d due to lack of resources.\n",
2653 __func__, tx_ring_idx);
2654 netif_stop_subqueue(ndev, tx_ring->wq_id);
2655 tx_ring->tx_errors++;
2656 return NETDEV_TX_BUSY;
2657 }
2658 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2659 mac_iocb_ptr = tx_ring_desc->queue_entry;
2660 memset((void *)mac_iocb_ptr, 0, sizeof(*mac_iocb_ptr));
2661
2662 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2663 mac_iocb_ptr->tid = tx_ring_desc->index;
2664 /* We use the upper 32-bits to store the tx queue for this IO.
2665 * When we get the completion we can use it to establish the context.
2666 */
2667 mac_iocb_ptr->txq_idx = tx_ring_idx;
2668 tx_ring_desc->skb = skb;
2669
2670 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2671
2672 if (vlan_tx_tag_present(skb)) {
2673 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
2674 "Adding a vlan tag %d.\n", vlan_tx_tag_get(skb));
2675 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2676 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2677 }
2678 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2679 if (tso < 0) {
2680 dev_kfree_skb_any(skb);
2681 return NETDEV_TX_OK;
2682 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2683 ql_hw_csum_setup(skb,
2684 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2685 }
2686 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2687 NETDEV_TX_OK) {
2688 netif_err(qdev, tx_queued, qdev->ndev,
2689 "Could not map the segments.\n");
2690 tx_ring->tx_errors++;
2691 return NETDEV_TX_BUSY;
2692 }
2693 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2694 tx_ring->prod_idx++;
2695 if (tx_ring->prod_idx == tx_ring->wq_len)
2696 tx_ring->prod_idx = 0;
2697 wmb();
2698
2699 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2700 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
2701 "tx queued, slot %d, len %d\n",
2702 tx_ring->prod_idx, skb->len);
2703
2704 atomic_dec(&tx_ring->tx_count);
2705
2706 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2707 netif_stop_subqueue(ndev, tx_ring->wq_id);
2708 if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
2709 /*
2710 * The queue got stopped because the tx_ring was full.
2711 * Wake it up, because it's now at least 25% empty.
2712 */
2713 netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
2714 }
2715 return NETDEV_TX_OK;
2716 }
2717
2718
2719 static void ql_free_shadow_space(struct ql_adapter *qdev)
2720 {
2721 if (qdev->rx_ring_shadow_reg_area) {
2722 pci_free_consistent(qdev->pdev,
2723 PAGE_SIZE,
2724 qdev->rx_ring_shadow_reg_area,
2725 qdev->rx_ring_shadow_reg_dma);
2726 qdev->rx_ring_shadow_reg_area = NULL;
2727 }
2728 if (qdev->tx_ring_shadow_reg_area) {
2729 pci_free_consistent(qdev->pdev,
2730 PAGE_SIZE,
2731 qdev->tx_ring_shadow_reg_area,
2732 qdev->tx_ring_shadow_reg_dma);
2733 qdev->tx_ring_shadow_reg_area = NULL;
2734 }
2735 }
2736
2737 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2738 {
2739 qdev->rx_ring_shadow_reg_area =
2740 pci_alloc_consistent(qdev->pdev,
2741 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2742 if (qdev->rx_ring_shadow_reg_area == NULL) {
2743 netif_err(qdev, ifup, qdev->ndev,
2744 "Allocation of RX shadow space failed.\n");
2745 return -ENOMEM;
2746 }
2747 memset(qdev->rx_ring_shadow_reg_area, 0, PAGE_SIZE);
2748 qdev->tx_ring_shadow_reg_area =
2749 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2750 &qdev->tx_ring_shadow_reg_dma);
2751 if (qdev->tx_ring_shadow_reg_area == NULL) {
2752 netif_err(qdev, ifup, qdev->ndev,
2753 "Allocation of TX shadow space failed.\n");
2754 goto err_wqp_sh_area;
2755 }
2756 memset(qdev->tx_ring_shadow_reg_area, 0, PAGE_SIZE);
2757 return 0;
2758
2759 err_wqp_sh_area:
2760 pci_free_consistent(qdev->pdev,
2761 PAGE_SIZE,
2762 qdev->rx_ring_shadow_reg_area,
2763 qdev->rx_ring_shadow_reg_dma);
2764 return -ENOMEM;
2765 }
2766
2767 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2768 {
2769 struct tx_ring_desc *tx_ring_desc;
2770 int i;
2771 struct ob_mac_iocb_req *mac_iocb_ptr;
2772
2773 mac_iocb_ptr = tx_ring->wq_base;
2774 tx_ring_desc = tx_ring->q;
2775 for (i = 0; i < tx_ring->wq_len; i++) {
2776 tx_ring_desc->index = i;
2777 tx_ring_desc->skb = NULL;
2778 tx_ring_desc->queue_entry = mac_iocb_ptr;
2779 mac_iocb_ptr++;
2780 tx_ring_desc++;
2781 }
2782 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2783 }
2784
2785 static void ql_free_tx_resources(struct ql_adapter *qdev,
2786 struct tx_ring *tx_ring)
2787 {
2788 if (tx_ring->wq_base) {
2789 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2790 tx_ring->wq_base, tx_ring->wq_base_dma);
2791 tx_ring->wq_base = NULL;
2792 }
2793 kfree(tx_ring->q);
2794 tx_ring->q = NULL;
2795 }
2796
2797 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2798 struct tx_ring *tx_ring)
2799 {
2800 tx_ring->wq_base =
2801 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2802 &tx_ring->wq_base_dma);
2803
2804 if ((tx_ring->wq_base == NULL) ||
2805 tx_ring->wq_base_dma & WQ_ADDR_ALIGN)
2806 goto pci_alloc_err;
2807
2808 tx_ring->q =
2809 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2810 if (tx_ring->q == NULL)
2811 goto err;
2812
2813 return 0;
2814 err:
2815 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2816 tx_ring->wq_base, tx_ring->wq_base_dma);
2817 tx_ring->wq_base = NULL;
2818 pci_alloc_err:
2819 netif_err(qdev, ifup, qdev->ndev, "tx_ring alloc failed.\n");
2820 return -ENOMEM;
2821 }
2822
2823 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2824 {
2825 struct bq_desc *lbq_desc;
2826
2827 uint32_t curr_idx, clean_idx;
2828
2829 curr_idx = rx_ring->lbq_curr_idx;
2830 clean_idx = rx_ring->lbq_clean_idx;
2831 while (curr_idx != clean_idx) {
2832 lbq_desc = &rx_ring->lbq[curr_idx];
2833
2834 if (lbq_desc->p.pg_chunk.last_flag) {
2835 pci_unmap_page(qdev->pdev,
2836 lbq_desc->p.pg_chunk.map,
2837 ql_lbq_block_size(qdev),
2838 PCI_DMA_FROMDEVICE);
2839 lbq_desc->p.pg_chunk.last_flag = 0;
2840 }
2841
2842 put_page(lbq_desc->p.pg_chunk.page);
2843 lbq_desc->p.pg_chunk.page = NULL;
2844
2845 if (++curr_idx == rx_ring->lbq_len)
2846 curr_idx = 0;
2847
2848 }
2849 if (rx_ring->pg_chunk.page) {
2850 pci_unmap_page(qdev->pdev, rx_ring->pg_chunk.map,
2851 ql_lbq_block_size(qdev), PCI_DMA_FROMDEVICE);
2852 put_page(rx_ring->pg_chunk.page);
2853 rx_ring->pg_chunk.page = NULL;
2854 }
2855 }
2856
2857 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2858 {
2859 int i;
2860 struct bq_desc *sbq_desc;
2861
2862 for (i = 0; i < rx_ring->sbq_len; i++) {
2863 sbq_desc = &rx_ring->sbq[i];
2864 if (sbq_desc == NULL) {
2865 netif_err(qdev, ifup, qdev->ndev,
2866 "sbq_desc %d is NULL.\n", i);
2867 return;
2868 }
2869 if (sbq_desc->p.skb) {
2870 pci_unmap_single(qdev->pdev,
2871 dma_unmap_addr(sbq_desc, mapaddr),
2872 dma_unmap_len(sbq_desc, maplen),
2873 PCI_DMA_FROMDEVICE);
2874 dev_kfree_skb(sbq_desc->p.skb);
2875 sbq_desc->p.skb = NULL;
2876 }
2877 }
2878 }
2879
2880 /* Free all large and small rx buffers associated
2881 * with the completion queues for this device.
2882 */
2883 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2884 {
2885 int i;
2886 struct rx_ring *rx_ring;
2887
2888 for (i = 0; i < qdev->rx_ring_count; i++) {
2889 rx_ring = &qdev->rx_ring[i];
2890 if (rx_ring->lbq)
2891 ql_free_lbq_buffers(qdev, rx_ring);
2892 if (rx_ring->sbq)
2893 ql_free_sbq_buffers(qdev, rx_ring);
2894 }
2895 }
2896
2897 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2898 {
2899 struct rx_ring *rx_ring;
2900 int i;
2901
2902 for (i = 0; i < qdev->rx_ring_count; i++) {
2903 rx_ring = &qdev->rx_ring[i];
2904 if (rx_ring->type != TX_Q)
2905 ql_update_buffer_queues(qdev, rx_ring);
2906 }
2907 }
2908
2909 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2910 struct rx_ring *rx_ring)
2911 {
2912 int i;
2913 struct bq_desc *lbq_desc;
2914 __le64 *bq = rx_ring->lbq_base;
2915
2916 memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2917 for (i = 0; i < rx_ring->lbq_len; i++) {
2918 lbq_desc = &rx_ring->lbq[i];
2919 memset(lbq_desc, 0, sizeof(*lbq_desc));
2920 lbq_desc->index = i;
2921 lbq_desc->addr = bq;
2922 bq++;
2923 }
2924 }
2925
2926 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2927 struct rx_ring *rx_ring)
2928 {
2929 int i;
2930 struct bq_desc *sbq_desc;
2931 __le64 *bq = rx_ring->sbq_base;
2932
2933 memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2934 for (i = 0; i < rx_ring->sbq_len; i++) {
2935 sbq_desc = &rx_ring->sbq[i];
2936 memset(sbq_desc, 0, sizeof(*sbq_desc));
2937 sbq_desc->index = i;
2938 sbq_desc->addr = bq;
2939 bq++;
2940 }
2941 }
2942
2943 static void ql_free_rx_resources(struct ql_adapter *qdev,
2944 struct rx_ring *rx_ring)
2945 {
2946 /* Free the small buffer queue. */
2947 if (rx_ring->sbq_base) {
2948 pci_free_consistent(qdev->pdev,
2949 rx_ring->sbq_size,
2950 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2951 rx_ring->sbq_base = NULL;
2952 }
2953
2954 /* Free the small buffer queue control blocks. */
2955 kfree(rx_ring->sbq);
2956 rx_ring->sbq = NULL;
2957
2958 /* Free the large buffer queue. */
2959 if (rx_ring->lbq_base) {
2960 pci_free_consistent(qdev->pdev,
2961 rx_ring->lbq_size,
2962 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2963 rx_ring->lbq_base = NULL;
2964 }
2965
2966 /* Free the large buffer queue control blocks. */
2967 kfree(rx_ring->lbq);
2968 rx_ring->lbq = NULL;
2969
2970 /* Free the rx queue. */
2971 if (rx_ring->cq_base) {
2972 pci_free_consistent(qdev->pdev,
2973 rx_ring->cq_size,
2974 rx_ring->cq_base, rx_ring->cq_base_dma);
2975 rx_ring->cq_base = NULL;
2976 }
2977 }
2978
2979 /* Allocate queues and buffers for this completions queue based
2980 * on the values in the parameter structure. */
2981 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2982 struct rx_ring *rx_ring)
2983 {
2984
2985 /*
2986 * Allocate the completion queue for this rx_ring.
2987 */
2988 rx_ring->cq_base =
2989 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2990 &rx_ring->cq_base_dma);
2991
2992 if (rx_ring->cq_base == NULL) {
2993 netif_err(qdev, ifup, qdev->ndev, "rx_ring alloc failed.\n");
2994 return -ENOMEM;
2995 }
2996
2997 if (rx_ring->sbq_len) {
2998 /*
2999 * Allocate small buffer queue.
3000 */
3001 rx_ring->sbq_base =
3002 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
3003 &rx_ring->sbq_base_dma);
3004
3005 if (rx_ring->sbq_base == NULL) {
3006 netif_err(qdev, ifup, qdev->ndev,
3007 "Small buffer queue allocation failed.\n");
3008 goto err_mem;
3009 }
3010
3011 /*
3012 * Allocate small buffer queue control blocks.
3013 */
3014 rx_ring->sbq = kmalloc_array(rx_ring->sbq_len,
3015 sizeof(struct bq_desc),
3016 GFP_KERNEL);
3017 if (rx_ring->sbq == NULL)
3018 goto err_mem;
3019
3020 ql_init_sbq_ring(qdev, rx_ring);
3021 }
3022
3023 if (rx_ring->lbq_len) {
3024 /*
3025 * Allocate large buffer queue.
3026 */
3027 rx_ring->lbq_base =
3028 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
3029 &rx_ring->lbq_base_dma);
3030
3031 if (rx_ring->lbq_base == NULL) {
3032 netif_err(qdev, ifup, qdev->ndev,
3033 "Large buffer queue allocation failed.\n");
3034 goto err_mem;
3035 }
3036 /*
3037 * Allocate large buffer queue control blocks.
3038 */
3039 rx_ring->lbq = kmalloc_array(rx_ring->lbq_len,
3040 sizeof(struct bq_desc),
3041 GFP_KERNEL);
3042 if (rx_ring->lbq == NULL)
3043 goto err_mem;
3044
3045 ql_init_lbq_ring(qdev, rx_ring);
3046 }
3047
3048 return 0;
3049
3050 err_mem:
3051 ql_free_rx_resources(qdev, rx_ring);
3052 return -ENOMEM;
3053 }
3054
3055 static void ql_tx_ring_clean(struct ql_adapter *qdev)
3056 {
3057 struct tx_ring *tx_ring;
3058 struct tx_ring_desc *tx_ring_desc;
3059 int i, j;
3060
3061 /*
3062 * Loop through all queues and free
3063 * any resources.
3064 */
3065 for (j = 0; j < qdev->tx_ring_count; j++) {
3066 tx_ring = &qdev->tx_ring[j];
3067 for (i = 0; i < tx_ring->wq_len; i++) {
3068 tx_ring_desc = &tx_ring->q[i];
3069 if (tx_ring_desc && tx_ring_desc->skb) {
3070 netif_err(qdev, ifdown, qdev->ndev,
3071 "Freeing lost SKB %p, from queue %d, index %d.\n",
3072 tx_ring_desc->skb, j,
3073 tx_ring_desc->index);
3074 ql_unmap_send(qdev, tx_ring_desc,
3075 tx_ring_desc->map_cnt);
3076 dev_kfree_skb(tx_ring_desc->skb);
3077 tx_ring_desc->skb = NULL;
3078 }
3079 }
3080 }
3081 }
3082
3083 static void ql_free_mem_resources(struct ql_adapter *qdev)
3084 {
3085 int i;
3086
3087 for (i = 0; i < qdev->tx_ring_count; i++)
3088 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
3089 for (i = 0; i < qdev->rx_ring_count; i++)
3090 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
3091 ql_free_shadow_space(qdev);
3092 }
3093
3094 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
3095 {
3096 int i;
3097
3098 /* Allocate space for our shadow registers and such. */
3099 if (ql_alloc_shadow_space(qdev))
3100 return -ENOMEM;
3101
3102 for (i = 0; i < qdev->rx_ring_count; i++) {
3103 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
3104 netif_err(qdev, ifup, qdev->ndev,
3105 "RX resource allocation failed.\n");
3106 goto err_mem;
3107 }
3108 }
3109 /* Allocate tx queue resources */
3110 for (i = 0; i < qdev->tx_ring_count; i++) {
3111 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
3112 netif_err(qdev, ifup, qdev->ndev,
3113 "TX resource allocation failed.\n");
3114 goto err_mem;
3115 }
3116 }
3117 return 0;
3118
3119 err_mem:
3120 ql_free_mem_resources(qdev);
3121 return -ENOMEM;
3122 }
3123
3124 /* Set up the rx ring control block and pass it to the chip.
3125 * The control block is defined as
3126 * "Completion Queue Initialization Control Block", or cqicb.
3127 */
3128 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
3129 {
3130 struct cqicb *cqicb = &rx_ring->cqicb;
3131 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
3132 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
3133 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
3134 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
3135 void __iomem *doorbell_area =
3136 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
3137 int err = 0;
3138 u16 bq_len;
3139 u64 tmp;
3140 __le64 *base_indirect_ptr;
3141 int page_entries;
3142
3143 /* Set up the shadow registers for this ring. */
3144 rx_ring->prod_idx_sh_reg = shadow_reg;
3145 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
3146 *rx_ring->prod_idx_sh_reg = 0;
3147 shadow_reg += sizeof(u64);
3148 shadow_reg_dma += sizeof(u64);
3149 rx_ring->lbq_base_indirect = shadow_reg;
3150 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
3151 shadow_reg += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3152 shadow_reg_dma += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3153 rx_ring->sbq_base_indirect = shadow_reg;
3154 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
3155
3156 /* PCI doorbell mem area + 0x00 for consumer index register */
3157 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
3158 rx_ring->cnsmr_idx = 0;
3159 rx_ring->curr_entry = rx_ring->cq_base;
3160
3161 /* PCI doorbell mem area + 0x04 for valid register */
3162 rx_ring->valid_db_reg = doorbell_area + 0x04;
3163
3164 /* PCI doorbell mem area + 0x18 for large buffer consumer */
3165 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
3166
3167 /* PCI doorbell mem area + 0x1c */
3168 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
3169
3170 memset((void *)cqicb, 0, sizeof(struct cqicb));
3171 cqicb->msix_vect = rx_ring->irq;
3172
3173 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
3174 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
3175
3176 cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
3177
3178 cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
3179
3180 /*
3181 * Set up the control block load flags.
3182 */
3183 cqicb->flags = FLAGS_LC | /* Load queue base address */
3184 FLAGS_LV | /* Load MSI-X vector */
3185 FLAGS_LI; /* Load irq delay values */
3186 if (rx_ring->lbq_len) {
3187 cqicb->flags |= FLAGS_LL; /* Load lbq values */
3188 tmp = (u64)rx_ring->lbq_base_dma;
3189 base_indirect_ptr = rx_ring->lbq_base_indirect;
3190 page_entries = 0;
3191 do {
3192 *base_indirect_ptr = cpu_to_le64(tmp);
3193 tmp += DB_PAGE_SIZE;
3194 base_indirect_ptr++;
3195 page_entries++;
3196 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3197 cqicb->lbq_addr =
3198 cpu_to_le64(rx_ring->lbq_base_indirect_dma);
3199 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
3200 (u16) rx_ring->lbq_buf_size;
3201 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
3202 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
3203 (u16) rx_ring->lbq_len;
3204 cqicb->lbq_len = cpu_to_le16(bq_len);
3205 rx_ring->lbq_prod_idx = 0;
3206 rx_ring->lbq_curr_idx = 0;
3207 rx_ring->lbq_clean_idx = 0;
3208 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
3209 }
3210 if (rx_ring->sbq_len) {
3211 cqicb->flags |= FLAGS_LS; /* Load sbq values */
3212 tmp = (u64)rx_ring->sbq_base_dma;
3213 base_indirect_ptr = rx_ring->sbq_base_indirect;
3214 page_entries = 0;
3215 do {
3216 *base_indirect_ptr = cpu_to_le64(tmp);
3217 tmp += DB_PAGE_SIZE;
3218 base_indirect_ptr++;
3219 page_entries++;
3220 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->sbq_len));
3221 cqicb->sbq_addr =
3222 cpu_to_le64(rx_ring->sbq_base_indirect_dma);
3223 cqicb->sbq_buf_size =
3224 cpu_to_le16((u16)(rx_ring->sbq_buf_size));
3225 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
3226 (u16) rx_ring->sbq_len;
3227 cqicb->sbq_len = cpu_to_le16(bq_len);
3228 rx_ring->sbq_prod_idx = 0;
3229 rx_ring->sbq_curr_idx = 0;
3230 rx_ring->sbq_clean_idx = 0;
3231 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
3232 }
3233 switch (rx_ring->type) {
3234 case TX_Q:
3235 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
3236 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
3237 break;
3238 case RX_Q:
3239 /* Inbound completion handling rx_rings run in
3240 * separate NAPI contexts.
3241 */
3242 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
3243 64);
3244 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
3245 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
3246 break;
3247 default:
3248 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3249 "Invalid rx_ring->type = %d.\n", rx_ring->type);
3250 }
3251 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
3252 CFG_LCQ, rx_ring->cq_id);
3253 if (err) {
3254 netif_err(qdev, ifup, qdev->ndev, "Failed to load CQICB.\n");
3255 return err;
3256 }
3257 return err;
3258 }
3259
3260 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
3261 {
3262 struct wqicb *wqicb = (struct wqicb *)tx_ring;
3263 void __iomem *doorbell_area =
3264 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
3265 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
3266 (tx_ring->wq_id * sizeof(u64));
3267 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
3268 (tx_ring->wq_id * sizeof(u64));
3269 int err = 0;
3270
3271 /*
3272 * Assign doorbell registers for this tx_ring.
3273 */
3274 /* TX PCI doorbell mem area for tx producer index */
3275 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
3276 tx_ring->prod_idx = 0;
3277 /* TX PCI doorbell mem area + 0x04 */
3278 tx_ring->valid_db_reg = doorbell_area + 0x04;
3279
3280 /*
3281 * Assign shadow registers for this tx_ring.
3282 */
3283 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
3284 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
3285
3286 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
3287 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
3288 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
3289 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
3290 wqicb->rid = 0;
3291 wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
3292
3293 wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
3294
3295 ql_init_tx_ring(qdev, tx_ring);
3296
3297 err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ,
3298 (u16) tx_ring->wq_id);
3299 if (err) {
3300 netif_err(qdev, ifup, qdev->ndev, "Failed to load tx_ring.\n");
3301 return err;
3302 }
3303 return err;
3304 }
3305
3306 static void ql_disable_msix(struct ql_adapter *qdev)
3307 {
3308 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3309 pci_disable_msix(qdev->pdev);
3310 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
3311 kfree(qdev->msi_x_entry);
3312 qdev->msi_x_entry = NULL;
3313 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3314 pci_disable_msi(qdev->pdev);
3315 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3316 }
3317 }
3318
3319 /* We start by trying to get the number of vectors
3320 * stored in qdev->intr_count. If we don't get that
3321 * many then we reduce the count and try again.
3322 */
3323 static void ql_enable_msix(struct ql_adapter *qdev)
3324 {
3325 int i, err;
3326
3327 /* Get the MSIX vectors. */
3328 if (qlge_irq_type == MSIX_IRQ) {
3329 /* Try to alloc space for the msix struct,
3330 * if it fails then go to MSI/legacy.
3331 */
3332 qdev->msi_x_entry = kcalloc(qdev->intr_count,
3333 sizeof(struct msix_entry),
3334 GFP_KERNEL);
3335 if (!qdev->msi_x_entry) {
3336 qlge_irq_type = MSI_IRQ;
3337 goto msi;
3338 }
3339
3340 for (i = 0; i < qdev->intr_count; i++)
3341 qdev->msi_x_entry[i].entry = i;
3342
3343 /* Loop to get our vectors. We start with
3344 * what we want and settle for what we get.
3345 */
3346 do {
3347 err = pci_enable_msix(qdev->pdev,
3348 qdev->msi_x_entry, qdev->intr_count);
3349 if (err > 0)
3350 qdev->intr_count = err;
3351 } while (err > 0);
3352
3353 if (err < 0) {
3354 kfree(qdev->msi_x_entry);
3355 qdev->msi_x_entry = NULL;
3356 netif_warn(qdev, ifup, qdev->ndev,
3357 "MSI-X Enable failed, trying MSI.\n");
3358 qdev->intr_count = 1;
3359 qlge_irq_type = MSI_IRQ;
3360 } else if (err == 0) {
3361 set_bit(QL_MSIX_ENABLED, &qdev->flags);
3362 netif_info(qdev, ifup, qdev->ndev,
3363 "MSI-X Enabled, got %d vectors.\n",
3364 qdev->intr_count);
3365 return;
3366 }
3367 }
3368 msi:
3369 qdev->intr_count = 1;
3370 if (qlge_irq_type == MSI_IRQ) {
3371 if (!pci_enable_msi(qdev->pdev)) {
3372 set_bit(QL_MSI_ENABLED, &qdev->flags);
3373 netif_info(qdev, ifup, qdev->ndev,
3374 "Running with MSI interrupts.\n");
3375 return;
3376 }
3377 }
3378 qlge_irq_type = LEG_IRQ;
3379 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3380 "Running with legacy interrupts.\n");
3381 }
3382
3383 /* Each vector services 1 RSS ring and and 1 or more
3384 * TX completion rings. This function loops through
3385 * the TX completion rings and assigns the vector that
3386 * will service it. An example would be if there are
3387 * 2 vectors (so 2 RSS rings) and 8 TX completion rings.
3388 * This would mean that vector 0 would service RSS ring 0
3389 * and TX completion rings 0,1,2 and 3. Vector 1 would
3390 * service RSS ring 1 and TX completion rings 4,5,6 and 7.
3391 */
3392 static void ql_set_tx_vect(struct ql_adapter *qdev)
3393 {
3394 int i, j, vect;
3395 u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
3396
3397 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3398 /* Assign irq vectors to TX rx_rings.*/
3399 for (vect = 0, j = 0, i = qdev->rss_ring_count;
3400 i < qdev->rx_ring_count; i++) {
3401 if (j == tx_rings_per_vector) {
3402 vect++;
3403 j = 0;
3404 }
3405 qdev->rx_ring[i].irq = vect;
3406 j++;
3407 }
3408 } else {
3409 /* For single vector all rings have an irq
3410 * of zero.
3411 */
3412 for (i = 0; i < qdev->rx_ring_count; i++)
3413 qdev->rx_ring[i].irq = 0;
3414 }
3415 }
3416
3417 /* Set the interrupt mask for this vector. Each vector
3418 * will service 1 RSS ring and 1 or more TX completion
3419 * rings. This function sets up a bit mask per vector
3420 * that indicates which rings it services.
3421 */
3422 static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx)
3423 {
3424 int j, vect = ctx->intr;
3425 u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
3426
3427 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3428 /* Add the RSS ring serviced by this vector
3429 * to the mask.
3430 */
3431 ctx->irq_mask = (1 << qdev->rx_ring[vect].cq_id);
3432 /* Add the TX ring(s) serviced by this vector
3433 * to the mask. */
3434 for (j = 0; j < tx_rings_per_vector; j++) {
3435 ctx->irq_mask |=
3436 (1 << qdev->rx_ring[qdev->rss_ring_count +
3437 (vect * tx_rings_per_vector) + j].cq_id);
3438 }
3439 } else {
3440 /* For single vector we just shift each queue's
3441 * ID into the mask.
3442 */
3443 for (j = 0; j < qdev->rx_ring_count; j++)
3444 ctx->irq_mask |= (1 << qdev->rx_ring[j].cq_id);
3445 }
3446 }
3447
3448 /*
3449 * Here we build the intr_context structures based on
3450 * our rx_ring count and intr vector count.
3451 * The intr_context structure is used to hook each vector
3452 * to possibly different handlers.
3453 */
3454 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
3455 {
3456 int i = 0;
3457 struct intr_context *intr_context = &qdev->intr_context[0];
3458
3459 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3460 /* Each rx_ring has it's
3461 * own intr_context since we have separate
3462 * vectors for each queue.
3463 */
3464 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3465 qdev->rx_ring[i].irq = i;
3466 intr_context->intr = i;
3467 intr_context->qdev = qdev;
3468 /* Set up this vector's bit-mask that indicates
3469 * which queues it services.
3470 */
3471 ql_set_irq_mask(qdev, intr_context);
3472 /*
3473 * We set up each vectors enable/disable/read bits so
3474 * there's no bit/mask calculations in the critical path.
3475 */
3476 intr_context->intr_en_mask =
3477 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3478 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
3479 | i;
3480 intr_context->intr_dis_mask =
3481 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3482 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
3483 INTR_EN_IHD | i;
3484 intr_context->intr_read_mask =
3485 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3486 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
3487 i;
3488 if (i == 0) {
3489 /* The first vector/queue handles
3490 * broadcast/multicast, fatal errors,
3491 * and firmware events. This in addition
3492 * to normal inbound NAPI processing.
3493 */
3494 intr_context->handler = qlge_isr;
3495 sprintf(intr_context->name, "%s-rx-%d",
3496 qdev->ndev->name, i);
3497 } else {
3498 /*
3499 * Inbound queues handle unicast frames only.
3500 */
3501 intr_context->handler = qlge_msix_rx_isr;
3502 sprintf(intr_context->name, "%s-rx-%d",
3503 qdev->ndev->name, i);
3504 }
3505 }
3506 } else {
3507 /*
3508 * All rx_rings use the same intr_context since
3509 * there is only one vector.
3510 */
3511 intr_context->intr = 0;
3512 intr_context->qdev = qdev;
3513 /*
3514 * We set up each vectors enable/disable/read bits so
3515 * there's no bit/mask calculations in the critical path.
3516 */
3517 intr_context->intr_en_mask =
3518 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
3519 intr_context->intr_dis_mask =
3520 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3521 INTR_EN_TYPE_DISABLE;
3522 intr_context->intr_read_mask =
3523 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
3524 /*
3525 * Single interrupt means one handler for all rings.
3526 */
3527 intr_context->handler = qlge_isr;
3528 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
3529 /* Set up this vector's bit-mask that indicates
3530 * which queues it services. In this case there is
3531 * a single vector so it will service all RSS and
3532 * TX completion rings.
3533 */
3534 ql_set_irq_mask(qdev, intr_context);
3535 }
3536 /* Tell the TX completion rings which MSIx vector
3537 * they will be using.
3538 */
3539 ql_set_tx_vect(qdev);
3540 }
3541
3542 static void ql_free_irq(struct ql_adapter *qdev)
3543 {
3544 int i;
3545 struct intr_context *intr_context = &qdev->intr_context[0];
3546
3547 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3548 if (intr_context->hooked) {
3549 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3550 free_irq(qdev->msi_x_entry[i].vector,
3551 &qdev->rx_ring[i]);
3552 } else {
3553 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
3554 }
3555 }
3556 }
3557 ql_disable_msix(qdev);
3558 }
3559
3560 static int ql_request_irq(struct ql_adapter *qdev)
3561 {
3562 int i;
3563 int status = 0;
3564 struct pci_dev *pdev = qdev->pdev;
3565 struct intr_context *intr_context = &qdev->intr_context[0];
3566
3567 ql_resolve_queues_to_irqs(qdev);
3568
3569 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3570 atomic_set(&intr_context->irq_cnt, 0);
3571 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3572 status = request_irq(qdev->msi_x_entry[i].vector,
3573 intr_context->handler,
3574 0,
3575 intr_context->name,
3576 &qdev->rx_ring[i]);
3577 if (status) {
3578 netif_err(qdev, ifup, qdev->ndev,
3579 "Failed request for MSIX interrupt %d.\n",
3580 i);
3581 goto err_irq;
3582 }
3583 } else {
3584 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3585 "trying msi or legacy interrupts.\n");
3586 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3587 "%s: irq = %d.\n", __func__, pdev->irq);
3588 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3589 "%s: context->name = %s.\n", __func__,
3590 intr_context->name);
3591 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3592 "%s: dev_id = 0x%p.\n", __func__,
3593 &qdev->rx_ring[0]);
3594 status =
3595 request_irq(pdev->irq, qlge_isr,
3596 test_bit(QL_MSI_ENABLED,
3597 &qdev->
3598 flags) ? 0 : IRQF_SHARED,
3599 intr_context->name, &qdev->rx_ring[0]);
3600 if (status)
3601 goto err_irq;
3602
3603 netif_err(qdev, ifup, qdev->ndev,
3604 "Hooked intr %d, queue type %s, with name %s.\n",
3605 i,
3606 qdev->rx_ring[0].type == DEFAULT_Q ?
3607 "DEFAULT_Q" :
3608 qdev->rx_ring[0].type == TX_Q ? "TX_Q" :
3609 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
3610 intr_context->name);
3611 }
3612 intr_context->hooked = 1;
3613 }
3614 return status;
3615 err_irq:
3616 netif_err(qdev, ifup, qdev->ndev, "Failed to get the interrupts!!!/n");
3617 ql_free_irq(qdev);
3618 return status;
3619 }
3620
3621 static int ql_start_rss(struct ql_adapter *qdev)
3622 {
3623 static const u8 init_hash_seed[] = {
3624 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
3625 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,
3626 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,
3627 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,
3628 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa
3629 };
3630 struct ricb *ricb = &qdev->ricb;
3631 int status = 0;
3632 int i;
3633 u8 *hash_id = (u8 *) ricb->hash_cq_id;
3634
3635 memset((void *)ricb, 0, sizeof(*ricb));
3636
3637 ricb->base_cq = RSS_L4K;
3638 ricb->flags =
3639 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RT4 | RSS_RT6);
3640 ricb->mask = cpu_to_le16((u16)(0x3ff));
3641
3642 /*
3643 * Fill out the Indirection Table.
3644 */
3645 for (i = 0; i < 1024; i++)
3646 hash_id[i] = (i & (qdev->rss_ring_count - 1));
3647
3648 memcpy((void *)&ricb->ipv6_hash_key[0], init_hash_seed, 40);
3649 memcpy((void *)&ricb->ipv4_hash_key[0], init_hash_seed, 16);
3650
3651 status = ql_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0);
3652 if (status) {
3653 netif_err(qdev, ifup, qdev->ndev, "Failed to load RICB.\n");
3654 return status;
3655 }
3656 return status;
3657 }
3658
3659 static int ql_clear_routing_entries(struct ql_adapter *qdev)
3660 {
3661 int i, status = 0;
3662
3663 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3664 if (status)
3665 return status;
3666 /* Clear all the entries in the routing table. */
3667 for (i = 0; i < 16; i++) {
3668 status = ql_set_routing_reg(qdev, i, 0, 0);
3669 if (status) {
3670 netif_err(qdev, ifup, qdev->ndev,
3671 "Failed to init routing register for CAM packets.\n");
3672 break;
3673 }
3674 }
3675 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3676 return status;
3677 }
3678
3679 /* Initialize the frame-to-queue routing. */
3680 static int ql_route_initialize(struct ql_adapter *qdev)
3681 {
3682 int status = 0;
3683
3684 /* Clear all the entries in the routing table. */
3685 status = ql_clear_routing_entries(qdev);
3686 if (status)
3687 return status;
3688
3689 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3690 if (status)
3691 return status;
3692
3693 status = ql_set_routing_reg(qdev, RT_IDX_IP_CSUM_ERR_SLOT,
3694 RT_IDX_IP_CSUM_ERR, 1);
3695 if (status) {
3696 netif_err(qdev, ifup, qdev->ndev,
3697 "Failed to init routing register "
3698 "for IP CSUM error packets.\n");
3699 goto exit;
3700 }
3701 status = ql_set_routing_reg(qdev, RT_IDX_TCP_UDP_CSUM_ERR_SLOT,
3702 RT_IDX_TU_CSUM_ERR, 1);
3703 if (status) {
3704 netif_err(qdev, ifup, qdev->ndev,
3705 "Failed to init routing register "
3706 "for TCP/UDP CSUM error packets.\n");
3707 goto exit;
3708 }
3709 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3710 if (status) {
3711 netif_err(qdev, ifup, qdev->ndev,
3712 "Failed to init routing register for broadcast packets.\n");
3713 goto exit;
3714 }
3715 /* If we have more than one inbound queue, then turn on RSS in the
3716 * routing block.
3717 */
3718 if (qdev->rss_ring_count > 1) {
3719 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3720 RT_IDX_RSS_MATCH, 1);
3721 if (status) {
3722 netif_err(qdev, ifup, qdev->ndev,
3723 "Failed to init routing register for MATCH RSS packets.\n");
3724 goto exit;
3725 }
3726 }
3727
3728 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3729 RT_IDX_CAM_HIT, 1);
3730 if (status)
3731 netif_err(qdev, ifup, qdev->ndev,
3732 "Failed to init routing register for CAM packets.\n");
3733 exit:
3734 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3735 return status;
3736 }
3737
3738 int ql_cam_route_initialize(struct ql_adapter *qdev)
3739 {
3740 int status, set;
3741
3742 /* If check if the link is up and use to
3743 * determine if we are setting or clearing
3744 * the MAC address in the CAM.
3745 */
3746 set = ql_read32(qdev, STS);
3747 set &= qdev->port_link_up;
3748 status = ql_set_mac_addr(qdev, set);
3749 if (status) {
3750 netif_err(qdev, ifup, qdev->ndev, "Failed to init mac address.\n");
3751 return status;
3752 }
3753
3754 status = ql_route_initialize(qdev);
3755 if (status)
3756 netif_err(qdev, ifup, qdev->ndev, "Failed to init routing table.\n");
3757
3758 return status;
3759 }
3760
3761 static int ql_adapter_initialize(struct ql_adapter *qdev)
3762 {
3763 u32 value, mask;
3764 int i;
3765 int status = 0;
3766
3767 /*
3768 * Set up the System register to halt on errors.
3769 */
3770 value = SYS_EFE | SYS_FAE;
3771 mask = value << 16;
3772 ql_write32(qdev, SYS, mask | value);
3773
3774 /* Set the default queue, and VLAN behavior. */
3775 value = NIC_RCV_CFG_DFQ;
3776 mask = NIC_RCV_CFG_DFQ_MASK;
3777 if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3778 value |= NIC_RCV_CFG_RV;
3779 mask |= (NIC_RCV_CFG_RV << 16);
3780 }
3781 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3782
3783 /* Set the MPI interrupt to enabled. */
3784 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3785
3786 /* Enable the function, set pagesize, enable error checking. */
3787 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3788 FSC_EC | FSC_VM_PAGE_4K;
3789 value |= SPLT_SETTING;
3790
3791 /* Set/clear header splitting. */
3792 mask = FSC_VM_PAGESIZE_MASK |
3793 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3794 ql_write32(qdev, FSC, mask | value);
3795
3796 ql_write32(qdev, SPLT_HDR, SPLT_LEN);
3797
3798 /* Set RX packet routing to use port/pci function on which the
3799 * packet arrived on in addition to usual frame routing.
3800 * This is helpful on bonding where both interfaces can have
3801 * the same MAC address.
3802 */
3803 ql_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ);
3804 /* Reroute all packets to our Interface.
3805 * They may have been routed to MPI firmware
3806 * due to WOL.
3807 */
3808 value = ql_read32(qdev, MGMT_RCV_CFG);
3809 value &= ~MGMT_RCV_CFG_RM;
3810 mask = 0xffff0000;
3811
3812 /* Sticky reg needs clearing due to WOL. */
3813 ql_write32(qdev, MGMT_RCV_CFG, mask);
3814 ql_write32(qdev, MGMT_RCV_CFG, mask | value);
3815
3816 /* Default WOL is enable on Mezz cards */
3817 if (qdev->pdev->subsystem_device == 0x0068 ||
3818 qdev->pdev->subsystem_device == 0x0180)
3819 qdev->wol = WAKE_MAGIC;
3820
3821 /* Start up the rx queues. */
3822 for (i = 0; i < qdev->rx_ring_count; i++) {
3823 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3824 if (status) {
3825 netif_err(qdev, ifup, qdev->ndev,
3826 "Failed to start rx ring[%d].\n", i);
3827 return status;
3828 }
3829 }
3830
3831 /* If there is more than one inbound completion queue
3832 * then download a RICB to configure RSS.
3833 */
3834 if (qdev->rss_ring_count > 1) {
3835 status = ql_start_rss(qdev);
3836 if (status) {
3837 netif_err(qdev, ifup, qdev->ndev, "Failed to start RSS.\n");
3838 return status;
3839 }
3840 }
3841
3842 /* Start up the tx queues. */
3843 for (i = 0; i < qdev->tx_ring_count; i++) {
3844 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3845 if (status) {
3846 netif_err(qdev, ifup, qdev->ndev,
3847 "Failed to start tx ring[%d].\n", i);
3848 return status;
3849 }
3850 }
3851
3852 /* Initialize the port and set the max framesize. */
3853 status = qdev->nic_ops->port_initialize(qdev);
3854 if (status)
3855 netif_err(qdev, ifup, qdev->ndev, "Failed to start port.\n");
3856
3857 /* Set up the MAC address and frame routing filter. */
3858 status = ql_cam_route_initialize(qdev);
3859 if (status) {
3860 netif_err(qdev, ifup, qdev->ndev,
3861 "Failed to init CAM/Routing tables.\n");
3862 return status;
3863 }
3864
3865 /* Start NAPI for the RSS queues. */
3866 for (i = 0; i < qdev->rss_ring_count; i++)
3867 napi_enable(&qdev->rx_ring[i].napi);
3868
3869 return status;
3870 }
3871
3872 /* Issue soft reset to chip. */
3873 static int ql_adapter_reset(struct ql_adapter *qdev)
3874 {
3875 u32 value;
3876 int status = 0;
3877 unsigned long end_jiffies;
3878
3879 /* Clear all the entries in the routing table. */
3880 status = ql_clear_routing_entries(qdev);
3881 if (status) {
3882 netif_err(qdev, ifup, qdev->ndev, "Failed to clear routing bits.\n");
3883 return status;
3884 }
3885
3886 end_jiffies = jiffies +
3887 max((unsigned long)1, usecs_to_jiffies(30));
3888
3889 /* Check if bit is set then skip the mailbox command and
3890 * clear the bit, else we are in normal reset process.
3891 */
3892 if (!test_bit(QL_ASIC_RECOVERY, &qdev->flags)) {
3893 /* Stop management traffic. */
3894 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP);
3895
3896 /* Wait for the NIC and MGMNT FIFOs to empty. */
3897 ql_wait_fifo_empty(qdev);
3898 } else
3899 clear_bit(QL_ASIC_RECOVERY, &qdev->flags);
3900
3901 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3902
3903 do {
3904 value = ql_read32(qdev, RST_FO);
3905 if ((value & RST_FO_FR) == 0)
3906 break;
3907 cpu_relax();
3908 } while (time_before(jiffies, end_jiffies));
3909
3910 if (value & RST_FO_FR) {
3911 netif_err(qdev, ifdown, qdev->ndev,
3912 "ETIMEDOUT!!! errored out of resetting the chip!\n");
3913 status = -ETIMEDOUT;
3914 }
3915
3916 /* Resume management traffic. */
3917 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_RESUME);
3918 return status;
3919 }
3920
3921 static void ql_display_dev_info(struct net_device *ndev)
3922 {
3923 struct ql_adapter *qdev = netdev_priv(ndev);
3924
3925 netif_info(qdev, probe, qdev->ndev,
3926 "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, "
3927 "XG Roll = %d, XG Rev = %d.\n",
3928 qdev->func,
3929 qdev->port,
3930 qdev->chip_rev_id & 0x0000000f,
3931 qdev->chip_rev_id >> 4 & 0x0000000f,
3932 qdev->chip_rev_id >> 8 & 0x0000000f,
3933 qdev->chip_rev_id >> 12 & 0x0000000f);
3934 netif_info(qdev, probe, qdev->ndev,
3935 "MAC address %pM\n", ndev->dev_addr);
3936 }
3937
3938 static int ql_wol(struct ql_adapter *qdev)
3939 {
3940 int status = 0;
3941 u32 wol = MB_WOL_DISABLE;
3942
3943 /* The CAM is still intact after a reset, but if we
3944 * are doing WOL, then we may need to program the
3945 * routing regs. We would also need to issue the mailbox
3946 * commands to instruct the MPI what to do per the ethtool
3947 * settings.
3948 */
3949
3950 if (qdev->wol & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY | WAKE_UCAST |
3951 WAKE_MCAST | WAKE_BCAST)) {
3952 netif_err(qdev, ifdown, qdev->ndev,
3953 "Unsupported WOL parameter. qdev->wol = 0x%x.\n",
3954 qdev->wol);
3955 return -EINVAL;
3956 }
3957
3958 if (qdev->wol & WAKE_MAGIC) {
3959 status = ql_mb_wol_set_magic(qdev, 1);
3960 if (status) {
3961 netif_err(qdev, ifdown, qdev->ndev,
3962 "Failed to set magic packet on %s.\n",
3963 qdev->ndev->name);
3964 return status;
3965 } else
3966 netif_info(qdev, drv, qdev->ndev,
3967 "Enabled magic packet successfully on %s.\n",
3968 qdev->ndev->name);
3969
3970 wol |= MB_WOL_MAGIC_PKT;
3971 }
3972
3973 if (qdev->wol) {
3974 wol |= MB_WOL_MODE_ON;
3975 status = ql_mb_wol_mode(qdev, wol);
3976 netif_err(qdev, drv, qdev->ndev,
3977 "WOL %s (wol code 0x%x) on %s\n",
3978 (status == 0) ? "Successfully set" : "Failed",
3979 wol, qdev->ndev->name);
3980 }
3981
3982 return status;
3983 }
3984
3985 static void ql_cancel_all_work_sync(struct ql_adapter *qdev)
3986 {
3987
3988 /* Don't kill the reset worker thread if we
3989 * are in the process of recovery.
3990 */
3991 if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3992 cancel_delayed_work_sync(&qdev->asic_reset_work);
3993 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3994 cancel_delayed_work_sync(&qdev->mpi_work);
3995 cancel_delayed_work_sync(&qdev->mpi_idc_work);
3996 cancel_delayed_work_sync(&qdev->mpi_core_to_log);
3997 cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3998 }
3999
4000 static int ql_adapter_down(struct ql_adapter *qdev)
4001 {
4002 int i, status = 0;
4003
4004 ql_link_off(qdev);
4005
4006 ql_cancel_all_work_sync(qdev);
4007
4008 for (i = 0; i < qdev->rss_ring_count; i++)
4009 napi_disable(&qdev->rx_ring[i].napi);
4010
4011 clear_bit(QL_ADAPTER_UP, &qdev->flags);
4012
4013 ql_disable_interrupts(qdev);
4014
4015 ql_tx_ring_clean(qdev);
4016
4017 /* Call netif_napi_del() from common point.
4018 */
4019 for (i = 0; i < qdev->rss_ring_count; i++)
4020 netif_napi_del(&qdev->rx_ring[i].napi);
4021
4022 status = ql_adapter_reset(qdev);
4023 if (status)
4024 netif_err(qdev, ifdown, qdev->ndev, "reset(func #%d) FAILED!\n",
4025 qdev->func);
4026 ql_free_rx_buffers(qdev);
4027
4028 return status;
4029 }
4030
4031 static int ql_adapter_up(struct ql_adapter *qdev)
4032 {
4033 int err = 0;
4034
4035 err = ql_adapter_initialize(qdev);
4036 if (err) {
4037 netif_info(qdev, ifup, qdev->ndev, "Unable to initialize adapter.\n");
4038 goto err_init;
4039 }
4040 set_bit(QL_ADAPTER_UP, &qdev->flags);
4041 ql_alloc_rx_buffers(qdev);
4042 /* If the port is initialized and the
4043 * link is up the turn on the carrier.
4044 */
4045 if ((ql_read32(qdev, STS) & qdev->port_init) &&
4046 (ql_read32(qdev, STS) & qdev->port_link_up))
4047 ql_link_on(qdev);
4048 /* Restore rx mode. */
4049 clear_bit(QL_ALLMULTI, &qdev->flags);
4050 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4051 qlge_set_multicast_list(qdev->ndev);
4052
4053 /* Restore vlan setting. */
4054 qlge_restore_vlan(qdev);
4055
4056 ql_enable_interrupts(qdev);
4057 ql_enable_all_completion_interrupts(qdev);
4058 netif_tx_start_all_queues(qdev->ndev);
4059
4060 return 0;
4061 err_init:
4062 ql_adapter_reset(qdev);
4063 return err;
4064 }
4065
4066 static void ql_release_adapter_resources(struct ql_adapter *qdev)
4067 {
4068 ql_free_mem_resources(qdev);
4069 ql_free_irq(qdev);
4070 }
4071
4072 static int ql_get_adapter_resources(struct ql_adapter *qdev)
4073 {
4074 int status = 0;
4075
4076 if (ql_alloc_mem_resources(qdev)) {
4077 netif_err(qdev, ifup, qdev->ndev, "Unable to allocate memory.\n");
4078 return -ENOMEM;
4079 }
4080 status = ql_request_irq(qdev);
4081 return status;
4082 }
4083
4084 static int qlge_close(struct net_device *ndev)
4085 {
4086 struct ql_adapter *qdev = netdev_priv(ndev);
4087
4088 /* If we hit pci_channel_io_perm_failure
4089 * failure condition, then we already
4090 * brought the adapter down.
4091 */
4092 if (test_bit(QL_EEH_FATAL, &qdev->flags)) {
4093 netif_err(qdev, drv, qdev->ndev, "EEH fatal did unload.\n");
4094 clear_bit(QL_EEH_FATAL, &qdev->flags);
4095 return 0;
4096 }
4097
4098 /*
4099 * Wait for device to recover from a reset.
4100 * (Rarely happens, but possible.)
4101 */
4102 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
4103 msleep(1);
4104 ql_adapter_down(qdev);
4105 ql_release_adapter_resources(qdev);
4106 return 0;
4107 }
4108
4109 static int ql_configure_rings(struct ql_adapter *qdev)
4110 {
4111 int i;
4112 struct rx_ring *rx_ring;
4113 struct tx_ring *tx_ring;
4114 int cpu_cnt = min(MAX_CPUS, (int)num_online_cpus());
4115 unsigned int lbq_buf_len = (qdev->ndev->mtu > 1500) ?
4116 LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
4117
4118 qdev->lbq_buf_order = get_order(lbq_buf_len);
4119
4120 /* In a perfect world we have one RSS ring for each CPU
4121 * and each has it's own vector. To do that we ask for
4122 * cpu_cnt vectors. ql_enable_msix() will adjust the
4123 * vector count to what we actually get. We then
4124 * allocate an RSS ring for each.
4125 * Essentially, we are doing min(cpu_count, msix_vector_count).
4126 */
4127 qdev->intr_count = cpu_cnt;
4128 ql_enable_msix(qdev);
4129 /* Adjust the RSS ring count to the actual vector count. */
4130 qdev->rss_ring_count = qdev->intr_count;
4131 qdev->tx_ring_count = cpu_cnt;
4132 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count;
4133
4134 for (i = 0; i < qdev->tx_ring_count; i++) {
4135 tx_ring = &qdev->tx_ring[i];
4136 memset((void *)tx_ring, 0, sizeof(*tx_ring));
4137 tx_ring->qdev = qdev;
4138 tx_ring->wq_id = i;
4139 tx_ring->wq_len = qdev->tx_ring_size;
4140 tx_ring->wq_size =
4141 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
4142
4143 /*
4144 * The completion queue ID for the tx rings start
4145 * immediately after the rss rings.
4146 */
4147 tx_ring->cq_id = qdev->rss_ring_count + i;
4148 }
4149
4150 for (i = 0; i < qdev->rx_ring_count; i++) {
4151 rx_ring = &qdev->rx_ring[i];
4152 memset((void *)rx_ring, 0, sizeof(*rx_ring));
4153 rx_ring->qdev = qdev;
4154 rx_ring->cq_id = i;
4155 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
4156 if (i < qdev->rss_ring_count) {
4157 /*
4158 * Inbound (RSS) queues.
4159 */
4160 rx_ring->cq_len = qdev->rx_ring_size;
4161 rx_ring->cq_size =
4162 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
4163 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
4164 rx_ring->lbq_size =
4165 rx_ring->lbq_len * sizeof(__le64);
4166 rx_ring->lbq_buf_size = (u16)lbq_buf_len;
4167 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
4168 rx_ring->sbq_size =
4169 rx_ring->sbq_len * sizeof(__le64);
4170 rx_ring->sbq_buf_size = SMALL_BUF_MAP_SIZE;
4171 rx_ring->type = RX_Q;
4172 } else {
4173 /*
4174 * Outbound queue handles outbound completions only.
4175 */
4176 /* outbound cq is same size as tx_ring it services. */
4177 rx_ring->cq_len = qdev->tx_ring_size;
4178 rx_ring->cq_size =
4179 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
4180 rx_ring->lbq_len = 0;
4181 rx_ring->lbq_size = 0;
4182 rx_ring->lbq_buf_size = 0;
4183 rx_ring->sbq_len = 0;
4184 rx_ring->sbq_size = 0;
4185 rx_ring->sbq_buf_size = 0;
4186 rx_ring->type = TX_Q;
4187 }
4188 }
4189 return 0;
4190 }
4191
4192 static int qlge_open(struct net_device *ndev)
4193 {
4194 int err = 0;
4195 struct ql_adapter *qdev = netdev_priv(ndev);
4196
4197 err = ql_adapter_reset(qdev);
4198 if (err)
4199 return err;
4200
4201 err = ql_configure_rings(qdev);
4202 if (err)
4203 return err;
4204
4205 err = ql_get_adapter_resources(qdev);
4206 if (err)
4207 goto error_up;
4208
4209 err = ql_adapter_up(qdev);
4210 if (err)
4211 goto error_up;
4212
4213 return err;
4214
4215 error_up:
4216 ql_release_adapter_resources(qdev);
4217 return err;
4218 }
4219
4220 static int ql_change_rx_buffers(struct ql_adapter *qdev)
4221 {
4222 struct rx_ring *rx_ring;
4223 int i, status;
4224 u32 lbq_buf_len;
4225
4226 /* Wait for an outstanding reset to complete. */
4227 if (!test_bit(QL_ADAPTER_UP, &qdev->flags)) {
4228 int i = 3;
4229 while (i-- && !test_bit(QL_ADAPTER_UP, &qdev->flags)) {
4230 netif_err(qdev, ifup, qdev->ndev,
4231 "Waiting for adapter UP...\n");
4232 ssleep(1);
4233 }
4234
4235 if (!i) {
4236 netif_err(qdev, ifup, qdev->ndev,
4237 "Timed out waiting for adapter UP\n");
4238 return -ETIMEDOUT;
4239 }
4240 }
4241
4242 status = ql_adapter_down(qdev);
4243 if (status)
4244 goto error;
4245
4246 /* Get the new rx buffer size. */
4247 lbq_buf_len = (qdev->ndev->mtu > 1500) ?
4248 LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
4249 qdev->lbq_buf_order = get_order(lbq_buf_len);
4250
4251 for (i = 0; i < qdev->rss_ring_count; i++) {
4252 rx_ring = &qdev->rx_ring[i];
4253 /* Set the new size. */
4254 rx_ring->lbq_buf_size = lbq_buf_len;
4255 }
4256
4257 status = ql_adapter_up(qdev);
4258 if (status)
4259 goto error;
4260
4261 return status;
4262 error:
4263 netif_alert(qdev, ifup, qdev->ndev,
4264 "Driver up/down cycle failed, closing device.\n");
4265 set_bit(QL_ADAPTER_UP, &qdev->flags);
4266 dev_close(qdev->ndev);
4267 return status;
4268 }
4269
4270 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
4271 {
4272 struct ql_adapter *qdev = netdev_priv(ndev);
4273 int status;
4274
4275 if (ndev->mtu == 1500 && new_mtu == 9000) {
4276 netif_err(qdev, ifup, qdev->ndev, "Changing to jumbo MTU.\n");
4277 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
4278 netif_err(qdev, ifup, qdev->ndev, "Changing to normal MTU.\n");
4279 } else
4280 return -EINVAL;
4281
4282 queue_delayed_work(qdev->workqueue,
4283 &qdev->mpi_port_cfg_work, 3*HZ);
4284
4285 ndev->mtu = new_mtu;
4286
4287 if (!netif_running(qdev->ndev)) {
4288 return 0;
4289 }
4290
4291 status = ql_change_rx_buffers(qdev);
4292 if (status) {
4293 netif_err(qdev, ifup, qdev->ndev,
4294 "Changing MTU failed.\n");
4295 }
4296
4297 return status;
4298 }
4299
4300 static struct net_device_stats *qlge_get_stats(struct net_device
4301 *ndev)
4302 {
4303 struct ql_adapter *qdev = netdev_priv(ndev);
4304 struct rx_ring *rx_ring = &qdev->rx_ring[0];
4305 struct tx_ring *tx_ring = &qdev->tx_ring[0];
4306 unsigned long pkts, mcast, dropped, errors, bytes;
4307 int i;
4308
4309 /* Get RX stats. */
4310 pkts = mcast = dropped = errors = bytes = 0;
4311 for (i = 0; i < qdev->rss_ring_count; i++, rx_ring++) {
4312 pkts += rx_ring->rx_packets;
4313 bytes += rx_ring->rx_bytes;
4314 dropped += rx_ring->rx_dropped;
4315 errors += rx_ring->rx_errors;
4316 mcast += rx_ring->rx_multicast;
4317 }
4318 ndev->stats.rx_packets = pkts;
4319 ndev->stats.rx_bytes = bytes;
4320 ndev->stats.rx_dropped = dropped;
4321 ndev->stats.rx_errors = errors;
4322 ndev->stats.multicast = mcast;
4323
4324 /* Get TX stats. */
4325 pkts = errors = bytes = 0;
4326 for (i = 0; i < qdev->tx_ring_count; i++, tx_ring++) {
4327 pkts += tx_ring->tx_packets;
4328 bytes += tx_ring->tx_bytes;
4329 errors += tx_ring->tx_errors;
4330 }
4331 ndev->stats.tx_packets = pkts;
4332 ndev->stats.tx_bytes = bytes;
4333 ndev->stats.tx_errors = errors;
4334 return &ndev->stats;
4335 }
4336
4337 static void qlge_set_multicast_list(struct net_device *ndev)
4338 {
4339 struct ql_adapter *qdev = netdev_priv(ndev);
4340 struct netdev_hw_addr *ha;
4341 int i, status;
4342
4343 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
4344 if (status)
4345 return;
4346 /*
4347 * Set or clear promiscuous mode if a
4348 * transition is taking place.
4349 */
4350 if (ndev->flags & IFF_PROMISC) {
4351 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
4352 if (ql_set_routing_reg
4353 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
4354 netif_err(qdev, hw, qdev->ndev,
4355 "Failed to set promiscuous mode.\n");
4356 } else {
4357 set_bit(QL_PROMISCUOUS, &qdev->flags);
4358 }
4359 }
4360 } else {
4361 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
4362 if (ql_set_routing_reg
4363 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
4364 netif_err(qdev, hw, qdev->ndev,
4365 "Failed to clear promiscuous mode.\n");
4366 } else {
4367 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4368 }
4369 }
4370 }
4371
4372 /*
4373 * Set or clear all multicast mode if a
4374 * transition is taking place.
4375 */
4376 if ((ndev->flags & IFF_ALLMULTI) ||
4377 (netdev_mc_count(ndev) > MAX_MULTICAST_ENTRIES)) {
4378 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
4379 if (ql_set_routing_reg
4380 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
4381 netif_err(qdev, hw, qdev->ndev,
4382 "Failed to set all-multi mode.\n");
4383 } else {
4384 set_bit(QL_ALLMULTI, &qdev->flags);
4385 }
4386 }
4387 } else {
4388 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
4389 if (ql_set_routing_reg
4390 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
4391 netif_err(qdev, hw, qdev->ndev,
4392 "Failed to clear all-multi mode.\n");
4393 } else {
4394 clear_bit(QL_ALLMULTI, &qdev->flags);
4395 }
4396 }
4397 }
4398
4399 if (!netdev_mc_empty(ndev)) {
4400 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
4401 if (status)
4402 goto exit;
4403 i = 0;
4404 netdev_for_each_mc_addr(ha, ndev) {
4405 if (ql_set_mac_addr_reg(qdev, (u8 *) ha->addr,
4406 MAC_ADDR_TYPE_MULTI_MAC, i)) {
4407 netif_err(qdev, hw, qdev->ndev,
4408 "Failed to loadmulticast address.\n");
4409 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4410 goto exit;
4411 }
4412 i++;
4413 }
4414 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4415 if (ql_set_routing_reg
4416 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
4417 netif_err(qdev, hw, qdev->ndev,
4418 "Failed to set multicast match mode.\n");
4419 } else {
4420 set_bit(QL_ALLMULTI, &qdev->flags);
4421 }
4422 }
4423 exit:
4424 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
4425 }
4426
4427 static int qlge_set_mac_address(struct net_device *ndev, void *p)
4428 {
4429 struct ql_adapter *qdev = netdev_priv(ndev);
4430 struct sockaddr *addr = p;
4431 int status;
4432
4433 if (!is_valid_ether_addr(addr->sa_data))
4434 return -EADDRNOTAVAIL;
4435 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
4436 /* Update local copy of current mac address. */
4437 memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len);
4438
4439 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
4440 if (status)
4441 return status;
4442 status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
4443 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
4444 if (status)
4445 netif_err(qdev, hw, qdev->ndev, "Failed to load MAC address.\n");
4446 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4447 return status;
4448 }
4449
4450 static void qlge_tx_timeout(struct net_device *ndev)
4451 {
4452 struct ql_adapter *qdev = netdev_priv(ndev);
4453 ql_queue_asic_error(qdev);
4454 }
4455
4456 static void ql_asic_reset_work(struct work_struct *work)
4457 {
4458 struct ql_adapter *qdev =
4459 container_of(work, struct ql_adapter, asic_reset_work.work);
4460 int status;
4461 rtnl_lock();
4462 status = ql_adapter_down(qdev);
4463 if (status)
4464 goto error;
4465
4466 status = ql_adapter_up(qdev);
4467 if (status)
4468 goto error;
4469
4470 /* Restore rx mode. */
4471 clear_bit(QL_ALLMULTI, &qdev->flags);
4472 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4473 qlge_set_multicast_list(qdev->ndev);
4474
4475 rtnl_unlock();
4476 return;
4477 error:
4478 netif_alert(qdev, ifup, qdev->ndev,
4479 "Driver up/down cycle failed, closing device\n");
4480
4481 set_bit(QL_ADAPTER_UP, &qdev->flags);
4482 dev_close(qdev->ndev);
4483 rtnl_unlock();
4484 }
4485
4486 static const struct nic_operations qla8012_nic_ops = {
4487 .get_flash = ql_get_8012_flash_params,
4488 .port_initialize = ql_8012_port_initialize,
4489 };
4490
4491 static const struct nic_operations qla8000_nic_ops = {
4492 .get_flash = ql_get_8000_flash_params,
4493 .port_initialize = ql_8000_port_initialize,
4494 };
4495
4496 /* Find the pcie function number for the other NIC
4497 * on this chip. Since both NIC functions share a
4498 * common firmware we have the lowest enabled function
4499 * do any common work. Examples would be resetting
4500 * after a fatal firmware error, or doing a firmware
4501 * coredump.
4502 */
4503 static int ql_get_alt_pcie_func(struct ql_adapter *qdev)
4504 {
4505 int status = 0;
4506 u32 temp;
4507 u32 nic_func1, nic_func2;
4508
4509 status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG,
4510 &temp);
4511 if (status)
4512 return status;
4513
4514 nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) &
4515 MPI_TEST_NIC_FUNC_MASK);
4516 nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) &
4517 MPI_TEST_NIC_FUNC_MASK);
4518
4519 if (qdev->func == nic_func1)
4520 qdev->alt_func = nic_func2;
4521 else if (qdev->func == nic_func2)
4522 qdev->alt_func = nic_func1;
4523 else
4524 status = -EIO;
4525
4526 return status;
4527 }
4528
4529 static int ql_get_board_info(struct ql_adapter *qdev)
4530 {
4531 int status;
4532 qdev->func =
4533 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
4534 if (qdev->func > 3)
4535 return -EIO;
4536
4537 status = ql_get_alt_pcie_func(qdev);
4538 if (status)
4539 return status;
4540
4541 qdev->port = (qdev->func < qdev->alt_func) ? 0 : 1;
4542 if (qdev->port) {
4543 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
4544 qdev->port_link_up = STS_PL1;
4545 qdev->port_init = STS_PI1;
4546 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
4547 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
4548 } else {
4549 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
4550 qdev->port_link_up = STS_PL0;
4551 qdev->port_init = STS_PI0;
4552 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
4553 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
4554 }
4555 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
4556 qdev->device_id = qdev->pdev->device;
4557 if (qdev->device_id == QLGE_DEVICE_ID_8012)
4558 qdev->nic_ops = &qla8012_nic_ops;
4559 else if (qdev->device_id == QLGE_DEVICE_ID_8000)
4560 qdev->nic_ops = &qla8000_nic_ops;
4561 return status;
4562 }
4563
4564 static void ql_release_all(struct pci_dev *pdev)
4565 {
4566 struct net_device *ndev = pci_get_drvdata(pdev);
4567 struct ql_adapter *qdev = netdev_priv(ndev);
4568
4569 if (qdev->workqueue) {
4570 destroy_workqueue(qdev->workqueue);
4571 qdev->workqueue = NULL;
4572 }
4573
4574 if (qdev->reg_base)
4575 iounmap(qdev->reg_base);
4576 if (qdev->doorbell_area)
4577 iounmap(qdev->doorbell_area);
4578 vfree(qdev->mpi_coredump);
4579 pci_release_regions(pdev);
4580 }
4581
4582 static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev,
4583 int cards_found)
4584 {
4585 struct ql_adapter *qdev = netdev_priv(ndev);
4586 int err = 0;
4587
4588 memset((void *)qdev, 0, sizeof(*qdev));
4589 err = pci_enable_device(pdev);
4590 if (err) {
4591 dev_err(&pdev->dev, "PCI device enable failed.\n");
4592 return err;
4593 }
4594
4595 qdev->ndev = ndev;
4596 qdev->pdev = pdev;
4597 pci_set_drvdata(pdev, ndev);
4598
4599 /* Set PCIe read request size */
4600 err = pcie_set_readrq(pdev, 4096);
4601 if (err) {
4602 dev_err(&pdev->dev, "Set readrq failed.\n");
4603 goto err_out1;
4604 }
4605
4606 err = pci_request_regions(pdev, DRV_NAME);
4607 if (err) {
4608 dev_err(&pdev->dev, "PCI region request failed.\n");
4609 return err;
4610 }
4611
4612 pci_set_master(pdev);
4613 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4614 set_bit(QL_DMA64, &qdev->flags);
4615 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4616 } else {
4617 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4618 if (!err)
4619 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4620 }
4621
4622 if (err) {
4623 dev_err(&pdev->dev, "No usable DMA configuration.\n");
4624 goto err_out2;
4625 }
4626
4627 /* Set PCIe reset type for EEH to fundamental. */
4628 pdev->needs_freset = 1;
4629 pci_save_state(pdev);
4630 qdev->reg_base =
4631 ioremap_nocache(pci_resource_start(pdev, 1),
4632 pci_resource_len(pdev, 1));
4633 if (!qdev->reg_base) {
4634 dev_err(&pdev->dev, "Register mapping failed.\n");
4635 err = -ENOMEM;
4636 goto err_out2;
4637 }
4638
4639 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
4640 qdev->doorbell_area =
4641 ioremap_nocache(pci_resource_start(pdev, 3),
4642 pci_resource_len(pdev, 3));
4643 if (!qdev->doorbell_area) {
4644 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
4645 err = -ENOMEM;
4646 goto err_out2;
4647 }
4648
4649 err = ql_get_board_info(qdev);
4650 if (err) {
4651 dev_err(&pdev->dev, "Register access failed.\n");
4652 err = -EIO;
4653 goto err_out2;
4654 }
4655 qdev->msg_enable = netif_msg_init(debug, default_msg);
4656 spin_lock_init(&qdev->hw_lock);
4657 spin_lock_init(&qdev->stats_lock);
4658
4659 if (qlge_mpi_coredump) {
4660 qdev->mpi_coredump =
4661 vmalloc(sizeof(struct ql_mpi_coredump));
4662 if (qdev->mpi_coredump == NULL) {
4663 err = -ENOMEM;
4664 goto err_out2;
4665 }
4666 if (qlge_force_coredump)
4667 set_bit(QL_FRC_COREDUMP, &qdev->flags);
4668 }
4669 /* make sure the EEPROM is good */
4670 err = qdev->nic_ops->get_flash(qdev);
4671 if (err) {
4672 dev_err(&pdev->dev, "Invalid FLASH.\n");
4673 goto err_out2;
4674 }
4675
4676 /* Keep local copy of current mac address. */
4677 memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len);
4678
4679 /* Set up the default ring sizes. */
4680 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
4681 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
4682
4683 /* Set up the coalescing parameters. */
4684 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
4685 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
4686 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
4687 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
4688
4689 /*
4690 * Set up the operating parameters.
4691 */
4692 qdev->workqueue = create_singlethread_workqueue(ndev->name);
4693 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
4694 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
4695 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
4696 INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
4697 INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
4698 INIT_DELAYED_WORK(&qdev->mpi_core_to_log, ql_mpi_core_to_log);
4699 init_completion(&qdev->ide_completion);
4700 mutex_init(&qdev->mpi_mutex);
4701
4702 if (!cards_found) {
4703 dev_info(&pdev->dev, "%s\n", DRV_STRING);
4704 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
4705 DRV_NAME, DRV_VERSION);
4706 }
4707 return 0;
4708 err_out2:
4709 ql_release_all(pdev);
4710 err_out1:
4711 pci_disable_device(pdev);
4712 return err;
4713 }
4714
4715 static const struct net_device_ops qlge_netdev_ops = {
4716 .ndo_open = qlge_open,
4717 .ndo_stop = qlge_close,
4718 .ndo_start_xmit = qlge_send,
4719 .ndo_change_mtu = qlge_change_mtu,
4720 .ndo_get_stats = qlge_get_stats,
4721 .ndo_set_rx_mode = qlge_set_multicast_list,
4722 .ndo_set_mac_address = qlge_set_mac_address,
4723 .ndo_validate_addr = eth_validate_addr,
4724 .ndo_tx_timeout = qlge_tx_timeout,
4725 .ndo_fix_features = qlge_fix_features,
4726 .ndo_set_features = qlge_set_features,
4727 .ndo_vlan_rx_add_vid = qlge_vlan_rx_add_vid,
4728 .ndo_vlan_rx_kill_vid = qlge_vlan_rx_kill_vid,
4729 };
4730
4731 static void ql_timer(unsigned long data)
4732 {
4733 struct ql_adapter *qdev = (struct ql_adapter *)data;
4734 u32 var = 0;
4735
4736 var = ql_read32(qdev, STS);
4737 if (pci_channel_offline(qdev->pdev)) {
4738 netif_err(qdev, ifup, qdev->ndev, "EEH STS = 0x%.08x.\n", var);
4739 return;
4740 }
4741
4742 mod_timer(&qdev->timer, jiffies + (5*HZ));
4743 }
4744
4745 static int qlge_probe(struct pci_dev *pdev,
4746 const struct pci_device_id *pci_entry)
4747 {
4748 struct net_device *ndev = NULL;
4749 struct ql_adapter *qdev = NULL;
4750 static int cards_found = 0;
4751 int err = 0;
4752
4753 ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
4754 min(MAX_CPUS, netif_get_num_default_rss_queues()));
4755 if (!ndev)
4756 return -ENOMEM;
4757
4758 err = ql_init_device(pdev, ndev, cards_found);
4759 if (err < 0) {
4760 free_netdev(ndev);
4761 return err;
4762 }
4763
4764 qdev = netdev_priv(ndev);
4765 SET_NETDEV_DEV(ndev, &pdev->dev);
4766 ndev->hw_features = NETIF_F_SG |
4767 NETIF_F_IP_CSUM |
4768 NETIF_F_TSO |
4769 NETIF_F_TSO_ECN |
4770 NETIF_F_HW_VLAN_CTAG_TX |
4771 NETIF_F_HW_VLAN_CTAG_RX |
4772 NETIF_F_HW_VLAN_CTAG_FILTER |
4773 NETIF_F_RXCSUM;
4774 ndev->features = ndev->hw_features;
4775 ndev->vlan_features = ndev->hw_features;
4776
4777 if (test_bit(QL_DMA64, &qdev->flags))
4778 ndev->features |= NETIF_F_HIGHDMA;
4779
4780 /*
4781 * Set up net_device structure.
4782 */
4783 ndev->tx_queue_len = qdev->tx_ring_size;
4784 ndev->irq = pdev->irq;
4785
4786 ndev->netdev_ops = &qlge_netdev_ops;
4787 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
4788 ndev->watchdog_timeo = 10 * HZ;
4789
4790 err = register_netdev(ndev);
4791 if (err) {
4792 dev_err(&pdev->dev, "net device registration failed.\n");
4793 ql_release_all(pdev);
4794 pci_disable_device(pdev);
4795 free_netdev(ndev);
4796 return err;
4797 }
4798 /* Start up the timer to trigger EEH if
4799 * the bus goes dead
4800 */
4801 init_timer_deferrable(&qdev->timer);
4802 qdev->timer.data = (unsigned long)qdev;
4803 qdev->timer.function = ql_timer;
4804 qdev->timer.expires = jiffies + (5*HZ);
4805 add_timer(&qdev->timer);
4806 ql_link_off(qdev);
4807 ql_display_dev_info(ndev);
4808 atomic_set(&qdev->lb_count, 0);
4809 cards_found++;
4810 return 0;
4811 }
4812
4813 netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev)
4814 {
4815 return qlge_send(skb, ndev);
4816 }
4817
4818 int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget)
4819 {
4820 return ql_clean_inbound_rx_ring(rx_ring, budget);
4821 }
4822
4823 static void qlge_remove(struct pci_dev *pdev)
4824 {
4825 struct net_device *ndev = pci_get_drvdata(pdev);
4826 struct ql_adapter *qdev = netdev_priv(ndev);
4827 del_timer_sync(&qdev->timer);
4828 ql_cancel_all_work_sync(qdev);
4829 unregister_netdev(ndev);
4830 ql_release_all(pdev);
4831 pci_disable_device(pdev);
4832 free_netdev(ndev);
4833 }
4834
4835 /* Clean up resources without touching hardware. */
4836 static void ql_eeh_close(struct net_device *ndev)
4837 {
4838 int i;
4839 struct ql_adapter *qdev = netdev_priv(ndev);
4840
4841 if (netif_carrier_ok(ndev)) {
4842 netif_carrier_off(ndev);
4843 netif_stop_queue(ndev);
4844 }
4845
4846 /* Disabling the timer */
4847 del_timer_sync(&qdev->timer);
4848 ql_cancel_all_work_sync(qdev);
4849
4850 for (i = 0; i < qdev->rss_ring_count; i++)
4851 netif_napi_del(&qdev->rx_ring[i].napi);
4852
4853 clear_bit(QL_ADAPTER_UP, &qdev->flags);
4854 ql_tx_ring_clean(qdev);
4855 ql_free_rx_buffers(qdev);
4856 ql_release_adapter_resources(qdev);
4857 }
4858
4859 /*
4860 * This callback is called by the PCI subsystem whenever
4861 * a PCI bus error is detected.
4862 */
4863 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
4864 enum pci_channel_state state)
4865 {
4866 struct net_device *ndev = pci_get_drvdata(pdev);
4867 struct ql_adapter *qdev = netdev_priv(ndev);
4868
4869 switch (state) {
4870 case pci_channel_io_normal:
4871 return PCI_ERS_RESULT_CAN_RECOVER;
4872 case pci_channel_io_frozen:
4873 netif_device_detach(ndev);
4874 if (netif_running(ndev))
4875 ql_eeh_close(ndev);
4876 pci_disable_device(pdev);
4877 return PCI_ERS_RESULT_NEED_RESET;
4878 case pci_channel_io_perm_failure:
4879 dev_err(&pdev->dev,
4880 "%s: pci_channel_io_perm_failure.\n", __func__);
4881 ql_eeh_close(ndev);
4882 set_bit(QL_EEH_FATAL, &qdev->flags);
4883 return PCI_ERS_RESULT_DISCONNECT;
4884 }
4885
4886 /* Request a slot reset. */
4887 return PCI_ERS_RESULT_NEED_RESET;
4888 }
4889
4890 /*
4891 * This callback is called after the PCI buss has been reset.
4892 * Basically, this tries to restart the card from scratch.
4893 * This is a shortened version of the device probe/discovery code,
4894 * it resembles the first-half of the () routine.
4895 */
4896 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
4897 {
4898 struct net_device *ndev = pci_get_drvdata(pdev);
4899 struct ql_adapter *qdev = netdev_priv(ndev);
4900
4901 pdev->error_state = pci_channel_io_normal;
4902
4903 pci_restore_state(pdev);
4904 if (pci_enable_device(pdev)) {
4905 netif_err(qdev, ifup, qdev->ndev,
4906 "Cannot re-enable PCI device after reset.\n");
4907 return PCI_ERS_RESULT_DISCONNECT;
4908 }
4909 pci_set_master(pdev);
4910
4911 if (ql_adapter_reset(qdev)) {
4912 netif_err(qdev, drv, qdev->ndev, "reset FAILED!\n");
4913 set_bit(QL_EEH_FATAL, &qdev->flags);
4914 return PCI_ERS_RESULT_DISCONNECT;
4915 }
4916
4917 return PCI_ERS_RESULT_RECOVERED;
4918 }
4919
4920 static void qlge_io_resume(struct pci_dev *pdev)
4921 {
4922 struct net_device *ndev = pci_get_drvdata(pdev);
4923 struct ql_adapter *qdev = netdev_priv(ndev);
4924 int err = 0;
4925
4926 if (netif_running(ndev)) {
4927 err = qlge_open(ndev);
4928 if (err) {
4929 netif_err(qdev, ifup, qdev->ndev,
4930 "Device initialization failed after reset.\n");
4931 return;
4932 }
4933 } else {
4934 netif_err(qdev, ifup, qdev->ndev,
4935 "Device was not running prior to EEH.\n");
4936 }
4937 mod_timer(&qdev->timer, jiffies + (5*HZ));
4938 netif_device_attach(ndev);
4939 }
4940
4941 static const struct pci_error_handlers qlge_err_handler = {
4942 .error_detected = qlge_io_error_detected,
4943 .slot_reset = qlge_io_slot_reset,
4944 .resume = qlge_io_resume,
4945 };
4946
4947 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
4948 {
4949 struct net_device *ndev = pci_get_drvdata(pdev);
4950 struct ql_adapter *qdev = netdev_priv(ndev);
4951 int err;
4952
4953 netif_device_detach(ndev);
4954 del_timer_sync(&qdev->timer);
4955
4956 if (netif_running(ndev)) {
4957 err = ql_adapter_down(qdev);
4958 if (!err)
4959 return err;
4960 }
4961
4962 ql_wol(qdev);
4963 err = pci_save_state(pdev);
4964 if (err)
4965 return err;
4966
4967 pci_disable_device(pdev);
4968
4969 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4970
4971 return 0;
4972 }
4973
4974 #ifdef CONFIG_PM
4975 static int qlge_resume(struct pci_dev *pdev)
4976 {
4977 struct net_device *ndev = pci_get_drvdata(pdev);
4978 struct ql_adapter *qdev = netdev_priv(ndev);
4979 int err;
4980
4981 pci_set_power_state(pdev, PCI_D0);
4982 pci_restore_state(pdev);
4983 err = pci_enable_device(pdev);
4984 if (err) {
4985 netif_err(qdev, ifup, qdev->ndev, "Cannot enable PCI device from suspend\n");
4986 return err;
4987 }
4988 pci_set_master(pdev);
4989
4990 pci_enable_wake(pdev, PCI_D3hot, 0);
4991 pci_enable_wake(pdev, PCI_D3cold, 0);
4992
4993 if (netif_running(ndev)) {
4994 err = ql_adapter_up(qdev);
4995 if (err)
4996 return err;
4997 }
4998
4999 mod_timer(&qdev->timer, jiffies + (5*HZ));
5000 netif_device_attach(ndev);
5001
5002 return 0;
5003 }
5004 #endif /* CONFIG_PM */
5005
5006 static void qlge_shutdown(struct pci_dev *pdev)
5007 {
5008 qlge_suspend(pdev, PMSG_SUSPEND);
5009 }
5010
5011 static struct pci_driver qlge_driver = {
5012 .name = DRV_NAME,
5013 .id_table = qlge_pci_tbl,
5014 .probe = qlge_probe,
5015 .remove = qlge_remove,
5016 #ifdef CONFIG_PM
5017 .suspend = qlge_suspend,
5018 .resume = qlge_resume,
5019 #endif
5020 .shutdown = qlge_shutdown,
5021 .err_handler = &qlge_err_handler
5022 };
5023
5024 module_pci_driver(qlge_driver);
Linux kernel - Deliverables
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