drivers/net/ethernet/qualcomm/emac/emac-sgmii.c

   1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
  14  */
  15
  16 #include <linux/iopoll.h>
  17 #include <linux/of_device.h>
  18 #include "emac.h"
  19 #include "emac-mac.h"
  20 #include "emac-sgmii.h"
  21
  22 /* EMAC_QSERDES register offsets */
  23 #define EMAC_QSERDES_COM_SYS_CLK_CTRL           0x000000
  24 #define EMAC_QSERDES_COM_PLL_CNTRL              0x000014
  25 #define EMAC_QSERDES_COM_PLL_IP_SETI            0x000018
  26 #define EMAC_QSERDES_COM_PLL_CP_SETI            0x000024
  27 #define EMAC_QSERDES_COM_PLL_IP_SETP            0x000028
  28 #define EMAC_QSERDES_COM_PLL_CP_SETP            0x00002c
  29 #define EMAC_QSERDES_COM_SYSCLK_EN_SEL          0x000038
  30 #define EMAC_QSERDES_COM_RESETSM_CNTRL          0x000040
  31 #define EMAC_QSERDES_COM_PLLLOCK_CMP1           0x000044
  32 #define EMAC_QSERDES_COM_PLLLOCK_CMP2           0x000048
  33 #define EMAC_QSERDES_COM_PLLLOCK_CMP3           0x00004c
  34 #define EMAC_QSERDES_COM_PLLLOCK_CMP_EN         0x000050
  35 #define EMAC_QSERDES_COM_DEC_START1             0x000064
  36 #define EMAC_QSERDES_COM_DIV_FRAC_START1        0x000098
  37 #define EMAC_QSERDES_COM_DIV_FRAC_START2        0x00009c
  38 #define EMAC_QSERDES_COM_DIV_FRAC_START3        0x0000a0
  39 #define EMAC_QSERDES_COM_DEC_START2             0x0000a4
  40 #define EMAC_QSERDES_COM_PLL_CRCTRL             0x0000ac
  41 #define EMAC_QSERDES_COM_RESET_SM               0x0000bc
  42 #define EMAC_QSERDES_TX_BIST_MODE_LANENO        0x000100
  43 #define EMAC_QSERDES_TX_TX_EMP_POST1_LVL        0x000108
  44 #define EMAC_QSERDES_TX_TX_DRV_LVL              0x00010c
  45 #define EMAC_QSERDES_TX_LANE_MODE               0x000150
  46 #define EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN        0x000170
  47 #define EMAC_QSERDES_RX_CDR_CONTROL             0x000200
  48 #define EMAC_QSERDES_RX_CDR_CONTROL2            0x000210
  49 #define EMAC_QSERDES_RX_RX_EQ_GAIN12            0x000230
  50
  51 /* EMAC_SGMII register offsets */
  52 #define EMAC_SGMII_PHY_SERDES_START             0x000000
  53 #define EMAC_SGMII_PHY_CMN_PWR_CTRL             0x000004
  54 #define EMAC_SGMII_PHY_RX_PWR_CTRL              0x000008
  55 #define EMAC_SGMII_PHY_TX_PWR_CTRL              0x00000C
  56 #define EMAC_SGMII_PHY_LANE_CTRL1               0x000018
  57 #define EMAC_SGMII_PHY_AUTONEG_CFG2             0x000048
  58 #define EMAC_SGMII_PHY_CDR_CTRL0                0x000058
  59 #define EMAC_SGMII_PHY_SPEED_CFG1               0x000074
  60 #define EMAC_SGMII_PHY_POW_DWN_CTRL0            0x000080
  61 #define EMAC_SGMII_PHY_RESET_CTRL               0x0000a8
  62 #define EMAC_SGMII_PHY_IRQ_CMD                  0x0000ac
  63 #define EMAC_SGMII_PHY_INTERRUPT_CLEAR          0x0000b0
  64 #define EMAC_SGMII_PHY_INTERRUPT_MASK           0x0000b4
  65 #define EMAC_SGMII_PHY_INTERRUPT_STATUS         0x0000b8
  66 #define EMAC_SGMII_PHY_RX_CHK_STATUS            0x0000d4
  67 #define EMAC_SGMII_PHY_AUTONEG0_STATUS          0x0000e0
  68 #define EMAC_SGMII_PHY_AUTONEG1_STATUS          0x0000e4
  69
  70 /* EMAC_QSERDES_COM_PLL_IP_SETI */
  71 #define PLL_IPSETI(x)                           ((x) & 0x3f)
  72
  73 /* EMAC_QSERDES_COM_PLL_CP_SETI */
  74 #define PLL_CPSETI(x)                           ((x) & 0xff)
  75
  76 /* EMAC_QSERDES_COM_PLL_IP_SETP */
  77 #define PLL_IPSETP(x)                           ((x) & 0x3f)
  78
  79 /* EMAC_QSERDES_COM_PLL_CP_SETP */
  80 #define PLL_CPSETP(x)                           ((x) & 0x1f)
  81
  82 /* EMAC_QSERDES_COM_PLL_CRCTRL */
  83 #define PLL_RCTRL(x)                            (((x) & 0xf) << 4)
  84 #define PLL_CCTRL(x)                            ((x) & 0xf)
  85
  86 /* SGMII v2 PHY registers per lane */
  87 #define EMAC_SGMII_PHY_LN_OFFSET                0x0400
  88
  89 /* SGMII v2 digital lane registers */
  90 #define EMAC_SGMII_LN_DRVR_CTRL0                0x00C
  91 #define EMAC_SGMII_LN_DRVR_TAP_EN               0x018
  92 #define EMAC_SGMII_LN_TX_MARGINING              0x01C
  93 #define EMAC_SGMII_LN_TX_PRE                    0x020
  94 #define EMAC_SGMII_LN_TX_POST                   0x024
  95 #define EMAC_SGMII_LN_TX_BAND_MODE              0x060
  96 #define EMAC_SGMII_LN_LANE_MODE                 0x064
  97 #define EMAC_SGMII_LN_PARALLEL_RATE             0x078
  98 #define EMAC_SGMII_LN_CML_CTRL_MODE0            0x0B8
  99 #define EMAC_SGMII_LN_MIXER_CTRL_MODE0          0x0D0
 100 #define EMAC_SGMII_LN_VGA_INITVAL               0x134
 101 #define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0        0x17C
 102 #define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0        0x188
 103 #define EMAC_SGMII_LN_UCDR_SO_CONFIG            0x194
 104 #define EMAC_SGMII_LN_RX_BAND                   0x19C
 105 #define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0       0x1B8
 106 #define EMAC_SGMII_LN_RSM_CONFIG                0x1F0
 107 #define EMAC_SGMII_LN_SIGDET_ENABLES            0x224
 108 #define EMAC_SGMII_LN_SIGDET_CNTRL              0x228
 109 #define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL     0x22C
 110 #define EMAC_SGMII_LN_RX_EN_SIGNAL              0x2A0
 111 #define EMAC_SGMII_LN_RX_MISC_CNTRL0            0x2AC
 112 #define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV         0x2BC
 113
 114 /* SGMII v2 digital lane register values */
 115 #define UCDR_STEP_BY_TWO_MODE0                  BIT(7)
 116 #define UCDR_xO_GAIN_MODE(x)                    ((x) & 0x7f)
 117 #define UCDR_ENABLE                             BIT(6)
 118 #define UCDR_SO_SATURATION(x)                   ((x) & 0x3f)
 119 #define SIGDET_LP_BYP_PS4                       BIT(7)
 120 #define SIGDET_EN_PS0_TO_PS2                    BIT(6)
 121 #define EN_ACCOUPLEVCM_SW_MUX                   BIT(5)
 122 #define EN_ACCOUPLEVCM_SW                       BIT(4)
 123 #define RX_SYNC_EN                              BIT(3)
 124 #define RXTERM_HIGHZ_PS5                        BIT(2)
 125 #define SIGDET_EN_PS3                           BIT(1)
 126 #define EN_ACCOUPLE_VCM_PS3                     BIT(0)
 127 #define UFS_MODE                                BIT(5)
 128 #define TXVAL_VALID_INIT                        BIT(4)
 129 #define TXVAL_VALID_MUX                         BIT(3)
 130 #define TXVAL_VALID                             BIT(2)
 131 #define USB3P1_MODE                             BIT(1)
 132 #define KR_PCIGEN3_MODE                         BIT(0)
 133 #define PRE_EN                                  BIT(3)
 134 #define POST_EN                                 BIT(2)
 135 #define MAIN_EN_MUX                             BIT(1)
 136 #define MAIN_EN                                 BIT(0)
 137 #define TX_MARGINING_MUX                        BIT(6)
 138 #define TX_MARGINING(x)                         ((x) & 0x3f)
 139 #define TX_PRE_MUX                              BIT(6)
 140 #define TX_PRE(x)                               ((x) & 0x3f)
 141 #define TX_POST_MUX                             BIT(6)
 142 #define TX_POST(x)                              ((x) & 0x3f)
 143 #define CML_GEAR_MODE(x)                        (((x) & 7) << 3)
 144 #define CML2CMOS_IBOOST_MODE(x)                 ((x) & 7)
 145 #define MIXER_LOADB_MODE(x)                     (((x) & 0xf) << 2)
 146 #define MIXER_DATARATE_MODE(x)                  ((x) & 3)
 147 #define VGA_THRESH_DFE(x)                       ((x) & 0x3f)
 148 #define SIGDET_LP_BYP_PS0_TO_PS2                BIT(5)
 149 #define SIGDET_LP_BYP_MUX                       BIT(4)
 150 #define SIGDET_LP_BYP                           BIT(3)
 151 #define SIGDET_EN_MUX                           BIT(2)
 152 #define SIGDET_EN                               BIT(1)
 153 #define SIGDET_FLT_BYP                          BIT(0)
 154 #define SIGDET_LVL(x)                           (((x) & 0xf) << 4)
 155 #define SIGDET_BW_CTRL(x)                       ((x) & 0xf)
 156 #define SIGDET_DEGLITCH_CTRL(x)                 (((x) & 0xf) << 1)
 157 #define SIGDET_DEGLITCH_BYP                     BIT(0)
 158 #define INVERT_PCS_RX_CLK                       BIT(7)
 159 #define PWM_EN                                  BIT(6)
 160 #define RXBIAS_SEL(x)                           (((x) & 0x3) << 4)
 161 #define EBDAC_SIGN                              BIT(3)
 162 #define EDAC_SIGN                               BIT(2)
 163 #define EN_AUXTAP1SIGN_INVERT                   BIT(1)
 164 #define EN_DAC_CHOPPING                         BIT(0)
 165 #define DRVR_LOGIC_CLK_EN                       BIT(4)
 166 #define DRVR_LOGIC_CLK_DIV(x)                   ((x) & 0xf)
 167 #define PARALLEL_RATE_MODE2(x)                  (((x) & 0x3) << 4)
 168 #define PARALLEL_RATE_MODE1(x)                  (((x) & 0x3) << 2)
 169 #define PARALLEL_RATE_MODE0(x)                  ((x) & 0x3)
 170 #define BAND_MODE2(x)                           (((x) & 0x3) << 4)
 171 #define BAND_MODE1(x)                           (((x) & 0x3) << 2)
 172 #define BAND_MODE0(x)                           ((x) & 0x3)
 173 #define LANE_SYNC_MODE                          BIT(5)
 174 #define LANE_MODE(x)                            ((x) & 0x1f)
 175 #define CDR_PD_SEL_MODE0(x)                     (((x) & 0x3) << 5)
 176 #define EN_DLL_MODE0                            BIT(4)
 177 #define EN_IQ_DCC_MODE0                         BIT(3)
 178 #define EN_IQCAL_MODE0                          BIT(2)
 179 #define EN_QPATH_MODE0                          BIT(1)
 180 #define EN_EPATH_MODE0                          BIT(0)
 181 #define FORCE_TSYNC_ACK                         BIT(7)
 182 #define FORCE_CMN_ACK                           BIT(6)
 183 #define FORCE_CMN_READY                         BIT(5)
 184 #define EN_RCLK_DEGLITCH                        BIT(4)
 185 #define BYPASS_RSM_CDR_RESET                    BIT(3)
 186 #define BYPASS_RSM_TSYNC                        BIT(2)
 187 #define BYPASS_RSM_SAMP_CAL                     BIT(1)
 188 #define BYPASS_RSM_DLL_CAL                      BIT(0)
 189
 190 /* EMAC_QSERDES_COM_SYS_CLK_CTRL */
 191 #define SYSCLK_CM                               BIT(4)
 192 #define SYSCLK_AC_COUPLE                        BIT(3)
 193
 194 /* EMAC_QSERDES_COM_PLL_CNTRL */
 195 #define OCP_EN                                  BIT(5)
 196 #define PLL_DIV_FFEN                            BIT(2)
 197 #define PLL_DIV_ORD                             BIT(1)
 198
 199 /* EMAC_QSERDES_COM_SYSCLK_EN_SEL */
 200 #define SYSCLK_SEL_CMOS                         BIT(3)
 201
 202 /* EMAC_QSERDES_COM_RESETSM_CNTRL */
 203 #define FRQ_TUNE_MODE                           BIT(4)
 204
 205 /* EMAC_QSERDES_COM_PLLLOCK_CMP_EN */
 206 #define PLLLOCK_CMP_EN                          BIT(0)
 207
 208 /* EMAC_QSERDES_COM_DEC_START1 */
 209 #define DEC_START1_MUX                          BIT(7)
 210 #define DEC_START1(x)                           ((x) & 0x7f)
 211
 212 /* EMAC_QSERDES_COM_DIV_FRAC_START1 * EMAC_QSERDES_COM_DIV_FRAC_START2 */
 213 #define DIV_FRAC_START_MUX                      BIT(7)
 214 #define DIV_FRAC_START(x)                       ((x) & 0x7f)
 215
 216 /* EMAC_QSERDES_COM_DIV_FRAC_START3 */
 217 #define DIV_FRAC_START3_MUX                     BIT(4)
 218 #define DIV_FRAC_START3(x)                      ((x) & 0xf)
 219
 220 /* EMAC_QSERDES_COM_DEC_START2 */
 221 #define DEC_START2_MUX                          BIT(1)
 222 #define DEC_START2                              BIT(0)
 223
 224 /* EMAC_QSERDES_COM_RESET_SM */
 225 #define READY                                   BIT(5)
 226
 227 /* EMAC_QSERDES_TX_TX_EMP_POST1_LVL */
 228 #define TX_EMP_POST1_LVL_MUX                    BIT(5)
 229 #define TX_EMP_POST1_LVL(x)                     ((x) & 0x1f)
 230 #define TX_EMP_POST1_LVL_BMSK                   0x1f
 231 #define TX_EMP_POST1_LVL_SHFT                   0
 232
 233 /* EMAC_QSERDES_TX_TX_DRV_LVL */
 234 #define TX_DRV_LVL_MUX                          BIT(4)
 235 #define TX_DRV_LVL(x)                           ((x) & 0xf)
 236
 237 /* EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN */
 238 #define EMP_EN_MUX                              BIT(1)
 239 #define EMP_EN                                  BIT(0)
 240
 241 /* EMAC_QSERDES_RX_CDR_CONTROL & EMAC_QSERDES_RX_CDR_CONTROL2 */
 242 #define HBW_PD_EN                               BIT(7)
 243 #define SECONDORDERENABLE                       BIT(6)
 244 #define FIRSTORDER_THRESH(x)                    (((x) & 0x7) << 3)
 245 #define SECONDORDERGAIN(x)                      ((x) & 0x7)
 246
 247 /* EMAC_QSERDES_RX_RX_EQ_GAIN12 */
 248 #define RX_EQ_GAIN2(x)                          (((x) & 0xf) << 4)
 249 #define RX_EQ_GAIN1(x)                          ((x) & 0xf)
 250
 251 /* EMAC_SGMII_PHY_SERDES_START */
 252 #define SERDES_START                            BIT(0)
 253
 254 /* EMAC_SGMII_PHY_CMN_PWR_CTRL */
 255 #define BIAS_EN                                 BIT(6)
 256 #define PLL_EN                                  BIT(5)
 257 #define SYSCLK_EN                               BIT(4)
 258 #define CLKBUF_L_EN                             BIT(3)
 259 #define PLL_TXCLK_EN                            BIT(1)
 260 #define PLL_RXCLK_EN                            BIT(0)
 261
 262 /* EMAC_SGMII_PHY_RX_PWR_CTRL */
 263 #define L0_RX_SIGDET_EN                         BIT(7)
 264 #define L0_RX_TERM_MODE(x)                      (((x) & 3) << 4)
 265 #define L0_RX_I_EN                              BIT(1)
 266
 267 /* EMAC_SGMII_PHY_TX_PWR_CTRL */
 268 #define L0_TX_EN                                BIT(5)
 269 #define L0_CLKBUF_EN                            BIT(4)
 270 #define L0_TRAN_BIAS_EN                         BIT(1)
 271
 272 /* EMAC_SGMII_PHY_LANE_CTRL1 */
 273 #define L0_RX_EQUALIZE_ENABLE                   BIT(6)
 274 #define L0_RESET_TSYNC_EN                       BIT(4)
 275 #define L0_DRV_LVL(x)                           ((x) & 0xf)
 276
 277 /* EMAC_SGMII_PHY_AUTONEG_CFG2 */
 278 #define FORCE_AN_TX_CFG                         BIT(5)
 279 #define FORCE_AN_RX_CFG                         BIT(4)
 280 #define AN_ENABLE                               BIT(0)
 281
 282 /* EMAC_SGMII_PHY_SPEED_CFG1 */
 283 #define DUPLEX_MODE                             BIT(4)
 284 #define SPDMODE_1000                            BIT(1)
 285 #define SPDMODE_100                             BIT(0)
 286 #define SPDMODE_10                              0
 287 #define SPDMODE_BMSK                            3
 288 #define SPDMODE_SHFT                            0
 289
 290 /* EMAC_SGMII_PHY_POW_DWN_CTRL0 */
 291 #define PWRDN_B                                 BIT(0)
 292 #define CDR_MAX_CNT(x)                          ((x) & 0xff)
 293
 294 /* EMAC_QSERDES_TX_BIST_MODE_LANENO */
 295 #define BIST_LANE_NUMBER(x)                     (((x) & 3) << 5)
 296 #define BISTMODE(x)                             ((x) & 0x1f)
 297
 298 /* EMAC_QSERDES_COM_PLLLOCK_CMPx */
 299 #define PLLLOCK_CMP(x)                          ((x) & 0xff)
 300
 301 /* EMAC_SGMII_PHY_RESET_CTRL */
 302 #define PHY_SW_RESET                            BIT(0)
 303
 304 /* EMAC_SGMII_PHY_IRQ_CMD */
 305 #define IRQ_GLOBAL_CLEAR                        BIT(0)
 306
 307 /* EMAC_SGMII_PHY_INTERRUPT_MASK */
 308 #define DECODE_CODE_ERR                         BIT(7)
 309 #define DECODE_DISP_ERR                         BIT(6)
 310 #define PLL_UNLOCK                              BIT(5)
 311 #define AN_ILLEGAL_TERM                         BIT(4)
 312 #define SYNC_FAIL                               BIT(3)
 313 #define AN_START                                BIT(2)
 314 #define AN_END                                  BIT(1)
 315 #define AN_REQUEST                              BIT(0)
 316
 317 #define SGMII_PHY_IRQ_CLR_WAIT_TIME             10
 318
 319 #define SGMII_PHY_INTERRUPT_ERR (\
 320         DECODE_CODE_ERR         |\
 321         DECODE_DISP_ERR)
 322
 323 #define SGMII_ISR_AN_MASK       (\
 324         AN_REQUEST              |\
 325         AN_START                |\
 326         AN_END                  |\
 327         AN_ILLEGAL_TERM         |\
 328         PLL_UNLOCK              |\
 329         SYNC_FAIL)
 330
 331 #define SGMII_ISR_MASK          (\
 332         SGMII_PHY_INTERRUPT_ERR |\
 333         SGMII_ISR_AN_MASK)
 334
 335 /* SGMII TX_CONFIG */
 336 #define TXCFG_LINK                              0x8000
 337 #define TXCFG_MODE_BMSK                         0x1c00
 338 #define TXCFG_1000_FULL                         0x1800
 339 #define TXCFG_100_FULL                          0x1400
 340 #define TXCFG_100_HALF                          0x0400
 341 #define TXCFG_10_FULL                           0x1000
 342 #define TXCFG_10_HALF                           0x0000
 343
 344 #define SERDES_START_WAIT_TIMES                 100
 345
 346 struct emac_reg_write {
 347         unsigned int offset;
 348         u32 val;
 349 };
 350
 351 static void emac_reg_write_all(void __iomem *base,
 352                                const struct emac_reg_write *itr, size_t size)
 353 {
 354         size_t i;
 355
 356         for (i = 0; i < size; ++itr, ++i)
 357                 writel(itr->val, base + itr->offset);
 358 }
 359
 360 static const struct emac_reg_write physical_coding_sublayer_programming_v1[] = {
 361         {EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
 362         {EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
 363         {EMAC_SGMII_PHY_CMN_PWR_CTRL,
 364                 BIAS_EN | SYSCLK_EN | CLKBUF_L_EN | PLL_TXCLK_EN | PLL_RXCLK_EN},
 365         {EMAC_SGMII_PHY_TX_PWR_CTRL, L0_TX_EN | L0_CLKBUF_EN | L0_TRAN_BIAS_EN},
 366         {EMAC_SGMII_PHY_RX_PWR_CTRL,
 367                 L0_RX_SIGDET_EN | L0_RX_TERM_MODE(1) | L0_RX_I_EN},
 368         {EMAC_SGMII_PHY_CMN_PWR_CTRL,
 369                 BIAS_EN | PLL_EN | SYSCLK_EN | CLKBUF_L_EN | PLL_TXCLK_EN |
 370                 PLL_RXCLK_EN},
 371         {EMAC_SGMII_PHY_LANE_CTRL1,
 372                 L0_RX_EQUALIZE_ENABLE | L0_RESET_TSYNC_EN | L0_DRV_LVL(15)},
 373 };
 374
 375 static const struct emac_reg_write sysclk_refclk_setting[] = {
 376         {EMAC_QSERDES_COM_SYSCLK_EN_SEL, SYSCLK_SEL_CMOS},
 377         {EMAC_QSERDES_COM_SYS_CLK_CTRL, SYSCLK_CM | SYSCLK_AC_COUPLE},
 378 };
 379
 380 static const struct emac_reg_write pll_setting[] = {
 381         {EMAC_QSERDES_COM_PLL_IP_SETI, PLL_IPSETI(1)},
 382         {EMAC_QSERDES_COM_PLL_CP_SETI, PLL_CPSETI(59)},
 383         {EMAC_QSERDES_COM_PLL_IP_SETP, PLL_IPSETP(10)},
 384         {EMAC_QSERDES_COM_PLL_CP_SETP, PLL_CPSETP(9)},
 385         {EMAC_QSERDES_COM_PLL_CRCTRL, PLL_RCTRL(15) | PLL_CCTRL(11)},
 386         {EMAC_QSERDES_COM_PLL_CNTRL, OCP_EN | PLL_DIV_FFEN | PLL_DIV_ORD},
 387         {EMAC_QSERDES_COM_DEC_START1, DEC_START1_MUX | DEC_START1(2)},
 388         {EMAC_QSERDES_COM_DEC_START2, DEC_START2_MUX | DEC_START2},
 389         {EMAC_QSERDES_COM_DIV_FRAC_START1,
 390                 DIV_FRAC_START_MUX | DIV_FRAC_START(85)},
 391         {EMAC_QSERDES_COM_DIV_FRAC_START2,
 392                 DIV_FRAC_START_MUX | DIV_FRAC_START(42)},
 393         {EMAC_QSERDES_COM_DIV_FRAC_START3,
 394                 DIV_FRAC_START3_MUX | DIV_FRAC_START3(3)},
 395         {EMAC_QSERDES_COM_PLLLOCK_CMP1, PLLLOCK_CMP(43)},
 396         {EMAC_QSERDES_COM_PLLLOCK_CMP2, PLLLOCK_CMP(104)},
 397         {EMAC_QSERDES_COM_PLLLOCK_CMP3, PLLLOCK_CMP(0)},
 398         {EMAC_QSERDES_COM_PLLLOCK_CMP_EN, PLLLOCK_CMP_EN},
 399         {EMAC_QSERDES_COM_RESETSM_CNTRL, FRQ_TUNE_MODE},
 400 };
 401
 402 static const struct emac_reg_write cdr_setting[] = {
 403         {EMAC_QSERDES_RX_CDR_CONTROL,
 404                 SECONDORDERENABLE | FIRSTORDER_THRESH(3) | SECONDORDERGAIN(2)},
 405         {EMAC_QSERDES_RX_CDR_CONTROL2,
 406                 SECONDORDERENABLE | FIRSTORDER_THRESH(3) | SECONDORDERGAIN(4)},
 407 };
 408
 409 static const struct emac_reg_write tx_rx_setting[] = {
 410         {EMAC_QSERDES_TX_BIST_MODE_LANENO, 0},
 411         {EMAC_QSERDES_TX_TX_DRV_LVL, TX_DRV_LVL_MUX | TX_DRV_LVL(15)},
 412         {EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN, EMP_EN_MUX | EMP_EN},
 413         {EMAC_QSERDES_TX_TX_EMP_POST1_LVL,
 414                 TX_EMP_POST1_LVL_MUX | TX_EMP_POST1_LVL(1)},
 415         {EMAC_QSERDES_RX_RX_EQ_GAIN12, RX_EQ_GAIN2(15) | RX_EQ_GAIN1(15)},
 416         {EMAC_QSERDES_TX_LANE_MODE, LANE_MODE(8)},
 417 };
 418
 419 static const struct emac_reg_write sgmii_v2_laned[] = {
 420         /* CDR Settings */
 421         {EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0,
 422                 UCDR_STEP_BY_TWO_MODE0 | UCDR_xO_GAIN_MODE(10)},
 423         {EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(6)},
 424         {EMAC_SGMII_LN_UCDR_SO_CONFIG, UCDR_ENABLE | UCDR_SO_SATURATION(12)},
 425
 426         /* TX/RX Settings */
 427         {EMAC_SGMII_LN_RX_EN_SIGNAL, SIGDET_LP_BYP_PS4 | SIGDET_EN_PS0_TO_PS2},
 428
 429         {EMAC_SGMII_LN_DRVR_CTRL0, TXVAL_VALID_INIT | KR_PCIGEN3_MODE},
 430         {EMAC_SGMII_LN_DRVR_TAP_EN, MAIN_EN},
 431         {EMAC_SGMII_LN_TX_MARGINING, TX_MARGINING_MUX | TX_MARGINING(25)},
 432         {EMAC_SGMII_LN_TX_PRE, TX_PRE_MUX},
 433         {EMAC_SGMII_LN_TX_POST, TX_POST_MUX},
 434
 435         {EMAC_SGMII_LN_CML_CTRL_MODE0,
 436                 CML_GEAR_MODE(1) | CML2CMOS_IBOOST_MODE(1)},
 437         {EMAC_SGMII_LN_MIXER_CTRL_MODE0,
 438                 MIXER_LOADB_MODE(12) | MIXER_DATARATE_MODE(1)},
 439         {EMAC_SGMII_LN_VGA_INITVAL, VGA_THRESH_DFE(31)},
 440         {EMAC_SGMII_LN_SIGDET_ENABLES,
 441                 SIGDET_LP_BYP_PS0_TO_PS2 | SIGDET_FLT_BYP},
 442         {EMAC_SGMII_LN_SIGDET_CNTRL, SIGDET_LVL(8)},
 443
 444         {EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL, SIGDET_DEGLITCH_CTRL(4)},
 445         {EMAC_SGMII_LN_RX_MISC_CNTRL0, 0},
 446         {EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV,
 447                 DRVR_LOGIC_CLK_EN | DRVR_LOGIC_CLK_DIV(4)},
 448
 449         {EMAC_SGMII_LN_PARALLEL_RATE, PARALLEL_RATE_MODE0(1)},
 450         {EMAC_SGMII_LN_TX_BAND_MODE, BAND_MODE0(2)},
 451         {EMAC_SGMII_LN_RX_BAND, BAND_MODE0(3)},
 452         {EMAC_SGMII_LN_LANE_MODE, LANE_MODE(26)},
 453         {EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0, CDR_PD_SEL_MODE0(3)},
 454         {EMAC_SGMII_LN_RSM_CONFIG, BYPASS_RSM_SAMP_CAL | BYPASS_RSM_DLL_CAL},
 455 };
 456
 457 static const struct emac_reg_write physical_coding_sublayer_programming_v2[] = {
 458         {EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
 459         {EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
 460         {EMAC_SGMII_PHY_TX_PWR_CTRL, 0},
 461         {EMAC_SGMII_PHY_LANE_CTRL1, L0_RX_EQUALIZE_ENABLE},
 462 };
 463
 464 static int emac_sgmii_link_init(struct emac_adapter *adpt)
 465 {
 466         struct phy_device *phydev = adpt->phydev;
 467         struct emac_phy *phy = &adpt->phy;
 468         u32 val;
 469
 470         val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
 471
 472         if (phydev->autoneg == AUTONEG_ENABLE) {
 473                 val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG);
 474                 val |= AN_ENABLE;
 475                 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
 476         } else {
 477                 u32 speed_cfg;
 478
 479                 switch (phydev->speed) {
 480                 case SPEED_10:
 481                         speed_cfg = SPDMODE_10;
 482                         break;
 483                 case SPEED_100:
 484                         speed_cfg = SPDMODE_100;
 485                         break;
 486                 case SPEED_1000:
 487                         speed_cfg = SPDMODE_1000;
 488                         break;
 489                 default:
 490                         return -EINVAL;
 491                 }
 492
 493                 if (phydev->duplex == DUPLEX_FULL)
 494                         speed_cfg |= DUPLEX_MODE;
 495
 496                 val &= ~AN_ENABLE;
 497                 writel(speed_cfg, phy->base + EMAC_SGMII_PHY_SPEED_CFG1);
 498                 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
 499         }
 500
 501         return 0;
 502 }
 503
 504 static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u32 irq_bits)
 505 {
 506         struct emac_phy *phy = &adpt->phy;
 507         u32 status;
 508
 509         writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
 510         writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
 511         /* Ensure interrupt clear command is written to HW */
 512         wmb();
 513
 514         /* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must
 515          * be confirmed before clearing the bits in other registers.
 516          * It takes a few cycles for hw to clear the interrupt status.
 517          */
 518         if (readl_poll_timeout_atomic(phy->base +
 519                                       EMAC_SGMII_PHY_INTERRUPT_STATUS,
 520                                       status, !(status & irq_bits), 1,
 521                                       SGMII_PHY_IRQ_CLR_WAIT_TIME)) {
 522                 netdev_err(adpt->netdev,
 523                            "error: failed clear SGMII irq: status:0x%x bits:0x%x\n",
 524                            status, irq_bits);
 525                 return -EIO;
 526         }
 527
 528         /* Finalize clearing procedure */
 529         writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
 530         writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
 531
 532         /* Ensure that clearing procedure finalization is written to HW */
 533         wmb();
 534
 535         return 0;
 536 }
 537
 538 int emac_sgmii_init_v1(struct emac_adapter *adpt)
 539 {
 540         struct emac_phy *phy = &adpt->phy;
 541         unsigned int i;
 542         int ret;
 543
 544         ret = emac_sgmii_link_init(adpt);
 545         if (ret)
 546                 return ret;
 547
 548         emac_reg_write_all(phy->base, physical_coding_sublayer_programming_v1,
 549                            ARRAY_SIZE(physical_coding_sublayer_programming_v1));
 550         emac_reg_write_all(phy->base, sysclk_refclk_setting,
 551                            ARRAY_SIZE(sysclk_refclk_setting));
 552         emac_reg_write_all(phy->base, pll_setting, ARRAY_SIZE(pll_setting));
 553         emac_reg_write_all(phy->base, cdr_setting, ARRAY_SIZE(cdr_setting));
 554         emac_reg_write_all(phy->base, tx_rx_setting,
 555                            ARRAY_SIZE(tx_rx_setting));
 556
 557         /* Power up the Ser/Des engine */
 558         writel(SERDES_START, phy->base + EMAC_SGMII_PHY_SERDES_START);
 559
 560         for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
 561                 if (readl(phy->base + EMAC_QSERDES_COM_RESET_SM) & READY)
 562                         break;
 563                 usleep_range(100, 200);
 564         }
 565
 566         if (i == SERDES_START_WAIT_TIMES) {
 567                 netdev_err(adpt->netdev, "error: ser/des failed to start\n");
 568                 return -EIO;
 569         }
 570         /* Mask out all the SGMII Interrupt */
 571         writel(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
 572
 573         emac_sgmii_irq_clear(adpt, SGMII_PHY_INTERRUPT_ERR);
 574
 575         return 0;
 576 }
 577
 578 int emac_sgmii_init_v2(struct emac_adapter *adpt)
 579 {
 580         struct emac_phy *phy = &adpt->phy;
 581         void __iomem *phy_regs = phy->base;
 582         void __iomem *laned = phy->digital;
 583         unsigned int i;
 584         u32 lnstatus;
 585         int ret;
 586
 587         ret = emac_sgmii_link_init(adpt);
 588         if (ret)
 589                 return ret;
 590
 591         /* PCS lane-x init */
 592         emac_reg_write_all(phy->base, physical_coding_sublayer_programming_v2,
 593                            ARRAY_SIZE(physical_coding_sublayer_programming_v2));
 594
 595         /* SGMII lane-x init */
 596         emac_reg_write_all(phy->digital,
 597                            sgmii_v2_laned, ARRAY_SIZE(sgmii_v2_laned));
 598
 599         /* Power up PCS and start reset lane state machine */
 600
 601         writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL);
 602         writel(1, laned + SGMII_LN_RSM_START);
 603
 604         /* Wait for c_ready assertion */
 605         for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
 606                 lnstatus = readl(phy_regs + SGMII_PHY_LN_LANE_STATUS);
 607                 if (lnstatus & BIT(1))
 608                         break;
 609                 usleep_range(100, 200);
 610         }
 611
 612         if (i == SERDES_START_WAIT_TIMES) {
 613                 netdev_err(adpt->netdev, "SGMII failed to start\n");
 614                 return -EIO;
 615         }
 616
 617         /* Disable digital and SERDES loopback */
 618         writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0);
 619         writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2);
 620         writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1);
 621
 622         /* Mask out all the SGMII Interrupt */
 623         writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK);
 624
 625         emac_sgmii_irq_clear(adpt, SGMII_PHY_INTERRUPT_ERR);
 626
 627         return 0;
 628 }
 629
 630 static void emac_sgmii_reset_prepare(struct emac_adapter *adpt)
 631 {
 632         struct emac_phy *phy = &adpt->phy;
 633         u32 val;
 634
 635         /* Reset PHY */
 636         val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
 637         writel(((val & ~PHY_RESET) | PHY_RESET), phy->base +
 638                EMAC_EMAC_WRAPPER_CSR2);
 639         /* Ensure phy-reset command is written to HW before the release cmd */
 640         msleep(50);
 641         val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
 642         writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2);
 643         /* Ensure phy-reset release command is written to HW before initializing
 644          * SGMII
 645          */
 646         msleep(50);
 647 }
 648
 649 void emac_sgmii_reset(struct emac_adapter *adpt)
 650 {
 651         int ret;
 652
 653         clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 19200000);
 654         emac_sgmii_reset_prepare(adpt);
 655
 656         ret = adpt->phy.initialize(adpt);
 657         if (ret)
 658                 netdev_err(adpt->netdev,
 659                            "could not reinitialize internal PHY (error=%i)\n",
 660                            ret);
 661
 662         clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 125000000);
 663 }
 664
 665 static const struct of_device_id emac_sgmii_dt_match[] = {
 666         {
 667                 .compatible = "qcom,fsm9900-emac-sgmii",
 668                 .data = emac_sgmii_init_v1,
 669         },
 670         {
 671                 .compatible = "qcom,qdf2432-emac-sgmii",
 672                 .data = emac_sgmii_init_v2,
 673         },
 674         {}
 675 };
 676
 677 int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt)
 678 {
 679         struct platform_device *sgmii_pdev = NULL;
 680         struct emac_phy *phy = &adpt->phy;
 681         struct resource *res;
 682         const struct of_device_id *match;
 683         struct device_node *np;
 684
 685         np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0);
 686         if (!np) {
 687                 dev_err(&pdev->dev, "missing internal-phy property\n");
 688                 return -ENODEV;
 689         }
 690
 691         sgmii_pdev = of_find_device_by_node(np);
 692         if (!sgmii_pdev) {
 693                 dev_err(&pdev->dev, "invalid internal-phy property\n");
 694                 return -ENODEV;
 695         }
 696
 697         match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev);
 698         if (!match) {
 699                 dev_err(&pdev->dev, "unrecognized internal phy node\n");
 700                 return -ENODEV;
 701         }
 702
 703         phy->initialize = (emac_sgmii_initialize)match->data;
 704
 705         /* Base address is the first address */
 706         res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0);
 707         phy->base = devm_ioremap_resource(&sgmii_pdev->dev, res);
 708         if (IS_ERR(phy->base))
 709                 return PTR_ERR(phy->base);
 710
 711         /* v2 SGMII has a per-lane digital digital, so parse it if it exists */
 712         res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 1);
 713         if (res) {
 714                 phy->digital = devm_ioremap_resource(&sgmii_pdev->dev, res);
 715                 if (IS_ERR(phy->base))
 716                         return PTR_ERR(phy->base);
 717
 718         }
 719
 720         return phy->initialize(adpt);
 721 }