2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
61 #define assert(expr) \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit
= 32;
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
110 RTL_GIGA_MAC_VER_01
= 0,
161 RTL_GIGA_MAC_NONE
= 0xff,
164 enum rtl_tx_desc_version
{
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
175 #define _R(NAME,TD,FW,SZ,B) { \
183 static const struct {
185 enum rtl_tx_desc_version txd_version
;
189 } rtl_chip_infos
[] = {
191 [RTL_GIGA_MAC_VER_01
] =
192 _R("RTL8169", RTL_TD_0
, NULL
, JUMBO_7K
, true),
193 [RTL_GIGA_MAC_VER_02
] =
194 _R("RTL8169s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
195 [RTL_GIGA_MAC_VER_03
] =
196 _R("RTL8110s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
197 [RTL_GIGA_MAC_VER_04
] =
198 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
, JUMBO_7K
, true),
199 [RTL_GIGA_MAC_VER_05
] =
200 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
201 [RTL_GIGA_MAC_VER_06
] =
202 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
204 [RTL_GIGA_MAC_VER_07
] =
205 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
206 [RTL_GIGA_MAC_VER_08
] =
207 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
208 [RTL_GIGA_MAC_VER_09
] =
209 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
210 [RTL_GIGA_MAC_VER_10
] =
211 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
212 [RTL_GIGA_MAC_VER_11
] =
213 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
214 [RTL_GIGA_MAC_VER_12
] =
215 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
216 [RTL_GIGA_MAC_VER_13
] =
217 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
218 [RTL_GIGA_MAC_VER_14
] =
219 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
220 [RTL_GIGA_MAC_VER_15
] =
221 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
222 [RTL_GIGA_MAC_VER_16
] =
223 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
224 [RTL_GIGA_MAC_VER_17
] =
225 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
226 [RTL_GIGA_MAC_VER_18
] =
227 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
228 [RTL_GIGA_MAC_VER_19
] =
229 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
230 [RTL_GIGA_MAC_VER_20
] =
231 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
232 [RTL_GIGA_MAC_VER_21
] =
233 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
234 [RTL_GIGA_MAC_VER_22
] =
235 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
236 [RTL_GIGA_MAC_VER_23
] =
237 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
238 [RTL_GIGA_MAC_VER_24
] =
239 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
240 [RTL_GIGA_MAC_VER_25
] =
241 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
,
243 [RTL_GIGA_MAC_VER_26
] =
244 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
,
246 [RTL_GIGA_MAC_VER_27
] =
247 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
248 [RTL_GIGA_MAC_VER_28
] =
249 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
250 [RTL_GIGA_MAC_VER_29
] =
251 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
253 [RTL_GIGA_MAC_VER_30
] =
254 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
256 [RTL_GIGA_MAC_VER_31
] =
257 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
258 [RTL_GIGA_MAC_VER_32
] =
259 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
,
261 [RTL_GIGA_MAC_VER_33
] =
262 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
,
264 [RTL_GIGA_MAC_VER_34
] =
265 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
,
267 [RTL_GIGA_MAC_VER_35
] =
268 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_1
,
270 [RTL_GIGA_MAC_VER_36
] =
271 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_2
,
273 [RTL_GIGA_MAC_VER_37
] =
274 _R("RTL8402", RTL_TD_1
, FIRMWARE_8402_1
,
276 [RTL_GIGA_MAC_VER_38
] =
277 _R("RTL8411", RTL_TD_1
, FIRMWARE_8411_1
,
279 [RTL_GIGA_MAC_VER_39
] =
280 _R("RTL8106e", RTL_TD_1
, FIRMWARE_8106E_1
,
282 [RTL_GIGA_MAC_VER_40
] =
283 _R("RTL8168g/8111g", RTL_TD_1
, FIRMWARE_8168G_2
,
285 [RTL_GIGA_MAC_VER_41
] =
286 _R("RTL8168g/8111g", RTL_TD_1
, NULL
, JUMBO_9K
, false),
287 [RTL_GIGA_MAC_VER_42
] =
288 _R("RTL8168g/8111g", RTL_TD_1
, FIRMWARE_8168G_3
,
290 [RTL_GIGA_MAC_VER_43
] =
291 _R("RTL8106e", RTL_TD_1
, FIRMWARE_8106E_2
,
293 [RTL_GIGA_MAC_VER_44
] =
294 _R("RTL8411", RTL_TD_1
, FIRMWARE_8411_2
,
296 [RTL_GIGA_MAC_VER_45
] =
297 _R("RTL8168h/8111h", RTL_TD_1
, FIRMWARE_8168H_1
,
299 [RTL_GIGA_MAC_VER_46
] =
300 _R("RTL8168h/8111h", RTL_TD_1
, FIRMWARE_8168H_2
,
302 [RTL_GIGA_MAC_VER_47
] =
303 _R("RTL8107e", RTL_TD_1
, FIRMWARE_8107E_1
,
305 [RTL_GIGA_MAC_VER_48
] =
306 _R("RTL8107e", RTL_TD_1
, FIRMWARE_8107E_2
,
308 [RTL_GIGA_MAC_VER_49
] =
309 _R("RTL8168ep/8111ep", RTL_TD_1
, NULL
,
311 [RTL_GIGA_MAC_VER_50
] =
312 _R("RTL8168ep/8111ep", RTL_TD_1
, NULL
,
314 [RTL_GIGA_MAC_VER_51
] =
315 _R("RTL8168ep/8111ep", RTL_TD_1
, NULL
,
326 static const struct pci_device_id rtl8169_pci_tbl
[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
332 { PCI_VENDOR_ID_DLINK
, 0x4300,
333 PCI_VENDOR_ID_DLINK
, 0x4b10, 0, 0, RTL_CFG_1
},
334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
336 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
338 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
339 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
341 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
345 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
347 static int rx_buf_sz
= 16383;
354 MAC0
= 0, /* Ethernet hardware address. */
356 MAR0
= 8, /* Multicast filter. */
357 CounterAddrLow
= 0x10,
358 CounterAddrHigh
= 0x14,
359 TxDescStartAddrLow
= 0x20,
360 TxDescStartAddrHigh
= 0x24,
361 TxHDescStartAddrLow
= 0x28,
362 TxHDescStartAddrHigh
= 0x2c,
371 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
375 #define RX128_INT_EN (1 << 15) /* 8111c and later */
376 #define RX_MULTI_EN (1 << 14) /* 8111c only */
377 #define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
380 #define RX_EARLY_OFF (1 << 11)
381 #define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
390 #define PME_SIGNAL (1 << 5) /* 8168c and later */
401 RxDescAddrLow
= 0xe4,
402 RxDescAddrHigh
= 0xe8,
403 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
405 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
407 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
409 #define TxPacketMax (8064 >> 7)
410 #define EarlySize 0x27
413 FuncEventMask
= 0xf4,
414 FuncPresetState
= 0xf8,
419 FuncForceEvent
= 0xfc,
422 enum rtl8110_registers
{
428 enum rtl8168_8101_registers
{
431 #define CSIAR_FLAG 0x80000000
432 #define CSIAR_WRITE_CMD 0x80000000
433 #define CSIAR_BYTE_ENABLE 0x0f
434 #define CSIAR_BYTE_ENABLE_SHIFT 12
435 #define CSIAR_ADDR_MASK 0x0fff
436 #define CSIAR_FUNC_CARD 0x00000000
437 #define CSIAR_FUNC_SDIO 0x00010000
438 #define CSIAR_FUNC_NIC 0x00020000
439 #define CSIAR_FUNC_NIC2 0x00010000
442 #define EPHYAR_FLAG 0x80000000
443 #define EPHYAR_WRITE_CMD 0x80000000
444 #define EPHYAR_REG_MASK 0x1f
445 #define EPHYAR_REG_SHIFT 16
446 #define EPHYAR_DATA_MASK 0xffff
448 #define PFM_EN (1 << 6)
449 #define TX_10M_PS_EN (1 << 7)
451 #define FIX_NAK_1 (1 << 4)
452 #define FIX_NAK_2 (1 << 3)
455 #define NOW_IS_OOB (1 << 7)
456 #define TX_EMPTY (1 << 5)
457 #define RX_EMPTY (1 << 4)
458 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
459 #define EN_NDP (1 << 3)
460 #define EN_OOB_RESET (1 << 2)
461 #define LINK_LIST_RDY (1 << 1)
463 #define EFUSEAR_FLAG 0x80000000
464 #define EFUSEAR_WRITE_CMD 0x80000000
465 #define EFUSEAR_READ_CMD 0x00000000
466 #define EFUSEAR_REG_MASK 0x03ff
467 #define EFUSEAR_REG_SHIFT 8
468 #define EFUSEAR_DATA_MASK 0xff
470 #define PFM_D3COLD_EN (1 << 6)
473 enum rtl8168_registers
{
478 #define ERIAR_FLAG 0x80000000
479 #define ERIAR_WRITE_CMD 0x80000000
480 #define ERIAR_READ_CMD 0x00000000
481 #define ERIAR_ADDR_BYTE_ALIGN 4
482 #define ERIAR_TYPE_SHIFT 16
483 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
486 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
487 #define ERIAR_MASK_SHIFT 12
488 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
490 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
491 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
492 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
493 EPHY_RXER_NUM
= 0x7c,
494 OCPDR
= 0xb0, /* OCP GPHY access */
495 #define OCPDR_WRITE_CMD 0x80000000
496 #define OCPDR_READ_CMD 0x00000000
497 #define OCPDR_REG_MASK 0x7f
498 #define OCPDR_GPHY_REG_SHIFT 16
499 #define OCPDR_DATA_MASK 0xffff
501 #define OCPAR_FLAG 0x80000000
502 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
503 #define OCPAR_GPHY_READ_CMD 0x0000f060
505 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC
= 0xf0, /* 8168e only. */
507 #define TXPLA_RST (1 << 29)
508 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
509 #define PWM_EN (1 << 22)
510 #define RXDV_GATED_EN (1 << 19)
511 #define EARLY_TALLY_EN (1 << 16)
514 enum rtl_register_content
{
515 /* InterruptStatusBits */
519 TxDescUnavail
= 0x0080,
543 /* TXPoll register p.5 */
544 HPQ
= 0x80, /* Poll cmd on the high prio queue */
545 NPQ
= 0x40, /* Poll cmd on the low prio queue */
546 FSWInt
= 0x01, /* Forced software interrupt */
550 Cfg9346_Unlock
= 0xc0,
555 AcceptBroadcast
= 0x08,
556 AcceptMulticast
= 0x04,
558 AcceptAllPhys
= 0x01,
559 #define RX_CONFIG_ACCEPT_MASK 0x3f
562 TxInterFrameGapShift
= 24,
563 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
565 /* Config1 register p.24 */
568 Speed_down
= (1 << 4),
572 PMEnable
= (1 << 0), /* Power Management Enable */
574 /* Config2 register p. 25 */
575 ClkReqEn
= (1 << 7), /* Clock Request Enable */
576 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
577 PCI_Clock_66MHz
= 0x01,
578 PCI_Clock_33MHz
= 0x00,
580 /* Config3 register p.25 */
581 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
583 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
584 Rdy_to_L23
= (1 << 1), /* L23 Enable */
585 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
587 /* Config4 register */
588 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
590 /* Config5 register p.27 */
591 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
593 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
595 LanWake
= (1 << 1), /* LanWake enable/disable */
596 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
597 ASPM_en
= (1 << 0), /* ASPM enable */
600 TBIReset
= 0x80000000,
601 TBILoopback
= 0x40000000,
602 TBINwEnable
= 0x20000000,
603 TBINwRestart
= 0x10000000,
604 TBILinkOk
= 0x02000000,
605 TBINwComplete
= 0x01000000,
608 EnableBist
= (1 << 15), // 8168 8101
609 Mac_dbgo_oe
= (1 << 14), // 8168 8101
610 Normal_mode
= (1 << 13), // unused
611 Force_half_dup
= (1 << 12), // 8168 8101
612 Force_rxflow_en
= (1 << 11), // 8168 8101
613 Force_txflow_en
= (1 << 10), // 8168 8101
614 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
615 ASF
= (1 << 8), // 8168 8101
616 PktCntrDisable
= (1 << 7), // 8168 8101
617 Mac_dbgo_sel
= 0x001c, // 8168
622 INTT_0
= 0x0000, // 8168
623 INTT_1
= 0x0001, // 8168
624 INTT_2
= 0x0002, // 8168
625 INTT_3
= 0x0003, // 8168
627 /* rtl8169_PHYstatus */
638 TBILinkOK
= 0x02000000,
640 /* ResetCounterCommand */
643 /* DumpCounterCommand */
646 /* magic enable v2 */
647 MagicPacket_v2
= (1 << 16), /* Wake up when receives a Magic Packet */
651 /* First doubleword. */
652 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
653 RingEnd
= (1 << 30), /* End of descriptor ring */
654 FirstFrag
= (1 << 29), /* First segment of a packet */
655 LastFrag
= (1 << 28), /* Final segment of a packet */
659 enum rtl_tx_desc_bit
{
660 /* First doubleword. */
661 TD_LSO
= (1 << 27), /* Large Send Offload */
662 #define TD_MSS_MAX 0x07ffu /* MSS value */
664 /* Second doubleword. */
665 TxVlanTag
= (1 << 17), /* Add VLAN tag */
668 /* 8169, 8168b and 810x except 8102e. */
669 enum rtl_tx_desc_bit_0
{
670 /* First doubleword. */
671 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
672 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
673 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
674 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
677 /* 8102e, 8168c and beyond. */
678 enum rtl_tx_desc_bit_1
{
679 /* First doubleword. */
680 TD1_GTSENV4
= (1 << 26), /* Giant Send for IPv4 */
681 TD1_GTSENV6
= (1 << 25), /* Giant Send for IPv6 */
682 #define GTTCPHO_SHIFT 18
683 #define GTTCPHO_MAX 0x7fU
685 /* Second doubleword. */
686 #define TCPHO_SHIFT 18
687 #define TCPHO_MAX 0x3ffU
688 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
689 TD1_IPv6_CS
= (1 << 28), /* Calculate IPv6 checksum */
690 TD1_IPv4_CS
= (1 << 29), /* Calculate IPv4 checksum */
691 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
692 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
695 enum rtl_rx_desc_bit
{
697 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
698 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
700 #define RxProtoUDP (PID1)
701 #define RxProtoTCP (PID0)
702 #define RxProtoIP (PID1 | PID0)
703 #define RxProtoMask RxProtoIP
705 IPFail
= (1 << 16), /* IP checksum failed */
706 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
707 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
708 RxVlanTag
= (1 << 16), /* VLAN tag available */
711 #define RsvdMask 0x3fffc000
728 u8 __pad
[sizeof(void *) - sizeof(u32
)];
732 RTL_FEATURE_WOL
= (1 << 0),
733 RTL_FEATURE_MSI
= (1 << 1),
734 RTL_FEATURE_GMII
= (1 << 2),
737 struct rtl8169_counters
{
744 __le32 tx_one_collision
;
745 __le32 tx_multi_collision
;
753 struct rtl8169_tc_offsets
{
756 __le32 tx_multi_collision
;
761 RTL_FLAG_TASK_ENABLED
,
762 RTL_FLAG_TASK_SLOW_PENDING
,
763 RTL_FLAG_TASK_RESET_PENDING
,
764 RTL_FLAG_TASK_PHY_PENDING
,
768 struct rtl8169_stats
{
771 struct u64_stats_sync syncp
;
774 struct rtl8169_private
{
775 void __iomem
*mmio_addr
; /* memory map physical address */
776 struct pci_dev
*pci_dev
;
777 struct net_device
*dev
;
778 struct napi_struct napi
;
782 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
783 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
785 struct rtl8169_stats rx_stats
;
786 struct rtl8169_stats tx_stats
;
787 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
788 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
789 dma_addr_t TxPhyAddr
;
790 dma_addr_t RxPhyAddr
;
791 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
792 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
793 struct timer_list timer
;
799 void (*write
)(struct rtl8169_private
*, int, int);
800 int (*read
)(struct rtl8169_private
*, int);
803 struct pll_power_ops
{
804 void (*down
)(struct rtl8169_private
*);
805 void (*up
)(struct rtl8169_private
*);
809 void (*enable
)(struct rtl8169_private
*);
810 void (*disable
)(struct rtl8169_private
*);
814 void (*write
)(struct rtl8169_private
*, int, int);
815 u32 (*read
)(struct rtl8169_private
*, int);
818 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
819 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
820 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
821 void (*hw_start
)(struct net_device
*);
822 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
823 unsigned int (*link_ok
)(void __iomem
*);
824 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
825 bool (*tso_csum
)(struct rtl8169_private
*, struct sk_buff
*, u32
*);
828 DECLARE_BITMAP(flags
, RTL_FLAG_MAX
);
830 struct work_struct work
;
835 struct mii_if_info mii
;
836 dma_addr_t counters_phys_addr
;
837 struct rtl8169_counters
*counters
;
838 struct rtl8169_tc_offsets tc_offset
;
843 const struct firmware
*fw
;
845 #define RTL_VER_SIZE 32
847 char version
[RTL_VER_SIZE
];
849 struct rtl_fw_phy_action
{
854 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
859 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
860 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
861 module_param(use_dac
, int, 0);
862 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
863 module_param_named(debug
, debug
.msg_enable
, int, 0);
864 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
865 MODULE_LICENSE("GPL");
866 MODULE_VERSION(RTL8169_VERSION
);
867 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
868 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
869 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
870 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
871 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
872 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
873 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
874 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
875 MODULE_FIRMWARE(FIRMWARE_8402_1
);
876 MODULE_FIRMWARE(FIRMWARE_8411_1
);
877 MODULE_FIRMWARE(FIRMWARE_8411_2
);
878 MODULE_FIRMWARE(FIRMWARE_8106E_1
);
879 MODULE_FIRMWARE(FIRMWARE_8106E_2
);
880 MODULE_FIRMWARE(FIRMWARE_8168G_2
);
881 MODULE_FIRMWARE(FIRMWARE_8168G_3
);
882 MODULE_FIRMWARE(FIRMWARE_8168H_1
);
883 MODULE_FIRMWARE(FIRMWARE_8168H_2
);
884 MODULE_FIRMWARE(FIRMWARE_8107E_1
);
885 MODULE_FIRMWARE(FIRMWARE_8107E_2
);
887 static void rtl_lock_work(struct rtl8169_private
*tp
)
889 mutex_lock(&tp
->wk
.mutex
);
892 static void rtl_unlock_work(struct rtl8169_private
*tp
)
894 mutex_unlock(&tp
->wk
.mutex
);
897 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
899 pcie_capability_clear_and_set_word(pdev
, PCI_EXP_DEVCTL
,
900 PCI_EXP_DEVCTL_READRQ
, force
);
904 bool (*check
)(struct rtl8169_private
*);
908 static void rtl_udelay(unsigned int d
)
913 static bool rtl_loop_wait(struct rtl8169_private
*tp
, const struct rtl_cond
*c
,
914 void (*delay
)(unsigned int), unsigned int d
, int n
,
919 for (i
= 0; i
< n
; i
++) {
921 if (c
->check(tp
) == high
)
924 netif_err(tp
, drv
, tp
->dev
, "%s == %d (loop: %d, delay: %d).\n",
925 c
->msg
, !high
, n
, d
);
929 static bool rtl_udelay_loop_wait_high(struct rtl8169_private
*tp
,
930 const struct rtl_cond
*c
,
931 unsigned int d
, int n
)
933 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, true);
936 static bool rtl_udelay_loop_wait_low(struct rtl8169_private
*tp
,
937 const struct rtl_cond
*c
,
938 unsigned int d
, int n
)
940 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, false);
943 static bool rtl_msleep_loop_wait_high(struct rtl8169_private
*tp
,
944 const struct rtl_cond
*c
,
945 unsigned int d
, int n
)
947 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, true);
950 static bool rtl_msleep_loop_wait_low(struct rtl8169_private
*tp
,
951 const struct rtl_cond
*c
,
952 unsigned int d
, int n
)
954 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, false);
957 #define DECLARE_RTL_COND(name) \
958 static bool name ## _check(struct rtl8169_private *); \
960 static const struct rtl_cond name = { \
961 .check = name ## _check, \
965 static bool name ## _check(struct rtl8169_private *tp)
967 static bool rtl_ocp_reg_failure(struct rtl8169_private
*tp
, u32 reg
)
969 if (reg
& 0xffff0001) {
970 netif_err(tp
, drv
, tp
->dev
, "Invalid ocp reg %x!\n", reg
);
976 DECLARE_RTL_COND(rtl_ocp_gphy_cond
)
978 void __iomem
*ioaddr
= tp
->mmio_addr
;
980 return RTL_R32(GPHY_OCP
) & OCPAR_FLAG
;
983 static void r8168_phy_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
985 void __iomem
*ioaddr
= tp
->mmio_addr
;
987 if (rtl_ocp_reg_failure(tp
, reg
))
990 RTL_W32(GPHY_OCP
, OCPAR_FLAG
| (reg
<< 15) | data
);
992 rtl_udelay_loop_wait_low(tp
, &rtl_ocp_gphy_cond
, 25, 10);
995 static u16
r8168_phy_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
997 void __iomem
*ioaddr
= tp
->mmio_addr
;
999 if (rtl_ocp_reg_failure(tp
, reg
))
1002 RTL_W32(GPHY_OCP
, reg
<< 15);
1004 return rtl_udelay_loop_wait_high(tp
, &rtl_ocp_gphy_cond
, 25, 10) ?
1005 (RTL_R32(GPHY_OCP
) & 0xffff) : ~0;
1008 static void r8168_mac_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
1010 void __iomem
*ioaddr
= tp
->mmio_addr
;
1012 if (rtl_ocp_reg_failure(tp
, reg
))
1015 RTL_W32(OCPDR
, OCPAR_FLAG
| (reg
<< 15) | data
);
1018 static u16
r8168_mac_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
1020 void __iomem
*ioaddr
= tp
->mmio_addr
;
1022 if (rtl_ocp_reg_failure(tp
, reg
))
1025 RTL_W32(OCPDR
, reg
<< 15);
1027 return RTL_R32(OCPDR
);
1030 #define OCP_STD_PHY_BASE 0xa400
1032 static void r8168g_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1035 tp
->ocp_base
= value
? value
<< 4 : OCP_STD_PHY_BASE
;
1039 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
1042 r8168_phy_ocp_write(tp
, tp
->ocp_base
+ reg
* 2, value
);
1045 static int r8168g_mdio_read(struct rtl8169_private
*tp
, int reg
)
1047 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
1050 return r8168_phy_ocp_read(tp
, tp
->ocp_base
+ reg
* 2);
1053 static void mac_mcu_write(struct rtl8169_private
*tp
, int reg
, int value
)
1056 tp
->ocp_base
= value
<< 4;
1060 r8168_mac_ocp_write(tp
, tp
->ocp_base
+ reg
, value
);
1063 static int mac_mcu_read(struct rtl8169_private
*tp
, int reg
)
1065 return r8168_mac_ocp_read(tp
, tp
->ocp_base
+ reg
);
1068 DECLARE_RTL_COND(rtl_phyar_cond
)
1070 void __iomem
*ioaddr
= tp
->mmio_addr
;
1072 return RTL_R32(PHYAR
) & 0x80000000;
1075 static void r8169_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1077 void __iomem
*ioaddr
= tp
->mmio_addr
;
1079 RTL_W32(PHYAR
, 0x80000000 | (reg
& 0x1f) << 16 | (value
& 0xffff));
1081 rtl_udelay_loop_wait_low(tp
, &rtl_phyar_cond
, 25, 20);
1083 * According to hardware specs a 20us delay is required after write
1084 * complete indication, but before sending next command.
1089 static int r8169_mdio_read(struct rtl8169_private
*tp
, int reg
)
1091 void __iomem
*ioaddr
= tp
->mmio_addr
;
1094 RTL_W32(PHYAR
, 0x0 | (reg
& 0x1f) << 16);
1096 value
= rtl_udelay_loop_wait_high(tp
, &rtl_phyar_cond
, 25, 20) ?
1097 RTL_R32(PHYAR
) & 0xffff : ~0;
1100 * According to hardware specs a 20us delay is required after read
1101 * complete indication, but before sending next command.
1108 DECLARE_RTL_COND(rtl_ocpar_cond
)
1110 void __iomem
*ioaddr
= tp
->mmio_addr
;
1112 return RTL_R32(OCPAR
) & OCPAR_FLAG
;
1115 static void r8168dp_1_mdio_access(struct rtl8169_private
*tp
, int reg
, u32 data
)
1117 void __iomem
*ioaddr
= tp
->mmio_addr
;
1119 RTL_W32(OCPDR
, data
| ((reg
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
1120 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
1121 RTL_W32(EPHY_RXER_NUM
, 0);
1123 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 1000, 100);
1126 static void r8168dp_1_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1128 r8168dp_1_mdio_access(tp
, reg
,
1129 OCPDR_WRITE_CMD
| (value
& OCPDR_DATA_MASK
));
1132 static int r8168dp_1_mdio_read(struct rtl8169_private
*tp
, int reg
)
1134 void __iomem
*ioaddr
= tp
->mmio_addr
;
1136 r8168dp_1_mdio_access(tp
, reg
, OCPDR_READ_CMD
);
1139 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
1140 RTL_W32(EPHY_RXER_NUM
, 0);
1142 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 1000, 100) ?
1143 RTL_R32(OCPDR
) & OCPDR_DATA_MASK
: ~0;
1146 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1148 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
1150 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
1153 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
1155 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
1158 static void r8168dp_2_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1160 void __iomem
*ioaddr
= tp
->mmio_addr
;
1162 r8168dp_2_mdio_start(ioaddr
);
1164 r8169_mdio_write(tp
, reg
, value
);
1166 r8168dp_2_mdio_stop(ioaddr
);
1169 static int r8168dp_2_mdio_read(struct rtl8169_private
*tp
, int reg
)
1171 void __iomem
*ioaddr
= tp
->mmio_addr
;
1174 r8168dp_2_mdio_start(ioaddr
);
1176 value
= r8169_mdio_read(tp
, reg
);
1178 r8168dp_2_mdio_stop(ioaddr
);
1183 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
1185 tp
->mdio_ops
.write(tp
, location
, val
);
1188 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1190 return tp
->mdio_ops
.read(tp
, location
);
1193 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1195 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1198 static void rtl_w0w1_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1202 val
= rtl_readphy(tp
, reg_addr
);
1203 rtl_writephy(tp
, reg_addr
, (val
& ~m
) | p
);
1206 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1209 struct rtl8169_private
*tp
= netdev_priv(dev
);
1211 rtl_writephy(tp
, location
, val
);
1214 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1216 struct rtl8169_private
*tp
= netdev_priv(dev
);
1218 return rtl_readphy(tp
, location
);
1221 DECLARE_RTL_COND(rtl_ephyar_cond
)
1223 void __iomem
*ioaddr
= tp
->mmio_addr
;
1225 return RTL_R32(EPHYAR
) & EPHYAR_FLAG
;
1228 static void rtl_ephy_write(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1230 void __iomem
*ioaddr
= tp
->mmio_addr
;
1232 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1233 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1235 rtl_udelay_loop_wait_low(tp
, &rtl_ephyar_cond
, 10, 100);
1240 static u16
rtl_ephy_read(struct rtl8169_private
*tp
, int reg_addr
)
1242 void __iomem
*ioaddr
= tp
->mmio_addr
;
1244 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1246 return rtl_udelay_loop_wait_high(tp
, &rtl_ephyar_cond
, 10, 100) ?
1247 RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
: ~0;
1250 DECLARE_RTL_COND(rtl_eriar_cond
)
1252 void __iomem
*ioaddr
= tp
->mmio_addr
;
1254 return RTL_R32(ERIAR
) & ERIAR_FLAG
;
1257 static void rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1260 void __iomem
*ioaddr
= tp
->mmio_addr
;
1262 BUG_ON((addr
& 3) || (mask
== 0));
1263 RTL_W32(ERIDR
, val
);
1264 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1266 rtl_udelay_loop_wait_low(tp
, &rtl_eriar_cond
, 100, 100);
1269 static u32
rtl_eri_read(struct rtl8169_private
*tp
, int addr
, int type
)
1271 void __iomem
*ioaddr
= tp
->mmio_addr
;
1273 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1275 return rtl_udelay_loop_wait_high(tp
, &rtl_eriar_cond
, 100, 100) ?
1276 RTL_R32(ERIDR
) : ~0;
1279 static void rtl_w0w1_eri(struct rtl8169_private
*tp
, int addr
, u32 mask
, u32 p
,
1284 val
= rtl_eri_read(tp
, addr
, type
);
1285 rtl_eri_write(tp
, addr
, mask
, (val
& ~m
) | p
, type
);
1288 static u32
r8168dp_ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1290 void __iomem
*ioaddr
= tp
->mmio_addr
;
1292 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1293 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 100, 20) ?
1294 RTL_R32(OCPDR
) : ~0;
1297 static u32
r8168ep_ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1299 return rtl_eri_read(tp
, reg
, ERIAR_OOB
);
1302 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1304 switch (tp
->mac_version
) {
1305 case RTL_GIGA_MAC_VER_27
:
1306 case RTL_GIGA_MAC_VER_28
:
1307 case RTL_GIGA_MAC_VER_31
:
1308 return r8168dp_ocp_read(tp
, mask
, reg
);
1309 case RTL_GIGA_MAC_VER_49
:
1310 case RTL_GIGA_MAC_VER_50
:
1311 case RTL_GIGA_MAC_VER_51
:
1312 return r8168ep_ocp_read(tp
, mask
, reg
);
1319 static void r8168dp_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1322 void __iomem
*ioaddr
= tp
->mmio_addr
;
1324 RTL_W32(OCPDR
, data
);
1325 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1326 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 100, 20);
1329 static void r8168ep_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1332 rtl_eri_write(tp
, reg
, ((u32
)mask
& 0x0f) << ERIAR_MASK_SHIFT
,
1336 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
1338 switch (tp
->mac_version
) {
1339 case RTL_GIGA_MAC_VER_27
:
1340 case RTL_GIGA_MAC_VER_28
:
1341 case RTL_GIGA_MAC_VER_31
:
1342 r8168dp_ocp_write(tp
, mask
, reg
, data
);
1344 case RTL_GIGA_MAC_VER_49
:
1345 case RTL_GIGA_MAC_VER_50
:
1346 case RTL_GIGA_MAC_VER_51
:
1347 r8168ep_ocp_write(tp
, mask
, reg
, data
);
1355 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
1357 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_0001
, cmd
, ERIAR_EXGMAC
);
1359 ocp_write(tp
, 0x1, 0x30, 0x00000001);
1362 #define OOB_CMD_RESET 0x00
1363 #define OOB_CMD_DRIVER_START 0x05
1364 #define OOB_CMD_DRIVER_STOP 0x06
1366 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
1368 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
1371 DECLARE_RTL_COND(rtl_ocp_read_cond
)
1375 reg
= rtl8168_get_ocp_reg(tp
);
1377 return ocp_read(tp
, 0x0f, reg
) & 0x00000800;
1380 DECLARE_RTL_COND(rtl_ep_ocp_read_cond
)
1382 return ocp_read(tp
, 0x0f, 0x124) & 0x00000001;
1385 DECLARE_RTL_COND(rtl_ocp_tx_cond
)
1387 void __iomem
*ioaddr
= tp
->mmio_addr
;
1389 return RTL_R8(IBISR0
) & 0x02;
1392 static void rtl8168ep_stop_cmac(struct rtl8169_private
*tp
)
1394 void __iomem
*ioaddr
= tp
->mmio_addr
;
1396 RTL_W8(IBCR2
, RTL_R8(IBCR2
) & ~0x01);
1397 rtl_msleep_loop_wait_low(tp
, &rtl_ocp_tx_cond
, 50, 2000);
1398 RTL_W8(IBISR0
, RTL_R8(IBISR0
) | 0x20);
1399 RTL_W8(IBCR0
, RTL_R8(IBCR0
) & ~0x01);
1402 static void rtl8168dp_driver_start(struct rtl8169_private
*tp
)
1404 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
1405 rtl_msleep_loop_wait_high(tp
, &rtl_ocp_read_cond
, 10, 10);
1408 static void rtl8168ep_driver_start(struct rtl8169_private
*tp
)
1410 ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_START
);
1411 ocp_write(tp
, 0x01, 0x30, ocp_read(tp
, 0x01, 0x30) | 0x01);
1412 rtl_msleep_loop_wait_high(tp
, &rtl_ep_ocp_read_cond
, 10, 10);
1415 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
1417 switch (tp
->mac_version
) {
1418 case RTL_GIGA_MAC_VER_27
:
1419 case RTL_GIGA_MAC_VER_28
:
1420 case RTL_GIGA_MAC_VER_31
:
1421 rtl8168dp_driver_start(tp
);
1423 case RTL_GIGA_MAC_VER_49
:
1424 case RTL_GIGA_MAC_VER_50
:
1425 case RTL_GIGA_MAC_VER_51
:
1426 rtl8168ep_driver_start(tp
);
1434 static void rtl8168dp_driver_stop(struct rtl8169_private
*tp
)
1436 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
1437 rtl_msleep_loop_wait_low(tp
, &rtl_ocp_read_cond
, 10, 10);
1440 static void rtl8168ep_driver_stop(struct rtl8169_private
*tp
)
1442 rtl8168ep_stop_cmac(tp
);
1443 ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_STOP
);
1444 ocp_write(tp
, 0x01, 0x30, ocp_read(tp
, 0x01, 0x30) | 0x01);
1445 rtl_msleep_loop_wait_low(tp
, &rtl_ep_ocp_read_cond
, 10, 10);
1448 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
1450 switch (tp
->mac_version
) {
1451 case RTL_GIGA_MAC_VER_27
:
1452 case RTL_GIGA_MAC_VER_28
:
1453 case RTL_GIGA_MAC_VER_31
:
1454 rtl8168dp_driver_stop(tp
);
1456 case RTL_GIGA_MAC_VER_49
:
1457 case RTL_GIGA_MAC_VER_50
:
1458 case RTL_GIGA_MAC_VER_51
:
1459 rtl8168ep_driver_stop(tp
);
1467 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
1469 u16 reg
= rtl8168_get_ocp_reg(tp
);
1471 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
1474 static int r8168ep_check_dash(struct rtl8169_private
*tp
)
1476 return (ocp_read(tp
, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1479 static int r8168_check_dash(struct rtl8169_private
*tp
)
1481 switch (tp
->mac_version
) {
1482 case RTL_GIGA_MAC_VER_27
:
1483 case RTL_GIGA_MAC_VER_28
:
1484 case RTL_GIGA_MAC_VER_31
:
1485 return r8168dp_check_dash(tp
);
1486 case RTL_GIGA_MAC_VER_49
:
1487 case RTL_GIGA_MAC_VER_50
:
1488 case RTL_GIGA_MAC_VER_51
:
1489 return r8168ep_check_dash(tp
);
1501 static void rtl_write_exgmac_batch(struct rtl8169_private
*tp
,
1502 const struct exgmac_reg
*r
, int len
)
1505 rtl_eri_write(tp
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1510 DECLARE_RTL_COND(rtl_efusear_cond
)
1512 void __iomem
*ioaddr
= tp
->mmio_addr
;
1514 return RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
;
1517 static u8
rtl8168d_efuse_read(struct rtl8169_private
*tp
, int reg_addr
)
1519 void __iomem
*ioaddr
= tp
->mmio_addr
;
1521 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1523 return rtl_udelay_loop_wait_high(tp
, &rtl_efusear_cond
, 100, 300) ?
1524 RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
: ~0;
1527 static u16
rtl_get_events(struct rtl8169_private
*tp
)
1529 void __iomem
*ioaddr
= tp
->mmio_addr
;
1531 return RTL_R16(IntrStatus
);
1534 static void rtl_ack_events(struct rtl8169_private
*tp
, u16 bits
)
1536 void __iomem
*ioaddr
= tp
->mmio_addr
;
1538 RTL_W16(IntrStatus
, bits
);
1542 static void rtl_irq_disable(struct rtl8169_private
*tp
)
1544 void __iomem
*ioaddr
= tp
->mmio_addr
;
1546 RTL_W16(IntrMask
, 0);
1550 static void rtl_irq_enable(struct rtl8169_private
*tp
, u16 bits
)
1552 void __iomem
*ioaddr
= tp
->mmio_addr
;
1554 RTL_W16(IntrMask
, bits
);
1557 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1558 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1559 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1561 static void rtl_irq_enable_all(struct rtl8169_private
*tp
)
1563 rtl_irq_enable(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1566 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1568 void __iomem
*ioaddr
= tp
->mmio_addr
;
1570 rtl_irq_disable(tp
);
1571 rtl_ack_events(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1575 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1577 void __iomem
*ioaddr
= tp
->mmio_addr
;
1579 return RTL_R32(TBICSR
) & TBIReset
;
1582 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1584 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1587 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1589 return RTL_R32(TBICSR
) & TBILinkOk
;
1592 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1594 return RTL_R8(PHYstatus
) & LinkStatus
;
1597 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1599 void __iomem
*ioaddr
= tp
->mmio_addr
;
1601 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1604 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1608 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1609 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1612 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1614 void __iomem
*ioaddr
= tp
->mmio_addr
;
1615 struct net_device
*dev
= tp
->dev
;
1617 if (!netif_running(dev
))
1620 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
1621 tp
->mac_version
== RTL_GIGA_MAC_VER_38
) {
1622 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1623 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011,
1625 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1627 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1628 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1630 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1633 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1635 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f,
1638 /* Reset packet filter */
1639 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1641 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1643 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1644 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1645 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1646 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011,
1648 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1651 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1653 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f,
1656 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_37
) {
1657 if (RTL_R8(PHYstatus
) & _10bps
) {
1658 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x4d02,
1660 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_0011
, 0x0060,
1663 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000,
1669 static void __rtl8169_check_link_status(struct net_device
*dev
,
1670 struct rtl8169_private
*tp
,
1671 void __iomem
*ioaddr
, bool pm
)
1673 if (tp
->link_ok(ioaddr
)) {
1674 rtl_link_chg_patch(tp
);
1675 /* This is to cancel a scheduled suspend if there's one. */
1677 pm_request_resume(&tp
->pci_dev
->dev
);
1678 netif_carrier_on(dev
);
1679 if (net_ratelimit())
1680 netif_info(tp
, ifup
, dev
, "link up\n");
1682 netif_carrier_off(dev
);
1683 netif_info(tp
, ifdown
, dev
, "link down\n");
1685 pm_schedule_suspend(&tp
->pci_dev
->dev
, 5000);
1689 static void rtl8169_check_link_status(struct net_device
*dev
,
1690 struct rtl8169_private
*tp
,
1691 void __iomem
*ioaddr
)
1693 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1696 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1698 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1700 void __iomem
*ioaddr
= tp
->mmio_addr
;
1704 options
= RTL_R8(Config1
);
1705 if (!(options
& PMEnable
))
1708 options
= RTL_R8(Config3
);
1709 if (options
& LinkUp
)
1710 wolopts
|= WAKE_PHY
;
1711 switch (tp
->mac_version
) {
1712 case RTL_GIGA_MAC_VER_34
:
1713 case RTL_GIGA_MAC_VER_35
:
1714 case RTL_GIGA_MAC_VER_36
:
1715 case RTL_GIGA_MAC_VER_37
:
1716 case RTL_GIGA_MAC_VER_38
:
1717 case RTL_GIGA_MAC_VER_40
:
1718 case RTL_GIGA_MAC_VER_41
:
1719 case RTL_GIGA_MAC_VER_42
:
1720 case RTL_GIGA_MAC_VER_43
:
1721 case RTL_GIGA_MAC_VER_44
:
1722 case RTL_GIGA_MAC_VER_45
:
1723 case RTL_GIGA_MAC_VER_46
:
1724 case RTL_GIGA_MAC_VER_47
:
1725 case RTL_GIGA_MAC_VER_48
:
1726 case RTL_GIGA_MAC_VER_49
:
1727 case RTL_GIGA_MAC_VER_50
:
1728 case RTL_GIGA_MAC_VER_51
:
1729 if (rtl_eri_read(tp
, 0xdc, ERIAR_EXGMAC
) & MagicPacket_v2
)
1730 wolopts
|= WAKE_MAGIC
;
1733 if (options
& MagicPacket
)
1734 wolopts
|= WAKE_MAGIC
;
1738 options
= RTL_R8(Config5
);
1740 wolopts
|= WAKE_UCAST
;
1742 wolopts
|= WAKE_BCAST
;
1744 wolopts
|= WAKE_MCAST
;
1749 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1751 struct rtl8169_private
*tp
= netdev_priv(dev
);
1755 wol
->supported
= WAKE_ANY
;
1756 wol
->wolopts
= __rtl8169_get_wol(tp
);
1758 rtl_unlock_work(tp
);
1761 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1763 void __iomem
*ioaddr
= tp
->mmio_addr
;
1764 unsigned int i
, tmp
;
1765 static const struct {
1770 { WAKE_PHY
, Config3
, LinkUp
},
1771 { WAKE_UCAST
, Config5
, UWF
},
1772 { WAKE_BCAST
, Config5
, BWF
},
1773 { WAKE_MCAST
, Config5
, MWF
},
1774 { WAKE_ANY
, Config5
, LanWake
},
1775 { WAKE_MAGIC
, Config3
, MagicPacket
}
1779 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1781 switch (tp
->mac_version
) {
1782 case RTL_GIGA_MAC_VER_34
:
1783 case RTL_GIGA_MAC_VER_35
:
1784 case RTL_GIGA_MAC_VER_36
:
1785 case RTL_GIGA_MAC_VER_37
:
1786 case RTL_GIGA_MAC_VER_38
:
1787 case RTL_GIGA_MAC_VER_40
:
1788 case RTL_GIGA_MAC_VER_41
:
1789 case RTL_GIGA_MAC_VER_42
:
1790 case RTL_GIGA_MAC_VER_43
:
1791 case RTL_GIGA_MAC_VER_44
:
1792 case RTL_GIGA_MAC_VER_45
:
1793 case RTL_GIGA_MAC_VER_46
:
1794 case RTL_GIGA_MAC_VER_47
:
1795 case RTL_GIGA_MAC_VER_48
:
1796 case RTL_GIGA_MAC_VER_49
:
1797 case RTL_GIGA_MAC_VER_50
:
1798 case RTL_GIGA_MAC_VER_51
:
1799 tmp
= ARRAY_SIZE(cfg
) - 1;
1800 if (wolopts
& WAKE_MAGIC
)
1816 tmp
= ARRAY_SIZE(cfg
);
1820 for (i
= 0; i
< tmp
; i
++) {
1821 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1822 if (wolopts
& cfg
[i
].opt
)
1823 options
|= cfg
[i
].mask
;
1824 RTL_W8(cfg
[i
].reg
, options
);
1827 switch (tp
->mac_version
) {
1828 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_17
:
1829 options
= RTL_R8(Config1
) & ~PMEnable
;
1831 options
|= PMEnable
;
1832 RTL_W8(Config1
, options
);
1835 options
= RTL_R8(Config2
) & ~PME_SIGNAL
;
1837 options
|= PME_SIGNAL
;
1838 RTL_W8(Config2
, options
);
1842 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1845 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1847 struct rtl8169_private
*tp
= netdev_priv(dev
);
1852 tp
->features
|= RTL_FEATURE_WOL
;
1854 tp
->features
&= ~RTL_FEATURE_WOL
;
1855 __rtl8169_set_wol(tp
, wol
->wolopts
);
1857 rtl_unlock_work(tp
);
1859 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1864 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1866 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1869 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1870 struct ethtool_drvinfo
*info
)
1872 struct rtl8169_private
*tp
= netdev_priv(dev
);
1873 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1875 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
1876 strlcpy(info
->version
, RTL8169_VERSION
, sizeof(info
->version
));
1877 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1878 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1879 if (!IS_ERR_OR_NULL(rtl_fw
))
1880 strlcpy(info
->fw_version
, rtl_fw
->version
,
1881 sizeof(info
->fw_version
));
1884 static int rtl8169_get_regs_len(struct net_device
*dev
)
1886 return R8169_REGS_SIZE
;
1889 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1890 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1892 struct rtl8169_private
*tp
= netdev_priv(dev
);
1893 void __iomem
*ioaddr
= tp
->mmio_addr
;
1897 reg
= RTL_R32(TBICSR
);
1898 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1899 (duplex
== DUPLEX_FULL
)) {
1900 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1901 } else if (autoneg
== AUTONEG_ENABLE
)
1902 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1904 netif_warn(tp
, link
, dev
,
1905 "incorrect speed setting refused in TBI mode\n");
1912 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1913 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1915 struct rtl8169_private
*tp
= netdev_priv(dev
);
1916 int giga_ctrl
, bmcr
;
1919 rtl_writephy(tp
, 0x1f, 0x0000);
1921 if (autoneg
== AUTONEG_ENABLE
) {
1924 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1925 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1926 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1928 if (adv
& ADVERTISED_10baseT_Half
)
1929 auto_nego
|= ADVERTISE_10HALF
;
1930 if (adv
& ADVERTISED_10baseT_Full
)
1931 auto_nego
|= ADVERTISE_10FULL
;
1932 if (adv
& ADVERTISED_100baseT_Half
)
1933 auto_nego
|= ADVERTISE_100HALF
;
1934 if (adv
& ADVERTISED_100baseT_Full
)
1935 auto_nego
|= ADVERTISE_100FULL
;
1937 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1939 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1940 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1942 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1943 if (tp
->mii
.supports_gmii
) {
1944 if (adv
& ADVERTISED_1000baseT_Half
)
1945 giga_ctrl
|= ADVERTISE_1000HALF
;
1946 if (adv
& ADVERTISED_1000baseT_Full
)
1947 giga_ctrl
|= ADVERTISE_1000FULL
;
1948 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1949 ADVERTISED_1000baseT_Full
)) {
1950 netif_info(tp
, link
, dev
,
1951 "PHY does not support 1000Mbps\n");
1955 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1957 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1958 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1962 if (speed
== SPEED_10
)
1964 else if (speed
== SPEED_100
)
1965 bmcr
= BMCR_SPEED100
;
1969 if (duplex
== DUPLEX_FULL
)
1970 bmcr
|= BMCR_FULLDPLX
;
1973 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1975 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1976 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1977 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1978 rtl_writephy(tp
, 0x17, 0x2138);
1979 rtl_writephy(tp
, 0x0e, 0x0260);
1981 rtl_writephy(tp
, 0x17, 0x2108);
1982 rtl_writephy(tp
, 0x0e, 0x0000);
1991 static int rtl8169_set_speed(struct net_device
*dev
,
1992 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1994 struct rtl8169_private
*tp
= netdev_priv(dev
);
1997 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
2001 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
2002 (advertising
& ADVERTISED_1000baseT_Full
)) {
2003 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2009 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2011 struct rtl8169_private
*tp
= netdev_priv(dev
);
2014 del_timer_sync(&tp
->timer
);
2017 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
2018 cmd
->duplex
, cmd
->advertising
);
2019 rtl_unlock_work(tp
);
2024 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
2025 netdev_features_t features
)
2027 struct rtl8169_private
*tp
= netdev_priv(dev
);
2029 if (dev
->mtu
> TD_MSS_MAX
)
2030 features
&= ~NETIF_F_ALL_TSO
;
2032 if (dev
->mtu
> JUMBO_1K
&&
2033 !rtl_chip_infos
[tp
->mac_version
].jumbo_tx_csum
)
2034 features
&= ~NETIF_F_IP_CSUM
;
2039 static void __rtl8169_set_features(struct net_device
*dev
,
2040 netdev_features_t features
)
2042 struct rtl8169_private
*tp
= netdev_priv(dev
);
2043 void __iomem
*ioaddr
= tp
->mmio_addr
;
2046 rx_config
= RTL_R32(RxConfig
);
2047 if (features
& NETIF_F_RXALL
)
2048 rx_config
|= (AcceptErr
| AcceptRunt
);
2050 rx_config
&= ~(AcceptErr
| AcceptRunt
);
2052 RTL_W32(RxConfig
, rx_config
);
2054 if (features
& NETIF_F_RXCSUM
)
2055 tp
->cp_cmd
|= RxChkSum
;
2057 tp
->cp_cmd
&= ~RxChkSum
;
2059 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
2060 tp
->cp_cmd
|= RxVlan
;
2062 tp
->cp_cmd
&= ~RxVlan
;
2064 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) & ~(RxVlan
| RxChkSum
);
2066 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2070 static int rtl8169_set_features(struct net_device
*dev
,
2071 netdev_features_t features
)
2073 struct rtl8169_private
*tp
= netdev_priv(dev
);
2075 features
&= NETIF_F_RXALL
| NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_RX
;
2078 if (features
^ dev
->features
)
2079 __rtl8169_set_features(dev
, features
);
2080 rtl_unlock_work(tp
);
2086 static inline u32
rtl8169_tx_vlan_tag(struct sk_buff
*skb
)
2088 return (skb_vlan_tag_present(skb
)) ?
2089 TxVlanTag
| swab16(skb_vlan_tag_get(skb
)) : 0x00;
2092 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
2094 u32 opts2
= le32_to_cpu(desc
->opts2
);
2096 if (opts2
& RxVlanTag
)
2097 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), swab16(opts2
& 0xffff));
2100 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2102 struct rtl8169_private
*tp
= netdev_priv(dev
);
2103 void __iomem
*ioaddr
= tp
->mmio_addr
;
2107 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
2108 cmd
->port
= PORT_FIBRE
;
2109 cmd
->transceiver
= XCVR_INTERNAL
;
2111 status
= RTL_R32(TBICSR
);
2112 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
2113 cmd
->autoneg
= !!(status
& TBINwEnable
);
2115 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
2116 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
2121 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2123 struct rtl8169_private
*tp
= netdev_priv(dev
);
2125 return mii_ethtool_gset(&tp
->mii
, cmd
);
2128 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2130 struct rtl8169_private
*tp
= netdev_priv(dev
);
2134 rc
= tp
->get_settings(dev
, cmd
);
2135 rtl_unlock_work(tp
);
2140 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2143 struct rtl8169_private
*tp
= netdev_priv(dev
);
2144 u32 __iomem
*data
= tp
->mmio_addr
;
2149 for (i
= 0; i
< R8169_REGS_SIZE
; i
+= 4)
2150 memcpy_fromio(dw
++, data
++, 4);
2151 rtl_unlock_work(tp
);
2154 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
2156 struct rtl8169_private
*tp
= netdev_priv(dev
);
2158 return tp
->msg_enable
;
2161 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
2163 struct rtl8169_private
*tp
= netdev_priv(dev
);
2165 tp
->msg_enable
= value
;
2168 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
2175 "tx_single_collisions",
2176 "tx_multi_collisions",
2184 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
2188 return ARRAY_SIZE(rtl8169_gstrings
);
2194 DECLARE_RTL_COND(rtl_counters_cond
)
2196 void __iomem
*ioaddr
= tp
->mmio_addr
;
2198 return RTL_R32(CounterAddrLow
) & (CounterReset
| CounterDump
);
2201 static bool rtl8169_do_counters(struct net_device
*dev
, u32 counter_cmd
)
2203 struct rtl8169_private
*tp
= netdev_priv(dev
);
2204 void __iomem
*ioaddr
= tp
->mmio_addr
;
2205 dma_addr_t paddr
= tp
->counters_phys_addr
;
2209 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
2210 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
2211 RTL_W32(CounterAddrLow
, cmd
);
2212 RTL_W32(CounterAddrLow
, cmd
| counter_cmd
);
2214 ret
= rtl_udelay_loop_wait_low(tp
, &rtl_counters_cond
, 10, 1000);
2216 RTL_W32(CounterAddrLow
, 0);
2217 RTL_W32(CounterAddrHigh
, 0);
2222 static bool rtl8169_reset_counters(struct net_device
*dev
)
2224 struct rtl8169_private
*tp
= netdev_priv(dev
);
2227 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2230 if (tp
->mac_version
< RTL_GIGA_MAC_VER_19
)
2233 return rtl8169_do_counters(dev
, CounterReset
);
2236 static bool rtl8169_update_counters(struct net_device
*dev
)
2238 struct rtl8169_private
*tp
= netdev_priv(dev
);
2239 void __iomem
*ioaddr
= tp
->mmio_addr
;
2242 * Some chips are unable to dump tally counters when the receiver
2245 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
2248 return rtl8169_do_counters(dev
, CounterDump
);
2251 static bool rtl8169_init_counter_offsets(struct net_device
*dev
)
2253 struct rtl8169_private
*tp
= netdev_priv(dev
);
2254 struct rtl8169_counters
*counters
= tp
->counters
;
2258 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2259 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2260 * reset by a power cycle, while the counter values collected by the
2261 * driver are reset at every driver unload/load cycle.
2263 * To make sure the HW values returned by @get_stats64 match the SW
2264 * values, we collect the initial values at first open(*) and use them
2265 * as offsets to normalize the values returned by @get_stats64.
2267 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2268 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2269 * set at open time by rtl_hw_start.
2272 if (tp
->tc_offset
.inited
)
2275 /* If both, reset and update fail, propagate to caller. */
2276 if (rtl8169_reset_counters(dev
))
2279 if (rtl8169_update_counters(dev
))
2282 tp
->tc_offset
.tx_errors
= counters
->tx_errors
;
2283 tp
->tc_offset
.tx_multi_collision
= counters
->tx_multi_collision
;
2284 tp
->tc_offset
.tx_aborted
= counters
->tx_aborted
;
2285 tp
->tc_offset
.inited
= true;
2290 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
2291 struct ethtool_stats
*stats
, u64
*data
)
2293 struct rtl8169_private
*tp
= netdev_priv(dev
);
2294 struct rtl8169_counters
*counters
= tp
->counters
;
2298 rtl8169_update_counters(dev
);
2300 data
[0] = le64_to_cpu(counters
->tx_packets
);
2301 data
[1] = le64_to_cpu(counters
->rx_packets
);
2302 data
[2] = le64_to_cpu(counters
->tx_errors
);
2303 data
[3] = le32_to_cpu(counters
->rx_errors
);
2304 data
[4] = le16_to_cpu(counters
->rx_missed
);
2305 data
[5] = le16_to_cpu(counters
->align_errors
);
2306 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
2307 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
2308 data
[8] = le64_to_cpu(counters
->rx_unicast
);
2309 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
2310 data
[10] = le32_to_cpu(counters
->rx_multicast
);
2311 data
[11] = le16_to_cpu(counters
->tx_aborted
);
2312 data
[12] = le16_to_cpu(counters
->tx_underun
);
2315 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
2319 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
2324 static const struct ethtool_ops rtl8169_ethtool_ops
= {
2325 .get_drvinfo
= rtl8169_get_drvinfo
,
2326 .get_regs_len
= rtl8169_get_regs_len
,
2327 .get_link
= ethtool_op_get_link
,
2328 .get_settings
= rtl8169_get_settings
,
2329 .set_settings
= rtl8169_set_settings
,
2330 .get_msglevel
= rtl8169_get_msglevel
,
2331 .set_msglevel
= rtl8169_set_msglevel
,
2332 .get_regs
= rtl8169_get_regs
,
2333 .get_wol
= rtl8169_get_wol
,
2334 .set_wol
= rtl8169_set_wol
,
2335 .get_strings
= rtl8169_get_strings
,
2336 .get_sset_count
= rtl8169_get_sset_count
,
2337 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
2338 .get_ts_info
= ethtool_op_get_ts_info
,
2341 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
2342 struct net_device
*dev
, u8 default_version
)
2344 void __iomem
*ioaddr
= tp
->mmio_addr
;
2346 * The driver currently handles the 8168Bf and the 8168Be identically
2347 * but they can be identified more specifically through the test below
2350 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2352 * Same thing for the 8101Eb and the 8101Ec:
2354 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2356 static const struct rtl_mac_info
{
2361 /* 8168EP family. */
2362 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51
},
2363 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50
},
2364 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49
},
2367 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46
},
2368 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45
},
2371 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44
},
2372 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42
},
2373 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41
},
2374 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40
},
2377 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38
},
2378 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36
},
2379 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35
},
2382 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
2383 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
2384 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
2385 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
2388 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
2389 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
2390 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
2392 /* 8168DP family. */
2393 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
2394 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
2395 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
2398 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
2399 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
2400 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
2401 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
2402 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
2403 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
2404 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
2405 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
2406 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
2409 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
2410 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
2411 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
2412 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
2415 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39
},
2416 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39
},
2417 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37
},
2418 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
2419 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
2420 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
2421 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
2422 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
2423 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
2424 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
2425 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
2426 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
2427 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
2428 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
2429 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
2430 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
2431 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
2432 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
2433 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
2434 /* FIXME: where did these entries come from ? -- FR */
2435 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
2436 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
2439 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
2440 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
2441 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
2442 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
2443 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
2444 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
2447 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
2449 const struct rtl_mac_info
*p
= mac_info
;
2452 reg
= RTL_R32(TxConfig
);
2453 while ((reg
& p
->mask
) != p
->val
)
2455 tp
->mac_version
= p
->mac_version
;
2457 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
2458 netif_notice(tp
, probe
, dev
,
2459 "unknown MAC, using family default\n");
2460 tp
->mac_version
= default_version
;
2461 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_42
) {
2462 tp
->mac_version
= tp
->mii
.supports_gmii
?
2463 RTL_GIGA_MAC_VER_42
:
2464 RTL_GIGA_MAC_VER_43
;
2465 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_45
) {
2466 tp
->mac_version
= tp
->mii
.supports_gmii
?
2467 RTL_GIGA_MAC_VER_45
:
2468 RTL_GIGA_MAC_VER_47
;
2469 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_46
) {
2470 tp
->mac_version
= tp
->mii
.supports_gmii
?
2471 RTL_GIGA_MAC_VER_46
:
2472 RTL_GIGA_MAC_VER_48
;
2476 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
2478 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
2486 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
2487 const struct phy_reg
*regs
, int len
)
2490 rtl_writephy(tp
, regs
->reg
, regs
->val
);
2495 #define PHY_READ 0x00000000
2496 #define PHY_DATA_OR 0x10000000
2497 #define PHY_DATA_AND 0x20000000
2498 #define PHY_BJMPN 0x30000000
2499 #define PHY_MDIO_CHG 0x40000000
2500 #define PHY_CLEAR_READCOUNT 0x70000000
2501 #define PHY_WRITE 0x80000000
2502 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2503 #define PHY_COMP_EQ_SKIPN 0xa0000000
2504 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2505 #define PHY_WRITE_PREVIOUS 0xc0000000
2506 #define PHY_SKIPN 0xd0000000
2507 #define PHY_DELAY_MS 0xe0000000
2511 char version
[RTL_VER_SIZE
];
2517 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2519 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2521 const struct firmware
*fw
= rtl_fw
->fw
;
2522 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
2523 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2524 char *version
= rtl_fw
->version
;
2527 if (fw
->size
< FW_OPCODE_SIZE
)
2530 if (!fw_info
->magic
) {
2531 size_t i
, size
, start
;
2534 if (fw
->size
< sizeof(*fw_info
))
2537 for (i
= 0; i
< fw
->size
; i
++)
2538 checksum
+= fw
->data
[i
];
2542 start
= le32_to_cpu(fw_info
->fw_start
);
2543 if (start
> fw
->size
)
2546 size
= le32_to_cpu(fw_info
->fw_len
);
2547 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
2550 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
2552 pa
->code
= (__le32
*)(fw
->data
+ start
);
2555 if (fw
->size
% FW_OPCODE_SIZE
)
2558 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
2560 pa
->code
= (__le32
*)fw
->data
;
2561 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
2563 version
[RTL_VER_SIZE
- 1] = 0;
2570 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
2571 struct rtl_fw_phy_action
*pa
)
2576 for (index
= 0; index
< pa
->size
; index
++) {
2577 u32 action
= le32_to_cpu(pa
->code
[index
]);
2578 u32 regno
= (action
& 0x0fff0000) >> 16;
2580 switch(action
& 0xf0000000) {
2585 case PHY_CLEAR_READCOUNT
:
2587 case PHY_WRITE_PREVIOUS
:
2592 if (regno
> index
) {
2593 netif_err(tp
, ifup
, tp
->dev
,
2594 "Out of range of firmware\n");
2598 case PHY_READCOUNT_EQ_SKIP
:
2599 if (index
+ 2 >= pa
->size
) {
2600 netif_err(tp
, ifup
, tp
->dev
,
2601 "Out of range of firmware\n");
2605 case PHY_COMP_EQ_SKIPN
:
2606 case PHY_COMP_NEQ_SKIPN
:
2608 if (index
+ 1 + regno
>= pa
->size
) {
2609 netif_err(tp
, ifup
, tp
->dev
,
2610 "Out of range of firmware\n");
2616 netif_err(tp
, ifup
, tp
->dev
,
2617 "Invalid action 0x%08x\n", action
);
2626 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2628 struct net_device
*dev
= tp
->dev
;
2631 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2632 netif_err(tp
, ifup
, dev
, "invalid firmware\n");
2636 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2642 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2644 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2645 struct mdio_ops org
, *ops
= &tp
->mdio_ops
;
2649 predata
= count
= 0;
2650 org
.write
= ops
->write
;
2651 org
.read
= ops
->read
;
2653 for (index
= 0; index
< pa
->size
; ) {
2654 u32 action
= le32_to_cpu(pa
->code
[index
]);
2655 u32 data
= action
& 0x0000ffff;
2656 u32 regno
= (action
& 0x0fff0000) >> 16;
2661 switch(action
& 0xf0000000) {
2663 predata
= rtl_readphy(tp
, regno
);
2680 ops
->write
= org
.write
;
2681 ops
->read
= org
.read
;
2682 } else if (data
== 1) {
2683 ops
->write
= mac_mcu_write
;
2684 ops
->read
= mac_mcu_read
;
2689 case PHY_CLEAR_READCOUNT
:
2694 rtl_writephy(tp
, regno
, data
);
2697 case PHY_READCOUNT_EQ_SKIP
:
2698 index
+= (count
== data
) ? 2 : 1;
2700 case PHY_COMP_EQ_SKIPN
:
2701 if (predata
== data
)
2705 case PHY_COMP_NEQ_SKIPN
:
2706 if (predata
!= data
)
2710 case PHY_WRITE_PREVIOUS
:
2711 rtl_writephy(tp
, regno
, predata
);
2727 ops
->write
= org
.write
;
2728 ops
->read
= org
.read
;
2731 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2733 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2734 release_firmware(tp
->rtl_fw
->fw
);
2737 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2740 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2742 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2744 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2745 if (!IS_ERR_OR_NULL(rtl_fw
))
2746 rtl_phy_write_fw(tp
, rtl_fw
);
2749 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2751 if (rtl_readphy(tp
, reg
) != val
)
2752 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2754 rtl_apply_firmware(tp
);
2757 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2759 static const struct phy_reg phy_reg_init
[] = {
2821 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2824 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2826 static const struct phy_reg phy_reg_init
[] = {
2832 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2835 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2837 struct pci_dev
*pdev
= tp
->pci_dev
;
2839 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2840 (pdev
->subsystem_device
!= 0xe000))
2843 rtl_writephy(tp
, 0x1f, 0x0001);
2844 rtl_writephy(tp
, 0x10, 0xf01b);
2845 rtl_writephy(tp
, 0x1f, 0x0000);
2848 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2850 static const struct phy_reg phy_reg_init
[] = {
2890 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2892 rtl8169scd_hw_phy_config_quirk(tp
);
2895 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2897 static const struct phy_reg phy_reg_init
[] = {
2945 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2948 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2950 static const struct phy_reg phy_reg_init
[] = {
2955 rtl_writephy(tp
, 0x1f, 0x0001);
2956 rtl_patchphy(tp
, 0x16, 1 << 0);
2958 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2961 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2963 static const struct phy_reg phy_reg_init
[] = {
2969 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2972 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2974 static const struct phy_reg phy_reg_init
[] = {
2982 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2985 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2987 static const struct phy_reg phy_reg_init
[] = {
2993 rtl_writephy(tp
, 0x1f, 0x0000);
2994 rtl_patchphy(tp
, 0x14, 1 << 5);
2995 rtl_patchphy(tp
, 0x0d, 1 << 5);
2997 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3000 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
3002 static const struct phy_reg phy_reg_init
[] = {
3022 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3024 rtl_patchphy(tp
, 0x14, 1 << 5);
3025 rtl_patchphy(tp
, 0x0d, 1 << 5);
3026 rtl_writephy(tp
, 0x1f, 0x0000);
3029 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
3031 static const struct phy_reg phy_reg_init
[] = {
3049 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3051 rtl_patchphy(tp
, 0x16, 1 << 0);
3052 rtl_patchphy(tp
, 0x14, 1 << 5);
3053 rtl_patchphy(tp
, 0x0d, 1 << 5);
3054 rtl_writephy(tp
, 0x1f, 0x0000);
3057 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
3059 static const struct phy_reg phy_reg_init
[] = {
3071 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3073 rtl_patchphy(tp
, 0x16, 1 << 0);
3074 rtl_patchphy(tp
, 0x14, 1 << 5);
3075 rtl_patchphy(tp
, 0x0d, 1 << 5);
3076 rtl_writephy(tp
, 0x1f, 0x0000);
3079 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
3081 rtl8168c_3_hw_phy_config(tp
);
3084 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
3086 static const struct phy_reg phy_reg_init_0
[] = {
3087 /* Channel Estimation */
3108 * Enhance line driver power
3117 * Can not link to 1Gbps with bad cable
3118 * Decrease SNR threshold form 21.07dB to 19.04dB
3127 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
3131 * Fine Tune Switching regulator parameter
3133 rtl_writephy(tp
, 0x1f, 0x0002);
3134 rtl_w0w1_phy(tp
, 0x0b, 0x0010, 0x00ef);
3135 rtl_w0w1_phy(tp
, 0x0c, 0xa200, 0x5d00);
3137 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
3138 static const struct phy_reg phy_reg_init
[] = {
3148 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3150 val
= rtl_readphy(tp
, 0x0d);
3152 if ((val
& 0x00ff) != 0x006c) {
3153 static const u32 set
[] = {
3154 0x0065, 0x0066, 0x0067, 0x0068,
3155 0x0069, 0x006a, 0x006b, 0x006c
3159 rtl_writephy(tp
, 0x1f, 0x0002);
3162 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
3163 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
3166 static const struct phy_reg phy_reg_init
[] = {
3174 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3177 /* RSET couple improve */
3178 rtl_writephy(tp
, 0x1f, 0x0002);
3179 rtl_patchphy(tp
, 0x0d, 0x0300);
3180 rtl_patchphy(tp
, 0x0f, 0x0010);
3182 /* Fine tune PLL performance */
3183 rtl_writephy(tp
, 0x1f, 0x0002);
3184 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
3185 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
3187 rtl_writephy(tp
, 0x1f, 0x0005);
3188 rtl_writephy(tp
, 0x05, 0x001b);
3190 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
3192 rtl_writephy(tp
, 0x1f, 0x0000);
3195 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
3197 static const struct phy_reg phy_reg_init_0
[] = {
3198 /* Channel Estimation */
3219 * Enhance line driver power
3228 * Can not link to 1Gbps with bad cable
3229 * Decrease SNR threshold form 21.07dB to 19.04dB
3238 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
3240 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
3241 static const struct phy_reg phy_reg_init
[] = {
3252 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3254 val
= rtl_readphy(tp
, 0x0d);
3255 if ((val
& 0x00ff) != 0x006c) {
3256 static const u32 set
[] = {
3257 0x0065, 0x0066, 0x0067, 0x0068,
3258 0x0069, 0x006a, 0x006b, 0x006c
3262 rtl_writephy(tp
, 0x1f, 0x0002);
3265 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
3266 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
3269 static const struct phy_reg phy_reg_init
[] = {
3277 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3280 /* Fine tune PLL performance */
3281 rtl_writephy(tp
, 0x1f, 0x0002);
3282 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
3283 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
3285 /* Switching regulator Slew rate */
3286 rtl_writephy(tp
, 0x1f, 0x0002);
3287 rtl_patchphy(tp
, 0x0f, 0x0017);
3289 rtl_writephy(tp
, 0x1f, 0x0005);
3290 rtl_writephy(tp
, 0x05, 0x001b);
3292 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
3294 rtl_writephy(tp
, 0x1f, 0x0000);
3297 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
3299 static const struct phy_reg phy_reg_init
[] = {
3355 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3358 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
3360 static const struct phy_reg phy_reg_init
[] = {
3370 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3371 rtl_patchphy(tp
, 0x0d, 1 << 5);
3374 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
3376 static const struct phy_reg phy_reg_init
[] = {
3377 /* Enable Delay cap */
3383 /* Channel estimation fine tune */
3392 /* Update PFM & 10M TX idle timer */
3404 rtl_apply_firmware(tp
);
3406 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3408 /* DCO enable for 10M IDLE Power */
3409 rtl_writephy(tp
, 0x1f, 0x0007);
3410 rtl_writephy(tp
, 0x1e, 0x0023);
3411 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
3412 rtl_writephy(tp
, 0x1f, 0x0000);
3414 /* For impedance matching */
3415 rtl_writephy(tp
, 0x1f, 0x0002);
3416 rtl_w0w1_phy(tp
, 0x08, 0x8000, 0x7f00);
3417 rtl_writephy(tp
, 0x1f, 0x0000);
3419 /* PHY auto speed down */
3420 rtl_writephy(tp
, 0x1f, 0x0007);
3421 rtl_writephy(tp
, 0x1e, 0x002d);
3422 rtl_w0w1_phy(tp
, 0x18, 0x0050, 0x0000);
3423 rtl_writephy(tp
, 0x1f, 0x0000);
3424 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3426 rtl_writephy(tp
, 0x1f, 0x0005);
3427 rtl_writephy(tp
, 0x05, 0x8b86);
3428 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3429 rtl_writephy(tp
, 0x1f, 0x0000);
3431 rtl_writephy(tp
, 0x1f, 0x0005);
3432 rtl_writephy(tp
, 0x05, 0x8b85);
3433 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3434 rtl_writephy(tp
, 0x1f, 0x0007);
3435 rtl_writephy(tp
, 0x1e, 0x0020);
3436 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x1100);
3437 rtl_writephy(tp
, 0x1f, 0x0006);
3438 rtl_writephy(tp
, 0x00, 0x5a00);
3439 rtl_writephy(tp
, 0x1f, 0x0000);
3440 rtl_writephy(tp
, 0x0d, 0x0007);
3441 rtl_writephy(tp
, 0x0e, 0x003c);
3442 rtl_writephy(tp
, 0x0d, 0x4007);
3443 rtl_writephy(tp
, 0x0e, 0x0000);
3444 rtl_writephy(tp
, 0x0d, 0x0000);
3447 static void rtl_rar_exgmac_set(struct rtl8169_private
*tp
, u8
*addr
)
3450 addr
[0] | (addr
[1] << 8),
3451 addr
[2] | (addr
[3] << 8),
3452 addr
[4] | (addr
[5] << 8)
3454 const struct exgmac_reg e
[] = {
3455 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= w
[0] | (w
[1] << 16) },
3456 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= w
[2] },
3457 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= w
[0] << 16 },
3458 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= w
[1] | (w
[2] << 16) }
3461 rtl_write_exgmac_batch(tp
, e
, ARRAY_SIZE(e
));
3464 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
3466 static const struct phy_reg phy_reg_init
[] = {
3467 /* Enable Delay cap */
3476 /* Channel estimation fine tune */
3493 rtl_apply_firmware(tp
);
3495 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3497 /* For 4-corner performance improve */
3498 rtl_writephy(tp
, 0x1f, 0x0005);
3499 rtl_writephy(tp
, 0x05, 0x8b80);
3500 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
3501 rtl_writephy(tp
, 0x1f, 0x0000);
3503 /* PHY auto speed down */
3504 rtl_writephy(tp
, 0x1f, 0x0004);
3505 rtl_writephy(tp
, 0x1f, 0x0007);
3506 rtl_writephy(tp
, 0x1e, 0x002d);
3507 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
3508 rtl_writephy(tp
, 0x1f, 0x0002);
3509 rtl_writephy(tp
, 0x1f, 0x0000);
3510 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3512 /* improve 10M EEE waveform */
3513 rtl_writephy(tp
, 0x1f, 0x0005);
3514 rtl_writephy(tp
, 0x05, 0x8b86);
3515 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3516 rtl_writephy(tp
, 0x1f, 0x0000);
3518 /* Improve 2-pair detection performance */
3519 rtl_writephy(tp
, 0x1f, 0x0005);
3520 rtl_writephy(tp
, 0x05, 0x8b85);
3521 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3522 rtl_writephy(tp
, 0x1f, 0x0000);
3525 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003, ERIAR_EXGMAC
);
3526 rtl_writephy(tp
, 0x1f, 0x0005);
3527 rtl_writephy(tp
, 0x05, 0x8b85);
3528 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3529 rtl_writephy(tp
, 0x1f, 0x0004);
3530 rtl_writephy(tp
, 0x1f, 0x0007);
3531 rtl_writephy(tp
, 0x1e, 0x0020);
3532 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0100);
3533 rtl_writephy(tp
, 0x1f, 0x0002);
3534 rtl_writephy(tp
, 0x1f, 0x0000);
3535 rtl_writephy(tp
, 0x0d, 0x0007);
3536 rtl_writephy(tp
, 0x0e, 0x003c);
3537 rtl_writephy(tp
, 0x0d, 0x4007);
3538 rtl_writephy(tp
, 0x0e, 0x0000);
3539 rtl_writephy(tp
, 0x0d, 0x0000);
3542 rtl_writephy(tp
, 0x1f, 0x0003);
3543 rtl_w0w1_phy(tp
, 0x19, 0x0000, 0x0001);
3544 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0400);
3545 rtl_writephy(tp
, 0x1f, 0x0000);
3547 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3548 rtl_rar_exgmac_set(tp
, tp
->dev
->dev_addr
);
3551 static void rtl8168f_hw_phy_config(struct rtl8169_private
*tp
)
3553 /* For 4-corner performance improve */
3554 rtl_writephy(tp
, 0x1f, 0x0005);
3555 rtl_writephy(tp
, 0x05, 0x8b80);
3556 rtl_w0w1_phy(tp
, 0x06, 0x0006, 0x0000);
3557 rtl_writephy(tp
, 0x1f, 0x0000);
3559 /* PHY auto speed down */
3560 rtl_writephy(tp
, 0x1f, 0x0007);
3561 rtl_writephy(tp
, 0x1e, 0x002d);
3562 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
3563 rtl_writephy(tp
, 0x1f, 0x0000);
3564 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3566 /* Improve 10M EEE waveform */
3567 rtl_writephy(tp
, 0x1f, 0x0005);
3568 rtl_writephy(tp
, 0x05, 0x8b86);
3569 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3570 rtl_writephy(tp
, 0x1f, 0x0000);
3573 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
3575 static const struct phy_reg phy_reg_init
[] = {
3576 /* Channel estimation fine tune */
3581 /* Modify green table for giga & fnet */
3598 /* Modify green table for 10M */
3604 /* Disable hiimpedance detection (RTCT) */
3610 rtl_apply_firmware(tp
);
3612 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3614 rtl8168f_hw_phy_config(tp
);
3616 /* Improve 2-pair detection performance */
3617 rtl_writephy(tp
, 0x1f, 0x0005);
3618 rtl_writephy(tp
, 0x05, 0x8b85);
3619 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3620 rtl_writephy(tp
, 0x1f, 0x0000);
3623 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3625 rtl_apply_firmware(tp
);
3627 rtl8168f_hw_phy_config(tp
);
3630 static void rtl8411_hw_phy_config(struct rtl8169_private
*tp
)
3632 static const struct phy_reg phy_reg_init
[] = {
3633 /* Channel estimation fine tune */
3638 /* Modify green table for giga & fnet */
3655 /* Modify green table for 10M */
3661 /* Disable hiimpedance detection (RTCT) */
3668 rtl_apply_firmware(tp
);
3670 rtl8168f_hw_phy_config(tp
);
3672 /* Improve 2-pair detection performance */
3673 rtl_writephy(tp
, 0x1f, 0x0005);
3674 rtl_writephy(tp
, 0x05, 0x8b85);
3675 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3676 rtl_writephy(tp
, 0x1f, 0x0000);
3678 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3680 /* Modify green table for giga */
3681 rtl_writephy(tp
, 0x1f, 0x0005);
3682 rtl_writephy(tp
, 0x05, 0x8b54);
3683 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3684 rtl_writephy(tp
, 0x05, 0x8b5d);
3685 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3686 rtl_writephy(tp
, 0x05, 0x8a7c);
3687 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3688 rtl_writephy(tp
, 0x05, 0x8a7f);
3689 rtl_w0w1_phy(tp
, 0x06, 0x0100, 0x0000);
3690 rtl_writephy(tp
, 0x05, 0x8a82);
3691 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3692 rtl_writephy(tp
, 0x05, 0x8a85);
3693 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3694 rtl_writephy(tp
, 0x05, 0x8a88);
3695 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3696 rtl_writephy(tp
, 0x1f, 0x0000);
3698 /* uc same-seed solution */
3699 rtl_writephy(tp
, 0x1f, 0x0005);
3700 rtl_writephy(tp
, 0x05, 0x8b85);
3701 rtl_w0w1_phy(tp
, 0x06, 0x8000, 0x0000);
3702 rtl_writephy(tp
, 0x1f, 0x0000);
3705 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x00, 0x03, ERIAR_EXGMAC
);
3706 rtl_writephy(tp
, 0x1f, 0x0005);
3707 rtl_writephy(tp
, 0x05, 0x8b85);
3708 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3709 rtl_writephy(tp
, 0x1f, 0x0004);
3710 rtl_writephy(tp
, 0x1f, 0x0007);
3711 rtl_writephy(tp
, 0x1e, 0x0020);
3712 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0100);
3713 rtl_writephy(tp
, 0x1f, 0x0000);
3714 rtl_writephy(tp
, 0x0d, 0x0007);
3715 rtl_writephy(tp
, 0x0e, 0x003c);
3716 rtl_writephy(tp
, 0x0d, 0x4007);
3717 rtl_writephy(tp
, 0x0e, 0x0000);
3718 rtl_writephy(tp
, 0x0d, 0x0000);
3721 rtl_writephy(tp
, 0x1f, 0x0003);
3722 rtl_w0w1_phy(tp
, 0x19, 0x0000, 0x0001);
3723 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0400);
3724 rtl_writephy(tp
, 0x1f, 0x0000);
3727 static void rtl8168g_1_hw_phy_config(struct rtl8169_private
*tp
)
3729 rtl_apply_firmware(tp
);
3731 rtl_writephy(tp
, 0x1f, 0x0a46);
3732 if (rtl_readphy(tp
, 0x10) & 0x0100) {
3733 rtl_writephy(tp
, 0x1f, 0x0bcc);
3734 rtl_w0w1_phy(tp
, 0x12, 0x0000, 0x8000);
3736 rtl_writephy(tp
, 0x1f, 0x0bcc);
3737 rtl_w0w1_phy(tp
, 0x12, 0x8000, 0x0000);
3740 rtl_writephy(tp
, 0x1f, 0x0a46);
3741 if (rtl_readphy(tp
, 0x13) & 0x0100) {
3742 rtl_writephy(tp
, 0x1f, 0x0c41);
3743 rtl_w0w1_phy(tp
, 0x15, 0x0002, 0x0000);
3745 rtl_writephy(tp
, 0x1f, 0x0c41);
3746 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0002);
3749 /* Enable PHY auto speed down */
3750 rtl_writephy(tp
, 0x1f, 0x0a44);
3751 rtl_w0w1_phy(tp
, 0x11, 0x000c, 0x0000);
3753 rtl_writephy(tp
, 0x1f, 0x0bcc);
3754 rtl_w0w1_phy(tp
, 0x14, 0x0100, 0x0000);
3755 rtl_writephy(tp
, 0x1f, 0x0a44);
3756 rtl_w0w1_phy(tp
, 0x11, 0x00c0, 0x0000);
3757 rtl_writephy(tp
, 0x1f, 0x0a43);
3758 rtl_writephy(tp
, 0x13, 0x8084);
3759 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x6000);
3760 rtl_w0w1_phy(tp
, 0x10, 0x1003, 0x0000);
3762 /* EEE auto-fallback function */
3763 rtl_writephy(tp
, 0x1f, 0x0a4b);
3764 rtl_w0w1_phy(tp
, 0x11, 0x0004, 0x0000);
3766 /* Enable UC LPF tune function */
3767 rtl_writephy(tp
, 0x1f, 0x0a43);
3768 rtl_writephy(tp
, 0x13, 0x8012);
3769 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3771 rtl_writephy(tp
, 0x1f, 0x0c42);
3772 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
3774 /* Improve SWR Efficiency */
3775 rtl_writephy(tp
, 0x1f, 0x0bcd);
3776 rtl_writephy(tp
, 0x14, 0x5065);
3777 rtl_writephy(tp
, 0x14, 0xd065);
3778 rtl_writephy(tp
, 0x1f, 0x0bc8);
3779 rtl_writephy(tp
, 0x11, 0x5655);
3780 rtl_writephy(tp
, 0x1f, 0x0bcd);
3781 rtl_writephy(tp
, 0x14, 0x1065);
3782 rtl_writephy(tp
, 0x14, 0x9065);
3783 rtl_writephy(tp
, 0x14, 0x1065);
3785 /* Check ALDPS bit, disable it if enabled */
3786 rtl_writephy(tp
, 0x1f, 0x0a43);
3787 if (rtl_readphy(tp
, 0x10) & 0x0004)
3788 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
3790 rtl_writephy(tp
, 0x1f, 0x0000);
3793 static void rtl8168g_2_hw_phy_config(struct rtl8169_private
*tp
)
3795 rtl_apply_firmware(tp
);
3798 static void rtl8168h_1_hw_phy_config(struct rtl8169_private
*tp
)
3803 rtl_apply_firmware(tp
);
3805 /* CHN EST parameters adjust - giga master */
3806 rtl_writephy(tp
, 0x1f, 0x0a43);
3807 rtl_writephy(tp
, 0x13, 0x809b);
3808 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xf800);
3809 rtl_writephy(tp
, 0x13, 0x80a2);
3810 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xff00);
3811 rtl_writephy(tp
, 0x13, 0x80a4);
3812 rtl_w0w1_phy(tp
, 0x14, 0x8500, 0xff00);
3813 rtl_writephy(tp
, 0x13, 0x809c);
3814 rtl_w0w1_phy(tp
, 0x14, 0xbd00, 0xff00);
3815 rtl_writephy(tp
, 0x1f, 0x0000);
3817 /* CHN EST parameters adjust - giga slave */
3818 rtl_writephy(tp
, 0x1f, 0x0a43);
3819 rtl_writephy(tp
, 0x13, 0x80ad);
3820 rtl_w0w1_phy(tp
, 0x14, 0x7000, 0xf800);
3821 rtl_writephy(tp
, 0x13, 0x80b4);
3822 rtl_w0w1_phy(tp
, 0x14, 0x5000, 0xff00);
3823 rtl_writephy(tp
, 0x13, 0x80ac);
3824 rtl_w0w1_phy(tp
, 0x14, 0x4000, 0xff00);
3825 rtl_writephy(tp
, 0x1f, 0x0000);
3827 /* CHN EST parameters adjust - fnet */
3828 rtl_writephy(tp
, 0x1f, 0x0a43);
3829 rtl_writephy(tp
, 0x13, 0x808e);
3830 rtl_w0w1_phy(tp
, 0x14, 0x1200, 0xff00);
3831 rtl_writephy(tp
, 0x13, 0x8090);
3832 rtl_w0w1_phy(tp
, 0x14, 0xe500, 0xff00);
3833 rtl_writephy(tp
, 0x13, 0x8092);
3834 rtl_w0w1_phy(tp
, 0x14, 0x9f00, 0xff00);
3835 rtl_writephy(tp
, 0x1f, 0x0000);
3837 /* enable R-tune & PGA-retune function */
3839 rtl_writephy(tp
, 0x1f, 0x0a46);
3840 data
= rtl_readphy(tp
, 0x13);
3843 dout_tapbin
|= data
;
3844 data
= rtl_readphy(tp
, 0x12);
3847 dout_tapbin
|= data
;
3848 dout_tapbin
= ~(dout_tapbin
^0x08);
3850 dout_tapbin
&= 0xf000;
3851 rtl_writephy(tp
, 0x1f, 0x0a43);
3852 rtl_writephy(tp
, 0x13, 0x827a);
3853 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3854 rtl_writephy(tp
, 0x13, 0x827b);
3855 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3856 rtl_writephy(tp
, 0x13, 0x827c);
3857 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3858 rtl_writephy(tp
, 0x13, 0x827d);
3859 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3861 rtl_writephy(tp
, 0x1f, 0x0a43);
3862 rtl_writephy(tp
, 0x13, 0x0811);
3863 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
3864 rtl_writephy(tp
, 0x1f, 0x0a42);
3865 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
3866 rtl_writephy(tp
, 0x1f, 0x0000);
3868 /* enable GPHY 10M */
3869 rtl_writephy(tp
, 0x1f, 0x0a44);
3870 rtl_w0w1_phy(tp
, 0x11, 0x0800, 0x0000);
3871 rtl_writephy(tp
, 0x1f, 0x0000);
3873 /* SAR ADC performance */
3874 rtl_writephy(tp
, 0x1f, 0x0bca);
3875 rtl_w0w1_phy(tp
, 0x17, 0x4000, 0x3000);
3876 rtl_writephy(tp
, 0x1f, 0x0000);
3878 rtl_writephy(tp
, 0x1f, 0x0a43);
3879 rtl_writephy(tp
, 0x13, 0x803f);
3880 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3881 rtl_writephy(tp
, 0x13, 0x8047);
3882 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3883 rtl_writephy(tp
, 0x13, 0x804f);
3884 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3885 rtl_writephy(tp
, 0x13, 0x8057);
3886 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3887 rtl_writephy(tp
, 0x13, 0x805f);
3888 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3889 rtl_writephy(tp
, 0x13, 0x8067);
3890 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3891 rtl_writephy(tp
, 0x13, 0x806f);
3892 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3893 rtl_writephy(tp
, 0x1f, 0x0000);
3895 /* disable phy pfm mode */
3896 rtl_writephy(tp
, 0x1f, 0x0a44);
3897 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x0080);
3898 rtl_writephy(tp
, 0x1f, 0x0000);
3900 /* Check ALDPS bit, disable it if enabled */
3901 rtl_writephy(tp
, 0x1f, 0x0a43);
3902 if (rtl_readphy(tp
, 0x10) & 0x0004)
3903 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
3905 rtl_writephy(tp
, 0x1f, 0x0000);
3908 static void rtl8168h_2_hw_phy_config(struct rtl8169_private
*tp
)
3910 u16 ioffset_p3
, ioffset_p2
, ioffset_p1
, ioffset_p0
;
3914 rtl_apply_firmware(tp
);
3916 /* CHIN EST parameter update */
3917 rtl_writephy(tp
, 0x1f, 0x0a43);
3918 rtl_writephy(tp
, 0x13, 0x808a);
3919 rtl_w0w1_phy(tp
, 0x14, 0x000a, 0x003f);
3920 rtl_writephy(tp
, 0x1f, 0x0000);
3922 /* enable R-tune & PGA-retune function */
3923 rtl_writephy(tp
, 0x1f, 0x0a43);
3924 rtl_writephy(tp
, 0x13, 0x0811);
3925 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
3926 rtl_writephy(tp
, 0x1f, 0x0a42);
3927 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
3928 rtl_writephy(tp
, 0x1f, 0x0000);
3930 /* enable GPHY 10M */
3931 rtl_writephy(tp
, 0x1f, 0x0a44);
3932 rtl_w0w1_phy(tp
, 0x11, 0x0800, 0x0000);
3933 rtl_writephy(tp
, 0x1f, 0x0000);
3935 r8168_mac_ocp_write(tp
, 0xdd02, 0x807d);
3936 data
= r8168_mac_ocp_read(tp
, 0xdd02);
3937 ioffset_p3
= ((data
& 0x80)>>7);
3940 data
= r8168_mac_ocp_read(tp
, 0xdd00);
3941 ioffset_p3
|= ((data
& (0xe000))>>13);
3942 ioffset_p2
= ((data
& (0x1e00))>>9);
3943 ioffset_p1
= ((data
& (0x01e0))>>5);
3944 ioffset_p0
= ((data
& 0x0010)>>4);
3946 ioffset_p0
|= (data
& (0x07));
3947 data
= (ioffset_p3
<<12)|(ioffset_p2
<<8)|(ioffset_p1
<<4)|(ioffset_p0
);
3949 if ((ioffset_p3
!= 0x0f) || (ioffset_p2
!= 0x0f) ||
3950 (ioffset_p1
!= 0x0f) || (ioffset_p0
!= 0x0f)) {
3951 rtl_writephy(tp
, 0x1f, 0x0bcf);
3952 rtl_writephy(tp
, 0x16, data
);
3953 rtl_writephy(tp
, 0x1f, 0x0000);
3956 /* Modify rlen (TX LPF corner frequency) level */
3957 rtl_writephy(tp
, 0x1f, 0x0bcd);
3958 data
= rtl_readphy(tp
, 0x16);
3963 data
= rlen
| (rlen
<<4) | (rlen
<<8) | (rlen
<<12);
3964 rtl_writephy(tp
, 0x17, data
);
3965 rtl_writephy(tp
, 0x1f, 0x0bcd);
3966 rtl_writephy(tp
, 0x1f, 0x0000);
3968 /* disable phy pfm mode */
3969 rtl_writephy(tp
, 0x1f, 0x0a44);
3970 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x0080);
3971 rtl_writephy(tp
, 0x1f, 0x0000);
3973 /* Check ALDPS bit, disable it if enabled */
3974 rtl_writephy(tp
, 0x1f, 0x0a43);
3975 if (rtl_readphy(tp
, 0x10) & 0x0004)
3976 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
3978 rtl_writephy(tp
, 0x1f, 0x0000);
3981 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private
*tp
)
3983 /* Enable PHY auto speed down */
3984 rtl_writephy(tp
, 0x1f, 0x0a44);
3985 rtl_w0w1_phy(tp
, 0x11, 0x000c, 0x0000);
3986 rtl_writephy(tp
, 0x1f, 0x0000);
3988 /* patch 10M & ALDPS */
3989 rtl_writephy(tp
, 0x1f, 0x0bcc);
3990 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x0100);
3991 rtl_writephy(tp
, 0x1f, 0x0a44);
3992 rtl_w0w1_phy(tp
, 0x11, 0x00c0, 0x0000);
3993 rtl_writephy(tp
, 0x1f, 0x0a43);
3994 rtl_writephy(tp
, 0x13, 0x8084);
3995 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x6000);
3996 rtl_w0w1_phy(tp
, 0x10, 0x1003, 0x0000);
3997 rtl_writephy(tp
, 0x1f, 0x0000);
3999 /* Enable EEE auto-fallback function */
4000 rtl_writephy(tp
, 0x1f, 0x0a4b);
4001 rtl_w0w1_phy(tp
, 0x11, 0x0004, 0x0000);
4002 rtl_writephy(tp
, 0x1f, 0x0000);
4004 /* Enable UC LPF tune function */
4005 rtl_writephy(tp
, 0x1f, 0x0a43);
4006 rtl_writephy(tp
, 0x13, 0x8012);
4007 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
4008 rtl_writephy(tp
, 0x1f, 0x0000);
4010 /* set rg_sel_sdm_rate */
4011 rtl_writephy(tp
, 0x1f, 0x0c42);
4012 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
4013 rtl_writephy(tp
, 0x1f, 0x0000);
4015 /* Check ALDPS bit, disable it if enabled */
4016 rtl_writephy(tp
, 0x1f, 0x0a43);
4017 if (rtl_readphy(tp
, 0x10) & 0x0004)
4018 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
4020 rtl_writephy(tp
, 0x1f, 0x0000);
4023 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private
*tp
)
4025 /* patch 10M & ALDPS */
4026 rtl_writephy(tp
, 0x1f, 0x0bcc);
4027 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x0100);
4028 rtl_writephy(tp
, 0x1f, 0x0a44);
4029 rtl_w0w1_phy(tp
, 0x11, 0x00c0, 0x0000);
4030 rtl_writephy(tp
, 0x1f, 0x0a43);
4031 rtl_writephy(tp
, 0x13, 0x8084);
4032 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x6000);
4033 rtl_w0w1_phy(tp
, 0x10, 0x1003, 0x0000);
4034 rtl_writephy(tp
, 0x1f, 0x0000);
4036 /* Enable UC LPF tune function */
4037 rtl_writephy(tp
, 0x1f, 0x0a43);
4038 rtl_writephy(tp
, 0x13, 0x8012);
4039 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
4040 rtl_writephy(tp
, 0x1f, 0x0000);
4042 /* Set rg_sel_sdm_rate */
4043 rtl_writephy(tp
, 0x1f, 0x0c42);
4044 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
4045 rtl_writephy(tp
, 0x1f, 0x0000);
4047 /* Channel estimation parameters */
4048 rtl_writephy(tp
, 0x1f, 0x0a43);
4049 rtl_writephy(tp
, 0x13, 0x80f3);
4050 rtl_w0w1_phy(tp
, 0x14, 0x8b00, ~0x8bff);
4051 rtl_writephy(tp
, 0x13, 0x80f0);
4052 rtl_w0w1_phy(tp
, 0x14, 0x3a00, ~0x3aff);
4053 rtl_writephy(tp
, 0x13, 0x80ef);
4054 rtl_w0w1_phy(tp
, 0x14, 0x0500, ~0x05ff);
4055 rtl_writephy(tp
, 0x13, 0x80f6);
4056 rtl_w0w1_phy(tp
, 0x14, 0x6e00, ~0x6eff);
4057 rtl_writephy(tp
, 0x13, 0x80ec);
4058 rtl_w0w1_phy(tp
, 0x14, 0x6800, ~0x68ff);
4059 rtl_writephy(tp
, 0x13, 0x80ed);
4060 rtl_w0w1_phy(tp
, 0x14, 0x7c00, ~0x7cff);
4061 rtl_writephy(tp
, 0x13, 0x80f2);
4062 rtl_w0w1_phy(tp
, 0x14, 0xf400, ~0xf4ff);
4063 rtl_writephy(tp
, 0x13, 0x80f4);
4064 rtl_w0w1_phy(tp
, 0x14, 0x8500, ~0x85ff);
4065 rtl_writephy(tp
, 0x1f, 0x0a43);
4066 rtl_writephy(tp
, 0x13, 0x8110);
4067 rtl_w0w1_phy(tp
, 0x14, 0xa800, ~0xa8ff);
4068 rtl_writephy(tp
, 0x13, 0x810f);
4069 rtl_w0w1_phy(tp
, 0x14, 0x1d00, ~0x1dff);
4070 rtl_writephy(tp
, 0x13, 0x8111);
4071 rtl_w0w1_phy(tp
, 0x14, 0xf500, ~0xf5ff);
4072 rtl_writephy(tp
, 0x13, 0x8113);
4073 rtl_w0w1_phy(tp
, 0x14, 0x6100, ~0x61ff);
4074 rtl_writephy(tp
, 0x13, 0x8115);
4075 rtl_w0w1_phy(tp
, 0x14, 0x9200, ~0x92ff);
4076 rtl_writephy(tp
, 0x13, 0x810e);
4077 rtl_w0w1_phy(tp
, 0x14, 0x0400, ~0x04ff);
4078 rtl_writephy(tp
, 0x13, 0x810c);
4079 rtl_w0w1_phy(tp
, 0x14, 0x7c00, ~0x7cff);
4080 rtl_writephy(tp
, 0x13, 0x810b);
4081 rtl_w0w1_phy(tp
, 0x14, 0x5a00, ~0x5aff);
4082 rtl_writephy(tp
, 0x1f, 0x0a43);
4083 rtl_writephy(tp
, 0x13, 0x80d1);
4084 rtl_w0w1_phy(tp
, 0x14, 0xff00, ~0xffff);
4085 rtl_writephy(tp
, 0x13, 0x80cd);
4086 rtl_w0w1_phy(tp
, 0x14, 0x9e00, ~0x9eff);
4087 rtl_writephy(tp
, 0x13, 0x80d3);
4088 rtl_w0w1_phy(tp
, 0x14, 0x0e00, ~0x0eff);
4089 rtl_writephy(tp
, 0x13, 0x80d5);
4090 rtl_w0w1_phy(tp
, 0x14, 0xca00, ~0xcaff);
4091 rtl_writephy(tp
, 0x13, 0x80d7);
4092 rtl_w0w1_phy(tp
, 0x14, 0x8400, ~0x84ff);
4094 /* Force PWM-mode */
4095 rtl_writephy(tp
, 0x1f, 0x0bcd);
4096 rtl_writephy(tp
, 0x14, 0x5065);
4097 rtl_writephy(tp
, 0x14, 0xd065);
4098 rtl_writephy(tp
, 0x1f, 0x0bc8);
4099 rtl_writephy(tp
, 0x12, 0x00ed);
4100 rtl_writephy(tp
, 0x1f, 0x0bcd);
4101 rtl_writephy(tp
, 0x14, 0x1065);
4102 rtl_writephy(tp
, 0x14, 0x9065);
4103 rtl_writephy(tp
, 0x14, 0x1065);
4104 rtl_writephy(tp
, 0x1f, 0x0000);
4106 /* Check ALDPS bit, disable it if enabled */
4107 rtl_writephy(tp
, 0x1f, 0x0a43);
4108 if (rtl_readphy(tp
, 0x10) & 0x0004)
4109 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
4111 rtl_writephy(tp
, 0x1f, 0x0000);
4114 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
4116 static const struct phy_reg phy_reg_init
[] = {
4123 rtl_writephy(tp
, 0x1f, 0x0000);
4124 rtl_patchphy(tp
, 0x11, 1 << 12);
4125 rtl_patchphy(tp
, 0x19, 1 << 13);
4126 rtl_patchphy(tp
, 0x10, 1 << 15);
4128 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
4131 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
4133 static const struct phy_reg phy_reg_init
[] = {
4147 /* Disable ALDPS before ram code */
4148 rtl_writephy(tp
, 0x1f, 0x0000);
4149 rtl_writephy(tp
, 0x18, 0x0310);
4152 rtl_apply_firmware(tp
);
4154 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
4157 static void rtl8402_hw_phy_config(struct rtl8169_private
*tp
)
4159 /* Disable ALDPS before setting firmware */
4160 rtl_writephy(tp
, 0x1f, 0x0000);
4161 rtl_writephy(tp
, 0x18, 0x0310);
4164 rtl_apply_firmware(tp
);
4167 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4168 rtl_writephy(tp
, 0x1f, 0x0004);
4169 rtl_writephy(tp
, 0x10, 0x401f);
4170 rtl_writephy(tp
, 0x19, 0x7030);
4171 rtl_writephy(tp
, 0x1f, 0x0000);
4174 static void rtl8106e_hw_phy_config(struct rtl8169_private
*tp
)
4176 static const struct phy_reg phy_reg_init
[] = {
4183 /* Disable ALDPS before ram code */
4184 rtl_writephy(tp
, 0x1f, 0x0000);
4185 rtl_writephy(tp
, 0x18, 0x0310);
4188 rtl_apply_firmware(tp
);
4190 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4191 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
4193 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4196 static void rtl_hw_phy_config(struct net_device
*dev
)
4198 struct rtl8169_private
*tp
= netdev_priv(dev
);
4200 rtl8169_print_mac_version(tp
);
4202 switch (tp
->mac_version
) {
4203 case RTL_GIGA_MAC_VER_01
:
4205 case RTL_GIGA_MAC_VER_02
:
4206 case RTL_GIGA_MAC_VER_03
:
4207 rtl8169s_hw_phy_config(tp
);
4209 case RTL_GIGA_MAC_VER_04
:
4210 rtl8169sb_hw_phy_config(tp
);
4212 case RTL_GIGA_MAC_VER_05
:
4213 rtl8169scd_hw_phy_config(tp
);
4215 case RTL_GIGA_MAC_VER_06
:
4216 rtl8169sce_hw_phy_config(tp
);
4218 case RTL_GIGA_MAC_VER_07
:
4219 case RTL_GIGA_MAC_VER_08
:
4220 case RTL_GIGA_MAC_VER_09
:
4221 rtl8102e_hw_phy_config(tp
);
4223 case RTL_GIGA_MAC_VER_11
:
4224 rtl8168bb_hw_phy_config(tp
);
4226 case RTL_GIGA_MAC_VER_12
:
4227 rtl8168bef_hw_phy_config(tp
);
4229 case RTL_GIGA_MAC_VER_17
:
4230 rtl8168bef_hw_phy_config(tp
);
4232 case RTL_GIGA_MAC_VER_18
:
4233 rtl8168cp_1_hw_phy_config(tp
);
4235 case RTL_GIGA_MAC_VER_19
:
4236 rtl8168c_1_hw_phy_config(tp
);
4238 case RTL_GIGA_MAC_VER_20
:
4239 rtl8168c_2_hw_phy_config(tp
);
4241 case RTL_GIGA_MAC_VER_21
:
4242 rtl8168c_3_hw_phy_config(tp
);
4244 case RTL_GIGA_MAC_VER_22
:
4245 rtl8168c_4_hw_phy_config(tp
);
4247 case RTL_GIGA_MAC_VER_23
:
4248 case RTL_GIGA_MAC_VER_24
:
4249 rtl8168cp_2_hw_phy_config(tp
);
4251 case RTL_GIGA_MAC_VER_25
:
4252 rtl8168d_1_hw_phy_config(tp
);
4254 case RTL_GIGA_MAC_VER_26
:
4255 rtl8168d_2_hw_phy_config(tp
);
4257 case RTL_GIGA_MAC_VER_27
:
4258 rtl8168d_3_hw_phy_config(tp
);
4260 case RTL_GIGA_MAC_VER_28
:
4261 rtl8168d_4_hw_phy_config(tp
);
4263 case RTL_GIGA_MAC_VER_29
:
4264 case RTL_GIGA_MAC_VER_30
:
4265 rtl8105e_hw_phy_config(tp
);
4267 case RTL_GIGA_MAC_VER_31
:
4270 case RTL_GIGA_MAC_VER_32
:
4271 case RTL_GIGA_MAC_VER_33
:
4272 rtl8168e_1_hw_phy_config(tp
);
4274 case RTL_GIGA_MAC_VER_34
:
4275 rtl8168e_2_hw_phy_config(tp
);
4277 case RTL_GIGA_MAC_VER_35
:
4278 rtl8168f_1_hw_phy_config(tp
);
4280 case RTL_GIGA_MAC_VER_36
:
4281 rtl8168f_2_hw_phy_config(tp
);
4284 case RTL_GIGA_MAC_VER_37
:
4285 rtl8402_hw_phy_config(tp
);
4288 case RTL_GIGA_MAC_VER_38
:
4289 rtl8411_hw_phy_config(tp
);
4292 case RTL_GIGA_MAC_VER_39
:
4293 rtl8106e_hw_phy_config(tp
);
4296 case RTL_GIGA_MAC_VER_40
:
4297 rtl8168g_1_hw_phy_config(tp
);
4299 case RTL_GIGA_MAC_VER_42
:
4300 case RTL_GIGA_MAC_VER_43
:
4301 case RTL_GIGA_MAC_VER_44
:
4302 rtl8168g_2_hw_phy_config(tp
);
4304 case RTL_GIGA_MAC_VER_45
:
4305 case RTL_GIGA_MAC_VER_47
:
4306 rtl8168h_1_hw_phy_config(tp
);
4308 case RTL_GIGA_MAC_VER_46
:
4309 case RTL_GIGA_MAC_VER_48
:
4310 rtl8168h_2_hw_phy_config(tp
);
4313 case RTL_GIGA_MAC_VER_49
:
4314 rtl8168ep_1_hw_phy_config(tp
);
4316 case RTL_GIGA_MAC_VER_50
:
4317 case RTL_GIGA_MAC_VER_51
:
4318 rtl8168ep_2_hw_phy_config(tp
);
4321 case RTL_GIGA_MAC_VER_41
:
4327 static void rtl_phy_work(struct rtl8169_private
*tp
)
4329 struct timer_list
*timer
= &tp
->timer
;
4330 void __iomem
*ioaddr
= tp
->mmio_addr
;
4331 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
4333 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
4335 if (tp
->phy_reset_pending(tp
)) {
4337 * A busy loop could burn quite a few cycles on nowadays CPU.
4338 * Let's delay the execution of the timer for a few ticks.
4344 if (tp
->link_ok(ioaddr
))
4347 netif_dbg(tp
, link
, tp
->dev
, "PHY reset until link up\n");
4349 tp
->phy_reset_enable(tp
);
4352 mod_timer(timer
, jiffies
+ timeout
);
4355 static void rtl_schedule_task(struct rtl8169_private
*tp
, enum rtl_flag flag
)
4357 if (!test_and_set_bit(flag
, tp
->wk
.flags
))
4358 schedule_work(&tp
->wk
.work
);
4361 static void rtl8169_phy_timer(unsigned long __opaque
)
4363 struct net_device
*dev
= (struct net_device
*)__opaque
;
4364 struct rtl8169_private
*tp
= netdev_priv(dev
);
4366 rtl_schedule_task(tp
, RTL_FLAG_TASK_PHY_PENDING
);
4369 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
4370 void __iomem
*ioaddr
)
4373 pci_release_regions(pdev
);
4374 pci_clear_mwi(pdev
);
4375 pci_disable_device(pdev
);
4379 DECLARE_RTL_COND(rtl_phy_reset_cond
)
4381 return tp
->phy_reset_pending(tp
);
4384 static void rtl8169_phy_reset(struct net_device
*dev
,
4385 struct rtl8169_private
*tp
)
4387 tp
->phy_reset_enable(tp
);
4388 rtl_msleep_loop_wait_low(tp
, &rtl_phy_reset_cond
, 1, 100);
4391 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
4393 void __iomem
*ioaddr
= tp
->mmio_addr
;
4395 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
4396 (RTL_R8(PHYstatus
) & TBI_Enable
);
4399 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
4401 void __iomem
*ioaddr
= tp
->mmio_addr
;
4403 rtl_hw_phy_config(dev
);
4405 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
4406 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4410 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
4412 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
4413 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
4415 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
4416 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4418 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4419 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
4422 rtl8169_phy_reset(dev
, tp
);
4424 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
4425 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4426 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
4427 (tp
->mii
.supports_gmii
?
4428 ADVERTISED_1000baseT_Half
|
4429 ADVERTISED_1000baseT_Full
: 0));
4431 if (rtl_tbi_enabled(tp
))
4432 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
4435 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
4437 void __iomem
*ioaddr
= tp
->mmio_addr
;
4441 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4443 RTL_W32(MAC4
, addr
[4] | addr
[5] << 8);
4446 RTL_W32(MAC0
, addr
[0] | addr
[1] << 8 | addr
[2] << 16 | addr
[3] << 24);
4449 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
4450 rtl_rar_exgmac_set(tp
, addr
);
4452 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4454 rtl_unlock_work(tp
);
4457 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
4459 struct rtl8169_private
*tp
= netdev_priv(dev
);
4460 struct sockaddr
*addr
= p
;
4462 if (!is_valid_ether_addr(addr
->sa_data
))
4463 return -EADDRNOTAVAIL
;
4465 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
4467 rtl_rar_set(tp
, dev
->dev_addr
);
4472 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4474 struct rtl8169_private
*tp
= netdev_priv(dev
);
4475 struct mii_ioctl_data
*data
= if_mii(ifr
);
4477 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
4480 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
4481 struct mii_ioctl_data
*data
, int cmd
)
4485 data
->phy_id
= 32; /* Internal PHY */
4489 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
4493 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
4499 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
4504 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
4506 if (tp
->features
& RTL_FEATURE_MSI
) {
4507 pci_disable_msi(pdev
);
4508 tp
->features
&= ~RTL_FEATURE_MSI
;
4512 static void rtl_init_mdio_ops(struct rtl8169_private
*tp
)
4514 struct mdio_ops
*ops
= &tp
->mdio_ops
;
4516 switch (tp
->mac_version
) {
4517 case RTL_GIGA_MAC_VER_27
:
4518 ops
->write
= r8168dp_1_mdio_write
;
4519 ops
->read
= r8168dp_1_mdio_read
;
4521 case RTL_GIGA_MAC_VER_28
:
4522 case RTL_GIGA_MAC_VER_31
:
4523 ops
->write
= r8168dp_2_mdio_write
;
4524 ops
->read
= r8168dp_2_mdio_read
;
4526 case RTL_GIGA_MAC_VER_40
:
4527 case RTL_GIGA_MAC_VER_41
:
4528 case RTL_GIGA_MAC_VER_42
:
4529 case RTL_GIGA_MAC_VER_43
:
4530 case RTL_GIGA_MAC_VER_44
:
4531 case RTL_GIGA_MAC_VER_45
:
4532 case RTL_GIGA_MAC_VER_46
:
4533 case RTL_GIGA_MAC_VER_47
:
4534 case RTL_GIGA_MAC_VER_48
:
4535 case RTL_GIGA_MAC_VER_49
:
4536 case RTL_GIGA_MAC_VER_50
:
4537 case RTL_GIGA_MAC_VER_51
:
4538 ops
->write
= r8168g_mdio_write
;
4539 ops
->read
= r8168g_mdio_read
;
4542 ops
->write
= r8169_mdio_write
;
4543 ops
->read
= r8169_mdio_read
;
4548 static void rtl_speed_down(struct rtl8169_private
*tp
)
4553 rtl_writephy(tp
, 0x1f, 0x0000);
4554 lpa
= rtl_readphy(tp
, MII_LPA
);
4556 if (lpa
& (LPA_10HALF
| LPA_10FULL
))
4557 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
;
4558 else if (lpa
& (LPA_100HALF
| LPA_100FULL
))
4559 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4560 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4562 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4563 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
4564 (tp
->mii
.supports_gmii
?
4565 ADVERTISED_1000baseT_Half
|
4566 ADVERTISED_1000baseT_Full
: 0);
4568 rtl8169_set_speed(tp
->dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
4572 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
4574 void __iomem
*ioaddr
= tp
->mmio_addr
;
4576 switch (tp
->mac_version
) {
4577 case RTL_GIGA_MAC_VER_25
:
4578 case RTL_GIGA_MAC_VER_26
:
4579 case RTL_GIGA_MAC_VER_29
:
4580 case RTL_GIGA_MAC_VER_30
:
4581 case RTL_GIGA_MAC_VER_32
:
4582 case RTL_GIGA_MAC_VER_33
:
4583 case RTL_GIGA_MAC_VER_34
:
4584 case RTL_GIGA_MAC_VER_37
:
4585 case RTL_GIGA_MAC_VER_38
:
4586 case RTL_GIGA_MAC_VER_39
:
4587 case RTL_GIGA_MAC_VER_40
:
4588 case RTL_GIGA_MAC_VER_41
:
4589 case RTL_GIGA_MAC_VER_42
:
4590 case RTL_GIGA_MAC_VER_43
:
4591 case RTL_GIGA_MAC_VER_44
:
4592 case RTL_GIGA_MAC_VER_45
:
4593 case RTL_GIGA_MAC_VER_46
:
4594 case RTL_GIGA_MAC_VER_47
:
4595 case RTL_GIGA_MAC_VER_48
:
4596 case RTL_GIGA_MAC_VER_49
:
4597 case RTL_GIGA_MAC_VER_50
:
4598 case RTL_GIGA_MAC_VER_51
:
4599 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
4600 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
4607 static bool rtl_wol_pll_power_down(struct rtl8169_private
*tp
)
4609 if (!(__rtl8169_get_wol(tp
) & WAKE_ANY
))
4613 rtl_wol_suspend_quirk(tp
);
4618 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
4620 rtl_writephy(tp
, 0x1f, 0x0000);
4621 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
4624 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
4626 rtl_writephy(tp
, 0x1f, 0x0000);
4627 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
4630 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
4632 void __iomem
*ioaddr
= tp
->mmio_addr
;
4634 if (rtl_wol_pll_power_down(tp
))
4637 r810x_phy_power_down(tp
);
4639 switch (tp
->mac_version
) {
4640 case RTL_GIGA_MAC_VER_07
:
4641 case RTL_GIGA_MAC_VER_08
:
4642 case RTL_GIGA_MAC_VER_09
:
4643 case RTL_GIGA_MAC_VER_10
:
4644 case RTL_GIGA_MAC_VER_13
:
4645 case RTL_GIGA_MAC_VER_16
:
4648 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4653 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
4655 void __iomem
*ioaddr
= tp
->mmio_addr
;
4657 r810x_phy_power_up(tp
);
4659 switch (tp
->mac_version
) {
4660 case RTL_GIGA_MAC_VER_07
:
4661 case RTL_GIGA_MAC_VER_08
:
4662 case RTL_GIGA_MAC_VER_09
:
4663 case RTL_GIGA_MAC_VER_10
:
4664 case RTL_GIGA_MAC_VER_13
:
4665 case RTL_GIGA_MAC_VER_16
:
4667 case RTL_GIGA_MAC_VER_47
:
4668 case RTL_GIGA_MAC_VER_48
:
4669 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
4672 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
4677 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
4679 rtl_writephy(tp
, 0x1f, 0x0000);
4680 switch (tp
->mac_version
) {
4681 case RTL_GIGA_MAC_VER_11
:
4682 case RTL_GIGA_MAC_VER_12
:
4683 case RTL_GIGA_MAC_VER_17
:
4684 case RTL_GIGA_MAC_VER_18
:
4685 case RTL_GIGA_MAC_VER_19
:
4686 case RTL_GIGA_MAC_VER_20
:
4687 case RTL_GIGA_MAC_VER_21
:
4688 case RTL_GIGA_MAC_VER_22
:
4689 case RTL_GIGA_MAC_VER_23
:
4690 case RTL_GIGA_MAC_VER_24
:
4691 case RTL_GIGA_MAC_VER_25
:
4692 case RTL_GIGA_MAC_VER_26
:
4693 case RTL_GIGA_MAC_VER_27
:
4694 case RTL_GIGA_MAC_VER_28
:
4695 case RTL_GIGA_MAC_VER_31
:
4696 rtl_writephy(tp
, 0x0e, 0x0000);
4701 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
4704 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
4706 rtl_writephy(tp
, 0x1f, 0x0000);
4707 switch (tp
->mac_version
) {
4708 case RTL_GIGA_MAC_VER_32
:
4709 case RTL_GIGA_MAC_VER_33
:
4710 case RTL_GIGA_MAC_VER_40
:
4711 case RTL_GIGA_MAC_VER_41
:
4712 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
4715 case RTL_GIGA_MAC_VER_11
:
4716 case RTL_GIGA_MAC_VER_12
:
4717 case RTL_GIGA_MAC_VER_17
:
4718 case RTL_GIGA_MAC_VER_18
:
4719 case RTL_GIGA_MAC_VER_19
:
4720 case RTL_GIGA_MAC_VER_20
:
4721 case RTL_GIGA_MAC_VER_21
:
4722 case RTL_GIGA_MAC_VER_22
:
4723 case RTL_GIGA_MAC_VER_23
:
4724 case RTL_GIGA_MAC_VER_24
:
4725 case RTL_GIGA_MAC_VER_25
:
4726 case RTL_GIGA_MAC_VER_26
:
4727 case RTL_GIGA_MAC_VER_27
:
4728 case RTL_GIGA_MAC_VER_28
:
4729 case RTL_GIGA_MAC_VER_31
:
4730 rtl_writephy(tp
, 0x0e, 0x0200);
4732 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
4737 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
4739 void __iomem
*ioaddr
= tp
->mmio_addr
;
4741 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4742 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4743 tp
->mac_version
== RTL_GIGA_MAC_VER_31
||
4744 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
4745 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
4746 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) &&
4747 r8168_check_dash(tp
)) {
4751 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
4752 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
4753 (RTL_R16(CPlusCmd
) & ASF
)) {
4757 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
4758 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
4759 rtl_ephy_write(tp
, 0x19, 0xff64);
4761 if (rtl_wol_pll_power_down(tp
))
4764 r8168_phy_power_down(tp
);
4766 switch (tp
->mac_version
) {
4767 case RTL_GIGA_MAC_VER_25
:
4768 case RTL_GIGA_MAC_VER_26
:
4769 case RTL_GIGA_MAC_VER_27
:
4770 case RTL_GIGA_MAC_VER_28
:
4771 case RTL_GIGA_MAC_VER_31
:
4772 case RTL_GIGA_MAC_VER_32
:
4773 case RTL_GIGA_MAC_VER_33
:
4774 case RTL_GIGA_MAC_VER_44
:
4775 case RTL_GIGA_MAC_VER_45
:
4776 case RTL_GIGA_MAC_VER_46
:
4777 case RTL_GIGA_MAC_VER_50
:
4778 case RTL_GIGA_MAC_VER_51
:
4779 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4781 case RTL_GIGA_MAC_VER_40
:
4782 case RTL_GIGA_MAC_VER_41
:
4783 case RTL_GIGA_MAC_VER_49
:
4784 rtl_w0w1_eri(tp
, 0x1a8, ERIAR_MASK_1111
, 0x00000000,
4785 0xfc000000, ERIAR_EXGMAC
);
4786 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4791 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
4793 void __iomem
*ioaddr
= tp
->mmio_addr
;
4795 switch (tp
->mac_version
) {
4796 case RTL_GIGA_MAC_VER_25
:
4797 case RTL_GIGA_MAC_VER_26
:
4798 case RTL_GIGA_MAC_VER_27
:
4799 case RTL_GIGA_MAC_VER_28
:
4800 case RTL_GIGA_MAC_VER_31
:
4801 case RTL_GIGA_MAC_VER_32
:
4802 case RTL_GIGA_MAC_VER_33
:
4803 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
4805 case RTL_GIGA_MAC_VER_44
:
4806 case RTL_GIGA_MAC_VER_45
:
4807 case RTL_GIGA_MAC_VER_46
:
4808 case RTL_GIGA_MAC_VER_50
:
4809 case RTL_GIGA_MAC_VER_51
:
4810 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
4812 case RTL_GIGA_MAC_VER_40
:
4813 case RTL_GIGA_MAC_VER_41
:
4814 case RTL_GIGA_MAC_VER_49
:
4815 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
4816 rtl_w0w1_eri(tp
, 0x1a8, ERIAR_MASK_1111
, 0xfc000000,
4817 0x00000000, ERIAR_EXGMAC
);
4821 r8168_phy_power_up(tp
);
4824 static void rtl_generic_op(struct rtl8169_private
*tp
,
4825 void (*op
)(struct rtl8169_private
*))
4831 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
4833 rtl_generic_op(tp
, tp
->pll_power_ops
.down
);
4836 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
4838 rtl_generic_op(tp
, tp
->pll_power_ops
.up
);
4841 static void rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
4843 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
4845 switch (tp
->mac_version
) {
4846 case RTL_GIGA_MAC_VER_07
:
4847 case RTL_GIGA_MAC_VER_08
:
4848 case RTL_GIGA_MAC_VER_09
:
4849 case RTL_GIGA_MAC_VER_10
:
4850 case RTL_GIGA_MAC_VER_16
:
4851 case RTL_GIGA_MAC_VER_29
:
4852 case RTL_GIGA_MAC_VER_30
:
4853 case RTL_GIGA_MAC_VER_37
:
4854 case RTL_GIGA_MAC_VER_39
:
4855 case RTL_GIGA_MAC_VER_43
:
4856 case RTL_GIGA_MAC_VER_47
:
4857 case RTL_GIGA_MAC_VER_48
:
4858 ops
->down
= r810x_pll_power_down
;
4859 ops
->up
= r810x_pll_power_up
;
4862 case RTL_GIGA_MAC_VER_11
:
4863 case RTL_GIGA_MAC_VER_12
:
4864 case RTL_GIGA_MAC_VER_17
:
4865 case RTL_GIGA_MAC_VER_18
:
4866 case RTL_GIGA_MAC_VER_19
:
4867 case RTL_GIGA_MAC_VER_20
:
4868 case RTL_GIGA_MAC_VER_21
:
4869 case RTL_GIGA_MAC_VER_22
:
4870 case RTL_GIGA_MAC_VER_23
:
4871 case RTL_GIGA_MAC_VER_24
:
4872 case RTL_GIGA_MAC_VER_25
:
4873 case RTL_GIGA_MAC_VER_26
:
4874 case RTL_GIGA_MAC_VER_27
:
4875 case RTL_GIGA_MAC_VER_28
:
4876 case RTL_GIGA_MAC_VER_31
:
4877 case RTL_GIGA_MAC_VER_32
:
4878 case RTL_GIGA_MAC_VER_33
:
4879 case RTL_GIGA_MAC_VER_34
:
4880 case RTL_GIGA_MAC_VER_35
:
4881 case RTL_GIGA_MAC_VER_36
:
4882 case RTL_GIGA_MAC_VER_38
:
4883 case RTL_GIGA_MAC_VER_40
:
4884 case RTL_GIGA_MAC_VER_41
:
4885 case RTL_GIGA_MAC_VER_42
:
4886 case RTL_GIGA_MAC_VER_44
:
4887 case RTL_GIGA_MAC_VER_45
:
4888 case RTL_GIGA_MAC_VER_46
:
4889 case RTL_GIGA_MAC_VER_49
:
4890 case RTL_GIGA_MAC_VER_50
:
4891 case RTL_GIGA_MAC_VER_51
:
4892 ops
->down
= r8168_pll_power_down
;
4893 ops
->up
= r8168_pll_power_up
;
4903 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
4905 void __iomem
*ioaddr
= tp
->mmio_addr
;
4907 switch (tp
->mac_version
) {
4908 case RTL_GIGA_MAC_VER_01
:
4909 case RTL_GIGA_MAC_VER_02
:
4910 case RTL_GIGA_MAC_VER_03
:
4911 case RTL_GIGA_MAC_VER_04
:
4912 case RTL_GIGA_MAC_VER_05
:
4913 case RTL_GIGA_MAC_VER_06
:
4914 case RTL_GIGA_MAC_VER_10
:
4915 case RTL_GIGA_MAC_VER_11
:
4916 case RTL_GIGA_MAC_VER_12
:
4917 case RTL_GIGA_MAC_VER_13
:
4918 case RTL_GIGA_MAC_VER_14
:
4919 case RTL_GIGA_MAC_VER_15
:
4920 case RTL_GIGA_MAC_VER_16
:
4921 case RTL_GIGA_MAC_VER_17
:
4922 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
4924 case RTL_GIGA_MAC_VER_18
:
4925 case RTL_GIGA_MAC_VER_19
:
4926 case RTL_GIGA_MAC_VER_20
:
4927 case RTL_GIGA_MAC_VER_21
:
4928 case RTL_GIGA_MAC_VER_22
:
4929 case RTL_GIGA_MAC_VER_23
:
4930 case RTL_GIGA_MAC_VER_24
:
4931 case RTL_GIGA_MAC_VER_34
:
4932 case RTL_GIGA_MAC_VER_35
:
4933 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
4935 case RTL_GIGA_MAC_VER_40
:
4936 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
4938 case RTL_GIGA_MAC_VER_41
:
4939 case RTL_GIGA_MAC_VER_42
:
4940 case RTL_GIGA_MAC_VER_43
:
4941 case RTL_GIGA_MAC_VER_44
:
4942 case RTL_GIGA_MAC_VER_45
:
4943 case RTL_GIGA_MAC_VER_46
:
4944 case RTL_GIGA_MAC_VER_47
:
4945 case RTL_GIGA_MAC_VER_48
:
4946 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
4948 case RTL_GIGA_MAC_VER_49
:
4949 case RTL_GIGA_MAC_VER_50
:
4950 case RTL_GIGA_MAC_VER_51
:
4951 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
4954 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
4959 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4961 tp
->dirty_tx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4964 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
4966 void __iomem
*ioaddr
= tp
->mmio_addr
;
4968 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4969 rtl_generic_op(tp
, tp
->jumbo_ops
.enable
);
4970 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4973 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
4975 void __iomem
*ioaddr
= tp
->mmio_addr
;
4977 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4978 rtl_generic_op(tp
, tp
->jumbo_ops
.disable
);
4979 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4982 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
4984 void __iomem
*ioaddr
= tp
->mmio_addr
;
4986 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
4987 RTL_W8(Config4
, RTL_R8(Config4
) | Jumbo_En1
);
4988 rtl_tx_performance_tweak(tp
->pci_dev
, PCI_EXP_DEVCTL_READRQ_512B
);
4991 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
4993 void __iomem
*ioaddr
= tp
->mmio_addr
;
4995 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
4996 RTL_W8(Config4
, RTL_R8(Config4
) & ~Jumbo_En1
);
4997 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5000 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
5002 void __iomem
*ioaddr
= tp
->mmio_addr
;
5004 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
5007 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
5009 void __iomem
*ioaddr
= tp
->mmio_addr
;
5011 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
5014 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
5016 void __iomem
*ioaddr
= tp
->mmio_addr
;
5018 RTL_W8(MaxTxPacketSize
, 0x3f);
5019 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
5020 RTL_W8(Config4
, RTL_R8(Config4
) | 0x01);
5021 rtl_tx_performance_tweak(tp
->pci_dev
, PCI_EXP_DEVCTL_READRQ_512B
);
5024 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
5026 void __iomem
*ioaddr
= tp
->mmio_addr
;
5028 RTL_W8(MaxTxPacketSize
, 0x0c);
5029 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
5030 RTL_W8(Config4
, RTL_R8(Config4
) & ~0x01);
5031 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5034 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
5036 rtl_tx_performance_tweak(tp
->pci_dev
,
5037 PCI_EXP_DEVCTL_READRQ_512B
| PCI_EXP_DEVCTL_NOSNOOP_EN
);
5040 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
5042 rtl_tx_performance_tweak(tp
->pci_dev
,
5043 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
5046 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
5048 void __iomem
*ioaddr
= tp
->mmio_addr
;
5050 r8168b_0_hw_jumbo_enable(tp
);
5052 RTL_W8(Config4
, RTL_R8(Config4
) | (1 << 0));
5055 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
5057 void __iomem
*ioaddr
= tp
->mmio_addr
;
5059 r8168b_0_hw_jumbo_disable(tp
);
5061 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
5064 static void rtl_init_jumbo_ops(struct rtl8169_private
*tp
)
5066 struct jumbo_ops
*ops
= &tp
->jumbo_ops
;
5068 switch (tp
->mac_version
) {
5069 case RTL_GIGA_MAC_VER_11
:
5070 ops
->disable
= r8168b_0_hw_jumbo_disable
;
5071 ops
->enable
= r8168b_0_hw_jumbo_enable
;
5073 case RTL_GIGA_MAC_VER_12
:
5074 case RTL_GIGA_MAC_VER_17
:
5075 ops
->disable
= r8168b_1_hw_jumbo_disable
;
5076 ops
->enable
= r8168b_1_hw_jumbo_enable
;
5078 case RTL_GIGA_MAC_VER_18
: /* Wild guess. Needs info from Realtek. */
5079 case RTL_GIGA_MAC_VER_19
:
5080 case RTL_GIGA_MAC_VER_20
:
5081 case RTL_GIGA_MAC_VER_21
: /* Wild guess. Needs info from Realtek. */
5082 case RTL_GIGA_MAC_VER_22
:
5083 case RTL_GIGA_MAC_VER_23
:
5084 case RTL_GIGA_MAC_VER_24
:
5085 case RTL_GIGA_MAC_VER_25
:
5086 case RTL_GIGA_MAC_VER_26
:
5087 ops
->disable
= r8168c_hw_jumbo_disable
;
5088 ops
->enable
= r8168c_hw_jumbo_enable
;
5090 case RTL_GIGA_MAC_VER_27
:
5091 case RTL_GIGA_MAC_VER_28
:
5092 ops
->disable
= r8168dp_hw_jumbo_disable
;
5093 ops
->enable
= r8168dp_hw_jumbo_enable
;
5095 case RTL_GIGA_MAC_VER_31
: /* Wild guess. Needs info from Realtek. */
5096 case RTL_GIGA_MAC_VER_32
:
5097 case RTL_GIGA_MAC_VER_33
:
5098 case RTL_GIGA_MAC_VER_34
:
5099 ops
->disable
= r8168e_hw_jumbo_disable
;
5100 ops
->enable
= r8168e_hw_jumbo_enable
;
5104 * No action needed for jumbo frames with 8169.
5105 * No jumbo for 810x at all.
5107 case RTL_GIGA_MAC_VER_40
:
5108 case RTL_GIGA_MAC_VER_41
:
5109 case RTL_GIGA_MAC_VER_42
:
5110 case RTL_GIGA_MAC_VER_43
:
5111 case RTL_GIGA_MAC_VER_44
:
5112 case RTL_GIGA_MAC_VER_45
:
5113 case RTL_GIGA_MAC_VER_46
:
5114 case RTL_GIGA_MAC_VER_47
:
5115 case RTL_GIGA_MAC_VER_48
:
5116 case RTL_GIGA_MAC_VER_49
:
5117 case RTL_GIGA_MAC_VER_50
:
5118 case RTL_GIGA_MAC_VER_51
:
5120 ops
->disable
= NULL
;
5126 DECLARE_RTL_COND(rtl_chipcmd_cond
)
5128 void __iomem
*ioaddr
= tp
->mmio_addr
;
5130 return RTL_R8(ChipCmd
) & CmdReset
;
5133 static void rtl_hw_reset(struct rtl8169_private
*tp
)
5135 void __iomem
*ioaddr
= tp
->mmio_addr
;
5137 RTL_W8(ChipCmd
, CmdReset
);
5139 rtl_udelay_loop_wait_low(tp
, &rtl_chipcmd_cond
, 100, 100);
5142 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
5144 struct rtl_fw
*rtl_fw
;
5148 name
= rtl_lookup_firmware_name(tp
);
5150 goto out_no_firmware
;
5152 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
5156 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
5160 rc
= rtl_check_firmware(tp
, rtl_fw
);
5162 goto err_release_firmware
;
5164 tp
->rtl_fw
= rtl_fw
;
5168 err_release_firmware
:
5169 release_firmware(rtl_fw
->fw
);
5173 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
5180 static void rtl_request_firmware(struct rtl8169_private
*tp
)
5182 if (IS_ERR(tp
->rtl_fw
))
5183 rtl_request_uncached_firmware(tp
);
5186 static void rtl_rx_close(struct rtl8169_private
*tp
)
5188 void __iomem
*ioaddr
= tp
->mmio_addr
;
5190 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
5193 DECLARE_RTL_COND(rtl_npq_cond
)
5195 void __iomem
*ioaddr
= tp
->mmio_addr
;
5197 return RTL_R8(TxPoll
) & NPQ
;
5200 DECLARE_RTL_COND(rtl_txcfg_empty_cond
)
5202 void __iomem
*ioaddr
= tp
->mmio_addr
;
5204 return RTL_R32(TxConfig
) & TXCFG_EMPTY
;
5207 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
5209 void __iomem
*ioaddr
= tp
->mmio_addr
;
5211 /* Disable interrupts */
5212 rtl8169_irq_mask_and_ack(tp
);
5216 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
5217 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
5218 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
5219 rtl_udelay_loop_wait_low(tp
, &rtl_npq_cond
, 20, 42*42);
5220 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
5221 tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
5222 tp
->mac_version
== RTL_GIGA_MAC_VER_36
||
5223 tp
->mac_version
== RTL_GIGA_MAC_VER_37
||
5224 tp
->mac_version
== RTL_GIGA_MAC_VER_38
||
5225 tp
->mac_version
== RTL_GIGA_MAC_VER_40
||
5226 tp
->mac_version
== RTL_GIGA_MAC_VER_41
||
5227 tp
->mac_version
== RTL_GIGA_MAC_VER_42
||
5228 tp
->mac_version
== RTL_GIGA_MAC_VER_43
||
5229 tp
->mac_version
== RTL_GIGA_MAC_VER_44
||
5230 tp
->mac_version
== RTL_GIGA_MAC_VER_45
||
5231 tp
->mac_version
== RTL_GIGA_MAC_VER_46
||
5232 tp
->mac_version
== RTL_GIGA_MAC_VER_47
||
5233 tp
->mac_version
== RTL_GIGA_MAC_VER_48
||
5234 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
5235 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
5236 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) {
5237 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
5238 rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 666);
5240 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
5247 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
5249 void __iomem
*ioaddr
= tp
->mmio_addr
;
5251 /* Set DMA burst size and Interframe Gap Time */
5252 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
5253 (InterFrameGap
<< TxInterFrameGapShift
));
5256 static void rtl_hw_start(struct net_device
*dev
)
5258 struct rtl8169_private
*tp
= netdev_priv(dev
);
5262 rtl_irq_enable_all(tp
);
5265 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
5266 void __iomem
*ioaddr
)
5269 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5270 * register to be written before TxDescAddrLow to work.
5271 * Switching from MMIO to I/O access fixes the issue as well.
5273 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
5274 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
5275 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
5276 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
5279 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
5283 cmd
= RTL_R16(CPlusCmd
);
5284 RTL_W16(CPlusCmd
, cmd
);
5288 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
5290 /* Low hurts. Let's disable the filtering. */
5291 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
5294 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
5296 static const struct rtl_cfg2_info
{
5301 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
5302 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
5303 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
5304 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
5306 const struct rtl_cfg2_info
*p
= cfg2_info
;
5310 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
5311 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
5312 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
5313 RTL_W32(0x7c, p
->val
);
5319 static void rtl_set_rx_mode(struct net_device
*dev
)
5321 struct rtl8169_private
*tp
= netdev_priv(dev
);
5322 void __iomem
*ioaddr
= tp
->mmio_addr
;
5323 u32 mc_filter
[2]; /* Multicast hash filter */
5327 if (dev
->flags
& IFF_PROMISC
) {
5328 /* Unconditionally log net taps. */
5329 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5331 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5333 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5334 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5335 (dev
->flags
& IFF_ALLMULTI
)) {
5336 /* Too many to filter perfectly -- accept all multicasts. */
5337 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5338 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5340 struct netdev_hw_addr
*ha
;
5342 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5343 mc_filter
[1] = mc_filter
[0] = 0;
5344 netdev_for_each_mc_addr(ha
, dev
) {
5345 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5346 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
5347 rx_mode
|= AcceptMulticast
;
5351 if (dev
->features
& NETIF_F_RXALL
)
5352 rx_mode
|= (AcceptErr
| AcceptRunt
);
5354 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
5356 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
5357 u32 data
= mc_filter
[0];
5359 mc_filter
[0] = swab32(mc_filter
[1]);
5360 mc_filter
[1] = swab32(data
);
5363 if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
)
5364 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5366 RTL_W32(MAR0
+ 4, mc_filter
[1]);
5367 RTL_W32(MAR0
+ 0, mc_filter
[0]);
5369 RTL_W32(RxConfig
, tmp
);
5372 static void rtl_hw_start_8169(struct net_device
*dev
)
5374 struct rtl8169_private
*tp
= netdev_priv(dev
);
5375 void __iomem
*ioaddr
= tp
->mmio_addr
;
5376 struct pci_dev
*pdev
= tp
->pci_dev
;
5378 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
5379 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
5380 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
5383 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5384 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
5385 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5386 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
5387 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
5388 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5392 RTL_W8(EarlyTxThres
, NoEarlyTx
);
5394 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
5396 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
5397 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5398 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
5399 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
5400 rtl_set_rx_tx_config_registers(tp
);
5402 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
5404 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5405 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
5406 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5407 "Bit-3 and bit-14 MUST be 1\n");
5408 tp
->cp_cmd
|= (1 << 14);
5411 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5413 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
5416 * Undocumented corner. Supposedly:
5417 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5419 RTL_W16(IntrMitigate
, 0x0000);
5421 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
5423 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
5424 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
5425 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
5426 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
5427 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5428 rtl_set_rx_tx_config_registers(tp
);
5431 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5433 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5436 RTL_W32(RxMissed
, 0);
5438 rtl_set_rx_mode(dev
);
5440 /* no early-rx interrupts */
5441 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
5444 static void rtl_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5446 if (tp
->csi_ops
.write
)
5447 tp
->csi_ops
.write(tp
, addr
, value
);
5450 static u32
rtl_csi_read(struct rtl8169_private
*tp
, int addr
)
5452 return tp
->csi_ops
.read
? tp
->csi_ops
.read(tp
, addr
) : ~0;
5455 static void rtl_csi_access_enable(struct rtl8169_private
*tp
, u32 bits
)
5459 csi
= rtl_csi_read(tp
, 0x070c) & 0x00ffffff;
5460 rtl_csi_write(tp
, 0x070c, csi
| bits
);
5463 static void rtl_csi_access_enable_1(struct rtl8169_private
*tp
)
5465 rtl_csi_access_enable(tp
, 0x17000000);
5468 static void rtl_csi_access_enable_2(struct rtl8169_private
*tp
)
5470 rtl_csi_access_enable(tp
, 0x27000000);
5473 DECLARE_RTL_COND(rtl_csiar_cond
)
5475 void __iomem
*ioaddr
= tp
->mmio_addr
;
5477 return RTL_R32(CSIAR
) & CSIAR_FLAG
;
5480 static void r8169_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5482 void __iomem
*ioaddr
= tp
->mmio_addr
;
5484 RTL_W32(CSIDR
, value
);
5485 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5486 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5488 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5491 static u32
r8169_csi_read(struct rtl8169_private
*tp
, int addr
)
5493 void __iomem
*ioaddr
= tp
->mmio_addr
;
5495 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
5496 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5498 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5499 RTL_R32(CSIDR
) : ~0;
5502 static void r8402_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5504 void __iomem
*ioaddr
= tp
->mmio_addr
;
5506 RTL_W32(CSIDR
, value
);
5507 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5508 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
|
5511 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5514 static u32
r8402_csi_read(struct rtl8169_private
*tp
, int addr
)
5516 void __iomem
*ioaddr
= tp
->mmio_addr
;
5518 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) | CSIAR_FUNC_NIC
|
5519 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5521 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5522 RTL_R32(CSIDR
) : ~0;
5525 static void r8411_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5527 void __iomem
*ioaddr
= tp
->mmio_addr
;
5529 RTL_W32(CSIDR
, value
);
5530 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5531 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
|
5534 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5537 static u32
r8411_csi_read(struct rtl8169_private
*tp
, int addr
)
5539 void __iomem
*ioaddr
= tp
->mmio_addr
;
5541 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) | CSIAR_FUNC_NIC2
|
5542 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5544 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5545 RTL_R32(CSIDR
) : ~0;
5548 static void rtl_init_csi_ops(struct rtl8169_private
*tp
)
5550 struct csi_ops
*ops
= &tp
->csi_ops
;
5552 switch (tp
->mac_version
) {
5553 case RTL_GIGA_MAC_VER_01
:
5554 case RTL_GIGA_MAC_VER_02
:
5555 case RTL_GIGA_MAC_VER_03
:
5556 case RTL_GIGA_MAC_VER_04
:
5557 case RTL_GIGA_MAC_VER_05
:
5558 case RTL_GIGA_MAC_VER_06
:
5559 case RTL_GIGA_MAC_VER_10
:
5560 case RTL_GIGA_MAC_VER_11
:
5561 case RTL_GIGA_MAC_VER_12
:
5562 case RTL_GIGA_MAC_VER_13
:
5563 case RTL_GIGA_MAC_VER_14
:
5564 case RTL_GIGA_MAC_VER_15
:
5565 case RTL_GIGA_MAC_VER_16
:
5566 case RTL_GIGA_MAC_VER_17
:
5571 case RTL_GIGA_MAC_VER_37
:
5572 case RTL_GIGA_MAC_VER_38
:
5573 ops
->write
= r8402_csi_write
;
5574 ops
->read
= r8402_csi_read
;
5577 case RTL_GIGA_MAC_VER_44
:
5578 ops
->write
= r8411_csi_write
;
5579 ops
->read
= r8411_csi_read
;
5583 ops
->write
= r8169_csi_write
;
5584 ops
->read
= r8169_csi_read
;
5590 unsigned int offset
;
5595 static void rtl_ephy_init(struct rtl8169_private
*tp
, const struct ephy_info
*e
,
5601 w
= (rtl_ephy_read(tp
, e
->offset
) & ~e
->mask
) | e
->bits
;
5602 rtl_ephy_write(tp
, e
->offset
, w
);
5607 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
5609 pcie_capability_clear_word(pdev
, PCI_EXP_LNKCTL
,
5610 PCI_EXP_LNKCTL_CLKREQ_EN
);
5613 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
5615 pcie_capability_set_word(pdev
, PCI_EXP_LNKCTL
,
5616 PCI_EXP_LNKCTL_CLKREQ_EN
);
5619 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private
*tp
, bool enable
)
5621 void __iomem
*ioaddr
= tp
->mmio_addr
;
5624 data
= RTL_R8(Config3
);
5629 data
&= ~Rdy_to_L23
;
5631 RTL_W8(Config3
, data
);
5634 #define R8168_CPCMD_QUIRK_MASK (\
5645 static void rtl_hw_start_8168bb(struct rtl8169_private
*tp
)
5647 void __iomem
*ioaddr
= tp
->mmio_addr
;
5648 struct pci_dev
*pdev
= tp
->pci_dev
;
5650 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5652 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5654 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
5655 rtl_tx_performance_tweak(pdev
, (0x5 << MAX_READ_REQUEST_SHIFT
) |
5656 PCI_EXP_DEVCTL_NOSNOOP_EN
);
5660 static void rtl_hw_start_8168bef(struct rtl8169_private
*tp
)
5662 void __iomem
*ioaddr
= tp
->mmio_addr
;
5664 rtl_hw_start_8168bb(tp
);
5666 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5668 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
5671 static void __rtl_hw_start_8168cp(struct rtl8169_private
*tp
)
5673 void __iomem
*ioaddr
= tp
->mmio_addr
;
5674 struct pci_dev
*pdev
= tp
->pci_dev
;
5676 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
5678 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5680 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5681 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5683 rtl_disable_clock_request(pdev
);
5685 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5688 static void rtl_hw_start_8168cp_1(struct rtl8169_private
*tp
)
5690 static const struct ephy_info e_info_8168cp
[] = {
5691 { 0x01, 0, 0x0001 },
5692 { 0x02, 0x0800, 0x1000 },
5693 { 0x03, 0, 0x0042 },
5694 { 0x06, 0x0080, 0x0000 },
5698 rtl_csi_access_enable_2(tp
);
5700 rtl_ephy_init(tp
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
5702 __rtl_hw_start_8168cp(tp
);
5705 static void rtl_hw_start_8168cp_2(struct rtl8169_private
*tp
)
5707 void __iomem
*ioaddr
= tp
->mmio_addr
;
5708 struct pci_dev
*pdev
= tp
->pci_dev
;
5710 rtl_csi_access_enable_2(tp
);
5712 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5714 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5715 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5717 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5720 static void rtl_hw_start_8168cp_3(struct rtl8169_private
*tp
)
5722 void __iomem
*ioaddr
= tp
->mmio_addr
;
5723 struct pci_dev
*pdev
= tp
->pci_dev
;
5725 rtl_csi_access_enable_2(tp
);
5727 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5730 RTL_W8(DBG_REG
, 0x20);
5732 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5734 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5735 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5737 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5740 static void rtl_hw_start_8168c_1(struct rtl8169_private
*tp
)
5742 void __iomem
*ioaddr
= tp
->mmio_addr
;
5743 static const struct ephy_info e_info_8168c_1
[] = {
5744 { 0x02, 0x0800, 0x1000 },
5745 { 0x03, 0, 0x0002 },
5746 { 0x06, 0x0080, 0x0000 }
5749 rtl_csi_access_enable_2(tp
);
5751 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
5753 rtl_ephy_init(tp
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
5755 __rtl_hw_start_8168cp(tp
);
5758 static void rtl_hw_start_8168c_2(struct rtl8169_private
*tp
)
5760 static const struct ephy_info e_info_8168c_2
[] = {
5761 { 0x01, 0, 0x0001 },
5762 { 0x03, 0x0400, 0x0220 }
5765 rtl_csi_access_enable_2(tp
);
5767 rtl_ephy_init(tp
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
5769 __rtl_hw_start_8168cp(tp
);
5772 static void rtl_hw_start_8168c_3(struct rtl8169_private
*tp
)
5774 rtl_hw_start_8168c_2(tp
);
5777 static void rtl_hw_start_8168c_4(struct rtl8169_private
*tp
)
5779 rtl_csi_access_enable_2(tp
);
5781 __rtl_hw_start_8168cp(tp
);
5784 static void rtl_hw_start_8168d(struct rtl8169_private
*tp
)
5786 void __iomem
*ioaddr
= tp
->mmio_addr
;
5787 struct pci_dev
*pdev
= tp
->pci_dev
;
5789 rtl_csi_access_enable_2(tp
);
5791 rtl_disable_clock_request(pdev
);
5793 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5795 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5796 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5798 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5801 static void rtl_hw_start_8168dp(struct rtl8169_private
*tp
)
5803 void __iomem
*ioaddr
= tp
->mmio_addr
;
5804 struct pci_dev
*pdev
= tp
->pci_dev
;
5806 rtl_csi_access_enable_1(tp
);
5808 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5809 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5811 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5813 rtl_disable_clock_request(pdev
);
5816 static void rtl_hw_start_8168d_4(struct rtl8169_private
*tp
)
5818 void __iomem
*ioaddr
= tp
->mmio_addr
;
5819 struct pci_dev
*pdev
= tp
->pci_dev
;
5820 static const struct ephy_info e_info_8168d_4
[] = {
5822 { 0x19, 0x20, 0x50 },
5827 rtl_csi_access_enable_1(tp
);
5829 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5831 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5833 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
5834 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
5837 w
= rtl_ephy_read(tp
, e
->offset
);
5838 rtl_ephy_write(tp
, 0x03, (w
& e
->mask
) | e
->bits
);
5841 rtl_enable_clock_request(pdev
);
5844 static void rtl_hw_start_8168e_1(struct rtl8169_private
*tp
)
5846 void __iomem
*ioaddr
= tp
->mmio_addr
;
5847 struct pci_dev
*pdev
= tp
->pci_dev
;
5848 static const struct ephy_info e_info_8168e_1
[] = {
5849 { 0x00, 0x0200, 0x0100 },
5850 { 0x00, 0x0000, 0x0004 },
5851 { 0x06, 0x0002, 0x0001 },
5852 { 0x06, 0x0000, 0x0030 },
5853 { 0x07, 0x0000, 0x2000 },
5854 { 0x00, 0x0000, 0x0020 },
5855 { 0x03, 0x5800, 0x2000 },
5856 { 0x03, 0x0000, 0x0001 },
5857 { 0x01, 0x0800, 0x1000 },
5858 { 0x07, 0x0000, 0x4000 },
5859 { 0x1e, 0x0000, 0x2000 },
5860 { 0x19, 0xffff, 0xfe6c },
5861 { 0x0a, 0x0000, 0x0040 }
5864 rtl_csi_access_enable_2(tp
);
5866 rtl_ephy_init(tp
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
5868 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5869 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5871 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5873 rtl_disable_clock_request(pdev
);
5875 /* Reset tx FIFO pointer */
5876 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
5877 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
5879 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5882 static void rtl_hw_start_8168e_2(struct rtl8169_private
*tp
)
5884 void __iomem
*ioaddr
= tp
->mmio_addr
;
5885 struct pci_dev
*pdev
= tp
->pci_dev
;
5886 static const struct ephy_info e_info_8168e_2
[] = {
5887 { 0x09, 0x0000, 0x0080 },
5888 { 0x19, 0x0000, 0x0224 }
5891 rtl_csi_access_enable_1(tp
);
5893 rtl_ephy_init(tp
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
5895 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5896 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5898 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5899 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5900 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
5901 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5902 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
5903 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
5904 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5905 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00, ERIAR_EXGMAC
);
5907 RTL_W8(MaxTxPacketSize
, EarlySize
);
5909 rtl_disable_clock_request(pdev
);
5911 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5912 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
5914 /* Adjust EEE LED frequency */
5915 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
5917 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5918 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
5919 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5922 static void rtl_hw_start_8168f(struct rtl8169_private
*tp
)
5924 void __iomem
*ioaddr
= tp
->mmio_addr
;
5925 struct pci_dev
*pdev
= tp
->pci_dev
;
5927 rtl_csi_access_enable_2(tp
);
5929 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5931 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5932 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5933 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
5934 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5935 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
5936 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
5937 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5938 rtl_w0w1_eri(tp
, 0x1d0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5939 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
5940 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x00000060, ERIAR_EXGMAC
);
5942 RTL_W8(MaxTxPacketSize
, EarlySize
);
5944 rtl_disable_clock_request(pdev
);
5946 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5947 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
5948 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5949 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
5950 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5953 static void rtl_hw_start_8168f_1(struct rtl8169_private
*tp
)
5955 void __iomem
*ioaddr
= tp
->mmio_addr
;
5956 static const struct ephy_info e_info_8168f_1
[] = {
5957 { 0x06, 0x00c0, 0x0020 },
5958 { 0x08, 0x0001, 0x0002 },
5959 { 0x09, 0x0000, 0x0080 },
5960 { 0x19, 0x0000, 0x0224 }
5963 rtl_hw_start_8168f(tp
);
5965 rtl_ephy_init(tp
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
5967 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00, ERIAR_EXGMAC
);
5969 /* Adjust EEE LED frequency */
5970 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
5973 static void rtl_hw_start_8411(struct rtl8169_private
*tp
)
5975 static const struct ephy_info e_info_8168f_1
[] = {
5976 { 0x06, 0x00c0, 0x0020 },
5977 { 0x0f, 0xffff, 0x5200 },
5978 { 0x1e, 0x0000, 0x4000 },
5979 { 0x19, 0x0000, 0x0224 }
5982 rtl_hw_start_8168f(tp
);
5983 rtl_pcie_state_l2l3_enable(tp
, false);
5985 rtl_ephy_init(tp
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
5987 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0x0000, ERIAR_EXGMAC
);
5990 static void rtl_hw_start_8168g(struct rtl8169_private
*tp
)
5992 void __iomem
*ioaddr
= tp
->mmio_addr
;
5993 struct pci_dev
*pdev
= tp
->pci_dev
;
5995 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5997 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x080002, ERIAR_EXGMAC
);
5998 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x38, ERIAR_EXGMAC
);
5999 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x48, ERIAR_EXGMAC
);
6000 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6002 rtl_csi_access_enable_1(tp
);
6004 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6006 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6007 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6008 rtl_eri_write(tp
, 0x2f8, ERIAR_MASK_0011
, 0x1d8f, ERIAR_EXGMAC
);
6010 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
6011 RTL_W8(MaxTxPacketSize
, EarlySize
);
6013 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6014 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6016 /* Adjust EEE LED frequency */
6017 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6019 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06, ERIAR_EXGMAC
);
6020 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, 0x1000, ERIAR_EXGMAC
);
6022 rtl_pcie_state_l2l3_enable(tp
, false);
6025 static void rtl_hw_start_8168g_1(struct rtl8169_private
*tp
)
6027 void __iomem
*ioaddr
= tp
->mmio_addr
;
6028 static const struct ephy_info e_info_8168g_1
[] = {
6029 { 0x00, 0x0000, 0x0008 },
6030 { 0x0c, 0x37d0, 0x0820 },
6031 { 0x1e, 0x0000, 0x0001 },
6032 { 0x19, 0x8000, 0x0000 }
6035 rtl_hw_start_8168g(tp
);
6037 /* disable aspm and clock request before access ephy */
6038 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6039 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6040 rtl_ephy_init(tp
, e_info_8168g_1
, ARRAY_SIZE(e_info_8168g_1
));
6043 static void rtl_hw_start_8168g_2(struct rtl8169_private
*tp
)
6045 void __iomem
*ioaddr
= tp
->mmio_addr
;
6046 static const struct ephy_info e_info_8168g_2
[] = {
6047 { 0x00, 0x0000, 0x0008 },
6048 { 0x0c, 0x3df0, 0x0200 },
6049 { 0x19, 0xffff, 0xfc00 },
6050 { 0x1e, 0xffff, 0x20eb }
6053 rtl_hw_start_8168g(tp
);
6055 /* disable aspm and clock request before access ephy */
6056 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6057 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6058 rtl_ephy_init(tp
, e_info_8168g_2
, ARRAY_SIZE(e_info_8168g_2
));
6061 static void rtl_hw_start_8411_2(struct rtl8169_private
*tp
)
6063 void __iomem
*ioaddr
= tp
->mmio_addr
;
6064 static const struct ephy_info e_info_8411_2
[] = {
6065 { 0x00, 0x0000, 0x0008 },
6066 { 0x0c, 0x3df0, 0x0200 },
6067 { 0x0f, 0xffff, 0x5200 },
6068 { 0x19, 0x0020, 0x0000 },
6069 { 0x1e, 0x0000, 0x2000 }
6072 rtl_hw_start_8168g(tp
);
6074 /* disable aspm and clock request before access ephy */
6075 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6076 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6077 rtl_ephy_init(tp
, e_info_8411_2
, ARRAY_SIZE(e_info_8411_2
));
6080 static void rtl_hw_start_8168h_1(struct rtl8169_private
*tp
)
6082 void __iomem
*ioaddr
= tp
->mmio_addr
;
6083 struct pci_dev
*pdev
= tp
->pci_dev
;
6086 static const struct ephy_info e_info_8168h_1
[] = {
6087 { 0x1e, 0x0800, 0x0001 },
6088 { 0x1d, 0x0000, 0x0800 },
6089 { 0x05, 0xffff, 0x2089 },
6090 { 0x06, 0xffff, 0x5881 },
6091 { 0x04, 0xffff, 0x154a },
6092 { 0x01, 0xffff, 0x068b }
6095 /* disable aspm and clock request before access ephy */
6096 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6097 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6098 rtl_ephy_init(tp
, e_info_8168h_1
, ARRAY_SIZE(e_info_8168h_1
));
6100 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6102 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x00080002, ERIAR_EXGMAC
);
6103 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x38, ERIAR_EXGMAC
);
6104 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x48, ERIAR_EXGMAC
);
6105 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6107 rtl_csi_access_enable_1(tp
);
6109 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6111 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6112 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6114 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_1111
, 0x0010, 0x00, ERIAR_EXGMAC
);
6116 rtl_w0w1_eri(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f00, 0x00, ERIAR_EXGMAC
);
6118 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87, ERIAR_EXGMAC
);
6120 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
6121 RTL_W8(MaxTxPacketSize
, EarlySize
);
6123 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6124 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6126 /* Adjust EEE LED frequency */
6127 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6129 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6130 RTL_W8(MISC_1
, RTL_R8(MISC_1
) & ~PFM_D3COLD_EN
);
6132 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~TX_10M_PS_EN
);
6134 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, 0x1000, ERIAR_EXGMAC
);
6136 rtl_pcie_state_l2l3_enable(tp
, false);
6138 rtl_writephy(tp
, 0x1f, 0x0c42);
6139 rg_saw_cnt
= (rtl_readphy(tp
, 0x13) & 0x3fff);
6140 rtl_writephy(tp
, 0x1f, 0x0000);
6141 if (rg_saw_cnt
> 0) {
6144 sw_cnt_1ms_ini
= 16000000/rg_saw_cnt
;
6145 sw_cnt_1ms_ini
&= 0x0fff;
6146 data
= r8168_mac_ocp_read(tp
, 0xd412);
6148 data
|= sw_cnt_1ms_ini
;
6149 r8168_mac_ocp_write(tp
, 0xd412, data
);
6152 data
= r8168_mac_ocp_read(tp
, 0xe056);
6155 r8168_mac_ocp_write(tp
, 0xe056, data
);
6157 data
= r8168_mac_ocp_read(tp
, 0xe052);
6160 r8168_mac_ocp_write(tp
, 0xe052, data
);
6162 data
= r8168_mac_ocp_read(tp
, 0xe0d6);
6165 r8168_mac_ocp_write(tp
, 0xe0d6, data
);
6167 data
= r8168_mac_ocp_read(tp
, 0xd420);
6170 r8168_mac_ocp_write(tp
, 0xd420, data
);
6172 r8168_mac_ocp_write(tp
, 0xe63e, 0x0001);
6173 r8168_mac_ocp_write(tp
, 0xe63e, 0x0000);
6174 r8168_mac_ocp_write(tp
, 0xc094, 0x0000);
6175 r8168_mac_ocp_write(tp
, 0xc09e, 0x0000);
6178 static void rtl_hw_start_8168ep(struct rtl8169_private
*tp
)
6180 void __iomem
*ioaddr
= tp
->mmio_addr
;
6181 struct pci_dev
*pdev
= tp
->pci_dev
;
6183 rtl8168ep_stop_cmac(tp
);
6185 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6187 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x00080002, ERIAR_EXGMAC
);
6188 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x2f, ERIAR_EXGMAC
);
6189 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x5f, ERIAR_EXGMAC
);
6190 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6192 rtl_csi_access_enable_1(tp
);
6194 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6196 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6197 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6199 rtl_w0w1_eri(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f80, 0x00, ERIAR_EXGMAC
);
6201 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87, ERIAR_EXGMAC
);
6203 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
6204 RTL_W8(MaxTxPacketSize
, EarlySize
);
6206 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6207 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6209 /* Adjust EEE LED frequency */
6210 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6212 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06, ERIAR_EXGMAC
);
6214 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~TX_10M_PS_EN
);
6216 rtl_pcie_state_l2l3_enable(tp
, false);
6219 static void rtl_hw_start_8168ep_1(struct rtl8169_private
*tp
)
6221 void __iomem
*ioaddr
= tp
->mmio_addr
;
6222 static const struct ephy_info e_info_8168ep_1
[] = {
6223 { 0x00, 0xffff, 0x10ab },
6224 { 0x06, 0xffff, 0xf030 },
6225 { 0x08, 0xffff, 0x2006 },
6226 { 0x0d, 0xffff, 0x1666 },
6227 { 0x0c, 0x3ff0, 0x0000 }
6230 /* disable aspm and clock request before access ephy */
6231 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6232 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6233 rtl_ephy_init(tp
, e_info_8168ep_1
, ARRAY_SIZE(e_info_8168ep_1
));
6235 rtl_hw_start_8168ep(tp
);
6238 static void rtl_hw_start_8168ep_2(struct rtl8169_private
*tp
)
6240 void __iomem
*ioaddr
= tp
->mmio_addr
;
6241 static const struct ephy_info e_info_8168ep_2
[] = {
6242 { 0x00, 0xffff, 0x10a3 },
6243 { 0x19, 0xffff, 0xfc00 },
6244 { 0x1e, 0xffff, 0x20ea }
6247 /* disable aspm and clock request before access ephy */
6248 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6249 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6250 rtl_ephy_init(tp
, e_info_8168ep_2
, ARRAY_SIZE(e_info_8168ep_2
));
6252 rtl_hw_start_8168ep(tp
);
6254 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6255 RTL_W8(MISC_1
, RTL_R8(MISC_1
) & ~PFM_D3COLD_EN
);
6258 static void rtl_hw_start_8168ep_3(struct rtl8169_private
*tp
)
6260 void __iomem
*ioaddr
= tp
->mmio_addr
;
6262 static const struct ephy_info e_info_8168ep_3
[] = {
6263 { 0x00, 0xffff, 0x10a3 },
6264 { 0x19, 0xffff, 0x7c00 },
6265 { 0x1e, 0xffff, 0x20eb },
6266 { 0x0d, 0xffff, 0x1666 }
6269 /* disable aspm and clock request before access ephy */
6270 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6271 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6272 rtl_ephy_init(tp
, e_info_8168ep_3
, ARRAY_SIZE(e_info_8168ep_3
));
6274 rtl_hw_start_8168ep(tp
);
6276 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6277 RTL_W8(MISC_1
, RTL_R8(MISC_1
) & ~PFM_D3COLD_EN
);
6279 data
= r8168_mac_ocp_read(tp
, 0xd3e2);
6282 r8168_mac_ocp_write(tp
, 0xd3e2, data
);
6284 data
= r8168_mac_ocp_read(tp
, 0xd3e4);
6286 r8168_mac_ocp_write(tp
, 0xd3e4, data
);
6288 data
= r8168_mac_ocp_read(tp
, 0xe860);
6290 r8168_mac_ocp_write(tp
, 0xe860, data
);
6293 static void rtl_hw_start_8168(struct net_device
*dev
)
6295 struct rtl8169_private
*tp
= netdev_priv(dev
);
6296 void __iomem
*ioaddr
= tp
->mmio_addr
;
6298 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
6300 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6302 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
6304 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
6306 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
6308 RTL_W16(IntrMitigate
, 0x5151);
6310 /* Work around for RxFIFO overflow. */
6311 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
6312 tp
->event_slow
|= RxFIFOOver
| PCSTimeout
;
6313 tp
->event_slow
&= ~RxOverflow
;
6316 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
6318 rtl_set_rx_tx_config_registers(tp
);
6322 switch (tp
->mac_version
) {
6323 case RTL_GIGA_MAC_VER_11
:
6324 rtl_hw_start_8168bb(tp
);
6327 case RTL_GIGA_MAC_VER_12
:
6328 case RTL_GIGA_MAC_VER_17
:
6329 rtl_hw_start_8168bef(tp
);
6332 case RTL_GIGA_MAC_VER_18
:
6333 rtl_hw_start_8168cp_1(tp
);
6336 case RTL_GIGA_MAC_VER_19
:
6337 rtl_hw_start_8168c_1(tp
);
6340 case RTL_GIGA_MAC_VER_20
:
6341 rtl_hw_start_8168c_2(tp
);
6344 case RTL_GIGA_MAC_VER_21
:
6345 rtl_hw_start_8168c_3(tp
);
6348 case RTL_GIGA_MAC_VER_22
:
6349 rtl_hw_start_8168c_4(tp
);
6352 case RTL_GIGA_MAC_VER_23
:
6353 rtl_hw_start_8168cp_2(tp
);
6356 case RTL_GIGA_MAC_VER_24
:
6357 rtl_hw_start_8168cp_3(tp
);
6360 case RTL_GIGA_MAC_VER_25
:
6361 case RTL_GIGA_MAC_VER_26
:
6362 case RTL_GIGA_MAC_VER_27
:
6363 rtl_hw_start_8168d(tp
);
6366 case RTL_GIGA_MAC_VER_28
:
6367 rtl_hw_start_8168d_4(tp
);
6370 case RTL_GIGA_MAC_VER_31
:
6371 rtl_hw_start_8168dp(tp
);
6374 case RTL_GIGA_MAC_VER_32
:
6375 case RTL_GIGA_MAC_VER_33
:
6376 rtl_hw_start_8168e_1(tp
);
6378 case RTL_GIGA_MAC_VER_34
:
6379 rtl_hw_start_8168e_2(tp
);
6382 case RTL_GIGA_MAC_VER_35
:
6383 case RTL_GIGA_MAC_VER_36
:
6384 rtl_hw_start_8168f_1(tp
);
6387 case RTL_GIGA_MAC_VER_38
:
6388 rtl_hw_start_8411(tp
);
6391 case RTL_GIGA_MAC_VER_40
:
6392 case RTL_GIGA_MAC_VER_41
:
6393 rtl_hw_start_8168g_1(tp
);
6395 case RTL_GIGA_MAC_VER_42
:
6396 rtl_hw_start_8168g_2(tp
);
6399 case RTL_GIGA_MAC_VER_44
:
6400 rtl_hw_start_8411_2(tp
);
6403 case RTL_GIGA_MAC_VER_45
:
6404 case RTL_GIGA_MAC_VER_46
:
6405 rtl_hw_start_8168h_1(tp
);
6408 case RTL_GIGA_MAC_VER_49
:
6409 rtl_hw_start_8168ep_1(tp
);
6412 case RTL_GIGA_MAC_VER_50
:
6413 rtl_hw_start_8168ep_2(tp
);
6416 case RTL_GIGA_MAC_VER_51
:
6417 rtl_hw_start_8168ep_3(tp
);
6421 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
6422 dev
->name
, tp
->mac_version
);
6426 RTL_W8(Cfg9346
, Cfg9346_Lock
);
6428 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
6430 rtl_set_rx_mode(dev
);
6432 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
6435 #define R810X_CPCMD_QUIRK_MASK (\
6446 static void rtl_hw_start_8102e_1(struct rtl8169_private
*tp
)
6448 void __iomem
*ioaddr
= tp
->mmio_addr
;
6449 struct pci_dev
*pdev
= tp
->pci_dev
;
6450 static const struct ephy_info e_info_8102e_1
[] = {
6451 { 0x01, 0, 0x6e65 },
6452 { 0x02, 0, 0x091f },
6453 { 0x03, 0, 0xc2f9 },
6454 { 0x06, 0, 0xafb5 },
6455 { 0x07, 0, 0x0e00 },
6456 { 0x19, 0, 0xec80 },
6457 { 0x01, 0, 0x2e65 },
6462 rtl_csi_access_enable_2(tp
);
6464 RTL_W8(DBG_REG
, FIX_NAK_1
);
6466 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6469 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
6470 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
6472 cfg1
= RTL_R8(Config1
);
6473 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
6474 RTL_W8(Config1
, cfg1
& ~LEDS0
);
6476 rtl_ephy_init(tp
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
6479 static void rtl_hw_start_8102e_2(struct rtl8169_private
*tp
)
6481 void __iomem
*ioaddr
= tp
->mmio_addr
;
6482 struct pci_dev
*pdev
= tp
->pci_dev
;
6484 rtl_csi_access_enable_2(tp
);
6486 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6488 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
6489 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
6492 static void rtl_hw_start_8102e_3(struct rtl8169_private
*tp
)
6494 rtl_hw_start_8102e_2(tp
);
6496 rtl_ephy_write(tp
, 0x03, 0xc2f9);
6499 static void rtl_hw_start_8105e_1(struct rtl8169_private
*tp
)
6501 void __iomem
*ioaddr
= tp
->mmio_addr
;
6502 static const struct ephy_info e_info_8105e_1
[] = {
6503 { 0x07, 0, 0x4000 },
6504 { 0x19, 0, 0x0200 },
6505 { 0x19, 0, 0x0020 },
6506 { 0x1e, 0, 0x2000 },
6507 { 0x03, 0, 0x0001 },
6508 { 0x19, 0, 0x0100 },
6509 { 0x19, 0, 0x0004 },
6513 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6514 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
6516 /* Disable Early Tally Counter */
6517 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
6519 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
6520 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
6522 rtl_ephy_init(tp
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
6524 rtl_pcie_state_l2l3_enable(tp
, false);
6527 static void rtl_hw_start_8105e_2(struct rtl8169_private
*tp
)
6529 rtl_hw_start_8105e_1(tp
);
6530 rtl_ephy_write(tp
, 0x1e, rtl_ephy_read(tp
, 0x1e) | 0x8000);
6533 static void rtl_hw_start_8402(struct rtl8169_private
*tp
)
6535 void __iomem
*ioaddr
= tp
->mmio_addr
;
6536 static const struct ephy_info e_info_8402
[] = {
6537 { 0x19, 0xffff, 0xff64 },
6541 rtl_csi_access_enable_2(tp
);
6543 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6544 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
6546 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6547 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
6549 rtl_ephy_init(tp
, e_info_8402
, ARRAY_SIZE(e_info_8402
));
6551 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6553 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00000002, ERIAR_EXGMAC
);
6554 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00000006, ERIAR_EXGMAC
);
6555 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6556 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6557 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6558 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6559 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0e00, 0xff00, ERIAR_EXGMAC
);
6561 rtl_pcie_state_l2l3_enable(tp
, false);
6564 static void rtl_hw_start_8106(struct rtl8169_private
*tp
)
6566 void __iomem
*ioaddr
= tp
->mmio_addr
;
6568 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6569 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
6571 RTL_W32(MISC
, (RTL_R32(MISC
) | DISABLE_LAN_EN
) & ~EARLY_TALLY_EN
);
6572 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
6573 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6575 rtl_pcie_state_l2l3_enable(tp
, false);
6578 static void rtl_hw_start_8101(struct net_device
*dev
)
6580 struct rtl8169_private
*tp
= netdev_priv(dev
);
6581 void __iomem
*ioaddr
= tp
->mmio_addr
;
6582 struct pci_dev
*pdev
= tp
->pci_dev
;
6584 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_30
)
6585 tp
->event_slow
&= ~RxFIFOOver
;
6587 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
6588 tp
->mac_version
== RTL_GIGA_MAC_VER_16
)
6589 pcie_capability_set_word(pdev
, PCI_EXP_DEVCTL
,
6590 PCI_EXP_DEVCTL_NOSNOOP_EN
);
6592 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
6594 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6596 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
6598 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
6599 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
6601 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
6603 rtl_set_rx_tx_config_registers(tp
);
6605 switch (tp
->mac_version
) {
6606 case RTL_GIGA_MAC_VER_07
:
6607 rtl_hw_start_8102e_1(tp
);
6610 case RTL_GIGA_MAC_VER_08
:
6611 rtl_hw_start_8102e_3(tp
);
6614 case RTL_GIGA_MAC_VER_09
:
6615 rtl_hw_start_8102e_2(tp
);
6618 case RTL_GIGA_MAC_VER_29
:
6619 rtl_hw_start_8105e_1(tp
);
6621 case RTL_GIGA_MAC_VER_30
:
6622 rtl_hw_start_8105e_2(tp
);
6625 case RTL_GIGA_MAC_VER_37
:
6626 rtl_hw_start_8402(tp
);
6629 case RTL_GIGA_MAC_VER_39
:
6630 rtl_hw_start_8106(tp
);
6632 case RTL_GIGA_MAC_VER_43
:
6633 rtl_hw_start_8168g_2(tp
);
6635 case RTL_GIGA_MAC_VER_47
:
6636 case RTL_GIGA_MAC_VER_48
:
6637 rtl_hw_start_8168h_1(tp
);
6641 RTL_W8(Cfg9346
, Cfg9346_Lock
);
6643 RTL_W16(IntrMitigate
, 0x0000);
6645 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
6647 rtl_set_rx_mode(dev
);
6651 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
6654 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
6656 struct rtl8169_private
*tp
= netdev_priv(dev
);
6658 if (new_mtu
< ETH_ZLEN
||
6659 new_mtu
> rtl_chip_infos
[tp
->mac_version
].jumbo_max
)
6662 if (new_mtu
> ETH_DATA_LEN
)
6663 rtl_hw_jumbo_enable(tp
);
6665 rtl_hw_jumbo_disable(tp
);
6668 netdev_update_features(dev
);
6673 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
6675 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
6676 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
6679 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
6680 void **data_buff
, struct RxDesc
*desc
)
6682 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
6687 rtl8169_make_unusable_by_asic(desc
);
6690 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
6692 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
6694 /* Force memory writes to complete before releasing descriptor */
6697 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
6700 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
6703 desc
->addr
= cpu_to_le64(mapping
);
6704 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
6707 static inline void *rtl8169_align(void *data
)
6709 return (void *)ALIGN((long)data
, 16);
6712 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
6713 struct RxDesc
*desc
)
6717 struct device
*d
= &tp
->pci_dev
->dev
;
6718 struct net_device
*dev
= tp
->dev
;
6719 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
6721 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
6725 if (rtl8169_align(data
) != data
) {
6727 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
6732 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
6734 if (unlikely(dma_mapping_error(d
, mapping
))) {
6735 if (net_ratelimit())
6736 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
6740 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
6748 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
6752 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
6753 if (tp
->Rx_databuff
[i
]) {
6754 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
6755 tp
->RxDescArray
+ i
);
6760 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
6762 desc
->opts1
|= cpu_to_le32(RingEnd
);
6765 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
6769 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
6772 if (tp
->Rx_databuff
[i
])
6775 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
6777 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
6780 tp
->Rx_databuff
[i
] = data
;
6783 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
6787 rtl8169_rx_clear(tp
);
6791 static int rtl8169_init_ring(struct net_device
*dev
)
6793 struct rtl8169_private
*tp
= netdev_priv(dev
);
6795 rtl8169_init_ring_indexes(tp
);
6797 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
6798 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
6800 return rtl8169_rx_fill(tp
);
6803 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
6804 struct TxDesc
*desc
)
6806 unsigned int len
= tx_skb
->len
;
6808 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
6816 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
6821 for (i
= 0; i
< n
; i
++) {
6822 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
6823 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
6824 unsigned int len
= tx_skb
->len
;
6827 struct sk_buff
*skb
= tx_skb
->skb
;
6829 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
6830 tp
->TxDescArray
+ entry
);
6832 tp
->dev
->stats
.tx_dropped
++;
6833 dev_kfree_skb_any(skb
);
6840 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
6842 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
6843 tp
->cur_tx
= tp
->dirty_tx
= 0;
6846 static void rtl_reset_work(struct rtl8169_private
*tp
)
6848 struct net_device
*dev
= tp
->dev
;
6851 napi_disable(&tp
->napi
);
6852 netif_stop_queue(dev
);
6853 synchronize_sched();
6855 rtl8169_hw_reset(tp
);
6857 for (i
= 0; i
< NUM_RX_DESC
; i
++)
6858 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
6860 rtl8169_tx_clear(tp
);
6861 rtl8169_init_ring_indexes(tp
);
6863 napi_enable(&tp
->napi
);
6865 netif_wake_queue(dev
);
6866 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
6869 static void rtl8169_tx_timeout(struct net_device
*dev
)
6871 struct rtl8169_private
*tp
= netdev_priv(dev
);
6873 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6876 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
6879 struct skb_shared_info
*info
= skb_shinfo(skb
);
6880 unsigned int cur_frag
, entry
;
6881 struct TxDesc
*uninitialized_var(txd
);
6882 struct device
*d
= &tp
->pci_dev
->dev
;
6885 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
6886 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
6891 entry
= (entry
+ 1) % NUM_TX_DESC
;
6893 txd
= tp
->TxDescArray
+ entry
;
6894 len
= skb_frag_size(frag
);
6895 addr
= skb_frag_address(frag
);
6896 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
6897 if (unlikely(dma_mapping_error(d
, mapping
))) {
6898 if (net_ratelimit())
6899 netif_err(tp
, drv
, tp
->dev
,
6900 "Failed to map TX fragments DMA!\n");
6904 /* Anti gcc 2.95.3 bugware (sic) */
6905 status
= opts
[0] | len
|
6906 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
6908 txd
->opts1
= cpu_to_le32(status
);
6909 txd
->opts2
= cpu_to_le32(opts
[1]);
6910 txd
->addr
= cpu_to_le64(mapping
);
6912 tp
->tx_skb
[entry
].len
= len
;
6916 tp
->tx_skb
[entry
].skb
= skb
;
6917 txd
->opts1
|= cpu_to_le32(LastFrag
);
6923 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
6927 static bool rtl_test_hw_pad_bug(struct rtl8169_private
*tp
, struct sk_buff
*skb
)
6929 return skb
->len
< ETH_ZLEN
&& tp
->mac_version
== RTL_GIGA_MAC_VER_34
;
6932 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
6933 struct net_device
*dev
);
6934 /* r8169_csum_workaround()
6935 * The hw limites the value the transport offset. When the offset is out of the
6936 * range, calculate the checksum by sw.
6938 static void r8169_csum_workaround(struct rtl8169_private
*tp
,
6939 struct sk_buff
*skb
)
6941 if (skb_shinfo(skb
)->gso_size
) {
6942 netdev_features_t features
= tp
->dev
->features
;
6943 struct sk_buff
*segs
, *nskb
;
6945 features
&= ~(NETIF_F_SG
| NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
);
6946 segs
= skb_gso_segment(skb
, features
);
6947 if (IS_ERR(segs
) || !segs
)
6954 rtl8169_start_xmit(nskb
, tp
->dev
);
6957 dev_consume_skb_any(skb
);
6958 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6959 if (skb_checksum_help(skb
) < 0)
6962 rtl8169_start_xmit(skb
, tp
->dev
);
6964 struct net_device_stats
*stats
;
6967 stats
= &tp
->dev
->stats
;
6968 stats
->tx_dropped
++;
6969 dev_kfree_skb_any(skb
);
6973 /* msdn_giant_send_check()
6974 * According to the document of microsoft, the TCP Pseudo Header excludes the
6975 * packet length for IPv6 TCP large packets.
6977 static int msdn_giant_send_check(struct sk_buff
*skb
)
6979 const struct ipv6hdr
*ipv6h
;
6983 ret
= skb_cow_head(skb
, 0);
6987 ipv6h
= ipv6_hdr(skb
);
6991 th
->check
= ~tcp_v6_check(0, &ipv6h
->saddr
, &ipv6h
->daddr
, 0);
6996 static inline __be16
get_protocol(struct sk_buff
*skb
)
7000 if (skb
->protocol
== htons(ETH_P_8021Q
))
7001 protocol
= vlan_eth_hdr(skb
)->h_vlan_encapsulated_proto
;
7003 protocol
= skb
->protocol
;
7008 static bool rtl8169_tso_csum_v1(struct rtl8169_private
*tp
,
7009 struct sk_buff
*skb
, u32
*opts
)
7011 u32 mss
= skb_shinfo(skb
)->gso_size
;
7015 opts
[0] |= min(mss
, TD_MSS_MAX
) << TD0_MSS_SHIFT
;
7016 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
7017 const struct iphdr
*ip
= ip_hdr(skb
);
7019 if (ip
->protocol
== IPPROTO_TCP
)
7020 opts
[0] |= TD0_IP_CS
| TD0_TCP_CS
;
7021 else if (ip
->protocol
== IPPROTO_UDP
)
7022 opts
[0] |= TD0_IP_CS
| TD0_UDP_CS
;
7030 static bool rtl8169_tso_csum_v2(struct rtl8169_private
*tp
,
7031 struct sk_buff
*skb
, u32
*opts
)
7033 u32 transport_offset
= (u32
)skb_transport_offset(skb
);
7034 u32 mss
= skb_shinfo(skb
)->gso_size
;
7037 if (transport_offset
> GTTCPHO_MAX
) {
7038 netif_warn(tp
, tx_err
, tp
->dev
,
7039 "Invalid transport offset 0x%x for TSO\n",
7044 switch (get_protocol(skb
)) {
7045 case htons(ETH_P_IP
):
7046 opts
[0] |= TD1_GTSENV4
;
7049 case htons(ETH_P_IPV6
):
7050 if (msdn_giant_send_check(skb
))
7053 opts
[0] |= TD1_GTSENV6
;
7061 opts
[0] |= transport_offset
<< GTTCPHO_SHIFT
;
7062 opts
[1] |= min(mss
, TD_MSS_MAX
) << TD1_MSS_SHIFT
;
7063 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
7066 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
7067 return !(skb_checksum_help(skb
) || eth_skb_pad(skb
));
7069 if (transport_offset
> TCPHO_MAX
) {
7070 netif_warn(tp
, tx_err
, tp
->dev
,
7071 "Invalid transport offset 0x%x\n",
7076 switch (get_protocol(skb
)) {
7077 case htons(ETH_P_IP
):
7078 opts
[1] |= TD1_IPv4_CS
;
7079 ip_protocol
= ip_hdr(skb
)->protocol
;
7082 case htons(ETH_P_IPV6
):
7083 opts
[1] |= TD1_IPv6_CS
;
7084 ip_protocol
= ipv6_hdr(skb
)->nexthdr
;
7088 ip_protocol
= IPPROTO_RAW
;
7092 if (ip_protocol
== IPPROTO_TCP
)
7093 opts
[1] |= TD1_TCP_CS
;
7094 else if (ip_protocol
== IPPROTO_UDP
)
7095 opts
[1] |= TD1_UDP_CS
;
7099 opts
[1] |= transport_offset
<< TCPHO_SHIFT
;
7101 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
7102 return !eth_skb_pad(skb
);
7108 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
7109 struct net_device
*dev
)
7111 struct rtl8169_private
*tp
= netdev_priv(dev
);
7112 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
7113 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
7114 void __iomem
*ioaddr
= tp
->mmio_addr
;
7115 struct device
*d
= &tp
->pci_dev
->dev
;
7121 if (unlikely(!TX_FRAGS_READY_FOR(tp
, skb_shinfo(skb
)->nr_frags
))) {
7122 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
7126 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
7129 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb
));
7132 if (!tp
->tso_csum(tp
, skb
, opts
)) {
7133 r8169_csum_workaround(tp
, skb
);
7134 return NETDEV_TX_OK
;
7137 len
= skb_headlen(skb
);
7138 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
7139 if (unlikely(dma_mapping_error(d
, mapping
))) {
7140 if (net_ratelimit())
7141 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
7145 tp
->tx_skb
[entry
].len
= len
;
7146 txd
->addr
= cpu_to_le64(mapping
);
7148 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
7152 opts
[0] |= FirstFrag
;
7154 opts
[0] |= FirstFrag
| LastFrag
;
7155 tp
->tx_skb
[entry
].skb
= skb
;
7158 txd
->opts2
= cpu_to_le32(opts
[1]);
7160 skb_tx_timestamp(skb
);
7162 /* Force memory writes to complete before releasing descriptor */
7165 /* Anti gcc 2.95.3 bugware (sic) */
7166 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
7167 txd
->opts1
= cpu_to_le32(status
);
7169 /* Force all memory writes to complete before notifying device */
7172 tp
->cur_tx
+= frags
+ 1;
7174 RTL_W8(TxPoll
, NPQ
);
7178 if (!TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
)) {
7179 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7180 * not miss a ring update when it notices a stopped queue.
7183 netif_stop_queue(dev
);
7184 /* Sync with rtl_tx:
7185 * - publish queue status and cur_tx ring index (write barrier)
7186 * - refresh dirty_tx ring index (read barrier).
7187 * May the current thread have a pessimistic view of the ring
7188 * status and forget to wake up queue, a racing rtl_tx thread
7192 if (TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
))
7193 netif_wake_queue(dev
);
7196 return NETDEV_TX_OK
;
7199 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
7201 dev_kfree_skb_any(skb
);
7202 dev
->stats
.tx_dropped
++;
7203 return NETDEV_TX_OK
;
7206 netif_stop_queue(dev
);
7207 dev
->stats
.tx_dropped
++;
7208 return NETDEV_TX_BUSY
;
7211 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
7213 struct rtl8169_private
*tp
= netdev_priv(dev
);
7214 struct pci_dev
*pdev
= tp
->pci_dev
;
7215 u16 pci_status
, pci_cmd
;
7217 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
7218 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
7220 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7221 pci_cmd
, pci_status
);
7224 * The recovery sequence below admits a very elaborated explanation:
7225 * - it seems to work;
7226 * - I did not see what else could be done;
7227 * - it makes iop3xx happy.
7229 * Feel free to adjust to your needs.
7231 if (pdev
->broken_parity_status
)
7232 pci_cmd
&= ~PCI_COMMAND_PARITY
;
7234 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
7236 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
7238 pci_write_config_word(pdev
, PCI_STATUS
,
7239 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
7240 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
7241 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
7243 /* The infamous DAC f*ckup only happens at boot time */
7244 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->cur_rx
) {
7245 void __iomem
*ioaddr
= tp
->mmio_addr
;
7247 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
7248 tp
->cp_cmd
&= ~PCIDAC
;
7249 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
7250 dev
->features
&= ~NETIF_F_HIGHDMA
;
7253 rtl8169_hw_reset(tp
);
7255 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
7258 static void rtl_tx(struct net_device
*dev
, struct rtl8169_private
*tp
)
7260 unsigned int dirty_tx
, tx_left
;
7262 dirty_tx
= tp
->dirty_tx
;
7264 tx_left
= tp
->cur_tx
- dirty_tx
;
7266 while (tx_left
> 0) {
7267 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
7268 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
7271 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
7272 if (status
& DescOwn
)
7275 /* This barrier is needed to keep us from reading
7276 * any other fields out of the Tx descriptor until
7277 * we know the status of DescOwn
7281 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
7282 tp
->TxDescArray
+ entry
);
7283 if (status
& LastFrag
) {
7284 u64_stats_update_begin(&tp
->tx_stats
.syncp
);
7285 tp
->tx_stats
.packets
++;
7286 tp
->tx_stats
.bytes
+= tx_skb
->skb
->len
;
7287 u64_stats_update_end(&tp
->tx_stats
.syncp
);
7288 dev_kfree_skb_any(tx_skb
->skb
);
7295 if (tp
->dirty_tx
!= dirty_tx
) {
7296 tp
->dirty_tx
= dirty_tx
;
7297 /* Sync with rtl8169_start_xmit:
7298 * - publish dirty_tx ring index (write barrier)
7299 * - refresh cur_tx ring index and queue status (read barrier)
7300 * May the current thread miss the stopped queue condition,
7301 * a racing xmit thread can only have a right view of the
7305 if (netif_queue_stopped(dev
) &&
7306 TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
)) {
7307 netif_wake_queue(dev
);
7310 * 8168 hack: TxPoll requests are lost when the Tx packets are
7311 * too close. Let's kick an extra TxPoll request when a burst
7312 * of start_xmit activity is detected (if it is not detected,
7313 * it is slow enough). -- FR
7315 if (tp
->cur_tx
!= dirty_tx
) {
7316 void __iomem
*ioaddr
= tp
->mmio_addr
;
7318 RTL_W8(TxPoll
, NPQ
);
7323 static inline int rtl8169_fragmented_frame(u32 status
)
7325 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
7328 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
7330 u32 status
= opts1
& RxProtoMask
;
7332 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
7333 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
7334 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
7336 skb_checksum_none_assert(skb
);
7339 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
7340 struct rtl8169_private
*tp
,
7344 struct sk_buff
*skb
;
7345 struct device
*d
= &tp
->pci_dev
->dev
;
7347 data
= rtl8169_align(data
);
7348 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
7350 skb
= napi_alloc_skb(&tp
->napi
, pkt_size
);
7352 memcpy(skb
->data
, data
, pkt_size
);
7353 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
7358 static int rtl_rx(struct net_device
*dev
, struct rtl8169_private
*tp
, u32 budget
)
7360 unsigned int cur_rx
, rx_left
;
7363 cur_rx
= tp
->cur_rx
;
7365 for (rx_left
= min(budget
, NUM_RX_DESC
); rx_left
> 0; rx_left
--, cur_rx
++) {
7366 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
7367 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
7370 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
7371 if (status
& DescOwn
)
7374 /* This barrier is needed to keep us from reading
7375 * any other fields out of the Rx descriptor until
7376 * we know the status of DescOwn
7380 if (unlikely(status
& RxRES
)) {
7381 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
7383 dev
->stats
.rx_errors
++;
7384 if (status
& (RxRWT
| RxRUNT
))
7385 dev
->stats
.rx_length_errors
++;
7387 dev
->stats
.rx_crc_errors
++;
7388 if (status
& RxFOVF
) {
7389 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
7390 dev
->stats
.rx_fifo_errors
++;
7392 if ((status
& (RxRUNT
| RxCRC
)) &&
7393 !(status
& (RxRWT
| RxFOVF
)) &&
7394 (dev
->features
& NETIF_F_RXALL
))
7397 struct sk_buff
*skb
;
7402 addr
= le64_to_cpu(desc
->addr
);
7403 if (likely(!(dev
->features
& NETIF_F_RXFCS
)))
7404 pkt_size
= (status
& 0x00003fff) - 4;
7406 pkt_size
= status
& 0x00003fff;
7409 * The driver does not support incoming fragmented
7410 * frames. They are seen as a symptom of over-mtu
7413 if (unlikely(rtl8169_fragmented_frame(status
))) {
7414 dev
->stats
.rx_dropped
++;
7415 dev
->stats
.rx_length_errors
++;
7416 goto release_descriptor
;
7419 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
7420 tp
, pkt_size
, addr
);
7422 dev
->stats
.rx_dropped
++;
7423 goto release_descriptor
;
7426 rtl8169_rx_csum(skb
, status
);
7427 skb_put(skb
, pkt_size
);
7428 skb
->protocol
= eth_type_trans(skb
, dev
);
7430 rtl8169_rx_vlan_tag(desc
, skb
);
7432 if (skb
->pkt_type
== PACKET_MULTICAST
)
7433 dev
->stats
.multicast
++;
7435 napi_gro_receive(&tp
->napi
, skb
);
7437 u64_stats_update_begin(&tp
->rx_stats
.syncp
);
7438 tp
->rx_stats
.packets
++;
7439 tp
->rx_stats
.bytes
+= pkt_size
;
7440 u64_stats_update_end(&tp
->rx_stats
.syncp
);
7444 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
7447 count
= cur_rx
- tp
->cur_rx
;
7448 tp
->cur_rx
= cur_rx
;
7453 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
7455 struct net_device
*dev
= dev_instance
;
7456 struct rtl8169_private
*tp
= netdev_priv(dev
);
7460 status
= rtl_get_events(tp
);
7461 if (status
&& status
!= 0xffff) {
7462 status
&= RTL_EVENT_NAPI
| tp
->event_slow
;
7466 rtl_irq_disable(tp
);
7467 napi_schedule(&tp
->napi
);
7470 return IRQ_RETVAL(handled
);
7474 * Workqueue context.
7476 static void rtl_slow_event_work(struct rtl8169_private
*tp
)
7478 struct net_device
*dev
= tp
->dev
;
7481 status
= rtl_get_events(tp
) & tp
->event_slow
;
7482 rtl_ack_events(tp
, status
);
7484 if (unlikely(status
& RxFIFOOver
)) {
7485 switch (tp
->mac_version
) {
7486 /* Work around for rx fifo overflow */
7487 case RTL_GIGA_MAC_VER_11
:
7488 netif_stop_queue(dev
);
7489 /* XXX - Hack alert. See rtl_task(). */
7490 set_bit(RTL_FLAG_TASK_RESET_PENDING
, tp
->wk
.flags
);
7496 if (unlikely(status
& SYSErr
))
7497 rtl8169_pcierr_interrupt(dev
);
7499 if (status
& LinkChg
)
7500 __rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
, true);
7502 rtl_irq_enable_all(tp
);
7505 static void rtl_task(struct work_struct
*work
)
7507 static const struct {
7509 void (*action
)(struct rtl8169_private
*);
7511 /* XXX - keep rtl_slow_event_work() as first element. */
7512 { RTL_FLAG_TASK_SLOW_PENDING
, rtl_slow_event_work
},
7513 { RTL_FLAG_TASK_RESET_PENDING
, rtl_reset_work
},
7514 { RTL_FLAG_TASK_PHY_PENDING
, rtl_phy_work
}
7516 struct rtl8169_private
*tp
=
7517 container_of(work
, struct rtl8169_private
, wk
.work
);
7518 struct net_device
*dev
= tp
->dev
;
7523 if (!netif_running(dev
) ||
7524 !test_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
))
7527 for (i
= 0; i
< ARRAY_SIZE(rtl_work
); i
++) {
7530 pending
= test_and_clear_bit(rtl_work
[i
].bitnr
, tp
->wk
.flags
);
7532 rtl_work
[i
].action(tp
);
7536 rtl_unlock_work(tp
);
7539 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
7541 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
7542 struct net_device
*dev
= tp
->dev
;
7543 u16 enable_mask
= RTL_EVENT_NAPI
| tp
->event_slow
;
7547 status
= rtl_get_events(tp
);
7548 rtl_ack_events(tp
, status
& ~tp
->event_slow
);
7550 if (status
& RTL_EVENT_NAPI_RX
)
7551 work_done
= rtl_rx(dev
, tp
, (u32
) budget
);
7553 if (status
& RTL_EVENT_NAPI_TX
)
7556 if (status
& tp
->event_slow
) {
7557 enable_mask
&= ~tp
->event_slow
;
7559 rtl_schedule_task(tp
, RTL_FLAG_TASK_SLOW_PENDING
);
7562 if (work_done
< budget
) {
7563 napi_complete(napi
);
7565 rtl_irq_enable(tp
, enable_mask
);
7572 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
7574 struct rtl8169_private
*tp
= netdev_priv(dev
);
7576 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
7579 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
7580 RTL_W32(RxMissed
, 0);
7583 static void rtl8169_down(struct net_device
*dev
)
7585 struct rtl8169_private
*tp
= netdev_priv(dev
);
7586 void __iomem
*ioaddr
= tp
->mmio_addr
;
7588 del_timer_sync(&tp
->timer
);
7590 napi_disable(&tp
->napi
);
7591 netif_stop_queue(dev
);
7593 rtl8169_hw_reset(tp
);
7595 * At this point device interrupts can not be enabled in any function,
7596 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7597 * and napi is disabled (rtl8169_poll).
7599 rtl8169_rx_missed(dev
, ioaddr
);
7601 /* Give a racing hard_start_xmit a few cycles to complete. */
7602 synchronize_sched();
7604 rtl8169_tx_clear(tp
);
7606 rtl8169_rx_clear(tp
);
7608 rtl_pll_power_down(tp
);
7611 static int rtl8169_close(struct net_device
*dev
)
7613 struct rtl8169_private
*tp
= netdev_priv(dev
);
7614 struct pci_dev
*pdev
= tp
->pci_dev
;
7616 pm_runtime_get_sync(&pdev
->dev
);
7618 /* Update counters before going down */
7619 rtl8169_update_counters(dev
);
7622 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7625 rtl_unlock_work(tp
);
7627 cancel_work_sync(&tp
->wk
.work
);
7629 free_irq(pdev
->irq
, dev
);
7631 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
7633 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
7635 tp
->TxDescArray
= NULL
;
7636 tp
->RxDescArray
= NULL
;
7638 pm_runtime_put_sync(&pdev
->dev
);
7643 #ifdef CONFIG_NET_POLL_CONTROLLER
7644 static void rtl8169_netpoll(struct net_device
*dev
)
7646 struct rtl8169_private
*tp
= netdev_priv(dev
);
7648 rtl8169_interrupt(tp
->pci_dev
->irq
, dev
);
7652 static int rtl_open(struct net_device
*dev
)
7654 struct rtl8169_private
*tp
= netdev_priv(dev
);
7655 void __iomem
*ioaddr
= tp
->mmio_addr
;
7656 struct pci_dev
*pdev
= tp
->pci_dev
;
7657 int retval
= -ENOMEM
;
7659 pm_runtime_get_sync(&pdev
->dev
);
7662 * Rx and Tx descriptors needs 256 bytes alignment.
7663 * dma_alloc_coherent provides more.
7665 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
7666 &tp
->TxPhyAddr
, GFP_KERNEL
);
7667 if (!tp
->TxDescArray
)
7668 goto err_pm_runtime_put
;
7670 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
7671 &tp
->RxPhyAddr
, GFP_KERNEL
);
7672 if (!tp
->RxDescArray
)
7675 retval
= rtl8169_init_ring(dev
);
7679 INIT_WORK(&tp
->wk
.work
, rtl_task
);
7683 rtl_request_firmware(tp
);
7685 retval
= request_irq(pdev
->irq
, rtl8169_interrupt
,
7686 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
7689 goto err_release_fw_2
;
7693 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7695 napi_enable(&tp
->napi
);
7697 rtl8169_init_phy(dev
, tp
);
7699 __rtl8169_set_features(dev
, dev
->features
);
7701 rtl_pll_power_up(tp
);
7705 if (!rtl8169_init_counter_offsets(dev
))
7706 netif_warn(tp
, hw
, dev
, "counter reset/update failed\n");
7708 netif_start_queue(dev
);
7710 rtl_unlock_work(tp
);
7712 tp
->saved_wolopts
= 0;
7713 pm_runtime_put_noidle(&pdev
->dev
);
7715 rtl8169_check_link_status(dev
, tp
, ioaddr
);
7720 rtl_release_firmware(tp
);
7721 rtl8169_rx_clear(tp
);
7723 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
7725 tp
->RxDescArray
= NULL
;
7727 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
7729 tp
->TxDescArray
= NULL
;
7731 pm_runtime_put_noidle(&pdev
->dev
);
7735 static struct rtnl_link_stats64
*
7736 rtl8169_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
7738 struct rtl8169_private
*tp
= netdev_priv(dev
);
7739 void __iomem
*ioaddr
= tp
->mmio_addr
;
7740 struct rtl8169_counters
*counters
= tp
->counters
;
7743 if (netif_running(dev
))
7744 rtl8169_rx_missed(dev
, ioaddr
);
7747 start
= u64_stats_fetch_begin_irq(&tp
->rx_stats
.syncp
);
7748 stats
->rx_packets
= tp
->rx_stats
.packets
;
7749 stats
->rx_bytes
= tp
->rx_stats
.bytes
;
7750 } while (u64_stats_fetch_retry_irq(&tp
->rx_stats
.syncp
, start
));
7753 start
= u64_stats_fetch_begin_irq(&tp
->tx_stats
.syncp
);
7754 stats
->tx_packets
= tp
->tx_stats
.packets
;
7755 stats
->tx_bytes
= tp
->tx_stats
.bytes
;
7756 } while (u64_stats_fetch_retry_irq(&tp
->tx_stats
.syncp
, start
));
7758 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
7759 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
7760 stats
->rx_length_errors
= dev
->stats
.rx_length_errors
;
7761 stats
->rx_errors
= dev
->stats
.rx_errors
;
7762 stats
->rx_crc_errors
= dev
->stats
.rx_crc_errors
;
7763 stats
->rx_fifo_errors
= dev
->stats
.rx_fifo_errors
;
7764 stats
->rx_missed_errors
= dev
->stats
.rx_missed_errors
;
7765 stats
->multicast
= dev
->stats
.multicast
;
7768 * Fetch additonal counter values missing in stats collected by driver
7769 * from tally counters.
7771 rtl8169_update_counters(dev
);
7774 * Subtract values fetched during initalization.
7775 * See rtl8169_init_counter_offsets for a description why we do that.
7777 stats
->tx_errors
= le64_to_cpu(counters
->tx_errors
) -
7778 le64_to_cpu(tp
->tc_offset
.tx_errors
);
7779 stats
->collisions
= le32_to_cpu(counters
->tx_multi_collision
) -
7780 le32_to_cpu(tp
->tc_offset
.tx_multi_collision
);
7781 stats
->tx_aborted_errors
= le16_to_cpu(counters
->tx_aborted
) -
7782 le16_to_cpu(tp
->tc_offset
.tx_aborted
);
7787 static void rtl8169_net_suspend(struct net_device
*dev
)
7789 struct rtl8169_private
*tp
= netdev_priv(dev
);
7791 if (!netif_running(dev
))
7794 netif_device_detach(dev
);
7795 netif_stop_queue(dev
);
7798 napi_disable(&tp
->napi
);
7799 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7800 rtl_unlock_work(tp
);
7802 rtl_pll_power_down(tp
);
7807 static int rtl8169_suspend(struct device
*device
)
7809 struct pci_dev
*pdev
= to_pci_dev(device
);
7810 struct net_device
*dev
= pci_get_drvdata(pdev
);
7812 rtl8169_net_suspend(dev
);
7817 static void __rtl8169_resume(struct net_device
*dev
)
7819 struct rtl8169_private
*tp
= netdev_priv(dev
);
7821 netif_device_attach(dev
);
7823 rtl_pll_power_up(tp
);
7826 napi_enable(&tp
->napi
);
7827 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7828 rtl_unlock_work(tp
);
7830 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
7833 static int rtl8169_resume(struct device
*device
)
7835 struct pci_dev
*pdev
= to_pci_dev(device
);
7836 struct net_device
*dev
= pci_get_drvdata(pdev
);
7837 struct rtl8169_private
*tp
= netdev_priv(dev
);
7839 rtl8169_init_phy(dev
, tp
);
7841 if (netif_running(dev
))
7842 __rtl8169_resume(dev
);
7847 static int rtl8169_runtime_suspend(struct device
*device
)
7849 struct pci_dev
*pdev
= to_pci_dev(device
);
7850 struct net_device
*dev
= pci_get_drvdata(pdev
);
7851 struct rtl8169_private
*tp
= netdev_priv(dev
);
7853 if (!tp
->TxDescArray
)
7857 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
7858 __rtl8169_set_wol(tp
, WAKE_ANY
);
7859 rtl_unlock_work(tp
);
7861 rtl8169_net_suspend(dev
);
7866 static int rtl8169_runtime_resume(struct device
*device
)
7868 struct pci_dev
*pdev
= to_pci_dev(device
);
7869 struct net_device
*dev
= pci_get_drvdata(pdev
);
7870 struct rtl8169_private
*tp
= netdev_priv(dev
);
7872 if (!tp
->TxDescArray
)
7876 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
7877 tp
->saved_wolopts
= 0;
7878 rtl_unlock_work(tp
);
7880 rtl8169_init_phy(dev
, tp
);
7882 __rtl8169_resume(dev
);
7887 static int rtl8169_runtime_idle(struct device
*device
)
7889 struct pci_dev
*pdev
= to_pci_dev(device
);
7890 struct net_device
*dev
= pci_get_drvdata(pdev
);
7891 struct rtl8169_private
*tp
= netdev_priv(dev
);
7893 return tp
->TxDescArray
? -EBUSY
: 0;
7896 static const struct dev_pm_ops rtl8169_pm_ops
= {
7897 .suspend
= rtl8169_suspend
,
7898 .resume
= rtl8169_resume
,
7899 .freeze
= rtl8169_suspend
,
7900 .thaw
= rtl8169_resume
,
7901 .poweroff
= rtl8169_suspend
,
7902 .restore
= rtl8169_resume
,
7903 .runtime_suspend
= rtl8169_runtime_suspend
,
7904 .runtime_resume
= rtl8169_runtime_resume
,
7905 .runtime_idle
= rtl8169_runtime_idle
,
7908 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7910 #else /* !CONFIG_PM */
7912 #define RTL8169_PM_OPS NULL
7914 #endif /* !CONFIG_PM */
7916 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
7918 void __iomem
*ioaddr
= tp
->mmio_addr
;
7920 /* WoL fails with 8168b when the receiver is disabled. */
7921 switch (tp
->mac_version
) {
7922 case RTL_GIGA_MAC_VER_11
:
7923 case RTL_GIGA_MAC_VER_12
:
7924 case RTL_GIGA_MAC_VER_17
:
7925 pci_clear_master(tp
->pci_dev
);
7927 RTL_W8(ChipCmd
, CmdRxEnb
);
7936 static void rtl_shutdown(struct pci_dev
*pdev
)
7938 struct net_device
*dev
= pci_get_drvdata(pdev
);
7939 struct rtl8169_private
*tp
= netdev_priv(dev
);
7940 struct device
*d
= &pdev
->dev
;
7942 pm_runtime_get_sync(d
);
7944 rtl8169_net_suspend(dev
);
7946 /* Restore original MAC address */
7947 rtl_rar_set(tp
, dev
->perm_addr
);
7949 rtl8169_hw_reset(tp
);
7951 if (system_state
== SYSTEM_POWER_OFF
) {
7952 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
7953 rtl_wol_suspend_quirk(tp
);
7954 rtl_wol_shutdown_quirk(tp
);
7957 pci_wake_from_d3(pdev
, true);
7958 pci_set_power_state(pdev
, PCI_D3hot
);
7961 pm_runtime_put_noidle(d
);
7964 static void rtl_remove_one(struct pci_dev
*pdev
)
7966 struct net_device
*dev
= pci_get_drvdata(pdev
);
7967 struct rtl8169_private
*tp
= netdev_priv(dev
);
7969 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
7970 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
7971 tp
->mac_version
== RTL_GIGA_MAC_VER_31
||
7972 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
7973 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
7974 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) &&
7975 r8168_check_dash(tp
)) {
7976 rtl8168_driver_stop(tp
);
7979 netif_napi_del(&tp
->napi
);
7981 unregister_netdev(dev
);
7983 dma_free_coherent(&tp
->pci_dev
->dev
, sizeof(*tp
->counters
),
7984 tp
->counters
, tp
->counters_phys_addr
);
7986 rtl_release_firmware(tp
);
7988 if (pci_dev_run_wake(pdev
))
7989 pm_runtime_get_noresume(&pdev
->dev
);
7991 /* restore original MAC address */
7992 rtl_rar_set(tp
, dev
->perm_addr
);
7994 rtl_disable_msi(pdev
, tp
);
7995 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
7998 static const struct net_device_ops rtl_netdev_ops
= {
7999 .ndo_open
= rtl_open
,
8000 .ndo_stop
= rtl8169_close
,
8001 .ndo_get_stats64
= rtl8169_get_stats64
,
8002 .ndo_start_xmit
= rtl8169_start_xmit
,
8003 .ndo_tx_timeout
= rtl8169_tx_timeout
,
8004 .ndo_validate_addr
= eth_validate_addr
,
8005 .ndo_change_mtu
= rtl8169_change_mtu
,
8006 .ndo_fix_features
= rtl8169_fix_features
,
8007 .ndo_set_features
= rtl8169_set_features
,
8008 .ndo_set_mac_address
= rtl_set_mac_address
,
8009 .ndo_do_ioctl
= rtl8169_ioctl
,
8010 .ndo_set_rx_mode
= rtl_set_rx_mode
,
8011 #ifdef CONFIG_NET_POLL_CONTROLLER
8012 .ndo_poll_controller
= rtl8169_netpoll
,
8017 static const struct rtl_cfg_info
{
8018 void (*hw_start
)(struct net_device
*);
8019 unsigned int region
;
8024 } rtl_cfg_infos
[] = {
8026 .hw_start
= rtl_hw_start_8169
,
8029 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
,
8030 .features
= RTL_FEATURE_GMII
,
8031 .default_ver
= RTL_GIGA_MAC_VER_01
,
8034 .hw_start
= rtl_hw_start_8168
,
8037 .event_slow
= SYSErr
| LinkChg
| RxOverflow
,
8038 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
8039 .default_ver
= RTL_GIGA_MAC_VER_11
,
8042 .hw_start
= rtl_hw_start_8101
,
8045 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
|
8047 .features
= RTL_FEATURE_MSI
,
8048 .default_ver
= RTL_GIGA_MAC_VER_13
,
8052 /* Cfg9346_Unlock assumed. */
8053 static unsigned rtl_try_msi(struct rtl8169_private
*tp
,
8054 const struct rtl_cfg_info
*cfg
)
8056 void __iomem
*ioaddr
= tp
->mmio_addr
;
8060 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
8061 if (cfg
->features
& RTL_FEATURE_MSI
) {
8062 if (pci_enable_msi(tp
->pci_dev
)) {
8063 netif_info(tp
, hw
, tp
->dev
, "no MSI. Back to INTx.\n");
8066 msi
= RTL_FEATURE_MSI
;
8069 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
8070 RTL_W8(Config2
, cfg2
);
8074 DECLARE_RTL_COND(rtl_link_list_ready_cond
)
8076 void __iomem
*ioaddr
= tp
->mmio_addr
;
8078 return RTL_R8(MCU
) & LINK_LIST_RDY
;
8081 DECLARE_RTL_COND(rtl_rxtx_empty_cond
)
8083 void __iomem
*ioaddr
= tp
->mmio_addr
;
8085 return (RTL_R8(MCU
) & RXTX_EMPTY
) == RXTX_EMPTY
;
8088 static void rtl_hw_init_8168g(struct rtl8169_private
*tp
)
8090 void __iomem
*ioaddr
= tp
->mmio_addr
;
8093 tp
->ocp_base
= OCP_STD_PHY_BASE
;
8095 RTL_W32(MISC
, RTL_R32(MISC
) | RXDV_GATED_EN
);
8097 if (!rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 42))
8100 if (!rtl_udelay_loop_wait_high(tp
, &rtl_rxtx_empty_cond
, 100, 42))
8103 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) & ~(CmdTxEnb
| CmdRxEnb
));
8105 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
8107 data
= r8168_mac_ocp_read(tp
, 0xe8de);
8109 r8168_mac_ocp_write(tp
, 0xe8de, data
);
8111 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
8114 data
= r8168_mac_ocp_read(tp
, 0xe8de);
8116 r8168_mac_ocp_write(tp
, 0xe8de, data
);
8118 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
8122 static void rtl_hw_init_8168ep(struct rtl8169_private
*tp
)
8124 rtl8168ep_stop_cmac(tp
);
8125 rtl_hw_init_8168g(tp
);
8128 static void rtl_hw_initialize(struct rtl8169_private
*tp
)
8130 switch (tp
->mac_version
) {
8131 case RTL_GIGA_MAC_VER_40
:
8132 case RTL_GIGA_MAC_VER_41
:
8133 case RTL_GIGA_MAC_VER_42
:
8134 case RTL_GIGA_MAC_VER_43
:
8135 case RTL_GIGA_MAC_VER_44
:
8136 case RTL_GIGA_MAC_VER_45
:
8137 case RTL_GIGA_MAC_VER_46
:
8138 case RTL_GIGA_MAC_VER_47
:
8139 case RTL_GIGA_MAC_VER_48
:
8140 rtl_hw_init_8168g(tp
);
8142 case RTL_GIGA_MAC_VER_49
:
8143 case RTL_GIGA_MAC_VER_50
:
8144 case RTL_GIGA_MAC_VER_51
:
8145 rtl_hw_init_8168ep(tp
);
8152 static int rtl_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
8154 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
8155 const unsigned int region
= cfg
->region
;
8156 struct rtl8169_private
*tp
;
8157 struct mii_if_info
*mii
;
8158 struct net_device
*dev
;
8159 void __iomem
*ioaddr
;
8163 if (netif_msg_drv(&debug
)) {
8164 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
8165 MODULENAME
, RTL8169_VERSION
);
8168 dev
= alloc_etherdev(sizeof (*tp
));
8174 SET_NETDEV_DEV(dev
, &pdev
->dev
);
8175 dev
->netdev_ops
= &rtl_netdev_ops
;
8176 tp
= netdev_priv(dev
);
8179 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
8183 mii
->mdio_read
= rtl_mdio_read
;
8184 mii
->mdio_write
= rtl_mdio_write
;
8185 mii
->phy_id_mask
= 0x1f;
8186 mii
->reg_num_mask
= 0x1f;
8187 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
8189 /* disable ASPM completely as that cause random device stop working
8190 * problems as well as full system hangs for some PCIe devices users */
8191 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
8192 PCIE_LINK_STATE_CLKPM
);
8194 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8195 rc
= pci_enable_device(pdev
);
8197 netif_err(tp
, probe
, dev
, "enable failure\n");
8198 goto err_out_free_dev_1
;
8201 if (pci_set_mwi(pdev
) < 0)
8202 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
8204 /* make sure PCI base addr 1 is MMIO */
8205 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
8206 netif_err(tp
, probe
, dev
,
8207 "region #%d not an MMIO resource, aborting\n",
8213 /* check for weird/broken PCI region reporting */
8214 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
8215 netif_err(tp
, probe
, dev
,
8216 "Invalid PCI region size(s), aborting\n");
8221 rc
= pci_request_regions(pdev
, MODULENAME
);
8223 netif_err(tp
, probe
, dev
, "could not request regions\n");
8229 if ((sizeof(dma_addr_t
) > 4) &&
8230 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
8231 tp
->cp_cmd
|= PCIDAC
;
8232 dev
->features
|= NETIF_F_HIGHDMA
;
8234 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
8236 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
8237 goto err_out_free_res_3
;
8241 /* ioremap MMIO region */
8242 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
8244 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
8246 goto err_out_free_res_3
;
8248 tp
->mmio_addr
= ioaddr
;
8250 if (!pci_is_pcie(pdev
))
8251 netif_info(tp
, probe
, dev
, "not PCI Express\n");
8253 /* Identify chip attached to board */
8254 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
8258 rtl_irq_disable(tp
);
8260 rtl_hw_initialize(tp
);
8264 rtl_ack_events(tp
, 0xffff);
8266 pci_set_master(pdev
);
8268 rtl_init_mdio_ops(tp
);
8269 rtl_init_pll_power_ops(tp
);
8270 rtl_init_jumbo_ops(tp
);
8271 rtl_init_csi_ops(tp
);
8273 rtl8169_print_mac_version(tp
);
8275 chipset
= tp
->mac_version
;
8276 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
8278 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
8279 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
8280 RTL_W8(Config5
, RTL_R8(Config5
) & (BWF
| MWF
| UWF
| LanWake
| PMEStatus
));
8281 switch (tp
->mac_version
) {
8282 case RTL_GIGA_MAC_VER_34
:
8283 case RTL_GIGA_MAC_VER_35
:
8284 case RTL_GIGA_MAC_VER_36
:
8285 case RTL_GIGA_MAC_VER_37
:
8286 case RTL_GIGA_MAC_VER_38
:
8287 case RTL_GIGA_MAC_VER_40
:
8288 case RTL_GIGA_MAC_VER_41
:
8289 case RTL_GIGA_MAC_VER_42
:
8290 case RTL_GIGA_MAC_VER_43
:
8291 case RTL_GIGA_MAC_VER_44
:
8292 case RTL_GIGA_MAC_VER_45
:
8293 case RTL_GIGA_MAC_VER_46
:
8294 case RTL_GIGA_MAC_VER_47
:
8295 case RTL_GIGA_MAC_VER_48
:
8296 case RTL_GIGA_MAC_VER_49
:
8297 case RTL_GIGA_MAC_VER_50
:
8298 case RTL_GIGA_MAC_VER_51
:
8299 if (rtl_eri_read(tp
, 0xdc, ERIAR_EXGMAC
) & MagicPacket_v2
)
8300 tp
->features
|= RTL_FEATURE_WOL
;
8301 if ((RTL_R8(Config3
) & LinkUp
) != 0)
8302 tp
->features
|= RTL_FEATURE_WOL
;
8305 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
8306 tp
->features
|= RTL_FEATURE_WOL
;
8309 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
8310 tp
->features
|= RTL_FEATURE_WOL
;
8311 tp
->features
|= rtl_try_msi(tp
, cfg
);
8312 RTL_W8(Cfg9346
, Cfg9346_Lock
);
8314 if (rtl_tbi_enabled(tp
)) {
8315 tp
->set_speed
= rtl8169_set_speed_tbi
;
8316 tp
->get_settings
= rtl8169_gset_tbi
;
8317 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
8318 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
8319 tp
->link_ok
= rtl8169_tbi_link_ok
;
8320 tp
->do_ioctl
= rtl_tbi_ioctl
;
8322 tp
->set_speed
= rtl8169_set_speed_xmii
;
8323 tp
->get_settings
= rtl8169_gset_xmii
;
8324 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
8325 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
8326 tp
->link_ok
= rtl8169_xmii_link_ok
;
8327 tp
->do_ioctl
= rtl_xmii_ioctl
;
8330 mutex_init(&tp
->wk
.mutex
);
8331 u64_stats_init(&tp
->rx_stats
.syncp
);
8332 u64_stats_init(&tp
->tx_stats
.syncp
);
8334 /* Get MAC address */
8335 if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
8336 tp
->mac_version
== RTL_GIGA_MAC_VER_36
||
8337 tp
->mac_version
== RTL_GIGA_MAC_VER_37
||
8338 tp
->mac_version
== RTL_GIGA_MAC_VER_38
||
8339 tp
->mac_version
== RTL_GIGA_MAC_VER_40
||
8340 tp
->mac_version
== RTL_GIGA_MAC_VER_41
||
8341 tp
->mac_version
== RTL_GIGA_MAC_VER_42
||
8342 tp
->mac_version
== RTL_GIGA_MAC_VER_43
||
8343 tp
->mac_version
== RTL_GIGA_MAC_VER_44
||
8344 tp
->mac_version
== RTL_GIGA_MAC_VER_45
||
8345 tp
->mac_version
== RTL_GIGA_MAC_VER_46
||
8346 tp
->mac_version
== RTL_GIGA_MAC_VER_47
||
8347 tp
->mac_version
== RTL_GIGA_MAC_VER_48
||
8348 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
8349 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
8350 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) {
8353 *(u32
*)&mac_addr
[0] = rtl_eri_read(tp
, 0xe0, ERIAR_EXGMAC
);
8354 *(u16
*)&mac_addr
[2] = rtl_eri_read(tp
, 0xe4, ERIAR_EXGMAC
);
8356 if (is_valid_ether_addr((u8
*)mac_addr
))
8357 rtl_rar_set(tp
, (u8
*)mac_addr
);
8359 for (i
= 0; i
< ETH_ALEN
; i
++)
8360 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
8362 dev
->ethtool_ops
= &rtl8169_ethtool_ops
;
8363 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
8365 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
8367 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8368 * properly for all devices */
8369 dev
->features
|= NETIF_F_RXCSUM
|
8370 NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
;
8372 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
8373 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
|
8374 NETIF_F_HW_VLAN_CTAG_RX
;
8375 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
8378 tp
->cp_cmd
|= RxChkSum
| RxVlan
;
8381 * Pretend we are using VLANs; This bypasses a nasty bug where
8382 * Interrupts stop flowing on high load on 8110SCd controllers.
8384 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
8385 /* Disallow toggling */
8386 dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_RX
;
8388 if (tp
->txd_version
== RTL_TD_0
)
8389 tp
->tso_csum
= rtl8169_tso_csum_v1
;
8390 else if (tp
->txd_version
== RTL_TD_1
) {
8391 tp
->tso_csum
= rtl8169_tso_csum_v2
;
8392 dev
->hw_features
|= NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
;
8396 dev
->hw_features
|= NETIF_F_RXALL
;
8397 dev
->hw_features
|= NETIF_F_RXFCS
;
8399 tp
->hw_start
= cfg
->hw_start
;
8400 tp
->event_slow
= cfg
->event_slow
;
8402 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
8403 ~(RxBOVF
| RxFOVF
) : ~0;
8405 init_timer(&tp
->timer
);
8406 tp
->timer
.data
= (unsigned long) dev
;
8407 tp
->timer
.function
= rtl8169_phy_timer
;
8409 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
8411 tp
->counters
= dma_alloc_coherent (&pdev
->dev
, sizeof(*tp
->counters
),
8412 &tp
->counters_phys_addr
, GFP_KERNEL
);
8413 if (!tp
->counters
) {
8418 rc
= register_netdev(dev
);
8422 pci_set_drvdata(pdev
, dev
);
8424 netif_info(tp
, probe
, dev
, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8425 rtl_chip_infos
[chipset
].name
, ioaddr
, dev
->dev_addr
,
8426 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), pdev
->irq
);
8427 if (rtl_chip_infos
[chipset
].jumbo_max
!= JUMBO_1K
) {
8428 netif_info(tp
, probe
, dev
, "jumbo features [frames: %d bytes, "
8429 "tx checksumming: %s]\n",
8430 rtl_chip_infos
[chipset
].jumbo_max
,
8431 rtl_chip_infos
[chipset
].jumbo_tx_csum
? "ok" : "ko");
8434 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
8435 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
8436 tp
->mac_version
== RTL_GIGA_MAC_VER_31
||
8437 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
8438 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
8439 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) &&
8440 r8168_check_dash(tp
)) {
8441 rtl8168_driver_start(tp
);
8444 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
8446 if (pci_dev_run_wake(pdev
))
8447 pm_runtime_put_noidle(&pdev
->dev
);
8449 netif_carrier_off(dev
);
8455 dma_free_coherent(&pdev
->dev
, sizeof(*tp
->counters
), tp
->counters
,
8456 tp
->counters_phys_addr
);
8458 netif_napi_del(&tp
->napi
);
8459 rtl_disable_msi(pdev
, tp
);
8462 pci_release_regions(pdev
);
8464 pci_clear_mwi(pdev
);
8465 pci_disable_device(pdev
);
8471 static struct pci_driver rtl8169_pci_driver
= {
8473 .id_table
= rtl8169_pci_tbl
,
8474 .probe
= rtl_init_one
,
8475 .remove
= rtl_remove_one
,
8476 .shutdown
= rtl_shutdown
,
8477 .driver
.pm
= RTL8169_PM_OPS
,
8480 module_pci_driver(rtl8169_pci_driver
);