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r8169: adjust some functions of 8111f
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48
49 #ifdef RTL8169_DEBUG
50 #define assert(expr) \
51 if (!(expr)) { \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
53 #expr,__FILE__,__func__,__LINE__); \
54 }
55 #define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
57 #else
58 #define assert(expr) do {} while (0)
59 #define dprintk(fmt, args...) do {} while (0)
60 #endif /* RTL8169_DEBUG */
61
62 #define R8169_MSG_DEFAULT \
63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
64
65 #define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
67
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit = 32;
71
72 #define MAX_READ_REQUEST_SHIFT 12
73 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77 #define R8169_REGS_SIZE 256
78 #define R8169_NAPI_WEIGHT 64
79 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85 #define RTL8169_TX_TIMEOUT (6*HZ)
86 #define RTL8169_PHY_TIMEOUT (10*HZ)
87
88 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR 0x0000
91
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg) readb (ioaddr + (reg))
97 #define RTL_R16(reg) readw (ioaddr + (reg))
98 #define RTL_R32(reg) readl (ioaddr + (reg))
99
100 enum mac_version {
101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_33,
134 RTL_GIGA_MAC_VER_34,
135 RTL_GIGA_MAC_VER_35,
136 RTL_GIGA_MAC_VER_36,
137 RTL_GIGA_MAC_VER_37,
138 RTL_GIGA_MAC_NONE = 0xff,
139 };
140
141 enum rtl_tx_desc_version {
142 RTL_TD_0 = 0,
143 RTL_TD_1 = 1,
144 };
145
146 #define JUMBO_1K ETH_DATA_LEN
147 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
148 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
149 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
150 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
151
152 #define _R(NAME,TD,FW,SZ,B) { \
153 .name = NAME, \
154 .txd_version = TD, \
155 .fw_name = FW, \
156 .jumbo_max = SZ, \
157 .jumbo_tx_csum = B \
158 }
159
160 static const struct {
161 const char *name;
162 enum rtl_tx_desc_version txd_version;
163 const char *fw_name;
164 u16 jumbo_max;
165 bool jumbo_tx_csum;
166 } rtl_chip_infos[] = {
167 /* PCI devices. */
168 [RTL_GIGA_MAC_VER_01] =
169 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
170 [RTL_GIGA_MAC_VER_02] =
171 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
172 [RTL_GIGA_MAC_VER_03] =
173 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
174 [RTL_GIGA_MAC_VER_04] =
175 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
176 [RTL_GIGA_MAC_VER_05] =
177 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
178 [RTL_GIGA_MAC_VER_06] =
179 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
180 /* PCI-E devices. */
181 [RTL_GIGA_MAC_VER_07] =
182 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
183 [RTL_GIGA_MAC_VER_08] =
184 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
185 [RTL_GIGA_MAC_VER_09] =
186 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
187 [RTL_GIGA_MAC_VER_10] =
188 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
189 [RTL_GIGA_MAC_VER_11] =
190 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
191 [RTL_GIGA_MAC_VER_12] =
192 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
193 [RTL_GIGA_MAC_VER_13] =
194 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
195 [RTL_GIGA_MAC_VER_14] =
196 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
197 [RTL_GIGA_MAC_VER_15] =
198 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
199 [RTL_GIGA_MAC_VER_16] =
200 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
201 [RTL_GIGA_MAC_VER_17] =
202 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
203 [RTL_GIGA_MAC_VER_18] =
204 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
205 [RTL_GIGA_MAC_VER_19] =
206 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
207 [RTL_GIGA_MAC_VER_20] =
208 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
209 [RTL_GIGA_MAC_VER_21] =
210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
211 [RTL_GIGA_MAC_VER_22] =
212 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
213 [RTL_GIGA_MAC_VER_23] =
214 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
215 [RTL_GIGA_MAC_VER_24] =
216 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
217 [RTL_GIGA_MAC_VER_25] =
218 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
219 JUMBO_9K, false),
220 [RTL_GIGA_MAC_VER_26] =
221 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
222 JUMBO_9K, false),
223 [RTL_GIGA_MAC_VER_27] =
224 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
225 [RTL_GIGA_MAC_VER_28] =
226 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
227 [RTL_GIGA_MAC_VER_29] =
228 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
229 JUMBO_1K, true),
230 [RTL_GIGA_MAC_VER_30] =
231 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
232 JUMBO_1K, true),
233 [RTL_GIGA_MAC_VER_31] =
234 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
235 [RTL_GIGA_MAC_VER_32] =
236 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
237 JUMBO_9K, false),
238 [RTL_GIGA_MAC_VER_33] =
239 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
240 JUMBO_9K, false),
241 [RTL_GIGA_MAC_VER_34] =
242 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
243 JUMBO_9K, false),
244 [RTL_GIGA_MAC_VER_35] =
245 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
246 JUMBO_9K, false),
247 [RTL_GIGA_MAC_VER_36] =
248 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
249 JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_37] =
251 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
252 JUMBO_1K, true),
253 };
254 #undef _R
255
256 enum cfg_version {
257 RTL_CFG_0 = 0x00,
258 RTL_CFG_1,
259 RTL_CFG_2
260 };
261
262 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
270 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
272 { PCI_VENDOR_ID_LINKSYS, 0x1032,
273 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
274 { 0x0001, 0x8168,
275 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
276 {0,},
277 };
278
279 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
280
281 static int rx_buf_sz = 16383;
282 static int use_dac;
283 static struct {
284 u32 msg_enable;
285 } debug = { -1 };
286
287 enum rtl_registers {
288 MAC0 = 0, /* Ethernet hardware address. */
289 MAC4 = 4,
290 MAR0 = 8, /* Multicast filter. */
291 CounterAddrLow = 0x10,
292 CounterAddrHigh = 0x14,
293 TxDescStartAddrLow = 0x20,
294 TxDescStartAddrHigh = 0x24,
295 TxHDescStartAddrLow = 0x28,
296 TxHDescStartAddrHigh = 0x2c,
297 FLASH = 0x30,
298 ERSR = 0x36,
299 ChipCmd = 0x37,
300 TxPoll = 0x38,
301 IntrMask = 0x3c,
302 IntrStatus = 0x3e,
303
304 TxConfig = 0x40,
305 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
306 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
307
308 RxConfig = 0x44,
309 #define RX128_INT_EN (1 << 15) /* 8111c and later */
310 #define RX_MULTI_EN (1 << 14) /* 8111c only */
311 #define RXCFG_FIFO_SHIFT 13
312 /* No threshold before first PCI xfer */
313 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
314 #define RXCFG_DMA_SHIFT 8
315 /* Unlimited maximum PCI burst. */
316 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
317
318 RxMissed = 0x4c,
319 Cfg9346 = 0x50,
320 Config0 = 0x51,
321 Config1 = 0x52,
322 Config2 = 0x53,
323 #define PME_SIGNAL (1 << 5) /* 8168c and later */
324
325 Config3 = 0x54,
326 Config4 = 0x55,
327 Config5 = 0x56,
328 MultiIntr = 0x5c,
329 PHYAR = 0x60,
330 PHYstatus = 0x6c,
331 RxMaxSize = 0xda,
332 CPlusCmd = 0xe0,
333 IntrMitigate = 0xe2,
334 RxDescAddrLow = 0xe4,
335 RxDescAddrHigh = 0xe8,
336 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
337
338 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
339
340 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
341
342 #define TxPacketMax (8064 >> 7)
343 #define EarlySize 0x27
344
345 FuncEvent = 0xf0,
346 FuncEventMask = 0xf4,
347 FuncPresetState = 0xf8,
348 FuncForceEvent = 0xfc,
349 };
350
351 enum rtl8110_registers {
352 TBICSR = 0x64,
353 TBI_ANAR = 0x68,
354 TBI_LPAR = 0x6a,
355 };
356
357 enum rtl8168_8101_registers {
358 CSIDR = 0x64,
359 CSIAR = 0x68,
360 #define CSIAR_FLAG 0x80000000
361 #define CSIAR_WRITE_CMD 0x80000000
362 #define CSIAR_BYTE_ENABLE 0x0f
363 #define CSIAR_BYTE_ENABLE_SHIFT 12
364 #define CSIAR_ADDR_MASK 0x0fff
365 #define CSIAR_FUNC_CARD 0x00000000
366 #define CSIAR_FUNC_SDIO 0x00010000
367 #define CSIAR_FUNC_NIC 0x00020000
368 PMCH = 0x6f,
369 EPHYAR = 0x80,
370 #define EPHYAR_FLAG 0x80000000
371 #define EPHYAR_WRITE_CMD 0x80000000
372 #define EPHYAR_REG_MASK 0x1f
373 #define EPHYAR_REG_SHIFT 16
374 #define EPHYAR_DATA_MASK 0xffff
375 DLLPR = 0xd0,
376 #define PFM_EN (1 << 6)
377 DBG_REG = 0xd1,
378 #define FIX_NAK_1 (1 << 4)
379 #define FIX_NAK_2 (1 << 3)
380 TWSI = 0xd2,
381 MCU = 0xd3,
382 #define NOW_IS_OOB (1 << 7)
383 #define EN_NDP (1 << 3)
384 #define EN_OOB_RESET (1 << 2)
385 EFUSEAR = 0xdc,
386 #define EFUSEAR_FLAG 0x80000000
387 #define EFUSEAR_WRITE_CMD 0x80000000
388 #define EFUSEAR_READ_CMD 0x00000000
389 #define EFUSEAR_REG_MASK 0x03ff
390 #define EFUSEAR_REG_SHIFT 8
391 #define EFUSEAR_DATA_MASK 0xff
392 };
393
394 enum rtl8168_registers {
395 LED_FREQ = 0x1a,
396 EEE_LED = 0x1b,
397 ERIDR = 0x70,
398 ERIAR = 0x74,
399 #define ERIAR_FLAG 0x80000000
400 #define ERIAR_WRITE_CMD 0x80000000
401 #define ERIAR_READ_CMD 0x00000000
402 #define ERIAR_ADDR_BYTE_ALIGN 4
403 #define ERIAR_TYPE_SHIFT 16
404 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
405 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
406 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
407 #define ERIAR_MASK_SHIFT 12
408 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
409 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
410 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
411 EPHY_RXER_NUM = 0x7c,
412 OCPDR = 0xb0, /* OCP GPHY access */
413 #define OCPDR_WRITE_CMD 0x80000000
414 #define OCPDR_READ_CMD 0x00000000
415 #define OCPDR_REG_MASK 0x7f
416 #define OCPDR_GPHY_REG_SHIFT 16
417 #define OCPDR_DATA_MASK 0xffff
418 OCPAR = 0xb4,
419 #define OCPAR_FLAG 0x80000000
420 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
421 #define OCPAR_GPHY_READ_CMD 0x0000f060
422 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
423 MISC = 0xf0, /* 8168e only. */
424 #define TXPLA_RST (1 << 29)
425 #define PWM_EN (1 << 22)
426 };
427
428 enum rtl_register_content {
429 /* InterruptStatusBits */
430 SYSErr = 0x8000,
431 PCSTimeout = 0x4000,
432 SWInt = 0x0100,
433 TxDescUnavail = 0x0080,
434 RxFIFOOver = 0x0040,
435 LinkChg = 0x0020,
436 RxOverflow = 0x0010,
437 TxErr = 0x0008,
438 TxOK = 0x0004,
439 RxErr = 0x0002,
440 RxOK = 0x0001,
441
442 /* RxStatusDesc */
443 RxBOVF = (1 << 24),
444 RxFOVF = (1 << 23),
445 RxRWT = (1 << 22),
446 RxRES = (1 << 21),
447 RxRUNT = (1 << 20),
448 RxCRC = (1 << 19),
449
450 /* ChipCmdBits */
451 StopReq = 0x80,
452 CmdReset = 0x10,
453 CmdRxEnb = 0x08,
454 CmdTxEnb = 0x04,
455 RxBufEmpty = 0x01,
456
457 /* TXPoll register p.5 */
458 HPQ = 0x80, /* Poll cmd on the high prio queue */
459 NPQ = 0x40, /* Poll cmd on the low prio queue */
460 FSWInt = 0x01, /* Forced software interrupt */
461
462 /* Cfg9346Bits */
463 Cfg9346_Lock = 0x00,
464 Cfg9346_Unlock = 0xc0,
465
466 /* rx_mode_bits */
467 AcceptErr = 0x20,
468 AcceptRunt = 0x10,
469 AcceptBroadcast = 0x08,
470 AcceptMulticast = 0x04,
471 AcceptMyPhys = 0x02,
472 AcceptAllPhys = 0x01,
473 #define RX_CONFIG_ACCEPT_MASK 0x3f
474
475 /* TxConfigBits */
476 TxInterFrameGapShift = 24,
477 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
478
479 /* Config1 register p.24 */
480 LEDS1 = (1 << 7),
481 LEDS0 = (1 << 6),
482 Speed_down = (1 << 4),
483 MEMMAP = (1 << 3),
484 IOMAP = (1 << 2),
485 VPD = (1 << 1),
486 PMEnable = (1 << 0), /* Power Management Enable */
487
488 /* Config2 register p. 25 */
489 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
490 PCI_Clock_66MHz = 0x01,
491 PCI_Clock_33MHz = 0x00,
492
493 /* Config3 register p.25 */
494 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
495 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
496 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
497 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
498
499 /* Config4 register */
500 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
501
502 /* Config5 register p.27 */
503 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
504 MWF = (1 << 5), /* Accept Multicast wakeup frame */
505 UWF = (1 << 4), /* Accept Unicast wakeup frame */
506 Spi_en = (1 << 3),
507 LanWake = (1 << 1), /* LanWake enable/disable */
508 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
509
510 /* TBICSR p.28 */
511 TBIReset = 0x80000000,
512 TBILoopback = 0x40000000,
513 TBINwEnable = 0x20000000,
514 TBINwRestart = 0x10000000,
515 TBILinkOk = 0x02000000,
516 TBINwComplete = 0x01000000,
517
518 /* CPlusCmd p.31 */
519 EnableBist = (1 << 15), // 8168 8101
520 Mac_dbgo_oe = (1 << 14), // 8168 8101
521 Normal_mode = (1 << 13), // unused
522 Force_half_dup = (1 << 12), // 8168 8101
523 Force_rxflow_en = (1 << 11), // 8168 8101
524 Force_txflow_en = (1 << 10), // 8168 8101
525 Cxpl_dbg_sel = (1 << 9), // 8168 8101
526 ASF = (1 << 8), // 8168 8101
527 PktCntrDisable = (1 << 7), // 8168 8101
528 Mac_dbgo_sel = 0x001c, // 8168
529 RxVlan = (1 << 6),
530 RxChkSum = (1 << 5),
531 PCIDAC = (1 << 4),
532 PCIMulRW = (1 << 3),
533 INTT_0 = 0x0000, // 8168
534 INTT_1 = 0x0001, // 8168
535 INTT_2 = 0x0002, // 8168
536 INTT_3 = 0x0003, // 8168
537
538 /* rtl8169_PHYstatus */
539 TBI_Enable = 0x80,
540 TxFlowCtrl = 0x40,
541 RxFlowCtrl = 0x20,
542 _1000bpsF = 0x10,
543 _100bps = 0x08,
544 _10bps = 0x04,
545 LinkStatus = 0x02,
546 FullDup = 0x01,
547
548 /* _TBICSRBit */
549 TBILinkOK = 0x02000000,
550
551 /* DumpCounterCommand */
552 CounterDump = 0x8,
553 };
554
555 enum rtl_desc_bit {
556 /* First doubleword. */
557 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
558 RingEnd = (1 << 30), /* End of descriptor ring */
559 FirstFrag = (1 << 29), /* First segment of a packet */
560 LastFrag = (1 << 28), /* Final segment of a packet */
561 };
562
563 /* Generic case. */
564 enum rtl_tx_desc_bit {
565 /* First doubleword. */
566 TD_LSO = (1 << 27), /* Large Send Offload */
567 #define TD_MSS_MAX 0x07ffu /* MSS value */
568
569 /* Second doubleword. */
570 TxVlanTag = (1 << 17), /* Add VLAN tag */
571 };
572
573 /* 8169, 8168b and 810x except 8102e. */
574 enum rtl_tx_desc_bit_0 {
575 /* First doubleword. */
576 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
577 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
578 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
579 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
580 };
581
582 /* 8102e, 8168c and beyond. */
583 enum rtl_tx_desc_bit_1 {
584 /* Second doubleword. */
585 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
586 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
587 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
588 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
589 };
590
591 static const struct rtl_tx_desc_info {
592 struct {
593 u32 udp;
594 u32 tcp;
595 } checksum;
596 u16 mss_shift;
597 u16 opts_offset;
598 } tx_desc_info [] = {
599 [RTL_TD_0] = {
600 .checksum = {
601 .udp = TD0_IP_CS | TD0_UDP_CS,
602 .tcp = TD0_IP_CS | TD0_TCP_CS
603 },
604 .mss_shift = TD0_MSS_SHIFT,
605 .opts_offset = 0
606 },
607 [RTL_TD_1] = {
608 .checksum = {
609 .udp = TD1_IP_CS | TD1_UDP_CS,
610 .tcp = TD1_IP_CS | TD1_TCP_CS
611 },
612 .mss_shift = TD1_MSS_SHIFT,
613 .opts_offset = 1
614 }
615 };
616
617 enum rtl_rx_desc_bit {
618 /* Rx private */
619 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
620 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
621
622 #define RxProtoUDP (PID1)
623 #define RxProtoTCP (PID0)
624 #define RxProtoIP (PID1 | PID0)
625 #define RxProtoMask RxProtoIP
626
627 IPFail = (1 << 16), /* IP checksum failed */
628 UDPFail = (1 << 15), /* UDP/IP checksum failed */
629 TCPFail = (1 << 14), /* TCP/IP checksum failed */
630 RxVlanTag = (1 << 16), /* VLAN tag available */
631 };
632
633 #define RsvdMask 0x3fffc000
634
635 struct TxDesc {
636 __le32 opts1;
637 __le32 opts2;
638 __le64 addr;
639 };
640
641 struct RxDesc {
642 __le32 opts1;
643 __le32 opts2;
644 __le64 addr;
645 };
646
647 struct ring_info {
648 struct sk_buff *skb;
649 u32 len;
650 u8 __pad[sizeof(void *) - sizeof(u32)];
651 };
652
653 enum features {
654 RTL_FEATURE_WOL = (1 << 0),
655 RTL_FEATURE_MSI = (1 << 1),
656 RTL_FEATURE_GMII = (1 << 2),
657 };
658
659 struct rtl8169_counters {
660 __le64 tx_packets;
661 __le64 rx_packets;
662 __le64 tx_errors;
663 __le32 rx_errors;
664 __le16 rx_missed;
665 __le16 align_errors;
666 __le32 tx_one_collision;
667 __le32 tx_multi_collision;
668 __le64 rx_unicast;
669 __le64 rx_broadcast;
670 __le32 rx_multicast;
671 __le16 tx_aborted;
672 __le16 tx_underun;
673 };
674
675 enum rtl_flag {
676 RTL_FLAG_TASK_ENABLED,
677 RTL_FLAG_TASK_SLOW_PENDING,
678 RTL_FLAG_TASK_RESET_PENDING,
679 RTL_FLAG_TASK_PHY_PENDING,
680 RTL_FLAG_MAX
681 };
682
683 struct rtl8169_stats {
684 u64 packets;
685 u64 bytes;
686 struct u64_stats_sync syncp;
687 };
688
689 struct rtl8169_private {
690 void __iomem *mmio_addr; /* memory map physical address */
691 struct pci_dev *pci_dev;
692 struct net_device *dev;
693 struct napi_struct napi;
694 u32 msg_enable;
695 u16 txd_version;
696 u16 mac_version;
697 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
698 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
699 u32 dirty_rx;
700 u32 dirty_tx;
701 struct rtl8169_stats rx_stats;
702 struct rtl8169_stats tx_stats;
703 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
704 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
705 dma_addr_t TxPhyAddr;
706 dma_addr_t RxPhyAddr;
707 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
708 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
709 struct timer_list timer;
710 u16 cp_cmd;
711
712 u16 event_slow;
713
714 struct mdio_ops {
715 void (*write)(void __iomem *, int, int);
716 int (*read)(void __iomem *, int);
717 } mdio_ops;
718
719 struct pll_power_ops {
720 void (*down)(struct rtl8169_private *);
721 void (*up)(struct rtl8169_private *);
722 } pll_power_ops;
723
724 struct jumbo_ops {
725 void (*enable)(struct rtl8169_private *);
726 void (*disable)(struct rtl8169_private *);
727 } jumbo_ops;
728
729 struct csi_ops {
730 void (*write)(void __iomem *, int, int);
731 u32 (*read)(void __iomem *, int);
732 } csi_ops;
733
734 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
735 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
736 void (*phy_reset_enable)(struct rtl8169_private *tp);
737 void (*hw_start)(struct net_device *);
738 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
739 unsigned int (*link_ok)(void __iomem *);
740 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
741
742 struct {
743 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
744 struct mutex mutex;
745 struct work_struct work;
746 } wk;
747
748 unsigned features;
749
750 struct mii_if_info mii;
751 struct rtl8169_counters counters;
752 u32 saved_wolopts;
753 u32 opts1_mask;
754
755 struct rtl_fw {
756 const struct firmware *fw;
757
758 #define RTL_VER_SIZE 32
759
760 char version[RTL_VER_SIZE];
761
762 struct rtl_fw_phy_action {
763 __le32 *code;
764 size_t size;
765 } phy_action;
766 } *rtl_fw;
767 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
768 };
769
770 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
771 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
772 module_param(use_dac, int, 0);
773 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
774 module_param_named(debug, debug.msg_enable, int, 0);
775 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
776 MODULE_LICENSE("GPL");
777 MODULE_VERSION(RTL8169_VERSION);
778 MODULE_FIRMWARE(FIRMWARE_8168D_1);
779 MODULE_FIRMWARE(FIRMWARE_8168D_2);
780 MODULE_FIRMWARE(FIRMWARE_8168E_1);
781 MODULE_FIRMWARE(FIRMWARE_8168E_2);
782 MODULE_FIRMWARE(FIRMWARE_8168E_3);
783 MODULE_FIRMWARE(FIRMWARE_8105E_1);
784 MODULE_FIRMWARE(FIRMWARE_8168F_1);
785 MODULE_FIRMWARE(FIRMWARE_8168F_2);
786 MODULE_FIRMWARE(FIRMWARE_8402_1);
787
788 static void rtl_lock_work(struct rtl8169_private *tp)
789 {
790 mutex_lock(&tp->wk.mutex);
791 }
792
793 static void rtl_unlock_work(struct rtl8169_private *tp)
794 {
795 mutex_unlock(&tp->wk.mutex);
796 }
797
798 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
799 {
800 int cap = pci_pcie_cap(pdev);
801
802 if (cap) {
803 u16 ctl;
804
805 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
806 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
807 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
808 }
809 }
810
811 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
812 {
813 void __iomem *ioaddr = tp->mmio_addr;
814 int i;
815
816 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
817 for (i = 0; i < 20; i++) {
818 udelay(100);
819 if (RTL_R32(OCPAR) & OCPAR_FLAG)
820 break;
821 }
822 return RTL_R32(OCPDR);
823 }
824
825 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
826 {
827 void __iomem *ioaddr = tp->mmio_addr;
828 int i;
829
830 RTL_W32(OCPDR, data);
831 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
832 for (i = 0; i < 20; i++) {
833 udelay(100);
834 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
835 break;
836 }
837 }
838
839 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
840 {
841 void __iomem *ioaddr = tp->mmio_addr;
842 int i;
843
844 RTL_W8(ERIDR, cmd);
845 RTL_W32(ERIAR, 0x800010e8);
846 msleep(2);
847 for (i = 0; i < 5; i++) {
848 udelay(100);
849 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
850 break;
851 }
852
853 ocp_write(tp, 0x1, 0x30, 0x00000001);
854 }
855
856 #define OOB_CMD_RESET 0x00
857 #define OOB_CMD_DRIVER_START 0x05
858 #define OOB_CMD_DRIVER_STOP 0x06
859
860 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
861 {
862 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
863 }
864
865 static void rtl8168_driver_start(struct rtl8169_private *tp)
866 {
867 u16 reg;
868 int i;
869
870 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
871
872 reg = rtl8168_get_ocp_reg(tp);
873
874 for (i = 0; i < 10; i++) {
875 msleep(10);
876 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
877 break;
878 }
879 }
880
881 static void rtl8168_driver_stop(struct rtl8169_private *tp)
882 {
883 u16 reg;
884 int i;
885
886 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
887
888 reg = rtl8168_get_ocp_reg(tp);
889
890 for (i = 0; i < 10; i++) {
891 msleep(10);
892 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
893 break;
894 }
895 }
896
897 static int r8168dp_check_dash(struct rtl8169_private *tp)
898 {
899 u16 reg = rtl8168_get_ocp_reg(tp);
900
901 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
902 }
903
904 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
905 {
906 int i;
907
908 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
909
910 for (i = 20; i > 0; i--) {
911 /*
912 * Check if the RTL8169 has completed writing to the specified
913 * MII register.
914 */
915 if (!(RTL_R32(PHYAR) & 0x80000000))
916 break;
917 udelay(25);
918 }
919 /*
920 * According to hardware specs a 20us delay is required after write
921 * complete indication, but before sending next command.
922 */
923 udelay(20);
924 }
925
926 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
927 {
928 int i, value = -1;
929
930 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
931
932 for (i = 20; i > 0; i--) {
933 /*
934 * Check if the RTL8169 has completed retrieving data from
935 * the specified MII register.
936 */
937 if (RTL_R32(PHYAR) & 0x80000000) {
938 value = RTL_R32(PHYAR) & 0xffff;
939 break;
940 }
941 udelay(25);
942 }
943 /*
944 * According to hardware specs a 20us delay is required after read
945 * complete indication, but before sending next command.
946 */
947 udelay(20);
948
949 return value;
950 }
951
952 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
953 {
954 int i;
955
956 RTL_W32(OCPDR, data |
957 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
958 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
959 RTL_W32(EPHY_RXER_NUM, 0);
960
961 for (i = 0; i < 100; i++) {
962 mdelay(1);
963 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
964 break;
965 }
966 }
967
968 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
969 {
970 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
971 (value & OCPDR_DATA_MASK));
972 }
973
974 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
975 {
976 int i;
977
978 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
979
980 mdelay(1);
981 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
982 RTL_W32(EPHY_RXER_NUM, 0);
983
984 for (i = 0; i < 100; i++) {
985 mdelay(1);
986 if (RTL_R32(OCPAR) & OCPAR_FLAG)
987 break;
988 }
989
990 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
991 }
992
993 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
994
995 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
996 {
997 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
998 }
999
1000 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1001 {
1002 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1003 }
1004
1005 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1006 {
1007 r8168dp_2_mdio_start(ioaddr);
1008
1009 r8169_mdio_write(ioaddr, reg_addr, value);
1010
1011 r8168dp_2_mdio_stop(ioaddr);
1012 }
1013
1014 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1015 {
1016 int value;
1017
1018 r8168dp_2_mdio_start(ioaddr);
1019
1020 value = r8169_mdio_read(ioaddr, reg_addr);
1021
1022 r8168dp_2_mdio_stop(ioaddr);
1023
1024 return value;
1025 }
1026
1027 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1028 {
1029 tp->mdio_ops.write(tp->mmio_addr, location, val);
1030 }
1031
1032 static int rtl_readphy(struct rtl8169_private *tp, int location)
1033 {
1034 return tp->mdio_ops.read(tp->mmio_addr, location);
1035 }
1036
1037 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1038 {
1039 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1040 }
1041
1042 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1043 {
1044 int val;
1045
1046 val = rtl_readphy(tp, reg_addr);
1047 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1048 }
1049
1050 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1051 int val)
1052 {
1053 struct rtl8169_private *tp = netdev_priv(dev);
1054
1055 rtl_writephy(tp, location, val);
1056 }
1057
1058 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1059 {
1060 struct rtl8169_private *tp = netdev_priv(dev);
1061
1062 return rtl_readphy(tp, location);
1063 }
1064
1065 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1066 {
1067 unsigned int i;
1068
1069 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1070 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1071
1072 for (i = 0; i < 100; i++) {
1073 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1074 break;
1075 udelay(10);
1076 }
1077 }
1078
1079 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1080 {
1081 u16 value = 0xffff;
1082 unsigned int i;
1083
1084 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1085
1086 for (i = 0; i < 100; i++) {
1087 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1088 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1089 break;
1090 }
1091 udelay(10);
1092 }
1093
1094 return value;
1095 }
1096
1097 static
1098 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1099 {
1100 unsigned int i;
1101
1102 BUG_ON((addr & 3) || (mask == 0));
1103 RTL_W32(ERIDR, val);
1104 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1105
1106 for (i = 0; i < 100; i++) {
1107 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1108 break;
1109 udelay(100);
1110 }
1111 }
1112
1113 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1114 {
1115 u32 value = ~0x00;
1116 unsigned int i;
1117
1118 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1119
1120 for (i = 0; i < 100; i++) {
1121 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1122 value = RTL_R32(ERIDR);
1123 break;
1124 }
1125 udelay(100);
1126 }
1127
1128 return value;
1129 }
1130
1131 static void
1132 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1133 {
1134 u32 val;
1135
1136 val = rtl_eri_read(ioaddr, addr, type);
1137 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1138 }
1139
1140 struct exgmac_reg {
1141 u16 addr;
1142 u16 mask;
1143 u32 val;
1144 };
1145
1146 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1147 const struct exgmac_reg *r, int len)
1148 {
1149 while (len-- > 0) {
1150 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1151 r++;
1152 }
1153 }
1154
1155 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1156 {
1157 u8 value = 0xff;
1158 unsigned int i;
1159
1160 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1161
1162 for (i = 0; i < 300; i++) {
1163 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1164 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1165 break;
1166 }
1167 udelay(100);
1168 }
1169
1170 return value;
1171 }
1172
1173 static u16 rtl_get_events(struct rtl8169_private *tp)
1174 {
1175 void __iomem *ioaddr = tp->mmio_addr;
1176
1177 return RTL_R16(IntrStatus);
1178 }
1179
1180 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1181 {
1182 void __iomem *ioaddr = tp->mmio_addr;
1183
1184 RTL_W16(IntrStatus, bits);
1185 mmiowb();
1186 }
1187
1188 static void rtl_irq_disable(struct rtl8169_private *tp)
1189 {
1190 void __iomem *ioaddr = tp->mmio_addr;
1191
1192 RTL_W16(IntrMask, 0);
1193 mmiowb();
1194 }
1195
1196 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1197 {
1198 void __iomem *ioaddr = tp->mmio_addr;
1199
1200 RTL_W16(IntrMask, bits);
1201 }
1202
1203 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1204 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1205 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1206
1207 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1208 {
1209 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1210 }
1211
1212 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1213 {
1214 void __iomem *ioaddr = tp->mmio_addr;
1215
1216 rtl_irq_disable(tp);
1217 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1218 RTL_R8(ChipCmd);
1219 }
1220
1221 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1222 {
1223 void __iomem *ioaddr = tp->mmio_addr;
1224
1225 return RTL_R32(TBICSR) & TBIReset;
1226 }
1227
1228 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1229 {
1230 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1231 }
1232
1233 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1234 {
1235 return RTL_R32(TBICSR) & TBILinkOk;
1236 }
1237
1238 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1239 {
1240 return RTL_R8(PHYstatus) & LinkStatus;
1241 }
1242
1243 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1244 {
1245 void __iomem *ioaddr = tp->mmio_addr;
1246
1247 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1248 }
1249
1250 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1251 {
1252 unsigned int val;
1253
1254 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1255 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1256 }
1257
1258 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1259 {
1260 void __iomem *ioaddr = tp->mmio_addr;
1261 struct net_device *dev = tp->dev;
1262
1263 if (!netif_running(dev))
1264 return;
1265
1266 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1267 if (RTL_R8(PHYstatus) & _1000bpsF) {
1268 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1269 0x00000011, ERIAR_EXGMAC);
1270 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1271 0x00000005, ERIAR_EXGMAC);
1272 } else if (RTL_R8(PHYstatus) & _100bps) {
1273 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1274 0x0000001f, ERIAR_EXGMAC);
1275 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1276 0x00000005, ERIAR_EXGMAC);
1277 } else {
1278 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1279 0x0000001f, ERIAR_EXGMAC);
1280 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1281 0x0000003f, ERIAR_EXGMAC);
1282 }
1283 /* Reset packet filter */
1284 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1285 ERIAR_EXGMAC);
1286 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1287 ERIAR_EXGMAC);
1288 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1289 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1290 if (RTL_R8(PHYstatus) & _1000bpsF) {
1291 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1292 0x00000011, ERIAR_EXGMAC);
1293 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1294 0x00000005, ERIAR_EXGMAC);
1295 } else {
1296 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1297 0x0000001f, ERIAR_EXGMAC);
1298 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1299 0x0000003f, ERIAR_EXGMAC);
1300 }
1301 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1302 if (RTL_R8(PHYstatus) & _10bps) {
1303 rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
1304 0x4d02, ERIAR_EXGMAC);
1305 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_0011,
1306 0x0060, ERIAR_EXGMAC);
1307 } else {
1308 rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
1309 0x0000, ERIAR_EXGMAC);
1310 }
1311 }
1312 }
1313
1314 static void __rtl8169_check_link_status(struct net_device *dev,
1315 struct rtl8169_private *tp,
1316 void __iomem *ioaddr, bool pm)
1317 {
1318 if (tp->link_ok(ioaddr)) {
1319 rtl_link_chg_patch(tp);
1320 /* This is to cancel a scheduled suspend if there's one. */
1321 if (pm)
1322 pm_request_resume(&tp->pci_dev->dev);
1323 netif_carrier_on(dev);
1324 if (net_ratelimit())
1325 netif_info(tp, ifup, dev, "link up\n");
1326 } else {
1327 netif_carrier_off(dev);
1328 netif_info(tp, ifdown, dev, "link down\n");
1329 if (pm)
1330 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1331 }
1332 }
1333
1334 static void rtl8169_check_link_status(struct net_device *dev,
1335 struct rtl8169_private *tp,
1336 void __iomem *ioaddr)
1337 {
1338 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1339 }
1340
1341 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1342
1343 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1344 {
1345 void __iomem *ioaddr = tp->mmio_addr;
1346 u8 options;
1347 u32 wolopts = 0;
1348
1349 options = RTL_R8(Config1);
1350 if (!(options & PMEnable))
1351 return 0;
1352
1353 options = RTL_R8(Config3);
1354 if (options & LinkUp)
1355 wolopts |= WAKE_PHY;
1356 if (options & MagicPacket)
1357 wolopts |= WAKE_MAGIC;
1358
1359 options = RTL_R8(Config5);
1360 if (options & UWF)
1361 wolopts |= WAKE_UCAST;
1362 if (options & BWF)
1363 wolopts |= WAKE_BCAST;
1364 if (options & MWF)
1365 wolopts |= WAKE_MCAST;
1366
1367 return wolopts;
1368 }
1369
1370 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1371 {
1372 struct rtl8169_private *tp = netdev_priv(dev);
1373
1374 rtl_lock_work(tp);
1375
1376 wol->supported = WAKE_ANY;
1377 wol->wolopts = __rtl8169_get_wol(tp);
1378
1379 rtl_unlock_work(tp);
1380 }
1381
1382 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1383 {
1384 void __iomem *ioaddr = tp->mmio_addr;
1385 unsigned int i;
1386 static const struct {
1387 u32 opt;
1388 u16 reg;
1389 u8 mask;
1390 } cfg[] = {
1391 { WAKE_PHY, Config3, LinkUp },
1392 { WAKE_MAGIC, Config3, MagicPacket },
1393 { WAKE_UCAST, Config5, UWF },
1394 { WAKE_BCAST, Config5, BWF },
1395 { WAKE_MCAST, Config5, MWF },
1396 { WAKE_ANY, Config5, LanWake }
1397 };
1398 u8 options;
1399
1400 RTL_W8(Cfg9346, Cfg9346_Unlock);
1401
1402 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1403 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1404 if (wolopts & cfg[i].opt)
1405 options |= cfg[i].mask;
1406 RTL_W8(cfg[i].reg, options);
1407 }
1408
1409 switch (tp->mac_version) {
1410 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1411 options = RTL_R8(Config1) & ~PMEnable;
1412 if (wolopts)
1413 options |= PMEnable;
1414 RTL_W8(Config1, options);
1415 break;
1416 default:
1417 options = RTL_R8(Config2) & ~PME_SIGNAL;
1418 if (wolopts)
1419 options |= PME_SIGNAL;
1420 RTL_W8(Config2, options);
1421 break;
1422 }
1423
1424 RTL_W8(Cfg9346, Cfg9346_Lock);
1425 }
1426
1427 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1428 {
1429 struct rtl8169_private *tp = netdev_priv(dev);
1430
1431 rtl_lock_work(tp);
1432
1433 if (wol->wolopts)
1434 tp->features |= RTL_FEATURE_WOL;
1435 else
1436 tp->features &= ~RTL_FEATURE_WOL;
1437 __rtl8169_set_wol(tp, wol->wolopts);
1438
1439 rtl_unlock_work(tp);
1440
1441 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1442
1443 return 0;
1444 }
1445
1446 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1447 {
1448 return rtl_chip_infos[tp->mac_version].fw_name;
1449 }
1450
1451 static void rtl8169_get_drvinfo(struct net_device *dev,
1452 struct ethtool_drvinfo *info)
1453 {
1454 struct rtl8169_private *tp = netdev_priv(dev);
1455 struct rtl_fw *rtl_fw = tp->rtl_fw;
1456
1457 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1458 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1459 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1460 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1461 if (!IS_ERR_OR_NULL(rtl_fw))
1462 strlcpy(info->fw_version, rtl_fw->version,
1463 sizeof(info->fw_version));
1464 }
1465
1466 static int rtl8169_get_regs_len(struct net_device *dev)
1467 {
1468 return R8169_REGS_SIZE;
1469 }
1470
1471 static int rtl8169_set_speed_tbi(struct net_device *dev,
1472 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1473 {
1474 struct rtl8169_private *tp = netdev_priv(dev);
1475 void __iomem *ioaddr = tp->mmio_addr;
1476 int ret = 0;
1477 u32 reg;
1478
1479 reg = RTL_R32(TBICSR);
1480 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1481 (duplex == DUPLEX_FULL)) {
1482 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1483 } else if (autoneg == AUTONEG_ENABLE)
1484 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1485 else {
1486 netif_warn(tp, link, dev,
1487 "incorrect speed setting refused in TBI mode\n");
1488 ret = -EOPNOTSUPP;
1489 }
1490
1491 return ret;
1492 }
1493
1494 static int rtl8169_set_speed_xmii(struct net_device *dev,
1495 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1496 {
1497 struct rtl8169_private *tp = netdev_priv(dev);
1498 int giga_ctrl, bmcr;
1499 int rc = -EINVAL;
1500
1501 rtl_writephy(tp, 0x1f, 0x0000);
1502
1503 if (autoneg == AUTONEG_ENABLE) {
1504 int auto_nego;
1505
1506 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1507 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1508 ADVERTISE_100HALF | ADVERTISE_100FULL);
1509
1510 if (adv & ADVERTISED_10baseT_Half)
1511 auto_nego |= ADVERTISE_10HALF;
1512 if (adv & ADVERTISED_10baseT_Full)
1513 auto_nego |= ADVERTISE_10FULL;
1514 if (adv & ADVERTISED_100baseT_Half)
1515 auto_nego |= ADVERTISE_100HALF;
1516 if (adv & ADVERTISED_100baseT_Full)
1517 auto_nego |= ADVERTISE_100FULL;
1518
1519 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1520
1521 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1522 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1523
1524 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1525 if (tp->mii.supports_gmii) {
1526 if (adv & ADVERTISED_1000baseT_Half)
1527 giga_ctrl |= ADVERTISE_1000HALF;
1528 if (adv & ADVERTISED_1000baseT_Full)
1529 giga_ctrl |= ADVERTISE_1000FULL;
1530 } else if (adv & (ADVERTISED_1000baseT_Half |
1531 ADVERTISED_1000baseT_Full)) {
1532 netif_info(tp, link, dev,
1533 "PHY does not support 1000Mbps\n");
1534 goto out;
1535 }
1536
1537 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1538
1539 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1540 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1541 } else {
1542 giga_ctrl = 0;
1543
1544 if (speed == SPEED_10)
1545 bmcr = 0;
1546 else if (speed == SPEED_100)
1547 bmcr = BMCR_SPEED100;
1548 else
1549 goto out;
1550
1551 if (duplex == DUPLEX_FULL)
1552 bmcr |= BMCR_FULLDPLX;
1553 }
1554
1555 rtl_writephy(tp, MII_BMCR, bmcr);
1556
1557 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1558 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1559 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1560 rtl_writephy(tp, 0x17, 0x2138);
1561 rtl_writephy(tp, 0x0e, 0x0260);
1562 } else {
1563 rtl_writephy(tp, 0x17, 0x2108);
1564 rtl_writephy(tp, 0x0e, 0x0000);
1565 }
1566 }
1567
1568 rc = 0;
1569 out:
1570 return rc;
1571 }
1572
1573 static int rtl8169_set_speed(struct net_device *dev,
1574 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1575 {
1576 struct rtl8169_private *tp = netdev_priv(dev);
1577 int ret;
1578
1579 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1580 if (ret < 0)
1581 goto out;
1582
1583 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1584 (advertising & ADVERTISED_1000baseT_Full)) {
1585 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1586 }
1587 out:
1588 return ret;
1589 }
1590
1591 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1592 {
1593 struct rtl8169_private *tp = netdev_priv(dev);
1594 int ret;
1595
1596 del_timer_sync(&tp->timer);
1597
1598 rtl_lock_work(tp);
1599 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1600 cmd->duplex, cmd->advertising);
1601 rtl_unlock_work(tp);
1602
1603 return ret;
1604 }
1605
1606 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1607 netdev_features_t features)
1608 {
1609 struct rtl8169_private *tp = netdev_priv(dev);
1610
1611 if (dev->mtu > TD_MSS_MAX)
1612 features &= ~NETIF_F_ALL_TSO;
1613
1614 if (dev->mtu > JUMBO_1K &&
1615 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1616 features &= ~NETIF_F_IP_CSUM;
1617
1618 return features;
1619 }
1620
1621 static void __rtl8169_set_features(struct net_device *dev,
1622 netdev_features_t features)
1623 {
1624 struct rtl8169_private *tp = netdev_priv(dev);
1625 netdev_features_t changed = features ^ dev->features;
1626 void __iomem *ioaddr = tp->mmio_addr;
1627
1628 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1629 return;
1630
1631 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1632 if (features & NETIF_F_RXCSUM)
1633 tp->cp_cmd |= RxChkSum;
1634 else
1635 tp->cp_cmd &= ~RxChkSum;
1636
1637 if (dev->features & NETIF_F_HW_VLAN_RX)
1638 tp->cp_cmd |= RxVlan;
1639 else
1640 tp->cp_cmd &= ~RxVlan;
1641
1642 RTL_W16(CPlusCmd, tp->cp_cmd);
1643 RTL_R16(CPlusCmd);
1644 }
1645 if (changed & NETIF_F_RXALL) {
1646 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1647 if (features & NETIF_F_RXALL)
1648 tmp |= (AcceptErr | AcceptRunt);
1649 RTL_W32(RxConfig, tmp);
1650 }
1651 }
1652
1653 static int rtl8169_set_features(struct net_device *dev,
1654 netdev_features_t features)
1655 {
1656 struct rtl8169_private *tp = netdev_priv(dev);
1657
1658 rtl_lock_work(tp);
1659 __rtl8169_set_features(dev, features);
1660 rtl_unlock_work(tp);
1661
1662 return 0;
1663 }
1664
1665
1666 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1667 struct sk_buff *skb)
1668 {
1669 return (vlan_tx_tag_present(skb)) ?
1670 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1671 }
1672
1673 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1674 {
1675 u32 opts2 = le32_to_cpu(desc->opts2);
1676
1677 if (opts2 & RxVlanTag)
1678 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1679
1680 desc->opts2 = 0;
1681 }
1682
1683 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1684 {
1685 struct rtl8169_private *tp = netdev_priv(dev);
1686 void __iomem *ioaddr = tp->mmio_addr;
1687 u32 status;
1688
1689 cmd->supported =
1690 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1691 cmd->port = PORT_FIBRE;
1692 cmd->transceiver = XCVR_INTERNAL;
1693
1694 status = RTL_R32(TBICSR);
1695 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1696 cmd->autoneg = !!(status & TBINwEnable);
1697
1698 ethtool_cmd_speed_set(cmd, SPEED_1000);
1699 cmd->duplex = DUPLEX_FULL; /* Always set */
1700
1701 return 0;
1702 }
1703
1704 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1705 {
1706 struct rtl8169_private *tp = netdev_priv(dev);
1707
1708 return mii_ethtool_gset(&tp->mii, cmd);
1709 }
1710
1711 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1712 {
1713 struct rtl8169_private *tp = netdev_priv(dev);
1714 int rc;
1715
1716 rtl_lock_work(tp);
1717 rc = tp->get_settings(dev, cmd);
1718 rtl_unlock_work(tp);
1719
1720 return rc;
1721 }
1722
1723 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1724 void *p)
1725 {
1726 struct rtl8169_private *tp = netdev_priv(dev);
1727
1728 if (regs->len > R8169_REGS_SIZE)
1729 regs->len = R8169_REGS_SIZE;
1730
1731 rtl_lock_work(tp);
1732 memcpy_fromio(p, tp->mmio_addr, regs->len);
1733 rtl_unlock_work(tp);
1734 }
1735
1736 static u32 rtl8169_get_msglevel(struct net_device *dev)
1737 {
1738 struct rtl8169_private *tp = netdev_priv(dev);
1739
1740 return tp->msg_enable;
1741 }
1742
1743 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1744 {
1745 struct rtl8169_private *tp = netdev_priv(dev);
1746
1747 tp->msg_enable = value;
1748 }
1749
1750 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1751 "tx_packets",
1752 "rx_packets",
1753 "tx_errors",
1754 "rx_errors",
1755 "rx_missed",
1756 "align_errors",
1757 "tx_single_collisions",
1758 "tx_multi_collisions",
1759 "unicast",
1760 "broadcast",
1761 "multicast",
1762 "tx_aborted",
1763 "tx_underrun",
1764 };
1765
1766 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1767 {
1768 switch (sset) {
1769 case ETH_SS_STATS:
1770 return ARRAY_SIZE(rtl8169_gstrings);
1771 default:
1772 return -EOPNOTSUPP;
1773 }
1774 }
1775
1776 static void rtl8169_update_counters(struct net_device *dev)
1777 {
1778 struct rtl8169_private *tp = netdev_priv(dev);
1779 void __iomem *ioaddr = tp->mmio_addr;
1780 struct device *d = &tp->pci_dev->dev;
1781 struct rtl8169_counters *counters;
1782 dma_addr_t paddr;
1783 u32 cmd;
1784 int wait = 1000;
1785
1786 /*
1787 * Some chips are unable to dump tally counters when the receiver
1788 * is disabled.
1789 */
1790 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1791 return;
1792
1793 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1794 if (!counters)
1795 return;
1796
1797 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1798 cmd = (u64)paddr & DMA_BIT_MASK(32);
1799 RTL_W32(CounterAddrLow, cmd);
1800 RTL_W32(CounterAddrLow, cmd | CounterDump);
1801
1802 while (wait--) {
1803 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1804 memcpy(&tp->counters, counters, sizeof(*counters));
1805 break;
1806 }
1807 udelay(10);
1808 }
1809
1810 RTL_W32(CounterAddrLow, 0);
1811 RTL_W32(CounterAddrHigh, 0);
1812
1813 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1814 }
1815
1816 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1817 struct ethtool_stats *stats, u64 *data)
1818 {
1819 struct rtl8169_private *tp = netdev_priv(dev);
1820
1821 ASSERT_RTNL();
1822
1823 rtl8169_update_counters(dev);
1824
1825 data[0] = le64_to_cpu(tp->counters.tx_packets);
1826 data[1] = le64_to_cpu(tp->counters.rx_packets);
1827 data[2] = le64_to_cpu(tp->counters.tx_errors);
1828 data[3] = le32_to_cpu(tp->counters.rx_errors);
1829 data[4] = le16_to_cpu(tp->counters.rx_missed);
1830 data[5] = le16_to_cpu(tp->counters.align_errors);
1831 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1832 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1833 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1834 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1835 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1836 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1837 data[12] = le16_to_cpu(tp->counters.tx_underun);
1838 }
1839
1840 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1841 {
1842 switch(stringset) {
1843 case ETH_SS_STATS:
1844 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1845 break;
1846 }
1847 }
1848
1849 static const struct ethtool_ops rtl8169_ethtool_ops = {
1850 .get_drvinfo = rtl8169_get_drvinfo,
1851 .get_regs_len = rtl8169_get_regs_len,
1852 .get_link = ethtool_op_get_link,
1853 .get_settings = rtl8169_get_settings,
1854 .set_settings = rtl8169_set_settings,
1855 .get_msglevel = rtl8169_get_msglevel,
1856 .set_msglevel = rtl8169_set_msglevel,
1857 .get_regs = rtl8169_get_regs,
1858 .get_wol = rtl8169_get_wol,
1859 .set_wol = rtl8169_set_wol,
1860 .get_strings = rtl8169_get_strings,
1861 .get_sset_count = rtl8169_get_sset_count,
1862 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1863 .get_ts_info = ethtool_op_get_ts_info,
1864 };
1865
1866 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1867 struct net_device *dev, u8 default_version)
1868 {
1869 void __iomem *ioaddr = tp->mmio_addr;
1870 /*
1871 * The driver currently handles the 8168Bf and the 8168Be identically
1872 * but they can be identified more specifically through the test below
1873 * if needed:
1874 *
1875 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1876 *
1877 * Same thing for the 8101Eb and the 8101Ec:
1878 *
1879 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1880 */
1881 static const struct rtl_mac_info {
1882 u32 mask;
1883 u32 val;
1884 int mac_version;
1885 } mac_info[] = {
1886 /* 8168F family. */
1887 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1888 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1889
1890 /* 8168E family. */
1891 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1892 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1893 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1894 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1895
1896 /* 8168D family. */
1897 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1898 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1899 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1900
1901 /* 8168DP family. */
1902 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1903 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1904 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1905
1906 /* 8168C family. */
1907 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1908 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1909 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1910 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1911 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1912 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1913 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1914 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1915 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1916
1917 /* 8168B family. */
1918 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1919 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1920 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1921 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1922
1923 /* 8101 family. */
1924 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
1925 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1926 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1927 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1928 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1929 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1930 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1931 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1932 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1933 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1934 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1935 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1936 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1937 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1938 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1939 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1940 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1941 /* FIXME: where did these entries come from ? -- FR */
1942 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1943 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1944
1945 /* 8110 family. */
1946 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1947 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1948 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1949 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1950 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1951 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1952
1953 /* Catch-all */
1954 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1955 };
1956 const struct rtl_mac_info *p = mac_info;
1957 u32 reg;
1958
1959 reg = RTL_R32(TxConfig);
1960 while ((reg & p->mask) != p->val)
1961 p++;
1962 tp->mac_version = p->mac_version;
1963
1964 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1965 netif_notice(tp, probe, dev,
1966 "unknown MAC, using family default\n");
1967 tp->mac_version = default_version;
1968 }
1969 }
1970
1971 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1972 {
1973 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1974 }
1975
1976 struct phy_reg {
1977 u16 reg;
1978 u16 val;
1979 };
1980
1981 static void rtl_writephy_batch(struct rtl8169_private *tp,
1982 const struct phy_reg *regs, int len)
1983 {
1984 while (len-- > 0) {
1985 rtl_writephy(tp, regs->reg, regs->val);
1986 regs++;
1987 }
1988 }
1989
1990 #define PHY_READ 0x00000000
1991 #define PHY_DATA_OR 0x10000000
1992 #define PHY_DATA_AND 0x20000000
1993 #define PHY_BJMPN 0x30000000
1994 #define PHY_READ_EFUSE 0x40000000
1995 #define PHY_READ_MAC_BYTE 0x50000000
1996 #define PHY_WRITE_MAC_BYTE 0x60000000
1997 #define PHY_CLEAR_READCOUNT 0x70000000
1998 #define PHY_WRITE 0x80000000
1999 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2000 #define PHY_COMP_EQ_SKIPN 0xa0000000
2001 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2002 #define PHY_WRITE_PREVIOUS 0xc0000000
2003 #define PHY_SKIPN 0xd0000000
2004 #define PHY_DELAY_MS 0xe0000000
2005 #define PHY_WRITE_ERI_WORD 0xf0000000
2006
2007 struct fw_info {
2008 u32 magic;
2009 char version[RTL_VER_SIZE];
2010 __le32 fw_start;
2011 __le32 fw_len;
2012 u8 chksum;
2013 } __packed;
2014
2015 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2016
2017 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2018 {
2019 const struct firmware *fw = rtl_fw->fw;
2020 struct fw_info *fw_info = (struct fw_info *)fw->data;
2021 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2022 char *version = rtl_fw->version;
2023 bool rc = false;
2024
2025 if (fw->size < FW_OPCODE_SIZE)
2026 goto out;
2027
2028 if (!fw_info->magic) {
2029 size_t i, size, start;
2030 u8 checksum = 0;
2031
2032 if (fw->size < sizeof(*fw_info))
2033 goto out;
2034
2035 for (i = 0; i < fw->size; i++)
2036 checksum += fw->data[i];
2037 if (checksum != 0)
2038 goto out;
2039
2040 start = le32_to_cpu(fw_info->fw_start);
2041 if (start > fw->size)
2042 goto out;
2043
2044 size = le32_to_cpu(fw_info->fw_len);
2045 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2046 goto out;
2047
2048 memcpy(version, fw_info->version, RTL_VER_SIZE);
2049
2050 pa->code = (__le32 *)(fw->data + start);
2051 pa->size = size;
2052 } else {
2053 if (fw->size % FW_OPCODE_SIZE)
2054 goto out;
2055
2056 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2057
2058 pa->code = (__le32 *)fw->data;
2059 pa->size = fw->size / FW_OPCODE_SIZE;
2060 }
2061 version[RTL_VER_SIZE - 1] = 0;
2062
2063 rc = true;
2064 out:
2065 return rc;
2066 }
2067
2068 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2069 struct rtl_fw_phy_action *pa)
2070 {
2071 bool rc = false;
2072 size_t index;
2073
2074 for (index = 0; index < pa->size; index++) {
2075 u32 action = le32_to_cpu(pa->code[index]);
2076 u32 regno = (action & 0x0fff0000) >> 16;
2077
2078 switch(action & 0xf0000000) {
2079 case PHY_READ:
2080 case PHY_DATA_OR:
2081 case PHY_DATA_AND:
2082 case PHY_READ_EFUSE:
2083 case PHY_CLEAR_READCOUNT:
2084 case PHY_WRITE:
2085 case PHY_WRITE_PREVIOUS:
2086 case PHY_DELAY_MS:
2087 break;
2088
2089 case PHY_BJMPN:
2090 if (regno > index) {
2091 netif_err(tp, ifup, tp->dev,
2092 "Out of range of firmware\n");
2093 goto out;
2094 }
2095 break;
2096 case PHY_READCOUNT_EQ_SKIP:
2097 if (index + 2 >= pa->size) {
2098 netif_err(tp, ifup, tp->dev,
2099 "Out of range of firmware\n");
2100 goto out;
2101 }
2102 break;
2103 case PHY_COMP_EQ_SKIPN:
2104 case PHY_COMP_NEQ_SKIPN:
2105 case PHY_SKIPN:
2106 if (index + 1 + regno >= pa->size) {
2107 netif_err(tp, ifup, tp->dev,
2108 "Out of range of firmware\n");
2109 goto out;
2110 }
2111 break;
2112
2113 case PHY_READ_MAC_BYTE:
2114 case PHY_WRITE_MAC_BYTE:
2115 case PHY_WRITE_ERI_WORD:
2116 default:
2117 netif_err(tp, ifup, tp->dev,
2118 "Invalid action 0x%08x\n", action);
2119 goto out;
2120 }
2121 }
2122 rc = true;
2123 out:
2124 return rc;
2125 }
2126
2127 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2128 {
2129 struct net_device *dev = tp->dev;
2130 int rc = -EINVAL;
2131
2132 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2133 netif_err(tp, ifup, dev, "invalid firwmare\n");
2134 goto out;
2135 }
2136
2137 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2138 rc = 0;
2139 out:
2140 return rc;
2141 }
2142
2143 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2144 {
2145 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2146 u32 predata, count;
2147 size_t index;
2148
2149 predata = count = 0;
2150
2151 for (index = 0; index < pa->size; ) {
2152 u32 action = le32_to_cpu(pa->code[index]);
2153 u32 data = action & 0x0000ffff;
2154 u32 regno = (action & 0x0fff0000) >> 16;
2155
2156 if (!action)
2157 break;
2158
2159 switch(action & 0xf0000000) {
2160 case PHY_READ:
2161 predata = rtl_readphy(tp, regno);
2162 count++;
2163 index++;
2164 break;
2165 case PHY_DATA_OR:
2166 predata |= data;
2167 index++;
2168 break;
2169 case PHY_DATA_AND:
2170 predata &= data;
2171 index++;
2172 break;
2173 case PHY_BJMPN:
2174 index -= regno;
2175 break;
2176 case PHY_READ_EFUSE:
2177 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2178 index++;
2179 break;
2180 case PHY_CLEAR_READCOUNT:
2181 count = 0;
2182 index++;
2183 break;
2184 case PHY_WRITE:
2185 rtl_writephy(tp, regno, data);
2186 index++;
2187 break;
2188 case PHY_READCOUNT_EQ_SKIP:
2189 index += (count == data) ? 2 : 1;
2190 break;
2191 case PHY_COMP_EQ_SKIPN:
2192 if (predata == data)
2193 index += regno;
2194 index++;
2195 break;
2196 case PHY_COMP_NEQ_SKIPN:
2197 if (predata != data)
2198 index += regno;
2199 index++;
2200 break;
2201 case PHY_WRITE_PREVIOUS:
2202 rtl_writephy(tp, regno, predata);
2203 index++;
2204 break;
2205 case PHY_SKIPN:
2206 index += regno + 1;
2207 break;
2208 case PHY_DELAY_MS:
2209 mdelay(data);
2210 index++;
2211 break;
2212
2213 case PHY_READ_MAC_BYTE:
2214 case PHY_WRITE_MAC_BYTE:
2215 case PHY_WRITE_ERI_WORD:
2216 default:
2217 BUG();
2218 }
2219 }
2220 }
2221
2222 static void rtl_release_firmware(struct rtl8169_private *tp)
2223 {
2224 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2225 release_firmware(tp->rtl_fw->fw);
2226 kfree(tp->rtl_fw);
2227 }
2228 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2229 }
2230
2231 static void rtl_apply_firmware(struct rtl8169_private *tp)
2232 {
2233 struct rtl_fw *rtl_fw = tp->rtl_fw;
2234
2235 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2236 if (!IS_ERR_OR_NULL(rtl_fw))
2237 rtl_phy_write_fw(tp, rtl_fw);
2238 }
2239
2240 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2241 {
2242 if (rtl_readphy(tp, reg) != val)
2243 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2244 else
2245 rtl_apply_firmware(tp);
2246 }
2247
2248 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2249 {
2250 static const struct phy_reg phy_reg_init[] = {
2251 { 0x1f, 0x0001 },
2252 { 0x06, 0x006e },
2253 { 0x08, 0x0708 },
2254 { 0x15, 0x4000 },
2255 { 0x18, 0x65c7 },
2256
2257 { 0x1f, 0x0001 },
2258 { 0x03, 0x00a1 },
2259 { 0x02, 0x0008 },
2260 { 0x01, 0x0120 },
2261 { 0x00, 0x1000 },
2262 { 0x04, 0x0800 },
2263 { 0x04, 0x0000 },
2264
2265 { 0x03, 0xff41 },
2266 { 0x02, 0xdf60 },
2267 { 0x01, 0x0140 },
2268 { 0x00, 0x0077 },
2269 { 0x04, 0x7800 },
2270 { 0x04, 0x7000 },
2271
2272 { 0x03, 0x802f },
2273 { 0x02, 0x4f02 },
2274 { 0x01, 0x0409 },
2275 { 0x00, 0xf0f9 },
2276 { 0x04, 0x9800 },
2277 { 0x04, 0x9000 },
2278
2279 { 0x03, 0xdf01 },
2280 { 0x02, 0xdf20 },
2281 { 0x01, 0xff95 },
2282 { 0x00, 0xba00 },
2283 { 0x04, 0xa800 },
2284 { 0x04, 0xa000 },
2285
2286 { 0x03, 0xff41 },
2287 { 0x02, 0xdf20 },
2288 { 0x01, 0x0140 },
2289 { 0x00, 0x00bb },
2290 { 0x04, 0xb800 },
2291 { 0x04, 0xb000 },
2292
2293 { 0x03, 0xdf41 },
2294 { 0x02, 0xdc60 },
2295 { 0x01, 0x6340 },
2296 { 0x00, 0x007d },
2297 { 0x04, 0xd800 },
2298 { 0x04, 0xd000 },
2299
2300 { 0x03, 0xdf01 },
2301 { 0x02, 0xdf20 },
2302 { 0x01, 0x100a },
2303 { 0x00, 0xa0ff },
2304 { 0x04, 0xf800 },
2305 { 0x04, 0xf000 },
2306
2307 { 0x1f, 0x0000 },
2308 { 0x0b, 0x0000 },
2309 { 0x00, 0x9200 }
2310 };
2311
2312 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2313 }
2314
2315 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2316 {
2317 static const struct phy_reg phy_reg_init[] = {
2318 { 0x1f, 0x0002 },
2319 { 0x01, 0x90d0 },
2320 { 0x1f, 0x0000 }
2321 };
2322
2323 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2324 }
2325
2326 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2327 {
2328 struct pci_dev *pdev = tp->pci_dev;
2329
2330 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2331 (pdev->subsystem_device != 0xe000))
2332 return;
2333
2334 rtl_writephy(tp, 0x1f, 0x0001);
2335 rtl_writephy(tp, 0x10, 0xf01b);
2336 rtl_writephy(tp, 0x1f, 0x0000);
2337 }
2338
2339 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2340 {
2341 static const struct phy_reg phy_reg_init[] = {
2342 { 0x1f, 0x0001 },
2343 { 0x04, 0x0000 },
2344 { 0x03, 0x00a1 },
2345 { 0x02, 0x0008 },
2346 { 0x01, 0x0120 },
2347 { 0x00, 0x1000 },
2348 { 0x04, 0x0800 },
2349 { 0x04, 0x9000 },
2350 { 0x03, 0x802f },
2351 { 0x02, 0x4f02 },
2352 { 0x01, 0x0409 },
2353 { 0x00, 0xf099 },
2354 { 0x04, 0x9800 },
2355 { 0x04, 0xa000 },
2356 { 0x03, 0xdf01 },
2357 { 0x02, 0xdf20 },
2358 { 0x01, 0xff95 },
2359 { 0x00, 0xba00 },
2360 { 0x04, 0xa800 },
2361 { 0x04, 0xf000 },
2362 { 0x03, 0xdf01 },
2363 { 0x02, 0xdf20 },
2364 { 0x01, 0x101a },
2365 { 0x00, 0xa0ff },
2366 { 0x04, 0xf800 },
2367 { 0x04, 0x0000 },
2368 { 0x1f, 0x0000 },
2369
2370 { 0x1f, 0x0001 },
2371 { 0x10, 0xf41b },
2372 { 0x14, 0xfb54 },
2373 { 0x18, 0xf5c7 },
2374 { 0x1f, 0x0000 },
2375
2376 { 0x1f, 0x0001 },
2377 { 0x17, 0x0cc0 },
2378 { 0x1f, 0x0000 }
2379 };
2380
2381 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2382
2383 rtl8169scd_hw_phy_config_quirk(tp);
2384 }
2385
2386 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2387 {
2388 static const struct phy_reg phy_reg_init[] = {
2389 { 0x1f, 0x0001 },
2390 { 0x04, 0x0000 },
2391 { 0x03, 0x00a1 },
2392 { 0x02, 0x0008 },
2393 { 0x01, 0x0120 },
2394 { 0x00, 0x1000 },
2395 { 0x04, 0x0800 },
2396 { 0x04, 0x9000 },
2397 { 0x03, 0x802f },
2398 { 0x02, 0x4f02 },
2399 { 0x01, 0x0409 },
2400 { 0x00, 0xf099 },
2401 { 0x04, 0x9800 },
2402 { 0x04, 0xa000 },
2403 { 0x03, 0xdf01 },
2404 { 0x02, 0xdf20 },
2405 { 0x01, 0xff95 },
2406 { 0x00, 0xba00 },
2407 { 0x04, 0xa800 },
2408 { 0x04, 0xf000 },
2409 { 0x03, 0xdf01 },
2410 { 0x02, 0xdf20 },
2411 { 0x01, 0x101a },
2412 { 0x00, 0xa0ff },
2413 { 0x04, 0xf800 },
2414 { 0x04, 0x0000 },
2415 { 0x1f, 0x0000 },
2416
2417 { 0x1f, 0x0001 },
2418 { 0x0b, 0x8480 },
2419 { 0x1f, 0x0000 },
2420
2421 { 0x1f, 0x0001 },
2422 { 0x18, 0x67c7 },
2423 { 0x04, 0x2000 },
2424 { 0x03, 0x002f },
2425 { 0x02, 0x4360 },
2426 { 0x01, 0x0109 },
2427 { 0x00, 0x3022 },
2428 { 0x04, 0x2800 },
2429 { 0x1f, 0x0000 },
2430
2431 { 0x1f, 0x0001 },
2432 { 0x17, 0x0cc0 },
2433 { 0x1f, 0x0000 }
2434 };
2435
2436 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2437 }
2438
2439 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2440 {
2441 static const struct phy_reg phy_reg_init[] = {
2442 { 0x10, 0xf41b },
2443 { 0x1f, 0x0000 }
2444 };
2445
2446 rtl_writephy(tp, 0x1f, 0x0001);
2447 rtl_patchphy(tp, 0x16, 1 << 0);
2448
2449 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2450 }
2451
2452 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2453 {
2454 static const struct phy_reg phy_reg_init[] = {
2455 { 0x1f, 0x0001 },
2456 { 0x10, 0xf41b },
2457 { 0x1f, 0x0000 }
2458 };
2459
2460 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2461 }
2462
2463 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2464 {
2465 static const struct phy_reg phy_reg_init[] = {
2466 { 0x1f, 0x0000 },
2467 { 0x1d, 0x0f00 },
2468 { 0x1f, 0x0002 },
2469 { 0x0c, 0x1ec8 },
2470 { 0x1f, 0x0000 }
2471 };
2472
2473 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2474 }
2475
2476 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2477 {
2478 static const struct phy_reg phy_reg_init[] = {
2479 { 0x1f, 0x0001 },
2480 { 0x1d, 0x3d98 },
2481 { 0x1f, 0x0000 }
2482 };
2483
2484 rtl_writephy(tp, 0x1f, 0x0000);
2485 rtl_patchphy(tp, 0x14, 1 << 5);
2486 rtl_patchphy(tp, 0x0d, 1 << 5);
2487
2488 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2489 }
2490
2491 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2492 {
2493 static const struct phy_reg phy_reg_init[] = {
2494 { 0x1f, 0x0001 },
2495 { 0x12, 0x2300 },
2496 { 0x1f, 0x0002 },
2497 { 0x00, 0x88d4 },
2498 { 0x01, 0x82b1 },
2499 { 0x03, 0x7002 },
2500 { 0x08, 0x9e30 },
2501 { 0x09, 0x01f0 },
2502 { 0x0a, 0x5500 },
2503 { 0x0c, 0x00c8 },
2504 { 0x1f, 0x0003 },
2505 { 0x12, 0xc096 },
2506 { 0x16, 0x000a },
2507 { 0x1f, 0x0000 },
2508 { 0x1f, 0x0000 },
2509 { 0x09, 0x2000 },
2510 { 0x09, 0x0000 }
2511 };
2512
2513 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2514
2515 rtl_patchphy(tp, 0x14, 1 << 5);
2516 rtl_patchphy(tp, 0x0d, 1 << 5);
2517 rtl_writephy(tp, 0x1f, 0x0000);
2518 }
2519
2520 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2521 {
2522 static const struct phy_reg phy_reg_init[] = {
2523 { 0x1f, 0x0001 },
2524 { 0x12, 0x2300 },
2525 { 0x03, 0x802f },
2526 { 0x02, 0x4f02 },
2527 { 0x01, 0x0409 },
2528 { 0x00, 0xf099 },
2529 { 0x04, 0x9800 },
2530 { 0x04, 0x9000 },
2531 { 0x1d, 0x3d98 },
2532 { 0x1f, 0x0002 },
2533 { 0x0c, 0x7eb8 },
2534 { 0x06, 0x0761 },
2535 { 0x1f, 0x0003 },
2536 { 0x16, 0x0f0a },
2537 { 0x1f, 0x0000 }
2538 };
2539
2540 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2541
2542 rtl_patchphy(tp, 0x16, 1 << 0);
2543 rtl_patchphy(tp, 0x14, 1 << 5);
2544 rtl_patchphy(tp, 0x0d, 1 << 5);
2545 rtl_writephy(tp, 0x1f, 0x0000);
2546 }
2547
2548 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2549 {
2550 static const struct phy_reg phy_reg_init[] = {
2551 { 0x1f, 0x0001 },
2552 { 0x12, 0x2300 },
2553 { 0x1d, 0x3d98 },
2554 { 0x1f, 0x0002 },
2555 { 0x0c, 0x7eb8 },
2556 { 0x06, 0x5461 },
2557 { 0x1f, 0x0003 },
2558 { 0x16, 0x0f0a },
2559 { 0x1f, 0x0000 }
2560 };
2561
2562 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2563
2564 rtl_patchphy(tp, 0x16, 1 << 0);
2565 rtl_patchphy(tp, 0x14, 1 << 5);
2566 rtl_patchphy(tp, 0x0d, 1 << 5);
2567 rtl_writephy(tp, 0x1f, 0x0000);
2568 }
2569
2570 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2571 {
2572 rtl8168c_3_hw_phy_config(tp);
2573 }
2574
2575 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2576 {
2577 static const struct phy_reg phy_reg_init_0[] = {
2578 /* Channel Estimation */
2579 { 0x1f, 0x0001 },
2580 { 0x06, 0x4064 },
2581 { 0x07, 0x2863 },
2582 { 0x08, 0x059c },
2583 { 0x09, 0x26b4 },
2584 { 0x0a, 0x6a19 },
2585 { 0x0b, 0xdcc8 },
2586 { 0x10, 0xf06d },
2587 { 0x14, 0x7f68 },
2588 { 0x18, 0x7fd9 },
2589 { 0x1c, 0xf0ff },
2590 { 0x1d, 0x3d9c },
2591 { 0x1f, 0x0003 },
2592 { 0x12, 0xf49f },
2593 { 0x13, 0x070b },
2594 { 0x1a, 0x05ad },
2595 { 0x14, 0x94c0 },
2596
2597 /*
2598 * Tx Error Issue
2599 * Enhance line driver power
2600 */
2601 { 0x1f, 0x0002 },
2602 { 0x06, 0x5561 },
2603 { 0x1f, 0x0005 },
2604 { 0x05, 0x8332 },
2605 { 0x06, 0x5561 },
2606
2607 /*
2608 * Can not link to 1Gbps with bad cable
2609 * Decrease SNR threshold form 21.07dB to 19.04dB
2610 */
2611 { 0x1f, 0x0001 },
2612 { 0x17, 0x0cc0 },
2613
2614 { 0x1f, 0x0000 },
2615 { 0x0d, 0xf880 }
2616 };
2617 void __iomem *ioaddr = tp->mmio_addr;
2618
2619 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2620
2621 /*
2622 * Rx Error Issue
2623 * Fine Tune Switching regulator parameter
2624 */
2625 rtl_writephy(tp, 0x1f, 0x0002);
2626 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2627 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2628
2629 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2630 static const struct phy_reg phy_reg_init[] = {
2631 { 0x1f, 0x0002 },
2632 { 0x05, 0x669a },
2633 { 0x1f, 0x0005 },
2634 { 0x05, 0x8330 },
2635 { 0x06, 0x669a },
2636 { 0x1f, 0x0002 }
2637 };
2638 int val;
2639
2640 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2641
2642 val = rtl_readphy(tp, 0x0d);
2643
2644 if ((val & 0x00ff) != 0x006c) {
2645 static const u32 set[] = {
2646 0x0065, 0x0066, 0x0067, 0x0068,
2647 0x0069, 0x006a, 0x006b, 0x006c
2648 };
2649 int i;
2650
2651 rtl_writephy(tp, 0x1f, 0x0002);
2652
2653 val &= 0xff00;
2654 for (i = 0; i < ARRAY_SIZE(set); i++)
2655 rtl_writephy(tp, 0x0d, val | set[i]);
2656 }
2657 } else {
2658 static const struct phy_reg phy_reg_init[] = {
2659 { 0x1f, 0x0002 },
2660 { 0x05, 0x6662 },
2661 { 0x1f, 0x0005 },
2662 { 0x05, 0x8330 },
2663 { 0x06, 0x6662 }
2664 };
2665
2666 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2667 }
2668
2669 /* RSET couple improve */
2670 rtl_writephy(tp, 0x1f, 0x0002);
2671 rtl_patchphy(tp, 0x0d, 0x0300);
2672 rtl_patchphy(tp, 0x0f, 0x0010);
2673
2674 /* Fine tune PLL performance */
2675 rtl_writephy(tp, 0x1f, 0x0002);
2676 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2677 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2678
2679 rtl_writephy(tp, 0x1f, 0x0005);
2680 rtl_writephy(tp, 0x05, 0x001b);
2681
2682 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2683
2684 rtl_writephy(tp, 0x1f, 0x0000);
2685 }
2686
2687 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2688 {
2689 static const struct phy_reg phy_reg_init_0[] = {
2690 /* Channel Estimation */
2691 { 0x1f, 0x0001 },
2692 { 0x06, 0x4064 },
2693 { 0x07, 0x2863 },
2694 { 0x08, 0x059c },
2695 { 0x09, 0x26b4 },
2696 { 0x0a, 0x6a19 },
2697 { 0x0b, 0xdcc8 },
2698 { 0x10, 0xf06d },
2699 { 0x14, 0x7f68 },
2700 { 0x18, 0x7fd9 },
2701 { 0x1c, 0xf0ff },
2702 { 0x1d, 0x3d9c },
2703 { 0x1f, 0x0003 },
2704 { 0x12, 0xf49f },
2705 { 0x13, 0x070b },
2706 { 0x1a, 0x05ad },
2707 { 0x14, 0x94c0 },
2708
2709 /*
2710 * Tx Error Issue
2711 * Enhance line driver power
2712 */
2713 { 0x1f, 0x0002 },
2714 { 0x06, 0x5561 },
2715 { 0x1f, 0x0005 },
2716 { 0x05, 0x8332 },
2717 { 0x06, 0x5561 },
2718
2719 /*
2720 * Can not link to 1Gbps with bad cable
2721 * Decrease SNR threshold form 21.07dB to 19.04dB
2722 */
2723 { 0x1f, 0x0001 },
2724 { 0x17, 0x0cc0 },
2725
2726 { 0x1f, 0x0000 },
2727 { 0x0d, 0xf880 }
2728 };
2729 void __iomem *ioaddr = tp->mmio_addr;
2730
2731 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2732
2733 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2734 static const struct phy_reg phy_reg_init[] = {
2735 { 0x1f, 0x0002 },
2736 { 0x05, 0x669a },
2737 { 0x1f, 0x0005 },
2738 { 0x05, 0x8330 },
2739 { 0x06, 0x669a },
2740
2741 { 0x1f, 0x0002 }
2742 };
2743 int val;
2744
2745 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2746
2747 val = rtl_readphy(tp, 0x0d);
2748 if ((val & 0x00ff) != 0x006c) {
2749 static const u32 set[] = {
2750 0x0065, 0x0066, 0x0067, 0x0068,
2751 0x0069, 0x006a, 0x006b, 0x006c
2752 };
2753 int i;
2754
2755 rtl_writephy(tp, 0x1f, 0x0002);
2756
2757 val &= 0xff00;
2758 for (i = 0; i < ARRAY_SIZE(set); i++)
2759 rtl_writephy(tp, 0x0d, val | set[i]);
2760 }
2761 } else {
2762 static const struct phy_reg phy_reg_init[] = {
2763 { 0x1f, 0x0002 },
2764 { 0x05, 0x2642 },
2765 { 0x1f, 0x0005 },
2766 { 0x05, 0x8330 },
2767 { 0x06, 0x2642 }
2768 };
2769
2770 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2771 }
2772
2773 /* Fine tune PLL performance */
2774 rtl_writephy(tp, 0x1f, 0x0002);
2775 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2776 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2777
2778 /* Switching regulator Slew rate */
2779 rtl_writephy(tp, 0x1f, 0x0002);
2780 rtl_patchphy(tp, 0x0f, 0x0017);
2781
2782 rtl_writephy(tp, 0x1f, 0x0005);
2783 rtl_writephy(tp, 0x05, 0x001b);
2784
2785 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2786
2787 rtl_writephy(tp, 0x1f, 0x0000);
2788 }
2789
2790 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2791 {
2792 static const struct phy_reg phy_reg_init[] = {
2793 { 0x1f, 0x0002 },
2794 { 0x10, 0x0008 },
2795 { 0x0d, 0x006c },
2796
2797 { 0x1f, 0x0000 },
2798 { 0x0d, 0xf880 },
2799
2800 { 0x1f, 0x0001 },
2801 { 0x17, 0x0cc0 },
2802
2803 { 0x1f, 0x0001 },
2804 { 0x0b, 0xa4d8 },
2805 { 0x09, 0x281c },
2806 { 0x07, 0x2883 },
2807 { 0x0a, 0x6b35 },
2808 { 0x1d, 0x3da4 },
2809 { 0x1c, 0xeffd },
2810 { 0x14, 0x7f52 },
2811 { 0x18, 0x7fc6 },
2812 { 0x08, 0x0601 },
2813 { 0x06, 0x4063 },
2814 { 0x10, 0xf074 },
2815 { 0x1f, 0x0003 },
2816 { 0x13, 0x0789 },
2817 { 0x12, 0xf4bd },
2818 { 0x1a, 0x04fd },
2819 { 0x14, 0x84b0 },
2820 { 0x1f, 0x0000 },
2821 { 0x00, 0x9200 },
2822
2823 { 0x1f, 0x0005 },
2824 { 0x01, 0x0340 },
2825 { 0x1f, 0x0001 },
2826 { 0x04, 0x4000 },
2827 { 0x03, 0x1d21 },
2828 { 0x02, 0x0c32 },
2829 { 0x01, 0x0200 },
2830 { 0x00, 0x5554 },
2831 { 0x04, 0x4800 },
2832 { 0x04, 0x4000 },
2833 { 0x04, 0xf000 },
2834 { 0x03, 0xdf01 },
2835 { 0x02, 0xdf20 },
2836 { 0x01, 0x101a },
2837 { 0x00, 0xa0ff },
2838 { 0x04, 0xf800 },
2839 { 0x04, 0xf000 },
2840 { 0x1f, 0x0000 },
2841
2842 { 0x1f, 0x0007 },
2843 { 0x1e, 0x0023 },
2844 { 0x16, 0x0000 },
2845 { 0x1f, 0x0000 }
2846 };
2847
2848 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2849 }
2850
2851 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2852 {
2853 static const struct phy_reg phy_reg_init[] = {
2854 { 0x1f, 0x0001 },
2855 { 0x17, 0x0cc0 },
2856
2857 { 0x1f, 0x0007 },
2858 { 0x1e, 0x002d },
2859 { 0x18, 0x0040 },
2860 { 0x1f, 0x0000 }
2861 };
2862
2863 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2864 rtl_patchphy(tp, 0x0d, 1 << 5);
2865 }
2866
2867 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2868 {
2869 static const struct phy_reg phy_reg_init[] = {
2870 /* Enable Delay cap */
2871 { 0x1f, 0x0005 },
2872 { 0x05, 0x8b80 },
2873 { 0x06, 0xc896 },
2874 { 0x1f, 0x0000 },
2875
2876 /* Channel estimation fine tune */
2877 { 0x1f, 0x0001 },
2878 { 0x0b, 0x6c20 },
2879 { 0x07, 0x2872 },
2880 { 0x1c, 0xefff },
2881 { 0x1f, 0x0003 },
2882 { 0x14, 0x6420 },
2883 { 0x1f, 0x0000 },
2884
2885 /* Update PFM & 10M TX idle timer */
2886 { 0x1f, 0x0007 },
2887 { 0x1e, 0x002f },
2888 { 0x15, 0x1919 },
2889 { 0x1f, 0x0000 },
2890
2891 { 0x1f, 0x0007 },
2892 { 0x1e, 0x00ac },
2893 { 0x18, 0x0006 },
2894 { 0x1f, 0x0000 }
2895 };
2896
2897 rtl_apply_firmware(tp);
2898
2899 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2900
2901 /* DCO enable for 10M IDLE Power */
2902 rtl_writephy(tp, 0x1f, 0x0007);
2903 rtl_writephy(tp, 0x1e, 0x0023);
2904 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2905 rtl_writephy(tp, 0x1f, 0x0000);
2906
2907 /* For impedance matching */
2908 rtl_writephy(tp, 0x1f, 0x0002);
2909 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2910 rtl_writephy(tp, 0x1f, 0x0000);
2911
2912 /* PHY auto speed down */
2913 rtl_writephy(tp, 0x1f, 0x0007);
2914 rtl_writephy(tp, 0x1e, 0x002d);
2915 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2916 rtl_writephy(tp, 0x1f, 0x0000);
2917 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2918
2919 rtl_writephy(tp, 0x1f, 0x0005);
2920 rtl_writephy(tp, 0x05, 0x8b86);
2921 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2922 rtl_writephy(tp, 0x1f, 0x0000);
2923
2924 rtl_writephy(tp, 0x1f, 0x0005);
2925 rtl_writephy(tp, 0x05, 0x8b85);
2926 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2927 rtl_writephy(tp, 0x1f, 0x0007);
2928 rtl_writephy(tp, 0x1e, 0x0020);
2929 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2930 rtl_writephy(tp, 0x1f, 0x0006);
2931 rtl_writephy(tp, 0x00, 0x5a00);
2932 rtl_writephy(tp, 0x1f, 0x0000);
2933 rtl_writephy(tp, 0x0d, 0x0007);
2934 rtl_writephy(tp, 0x0e, 0x003c);
2935 rtl_writephy(tp, 0x0d, 0x4007);
2936 rtl_writephy(tp, 0x0e, 0x0000);
2937 rtl_writephy(tp, 0x0d, 0x0000);
2938 }
2939
2940 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2941 {
2942 static const struct phy_reg phy_reg_init[] = {
2943 /* Enable Delay cap */
2944 { 0x1f, 0x0004 },
2945 { 0x1f, 0x0007 },
2946 { 0x1e, 0x00ac },
2947 { 0x18, 0x0006 },
2948 { 0x1f, 0x0002 },
2949 { 0x1f, 0x0000 },
2950 { 0x1f, 0x0000 },
2951
2952 /* Channel estimation fine tune */
2953 { 0x1f, 0x0003 },
2954 { 0x09, 0xa20f },
2955 { 0x1f, 0x0000 },
2956 { 0x1f, 0x0000 },
2957
2958 /* Green Setting */
2959 { 0x1f, 0x0005 },
2960 { 0x05, 0x8b5b },
2961 { 0x06, 0x9222 },
2962 { 0x05, 0x8b6d },
2963 { 0x06, 0x8000 },
2964 { 0x05, 0x8b76 },
2965 { 0x06, 0x8000 },
2966 { 0x1f, 0x0000 }
2967 };
2968
2969 rtl_apply_firmware(tp);
2970
2971 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2972
2973 /* For 4-corner performance improve */
2974 rtl_writephy(tp, 0x1f, 0x0005);
2975 rtl_writephy(tp, 0x05, 0x8b80);
2976 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2977 rtl_writephy(tp, 0x1f, 0x0000);
2978
2979 /* PHY auto speed down */
2980 rtl_writephy(tp, 0x1f, 0x0004);
2981 rtl_writephy(tp, 0x1f, 0x0007);
2982 rtl_writephy(tp, 0x1e, 0x002d);
2983 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2984 rtl_writephy(tp, 0x1f, 0x0002);
2985 rtl_writephy(tp, 0x1f, 0x0000);
2986 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2987
2988 /* improve 10M EEE waveform */
2989 rtl_writephy(tp, 0x1f, 0x0005);
2990 rtl_writephy(tp, 0x05, 0x8b86);
2991 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2992 rtl_writephy(tp, 0x1f, 0x0000);
2993
2994 /* Improve 2-pair detection performance */
2995 rtl_writephy(tp, 0x1f, 0x0005);
2996 rtl_writephy(tp, 0x05, 0x8b85);
2997 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2998 rtl_writephy(tp, 0x1f, 0x0000);
2999
3000 /* EEE setting */
3001 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3002 ERIAR_EXGMAC);
3003 rtl_writephy(tp, 0x1f, 0x0005);
3004 rtl_writephy(tp, 0x05, 0x8b85);
3005 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3006 rtl_writephy(tp, 0x1f, 0x0004);
3007 rtl_writephy(tp, 0x1f, 0x0007);
3008 rtl_writephy(tp, 0x1e, 0x0020);
3009 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3010 rtl_writephy(tp, 0x1f, 0x0002);
3011 rtl_writephy(tp, 0x1f, 0x0000);
3012 rtl_writephy(tp, 0x0d, 0x0007);
3013 rtl_writephy(tp, 0x0e, 0x003c);
3014 rtl_writephy(tp, 0x0d, 0x4007);
3015 rtl_writephy(tp, 0x0e, 0x0000);
3016 rtl_writephy(tp, 0x0d, 0x0000);
3017
3018 /* Green feature */
3019 rtl_writephy(tp, 0x1f, 0x0003);
3020 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3021 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3022 rtl_writephy(tp, 0x1f, 0x0000);
3023 }
3024
3025 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3026 {
3027 /* For 4-corner performance improve */
3028 rtl_writephy(tp, 0x1f, 0x0005);
3029 rtl_writephy(tp, 0x05, 0x8b80);
3030 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3031 rtl_writephy(tp, 0x1f, 0x0000);
3032
3033 /* PHY auto speed down */
3034 rtl_writephy(tp, 0x1f, 0x0007);
3035 rtl_writephy(tp, 0x1e, 0x002d);
3036 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3037 rtl_writephy(tp, 0x1f, 0x0000);
3038 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3039
3040 /* Improve 10M EEE waveform */
3041 rtl_writephy(tp, 0x1f, 0x0005);
3042 rtl_writephy(tp, 0x05, 0x8b86);
3043 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3044 rtl_writephy(tp, 0x1f, 0x0000);
3045 }
3046
3047 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3048 {
3049 static const struct phy_reg phy_reg_init[] = {
3050 /* Channel estimation fine tune */
3051 { 0x1f, 0x0003 },
3052 { 0x09, 0xa20f },
3053 { 0x1f, 0x0000 },
3054
3055 /* Modify green table for giga & fnet */
3056 { 0x1f, 0x0005 },
3057 { 0x05, 0x8b55 },
3058 { 0x06, 0x0000 },
3059 { 0x05, 0x8b5e },
3060 { 0x06, 0x0000 },
3061 { 0x05, 0x8b67 },
3062 { 0x06, 0x0000 },
3063 { 0x05, 0x8b70 },
3064 { 0x06, 0x0000 },
3065 { 0x1f, 0x0000 },
3066 { 0x1f, 0x0007 },
3067 { 0x1e, 0x0078 },
3068 { 0x17, 0x0000 },
3069 { 0x19, 0x00fb },
3070 { 0x1f, 0x0000 },
3071
3072 /* Modify green table for 10M */
3073 { 0x1f, 0x0005 },
3074 { 0x05, 0x8b79 },
3075 { 0x06, 0xaa00 },
3076 { 0x1f, 0x0000 },
3077
3078 /* Disable hiimpedance detection (RTCT) */
3079 { 0x1f, 0x0003 },
3080 { 0x01, 0x328a },
3081 { 0x1f, 0x0000 }
3082 };
3083
3084 rtl_apply_firmware(tp);
3085
3086 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3087
3088 rtl8168f_hw_phy_config(tp);
3089
3090 /* Improve 2-pair detection performance */
3091 rtl_writephy(tp, 0x1f, 0x0005);
3092 rtl_writephy(tp, 0x05, 0x8b85);
3093 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3094 rtl_writephy(tp, 0x1f, 0x0000);
3095 }
3096
3097 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3098 {
3099 rtl_apply_firmware(tp);
3100
3101 rtl8168f_hw_phy_config(tp);
3102 }
3103
3104 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3105 {
3106 static const struct phy_reg phy_reg_init[] = {
3107 { 0x1f, 0x0003 },
3108 { 0x08, 0x441d },
3109 { 0x01, 0x9100 },
3110 { 0x1f, 0x0000 }
3111 };
3112
3113 rtl_writephy(tp, 0x1f, 0x0000);
3114 rtl_patchphy(tp, 0x11, 1 << 12);
3115 rtl_patchphy(tp, 0x19, 1 << 13);
3116 rtl_patchphy(tp, 0x10, 1 << 15);
3117
3118 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3119 }
3120
3121 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3122 {
3123 static const struct phy_reg phy_reg_init[] = {
3124 { 0x1f, 0x0005 },
3125 { 0x1a, 0x0000 },
3126 { 0x1f, 0x0000 },
3127
3128 { 0x1f, 0x0004 },
3129 { 0x1c, 0x0000 },
3130 { 0x1f, 0x0000 },
3131
3132 { 0x1f, 0x0001 },
3133 { 0x15, 0x7701 },
3134 { 0x1f, 0x0000 }
3135 };
3136
3137 /* Disable ALDPS before ram code */
3138 rtl_writephy(tp, 0x1f, 0x0000);
3139 rtl_writephy(tp, 0x18, 0x0310);
3140 msleep(100);
3141
3142 rtl_apply_firmware(tp);
3143
3144 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3145 }
3146
3147 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3148 {
3149 void __iomem *ioaddr = tp->mmio_addr;
3150
3151 /* Disable ALDPS before setting firmware */
3152 rtl_writephy(tp, 0x1f, 0x0000);
3153 rtl_writephy(tp, 0x18, 0x0310);
3154 msleep(20);
3155
3156 rtl_apply_firmware(tp);
3157
3158 /* EEE setting */
3159 rtl_eri_write(ioaddr, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3160 rtl_writephy(tp, 0x1f, 0x0004);
3161 rtl_writephy(tp, 0x10, 0x401f);
3162 rtl_writephy(tp, 0x19, 0x7030);
3163 rtl_writephy(tp, 0x1f, 0x0000);
3164 }
3165
3166 static void rtl_hw_phy_config(struct net_device *dev)
3167 {
3168 struct rtl8169_private *tp = netdev_priv(dev);
3169
3170 rtl8169_print_mac_version(tp);
3171
3172 switch (tp->mac_version) {
3173 case RTL_GIGA_MAC_VER_01:
3174 break;
3175 case RTL_GIGA_MAC_VER_02:
3176 case RTL_GIGA_MAC_VER_03:
3177 rtl8169s_hw_phy_config(tp);
3178 break;
3179 case RTL_GIGA_MAC_VER_04:
3180 rtl8169sb_hw_phy_config(tp);
3181 break;
3182 case RTL_GIGA_MAC_VER_05:
3183 rtl8169scd_hw_phy_config(tp);
3184 break;
3185 case RTL_GIGA_MAC_VER_06:
3186 rtl8169sce_hw_phy_config(tp);
3187 break;
3188 case RTL_GIGA_MAC_VER_07:
3189 case RTL_GIGA_MAC_VER_08:
3190 case RTL_GIGA_MAC_VER_09:
3191 rtl8102e_hw_phy_config(tp);
3192 break;
3193 case RTL_GIGA_MAC_VER_11:
3194 rtl8168bb_hw_phy_config(tp);
3195 break;
3196 case RTL_GIGA_MAC_VER_12:
3197 rtl8168bef_hw_phy_config(tp);
3198 break;
3199 case RTL_GIGA_MAC_VER_17:
3200 rtl8168bef_hw_phy_config(tp);
3201 break;
3202 case RTL_GIGA_MAC_VER_18:
3203 rtl8168cp_1_hw_phy_config(tp);
3204 break;
3205 case RTL_GIGA_MAC_VER_19:
3206 rtl8168c_1_hw_phy_config(tp);
3207 break;
3208 case RTL_GIGA_MAC_VER_20:
3209 rtl8168c_2_hw_phy_config(tp);
3210 break;
3211 case RTL_GIGA_MAC_VER_21:
3212 rtl8168c_3_hw_phy_config(tp);
3213 break;
3214 case RTL_GIGA_MAC_VER_22:
3215 rtl8168c_4_hw_phy_config(tp);
3216 break;
3217 case RTL_GIGA_MAC_VER_23:
3218 case RTL_GIGA_MAC_VER_24:
3219 rtl8168cp_2_hw_phy_config(tp);
3220 break;
3221 case RTL_GIGA_MAC_VER_25:
3222 rtl8168d_1_hw_phy_config(tp);
3223 break;
3224 case RTL_GIGA_MAC_VER_26:
3225 rtl8168d_2_hw_phy_config(tp);
3226 break;
3227 case RTL_GIGA_MAC_VER_27:
3228 rtl8168d_3_hw_phy_config(tp);
3229 break;
3230 case RTL_GIGA_MAC_VER_28:
3231 rtl8168d_4_hw_phy_config(tp);
3232 break;
3233 case RTL_GIGA_MAC_VER_29:
3234 case RTL_GIGA_MAC_VER_30:
3235 rtl8105e_hw_phy_config(tp);
3236 break;
3237 case RTL_GIGA_MAC_VER_31:
3238 /* None. */
3239 break;
3240 case RTL_GIGA_MAC_VER_32:
3241 case RTL_GIGA_MAC_VER_33:
3242 rtl8168e_1_hw_phy_config(tp);
3243 break;
3244 case RTL_GIGA_MAC_VER_34:
3245 rtl8168e_2_hw_phy_config(tp);
3246 break;
3247 case RTL_GIGA_MAC_VER_35:
3248 rtl8168f_1_hw_phy_config(tp);
3249 break;
3250 case RTL_GIGA_MAC_VER_36:
3251 rtl8168f_2_hw_phy_config(tp);
3252 break;
3253
3254 case RTL_GIGA_MAC_VER_37:
3255 rtl8402_hw_phy_config(tp);
3256 break;
3257
3258 default:
3259 break;
3260 }
3261 }
3262
3263 static void rtl_phy_work(struct rtl8169_private *tp)
3264 {
3265 struct timer_list *timer = &tp->timer;
3266 void __iomem *ioaddr = tp->mmio_addr;
3267 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3268
3269 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3270
3271 if (tp->phy_reset_pending(tp)) {
3272 /*
3273 * A busy loop could burn quite a few cycles on nowadays CPU.
3274 * Let's delay the execution of the timer for a few ticks.
3275 */
3276 timeout = HZ/10;
3277 goto out_mod_timer;
3278 }
3279
3280 if (tp->link_ok(ioaddr))
3281 return;
3282
3283 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3284
3285 tp->phy_reset_enable(tp);
3286
3287 out_mod_timer:
3288 mod_timer(timer, jiffies + timeout);
3289 }
3290
3291 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3292 {
3293 if (!test_and_set_bit(flag, tp->wk.flags))
3294 schedule_work(&tp->wk.work);
3295 }
3296
3297 static void rtl8169_phy_timer(unsigned long __opaque)
3298 {
3299 struct net_device *dev = (struct net_device *)__opaque;
3300 struct rtl8169_private *tp = netdev_priv(dev);
3301
3302 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3303 }
3304
3305 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3306 void __iomem *ioaddr)
3307 {
3308 iounmap(ioaddr);
3309 pci_release_regions(pdev);
3310 pci_clear_mwi(pdev);
3311 pci_disable_device(pdev);
3312 free_netdev(dev);
3313 }
3314
3315 static void rtl8169_phy_reset(struct net_device *dev,
3316 struct rtl8169_private *tp)
3317 {
3318 unsigned int i;
3319
3320 tp->phy_reset_enable(tp);
3321 for (i = 0; i < 100; i++) {
3322 if (!tp->phy_reset_pending(tp))
3323 return;
3324 msleep(1);
3325 }
3326 netif_err(tp, link, dev, "PHY reset failed\n");
3327 }
3328
3329 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3330 {
3331 void __iomem *ioaddr = tp->mmio_addr;
3332
3333 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3334 (RTL_R8(PHYstatus) & TBI_Enable);
3335 }
3336
3337 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3338 {
3339 void __iomem *ioaddr = tp->mmio_addr;
3340
3341 rtl_hw_phy_config(dev);
3342
3343 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3344 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3345 RTL_W8(0x82, 0x01);
3346 }
3347
3348 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3349
3350 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3351 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3352
3353 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3354 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3355 RTL_W8(0x82, 0x01);
3356 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3357 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3358 }
3359
3360 rtl8169_phy_reset(dev, tp);
3361
3362 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3363 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3364 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3365 (tp->mii.supports_gmii ?
3366 ADVERTISED_1000baseT_Half |
3367 ADVERTISED_1000baseT_Full : 0));
3368
3369 if (rtl_tbi_enabled(tp))
3370 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3371 }
3372
3373 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3374 {
3375 void __iomem *ioaddr = tp->mmio_addr;
3376 u32 high;
3377 u32 low;
3378
3379 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3380 high = addr[4] | (addr[5] << 8);
3381
3382 rtl_lock_work(tp);
3383
3384 RTL_W8(Cfg9346, Cfg9346_Unlock);
3385
3386 RTL_W32(MAC4, high);
3387 RTL_R32(MAC4);
3388
3389 RTL_W32(MAC0, low);
3390 RTL_R32(MAC0);
3391
3392 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3393 const struct exgmac_reg e[] = {
3394 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3395 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3396 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3397 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3398 low >> 16 },
3399 };
3400
3401 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3402 }
3403
3404 RTL_W8(Cfg9346, Cfg9346_Lock);
3405
3406 rtl_unlock_work(tp);
3407 }
3408
3409 static int rtl_set_mac_address(struct net_device *dev, void *p)
3410 {
3411 struct rtl8169_private *tp = netdev_priv(dev);
3412 struct sockaddr *addr = p;
3413
3414 if (!is_valid_ether_addr(addr->sa_data))
3415 return -EADDRNOTAVAIL;
3416
3417 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3418
3419 rtl_rar_set(tp, dev->dev_addr);
3420
3421 return 0;
3422 }
3423
3424 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3425 {
3426 struct rtl8169_private *tp = netdev_priv(dev);
3427 struct mii_ioctl_data *data = if_mii(ifr);
3428
3429 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3430 }
3431
3432 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3433 struct mii_ioctl_data *data, int cmd)
3434 {
3435 switch (cmd) {
3436 case SIOCGMIIPHY:
3437 data->phy_id = 32; /* Internal PHY */
3438 return 0;
3439
3440 case SIOCGMIIREG:
3441 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3442 return 0;
3443
3444 case SIOCSMIIREG:
3445 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3446 return 0;
3447 }
3448 return -EOPNOTSUPP;
3449 }
3450
3451 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3452 {
3453 return -EOPNOTSUPP;
3454 }
3455
3456 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3457 {
3458 if (tp->features & RTL_FEATURE_MSI) {
3459 pci_disable_msi(pdev);
3460 tp->features &= ~RTL_FEATURE_MSI;
3461 }
3462 }
3463
3464 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3465 {
3466 struct mdio_ops *ops = &tp->mdio_ops;
3467
3468 switch (tp->mac_version) {
3469 case RTL_GIGA_MAC_VER_27:
3470 ops->write = r8168dp_1_mdio_write;
3471 ops->read = r8168dp_1_mdio_read;
3472 break;
3473 case RTL_GIGA_MAC_VER_28:
3474 case RTL_GIGA_MAC_VER_31:
3475 ops->write = r8168dp_2_mdio_write;
3476 ops->read = r8168dp_2_mdio_read;
3477 break;
3478 default:
3479 ops->write = r8169_mdio_write;
3480 ops->read = r8169_mdio_read;
3481 break;
3482 }
3483 }
3484
3485 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3486 {
3487 void __iomem *ioaddr = tp->mmio_addr;
3488
3489 switch (tp->mac_version) {
3490 case RTL_GIGA_MAC_VER_29:
3491 case RTL_GIGA_MAC_VER_30:
3492 case RTL_GIGA_MAC_VER_32:
3493 case RTL_GIGA_MAC_VER_33:
3494 case RTL_GIGA_MAC_VER_34:
3495 case RTL_GIGA_MAC_VER_37:
3496 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3497 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3498 break;
3499 default:
3500 break;
3501 }
3502 }
3503
3504 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3505 {
3506 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3507 return false;
3508
3509 rtl_writephy(tp, 0x1f, 0x0000);
3510 rtl_writephy(tp, MII_BMCR, 0x0000);
3511
3512 rtl_wol_suspend_quirk(tp);
3513
3514 return true;
3515 }
3516
3517 static void r810x_phy_power_down(struct rtl8169_private *tp)
3518 {
3519 rtl_writephy(tp, 0x1f, 0x0000);
3520 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3521 }
3522
3523 static void r810x_phy_power_up(struct rtl8169_private *tp)
3524 {
3525 rtl_writephy(tp, 0x1f, 0x0000);
3526 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3527 }
3528
3529 static void r810x_pll_power_down(struct rtl8169_private *tp)
3530 {
3531 void __iomem *ioaddr = tp->mmio_addr;
3532
3533 if (rtl_wol_pll_power_down(tp))
3534 return;
3535
3536 r810x_phy_power_down(tp);
3537
3538 switch (tp->mac_version) {
3539 case RTL_GIGA_MAC_VER_07:
3540 case RTL_GIGA_MAC_VER_08:
3541 case RTL_GIGA_MAC_VER_09:
3542 case RTL_GIGA_MAC_VER_10:
3543 case RTL_GIGA_MAC_VER_13:
3544 case RTL_GIGA_MAC_VER_16:
3545 break;
3546 default:
3547 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3548 break;
3549 }
3550 }
3551
3552 static void r810x_pll_power_up(struct rtl8169_private *tp)
3553 {
3554 void __iomem *ioaddr = tp->mmio_addr;
3555
3556 r810x_phy_power_up(tp);
3557
3558 switch (tp->mac_version) {
3559 case RTL_GIGA_MAC_VER_07:
3560 case RTL_GIGA_MAC_VER_08:
3561 case RTL_GIGA_MAC_VER_09:
3562 case RTL_GIGA_MAC_VER_10:
3563 case RTL_GIGA_MAC_VER_13:
3564 case RTL_GIGA_MAC_VER_16:
3565 break;
3566 default:
3567 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3568 break;
3569 }
3570 }
3571
3572 static void r8168_phy_power_up(struct rtl8169_private *tp)
3573 {
3574 rtl_writephy(tp, 0x1f, 0x0000);
3575 switch (tp->mac_version) {
3576 case RTL_GIGA_MAC_VER_11:
3577 case RTL_GIGA_MAC_VER_12:
3578 case RTL_GIGA_MAC_VER_17:
3579 case RTL_GIGA_MAC_VER_18:
3580 case RTL_GIGA_MAC_VER_19:
3581 case RTL_GIGA_MAC_VER_20:
3582 case RTL_GIGA_MAC_VER_21:
3583 case RTL_GIGA_MAC_VER_22:
3584 case RTL_GIGA_MAC_VER_23:
3585 case RTL_GIGA_MAC_VER_24:
3586 case RTL_GIGA_MAC_VER_25:
3587 case RTL_GIGA_MAC_VER_26:
3588 case RTL_GIGA_MAC_VER_27:
3589 case RTL_GIGA_MAC_VER_28:
3590 case RTL_GIGA_MAC_VER_31:
3591 rtl_writephy(tp, 0x0e, 0x0000);
3592 break;
3593 default:
3594 break;
3595 }
3596 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3597 }
3598
3599 static void r8168_phy_power_down(struct rtl8169_private *tp)
3600 {
3601 rtl_writephy(tp, 0x1f, 0x0000);
3602 switch (tp->mac_version) {
3603 case RTL_GIGA_MAC_VER_32:
3604 case RTL_GIGA_MAC_VER_33:
3605 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3606 break;
3607
3608 case RTL_GIGA_MAC_VER_11:
3609 case RTL_GIGA_MAC_VER_12:
3610 case RTL_GIGA_MAC_VER_17:
3611 case RTL_GIGA_MAC_VER_18:
3612 case RTL_GIGA_MAC_VER_19:
3613 case RTL_GIGA_MAC_VER_20:
3614 case RTL_GIGA_MAC_VER_21:
3615 case RTL_GIGA_MAC_VER_22:
3616 case RTL_GIGA_MAC_VER_23:
3617 case RTL_GIGA_MAC_VER_24:
3618 case RTL_GIGA_MAC_VER_25:
3619 case RTL_GIGA_MAC_VER_26:
3620 case RTL_GIGA_MAC_VER_27:
3621 case RTL_GIGA_MAC_VER_28:
3622 case RTL_GIGA_MAC_VER_31:
3623 rtl_writephy(tp, 0x0e, 0x0200);
3624 default:
3625 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3626 break;
3627 }
3628 }
3629
3630 static void r8168_pll_power_down(struct rtl8169_private *tp)
3631 {
3632 void __iomem *ioaddr = tp->mmio_addr;
3633
3634 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3635 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3636 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3637 r8168dp_check_dash(tp)) {
3638 return;
3639 }
3640
3641 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3642 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3643 (RTL_R16(CPlusCmd) & ASF)) {
3644 return;
3645 }
3646
3647 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3648 tp->mac_version == RTL_GIGA_MAC_VER_33)
3649 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3650
3651 if (rtl_wol_pll_power_down(tp))
3652 return;
3653
3654 r8168_phy_power_down(tp);
3655
3656 switch (tp->mac_version) {
3657 case RTL_GIGA_MAC_VER_25:
3658 case RTL_GIGA_MAC_VER_26:
3659 case RTL_GIGA_MAC_VER_27:
3660 case RTL_GIGA_MAC_VER_28:
3661 case RTL_GIGA_MAC_VER_31:
3662 case RTL_GIGA_MAC_VER_32:
3663 case RTL_GIGA_MAC_VER_33:
3664 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3665 break;
3666 }
3667 }
3668
3669 static void r8168_pll_power_up(struct rtl8169_private *tp)
3670 {
3671 void __iomem *ioaddr = tp->mmio_addr;
3672
3673 switch (tp->mac_version) {
3674 case RTL_GIGA_MAC_VER_25:
3675 case RTL_GIGA_MAC_VER_26:
3676 case RTL_GIGA_MAC_VER_27:
3677 case RTL_GIGA_MAC_VER_28:
3678 case RTL_GIGA_MAC_VER_31:
3679 case RTL_GIGA_MAC_VER_32:
3680 case RTL_GIGA_MAC_VER_33:
3681 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3682 break;
3683 }
3684
3685 r8168_phy_power_up(tp);
3686 }
3687
3688 static void rtl_generic_op(struct rtl8169_private *tp,
3689 void (*op)(struct rtl8169_private *))
3690 {
3691 if (op)
3692 op(tp);
3693 }
3694
3695 static void rtl_pll_power_down(struct rtl8169_private *tp)
3696 {
3697 rtl_generic_op(tp, tp->pll_power_ops.down);
3698 }
3699
3700 static void rtl_pll_power_up(struct rtl8169_private *tp)
3701 {
3702 rtl_generic_op(tp, tp->pll_power_ops.up);
3703 }
3704
3705 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3706 {
3707 struct pll_power_ops *ops = &tp->pll_power_ops;
3708
3709 switch (tp->mac_version) {
3710 case RTL_GIGA_MAC_VER_07:
3711 case RTL_GIGA_MAC_VER_08:
3712 case RTL_GIGA_MAC_VER_09:
3713 case RTL_GIGA_MAC_VER_10:
3714 case RTL_GIGA_MAC_VER_16:
3715 case RTL_GIGA_MAC_VER_29:
3716 case RTL_GIGA_MAC_VER_30:
3717 case RTL_GIGA_MAC_VER_37:
3718 ops->down = r810x_pll_power_down;
3719 ops->up = r810x_pll_power_up;
3720 break;
3721
3722 case RTL_GIGA_MAC_VER_11:
3723 case RTL_GIGA_MAC_VER_12:
3724 case RTL_GIGA_MAC_VER_17:
3725 case RTL_GIGA_MAC_VER_18:
3726 case RTL_GIGA_MAC_VER_19:
3727 case RTL_GIGA_MAC_VER_20:
3728 case RTL_GIGA_MAC_VER_21:
3729 case RTL_GIGA_MAC_VER_22:
3730 case RTL_GIGA_MAC_VER_23:
3731 case RTL_GIGA_MAC_VER_24:
3732 case RTL_GIGA_MAC_VER_25:
3733 case RTL_GIGA_MAC_VER_26:
3734 case RTL_GIGA_MAC_VER_27:
3735 case RTL_GIGA_MAC_VER_28:
3736 case RTL_GIGA_MAC_VER_31:
3737 case RTL_GIGA_MAC_VER_32:
3738 case RTL_GIGA_MAC_VER_33:
3739 case RTL_GIGA_MAC_VER_34:
3740 case RTL_GIGA_MAC_VER_35:
3741 case RTL_GIGA_MAC_VER_36:
3742 ops->down = r8168_pll_power_down;
3743 ops->up = r8168_pll_power_up;
3744 break;
3745
3746 default:
3747 ops->down = NULL;
3748 ops->up = NULL;
3749 break;
3750 }
3751 }
3752
3753 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3754 {
3755 void __iomem *ioaddr = tp->mmio_addr;
3756
3757 switch (tp->mac_version) {
3758 case RTL_GIGA_MAC_VER_01:
3759 case RTL_GIGA_MAC_VER_02:
3760 case RTL_GIGA_MAC_VER_03:
3761 case RTL_GIGA_MAC_VER_04:
3762 case RTL_GIGA_MAC_VER_05:
3763 case RTL_GIGA_MAC_VER_06:
3764 case RTL_GIGA_MAC_VER_10:
3765 case RTL_GIGA_MAC_VER_11:
3766 case RTL_GIGA_MAC_VER_12:
3767 case RTL_GIGA_MAC_VER_13:
3768 case RTL_GIGA_MAC_VER_14:
3769 case RTL_GIGA_MAC_VER_15:
3770 case RTL_GIGA_MAC_VER_16:
3771 case RTL_GIGA_MAC_VER_17:
3772 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3773 break;
3774 case RTL_GIGA_MAC_VER_18:
3775 case RTL_GIGA_MAC_VER_19:
3776 case RTL_GIGA_MAC_VER_20:
3777 case RTL_GIGA_MAC_VER_21:
3778 case RTL_GIGA_MAC_VER_22:
3779 case RTL_GIGA_MAC_VER_23:
3780 case RTL_GIGA_MAC_VER_24:
3781 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3782 break;
3783 default:
3784 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3785 break;
3786 }
3787 }
3788
3789 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3790 {
3791 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3792 }
3793
3794 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3795 {
3796 void __iomem *ioaddr = tp->mmio_addr;
3797
3798 RTL_W8(Cfg9346, Cfg9346_Unlock);
3799 rtl_generic_op(tp, tp->jumbo_ops.enable);
3800 RTL_W8(Cfg9346, Cfg9346_Lock);
3801 }
3802
3803 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3804 {
3805 void __iomem *ioaddr = tp->mmio_addr;
3806
3807 RTL_W8(Cfg9346, Cfg9346_Unlock);
3808 rtl_generic_op(tp, tp->jumbo_ops.disable);
3809 RTL_W8(Cfg9346, Cfg9346_Lock);
3810 }
3811
3812 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3813 {
3814 void __iomem *ioaddr = tp->mmio_addr;
3815
3816 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3817 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3818 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3819 }
3820
3821 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3822 {
3823 void __iomem *ioaddr = tp->mmio_addr;
3824
3825 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3826 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3827 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3828 }
3829
3830 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3831 {
3832 void __iomem *ioaddr = tp->mmio_addr;
3833
3834 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3835 }
3836
3837 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3838 {
3839 void __iomem *ioaddr = tp->mmio_addr;
3840
3841 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3842 }
3843
3844 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3845 {
3846 void __iomem *ioaddr = tp->mmio_addr;
3847
3848 RTL_W8(MaxTxPacketSize, 0x3f);
3849 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3850 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3851 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3852 }
3853
3854 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3855 {
3856 void __iomem *ioaddr = tp->mmio_addr;
3857
3858 RTL_W8(MaxTxPacketSize, 0x0c);
3859 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3860 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3861 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3862 }
3863
3864 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3865 {
3866 rtl_tx_performance_tweak(tp->pci_dev,
3867 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3868 }
3869
3870 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3871 {
3872 rtl_tx_performance_tweak(tp->pci_dev,
3873 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3874 }
3875
3876 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3877 {
3878 void __iomem *ioaddr = tp->mmio_addr;
3879
3880 r8168b_0_hw_jumbo_enable(tp);
3881
3882 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3883 }
3884
3885 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3886 {
3887 void __iomem *ioaddr = tp->mmio_addr;
3888
3889 r8168b_0_hw_jumbo_disable(tp);
3890
3891 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3892 }
3893
3894 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3895 {
3896 struct jumbo_ops *ops = &tp->jumbo_ops;
3897
3898 switch (tp->mac_version) {
3899 case RTL_GIGA_MAC_VER_11:
3900 ops->disable = r8168b_0_hw_jumbo_disable;
3901 ops->enable = r8168b_0_hw_jumbo_enable;
3902 break;
3903 case RTL_GIGA_MAC_VER_12:
3904 case RTL_GIGA_MAC_VER_17:
3905 ops->disable = r8168b_1_hw_jumbo_disable;
3906 ops->enable = r8168b_1_hw_jumbo_enable;
3907 break;
3908 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3909 case RTL_GIGA_MAC_VER_19:
3910 case RTL_GIGA_MAC_VER_20:
3911 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3912 case RTL_GIGA_MAC_VER_22:
3913 case RTL_GIGA_MAC_VER_23:
3914 case RTL_GIGA_MAC_VER_24:
3915 case RTL_GIGA_MAC_VER_25:
3916 case RTL_GIGA_MAC_VER_26:
3917 ops->disable = r8168c_hw_jumbo_disable;
3918 ops->enable = r8168c_hw_jumbo_enable;
3919 break;
3920 case RTL_GIGA_MAC_VER_27:
3921 case RTL_GIGA_MAC_VER_28:
3922 ops->disable = r8168dp_hw_jumbo_disable;
3923 ops->enable = r8168dp_hw_jumbo_enable;
3924 break;
3925 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3926 case RTL_GIGA_MAC_VER_32:
3927 case RTL_GIGA_MAC_VER_33:
3928 case RTL_GIGA_MAC_VER_34:
3929 ops->disable = r8168e_hw_jumbo_disable;
3930 ops->enable = r8168e_hw_jumbo_enable;
3931 break;
3932
3933 /*
3934 * No action needed for jumbo frames with 8169.
3935 * No jumbo for 810x at all.
3936 */
3937 default:
3938 ops->disable = NULL;
3939 ops->enable = NULL;
3940 break;
3941 }
3942 }
3943
3944 static void rtl_hw_reset(struct rtl8169_private *tp)
3945 {
3946 void __iomem *ioaddr = tp->mmio_addr;
3947 int i;
3948
3949 /* Soft reset the chip. */
3950 RTL_W8(ChipCmd, CmdReset);
3951
3952 /* Check that the chip has finished the reset. */
3953 for (i = 0; i < 100; i++) {
3954 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3955 break;
3956 udelay(100);
3957 }
3958 }
3959
3960 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3961 {
3962 struct rtl_fw *rtl_fw;
3963 const char *name;
3964 int rc = -ENOMEM;
3965
3966 name = rtl_lookup_firmware_name(tp);
3967 if (!name)
3968 goto out_no_firmware;
3969
3970 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3971 if (!rtl_fw)
3972 goto err_warn;
3973
3974 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3975 if (rc < 0)
3976 goto err_free;
3977
3978 rc = rtl_check_firmware(tp, rtl_fw);
3979 if (rc < 0)
3980 goto err_release_firmware;
3981
3982 tp->rtl_fw = rtl_fw;
3983 out:
3984 return;
3985
3986 err_release_firmware:
3987 release_firmware(rtl_fw->fw);
3988 err_free:
3989 kfree(rtl_fw);
3990 err_warn:
3991 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3992 name, rc);
3993 out_no_firmware:
3994 tp->rtl_fw = NULL;
3995 goto out;
3996 }
3997
3998 static void rtl_request_firmware(struct rtl8169_private *tp)
3999 {
4000 if (IS_ERR(tp->rtl_fw))
4001 rtl_request_uncached_firmware(tp);
4002 }
4003
4004 static void rtl_rx_close(struct rtl8169_private *tp)
4005 {
4006 void __iomem *ioaddr = tp->mmio_addr;
4007
4008 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4009 }
4010
4011 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4012 {
4013 void __iomem *ioaddr = tp->mmio_addr;
4014
4015 /* Disable interrupts */
4016 rtl8169_irq_mask_and_ack(tp);
4017
4018 rtl_rx_close(tp);
4019
4020 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4021 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4022 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4023 while (RTL_R8(TxPoll) & NPQ)
4024 udelay(20);
4025 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4026 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4027 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4028 tp->mac_version == RTL_GIGA_MAC_VER_37) {
4029 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4030 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4031 udelay(100);
4032 } else {
4033 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4034 udelay(100);
4035 }
4036
4037 rtl_hw_reset(tp);
4038 }
4039
4040 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4041 {
4042 void __iomem *ioaddr = tp->mmio_addr;
4043
4044 /* Set DMA burst size and Interframe Gap Time */
4045 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4046 (InterFrameGap << TxInterFrameGapShift));
4047 }
4048
4049 static void rtl_hw_start(struct net_device *dev)
4050 {
4051 struct rtl8169_private *tp = netdev_priv(dev);
4052
4053 tp->hw_start(dev);
4054
4055 rtl_irq_enable_all(tp);
4056 }
4057
4058 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4059 void __iomem *ioaddr)
4060 {
4061 /*
4062 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4063 * register to be written before TxDescAddrLow to work.
4064 * Switching from MMIO to I/O access fixes the issue as well.
4065 */
4066 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4067 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4068 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4069 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4070 }
4071
4072 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4073 {
4074 u16 cmd;
4075
4076 cmd = RTL_R16(CPlusCmd);
4077 RTL_W16(CPlusCmd, cmd);
4078 return cmd;
4079 }
4080
4081 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4082 {
4083 /* Low hurts. Let's disable the filtering. */
4084 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4085 }
4086
4087 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4088 {
4089 static const struct rtl_cfg2_info {
4090 u32 mac_version;
4091 u32 clk;
4092 u32 val;
4093 } cfg2_info [] = {
4094 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4095 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4096 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4097 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4098 };
4099 const struct rtl_cfg2_info *p = cfg2_info;
4100 unsigned int i;
4101 u32 clk;
4102
4103 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4104 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4105 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4106 RTL_W32(0x7c, p->val);
4107 break;
4108 }
4109 }
4110 }
4111
4112 static void rtl_set_rx_mode(struct net_device *dev)
4113 {
4114 struct rtl8169_private *tp = netdev_priv(dev);
4115 void __iomem *ioaddr = tp->mmio_addr;
4116 u32 mc_filter[2]; /* Multicast hash filter */
4117 int rx_mode;
4118 u32 tmp = 0;
4119
4120 if (dev->flags & IFF_PROMISC) {
4121 /* Unconditionally log net taps. */
4122 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4123 rx_mode =
4124 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4125 AcceptAllPhys;
4126 mc_filter[1] = mc_filter[0] = 0xffffffff;
4127 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4128 (dev->flags & IFF_ALLMULTI)) {
4129 /* Too many to filter perfectly -- accept all multicasts. */
4130 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4131 mc_filter[1] = mc_filter[0] = 0xffffffff;
4132 } else {
4133 struct netdev_hw_addr *ha;
4134
4135 rx_mode = AcceptBroadcast | AcceptMyPhys;
4136 mc_filter[1] = mc_filter[0] = 0;
4137 netdev_for_each_mc_addr(ha, dev) {
4138 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4139 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4140 rx_mode |= AcceptMulticast;
4141 }
4142 }
4143
4144 if (dev->features & NETIF_F_RXALL)
4145 rx_mode |= (AcceptErr | AcceptRunt);
4146
4147 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4148
4149 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4150 u32 data = mc_filter[0];
4151
4152 mc_filter[0] = swab32(mc_filter[1]);
4153 mc_filter[1] = swab32(data);
4154 }
4155
4156 RTL_W32(MAR0 + 4, mc_filter[1]);
4157 RTL_W32(MAR0 + 0, mc_filter[0]);
4158
4159 RTL_W32(RxConfig, tmp);
4160 }
4161
4162 static void rtl_hw_start_8169(struct net_device *dev)
4163 {
4164 struct rtl8169_private *tp = netdev_priv(dev);
4165 void __iomem *ioaddr = tp->mmio_addr;
4166 struct pci_dev *pdev = tp->pci_dev;
4167
4168 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4169 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4170 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4171 }
4172
4173 RTL_W8(Cfg9346, Cfg9346_Unlock);
4174 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4175 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4176 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4177 tp->mac_version == RTL_GIGA_MAC_VER_04)
4178 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4179
4180 rtl_init_rxcfg(tp);
4181
4182 RTL_W8(EarlyTxThres, NoEarlyTx);
4183
4184 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4185
4186 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4187 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4188 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4189 tp->mac_version == RTL_GIGA_MAC_VER_04)
4190 rtl_set_rx_tx_config_registers(tp);
4191
4192 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4193
4194 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4195 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4196 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4197 "Bit-3 and bit-14 MUST be 1\n");
4198 tp->cp_cmd |= (1 << 14);
4199 }
4200
4201 RTL_W16(CPlusCmd, tp->cp_cmd);
4202
4203 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4204
4205 /*
4206 * Undocumented corner. Supposedly:
4207 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4208 */
4209 RTL_W16(IntrMitigate, 0x0000);
4210
4211 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4212
4213 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4214 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4215 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4216 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4217 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4218 rtl_set_rx_tx_config_registers(tp);
4219 }
4220
4221 RTL_W8(Cfg9346, Cfg9346_Lock);
4222
4223 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4224 RTL_R8(IntrMask);
4225
4226 RTL_W32(RxMissed, 0);
4227
4228 rtl_set_rx_mode(dev);
4229
4230 /* no early-rx interrupts */
4231 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4232 }
4233
4234 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4235 {
4236 if (tp->csi_ops.write)
4237 tp->csi_ops.write(tp->mmio_addr, addr, value);
4238 }
4239
4240 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4241 {
4242 if (tp->csi_ops.read)
4243 return tp->csi_ops.read(tp->mmio_addr, addr);
4244 else
4245 return ~0;
4246 }
4247
4248 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4249 {
4250 u32 csi;
4251
4252 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4253 rtl_csi_write(tp, 0x070c, csi | bits);
4254 }
4255
4256 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4257 {
4258 rtl_csi_access_enable(tp, 0x17000000);
4259 }
4260
4261 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4262 {
4263 rtl_csi_access_enable(tp, 0x27000000);
4264 }
4265
4266 static void r8169_csi_write(void __iomem *ioaddr, int addr, int value)
4267 {
4268 unsigned int i;
4269
4270 RTL_W32(CSIDR, value);
4271 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4272 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4273
4274 for (i = 0; i < 100; i++) {
4275 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
4276 break;
4277 udelay(10);
4278 }
4279 }
4280
4281 static u32 r8169_csi_read(void __iomem *ioaddr, int addr)
4282 {
4283 u32 value = ~0x00;
4284 unsigned int i;
4285
4286 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4287 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4288
4289 for (i = 0; i < 100; i++) {
4290 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
4291 value = RTL_R32(CSIDR);
4292 break;
4293 }
4294 udelay(10);
4295 }
4296
4297 return value;
4298 }
4299
4300 static void r8402_csi_write(void __iomem *ioaddr, int addr, int value)
4301 {
4302 unsigned int i;
4303
4304 RTL_W32(CSIDR, value);
4305 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4306 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4307 CSIAR_FUNC_NIC);
4308
4309 for (i = 0; i < 100; i++) {
4310 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
4311 break;
4312 udelay(10);
4313 }
4314 }
4315
4316 static u32 r8402_csi_read(void __iomem *ioaddr, int addr)
4317 {
4318 u32 value = ~0x00;
4319 unsigned int i;
4320
4321 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4322 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4323
4324 for (i = 0; i < 100; i++) {
4325 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
4326 value = RTL_R32(CSIDR);
4327 break;
4328 }
4329 udelay(10);
4330 }
4331
4332 return value;
4333 }
4334
4335 static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
4336 {
4337 struct csi_ops *ops = &tp->csi_ops;
4338
4339 switch (tp->mac_version) {
4340 case RTL_GIGA_MAC_VER_01:
4341 case RTL_GIGA_MAC_VER_02:
4342 case RTL_GIGA_MAC_VER_03:
4343 case RTL_GIGA_MAC_VER_04:
4344 case RTL_GIGA_MAC_VER_05:
4345 case RTL_GIGA_MAC_VER_06:
4346 case RTL_GIGA_MAC_VER_10:
4347 case RTL_GIGA_MAC_VER_11:
4348 case RTL_GIGA_MAC_VER_12:
4349 case RTL_GIGA_MAC_VER_13:
4350 case RTL_GIGA_MAC_VER_14:
4351 case RTL_GIGA_MAC_VER_15:
4352 case RTL_GIGA_MAC_VER_16:
4353 case RTL_GIGA_MAC_VER_17:
4354 ops->write = NULL;
4355 ops->read = NULL;
4356 break;
4357
4358 case RTL_GIGA_MAC_VER_37:
4359 ops->write = r8402_csi_write;
4360 ops->read = r8402_csi_read;
4361 break;
4362
4363 default:
4364 ops->write = r8169_csi_write;
4365 ops->read = r8169_csi_read;
4366 break;
4367 }
4368 }
4369
4370 struct ephy_info {
4371 unsigned int offset;
4372 u16 mask;
4373 u16 bits;
4374 };
4375
4376 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4377 {
4378 u16 w;
4379
4380 while (len-- > 0) {
4381 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4382 rtl_ephy_write(ioaddr, e->offset, w);
4383 e++;
4384 }
4385 }
4386
4387 static void rtl_disable_clock_request(struct pci_dev *pdev)
4388 {
4389 int cap = pci_pcie_cap(pdev);
4390
4391 if (cap) {
4392 u16 ctl;
4393
4394 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4395 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4396 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4397 }
4398 }
4399
4400 static void rtl_enable_clock_request(struct pci_dev *pdev)
4401 {
4402 int cap = pci_pcie_cap(pdev);
4403
4404 if (cap) {
4405 u16 ctl;
4406
4407 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4408 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4409 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4410 }
4411 }
4412
4413 #define R8168_CPCMD_QUIRK_MASK (\
4414 EnableBist | \
4415 Mac_dbgo_oe | \
4416 Force_half_dup | \
4417 Force_rxflow_en | \
4418 Force_txflow_en | \
4419 Cxpl_dbg_sel | \
4420 ASF | \
4421 PktCntrDisable | \
4422 Mac_dbgo_sel)
4423
4424 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4425 {
4426 void __iomem *ioaddr = tp->mmio_addr;
4427 struct pci_dev *pdev = tp->pci_dev;
4428
4429 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4430
4431 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4432
4433 rtl_tx_performance_tweak(pdev,
4434 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4435 }
4436
4437 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4438 {
4439 void __iomem *ioaddr = tp->mmio_addr;
4440
4441 rtl_hw_start_8168bb(tp);
4442
4443 RTL_W8(MaxTxPacketSize, TxPacketMax);
4444
4445 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4446 }
4447
4448 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4449 {
4450 void __iomem *ioaddr = tp->mmio_addr;
4451 struct pci_dev *pdev = tp->pci_dev;
4452
4453 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4454
4455 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4456
4457 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4458
4459 rtl_disable_clock_request(pdev);
4460
4461 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4462 }
4463
4464 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4465 {
4466 void __iomem *ioaddr = tp->mmio_addr;
4467 static const struct ephy_info e_info_8168cp[] = {
4468 { 0x01, 0, 0x0001 },
4469 { 0x02, 0x0800, 0x1000 },
4470 { 0x03, 0, 0x0042 },
4471 { 0x06, 0x0080, 0x0000 },
4472 { 0x07, 0, 0x2000 }
4473 };
4474
4475 rtl_csi_access_enable_2(tp);
4476
4477 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4478
4479 __rtl_hw_start_8168cp(tp);
4480 }
4481
4482 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4483 {
4484 void __iomem *ioaddr = tp->mmio_addr;
4485 struct pci_dev *pdev = tp->pci_dev;
4486
4487 rtl_csi_access_enable_2(tp);
4488
4489 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4490
4491 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4492
4493 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4494 }
4495
4496 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4497 {
4498 void __iomem *ioaddr = tp->mmio_addr;
4499 struct pci_dev *pdev = tp->pci_dev;
4500
4501 rtl_csi_access_enable_2(tp);
4502
4503 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4504
4505 /* Magic. */
4506 RTL_W8(DBG_REG, 0x20);
4507
4508 RTL_W8(MaxTxPacketSize, TxPacketMax);
4509
4510 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4511
4512 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4513 }
4514
4515 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4516 {
4517 void __iomem *ioaddr = tp->mmio_addr;
4518 static const struct ephy_info e_info_8168c_1[] = {
4519 { 0x02, 0x0800, 0x1000 },
4520 { 0x03, 0, 0x0002 },
4521 { 0x06, 0x0080, 0x0000 }
4522 };
4523
4524 rtl_csi_access_enable_2(tp);
4525
4526 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4527
4528 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4529
4530 __rtl_hw_start_8168cp(tp);
4531 }
4532
4533 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4534 {
4535 void __iomem *ioaddr = tp->mmio_addr;
4536 static const struct ephy_info e_info_8168c_2[] = {
4537 { 0x01, 0, 0x0001 },
4538 { 0x03, 0x0400, 0x0220 }
4539 };
4540
4541 rtl_csi_access_enable_2(tp);
4542
4543 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4544
4545 __rtl_hw_start_8168cp(tp);
4546 }
4547
4548 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4549 {
4550 rtl_hw_start_8168c_2(tp);
4551 }
4552
4553 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4554 {
4555 rtl_csi_access_enable_2(tp);
4556
4557 __rtl_hw_start_8168cp(tp);
4558 }
4559
4560 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4561 {
4562 void __iomem *ioaddr = tp->mmio_addr;
4563 struct pci_dev *pdev = tp->pci_dev;
4564
4565 rtl_csi_access_enable_2(tp);
4566
4567 rtl_disable_clock_request(pdev);
4568
4569 RTL_W8(MaxTxPacketSize, TxPacketMax);
4570
4571 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4572
4573 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4574 }
4575
4576 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4577 {
4578 void __iomem *ioaddr = tp->mmio_addr;
4579 struct pci_dev *pdev = tp->pci_dev;
4580
4581 rtl_csi_access_enable_1(tp);
4582
4583 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4584
4585 RTL_W8(MaxTxPacketSize, TxPacketMax);
4586
4587 rtl_disable_clock_request(pdev);
4588 }
4589
4590 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4591 {
4592 void __iomem *ioaddr = tp->mmio_addr;
4593 struct pci_dev *pdev = tp->pci_dev;
4594 static const struct ephy_info e_info_8168d_4[] = {
4595 { 0x0b, ~0, 0x48 },
4596 { 0x19, 0x20, 0x50 },
4597 { 0x0c, ~0, 0x20 }
4598 };
4599 int i;
4600
4601 rtl_csi_access_enable_1(tp);
4602
4603 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4604
4605 RTL_W8(MaxTxPacketSize, TxPacketMax);
4606
4607 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4608 const struct ephy_info *e = e_info_8168d_4 + i;
4609 u16 w;
4610
4611 w = rtl_ephy_read(ioaddr, e->offset);
4612 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4613 }
4614
4615 rtl_enable_clock_request(pdev);
4616 }
4617
4618 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4619 {
4620 void __iomem *ioaddr = tp->mmio_addr;
4621 struct pci_dev *pdev = tp->pci_dev;
4622 static const struct ephy_info e_info_8168e_1[] = {
4623 { 0x00, 0x0200, 0x0100 },
4624 { 0x00, 0x0000, 0x0004 },
4625 { 0x06, 0x0002, 0x0001 },
4626 { 0x06, 0x0000, 0x0030 },
4627 { 0x07, 0x0000, 0x2000 },
4628 { 0x00, 0x0000, 0x0020 },
4629 { 0x03, 0x5800, 0x2000 },
4630 { 0x03, 0x0000, 0x0001 },
4631 { 0x01, 0x0800, 0x1000 },
4632 { 0x07, 0x0000, 0x4000 },
4633 { 0x1e, 0x0000, 0x2000 },
4634 { 0x19, 0xffff, 0xfe6c },
4635 { 0x0a, 0x0000, 0x0040 }
4636 };
4637
4638 rtl_csi_access_enable_2(tp);
4639
4640 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4641
4642 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4643
4644 RTL_W8(MaxTxPacketSize, TxPacketMax);
4645
4646 rtl_disable_clock_request(pdev);
4647
4648 /* Reset tx FIFO pointer */
4649 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4650 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4651
4652 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4653 }
4654
4655 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4656 {
4657 void __iomem *ioaddr = tp->mmio_addr;
4658 struct pci_dev *pdev = tp->pci_dev;
4659 static const struct ephy_info e_info_8168e_2[] = {
4660 { 0x09, 0x0000, 0x0080 },
4661 { 0x19, 0x0000, 0x0224 }
4662 };
4663
4664 rtl_csi_access_enable_1(tp);
4665
4666 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4667
4668 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4669
4670 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4671 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4672 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4673 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4674 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4675 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4676 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4677 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4678 ERIAR_EXGMAC);
4679
4680 RTL_W8(MaxTxPacketSize, EarlySize);
4681
4682 rtl_disable_clock_request(pdev);
4683
4684 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4685 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4686
4687 /* Adjust EEE LED frequency */
4688 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4689
4690 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4691 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4692 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4693 }
4694
4695 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4696 {
4697 void __iomem *ioaddr = tp->mmio_addr;
4698 struct pci_dev *pdev = tp->pci_dev;
4699
4700 rtl_csi_access_enable_2(tp);
4701
4702 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4703
4704 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4705 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4706 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4707 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4708 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4709 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4710 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4711 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4712 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4713 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4714
4715 RTL_W8(MaxTxPacketSize, EarlySize);
4716
4717 rtl_disable_clock_request(pdev);
4718
4719 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4720 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4721 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4722 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4723 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4724 }
4725
4726 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4727 {
4728 void __iomem *ioaddr = tp->mmio_addr;
4729 static const struct ephy_info e_info_8168f_1[] = {
4730 { 0x06, 0x00c0, 0x0020 },
4731 { 0x08, 0x0001, 0x0002 },
4732 { 0x09, 0x0000, 0x0080 },
4733 { 0x19, 0x0000, 0x0224 }
4734 };
4735
4736 rtl_hw_start_8168f(tp);
4737
4738 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4739
4740 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4741 ERIAR_EXGMAC);
4742
4743 /* Adjust EEE LED frequency */
4744 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4745 }
4746
4747 static void rtl_hw_start_8168(struct net_device *dev)
4748 {
4749 struct rtl8169_private *tp = netdev_priv(dev);
4750 void __iomem *ioaddr = tp->mmio_addr;
4751
4752 RTL_W8(Cfg9346, Cfg9346_Unlock);
4753
4754 RTL_W8(MaxTxPacketSize, TxPacketMax);
4755
4756 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4757
4758 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4759
4760 RTL_W16(CPlusCmd, tp->cp_cmd);
4761
4762 RTL_W16(IntrMitigate, 0x5151);
4763
4764 /* Work around for RxFIFO overflow. */
4765 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4766 tp->event_slow |= RxFIFOOver | PCSTimeout;
4767 tp->event_slow &= ~RxOverflow;
4768 }
4769
4770 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4771
4772 rtl_set_rx_mode(dev);
4773
4774 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4775 (InterFrameGap << TxInterFrameGapShift));
4776
4777 RTL_R8(IntrMask);
4778
4779 switch (tp->mac_version) {
4780 case RTL_GIGA_MAC_VER_11:
4781 rtl_hw_start_8168bb(tp);
4782 break;
4783
4784 case RTL_GIGA_MAC_VER_12:
4785 case RTL_GIGA_MAC_VER_17:
4786 rtl_hw_start_8168bef(tp);
4787 break;
4788
4789 case RTL_GIGA_MAC_VER_18:
4790 rtl_hw_start_8168cp_1(tp);
4791 break;
4792
4793 case RTL_GIGA_MAC_VER_19:
4794 rtl_hw_start_8168c_1(tp);
4795 break;
4796
4797 case RTL_GIGA_MAC_VER_20:
4798 rtl_hw_start_8168c_2(tp);
4799 break;
4800
4801 case RTL_GIGA_MAC_VER_21:
4802 rtl_hw_start_8168c_3(tp);
4803 break;
4804
4805 case RTL_GIGA_MAC_VER_22:
4806 rtl_hw_start_8168c_4(tp);
4807 break;
4808
4809 case RTL_GIGA_MAC_VER_23:
4810 rtl_hw_start_8168cp_2(tp);
4811 break;
4812
4813 case RTL_GIGA_MAC_VER_24:
4814 rtl_hw_start_8168cp_3(tp);
4815 break;
4816
4817 case RTL_GIGA_MAC_VER_25:
4818 case RTL_GIGA_MAC_VER_26:
4819 case RTL_GIGA_MAC_VER_27:
4820 rtl_hw_start_8168d(tp);
4821 break;
4822
4823 case RTL_GIGA_MAC_VER_28:
4824 rtl_hw_start_8168d_4(tp);
4825 break;
4826
4827 case RTL_GIGA_MAC_VER_31:
4828 rtl_hw_start_8168dp(tp);
4829 break;
4830
4831 case RTL_GIGA_MAC_VER_32:
4832 case RTL_GIGA_MAC_VER_33:
4833 rtl_hw_start_8168e_1(tp);
4834 break;
4835 case RTL_GIGA_MAC_VER_34:
4836 rtl_hw_start_8168e_2(tp);
4837 break;
4838
4839 case RTL_GIGA_MAC_VER_35:
4840 case RTL_GIGA_MAC_VER_36:
4841 rtl_hw_start_8168f_1(tp);
4842 break;
4843
4844 default:
4845 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4846 dev->name, tp->mac_version);
4847 break;
4848 }
4849
4850 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4851
4852 RTL_W8(Cfg9346, Cfg9346_Lock);
4853
4854 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4855 }
4856
4857 #define R810X_CPCMD_QUIRK_MASK (\
4858 EnableBist | \
4859 Mac_dbgo_oe | \
4860 Force_half_dup | \
4861 Force_rxflow_en | \
4862 Force_txflow_en | \
4863 Cxpl_dbg_sel | \
4864 ASF | \
4865 PktCntrDisable | \
4866 Mac_dbgo_sel)
4867
4868 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
4869 {
4870 void __iomem *ioaddr = tp->mmio_addr;
4871 struct pci_dev *pdev = tp->pci_dev;
4872 static const struct ephy_info e_info_8102e_1[] = {
4873 { 0x01, 0, 0x6e65 },
4874 { 0x02, 0, 0x091f },
4875 { 0x03, 0, 0xc2f9 },
4876 { 0x06, 0, 0xafb5 },
4877 { 0x07, 0, 0x0e00 },
4878 { 0x19, 0, 0xec80 },
4879 { 0x01, 0, 0x2e65 },
4880 { 0x01, 0, 0x6e65 }
4881 };
4882 u8 cfg1;
4883
4884 rtl_csi_access_enable_2(tp);
4885
4886 RTL_W8(DBG_REG, FIX_NAK_1);
4887
4888 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4889
4890 RTL_W8(Config1,
4891 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4892 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4893
4894 cfg1 = RTL_R8(Config1);
4895 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4896 RTL_W8(Config1, cfg1 & ~LEDS0);
4897
4898 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4899 }
4900
4901 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
4902 {
4903 void __iomem *ioaddr = tp->mmio_addr;
4904 struct pci_dev *pdev = tp->pci_dev;
4905
4906 rtl_csi_access_enable_2(tp);
4907
4908 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4909
4910 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4911 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4912 }
4913
4914 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
4915 {
4916 rtl_hw_start_8102e_2(tp);
4917
4918 rtl_ephy_write(tp->mmio_addr, 0x03, 0xc2f9);
4919 }
4920
4921 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
4922 {
4923 void __iomem *ioaddr = tp->mmio_addr;
4924 static const struct ephy_info e_info_8105e_1[] = {
4925 { 0x07, 0, 0x4000 },
4926 { 0x19, 0, 0x0200 },
4927 { 0x19, 0, 0x0020 },
4928 { 0x1e, 0, 0x2000 },
4929 { 0x03, 0, 0x0001 },
4930 { 0x19, 0, 0x0100 },
4931 { 0x19, 0, 0x0004 },
4932 { 0x0a, 0, 0x0020 }
4933 };
4934
4935 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4936 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4937
4938 /* Disable Early Tally Counter */
4939 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4940
4941 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4942 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4943
4944 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4945 }
4946
4947 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
4948 {
4949 void __iomem *ioaddr = tp->mmio_addr;
4950
4951 rtl_hw_start_8105e_1(tp);
4952 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4953 }
4954
4955 static void rtl_hw_start_8402(struct rtl8169_private *tp)
4956 {
4957 void __iomem *ioaddr = tp->mmio_addr;
4958 static const struct ephy_info e_info_8402[] = {
4959 { 0x19, 0xffff, 0xff64 },
4960 { 0x1e, 0, 0x4000 }
4961 };
4962
4963 rtl_csi_access_enable_2(tp);
4964
4965 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4966 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4967
4968 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4969 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4970
4971 rtl_ephy_init(ioaddr, e_info_8402, ARRAY_SIZE(e_info_8402));
4972
4973 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4974
4975 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
4976 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
4977 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4978 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4979 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4980 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4981 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00,
4982 ERIAR_EXGMAC);
4983 }
4984
4985 static void rtl_hw_start_8101(struct net_device *dev)
4986 {
4987 struct rtl8169_private *tp = netdev_priv(dev);
4988 void __iomem *ioaddr = tp->mmio_addr;
4989 struct pci_dev *pdev = tp->pci_dev;
4990
4991 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4992 tp->event_slow &= ~RxFIFOOver;
4993
4994 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4995 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4996 int cap = pci_pcie_cap(pdev);
4997
4998 if (cap) {
4999 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5000 PCI_EXP_DEVCTL_NOSNOOP_EN);
5001 }
5002 }
5003
5004 RTL_W8(Cfg9346, Cfg9346_Unlock);
5005
5006 switch (tp->mac_version) {
5007 case RTL_GIGA_MAC_VER_07:
5008 rtl_hw_start_8102e_1(tp);
5009 break;
5010
5011 case RTL_GIGA_MAC_VER_08:
5012 rtl_hw_start_8102e_3(tp);
5013 break;
5014
5015 case RTL_GIGA_MAC_VER_09:
5016 rtl_hw_start_8102e_2(tp);
5017 break;
5018
5019 case RTL_GIGA_MAC_VER_29:
5020 rtl_hw_start_8105e_1(tp);
5021 break;
5022 case RTL_GIGA_MAC_VER_30:
5023 rtl_hw_start_8105e_2(tp);
5024 break;
5025
5026 case RTL_GIGA_MAC_VER_37:
5027 rtl_hw_start_8402(tp);
5028 break;
5029 }
5030
5031 RTL_W8(Cfg9346, Cfg9346_Lock);
5032
5033 RTL_W8(MaxTxPacketSize, TxPacketMax);
5034
5035 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5036
5037 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5038 RTL_W16(CPlusCmd, tp->cp_cmd);
5039
5040 RTL_W16(IntrMitigate, 0x0000);
5041
5042 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5043
5044 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5045 rtl_set_rx_tx_config_registers(tp);
5046
5047 RTL_R8(IntrMask);
5048
5049 rtl_set_rx_mode(dev);
5050
5051 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5052 }
5053
5054 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5055 {
5056 struct rtl8169_private *tp = netdev_priv(dev);
5057
5058 if (new_mtu < ETH_ZLEN ||
5059 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5060 return -EINVAL;
5061
5062 if (new_mtu > ETH_DATA_LEN)
5063 rtl_hw_jumbo_enable(tp);
5064 else
5065 rtl_hw_jumbo_disable(tp);
5066
5067 dev->mtu = new_mtu;
5068 netdev_update_features(dev);
5069
5070 return 0;
5071 }
5072
5073 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5074 {
5075 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5076 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5077 }
5078
5079 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5080 void **data_buff, struct RxDesc *desc)
5081 {
5082 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5083 DMA_FROM_DEVICE);
5084
5085 kfree(*data_buff);
5086 *data_buff = NULL;
5087 rtl8169_make_unusable_by_asic(desc);
5088 }
5089
5090 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5091 {
5092 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5093
5094 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5095 }
5096
5097 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5098 u32 rx_buf_sz)
5099 {
5100 desc->addr = cpu_to_le64(mapping);
5101 wmb();
5102 rtl8169_mark_to_asic(desc, rx_buf_sz);
5103 }
5104
5105 static inline void *rtl8169_align(void *data)
5106 {
5107 return (void *)ALIGN((long)data, 16);
5108 }
5109
5110 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5111 struct RxDesc *desc)
5112 {
5113 void *data;
5114 dma_addr_t mapping;
5115 struct device *d = &tp->pci_dev->dev;
5116 struct net_device *dev = tp->dev;
5117 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5118
5119 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5120 if (!data)
5121 return NULL;
5122
5123 if (rtl8169_align(data) != data) {
5124 kfree(data);
5125 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5126 if (!data)
5127 return NULL;
5128 }
5129
5130 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5131 DMA_FROM_DEVICE);
5132 if (unlikely(dma_mapping_error(d, mapping))) {
5133 if (net_ratelimit())
5134 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5135 goto err_out;
5136 }
5137
5138 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5139 return data;
5140
5141 err_out:
5142 kfree(data);
5143 return NULL;
5144 }
5145
5146 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5147 {
5148 unsigned int i;
5149
5150 for (i = 0; i < NUM_RX_DESC; i++) {
5151 if (tp->Rx_databuff[i]) {
5152 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5153 tp->RxDescArray + i);
5154 }
5155 }
5156 }
5157
5158 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5159 {
5160 desc->opts1 |= cpu_to_le32(RingEnd);
5161 }
5162
5163 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5164 {
5165 unsigned int i;
5166
5167 for (i = 0; i < NUM_RX_DESC; i++) {
5168 void *data;
5169
5170 if (tp->Rx_databuff[i])
5171 continue;
5172
5173 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5174 if (!data) {
5175 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5176 goto err_out;
5177 }
5178 tp->Rx_databuff[i] = data;
5179 }
5180
5181 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5182 return 0;
5183
5184 err_out:
5185 rtl8169_rx_clear(tp);
5186 return -ENOMEM;
5187 }
5188
5189 static int rtl8169_init_ring(struct net_device *dev)
5190 {
5191 struct rtl8169_private *tp = netdev_priv(dev);
5192
5193 rtl8169_init_ring_indexes(tp);
5194
5195 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5196 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5197
5198 return rtl8169_rx_fill(tp);
5199 }
5200
5201 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5202 struct TxDesc *desc)
5203 {
5204 unsigned int len = tx_skb->len;
5205
5206 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5207
5208 desc->opts1 = 0x00;
5209 desc->opts2 = 0x00;
5210 desc->addr = 0x00;
5211 tx_skb->len = 0;
5212 }
5213
5214 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5215 unsigned int n)
5216 {
5217 unsigned int i;
5218
5219 for (i = 0; i < n; i++) {
5220 unsigned int entry = (start + i) % NUM_TX_DESC;
5221 struct ring_info *tx_skb = tp->tx_skb + entry;
5222 unsigned int len = tx_skb->len;
5223
5224 if (len) {
5225 struct sk_buff *skb = tx_skb->skb;
5226
5227 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5228 tp->TxDescArray + entry);
5229 if (skb) {
5230 tp->dev->stats.tx_dropped++;
5231 dev_kfree_skb(skb);
5232 tx_skb->skb = NULL;
5233 }
5234 }
5235 }
5236 }
5237
5238 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5239 {
5240 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5241 tp->cur_tx = tp->dirty_tx = 0;
5242 netdev_reset_queue(tp->dev);
5243 }
5244
5245 static void rtl_reset_work(struct rtl8169_private *tp)
5246 {
5247 struct net_device *dev = tp->dev;
5248 int i;
5249
5250 napi_disable(&tp->napi);
5251 netif_stop_queue(dev);
5252 synchronize_sched();
5253
5254 rtl8169_hw_reset(tp);
5255
5256 for (i = 0; i < NUM_RX_DESC; i++)
5257 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5258
5259 rtl8169_tx_clear(tp);
5260 rtl8169_init_ring_indexes(tp);
5261
5262 napi_enable(&tp->napi);
5263 rtl_hw_start(dev);
5264 netif_wake_queue(dev);
5265 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5266 }
5267
5268 static void rtl8169_tx_timeout(struct net_device *dev)
5269 {
5270 struct rtl8169_private *tp = netdev_priv(dev);
5271
5272 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5273 }
5274
5275 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5276 u32 *opts)
5277 {
5278 struct skb_shared_info *info = skb_shinfo(skb);
5279 unsigned int cur_frag, entry;
5280 struct TxDesc * uninitialized_var(txd);
5281 struct device *d = &tp->pci_dev->dev;
5282
5283 entry = tp->cur_tx;
5284 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5285 const skb_frag_t *frag = info->frags + cur_frag;
5286 dma_addr_t mapping;
5287 u32 status, len;
5288 void *addr;
5289
5290 entry = (entry + 1) % NUM_TX_DESC;
5291
5292 txd = tp->TxDescArray + entry;
5293 len = skb_frag_size(frag);
5294 addr = skb_frag_address(frag);
5295 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5296 if (unlikely(dma_mapping_error(d, mapping))) {
5297 if (net_ratelimit())
5298 netif_err(tp, drv, tp->dev,
5299 "Failed to map TX fragments DMA!\n");
5300 goto err_out;
5301 }
5302
5303 /* Anti gcc 2.95.3 bugware (sic) */
5304 status = opts[0] | len |
5305 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5306
5307 txd->opts1 = cpu_to_le32(status);
5308 txd->opts2 = cpu_to_le32(opts[1]);
5309 txd->addr = cpu_to_le64(mapping);
5310
5311 tp->tx_skb[entry].len = len;
5312 }
5313
5314 if (cur_frag) {
5315 tp->tx_skb[entry].skb = skb;
5316 txd->opts1 |= cpu_to_le32(LastFrag);
5317 }
5318
5319 return cur_frag;
5320
5321 err_out:
5322 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5323 return -EIO;
5324 }
5325
5326 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5327 struct sk_buff *skb, u32 *opts)
5328 {
5329 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5330 u32 mss = skb_shinfo(skb)->gso_size;
5331 int offset = info->opts_offset;
5332
5333 if (mss) {
5334 opts[0] |= TD_LSO;
5335 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5336 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5337 const struct iphdr *ip = ip_hdr(skb);
5338
5339 if (ip->protocol == IPPROTO_TCP)
5340 opts[offset] |= info->checksum.tcp;
5341 else if (ip->protocol == IPPROTO_UDP)
5342 opts[offset] |= info->checksum.udp;
5343 else
5344 WARN_ON_ONCE(1);
5345 }
5346 }
5347
5348 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5349 struct net_device *dev)
5350 {
5351 struct rtl8169_private *tp = netdev_priv(dev);
5352 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5353 struct TxDesc *txd = tp->TxDescArray + entry;
5354 void __iomem *ioaddr = tp->mmio_addr;
5355 struct device *d = &tp->pci_dev->dev;
5356 dma_addr_t mapping;
5357 u32 status, len;
5358 u32 opts[2];
5359 int frags;
5360
5361 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5362 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5363 goto err_stop_0;
5364 }
5365
5366 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5367 goto err_stop_0;
5368
5369 len = skb_headlen(skb);
5370 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5371 if (unlikely(dma_mapping_error(d, mapping))) {
5372 if (net_ratelimit())
5373 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5374 goto err_dma_0;
5375 }
5376
5377 tp->tx_skb[entry].len = len;
5378 txd->addr = cpu_to_le64(mapping);
5379
5380 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5381 opts[0] = DescOwn;
5382
5383 rtl8169_tso_csum(tp, skb, opts);
5384
5385 frags = rtl8169_xmit_frags(tp, skb, opts);
5386 if (frags < 0)
5387 goto err_dma_1;
5388 else if (frags)
5389 opts[0] |= FirstFrag;
5390 else {
5391 opts[0] |= FirstFrag | LastFrag;
5392 tp->tx_skb[entry].skb = skb;
5393 }
5394
5395 txd->opts2 = cpu_to_le32(opts[1]);
5396
5397 netdev_sent_queue(dev, skb->len);
5398
5399 skb_tx_timestamp(skb);
5400
5401 wmb();
5402
5403 /* Anti gcc 2.95.3 bugware (sic) */
5404 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5405 txd->opts1 = cpu_to_le32(status);
5406
5407 tp->cur_tx += frags + 1;
5408
5409 wmb();
5410
5411 RTL_W8(TxPoll, NPQ);
5412
5413 mmiowb();
5414
5415 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5416 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5417 * not miss a ring update when it notices a stopped queue.
5418 */
5419 smp_wmb();
5420 netif_stop_queue(dev);
5421 /* Sync with rtl_tx:
5422 * - publish queue status and cur_tx ring index (write barrier)
5423 * - refresh dirty_tx ring index (read barrier).
5424 * May the current thread have a pessimistic view of the ring
5425 * status and forget to wake up queue, a racing rtl_tx thread
5426 * can't.
5427 */
5428 smp_mb();
5429 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5430 netif_wake_queue(dev);
5431 }
5432
5433 return NETDEV_TX_OK;
5434
5435 err_dma_1:
5436 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5437 err_dma_0:
5438 dev_kfree_skb(skb);
5439 dev->stats.tx_dropped++;
5440 return NETDEV_TX_OK;
5441
5442 err_stop_0:
5443 netif_stop_queue(dev);
5444 dev->stats.tx_dropped++;
5445 return NETDEV_TX_BUSY;
5446 }
5447
5448 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5449 {
5450 struct rtl8169_private *tp = netdev_priv(dev);
5451 struct pci_dev *pdev = tp->pci_dev;
5452 u16 pci_status, pci_cmd;
5453
5454 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5455 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5456
5457 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5458 pci_cmd, pci_status);
5459
5460 /*
5461 * The recovery sequence below admits a very elaborated explanation:
5462 * - it seems to work;
5463 * - I did not see what else could be done;
5464 * - it makes iop3xx happy.
5465 *
5466 * Feel free to adjust to your needs.
5467 */
5468 if (pdev->broken_parity_status)
5469 pci_cmd &= ~PCI_COMMAND_PARITY;
5470 else
5471 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5472
5473 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5474
5475 pci_write_config_word(pdev, PCI_STATUS,
5476 pci_status & (PCI_STATUS_DETECTED_PARITY |
5477 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5478 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5479
5480 /* The infamous DAC f*ckup only happens at boot time */
5481 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5482 void __iomem *ioaddr = tp->mmio_addr;
5483
5484 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5485 tp->cp_cmd &= ~PCIDAC;
5486 RTL_W16(CPlusCmd, tp->cp_cmd);
5487 dev->features &= ~NETIF_F_HIGHDMA;
5488 }
5489
5490 rtl8169_hw_reset(tp);
5491
5492 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5493 }
5494
5495 struct rtl_txc {
5496 int packets;
5497 int bytes;
5498 };
5499
5500 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5501 {
5502 struct rtl8169_stats *tx_stats = &tp->tx_stats;
5503 unsigned int dirty_tx, tx_left;
5504 struct rtl_txc txc = { 0, 0 };
5505
5506 dirty_tx = tp->dirty_tx;
5507 smp_rmb();
5508 tx_left = tp->cur_tx - dirty_tx;
5509
5510 while (tx_left > 0) {
5511 unsigned int entry = dirty_tx % NUM_TX_DESC;
5512 struct ring_info *tx_skb = tp->tx_skb + entry;
5513 u32 status;
5514
5515 rmb();
5516 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5517 if (status & DescOwn)
5518 break;
5519
5520 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5521 tp->TxDescArray + entry);
5522 if (status & LastFrag) {
5523 struct sk_buff *skb = tx_skb->skb;
5524
5525 txc.packets++;
5526 txc.bytes += skb->len;
5527 dev_kfree_skb(skb);
5528 tx_skb->skb = NULL;
5529 }
5530 dirty_tx++;
5531 tx_left--;
5532 }
5533
5534 u64_stats_update_begin(&tx_stats->syncp);
5535 tx_stats->packets += txc.packets;
5536 tx_stats->bytes += txc.bytes;
5537 u64_stats_update_end(&tx_stats->syncp);
5538
5539 netdev_completed_queue(dev, txc.packets, txc.bytes);
5540
5541 if (tp->dirty_tx != dirty_tx) {
5542 tp->dirty_tx = dirty_tx;
5543 /* Sync with rtl8169_start_xmit:
5544 * - publish dirty_tx ring index (write barrier)
5545 * - refresh cur_tx ring index and queue status (read barrier)
5546 * May the current thread miss the stopped queue condition,
5547 * a racing xmit thread can only have a right view of the
5548 * ring status.
5549 */
5550 smp_mb();
5551 if (netif_queue_stopped(dev) &&
5552 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5553 netif_wake_queue(dev);
5554 }
5555 /*
5556 * 8168 hack: TxPoll requests are lost when the Tx packets are
5557 * too close. Let's kick an extra TxPoll request when a burst
5558 * of start_xmit activity is detected (if it is not detected,
5559 * it is slow enough). -- FR
5560 */
5561 if (tp->cur_tx != dirty_tx) {
5562 void __iomem *ioaddr = tp->mmio_addr;
5563
5564 RTL_W8(TxPoll, NPQ);
5565 }
5566 }
5567 }
5568
5569 static inline int rtl8169_fragmented_frame(u32 status)
5570 {
5571 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5572 }
5573
5574 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5575 {
5576 u32 status = opts1 & RxProtoMask;
5577
5578 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5579 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5580 skb->ip_summed = CHECKSUM_UNNECESSARY;
5581 else
5582 skb_checksum_none_assert(skb);
5583 }
5584
5585 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5586 struct rtl8169_private *tp,
5587 int pkt_size,
5588 dma_addr_t addr)
5589 {
5590 struct sk_buff *skb;
5591 struct device *d = &tp->pci_dev->dev;
5592
5593 data = rtl8169_align(data);
5594 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5595 prefetch(data);
5596 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5597 if (skb)
5598 memcpy(skb->data, data, pkt_size);
5599 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5600
5601 return skb;
5602 }
5603
5604 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5605 {
5606 unsigned int cur_rx, rx_left;
5607 unsigned int count;
5608
5609 cur_rx = tp->cur_rx;
5610 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5611 rx_left = min(rx_left, budget);
5612
5613 for (; rx_left > 0; rx_left--, cur_rx++) {
5614 unsigned int entry = cur_rx % NUM_RX_DESC;
5615 struct RxDesc *desc = tp->RxDescArray + entry;
5616 u32 status;
5617
5618 rmb();
5619 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5620
5621 if (status & DescOwn)
5622 break;
5623 if (unlikely(status & RxRES)) {
5624 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5625 status);
5626 dev->stats.rx_errors++;
5627 if (status & (RxRWT | RxRUNT))
5628 dev->stats.rx_length_errors++;
5629 if (status & RxCRC)
5630 dev->stats.rx_crc_errors++;
5631 if (status & RxFOVF) {
5632 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5633 dev->stats.rx_fifo_errors++;
5634 }
5635 if ((status & (RxRUNT | RxCRC)) &&
5636 !(status & (RxRWT | RxFOVF)) &&
5637 (dev->features & NETIF_F_RXALL))
5638 goto process_pkt;
5639
5640 rtl8169_mark_to_asic(desc, rx_buf_sz);
5641 } else {
5642 struct sk_buff *skb;
5643 dma_addr_t addr;
5644 int pkt_size;
5645
5646 process_pkt:
5647 addr = le64_to_cpu(desc->addr);
5648 if (likely(!(dev->features & NETIF_F_RXFCS)))
5649 pkt_size = (status & 0x00003fff) - 4;
5650 else
5651 pkt_size = status & 0x00003fff;
5652
5653 /*
5654 * The driver does not support incoming fragmented
5655 * frames. They are seen as a symptom of over-mtu
5656 * sized frames.
5657 */
5658 if (unlikely(rtl8169_fragmented_frame(status))) {
5659 dev->stats.rx_dropped++;
5660 dev->stats.rx_length_errors++;
5661 rtl8169_mark_to_asic(desc, rx_buf_sz);
5662 continue;
5663 }
5664
5665 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5666 tp, pkt_size, addr);
5667 rtl8169_mark_to_asic(desc, rx_buf_sz);
5668 if (!skb) {
5669 dev->stats.rx_dropped++;
5670 continue;
5671 }
5672
5673 rtl8169_rx_csum(skb, status);
5674 skb_put(skb, pkt_size);
5675 skb->protocol = eth_type_trans(skb, dev);
5676
5677 rtl8169_rx_vlan_tag(desc, skb);
5678
5679 napi_gro_receive(&tp->napi, skb);
5680
5681 u64_stats_update_begin(&tp->rx_stats.syncp);
5682 tp->rx_stats.packets++;
5683 tp->rx_stats.bytes += pkt_size;
5684 u64_stats_update_end(&tp->rx_stats.syncp);
5685 }
5686
5687 /* Work around for AMD plateform. */
5688 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5689 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5690 desc->opts2 = 0;
5691 cur_rx++;
5692 }
5693 }
5694
5695 count = cur_rx - tp->cur_rx;
5696 tp->cur_rx = cur_rx;
5697
5698 tp->dirty_rx += count;
5699
5700 return count;
5701 }
5702
5703 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5704 {
5705 struct net_device *dev = dev_instance;
5706 struct rtl8169_private *tp = netdev_priv(dev);
5707 int handled = 0;
5708 u16 status;
5709
5710 status = rtl_get_events(tp);
5711 if (status && status != 0xffff) {
5712 status &= RTL_EVENT_NAPI | tp->event_slow;
5713 if (status) {
5714 handled = 1;
5715
5716 rtl_irq_disable(tp);
5717 napi_schedule(&tp->napi);
5718 }
5719 }
5720 return IRQ_RETVAL(handled);
5721 }
5722
5723 /*
5724 * Workqueue context.
5725 */
5726 static void rtl_slow_event_work(struct rtl8169_private *tp)
5727 {
5728 struct net_device *dev = tp->dev;
5729 u16 status;
5730
5731 status = rtl_get_events(tp) & tp->event_slow;
5732 rtl_ack_events(tp, status);
5733
5734 if (unlikely(status & RxFIFOOver)) {
5735 switch (tp->mac_version) {
5736 /* Work around for rx fifo overflow */
5737 case RTL_GIGA_MAC_VER_11:
5738 netif_stop_queue(dev);
5739 /* XXX - Hack alert. See rtl_task(). */
5740 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5741 default:
5742 break;
5743 }
5744 }
5745
5746 if (unlikely(status & SYSErr))
5747 rtl8169_pcierr_interrupt(dev);
5748
5749 if (status & LinkChg)
5750 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5751
5752 napi_disable(&tp->napi);
5753 rtl_irq_disable(tp);
5754
5755 napi_enable(&tp->napi);
5756 napi_schedule(&tp->napi);
5757 }
5758
5759 static void rtl_task(struct work_struct *work)
5760 {
5761 static const struct {
5762 int bitnr;
5763 void (*action)(struct rtl8169_private *);
5764 } rtl_work[] = {
5765 /* XXX - keep rtl_slow_event_work() as first element. */
5766 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5767 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5768 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5769 };
5770 struct rtl8169_private *tp =
5771 container_of(work, struct rtl8169_private, wk.work);
5772 struct net_device *dev = tp->dev;
5773 int i;
5774
5775 rtl_lock_work(tp);
5776
5777 if (!netif_running(dev) ||
5778 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5779 goto out_unlock;
5780
5781 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5782 bool pending;
5783
5784 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5785 if (pending)
5786 rtl_work[i].action(tp);
5787 }
5788
5789 out_unlock:
5790 rtl_unlock_work(tp);
5791 }
5792
5793 static int rtl8169_poll(struct napi_struct *napi, int budget)
5794 {
5795 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5796 struct net_device *dev = tp->dev;
5797 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5798 int work_done= 0;
5799 u16 status;
5800
5801 status = rtl_get_events(tp);
5802 rtl_ack_events(tp, status & ~tp->event_slow);
5803
5804 if (status & RTL_EVENT_NAPI_RX)
5805 work_done = rtl_rx(dev, tp, (u32) budget);
5806
5807 if (status & RTL_EVENT_NAPI_TX)
5808 rtl_tx(dev, tp);
5809
5810 if (status & tp->event_slow) {
5811 enable_mask &= ~tp->event_slow;
5812
5813 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5814 }
5815
5816 if (work_done < budget) {
5817 napi_complete(napi);
5818
5819 rtl_irq_enable(tp, enable_mask);
5820 mmiowb();
5821 }
5822
5823 return work_done;
5824 }
5825
5826 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5827 {
5828 struct rtl8169_private *tp = netdev_priv(dev);
5829
5830 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5831 return;
5832
5833 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5834 RTL_W32(RxMissed, 0);
5835 }
5836
5837 static void rtl8169_down(struct net_device *dev)
5838 {
5839 struct rtl8169_private *tp = netdev_priv(dev);
5840 void __iomem *ioaddr = tp->mmio_addr;
5841
5842 del_timer_sync(&tp->timer);
5843
5844 napi_disable(&tp->napi);
5845 netif_stop_queue(dev);
5846
5847 rtl8169_hw_reset(tp);
5848 /*
5849 * At this point device interrupts can not be enabled in any function,
5850 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5851 * and napi is disabled (rtl8169_poll).
5852 */
5853 rtl8169_rx_missed(dev, ioaddr);
5854
5855 /* Give a racing hard_start_xmit a few cycles to complete. */
5856 synchronize_sched();
5857
5858 rtl8169_tx_clear(tp);
5859
5860 rtl8169_rx_clear(tp);
5861
5862 rtl_pll_power_down(tp);
5863 }
5864
5865 static int rtl8169_close(struct net_device *dev)
5866 {
5867 struct rtl8169_private *tp = netdev_priv(dev);
5868 struct pci_dev *pdev = tp->pci_dev;
5869
5870 pm_runtime_get_sync(&pdev->dev);
5871
5872 /* Update counters before going down */
5873 rtl8169_update_counters(dev);
5874
5875 rtl_lock_work(tp);
5876 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5877
5878 rtl8169_down(dev);
5879 rtl_unlock_work(tp);
5880
5881 free_irq(pdev->irq, dev);
5882
5883 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5884 tp->RxPhyAddr);
5885 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5886 tp->TxPhyAddr);
5887 tp->TxDescArray = NULL;
5888 tp->RxDescArray = NULL;
5889
5890 pm_runtime_put_sync(&pdev->dev);
5891
5892 return 0;
5893 }
5894
5895 #ifdef CONFIG_NET_POLL_CONTROLLER
5896 static void rtl8169_netpoll(struct net_device *dev)
5897 {
5898 struct rtl8169_private *tp = netdev_priv(dev);
5899
5900 rtl8169_interrupt(tp->pci_dev->irq, dev);
5901 }
5902 #endif
5903
5904 static int rtl_open(struct net_device *dev)
5905 {
5906 struct rtl8169_private *tp = netdev_priv(dev);
5907 void __iomem *ioaddr = tp->mmio_addr;
5908 struct pci_dev *pdev = tp->pci_dev;
5909 int retval = -ENOMEM;
5910
5911 pm_runtime_get_sync(&pdev->dev);
5912
5913 /*
5914 * Rx and Tx desscriptors needs 256 bytes alignment.
5915 * dma_alloc_coherent provides more.
5916 */
5917 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5918 &tp->TxPhyAddr, GFP_KERNEL);
5919 if (!tp->TxDescArray)
5920 goto err_pm_runtime_put;
5921
5922 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5923 &tp->RxPhyAddr, GFP_KERNEL);
5924 if (!tp->RxDescArray)
5925 goto err_free_tx_0;
5926
5927 retval = rtl8169_init_ring(dev);
5928 if (retval < 0)
5929 goto err_free_rx_1;
5930
5931 INIT_WORK(&tp->wk.work, rtl_task);
5932
5933 smp_mb();
5934
5935 rtl_request_firmware(tp);
5936
5937 retval = request_irq(pdev->irq, rtl8169_interrupt,
5938 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5939 dev->name, dev);
5940 if (retval < 0)
5941 goto err_release_fw_2;
5942
5943 rtl_lock_work(tp);
5944
5945 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5946
5947 napi_enable(&tp->napi);
5948
5949 rtl8169_init_phy(dev, tp);
5950
5951 __rtl8169_set_features(dev, dev->features);
5952
5953 rtl_pll_power_up(tp);
5954
5955 rtl_hw_start(dev);
5956
5957 netif_start_queue(dev);
5958
5959 rtl_unlock_work(tp);
5960
5961 tp->saved_wolopts = 0;
5962 pm_runtime_put_noidle(&pdev->dev);
5963
5964 rtl8169_check_link_status(dev, tp, ioaddr);
5965 out:
5966 return retval;
5967
5968 err_release_fw_2:
5969 rtl_release_firmware(tp);
5970 rtl8169_rx_clear(tp);
5971 err_free_rx_1:
5972 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5973 tp->RxPhyAddr);
5974 tp->RxDescArray = NULL;
5975 err_free_tx_0:
5976 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5977 tp->TxPhyAddr);
5978 tp->TxDescArray = NULL;
5979 err_pm_runtime_put:
5980 pm_runtime_put_noidle(&pdev->dev);
5981 goto out;
5982 }
5983
5984 static struct rtnl_link_stats64 *
5985 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5986 {
5987 struct rtl8169_private *tp = netdev_priv(dev);
5988 void __iomem *ioaddr = tp->mmio_addr;
5989 unsigned int start;
5990
5991 if (netif_running(dev))
5992 rtl8169_rx_missed(dev, ioaddr);
5993
5994 do {
5995 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5996 stats->rx_packets = tp->rx_stats.packets;
5997 stats->rx_bytes = tp->rx_stats.bytes;
5998 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5999
6000
6001 do {
6002 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6003 stats->tx_packets = tp->tx_stats.packets;
6004 stats->tx_bytes = tp->tx_stats.bytes;
6005 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6006
6007 stats->rx_dropped = dev->stats.rx_dropped;
6008 stats->tx_dropped = dev->stats.tx_dropped;
6009 stats->rx_length_errors = dev->stats.rx_length_errors;
6010 stats->rx_errors = dev->stats.rx_errors;
6011 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6012 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6013 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6014
6015 return stats;
6016 }
6017
6018 static void rtl8169_net_suspend(struct net_device *dev)
6019 {
6020 struct rtl8169_private *tp = netdev_priv(dev);
6021
6022 if (!netif_running(dev))
6023 return;
6024
6025 netif_device_detach(dev);
6026 netif_stop_queue(dev);
6027
6028 rtl_lock_work(tp);
6029 napi_disable(&tp->napi);
6030 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6031 rtl_unlock_work(tp);
6032
6033 rtl_pll_power_down(tp);
6034 }
6035
6036 #ifdef CONFIG_PM
6037
6038 static int rtl8169_suspend(struct device *device)
6039 {
6040 struct pci_dev *pdev = to_pci_dev(device);
6041 struct net_device *dev = pci_get_drvdata(pdev);
6042
6043 rtl8169_net_suspend(dev);
6044
6045 return 0;
6046 }
6047
6048 static void __rtl8169_resume(struct net_device *dev)
6049 {
6050 struct rtl8169_private *tp = netdev_priv(dev);
6051
6052 netif_device_attach(dev);
6053
6054 rtl_pll_power_up(tp);
6055
6056 rtl_lock_work(tp);
6057 napi_enable(&tp->napi);
6058 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6059 rtl_unlock_work(tp);
6060
6061 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6062 }
6063
6064 static int rtl8169_resume(struct device *device)
6065 {
6066 struct pci_dev *pdev = to_pci_dev(device);
6067 struct net_device *dev = pci_get_drvdata(pdev);
6068 struct rtl8169_private *tp = netdev_priv(dev);
6069
6070 rtl8169_init_phy(dev, tp);
6071
6072 if (netif_running(dev))
6073 __rtl8169_resume(dev);
6074
6075 return 0;
6076 }
6077
6078 static int rtl8169_runtime_suspend(struct device *device)
6079 {
6080 struct pci_dev *pdev = to_pci_dev(device);
6081 struct net_device *dev = pci_get_drvdata(pdev);
6082 struct rtl8169_private *tp = netdev_priv(dev);
6083
6084 if (!tp->TxDescArray)
6085 return 0;
6086
6087 rtl_lock_work(tp);
6088 tp->saved_wolopts = __rtl8169_get_wol(tp);
6089 __rtl8169_set_wol(tp, WAKE_ANY);
6090 rtl_unlock_work(tp);
6091
6092 rtl8169_net_suspend(dev);
6093
6094 return 0;
6095 }
6096
6097 static int rtl8169_runtime_resume(struct device *device)
6098 {
6099 struct pci_dev *pdev = to_pci_dev(device);
6100 struct net_device *dev = pci_get_drvdata(pdev);
6101 struct rtl8169_private *tp = netdev_priv(dev);
6102
6103 if (!tp->TxDescArray)
6104 return 0;
6105
6106 rtl_lock_work(tp);
6107 __rtl8169_set_wol(tp, tp->saved_wolopts);
6108 tp->saved_wolopts = 0;
6109 rtl_unlock_work(tp);
6110
6111 rtl8169_init_phy(dev, tp);
6112
6113 __rtl8169_resume(dev);
6114
6115 return 0;
6116 }
6117
6118 static int rtl8169_runtime_idle(struct device *device)
6119 {
6120 struct pci_dev *pdev = to_pci_dev(device);
6121 struct net_device *dev = pci_get_drvdata(pdev);
6122 struct rtl8169_private *tp = netdev_priv(dev);
6123
6124 return tp->TxDescArray ? -EBUSY : 0;
6125 }
6126
6127 static const struct dev_pm_ops rtl8169_pm_ops = {
6128 .suspend = rtl8169_suspend,
6129 .resume = rtl8169_resume,
6130 .freeze = rtl8169_suspend,
6131 .thaw = rtl8169_resume,
6132 .poweroff = rtl8169_suspend,
6133 .restore = rtl8169_resume,
6134 .runtime_suspend = rtl8169_runtime_suspend,
6135 .runtime_resume = rtl8169_runtime_resume,
6136 .runtime_idle = rtl8169_runtime_idle,
6137 };
6138
6139 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6140
6141 #else /* !CONFIG_PM */
6142
6143 #define RTL8169_PM_OPS NULL
6144
6145 #endif /* !CONFIG_PM */
6146
6147 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6148 {
6149 void __iomem *ioaddr = tp->mmio_addr;
6150
6151 /* WoL fails with 8168b when the receiver is disabled. */
6152 switch (tp->mac_version) {
6153 case RTL_GIGA_MAC_VER_11:
6154 case RTL_GIGA_MAC_VER_12:
6155 case RTL_GIGA_MAC_VER_17:
6156 pci_clear_master(tp->pci_dev);
6157
6158 RTL_W8(ChipCmd, CmdRxEnb);
6159 /* PCI commit */
6160 RTL_R8(ChipCmd);
6161 break;
6162 default:
6163 break;
6164 }
6165 }
6166
6167 static void rtl_shutdown(struct pci_dev *pdev)
6168 {
6169 struct net_device *dev = pci_get_drvdata(pdev);
6170 struct rtl8169_private *tp = netdev_priv(dev);
6171 struct device *d = &pdev->dev;
6172
6173 pm_runtime_get_sync(d);
6174
6175 rtl8169_net_suspend(dev);
6176
6177 /* Restore original MAC address */
6178 rtl_rar_set(tp, dev->perm_addr);
6179
6180 rtl8169_hw_reset(tp);
6181
6182 if (system_state == SYSTEM_POWER_OFF) {
6183 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6184 rtl_wol_suspend_quirk(tp);
6185 rtl_wol_shutdown_quirk(tp);
6186 }
6187
6188 pci_wake_from_d3(pdev, true);
6189 pci_set_power_state(pdev, PCI_D3hot);
6190 }
6191
6192 pm_runtime_put_noidle(d);
6193 }
6194
6195 static void __devexit rtl_remove_one(struct pci_dev *pdev)
6196 {
6197 struct net_device *dev = pci_get_drvdata(pdev);
6198 struct rtl8169_private *tp = netdev_priv(dev);
6199
6200 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6201 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6202 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6203 rtl8168_driver_stop(tp);
6204 }
6205
6206 cancel_work_sync(&tp->wk.work);
6207
6208 unregister_netdev(dev);
6209
6210 rtl_release_firmware(tp);
6211
6212 if (pci_dev_run_wake(pdev))
6213 pm_runtime_get_noresume(&pdev->dev);
6214
6215 /* restore original MAC address */
6216 rtl_rar_set(tp, dev->perm_addr);
6217
6218 rtl_disable_msi(pdev, tp);
6219 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6220 pci_set_drvdata(pdev, NULL);
6221 }
6222
6223 static const struct net_device_ops rtl_netdev_ops = {
6224 .ndo_open = rtl_open,
6225 .ndo_stop = rtl8169_close,
6226 .ndo_get_stats64 = rtl8169_get_stats64,
6227 .ndo_start_xmit = rtl8169_start_xmit,
6228 .ndo_tx_timeout = rtl8169_tx_timeout,
6229 .ndo_validate_addr = eth_validate_addr,
6230 .ndo_change_mtu = rtl8169_change_mtu,
6231 .ndo_fix_features = rtl8169_fix_features,
6232 .ndo_set_features = rtl8169_set_features,
6233 .ndo_set_mac_address = rtl_set_mac_address,
6234 .ndo_do_ioctl = rtl8169_ioctl,
6235 .ndo_set_rx_mode = rtl_set_rx_mode,
6236 #ifdef CONFIG_NET_POLL_CONTROLLER
6237 .ndo_poll_controller = rtl8169_netpoll,
6238 #endif
6239
6240 };
6241
6242 static const struct rtl_cfg_info {
6243 void (*hw_start)(struct net_device *);
6244 unsigned int region;
6245 unsigned int align;
6246 u16 event_slow;
6247 unsigned features;
6248 u8 default_ver;
6249 } rtl_cfg_infos [] = {
6250 [RTL_CFG_0] = {
6251 .hw_start = rtl_hw_start_8169,
6252 .region = 1,
6253 .align = 0,
6254 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6255 .features = RTL_FEATURE_GMII,
6256 .default_ver = RTL_GIGA_MAC_VER_01,
6257 },
6258 [RTL_CFG_1] = {
6259 .hw_start = rtl_hw_start_8168,
6260 .region = 2,
6261 .align = 8,
6262 .event_slow = SYSErr | LinkChg | RxOverflow,
6263 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6264 .default_ver = RTL_GIGA_MAC_VER_11,
6265 },
6266 [RTL_CFG_2] = {
6267 .hw_start = rtl_hw_start_8101,
6268 .region = 2,
6269 .align = 8,
6270 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6271 PCSTimeout,
6272 .features = RTL_FEATURE_MSI,
6273 .default_ver = RTL_GIGA_MAC_VER_13,
6274 }
6275 };
6276
6277 /* Cfg9346_Unlock assumed. */
6278 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6279 const struct rtl_cfg_info *cfg)
6280 {
6281 void __iomem *ioaddr = tp->mmio_addr;
6282 unsigned msi = 0;
6283 u8 cfg2;
6284
6285 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6286 if (cfg->features & RTL_FEATURE_MSI) {
6287 if (pci_enable_msi(tp->pci_dev)) {
6288 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6289 } else {
6290 cfg2 |= MSIEnable;
6291 msi = RTL_FEATURE_MSI;
6292 }
6293 }
6294 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6295 RTL_W8(Config2, cfg2);
6296 return msi;
6297 }
6298
6299 static int __devinit
6300 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6301 {
6302 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6303 const unsigned int region = cfg->region;
6304 struct rtl8169_private *tp;
6305 struct mii_if_info *mii;
6306 struct net_device *dev;
6307 void __iomem *ioaddr;
6308 int chipset, i;
6309 int rc;
6310
6311 if (netif_msg_drv(&debug)) {
6312 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6313 MODULENAME, RTL8169_VERSION);
6314 }
6315
6316 dev = alloc_etherdev(sizeof (*tp));
6317 if (!dev) {
6318 rc = -ENOMEM;
6319 goto out;
6320 }
6321
6322 SET_NETDEV_DEV(dev, &pdev->dev);
6323 dev->netdev_ops = &rtl_netdev_ops;
6324 tp = netdev_priv(dev);
6325 tp->dev = dev;
6326 tp->pci_dev = pdev;
6327 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6328
6329 mii = &tp->mii;
6330 mii->dev = dev;
6331 mii->mdio_read = rtl_mdio_read;
6332 mii->mdio_write = rtl_mdio_write;
6333 mii->phy_id_mask = 0x1f;
6334 mii->reg_num_mask = 0x1f;
6335 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6336
6337 /* disable ASPM completely as that cause random device stop working
6338 * problems as well as full system hangs for some PCIe devices users */
6339 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6340 PCIE_LINK_STATE_CLKPM);
6341
6342 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6343 rc = pci_enable_device(pdev);
6344 if (rc < 0) {
6345 netif_err(tp, probe, dev, "enable failure\n");
6346 goto err_out_free_dev_1;
6347 }
6348
6349 if (pci_set_mwi(pdev) < 0)
6350 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6351
6352 /* make sure PCI base addr 1 is MMIO */
6353 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6354 netif_err(tp, probe, dev,
6355 "region #%d not an MMIO resource, aborting\n",
6356 region);
6357 rc = -ENODEV;
6358 goto err_out_mwi_2;
6359 }
6360
6361 /* check for weird/broken PCI region reporting */
6362 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6363 netif_err(tp, probe, dev,
6364 "Invalid PCI region size(s), aborting\n");
6365 rc = -ENODEV;
6366 goto err_out_mwi_2;
6367 }
6368
6369 rc = pci_request_regions(pdev, MODULENAME);
6370 if (rc < 0) {
6371 netif_err(tp, probe, dev, "could not request regions\n");
6372 goto err_out_mwi_2;
6373 }
6374
6375 tp->cp_cmd = RxChkSum;
6376
6377 if ((sizeof(dma_addr_t) > 4) &&
6378 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6379 tp->cp_cmd |= PCIDAC;
6380 dev->features |= NETIF_F_HIGHDMA;
6381 } else {
6382 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6383 if (rc < 0) {
6384 netif_err(tp, probe, dev, "DMA configuration failed\n");
6385 goto err_out_free_res_3;
6386 }
6387 }
6388
6389 /* ioremap MMIO region */
6390 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6391 if (!ioaddr) {
6392 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6393 rc = -EIO;
6394 goto err_out_free_res_3;
6395 }
6396 tp->mmio_addr = ioaddr;
6397
6398 if (!pci_is_pcie(pdev))
6399 netif_info(tp, probe, dev, "not PCI Express\n");
6400
6401 /* Identify chip attached to board */
6402 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6403
6404 rtl_init_rxcfg(tp);
6405
6406 rtl_irq_disable(tp);
6407
6408 rtl_hw_reset(tp);
6409
6410 rtl_ack_events(tp, 0xffff);
6411
6412 pci_set_master(pdev);
6413
6414 /*
6415 * Pretend we are using VLANs; This bypasses a nasty bug where
6416 * Interrupts stop flowing on high load on 8110SCd controllers.
6417 */
6418 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6419 tp->cp_cmd |= RxVlan;
6420
6421 rtl_init_mdio_ops(tp);
6422 rtl_init_pll_power_ops(tp);
6423 rtl_init_jumbo_ops(tp);
6424 rtl_init_csi_ops(tp);
6425
6426 rtl8169_print_mac_version(tp);
6427
6428 chipset = tp->mac_version;
6429 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6430
6431 RTL_W8(Cfg9346, Cfg9346_Unlock);
6432 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6433 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6434 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6435 tp->features |= RTL_FEATURE_WOL;
6436 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6437 tp->features |= RTL_FEATURE_WOL;
6438 tp->features |= rtl_try_msi(tp, cfg);
6439 RTL_W8(Cfg9346, Cfg9346_Lock);
6440
6441 if (rtl_tbi_enabled(tp)) {
6442 tp->set_speed = rtl8169_set_speed_tbi;
6443 tp->get_settings = rtl8169_gset_tbi;
6444 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6445 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6446 tp->link_ok = rtl8169_tbi_link_ok;
6447 tp->do_ioctl = rtl_tbi_ioctl;
6448 } else {
6449 tp->set_speed = rtl8169_set_speed_xmii;
6450 tp->get_settings = rtl8169_gset_xmii;
6451 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6452 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6453 tp->link_ok = rtl8169_xmii_link_ok;
6454 tp->do_ioctl = rtl_xmii_ioctl;
6455 }
6456
6457 mutex_init(&tp->wk.mutex);
6458
6459 /* Get MAC address */
6460 for (i = 0; i < ETH_ALEN; i++)
6461 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6462 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6463
6464 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6465 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6466
6467 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6468
6469 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6470 * properly for all devices */
6471 dev->features |= NETIF_F_RXCSUM |
6472 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6473
6474 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6475 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6476 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6477 NETIF_F_HIGHDMA;
6478
6479 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6480 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6481 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6482
6483 dev->hw_features |= NETIF_F_RXALL;
6484 dev->hw_features |= NETIF_F_RXFCS;
6485
6486 tp->hw_start = cfg->hw_start;
6487 tp->event_slow = cfg->event_slow;
6488
6489 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6490 ~(RxBOVF | RxFOVF) : ~0;
6491
6492 init_timer(&tp->timer);
6493 tp->timer.data = (unsigned long) dev;
6494 tp->timer.function = rtl8169_phy_timer;
6495
6496 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6497
6498 rc = register_netdev(dev);
6499 if (rc < 0)
6500 goto err_out_msi_4;
6501
6502 pci_set_drvdata(pdev, dev);
6503
6504 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6505 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6506 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6507 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6508 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6509 "tx checksumming: %s]\n",
6510 rtl_chip_infos[chipset].jumbo_max,
6511 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6512 }
6513
6514 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6515 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6516 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6517 rtl8168_driver_start(tp);
6518 }
6519
6520 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6521
6522 if (pci_dev_run_wake(pdev))
6523 pm_runtime_put_noidle(&pdev->dev);
6524
6525 netif_carrier_off(dev);
6526
6527 out:
6528 return rc;
6529
6530 err_out_msi_4:
6531 rtl_disable_msi(pdev, tp);
6532 iounmap(ioaddr);
6533 err_out_free_res_3:
6534 pci_release_regions(pdev);
6535 err_out_mwi_2:
6536 pci_clear_mwi(pdev);
6537 pci_disable_device(pdev);
6538 err_out_free_dev_1:
6539 free_netdev(dev);
6540 goto out;
6541 }
6542
6543 static struct pci_driver rtl8169_pci_driver = {
6544 .name = MODULENAME,
6545 .id_table = rtl8169_pci_tbl,
6546 .probe = rtl_init_one,
6547 .remove = __devexit_p(rtl_remove_one),
6548 .shutdown = rtl_shutdown,
6549 .driver.pm = RTL8169_PM_OPS,
6550 };
6551
6552 static int __init rtl8169_init_module(void)
6553 {
6554 return pci_register_driver(&rtl8169_pci_driver);
6555 }
6556
6557 static void __exit rtl8169_cleanup_module(void)
6558 {
6559 pci_unregister_driver(&rtl8169_pci_driver);
6560 }
6561
6562 module_init(rtl8169_init_module);
6563 module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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