2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
61 #define assert(expr) \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit
= 32;
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
110 RTL_GIGA_MAC_VER_01
= 0,
158 RTL_GIGA_MAC_NONE
= 0xff,
161 enum rtl_tx_desc_version
{
166 #define JUMBO_1K ETH_DATA_LEN
167 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
168 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
169 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
170 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
172 #define _R(NAME,TD,FW,SZ,B) { \
180 static const struct {
182 enum rtl_tx_desc_version txd_version
;
186 } rtl_chip_infos
[] = {
188 [RTL_GIGA_MAC_VER_01
] =
189 _R("RTL8169", RTL_TD_0
, NULL
, JUMBO_7K
, true),
190 [RTL_GIGA_MAC_VER_02
] =
191 _R("RTL8169s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
192 [RTL_GIGA_MAC_VER_03
] =
193 _R("RTL8110s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
194 [RTL_GIGA_MAC_VER_04
] =
195 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
, JUMBO_7K
, true),
196 [RTL_GIGA_MAC_VER_05
] =
197 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
198 [RTL_GIGA_MAC_VER_06
] =
199 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
201 [RTL_GIGA_MAC_VER_07
] =
202 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
203 [RTL_GIGA_MAC_VER_08
] =
204 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
205 [RTL_GIGA_MAC_VER_09
] =
206 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
207 [RTL_GIGA_MAC_VER_10
] =
208 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
209 [RTL_GIGA_MAC_VER_11
] =
210 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
211 [RTL_GIGA_MAC_VER_12
] =
212 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
213 [RTL_GIGA_MAC_VER_13
] =
214 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
215 [RTL_GIGA_MAC_VER_14
] =
216 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
217 [RTL_GIGA_MAC_VER_15
] =
218 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
219 [RTL_GIGA_MAC_VER_16
] =
220 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
221 [RTL_GIGA_MAC_VER_17
] =
222 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
223 [RTL_GIGA_MAC_VER_18
] =
224 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
225 [RTL_GIGA_MAC_VER_19
] =
226 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
227 [RTL_GIGA_MAC_VER_20
] =
228 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
229 [RTL_GIGA_MAC_VER_21
] =
230 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
231 [RTL_GIGA_MAC_VER_22
] =
232 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
233 [RTL_GIGA_MAC_VER_23
] =
234 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
235 [RTL_GIGA_MAC_VER_24
] =
236 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
237 [RTL_GIGA_MAC_VER_25
] =
238 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
,
240 [RTL_GIGA_MAC_VER_26
] =
241 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
,
243 [RTL_GIGA_MAC_VER_27
] =
244 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
245 [RTL_GIGA_MAC_VER_28
] =
246 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
247 [RTL_GIGA_MAC_VER_29
] =
248 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
250 [RTL_GIGA_MAC_VER_30
] =
251 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
253 [RTL_GIGA_MAC_VER_31
] =
254 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
255 [RTL_GIGA_MAC_VER_32
] =
256 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
,
258 [RTL_GIGA_MAC_VER_33
] =
259 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
,
261 [RTL_GIGA_MAC_VER_34
] =
262 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
,
264 [RTL_GIGA_MAC_VER_35
] =
265 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_1
,
267 [RTL_GIGA_MAC_VER_36
] =
268 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_2
,
270 [RTL_GIGA_MAC_VER_37
] =
271 _R("RTL8402", RTL_TD_1
, FIRMWARE_8402_1
,
273 [RTL_GIGA_MAC_VER_38
] =
274 _R("RTL8411", RTL_TD_1
, FIRMWARE_8411_1
,
276 [RTL_GIGA_MAC_VER_39
] =
277 _R("RTL8106e", RTL_TD_1
, FIRMWARE_8106E_1
,
279 [RTL_GIGA_MAC_VER_40
] =
280 _R("RTL8168g/8111g", RTL_TD_1
, FIRMWARE_8168G_2
,
282 [RTL_GIGA_MAC_VER_41
] =
283 _R("RTL8168g/8111g", RTL_TD_1
, NULL
, JUMBO_9K
, false),
284 [RTL_GIGA_MAC_VER_42
] =
285 _R("RTL8168g/8111g", RTL_TD_1
, FIRMWARE_8168G_3
,
287 [RTL_GIGA_MAC_VER_43
] =
288 _R("RTL8106e", RTL_TD_1
, FIRMWARE_8106E_2
,
290 [RTL_GIGA_MAC_VER_44
] =
291 _R("RTL8411", RTL_TD_1
, FIRMWARE_8411_2
,
293 [RTL_GIGA_MAC_VER_45
] =
294 _R("RTL8168h/8111h", RTL_TD_1
, FIRMWARE_8168H_1
,
296 [RTL_GIGA_MAC_VER_46
] =
297 _R("RTL8168h/8111h", RTL_TD_1
, FIRMWARE_8168H_2
,
299 [RTL_GIGA_MAC_VER_47
] =
300 _R("RTL8107e", RTL_TD_1
, FIRMWARE_8107E_1
,
302 [RTL_GIGA_MAC_VER_48
] =
303 _R("RTL8107e", RTL_TD_1
, FIRMWARE_8107E_2
,
314 static const struct pci_device_id rtl8169_pci_tbl
[] = {
315 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
316 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
317 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
318 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
319 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
320 { PCI_VENDOR_ID_DLINK
, 0x4300,
321 PCI_VENDOR_ID_DLINK
, 0x4b10, 0, 0, RTL_CFG_1
},
322 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
323 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
324 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
325 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
326 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
327 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
329 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
333 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
335 static int rx_buf_sz
= 16383;
342 MAC0
= 0, /* Ethernet hardware address. */
344 MAR0
= 8, /* Multicast filter. */
345 CounterAddrLow
= 0x10,
346 CounterAddrHigh
= 0x14,
347 TxDescStartAddrLow
= 0x20,
348 TxDescStartAddrHigh
= 0x24,
349 TxHDescStartAddrLow
= 0x28,
350 TxHDescStartAddrHigh
= 0x2c,
359 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
360 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
363 #define RX128_INT_EN (1 << 15) /* 8111c and later */
364 #define RX_MULTI_EN (1 << 14) /* 8111c only */
365 #define RXCFG_FIFO_SHIFT 13
366 /* No threshold before first PCI xfer */
367 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
368 #define RX_EARLY_OFF (1 << 11)
369 #define RXCFG_DMA_SHIFT 8
370 /* Unlimited maximum PCI burst. */
371 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
378 #define PME_SIGNAL (1 << 5) /* 8168c and later */
389 RxDescAddrLow
= 0xe4,
390 RxDescAddrHigh
= 0xe8,
391 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
393 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
395 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
397 #define TxPacketMax (8064 >> 7)
398 #define EarlySize 0x27
401 FuncEventMask
= 0xf4,
402 FuncPresetState
= 0xf8,
403 FuncForceEvent
= 0xfc,
406 enum rtl8110_registers
{
412 enum rtl8168_8101_registers
{
415 #define CSIAR_FLAG 0x80000000
416 #define CSIAR_WRITE_CMD 0x80000000
417 #define CSIAR_BYTE_ENABLE 0x0f
418 #define CSIAR_BYTE_ENABLE_SHIFT 12
419 #define CSIAR_ADDR_MASK 0x0fff
420 #define CSIAR_FUNC_CARD 0x00000000
421 #define CSIAR_FUNC_SDIO 0x00010000
422 #define CSIAR_FUNC_NIC 0x00020000
423 #define CSIAR_FUNC_NIC2 0x00010000
426 #define EPHYAR_FLAG 0x80000000
427 #define EPHYAR_WRITE_CMD 0x80000000
428 #define EPHYAR_REG_MASK 0x1f
429 #define EPHYAR_REG_SHIFT 16
430 #define EPHYAR_DATA_MASK 0xffff
432 #define PFM_EN (1 << 6)
433 #define TX_10M_PS_EN (1 << 7)
435 #define FIX_NAK_1 (1 << 4)
436 #define FIX_NAK_2 (1 << 3)
439 #define NOW_IS_OOB (1 << 7)
440 #define TX_EMPTY (1 << 5)
441 #define RX_EMPTY (1 << 4)
442 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
443 #define EN_NDP (1 << 3)
444 #define EN_OOB_RESET (1 << 2)
445 #define LINK_LIST_RDY (1 << 1)
447 #define EFUSEAR_FLAG 0x80000000
448 #define EFUSEAR_WRITE_CMD 0x80000000
449 #define EFUSEAR_READ_CMD 0x00000000
450 #define EFUSEAR_REG_MASK 0x03ff
451 #define EFUSEAR_REG_SHIFT 8
452 #define EFUSEAR_DATA_MASK 0xff
454 #define PFM_D3COLD_EN (1 << 6)
457 enum rtl8168_registers
{
462 #define ERIAR_FLAG 0x80000000
463 #define ERIAR_WRITE_CMD 0x80000000
464 #define ERIAR_READ_CMD 0x00000000
465 #define ERIAR_ADDR_BYTE_ALIGN 4
466 #define ERIAR_TYPE_SHIFT 16
467 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
468 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
469 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
470 #define ERIAR_MASK_SHIFT 12
471 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
472 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
473 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
474 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
475 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
476 EPHY_RXER_NUM
= 0x7c,
477 OCPDR
= 0xb0, /* OCP GPHY access */
478 #define OCPDR_WRITE_CMD 0x80000000
479 #define OCPDR_READ_CMD 0x00000000
480 #define OCPDR_REG_MASK 0x7f
481 #define OCPDR_GPHY_REG_SHIFT 16
482 #define OCPDR_DATA_MASK 0xffff
484 #define OCPAR_FLAG 0x80000000
485 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
486 #define OCPAR_GPHY_READ_CMD 0x0000f060
488 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
489 MISC
= 0xf0, /* 8168e only. */
490 #define TXPLA_RST (1 << 29)
491 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
492 #define PWM_EN (1 << 22)
493 #define RXDV_GATED_EN (1 << 19)
494 #define EARLY_TALLY_EN (1 << 16)
497 enum rtl_register_content
{
498 /* InterruptStatusBits */
502 TxDescUnavail
= 0x0080,
526 /* TXPoll register p.5 */
527 HPQ
= 0x80, /* Poll cmd on the high prio queue */
528 NPQ
= 0x40, /* Poll cmd on the low prio queue */
529 FSWInt
= 0x01, /* Forced software interrupt */
533 Cfg9346_Unlock
= 0xc0,
538 AcceptBroadcast
= 0x08,
539 AcceptMulticast
= 0x04,
541 AcceptAllPhys
= 0x01,
542 #define RX_CONFIG_ACCEPT_MASK 0x3f
545 TxInterFrameGapShift
= 24,
546 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
548 /* Config1 register p.24 */
551 Speed_down
= (1 << 4),
555 PMEnable
= (1 << 0), /* Power Management Enable */
557 /* Config2 register p. 25 */
558 ClkReqEn
= (1 << 7), /* Clock Request Enable */
559 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
560 PCI_Clock_66MHz
= 0x01,
561 PCI_Clock_33MHz
= 0x00,
563 /* Config3 register p.25 */
564 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
565 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
566 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
567 Rdy_to_L23
= (1 << 1), /* L23 Enable */
568 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
570 /* Config4 register */
571 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
573 /* Config5 register p.27 */
574 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
575 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
576 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
578 LanWake
= (1 << 1), /* LanWake enable/disable */
579 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
580 ASPM_en
= (1 << 0), /* ASPM enable */
583 TBIReset
= 0x80000000,
584 TBILoopback
= 0x40000000,
585 TBINwEnable
= 0x20000000,
586 TBINwRestart
= 0x10000000,
587 TBILinkOk
= 0x02000000,
588 TBINwComplete
= 0x01000000,
591 EnableBist
= (1 << 15), // 8168 8101
592 Mac_dbgo_oe
= (1 << 14), // 8168 8101
593 Normal_mode
= (1 << 13), // unused
594 Force_half_dup
= (1 << 12), // 8168 8101
595 Force_rxflow_en
= (1 << 11), // 8168 8101
596 Force_txflow_en
= (1 << 10), // 8168 8101
597 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
598 ASF
= (1 << 8), // 8168 8101
599 PktCntrDisable
= (1 << 7), // 8168 8101
600 Mac_dbgo_sel
= 0x001c, // 8168
605 INTT_0
= 0x0000, // 8168
606 INTT_1
= 0x0001, // 8168
607 INTT_2
= 0x0002, // 8168
608 INTT_3
= 0x0003, // 8168
610 /* rtl8169_PHYstatus */
621 TBILinkOK
= 0x02000000,
623 /* DumpCounterCommand */
626 /* magic enable v2 */
627 MagicPacket_v2
= (1 << 16), /* Wake up when receives a Magic Packet */
631 /* First doubleword. */
632 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
633 RingEnd
= (1 << 30), /* End of descriptor ring */
634 FirstFrag
= (1 << 29), /* First segment of a packet */
635 LastFrag
= (1 << 28), /* Final segment of a packet */
639 enum rtl_tx_desc_bit
{
640 /* First doubleword. */
641 TD_LSO
= (1 << 27), /* Large Send Offload */
642 #define TD_MSS_MAX 0x07ffu /* MSS value */
644 /* Second doubleword. */
645 TxVlanTag
= (1 << 17), /* Add VLAN tag */
648 /* 8169, 8168b and 810x except 8102e. */
649 enum rtl_tx_desc_bit_0
{
650 /* First doubleword. */
651 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
652 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
653 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
654 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
657 /* 8102e, 8168c and beyond. */
658 enum rtl_tx_desc_bit_1
{
659 /* First doubleword. */
660 TD1_GTSENV4
= (1 << 26), /* Giant Send for IPv4 */
661 TD1_GTSENV6
= (1 << 25), /* Giant Send for IPv6 */
662 #define GTTCPHO_SHIFT 18
663 #define GTTCPHO_MAX 0x7fU
665 /* Second doubleword. */
666 #define TCPHO_SHIFT 18
667 #define TCPHO_MAX 0x3ffU
668 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
669 TD1_IPv6_CS
= (1 << 28), /* Calculate IPv6 checksum */
670 TD1_IPv4_CS
= (1 << 29), /* Calculate IPv4 checksum */
671 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
672 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
675 enum rtl_rx_desc_bit
{
677 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
678 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
680 #define RxProtoUDP (PID1)
681 #define RxProtoTCP (PID0)
682 #define RxProtoIP (PID1 | PID0)
683 #define RxProtoMask RxProtoIP
685 IPFail
= (1 << 16), /* IP checksum failed */
686 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
687 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
688 RxVlanTag
= (1 << 16), /* VLAN tag available */
691 #define RsvdMask 0x3fffc000
708 u8 __pad
[sizeof(void *) - sizeof(u32
)];
712 RTL_FEATURE_WOL
= (1 << 0),
713 RTL_FEATURE_MSI
= (1 << 1),
714 RTL_FEATURE_GMII
= (1 << 2),
717 struct rtl8169_counters
{
724 __le32 tx_one_collision
;
725 __le32 tx_multi_collision
;
734 RTL_FLAG_TASK_ENABLED
,
735 RTL_FLAG_TASK_SLOW_PENDING
,
736 RTL_FLAG_TASK_RESET_PENDING
,
737 RTL_FLAG_TASK_PHY_PENDING
,
741 struct rtl8169_stats
{
744 struct u64_stats_sync syncp
;
747 struct rtl8169_private
{
748 void __iomem
*mmio_addr
; /* memory map physical address */
749 struct pci_dev
*pci_dev
;
750 struct net_device
*dev
;
751 struct napi_struct napi
;
755 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
756 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
758 struct rtl8169_stats rx_stats
;
759 struct rtl8169_stats tx_stats
;
760 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
761 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
762 dma_addr_t TxPhyAddr
;
763 dma_addr_t RxPhyAddr
;
764 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
765 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
766 struct timer_list timer
;
772 void (*write
)(struct rtl8169_private
*, int, int);
773 int (*read
)(struct rtl8169_private
*, int);
776 struct pll_power_ops
{
777 void (*down
)(struct rtl8169_private
*);
778 void (*up
)(struct rtl8169_private
*);
782 void (*enable
)(struct rtl8169_private
*);
783 void (*disable
)(struct rtl8169_private
*);
787 void (*write
)(struct rtl8169_private
*, int, int);
788 u32 (*read
)(struct rtl8169_private
*, int);
791 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
792 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
793 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
794 void (*hw_start
)(struct net_device
*);
795 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
796 unsigned int (*link_ok
)(void __iomem
*);
797 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
798 bool (*tso_csum
)(struct rtl8169_private
*, struct sk_buff
*, u32
*);
801 DECLARE_BITMAP(flags
, RTL_FLAG_MAX
);
803 struct work_struct work
;
808 struct mii_if_info mii
;
809 struct rtl8169_counters counters
;
814 const struct firmware
*fw
;
816 #define RTL_VER_SIZE 32
818 char version
[RTL_VER_SIZE
];
820 struct rtl_fw_phy_action
{
825 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
830 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
831 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
832 module_param(use_dac
, int, 0);
833 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
834 module_param_named(debug
, debug
.msg_enable
, int, 0);
835 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
836 MODULE_LICENSE("GPL");
837 MODULE_VERSION(RTL8169_VERSION
);
838 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
839 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
840 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
841 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
842 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
843 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
844 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
845 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
846 MODULE_FIRMWARE(FIRMWARE_8402_1
);
847 MODULE_FIRMWARE(FIRMWARE_8411_1
);
848 MODULE_FIRMWARE(FIRMWARE_8411_2
);
849 MODULE_FIRMWARE(FIRMWARE_8106E_1
);
850 MODULE_FIRMWARE(FIRMWARE_8106E_2
);
851 MODULE_FIRMWARE(FIRMWARE_8168G_2
);
852 MODULE_FIRMWARE(FIRMWARE_8168G_3
);
853 MODULE_FIRMWARE(FIRMWARE_8168H_1
);
854 MODULE_FIRMWARE(FIRMWARE_8168H_2
);
855 MODULE_FIRMWARE(FIRMWARE_8107E_1
);
856 MODULE_FIRMWARE(FIRMWARE_8107E_2
);
858 static void rtl_lock_work(struct rtl8169_private
*tp
)
860 mutex_lock(&tp
->wk
.mutex
);
863 static void rtl_unlock_work(struct rtl8169_private
*tp
)
865 mutex_unlock(&tp
->wk
.mutex
);
868 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
870 pcie_capability_clear_and_set_word(pdev
, PCI_EXP_DEVCTL
,
871 PCI_EXP_DEVCTL_READRQ
, force
);
875 bool (*check
)(struct rtl8169_private
*);
879 static void rtl_udelay(unsigned int d
)
884 static bool rtl_loop_wait(struct rtl8169_private
*tp
, const struct rtl_cond
*c
,
885 void (*delay
)(unsigned int), unsigned int d
, int n
,
890 for (i
= 0; i
< n
; i
++) {
892 if (c
->check(tp
) == high
)
895 netif_err(tp
, drv
, tp
->dev
, "%s == %d (loop: %d, delay: %d).\n",
896 c
->msg
, !high
, n
, d
);
900 static bool rtl_udelay_loop_wait_high(struct rtl8169_private
*tp
,
901 const struct rtl_cond
*c
,
902 unsigned int d
, int n
)
904 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, true);
907 static bool rtl_udelay_loop_wait_low(struct rtl8169_private
*tp
,
908 const struct rtl_cond
*c
,
909 unsigned int d
, int n
)
911 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, false);
914 static bool rtl_msleep_loop_wait_high(struct rtl8169_private
*tp
,
915 const struct rtl_cond
*c
,
916 unsigned int d
, int n
)
918 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, true);
921 static bool rtl_msleep_loop_wait_low(struct rtl8169_private
*tp
,
922 const struct rtl_cond
*c
,
923 unsigned int d
, int n
)
925 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, false);
928 #define DECLARE_RTL_COND(name) \
929 static bool name ## _check(struct rtl8169_private *); \
931 static const struct rtl_cond name = { \
932 .check = name ## _check, \
936 static bool name ## _check(struct rtl8169_private *tp)
938 DECLARE_RTL_COND(rtl_ocpar_cond
)
940 void __iomem
*ioaddr
= tp
->mmio_addr
;
942 return RTL_R32(OCPAR
) & OCPAR_FLAG
;
945 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
947 void __iomem
*ioaddr
= tp
->mmio_addr
;
949 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
951 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 100, 20) ?
955 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
957 void __iomem
*ioaddr
= tp
->mmio_addr
;
959 RTL_W32(OCPDR
, data
);
960 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
962 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 100, 20);
965 DECLARE_RTL_COND(rtl_eriar_cond
)
967 void __iomem
*ioaddr
= tp
->mmio_addr
;
969 return RTL_R32(ERIAR
) & ERIAR_FLAG
;
972 static bool rtl_ocp_reg_failure(struct rtl8169_private
*tp
, u32 reg
)
974 if (reg
& 0xffff0001) {
975 netif_err(tp
, drv
, tp
->dev
, "Invalid ocp reg %x!\n", reg
);
981 DECLARE_RTL_COND(rtl_ocp_gphy_cond
)
983 void __iomem
*ioaddr
= tp
->mmio_addr
;
985 return RTL_R32(GPHY_OCP
) & OCPAR_FLAG
;
988 static void r8168_phy_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
990 void __iomem
*ioaddr
= tp
->mmio_addr
;
992 if (rtl_ocp_reg_failure(tp
, reg
))
995 RTL_W32(GPHY_OCP
, OCPAR_FLAG
| (reg
<< 15) | data
);
997 rtl_udelay_loop_wait_low(tp
, &rtl_ocp_gphy_cond
, 25, 10);
1000 static u16
r8168_phy_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
1002 void __iomem
*ioaddr
= tp
->mmio_addr
;
1004 if (rtl_ocp_reg_failure(tp
, reg
))
1007 RTL_W32(GPHY_OCP
, reg
<< 15);
1009 return rtl_udelay_loop_wait_high(tp
, &rtl_ocp_gphy_cond
, 25, 10) ?
1010 (RTL_R32(GPHY_OCP
) & 0xffff) : ~0;
1013 static void r8168_mac_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
1015 void __iomem
*ioaddr
= tp
->mmio_addr
;
1017 if (rtl_ocp_reg_failure(tp
, reg
))
1020 RTL_W32(OCPDR
, OCPAR_FLAG
| (reg
<< 15) | data
);
1023 static u16
r8168_mac_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
1025 void __iomem
*ioaddr
= tp
->mmio_addr
;
1027 if (rtl_ocp_reg_failure(tp
, reg
))
1030 RTL_W32(OCPDR
, reg
<< 15);
1032 return RTL_R32(OCPDR
);
1035 #define OCP_STD_PHY_BASE 0xa400
1037 static void r8168g_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1040 tp
->ocp_base
= value
? value
<< 4 : OCP_STD_PHY_BASE
;
1044 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
1047 r8168_phy_ocp_write(tp
, tp
->ocp_base
+ reg
* 2, value
);
1050 static int r8168g_mdio_read(struct rtl8169_private
*tp
, int reg
)
1052 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
1055 return r8168_phy_ocp_read(tp
, tp
->ocp_base
+ reg
* 2);
1058 static void mac_mcu_write(struct rtl8169_private
*tp
, int reg
, int value
)
1061 tp
->ocp_base
= value
<< 4;
1065 r8168_mac_ocp_write(tp
, tp
->ocp_base
+ reg
, value
);
1068 static int mac_mcu_read(struct rtl8169_private
*tp
, int reg
)
1070 return r8168_mac_ocp_read(tp
, tp
->ocp_base
+ reg
);
1073 DECLARE_RTL_COND(rtl_phyar_cond
)
1075 void __iomem
*ioaddr
= tp
->mmio_addr
;
1077 return RTL_R32(PHYAR
) & 0x80000000;
1080 static void r8169_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1082 void __iomem
*ioaddr
= tp
->mmio_addr
;
1084 RTL_W32(PHYAR
, 0x80000000 | (reg
& 0x1f) << 16 | (value
& 0xffff));
1086 rtl_udelay_loop_wait_low(tp
, &rtl_phyar_cond
, 25, 20);
1088 * According to hardware specs a 20us delay is required after write
1089 * complete indication, but before sending next command.
1094 static int r8169_mdio_read(struct rtl8169_private
*tp
, int reg
)
1096 void __iomem
*ioaddr
= tp
->mmio_addr
;
1099 RTL_W32(PHYAR
, 0x0 | (reg
& 0x1f) << 16);
1101 value
= rtl_udelay_loop_wait_high(tp
, &rtl_phyar_cond
, 25, 20) ?
1102 RTL_R32(PHYAR
) & 0xffff : ~0;
1105 * According to hardware specs a 20us delay is required after read
1106 * complete indication, but before sending next command.
1113 static void r8168dp_1_mdio_access(struct rtl8169_private
*tp
, int reg
, u32 data
)
1115 void __iomem
*ioaddr
= tp
->mmio_addr
;
1117 RTL_W32(OCPDR
, data
| ((reg
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
1118 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
1119 RTL_W32(EPHY_RXER_NUM
, 0);
1121 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 1000, 100);
1124 static void r8168dp_1_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1126 r8168dp_1_mdio_access(tp
, reg
,
1127 OCPDR_WRITE_CMD
| (value
& OCPDR_DATA_MASK
));
1130 static int r8168dp_1_mdio_read(struct rtl8169_private
*tp
, int reg
)
1132 void __iomem
*ioaddr
= tp
->mmio_addr
;
1134 r8168dp_1_mdio_access(tp
, reg
, OCPDR_READ_CMD
);
1137 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
1138 RTL_W32(EPHY_RXER_NUM
, 0);
1140 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 1000, 100) ?
1141 RTL_R32(OCPDR
) & OCPDR_DATA_MASK
: ~0;
1144 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1146 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
1148 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
1151 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
1153 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
1156 static void r8168dp_2_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1158 void __iomem
*ioaddr
= tp
->mmio_addr
;
1160 r8168dp_2_mdio_start(ioaddr
);
1162 r8169_mdio_write(tp
, reg
, value
);
1164 r8168dp_2_mdio_stop(ioaddr
);
1167 static int r8168dp_2_mdio_read(struct rtl8169_private
*tp
, int reg
)
1169 void __iomem
*ioaddr
= tp
->mmio_addr
;
1172 r8168dp_2_mdio_start(ioaddr
);
1174 value
= r8169_mdio_read(tp
, reg
);
1176 r8168dp_2_mdio_stop(ioaddr
);
1181 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
1183 tp
->mdio_ops
.write(tp
, location
, val
);
1186 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1188 return tp
->mdio_ops
.read(tp
, location
);
1191 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1193 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1196 static void rtl_w0w1_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1200 val
= rtl_readphy(tp
, reg_addr
);
1201 rtl_writephy(tp
, reg_addr
, (val
& ~m
) | p
);
1204 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1207 struct rtl8169_private
*tp
= netdev_priv(dev
);
1209 rtl_writephy(tp
, location
, val
);
1212 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1214 struct rtl8169_private
*tp
= netdev_priv(dev
);
1216 return rtl_readphy(tp
, location
);
1219 DECLARE_RTL_COND(rtl_ephyar_cond
)
1221 void __iomem
*ioaddr
= tp
->mmio_addr
;
1223 return RTL_R32(EPHYAR
) & EPHYAR_FLAG
;
1226 static void rtl_ephy_write(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1228 void __iomem
*ioaddr
= tp
->mmio_addr
;
1230 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1231 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1233 rtl_udelay_loop_wait_low(tp
, &rtl_ephyar_cond
, 10, 100);
1238 static u16
rtl_ephy_read(struct rtl8169_private
*tp
, int reg_addr
)
1240 void __iomem
*ioaddr
= tp
->mmio_addr
;
1242 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1244 return rtl_udelay_loop_wait_high(tp
, &rtl_ephyar_cond
, 10, 100) ?
1245 RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
: ~0;
1248 static void rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1251 void __iomem
*ioaddr
= tp
->mmio_addr
;
1253 BUG_ON((addr
& 3) || (mask
== 0));
1254 RTL_W32(ERIDR
, val
);
1255 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1257 rtl_udelay_loop_wait_low(tp
, &rtl_eriar_cond
, 100, 100);
1260 static u32
rtl_eri_read(struct rtl8169_private
*tp
, int addr
, int type
)
1262 void __iomem
*ioaddr
= tp
->mmio_addr
;
1264 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1266 return rtl_udelay_loop_wait_high(tp
, &rtl_eriar_cond
, 100, 100) ?
1267 RTL_R32(ERIDR
) : ~0;
1270 static void rtl_w0w1_eri(struct rtl8169_private
*tp
, int addr
, u32 mask
, u32 p
,
1275 val
= rtl_eri_read(tp
, addr
, type
);
1276 rtl_eri_write(tp
, addr
, mask
, (val
& ~m
) | p
, type
);
1279 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
1281 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_0001
, cmd
, ERIAR_EXGMAC
);
1283 ocp_write(tp
, 0x1, 0x30, 0x00000001);
1286 #define OOB_CMD_RESET 0x00
1287 #define OOB_CMD_DRIVER_START 0x05
1288 #define OOB_CMD_DRIVER_STOP 0x06
1290 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
1292 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
1295 DECLARE_RTL_COND(rtl_ocp_read_cond
)
1299 reg
= rtl8168_get_ocp_reg(tp
);
1301 return ocp_read(tp
, 0x0f, reg
) & 0x00000800;
1304 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
1306 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
1308 rtl_msleep_loop_wait_high(tp
, &rtl_ocp_read_cond
, 10, 10);
1311 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
1313 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
1315 rtl_msleep_loop_wait_low(tp
, &rtl_ocp_read_cond
, 10, 10);
1318 static int r8168_check_dash(struct rtl8169_private
*tp
)
1320 u16 reg
= rtl8168_get_ocp_reg(tp
);
1322 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
1331 static void rtl_write_exgmac_batch(struct rtl8169_private
*tp
,
1332 const struct exgmac_reg
*r
, int len
)
1335 rtl_eri_write(tp
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1340 DECLARE_RTL_COND(rtl_efusear_cond
)
1342 void __iomem
*ioaddr
= tp
->mmio_addr
;
1344 return RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
;
1347 static u8
rtl8168d_efuse_read(struct rtl8169_private
*tp
, int reg_addr
)
1349 void __iomem
*ioaddr
= tp
->mmio_addr
;
1351 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1353 return rtl_udelay_loop_wait_high(tp
, &rtl_efusear_cond
, 100, 300) ?
1354 RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
: ~0;
1357 static u16
rtl_get_events(struct rtl8169_private
*tp
)
1359 void __iomem
*ioaddr
= tp
->mmio_addr
;
1361 return RTL_R16(IntrStatus
);
1364 static void rtl_ack_events(struct rtl8169_private
*tp
, u16 bits
)
1366 void __iomem
*ioaddr
= tp
->mmio_addr
;
1368 RTL_W16(IntrStatus
, bits
);
1372 static void rtl_irq_disable(struct rtl8169_private
*tp
)
1374 void __iomem
*ioaddr
= tp
->mmio_addr
;
1376 RTL_W16(IntrMask
, 0);
1380 static void rtl_irq_enable(struct rtl8169_private
*tp
, u16 bits
)
1382 void __iomem
*ioaddr
= tp
->mmio_addr
;
1384 RTL_W16(IntrMask
, bits
);
1387 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1388 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1389 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1391 static void rtl_irq_enable_all(struct rtl8169_private
*tp
)
1393 rtl_irq_enable(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1396 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1398 void __iomem
*ioaddr
= tp
->mmio_addr
;
1400 rtl_irq_disable(tp
);
1401 rtl_ack_events(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1405 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1407 void __iomem
*ioaddr
= tp
->mmio_addr
;
1409 return RTL_R32(TBICSR
) & TBIReset
;
1412 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1414 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1417 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1419 return RTL_R32(TBICSR
) & TBILinkOk
;
1422 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1424 return RTL_R8(PHYstatus
) & LinkStatus
;
1427 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1429 void __iomem
*ioaddr
= tp
->mmio_addr
;
1431 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1434 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1438 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1439 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1442 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1444 void __iomem
*ioaddr
= tp
->mmio_addr
;
1445 struct net_device
*dev
= tp
->dev
;
1447 if (!netif_running(dev
))
1450 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
1451 tp
->mac_version
== RTL_GIGA_MAC_VER_38
) {
1452 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1453 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011,
1455 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1457 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1458 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1460 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1463 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1465 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f,
1468 /* Reset packet filter */
1469 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1471 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1473 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1474 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1475 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1476 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011,
1478 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1481 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1483 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f,
1486 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_37
) {
1487 if (RTL_R8(PHYstatus
) & _10bps
) {
1488 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x4d02,
1490 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_0011
, 0x0060,
1493 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000,
1499 static void __rtl8169_check_link_status(struct net_device
*dev
,
1500 struct rtl8169_private
*tp
,
1501 void __iomem
*ioaddr
, bool pm
)
1503 if (tp
->link_ok(ioaddr
)) {
1504 rtl_link_chg_patch(tp
);
1505 /* This is to cancel a scheduled suspend if there's one. */
1507 pm_request_resume(&tp
->pci_dev
->dev
);
1508 netif_carrier_on(dev
);
1509 if (net_ratelimit())
1510 netif_info(tp
, ifup
, dev
, "link up\n");
1512 netif_carrier_off(dev
);
1513 netif_info(tp
, ifdown
, dev
, "link down\n");
1515 pm_schedule_suspend(&tp
->pci_dev
->dev
, 5000);
1519 static void rtl8169_check_link_status(struct net_device
*dev
,
1520 struct rtl8169_private
*tp
,
1521 void __iomem
*ioaddr
)
1523 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1526 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1528 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1530 void __iomem
*ioaddr
= tp
->mmio_addr
;
1534 options
= RTL_R8(Config1
);
1535 if (!(options
& PMEnable
))
1538 options
= RTL_R8(Config3
);
1539 if (options
& LinkUp
)
1540 wolopts
|= WAKE_PHY
;
1541 switch (tp
->mac_version
) {
1542 case RTL_GIGA_MAC_VER_34
:
1543 case RTL_GIGA_MAC_VER_35
:
1544 case RTL_GIGA_MAC_VER_36
:
1545 case RTL_GIGA_MAC_VER_37
:
1546 case RTL_GIGA_MAC_VER_38
:
1547 case RTL_GIGA_MAC_VER_40
:
1548 case RTL_GIGA_MAC_VER_41
:
1549 case RTL_GIGA_MAC_VER_42
:
1550 case RTL_GIGA_MAC_VER_43
:
1551 case RTL_GIGA_MAC_VER_44
:
1552 case RTL_GIGA_MAC_VER_45
:
1553 case RTL_GIGA_MAC_VER_46
:
1554 case RTL_GIGA_MAC_VER_47
:
1555 case RTL_GIGA_MAC_VER_48
:
1556 if (rtl_eri_read(tp
, 0xdc, ERIAR_EXGMAC
) & MagicPacket_v2
)
1557 wolopts
|= WAKE_MAGIC
;
1560 if (options
& MagicPacket
)
1561 wolopts
|= WAKE_MAGIC
;
1565 options
= RTL_R8(Config5
);
1567 wolopts
|= WAKE_UCAST
;
1569 wolopts
|= WAKE_BCAST
;
1571 wolopts
|= WAKE_MCAST
;
1576 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1578 struct rtl8169_private
*tp
= netdev_priv(dev
);
1582 wol
->supported
= WAKE_ANY
;
1583 wol
->wolopts
= __rtl8169_get_wol(tp
);
1585 rtl_unlock_work(tp
);
1588 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1590 void __iomem
*ioaddr
= tp
->mmio_addr
;
1591 unsigned int i
, tmp
;
1592 static const struct {
1597 { WAKE_PHY
, Config3
, LinkUp
},
1598 { WAKE_UCAST
, Config5
, UWF
},
1599 { WAKE_BCAST
, Config5
, BWF
},
1600 { WAKE_MCAST
, Config5
, MWF
},
1601 { WAKE_ANY
, Config5
, LanWake
},
1602 { WAKE_MAGIC
, Config3
, MagicPacket
}
1606 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1608 switch (tp
->mac_version
) {
1609 case RTL_GIGA_MAC_VER_34
:
1610 case RTL_GIGA_MAC_VER_35
:
1611 case RTL_GIGA_MAC_VER_36
:
1612 case RTL_GIGA_MAC_VER_37
:
1613 case RTL_GIGA_MAC_VER_38
:
1614 case RTL_GIGA_MAC_VER_40
:
1615 case RTL_GIGA_MAC_VER_41
:
1616 case RTL_GIGA_MAC_VER_42
:
1617 case RTL_GIGA_MAC_VER_43
:
1618 case RTL_GIGA_MAC_VER_44
:
1619 case RTL_GIGA_MAC_VER_45
:
1620 case RTL_GIGA_MAC_VER_46
:
1621 case RTL_GIGA_MAC_VER_47
:
1622 case RTL_GIGA_MAC_VER_48
:
1623 tmp
= ARRAY_SIZE(cfg
) - 1;
1624 if (wolopts
& WAKE_MAGIC
)
1640 tmp
= ARRAY_SIZE(cfg
);
1644 for (i
= 0; i
< tmp
; i
++) {
1645 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1646 if (wolopts
& cfg
[i
].opt
)
1647 options
|= cfg
[i
].mask
;
1648 RTL_W8(cfg
[i
].reg
, options
);
1651 switch (tp
->mac_version
) {
1652 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_17
:
1653 options
= RTL_R8(Config1
) & ~PMEnable
;
1655 options
|= PMEnable
;
1656 RTL_W8(Config1
, options
);
1659 options
= RTL_R8(Config2
) & ~PME_SIGNAL
;
1661 options
|= PME_SIGNAL
;
1662 RTL_W8(Config2
, options
);
1666 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1669 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1671 struct rtl8169_private
*tp
= netdev_priv(dev
);
1676 tp
->features
|= RTL_FEATURE_WOL
;
1678 tp
->features
&= ~RTL_FEATURE_WOL
;
1679 __rtl8169_set_wol(tp
, wol
->wolopts
);
1681 rtl_unlock_work(tp
);
1683 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1688 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1690 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1693 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1694 struct ethtool_drvinfo
*info
)
1696 struct rtl8169_private
*tp
= netdev_priv(dev
);
1697 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1699 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
1700 strlcpy(info
->version
, RTL8169_VERSION
, sizeof(info
->version
));
1701 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1702 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1703 if (!IS_ERR_OR_NULL(rtl_fw
))
1704 strlcpy(info
->fw_version
, rtl_fw
->version
,
1705 sizeof(info
->fw_version
));
1708 static int rtl8169_get_regs_len(struct net_device
*dev
)
1710 return R8169_REGS_SIZE
;
1713 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1714 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1716 struct rtl8169_private
*tp
= netdev_priv(dev
);
1717 void __iomem
*ioaddr
= tp
->mmio_addr
;
1721 reg
= RTL_R32(TBICSR
);
1722 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1723 (duplex
== DUPLEX_FULL
)) {
1724 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1725 } else if (autoneg
== AUTONEG_ENABLE
)
1726 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1728 netif_warn(tp
, link
, dev
,
1729 "incorrect speed setting refused in TBI mode\n");
1736 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1737 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1739 struct rtl8169_private
*tp
= netdev_priv(dev
);
1740 int giga_ctrl
, bmcr
;
1743 rtl_writephy(tp
, 0x1f, 0x0000);
1745 if (autoneg
== AUTONEG_ENABLE
) {
1748 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1749 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1750 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1752 if (adv
& ADVERTISED_10baseT_Half
)
1753 auto_nego
|= ADVERTISE_10HALF
;
1754 if (adv
& ADVERTISED_10baseT_Full
)
1755 auto_nego
|= ADVERTISE_10FULL
;
1756 if (adv
& ADVERTISED_100baseT_Half
)
1757 auto_nego
|= ADVERTISE_100HALF
;
1758 if (adv
& ADVERTISED_100baseT_Full
)
1759 auto_nego
|= ADVERTISE_100FULL
;
1761 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1763 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1764 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1766 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1767 if (tp
->mii
.supports_gmii
) {
1768 if (adv
& ADVERTISED_1000baseT_Half
)
1769 giga_ctrl
|= ADVERTISE_1000HALF
;
1770 if (adv
& ADVERTISED_1000baseT_Full
)
1771 giga_ctrl
|= ADVERTISE_1000FULL
;
1772 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1773 ADVERTISED_1000baseT_Full
)) {
1774 netif_info(tp
, link
, dev
,
1775 "PHY does not support 1000Mbps\n");
1779 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1781 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1782 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1786 if (speed
== SPEED_10
)
1788 else if (speed
== SPEED_100
)
1789 bmcr
= BMCR_SPEED100
;
1793 if (duplex
== DUPLEX_FULL
)
1794 bmcr
|= BMCR_FULLDPLX
;
1797 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1799 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1800 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1801 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1802 rtl_writephy(tp
, 0x17, 0x2138);
1803 rtl_writephy(tp
, 0x0e, 0x0260);
1805 rtl_writephy(tp
, 0x17, 0x2108);
1806 rtl_writephy(tp
, 0x0e, 0x0000);
1815 static int rtl8169_set_speed(struct net_device
*dev
,
1816 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1818 struct rtl8169_private
*tp
= netdev_priv(dev
);
1821 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1825 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1826 (advertising
& ADVERTISED_1000baseT_Full
)) {
1827 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1833 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1835 struct rtl8169_private
*tp
= netdev_priv(dev
);
1838 del_timer_sync(&tp
->timer
);
1841 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1842 cmd
->duplex
, cmd
->advertising
);
1843 rtl_unlock_work(tp
);
1848 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
1849 netdev_features_t features
)
1851 struct rtl8169_private
*tp
= netdev_priv(dev
);
1853 if (dev
->mtu
> TD_MSS_MAX
)
1854 features
&= ~NETIF_F_ALL_TSO
;
1856 if (dev
->mtu
> JUMBO_1K
&&
1857 !rtl_chip_infos
[tp
->mac_version
].jumbo_tx_csum
)
1858 features
&= ~NETIF_F_IP_CSUM
;
1863 static void __rtl8169_set_features(struct net_device
*dev
,
1864 netdev_features_t features
)
1866 struct rtl8169_private
*tp
= netdev_priv(dev
);
1867 void __iomem
*ioaddr
= tp
->mmio_addr
;
1870 rx_config
= RTL_R32(RxConfig
);
1871 if (features
& NETIF_F_RXALL
)
1872 rx_config
|= (AcceptErr
| AcceptRunt
);
1874 rx_config
&= ~(AcceptErr
| AcceptRunt
);
1876 RTL_W32(RxConfig
, rx_config
);
1878 if (features
& NETIF_F_RXCSUM
)
1879 tp
->cp_cmd
|= RxChkSum
;
1881 tp
->cp_cmd
&= ~RxChkSum
;
1883 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
1884 tp
->cp_cmd
|= RxVlan
;
1886 tp
->cp_cmd
&= ~RxVlan
;
1888 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) & ~(RxVlan
| RxChkSum
);
1890 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1894 static int rtl8169_set_features(struct net_device
*dev
,
1895 netdev_features_t features
)
1897 struct rtl8169_private
*tp
= netdev_priv(dev
);
1899 features
&= NETIF_F_RXALL
| NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_RX
;
1902 if (features
^ dev
->features
)
1903 __rtl8169_set_features(dev
, features
);
1904 rtl_unlock_work(tp
);
1910 static inline u32
rtl8169_tx_vlan_tag(struct sk_buff
*skb
)
1912 return (vlan_tx_tag_present(skb
)) ?
1913 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1916 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1918 u32 opts2
= le32_to_cpu(desc
->opts2
);
1920 if (opts2
& RxVlanTag
)
1921 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), swab16(opts2
& 0xffff));
1924 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1926 struct rtl8169_private
*tp
= netdev_priv(dev
);
1927 void __iomem
*ioaddr
= tp
->mmio_addr
;
1931 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1932 cmd
->port
= PORT_FIBRE
;
1933 cmd
->transceiver
= XCVR_INTERNAL
;
1935 status
= RTL_R32(TBICSR
);
1936 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1937 cmd
->autoneg
= !!(status
& TBINwEnable
);
1939 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1940 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1945 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1947 struct rtl8169_private
*tp
= netdev_priv(dev
);
1949 return mii_ethtool_gset(&tp
->mii
, cmd
);
1952 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1954 struct rtl8169_private
*tp
= netdev_priv(dev
);
1958 rc
= tp
->get_settings(dev
, cmd
);
1959 rtl_unlock_work(tp
);
1964 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1967 struct rtl8169_private
*tp
= netdev_priv(dev
);
1968 u32 __iomem
*data
= tp
->mmio_addr
;
1973 for (i
= 0; i
< R8169_REGS_SIZE
; i
+= 4)
1974 memcpy_fromio(dw
++, data
++, 4);
1975 rtl_unlock_work(tp
);
1978 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1980 struct rtl8169_private
*tp
= netdev_priv(dev
);
1982 return tp
->msg_enable
;
1985 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1987 struct rtl8169_private
*tp
= netdev_priv(dev
);
1989 tp
->msg_enable
= value
;
1992 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1999 "tx_single_collisions",
2000 "tx_multi_collisions",
2008 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
2012 return ARRAY_SIZE(rtl8169_gstrings
);
2018 DECLARE_RTL_COND(rtl_counters_cond
)
2020 void __iomem
*ioaddr
= tp
->mmio_addr
;
2022 return RTL_R32(CounterAddrLow
) & CounterDump
;
2025 static void rtl8169_update_counters(struct net_device
*dev
)
2027 struct rtl8169_private
*tp
= netdev_priv(dev
);
2028 void __iomem
*ioaddr
= tp
->mmio_addr
;
2029 struct device
*d
= &tp
->pci_dev
->dev
;
2030 struct rtl8169_counters
*counters
;
2035 * Some chips are unable to dump tally counters when the receiver
2038 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
2041 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
2045 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
2046 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
2047 RTL_W32(CounterAddrLow
, cmd
);
2048 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
2050 if (rtl_udelay_loop_wait_low(tp
, &rtl_counters_cond
, 10, 1000))
2051 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
2053 RTL_W32(CounterAddrLow
, 0);
2054 RTL_W32(CounterAddrHigh
, 0);
2056 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
2059 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
2060 struct ethtool_stats
*stats
, u64
*data
)
2062 struct rtl8169_private
*tp
= netdev_priv(dev
);
2066 rtl8169_update_counters(dev
);
2068 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
2069 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
2070 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
2071 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
2072 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
2073 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
2074 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
2075 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
2076 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
2077 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
2078 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
2079 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
2080 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
2083 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
2087 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
2092 static const struct ethtool_ops rtl8169_ethtool_ops
= {
2093 .get_drvinfo
= rtl8169_get_drvinfo
,
2094 .get_regs_len
= rtl8169_get_regs_len
,
2095 .get_link
= ethtool_op_get_link
,
2096 .get_settings
= rtl8169_get_settings
,
2097 .set_settings
= rtl8169_set_settings
,
2098 .get_msglevel
= rtl8169_get_msglevel
,
2099 .set_msglevel
= rtl8169_set_msglevel
,
2100 .get_regs
= rtl8169_get_regs
,
2101 .get_wol
= rtl8169_get_wol
,
2102 .set_wol
= rtl8169_set_wol
,
2103 .get_strings
= rtl8169_get_strings
,
2104 .get_sset_count
= rtl8169_get_sset_count
,
2105 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
2106 .get_ts_info
= ethtool_op_get_ts_info
,
2109 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
2110 struct net_device
*dev
, u8 default_version
)
2112 void __iomem
*ioaddr
= tp
->mmio_addr
;
2114 * The driver currently handles the 8168Bf and the 8168Be identically
2115 * but they can be identified more specifically through the test below
2118 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2120 * Same thing for the 8101Eb and the 8101Ec:
2122 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2124 static const struct rtl_mac_info
{
2130 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46
},
2131 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45
},
2134 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44
},
2135 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42
},
2136 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41
},
2137 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40
},
2140 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38
},
2141 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36
},
2142 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35
},
2145 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
2146 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
2147 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
2148 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
2151 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
2152 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
2153 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
2155 /* 8168DP family. */
2156 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
2157 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
2158 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
2161 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
2162 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
2163 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
2164 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
2165 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
2166 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
2167 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
2168 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
2169 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
2172 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
2173 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
2174 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
2175 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
2178 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39
},
2179 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39
},
2180 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37
},
2181 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
2182 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
2183 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
2184 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
2185 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
2186 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
2187 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
2188 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
2189 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
2190 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
2191 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
2192 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
2193 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
2194 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
2195 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
2196 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
2197 /* FIXME: where did these entries come from ? -- FR */
2198 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
2199 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
2202 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
2203 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
2204 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
2205 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
2206 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
2207 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
2210 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
2212 const struct rtl_mac_info
*p
= mac_info
;
2215 reg
= RTL_R32(TxConfig
);
2216 while ((reg
& p
->mask
) != p
->val
)
2218 tp
->mac_version
= p
->mac_version
;
2220 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
2221 netif_notice(tp
, probe
, dev
,
2222 "unknown MAC, using family default\n");
2223 tp
->mac_version
= default_version
;
2224 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_42
) {
2225 tp
->mac_version
= tp
->mii
.supports_gmii
?
2226 RTL_GIGA_MAC_VER_42
:
2227 RTL_GIGA_MAC_VER_43
;
2228 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_45
) {
2229 tp
->mac_version
= tp
->mii
.supports_gmii
?
2230 RTL_GIGA_MAC_VER_45
:
2231 RTL_GIGA_MAC_VER_47
;
2232 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_46
) {
2233 tp
->mac_version
= tp
->mii
.supports_gmii
?
2234 RTL_GIGA_MAC_VER_46
:
2235 RTL_GIGA_MAC_VER_48
;
2239 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
2241 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
2249 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
2250 const struct phy_reg
*regs
, int len
)
2253 rtl_writephy(tp
, regs
->reg
, regs
->val
);
2258 #define PHY_READ 0x00000000
2259 #define PHY_DATA_OR 0x10000000
2260 #define PHY_DATA_AND 0x20000000
2261 #define PHY_BJMPN 0x30000000
2262 #define PHY_MDIO_CHG 0x40000000
2263 #define PHY_CLEAR_READCOUNT 0x70000000
2264 #define PHY_WRITE 0x80000000
2265 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2266 #define PHY_COMP_EQ_SKIPN 0xa0000000
2267 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2268 #define PHY_WRITE_PREVIOUS 0xc0000000
2269 #define PHY_SKIPN 0xd0000000
2270 #define PHY_DELAY_MS 0xe0000000
2274 char version
[RTL_VER_SIZE
];
2280 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2282 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2284 const struct firmware
*fw
= rtl_fw
->fw
;
2285 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
2286 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2287 char *version
= rtl_fw
->version
;
2290 if (fw
->size
< FW_OPCODE_SIZE
)
2293 if (!fw_info
->magic
) {
2294 size_t i
, size
, start
;
2297 if (fw
->size
< sizeof(*fw_info
))
2300 for (i
= 0; i
< fw
->size
; i
++)
2301 checksum
+= fw
->data
[i
];
2305 start
= le32_to_cpu(fw_info
->fw_start
);
2306 if (start
> fw
->size
)
2309 size
= le32_to_cpu(fw_info
->fw_len
);
2310 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
2313 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
2315 pa
->code
= (__le32
*)(fw
->data
+ start
);
2318 if (fw
->size
% FW_OPCODE_SIZE
)
2321 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
2323 pa
->code
= (__le32
*)fw
->data
;
2324 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
2326 version
[RTL_VER_SIZE
- 1] = 0;
2333 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
2334 struct rtl_fw_phy_action
*pa
)
2339 for (index
= 0; index
< pa
->size
; index
++) {
2340 u32 action
= le32_to_cpu(pa
->code
[index
]);
2341 u32 regno
= (action
& 0x0fff0000) >> 16;
2343 switch(action
& 0xf0000000) {
2348 case PHY_CLEAR_READCOUNT
:
2350 case PHY_WRITE_PREVIOUS
:
2355 if (regno
> index
) {
2356 netif_err(tp
, ifup
, tp
->dev
,
2357 "Out of range of firmware\n");
2361 case PHY_READCOUNT_EQ_SKIP
:
2362 if (index
+ 2 >= pa
->size
) {
2363 netif_err(tp
, ifup
, tp
->dev
,
2364 "Out of range of firmware\n");
2368 case PHY_COMP_EQ_SKIPN
:
2369 case PHY_COMP_NEQ_SKIPN
:
2371 if (index
+ 1 + regno
>= pa
->size
) {
2372 netif_err(tp
, ifup
, tp
->dev
,
2373 "Out of range of firmware\n");
2379 netif_err(tp
, ifup
, tp
->dev
,
2380 "Invalid action 0x%08x\n", action
);
2389 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2391 struct net_device
*dev
= tp
->dev
;
2394 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2395 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
2399 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2405 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2407 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2408 struct mdio_ops org
, *ops
= &tp
->mdio_ops
;
2412 predata
= count
= 0;
2413 org
.write
= ops
->write
;
2414 org
.read
= ops
->read
;
2416 for (index
= 0; index
< pa
->size
; ) {
2417 u32 action
= le32_to_cpu(pa
->code
[index
]);
2418 u32 data
= action
& 0x0000ffff;
2419 u32 regno
= (action
& 0x0fff0000) >> 16;
2424 switch(action
& 0xf0000000) {
2426 predata
= rtl_readphy(tp
, regno
);
2443 ops
->write
= org
.write
;
2444 ops
->read
= org
.read
;
2445 } else if (data
== 1) {
2446 ops
->write
= mac_mcu_write
;
2447 ops
->read
= mac_mcu_read
;
2452 case PHY_CLEAR_READCOUNT
:
2457 rtl_writephy(tp
, regno
, data
);
2460 case PHY_READCOUNT_EQ_SKIP
:
2461 index
+= (count
== data
) ? 2 : 1;
2463 case PHY_COMP_EQ_SKIPN
:
2464 if (predata
== data
)
2468 case PHY_COMP_NEQ_SKIPN
:
2469 if (predata
!= data
)
2473 case PHY_WRITE_PREVIOUS
:
2474 rtl_writephy(tp
, regno
, predata
);
2490 ops
->write
= org
.write
;
2491 ops
->read
= org
.read
;
2494 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2496 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2497 release_firmware(tp
->rtl_fw
->fw
);
2500 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2503 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2505 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2507 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2508 if (!IS_ERR_OR_NULL(rtl_fw
))
2509 rtl_phy_write_fw(tp
, rtl_fw
);
2512 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2514 if (rtl_readphy(tp
, reg
) != val
)
2515 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2517 rtl_apply_firmware(tp
);
2520 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2522 static const struct phy_reg phy_reg_init
[] = {
2584 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2587 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2589 static const struct phy_reg phy_reg_init
[] = {
2595 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2598 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2600 struct pci_dev
*pdev
= tp
->pci_dev
;
2602 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2603 (pdev
->subsystem_device
!= 0xe000))
2606 rtl_writephy(tp
, 0x1f, 0x0001);
2607 rtl_writephy(tp
, 0x10, 0xf01b);
2608 rtl_writephy(tp
, 0x1f, 0x0000);
2611 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2613 static const struct phy_reg phy_reg_init
[] = {
2653 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2655 rtl8169scd_hw_phy_config_quirk(tp
);
2658 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2660 static const struct phy_reg phy_reg_init
[] = {
2708 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2711 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2713 static const struct phy_reg phy_reg_init
[] = {
2718 rtl_writephy(tp
, 0x1f, 0x0001);
2719 rtl_patchphy(tp
, 0x16, 1 << 0);
2721 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2724 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2726 static const struct phy_reg phy_reg_init
[] = {
2732 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2735 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2737 static const struct phy_reg phy_reg_init
[] = {
2745 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2748 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2750 static const struct phy_reg phy_reg_init
[] = {
2756 rtl_writephy(tp
, 0x1f, 0x0000);
2757 rtl_patchphy(tp
, 0x14, 1 << 5);
2758 rtl_patchphy(tp
, 0x0d, 1 << 5);
2760 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2763 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2765 static const struct phy_reg phy_reg_init
[] = {
2785 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2787 rtl_patchphy(tp
, 0x14, 1 << 5);
2788 rtl_patchphy(tp
, 0x0d, 1 << 5);
2789 rtl_writephy(tp
, 0x1f, 0x0000);
2792 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2794 static const struct phy_reg phy_reg_init
[] = {
2812 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2814 rtl_patchphy(tp
, 0x16, 1 << 0);
2815 rtl_patchphy(tp
, 0x14, 1 << 5);
2816 rtl_patchphy(tp
, 0x0d, 1 << 5);
2817 rtl_writephy(tp
, 0x1f, 0x0000);
2820 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2822 static const struct phy_reg phy_reg_init
[] = {
2834 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2836 rtl_patchphy(tp
, 0x16, 1 << 0);
2837 rtl_patchphy(tp
, 0x14, 1 << 5);
2838 rtl_patchphy(tp
, 0x0d, 1 << 5);
2839 rtl_writephy(tp
, 0x1f, 0x0000);
2842 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2844 rtl8168c_3_hw_phy_config(tp
);
2847 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2849 static const struct phy_reg phy_reg_init_0
[] = {
2850 /* Channel Estimation */
2871 * Enhance line driver power
2880 * Can not link to 1Gbps with bad cable
2881 * Decrease SNR threshold form 21.07dB to 19.04dB
2890 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2894 * Fine Tune Switching regulator parameter
2896 rtl_writephy(tp
, 0x1f, 0x0002);
2897 rtl_w0w1_phy(tp
, 0x0b, 0x0010, 0x00ef);
2898 rtl_w0w1_phy(tp
, 0x0c, 0xa200, 0x5d00);
2900 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
2901 static const struct phy_reg phy_reg_init
[] = {
2911 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2913 val
= rtl_readphy(tp
, 0x0d);
2915 if ((val
& 0x00ff) != 0x006c) {
2916 static const u32 set
[] = {
2917 0x0065, 0x0066, 0x0067, 0x0068,
2918 0x0069, 0x006a, 0x006b, 0x006c
2922 rtl_writephy(tp
, 0x1f, 0x0002);
2925 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2926 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2929 static const struct phy_reg phy_reg_init
[] = {
2937 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2940 /* RSET couple improve */
2941 rtl_writephy(tp
, 0x1f, 0x0002);
2942 rtl_patchphy(tp
, 0x0d, 0x0300);
2943 rtl_patchphy(tp
, 0x0f, 0x0010);
2945 /* Fine tune PLL performance */
2946 rtl_writephy(tp
, 0x1f, 0x0002);
2947 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
2948 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
2950 rtl_writephy(tp
, 0x1f, 0x0005);
2951 rtl_writephy(tp
, 0x05, 0x001b);
2953 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2955 rtl_writephy(tp
, 0x1f, 0x0000);
2958 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2960 static const struct phy_reg phy_reg_init_0
[] = {
2961 /* Channel Estimation */
2982 * Enhance line driver power
2991 * Can not link to 1Gbps with bad cable
2992 * Decrease SNR threshold form 21.07dB to 19.04dB
3001 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
3003 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
3004 static const struct phy_reg phy_reg_init
[] = {
3015 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3017 val
= rtl_readphy(tp
, 0x0d);
3018 if ((val
& 0x00ff) != 0x006c) {
3019 static const u32 set
[] = {
3020 0x0065, 0x0066, 0x0067, 0x0068,
3021 0x0069, 0x006a, 0x006b, 0x006c
3025 rtl_writephy(tp
, 0x1f, 0x0002);
3028 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
3029 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
3032 static const struct phy_reg phy_reg_init
[] = {
3040 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3043 /* Fine tune PLL performance */
3044 rtl_writephy(tp
, 0x1f, 0x0002);
3045 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
3046 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
3048 /* Switching regulator Slew rate */
3049 rtl_writephy(tp
, 0x1f, 0x0002);
3050 rtl_patchphy(tp
, 0x0f, 0x0017);
3052 rtl_writephy(tp
, 0x1f, 0x0005);
3053 rtl_writephy(tp
, 0x05, 0x001b);
3055 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
3057 rtl_writephy(tp
, 0x1f, 0x0000);
3060 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
3062 static const struct phy_reg phy_reg_init
[] = {
3118 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3121 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
3123 static const struct phy_reg phy_reg_init
[] = {
3133 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3134 rtl_patchphy(tp
, 0x0d, 1 << 5);
3137 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
3139 static const struct phy_reg phy_reg_init
[] = {
3140 /* Enable Delay cap */
3146 /* Channel estimation fine tune */
3155 /* Update PFM & 10M TX idle timer */
3167 rtl_apply_firmware(tp
);
3169 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3171 /* DCO enable for 10M IDLE Power */
3172 rtl_writephy(tp
, 0x1f, 0x0007);
3173 rtl_writephy(tp
, 0x1e, 0x0023);
3174 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
3175 rtl_writephy(tp
, 0x1f, 0x0000);
3177 /* For impedance matching */
3178 rtl_writephy(tp
, 0x1f, 0x0002);
3179 rtl_w0w1_phy(tp
, 0x08, 0x8000, 0x7f00);
3180 rtl_writephy(tp
, 0x1f, 0x0000);
3182 /* PHY auto speed down */
3183 rtl_writephy(tp
, 0x1f, 0x0007);
3184 rtl_writephy(tp
, 0x1e, 0x002d);
3185 rtl_w0w1_phy(tp
, 0x18, 0x0050, 0x0000);
3186 rtl_writephy(tp
, 0x1f, 0x0000);
3187 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3189 rtl_writephy(tp
, 0x1f, 0x0005);
3190 rtl_writephy(tp
, 0x05, 0x8b86);
3191 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3192 rtl_writephy(tp
, 0x1f, 0x0000);
3194 rtl_writephy(tp
, 0x1f, 0x0005);
3195 rtl_writephy(tp
, 0x05, 0x8b85);
3196 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3197 rtl_writephy(tp
, 0x1f, 0x0007);
3198 rtl_writephy(tp
, 0x1e, 0x0020);
3199 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x1100);
3200 rtl_writephy(tp
, 0x1f, 0x0006);
3201 rtl_writephy(tp
, 0x00, 0x5a00);
3202 rtl_writephy(tp
, 0x1f, 0x0000);
3203 rtl_writephy(tp
, 0x0d, 0x0007);
3204 rtl_writephy(tp
, 0x0e, 0x003c);
3205 rtl_writephy(tp
, 0x0d, 0x4007);
3206 rtl_writephy(tp
, 0x0e, 0x0000);
3207 rtl_writephy(tp
, 0x0d, 0x0000);
3210 static void rtl_rar_exgmac_set(struct rtl8169_private
*tp
, u8
*addr
)
3213 addr
[0] | (addr
[1] << 8),
3214 addr
[2] | (addr
[3] << 8),
3215 addr
[4] | (addr
[5] << 8)
3217 const struct exgmac_reg e
[] = {
3218 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= w
[0] | (w
[1] << 16) },
3219 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= w
[2] },
3220 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= w
[0] << 16 },
3221 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= w
[1] | (w
[2] << 16) }
3224 rtl_write_exgmac_batch(tp
, e
, ARRAY_SIZE(e
));
3227 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
3229 static const struct phy_reg phy_reg_init
[] = {
3230 /* Enable Delay cap */
3239 /* Channel estimation fine tune */
3256 rtl_apply_firmware(tp
);
3258 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3260 /* For 4-corner performance improve */
3261 rtl_writephy(tp
, 0x1f, 0x0005);
3262 rtl_writephy(tp
, 0x05, 0x8b80);
3263 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
3264 rtl_writephy(tp
, 0x1f, 0x0000);
3266 /* PHY auto speed down */
3267 rtl_writephy(tp
, 0x1f, 0x0004);
3268 rtl_writephy(tp
, 0x1f, 0x0007);
3269 rtl_writephy(tp
, 0x1e, 0x002d);
3270 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
3271 rtl_writephy(tp
, 0x1f, 0x0002);
3272 rtl_writephy(tp
, 0x1f, 0x0000);
3273 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3275 /* improve 10M EEE waveform */
3276 rtl_writephy(tp
, 0x1f, 0x0005);
3277 rtl_writephy(tp
, 0x05, 0x8b86);
3278 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3279 rtl_writephy(tp
, 0x1f, 0x0000);
3281 /* Improve 2-pair detection performance */
3282 rtl_writephy(tp
, 0x1f, 0x0005);
3283 rtl_writephy(tp
, 0x05, 0x8b85);
3284 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3285 rtl_writephy(tp
, 0x1f, 0x0000);
3288 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003, ERIAR_EXGMAC
);
3289 rtl_writephy(tp
, 0x1f, 0x0005);
3290 rtl_writephy(tp
, 0x05, 0x8b85);
3291 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3292 rtl_writephy(tp
, 0x1f, 0x0004);
3293 rtl_writephy(tp
, 0x1f, 0x0007);
3294 rtl_writephy(tp
, 0x1e, 0x0020);
3295 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0100);
3296 rtl_writephy(tp
, 0x1f, 0x0002);
3297 rtl_writephy(tp
, 0x1f, 0x0000);
3298 rtl_writephy(tp
, 0x0d, 0x0007);
3299 rtl_writephy(tp
, 0x0e, 0x003c);
3300 rtl_writephy(tp
, 0x0d, 0x4007);
3301 rtl_writephy(tp
, 0x0e, 0x0000);
3302 rtl_writephy(tp
, 0x0d, 0x0000);
3305 rtl_writephy(tp
, 0x1f, 0x0003);
3306 rtl_w0w1_phy(tp
, 0x19, 0x0000, 0x0001);
3307 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0400);
3308 rtl_writephy(tp
, 0x1f, 0x0000);
3310 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3311 rtl_rar_exgmac_set(tp
, tp
->dev
->dev_addr
);
3314 static void rtl8168f_hw_phy_config(struct rtl8169_private
*tp
)
3316 /* For 4-corner performance improve */
3317 rtl_writephy(tp
, 0x1f, 0x0005);
3318 rtl_writephy(tp
, 0x05, 0x8b80);
3319 rtl_w0w1_phy(tp
, 0x06, 0x0006, 0x0000);
3320 rtl_writephy(tp
, 0x1f, 0x0000);
3322 /* PHY auto speed down */
3323 rtl_writephy(tp
, 0x1f, 0x0007);
3324 rtl_writephy(tp
, 0x1e, 0x002d);
3325 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
3326 rtl_writephy(tp
, 0x1f, 0x0000);
3327 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3329 /* Improve 10M EEE waveform */
3330 rtl_writephy(tp
, 0x1f, 0x0005);
3331 rtl_writephy(tp
, 0x05, 0x8b86);
3332 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3333 rtl_writephy(tp
, 0x1f, 0x0000);
3336 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
3338 static const struct phy_reg phy_reg_init
[] = {
3339 /* Channel estimation fine tune */
3344 /* Modify green table for giga & fnet */
3361 /* Modify green table for 10M */
3367 /* Disable hiimpedance detection (RTCT) */
3373 rtl_apply_firmware(tp
);
3375 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3377 rtl8168f_hw_phy_config(tp
);
3379 /* Improve 2-pair detection performance */
3380 rtl_writephy(tp
, 0x1f, 0x0005);
3381 rtl_writephy(tp
, 0x05, 0x8b85);
3382 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3383 rtl_writephy(tp
, 0x1f, 0x0000);
3386 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3388 rtl_apply_firmware(tp
);
3390 rtl8168f_hw_phy_config(tp
);
3393 static void rtl8411_hw_phy_config(struct rtl8169_private
*tp
)
3395 static const struct phy_reg phy_reg_init
[] = {
3396 /* Channel estimation fine tune */
3401 /* Modify green table for giga & fnet */
3418 /* Modify green table for 10M */
3424 /* Disable hiimpedance detection (RTCT) */
3431 rtl_apply_firmware(tp
);
3433 rtl8168f_hw_phy_config(tp
);
3435 /* Improve 2-pair detection performance */
3436 rtl_writephy(tp
, 0x1f, 0x0005);
3437 rtl_writephy(tp
, 0x05, 0x8b85);
3438 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3439 rtl_writephy(tp
, 0x1f, 0x0000);
3441 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3443 /* Modify green table for giga */
3444 rtl_writephy(tp
, 0x1f, 0x0005);
3445 rtl_writephy(tp
, 0x05, 0x8b54);
3446 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3447 rtl_writephy(tp
, 0x05, 0x8b5d);
3448 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3449 rtl_writephy(tp
, 0x05, 0x8a7c);
3450 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3451 rtl_writephy(tp
, 0x05, 0x8a7f);
3452 rtl_w0w1_phy(tp
, 0x06, 0x0100, 0x0000);
3453 rtl_writephy(tp
, 0x05, 0x8a82);
3454 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3455 rtl_writephy(tp
, 0x05, 0x8a85);
3456 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3457 rtl_writephy(tp
, 0x05, 0x8a88);
3458 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3459 rtl_writephy(tp
, 0x1f, 0x0000);
3461 /* uc same-seed solution */
3462 rtl_writephy(tp
, 0x1f, 0x0005);
3463 rtl_writephy(tp
, 0x05, 0x8b85);
3464 rtl_w0w1_phy(tp
, 0x06, 0x8000, 0x0000);
3465 rtl_writephy(tp
, 0x1f, 0x0000);
3468 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x00, 0x03, ERIAR_EXGMAC
);
3469 rtl_writephy(tp
, 0x1f, 0x0005);
3470 rtl_writephy(tp
, 0x05, 0x8b85);
3471 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3472 rtl_writephy(tp
, 0x1f, 0x0004);
3473 rtl_writephy(tp
, 0x1f, 0x0007);
3474 rtl_writephy(tp
, 0x1e, 0x0020);
3475 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0100);
3476 rtl_writephy(tp
, 0x1f, 0x0000);
3477 rtl_writephy(tp
, 0x0d, 0x0007);
3478 rtl_writephy(tp
, 0x0e, 0x003c);
3479 rtl_writephy(tp
, 0x0d, 0x4007);
3480 rtl_writephy(tp
, 0x0e, 0x0000);
3481 rtl_writephy(tp
, 0x0d, 0x0000);
3484 rtl_writephy(tp
, 0x1f, 0x0003);
3485 rtl_w0w1_phy(tp
, 0x19, 0x0000, 0x0001);
3486 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0400);
3487 rtl_writephy(tp
, 0x1f, 0x0000);
3490 static void rtl8168g_1_hw_phy_config(struct rtl8169_private
*tp
)
3492 rtl_apply_firmware(tp
);
3494 rtl_writephy(tp
, 0x1f, 0x0a46);
3495 if (rtl_readphy(tp
, 0x10) & 0x0100) {
3496 rtl_writephy(tp
, 0x1f, 0x0bcc);
3497 rtl_w0w1_phy(tp
, 0x12, 0x0000, 0x8000);
3499 rtl_writephy(tp
, 0x1f, 0x0bcc);
3500 rtl_w0w1_phy(tp
, 0x12, 0x8000, 0x0000);
3503 rtl_writephy(tp
, 0x1f, 0x0a46);
3504 if (rtl_readphy(tp
, 0x13) & 0x0100) {
3505 rtl_writephy(tp
, 0x1f, 0x0c41);
3506 rtl_w0w1_phy(tp
, 0x15, 0x0002, 0x0000);
3508 rtl_writephy(tp
, 0x1f, 0x0c41);
3509 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0002);
3512 /* Enable PHY auto speed down */
3513 rtl_writephy(tp
, 0x1f, 0x0a44);
3514 rtl_w0w1_phy(tp
, 0x11, 0x000c, 0x0000);
3516 rtl_writephy(tp
, 0x1f, 0x0bcc);
3517 rtl_w0w1_phy(tp
, 0x14, 0x0100, 0x0000);
3518 rtl_writephy(tp
, 0x1f, 0x0a44);
3519 rtl_w0w1_phy(tp
, 0x11, 0x00c0, 0x0000);
3520 rtl_writephy(tp
, 0x1f, 0x0a43);
3521 rtl_writephy(tp
, 0x13, 0x8084);
3522 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x6000);
3523 rtl_w0w1_phy(tp
, 0x10, 0x1003, 0x0000);
3525 /* EEE auto-fallback function */
3526 rtl_writephy(tp
, 0x1f, 0x0a4b);
3527 rtl_w0w1_phy(tp
, 0x11, 0x0004, 0x0000);
3529 /* Enable UC LPF tune function */
3530 rtl_writephy(tp
, 0x1f, 0x0a43);
3531 rtl_writephy(tp
, 0x13, 0x8012);
3532 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3534 rtl_writephy(tp
, 0x1f, 0x0c42);
3535 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
3537 /* Improve SWR Efficiency */
3538 rtl_writephy(tp
, 0x1f, 0x0bcd);
3539 rtl_writephy(tp
, 0x14, 0x5065);
3540 rtl_writephy(tp
, 0x14, 0xd065);
3541 rtl_writephy(tp
, 0x1f, 0x0bc8);
3542 rtl_writephy(tp
, 0x11, 0x5655);
3543 rtl_writephy(tp
, 0x1f, 0x0bcd);
3544 rtl_writephy(tp
, 0x14, 0x1065);
3545 rtl_writephy(tp
, 0x14, 0x9065);
3546 rtl_writephy(tp
, 0x14, 0x1065);
3548 /* Check ALDPS bit, disable it if enabled */
3549 rtl_writephy(tp
, 0x1f, 0x0a43);
3550 if (rtl_readphy(tp
, 0x10) & 0x0004)
3551 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
3553 rtl_writephy(tp
, 0x1f, 0x0000);
3556 static void rtl8168g_2_hw_phy_config(struct rtl8169_private
*tp
)
3558 rtl_apply_firmware(tp
);
3561 static void rtl8168h_1_hw_phy_config(struct rtl8169_private
*tp
)
3566 rtl_apply_firmware(tp
);
3568 /* CHN EST parameters adjust - giga master */
3569 rtl_writephy(tp
, 0x1f, 0x0a43);
3570 rtl_writephy(tp
, 0x13, 0x809b);
3571 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xf800);
3572 rtl_writephy(tp
, 0x13, 0x80a2);
3573 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xff00);
3574 rtl_writephy(tp
, 0x13, 0x80a4);
3575 rtl_w0w1_phy(tp
, 0x14, 0x8500, 0xff00);
3576 rtl_writephy(tp
, 0x13, 0x809c);
3577 rtl_w0w1_phy(tp
, 0x14, 0xbd00, 0xff00);
3578 rtl_writephy(tp
, 0x1f, 0x0000);
3580 /* CHN EST parameters adjust - giga slave */
3581 rtl_writephy(tp
, 0x1f, 0x0a43);
3582 rtl_writephy(tp
, 0x13, 0x80ad);
3583 rtl_w0w1_phy(tp
, 0x14, 0x7000, 0xf800);
3584 rtl_writephy(tp
, 0x13, 0x80b4);
3585 rtl_w0w1_phy(tp
, 0x14, 0x5000, 0xff00);
3586 rtl_writephy(tp
, 0x13, 0x80ac);
3587 rtl_w0w1_phy(tp
, 0x14, 0x4000, 0xff00);
3588 rtl_writephy(tp
, 0x1f, 0x0000);
3590 /* CHN EST parameters adjust - fnet */
3591 rtl_writephy(tp
, 0x1f, 0x0a43);
3592 rtl_writephy(tp
, 0x13, 0x808e);
3593 rtl_w0w1_phy(tp
, 0x14, 0x1200, 0xff00);
3594 rtl_writephy(tp
, 0x13, 0x8090);
3595 rtl_w0w1_phy(tp
, 0x14, 0xe500, 0xff00);
3596 rtl_writephy(tp
, 0x13, 0x8092);
3597 rtl_w0w1_phy(tp
, 0x14, 0x9f00, 0xff00);
3598 rtl_writephy(tp
, 0x1f, 0x0000);
3600 /* enable R-tune & PGA-retune function */
3602 rtl_writephy(tp
, 0x1f, 0x0a46);
3603 data
= rtl_readphy(tp
, 0x13);
3606 dout_tapbin
|= data
;
3607 data
= rtl_readphy(tp
, 0x12);
3610 dout_tapbin
|= data
;
3611 dout_tapbin
= ~(dout_tapbin
^0x08);
3613 dout_tapbin
&= 0xf000;
3614 rtl_writephy(tp
, 0x1f, 0x0a43);
3615 rtl_writephy(tp
, 0x13, 0x827a);
3616 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3617 rtl_writephy(tp
, 0x13, 0x827b);
3618 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3619 rtl_writephy(tp
, 0x13, 0x827c);
3620 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3621 rtl_writephy(tp
, 0x13, 0x827d);
3622 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3624 rtl_writephy(tp
, 0x1f, 0x0a43);
3625 rtl_writephy(tp
, 0x13, 0x0811);
3626 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
3627 rtl_writephy(tp
, 0x1f, 0x0a42);
3628 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
3629 rtl_writephy(tp
, 0x1f, 0x0000);
3631 /* enable GPHY 10M */
3632 rtl_writephy(tp
, 0x1f, 0x0a44);
3633 rtl_w0w1_phy(tp
, 0x11, 0x0800, 0x0000);
3634 rtl_writephy(tp
, 0x1f, 0x0000);
3636 /* SAR ADC performance */
3637 rtl_writephy(tp
, 0x1f, 0x0bca);
3638 rtl_w0w1_phy(tp
, 0x17, 0x4000, 0x3000);
3639 rtl_writephy(tp
, 0x1f, 0x0000);
3641 rtl_writephy(tp
, 0x1f, 0x0a43);
3642 rtl_writephy(tp
, 0x13, 0x803f);
3643 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3644 rtl_writephy(tp
, 0x13, 0x8047);
3645 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3646 rtl_writephy(tp
, 0x13, 0x804f);
3647 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3648 rtl_writephy(tp
, 0x13, 0x8057);
3649 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3650 rtl_writephy(tp
, 0x13, 0x805f);
3651 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3652 rtl_writephy(tp
, 0x13, 0x8067);
3653 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3654 rtl_writephy(tp
, 0x13, 0x806f);
3655 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3656 rtl_writephy(tp
, 0x1f, 0x0000);
3658 /* disable phy pfm mode */
3659 rtl_writephy(tp
, 0x1f, 0x0a44);
3660 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x0080);
3661 rtl_writephy(tp
, 0x1f, 0x0000);
3663 /* Check ALDPS bit, disable it if enabled */
3664 rtl_writephy(tp
, 0x1f, 0x0a43);
3665 if (rtl_readphy(tp
, 0x10) & 0x0004)
3666 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
3668 rtl_writephy(tp
, 0x1f, 0x0000);
3671 static void rtl8168h_2_hw_phy_config(struct rtl8169_private
*tp
)
3673 u16 ioffset_p3
, ioffset_p2
, ioffset_p1
, ioffset_p0
;
3677 rtl_apply_firmware(tp
);
3679 /* CHIN EST parameter update */
3680 rtl_writephy(tp
, 0x1f, 0x0a43);
3681 rtl_writephy(tp
, 0x13, 0x808a);
3682 rtl_w0w1_phy(tp
, 0x14, 0x000a, 0x003f);
3683 rtl_writephy(tp
, 0x1f, 0x0000);
3685 /* enable R-tune & PGA-retune function */
3686 rtl_writephy(tp
, 0x1f, 0x0a43);
3687 rtl_writephy(tp
, 0x13, 0x0811);
3688 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
3689 rtl_writephy(tp
, 0x1f, 0x0a42);
3690 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
3691 rtl_writephy(tp
, 0x1f, 0x0000);
3693 /* enable GPHY 10M */
3694 rtl_writephy(tp
, 0x1f, 0x0a44);
3695 rtl_w0w1_phy(tp
, 0x11, 0x0800, 0x0000);
3696 rtl_writephy(tp
, 0x1f, 0x0000);
3698 r8168_mac_ocp_write(tp
, 0xdd02, 0x807d);
3699 data
= r8168_mac_ocp_read(tp
, 0xdd02);
3700 ioffset_p3
= ((data
& 0x80)>>7);
3703 data
= r8168_mac_ocp_read(tp
, 0xdd00);
3704 ioffset_p3
|= ((data
& (0xe000))>>13);
3705 ioffset_p2
= ((data
& (0x1e00))>>9);
3706 ioffset_p1
= ((data
& (0x01e0))>>5);
3707 ioffset_p0
= ((data
& 0x0010)>>4);
3709 ioffset_p0
|= (data
& (0x07));
3710 data
= (ioffset_p3
<<12)|(ioffset_p2
<<8)|(ioffset_p1
<<4)|(ioffset_p0
);
3712 if ((ioffset_p3
!= 0x0f) || (ioffset_p2
!= 0x0f) ||
3713 (ioffset_p1
!= 0x0f) || (ioffset_p0
== 0x0f)) {
3714 rtl_writephy(tp
, 0x1f, 0x0bcf);
3715 rtl_writephy(tp
, 0x16, data
);
3716 rtl_writephy(tp
, 0x1f, 0x0000);
3719 /* Modify rlen (TX LPF corner frequency) level */
3720 rtl_writephy(tp
, 0x1f, 0x0bcd);
3721 data
= rtl_readphy(tp
, 0x16);
3726 data
= rlen
| (rlen
<<4) | (rlen
<<8) | (rlen
<<12);
3727 rtl_writephy(tp
, 0x17, data
);
3728 rtl_writephy(tp
, 0x1f, 0x0bcd);
3729 rtl_writephy(tp
, 0x1f, 0x0000);
3731 /* disable phy pfm mode */
3732 rtl_writephy(tp
, 0x1f, 0x0a44);
3733 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x0080);
3734 rtl_writephy(tp
, 0x1f, 0x0000);
3736 /* Check ALDPS bit, disable it if enabled */
3737 rtl_writephy(tp
, 0x1f, 0x0a43);
3738 if (rtl_readphy(tp
, 0x10) & 0x0004)
3739 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
3741 rtl_writephy(tp
, 0x1f, 0x0000);
3744 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
3746 static const struct phy_reg phy_reg_init
[] = {
3753 rtl_writephy(tp
, 0x1f, 0x0000);
3754 rtl_patchphy(tp
, 0x11, 1 << 12);
3755 rtl_patchphy(tp
, 0x19, 1 << 13);
3756 rtl_patchphy(tp
, 0x10, 1 << 15);
3758 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3761 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
3763 static const struct phy_reg phy_reg_init
[] = {
3777 /* Disable ALDPS before ram code */
3778 rtl_writephy(tp
, 0x1f, 0x0000);
3779 rtl_writephy(tp
, 0x18, 0x0310);
3782 rtl_apply_firmware(tp
);
3784 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3787 static void rtl8402_hw_phy_config(struct rtl8169_private
*tp
)
3789 /* Disable ALDPS before setting firmware */
3790 rtl_writephy(tp
, 0x1f, 0x0000);
3791 rtl_writephy(tp
, 0x18, 0x0310);
3794 rtl_apply_firmware(tp
);
3797 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
3798 rtl_writephy(tp
, 0x1f, 0x0004);
3799 rtl_writephy(tp
, 0x10, 0x401f);
3800 rtl_writephy(tp
, 0x19, 0x7030);
3801 rtl_writephy(tp
, 0x1f, 0x0000);
3804 static void rtl8106e_hw_phy_config(struct rtl8169_private
*tp
)
3806 static const struct phy_reg phy_reg_init
[] = {
3813 /* Disable ALDPS before ram code */
3814 rtl_writephy(tp
, 0x1f, 0x0000);
3815 rtl_writephy(tp
, 0x18, 0x0310);
3818 rtl_apply_firmware(tp
);
3820 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
3821 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3823 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
3826 static void rtl_hw_phy_config(struct net_device
*dev
)
3828 struct rtl8169_private
*tp
= netdev_priv(dev
);
3830 rtl8169_print_mac_version(tp
);
3832 switch (tp
->mac_version
) {
3833 case RTL_GIGA_MAC_VER_01
:
3835 case RTL_GIGA_MAC_VER_02
:
3836 case RTL_GIGA_MAC_VER_03
:
3837 rtl8169s_hw_phy_config(tp
);
3839 case RTL_GIGA_MAC_VER_04
:
3840 rtl8169sb_hw_phy_config(tp
);
3842 case RTL_GIGA_MAC_VER_05
:
3843 rtl8169scd_hw_phy_config(tp
);
3845 case RTL_GIGA_MAC_VER_06
:
3846 rtl8169sce_hw_phy_config(tp
);
3848 case RTL_GIGA_MAC_VER_07
:
3849 case RTL_GIGA_MAC_VER_08
:
3850 case RTL_GIGA_MAC_VER_09
:
3851 rtl8102e_hw_phy_config(tp
);
3853 case RTL_GIGA_MAC_VER_11
:
3854 rtl8168bb_hw_phy_config(tp
);
3856 case RTL_GIGA_MAC_VER_12
:
3857 rtl8168bef_hw_phy_config(tp
);
3859 case RTL_GIGA_MAC_VER_17
:
3860 rtl8168bef_hw_phy_config(tp
);
3862 case RTL_GIGA_MAC_VER_18
:
3863 rtl8168cp_1_hw_phy_config(tp
);
3865 case RTL_GIGA_MAC_VER_19
:
3866 rtl8168c_1_hw_phy_config(tp
);
3868 case RTL_GIGA_MAC_VER_20
:
3869 rtl8168c_2_hw_phy_config(tp
);
3871 case RTL_GIGA_MAC_VER_21
:
3872 rtl8168c_3_hw_phy_config(tp
);
3874 case RTL_GIGA_MAC_VER_22
:
3875 rtl8168c_4_hw_phy_config(tp
);
3877 case RTL_GIGA_MAC_VER_23
:
3878 case RTL_GIGA_MAC_VER_24
:
3879 rtl8168cp_2_hw_phy_config(tp
);
3881 case RTL_GIGA_MAC_VER_25
:
3882 rtl8168d_1_hw_phy_config(tp
);
3884 case RTL_GIGA_MAC_VER_26
:
3885 rtl8168d_2_hw_phy_config(tp
);
3887 case RTL_GIGA_MAC_VER_27
:
3888 rtl8168d_3_hw_phy_config(tp
);
3890 case RTL_GIGA_MAC_VER_28
:
3891 rtl8168d_4_hw_phy_config(tp
);
3893 case RTL_GIGA_MAC_VER_29
:
3894 case RTL_GIGA_MAC_VER_30
:
3895 rtl8105e_hw_phy_config(tp
);
3897 case RTL_GIGA_MAC_VER_31
:
3900 case RTL_GIGA_MAC_VER_32
:
3901 case RTL_GIGA_MAC_VER_33
:
3902 rtl8168e_1_hw_phy_config(tp
);
3904 case RTL_GIGA_MAC_VER_34
:
3905 rtl8168e_2_hw_phy_config(tp
);
3907 case RTL_GIGA_MAC_VER_35
:
3908 rtl8168f_1_hw_phy_config(tp
);
3910 case RTL_GIGA_MAC_VER_36
:
3911 rtl8168f_2_hw_phy_config(tp
);
3914 case RTL_GIGA_MAC_VER_37
:
3915 rtl8402_hw_phy_config(tp
);
3918 case RTL_GIGA_MAC_VER_38
:
3919 rtl8411_hw_phy_config(tp
);
3922 case RTL_GIGA_MAC_VER_39
:
3923 rtl8106e_hw_phy_config(tp
);
3926 case RTL_GIGA_MAC_VER_40
:
3927 rtl8168g_1_hw_phy_config(tp
);
3929 case RTL_GIGA_MAC_VER_42
:
3930 case RTL_GIGA_MAC_VER_43
:
3931 case RTL_GIGA_MAC_VER_44
:
3932 rtl8168g_2_hw_phy_config(tp
);
3934 case RTL_GIGA_MAC_VER_45
:
3935 case RTL_GIGA_MAC_VER_47
:
3936 rtl8168h_1_hw_phy_config(tp
);
3938 case RTL_GIGA_MAC_VER_46
:
3939 case RTL_GIGA_MAC_VER_48
:
3940 rtl8168h_2_hw_phy_config(tp
);
3943 case RTL_GIGA_MAC_VER_41
:
3949 static void rtl_phy_work(struct rtl8169_private
*tp
)
3951 struct timer_list
*timer
= &tp
->timer
;
3952 void __iomem
*ioaddr
= tp
->mmio_addr
;
3953 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
3955 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
3957 if (tp
->phy_reset_pending(tp
)) {
3959 * A busy loop could burn quite a few cycles on nowadays CPU.
3960 * Let's delay the execution of the timer for a few ticks.
3966 if (tp
->link_ok(ioaddr
))
3969 netif_dbg(tp
, link
, tp
->dev
, "PHY reset until link up\n");
3971 tp
->phy_reset_enable(tp
);
3974 mod_timer(timer
, jiffies
+ timeout
);
3977 static void rtl_schedule_task(struct rtl8169_private
*tp
, enum rtl_flag flag
)
3979 if (!test_and_set_bit(flag
, tp
->wk
.flags
))
3980 schedule_work(&tp
->wk
.work
);
3983 static void rtl8169_phy_timer(unsigned long __opaque
)
3985 struct net_device
*dev
= (struct net_device
*)__opaque
;
3986 struct rtl8169_private
*tp
= netdev_priv(dev
);
3988 rtl_schedule_task(tp
, RTL_FLAG_TASK_PHY_PENDING
);
3991 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
3992 void __iomem
*ioaddr
)
3995 pci_release_regions(pdev
);
3996 pci_clear_mwi(pdev
);
3997 pci_disable_device(pdev
);
4001 DECLARE_RTL_COND(rtl_phy_reset_cond
)
4003 return tp
->phy_reset_pending(tp
);
4006 static void rtl8169_phy_reset(struct net_device
*dev
,
4007 struct rtl8169_private
*tp
)
4009 tp
->phy_reset_enable(tp
);
4010 rtl_msleep_loop_wait_low(tp
, &rtl_phy_reset_cond
, 1, 100);
4013 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
4015 void __iomem
*ioaddr
= tp
->mmio_addr
;
4017 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
4018 (RTL_R8(PHYstatus
) & TBI_Enable
);
4021 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
4023 void __iomem
*ioaddr
= tp
->mmio_addr
;
4025 rtl_hw_phy_config(dev
);
4027 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
4028 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4032 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
4034 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
4035 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
4037 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
4038 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4040 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4041 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
4044 rtl8169_phy_reset(dev
, tp
);
4046 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
4047 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4048 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
4049 (tp
->mii
.supports_gmii
?
4050 ADVERTISED_1000baseT_Half
|
4051 ADVERTISED_1000baseT_Full
: 0));
4053 if (rtl_tbi_enabled(tp
))
4054 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
4057 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
4059 void __iomem
*ioaddr
= tp
->mmio_addr
;
4063 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4065 RTL_W32(MAC4
, addr
[4] | addr
[5] << 8);
4068 RTL_W32(MAC0
, addr
[0] | addr
[1] << 8 | addr
[2] << 16 | addr
[3] << 24);
4071 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
4072 rtl_rar_exgmac_set(tp
, addr
);
4074 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4076 rtl_unlock_work(tp
);
4079 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
4081 struct rtl8169_private
*tp
= netdev_priv(dev
);
4082 struct sockaddr
*addr
= p
;
4084 if (!is_valid_ether_addr(addr
->sa_data
))
4085 return -EADDRNOTAVAIL
;
4087 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
4089 rtl_rar_set(tp
, dev
->dev_addr
);
4094 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4096 struct rtl8169_private
*tp
= netdev_priv(dev
);
4097 struct mii_ioctl_data
*data
= if_mii(ifr
);
4099 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
4102 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
4103 struct mii_ioctl_data
*data
, int cmd
)
4107 data
->phy_id
= 32; /* Internal PHY */
4111 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
4115 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
4121 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
4126 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
4128 if (tp
->features
& RTL_FEATURE_MSI
) {
4129 pci_disable_msi(pdev
);
4130 tp
->features
&= ~RTL_FEATURE_MSI
;
4134 static void rtl_init_mdio_ops(struct rtl8169_private
*tp
)
4136 struct mdio_ops
*ops
= &tp
->mdio_ops
;
4138 switch (tp
->mac_version
) {
4139 case RTL_GIGA_MAC_VER_27
:
4140 ops
->write
= r8168dp_1_mdio_write
;
4141 ops
->read
= r8168dp_1_mdio_read
;
4143 case RTL_GIGA_MAC_VER_28
:
4144 case RTL_GIGA_MAC_VER_31
:
4145 ops
->write
= r8168dp_2_mdio_write
;
4146 ops
->read
= r8168dp_2_mdio_read
;
4148 case RTL_GIGA_MAC_VER_40
:
4149 case RTL_GIGA_MAC_VER_41
:
4150 case RTL_GIGA_MAC_VER_42
:
4151 case RTL_GIGA_MAC_VER_43
:
4152 case RTL_GIGA_MAC_VER_44
:
4153 case RTL_GIGA_MAC_VER_45
:
4154 case RTL_GIGA_MAC_VER_46
:
4155 case RTL_GIGA_MAC_VER_47
:
4156 case RTL_GIGA_MAC_VER_48
:
4157 ops
->write
= r8168g_mdio_write
;
4158 ops
->read
= r8168g_mdio_read
;
4161 ops
->write
= r8169_mdio_write
;
4162 ops
->read
= r8169_mdio_read
;
4167 static void rtl_speed_down(struct rtl8169_private
*tp
)
4172 rtl_writephy(tp
, 0x1f, 0x0000);
4173 lpa
= rtl_readphy(tp
, MII_LPA
);
4175 if (lpa
& (LPA_10HALF
| LPA_10FULL
))
4176 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
;
4177 else if (lpa
& (LPA_100HALF
| LPA_100FULL
))
4178 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4179 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4181 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4182 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
4183 (tp
->mii
.supports_gmii
?
4184 ADVERTISED_1000baseT_Half
|
4185 ADVERTISED_1000baseT_Full
: 0);
4187 rtl8169_set_speed(tp
->dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
4191 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
4193 void __iomem
*ioaddr
= tp
->mmio_addr
;
4195 switch (tp
->mac_version
) {
4196 case RTL_GIGA_MAC_VER_25
:
4197 case RTL_GIGA_MAC_VER_26
:
4198 case RTL_GIGA_MAC_VER_29
:
4199 case RTL_GIGA_MAC_VER_30
:
4200 case RTL_GIGA_MAC_VER_32
:
4201 case RTL_GIGA_MAC_VER_33
:
4202 case RTL_GIGA_MAC_VER_34
:
4203 case RTL_GIGA_MAC_VER_37
:
4204 case RTL_GIGA_MAC_VER_38
:
4205 case RTL_GIGA_MAC_VER_39
:
4206 case RTL_GIGA_MAC_VER_40
:
4207 case RTL_GIGA_MAC_VER_41
:
4208 case RTL_GIGA_MAC_VER_42
:
4209 case RTL_GIGA_MAC_VER_43
:
4210 case RTL_GIGA_MAC_VER_44
:
4211 case RTL_GIGA_MAC_VER_45
:
4212 case RTL_GIGA_MAC_VER_46
:
4213 case RTL_GIGA_MAC_VER_47
:
4214 case RTL_GIGA_MAC_VER_48
:
4215 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
4216 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
4223 static bool rtl_wol_pll_power_down(struct rtl8169_private
*tp
)
4225 if (!(__rtl8169_get_wol(tp
) & WAKE_ANY
))
4229 rtl_wol_suspend_quirk(tp
);
4234 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
4236 rtl_writephy(tp
, 0x1f, 0x0000);
4237 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
4240 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
4242 rtl_writephy(tp
, 0x1f, 0x0000);
4243 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
4246 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
4248 void __iomem
*ioaddr
= tp
->mmio_addr
;
4250 if (rtl_wol_pll_power_down(tp
))
4253 r810x_phy_power_down(tp
);
4255 switch (tp
->mac_version
) {
4256 case RTL_GIGA_MAC_VER_07
:
4257 case RTL_GIGA_MAC_VER_08
:
4258 case RTL_GIGA_MAC_VER_09
:
4259 case RTL_GIGA_MAC_VER_10
:
4260 case RTL_GIGA_MAC_VER_13
:
4261 case RTL_GIGA_MAC_VER_16
:
4264 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4269 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
4271 void __iomem
*ioaddr
= tp
->mmio_addr
;
4273 r810x_phy_power_up(tp
);
4275 switch (tp
->mac_version
) {
4276 case RTL_GIGA_MAC_VER_07
:
4277 case RTL_GIGA_MAC_VER_08
:
4278 case RTL_GIGA_MAC_VER_09
:
4279 case RTL_GIGA_MAC_VER_10
:
4280 case RTL_GIGA_MAC_VER_13
:
4281 case RTL_GIGA_MAC_VER_16
:
4283 case RTL_GIGA_MAC_VER_47
:
4284 case RTL_GIGA_MAC_VER_48
:
4285 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
4288 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
4293 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
4295 rtl_writephy(tp
, 0x1f, 0x0000);
4296 switch (tp
->mac_version
) {
4297 case RTL_GIGA_MAC_VER_11
:
4298 case RTL_GIGA_MAC_VER_12
:
4299 case RTL_GIGA_MAC_VER_17
:
4300 case RTL_GIGA_MAC_VER_18
:
4301 case RTL_GIGA_MAC_VER_19
:
4302 case RTL_GIGA_MAC_VER_20
:
4303 case RTL_GIGA_MAC_VER_21
:
4304 case RTL_GIGA_MAC_VER_22
:
4305 case RTL_GIGA_MAC_VER_23
:
4306 case RTL_GIGA_MAC_VER_24
:
4307 case RTL_GIGA_MAC_VER_25
:
4308 case RTL_GIGA_MAC_VER_26
:
4309 case RTL_GIGA_MAC_VER_27
:
4310 case RTL_GIGA_MAC_VER_28
:
4311 case RTL_GIGA_MAC_VER_31
:
4312 rtl_writephy(tp
, 0x0e, 0x0000);
4317 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
4320 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
4322 rtl_writephy(tp
, 0x1f, 0x0000);
4323 switch (tp
->mac_version
) {
4324 case RTL_GIGA_MAC_VER_32
:
4325 case RTL_GIGA_MAC_VER_33
:
4326 case RTL_GIGA_MAC_VER_40
:
4327 case RTL_GIGA_MAC_VER_41
:
4328 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
4331 case RTL_GIGA_MAC_VER_11
:
4332 case RTL_GIGA_MAC_VER_12
:
4333 case RTL_GIGA_MAC_VER_17
:
4334 case RTL_GIGA_MAC_VER_18
:
4335 case RTL_GIGA_MAC_VER_19
:
4336 case RTL_GIGA_MAC_VER_20
:
4337 case RTL_GIGA_MAC_VER_21
:
4338 case RTL_GIGA_MAC_VER_22
:
4339 case RTL_GIGA_MAC_VER_23
:
4340 case RTL_GIGA_MAC_VER_24
:
4341 case RTL_GIGA_MAC_VER_25
:
4342 case RTL_GIGA_MAC_VER_26
:
4343 case RTL_GIGA_MAC_VER_27
:
4344 case RTL_GIGA_MAC_VER_28
:
4345 case RTL_GIGA_MAC_VER_31
:
4346 rtl_writephy(tp
, 0x0e, 0x0200);
4348 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
4353 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
4355 void __iomem
*ioaddr
= tp
->mmio_addr
;
4357 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4358 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4359 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
4360 r8168_check_dash(tp
)) {
4364 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
4365 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
4366 (RTL_R16(CPlusCmd
) & ASF
)) {
4370 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
4371 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
4372 rtl_ephy_write(tp
, 0x19, 0xff64);
4374 if (rtl_wol_pll_power_down(tp
))
4377 r8168_phy_power_down(tp
);
4379 switch (tp
->mac_version
) {
4380 case RTL_GIGA_MAC_VER_25
:
4381 case RTL_GIGA_MAC_VER_26
:
4382 case RTL_GIGA_MAC_VER_27
:
4383 case RTL_GIGA_MAC_VER_28
:
4384 case RTL_GIGA_MAC_VER_31
:
4385 case RTL_GIGA_MAC_VER_32
:
4386 case RTL_GIGA_MAC_VER_33
:
4387 case RTL_GIGA_MAC_VER_44
:
4388 case RTL_GIGA_MAC_VER_45
:
4389 case RTL_GIGA_MAC_VER_46
:
4390 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4392 case RTL_GIGA_MAC_VER_40
:
4393 case RTL_GIGA_MAC_VER_41
:
4394 rtl_w0w1_eri(tp
, 0x1a8, ERIAR_MASK_1111
, 0x00000000,
4395 0xfc000000, ERIAR_EXGMAC
);
4396 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4401 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
4403 void __iomem
*ioaddr
= tp
->mmio_addr
;
4405 switch (tp
->mac_version
) {
4406 case RTL_GIGA_MAC_VER_25
:
4407 case RTL_GIGA_MAC_VER_26
:
4408 case RTL_GIGA_MAC_VER_27
:
4409 case RTL_GIGA_MAC_VER_28
:
4410 case RTL_GIGA_MAC_VER_31
:
4411 case RTL_GIGA_MAC_VER_32
:
4412 case RTL_GIGA_MAC_VER_33
:
4413 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
4415 case RTL_GIGA_MAC_VER_44
:
4416 case RTL_GIGA_MAC_VER_45
:
4417 case RTL_GIGA_MAC_VER_46
:
4418 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
4420 case RTL_GIGA_MAC_VER_40
:
4421 case RTL_GIGA_MAC_VER_41
:
4422 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
4423 rtl_w0w1_eri(tp
, 0x1a8, ERIAR_MASK_1111
, 0xfc000000,
4424 0x00000000, ERIAR_EXGMAC
);
4428 r8168_phy_power_up(tp
);
4431 static void rtl_generic_op(struct rtl8169_private
*tp
,
4432 void (*op
)(struct rtl8169_private
*))
4438 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
4440 rtl_generic_op(tp
, tp
->pll_power_ops
.down
);
4443 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
4445 rtl_generic_op(tp
, tp
->pll_power_ops
.up
);
4448 static void rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
4450 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
4452 switch (tp
->mac_version
) {
4453 case RTL_GIGA_MAC_VER_07
:
4454 case RTL_GIGA_MAC_VER_08
:
4455 case RTL_GIGA_MAC_VER_09
:
4456 case RTL_GIGA_MAC_VER_10
:
4457 case RTL_GIGA_MAC_VER_16
:
4458 case RTL_GIGA_MAC_VER_29
:
4459 case RTL_GIGA_MAC_VER_30
:
4460 case RTL_GIGA_MAC_VER_37
:
4461 case RTL_GIGA_MAC_VER_39
:
4462 case RTL_GIGA_MAC_VER_43
:
4463 case RTL_GIGA_MAC_VER_47
:
4464 case RTL_GIGA_MAC_VER_48
:
4465 ops
->down
= r810x_pll_power_down
;
4466 ops
->up
= r810x_pll_power_up
;
4469 case RTL_GIGA_MAC_VER_11
:
4470 case RTL_GIGA_MAC_VER_12
:
4471 case RTL_GIGA_MAC_VER_17
:
4472 case RTL_GIGA_MAC_VER_18
:
4473 case RTL_GIGA_MAC_VER_19
:
4474 case RTL_GIGA_MAC_VER_20
:
4475 case RTL_GIGA_MAC_VER_21
:
4476 case RTL_GIGA_MAC_VER_22
:
4477 case RTL_GIGA_MAC_VER_23
:
4478 case RTL_GIGA_MAC_VER_24
:
4479 case RTL_GIGA_MAC_VER_25
:
4480 case RTL_GIGA_MAC_VER_26
:
4481 case RTL_GIGA_MAC_VER_27
:
4482 case RTL_GIGA_MAC_VER_28
:
4483 case RTL_GIGA_MAC_VER_31
:
4484 case RTL_GIGA_MAC_VER_32
:
4485 case RTL_GIGA_MAC_VER_33
:
4486 case RTL_GIGA_MAC_VER_34
:
4487 case RTL_GIGA_MAC_VER_35
:
4488 case RTL_GIGA_MAC_VER_36
:
4489 case RTL_GIGA_MAC_VER_38
:
4490 case RTL_GIGA_MAC_VER_40
:
4491 case RTL_GIGA_MAC_VER_41
:
4492 case RTL_GIGA_MAC_VER_42
:
4493 case RTL_GIGA_MAC_VER_44
:
4494 case RTL_GIGA_MAC_VER_45
:
4495 case RTL_GIGA_MAC_VER_46
:
4496 ops
->down
= r8168_pll_power_down
;
4497 ops
->up
= r8168_pll_power_up
;
4507 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
4509 void __iomem
*ioaddr
= tp
->mmio_addr
;
4511 switch (tp
->mac_version
) {
4512 case RTL_GIGA_MAC_VER_01
:
4513 case RTL_GIGA_MAC_VER_02
:
4514 case RTL_GIGA_MAC_VER_03
:
4515 case RTL_GIGA_MAC_VER_04
:
4516 case RTL_GIGA_MAC_VER_05
:
4517 case RTL_GIGA_MAC_VER_06
:
4518 case RTL_GIGA_MAC_VER_10
:
4519 case RTL_GIGA_MAC_VER_11
:
4520 case RTL_GIGA_MAC_VER_12
:
4521 case RTL_GIGA_MAC_VER_13
:
4522 case RTL_GIGA_MAC_VER_14
:
4523 case RTL_GIGA_MAC_VER_15
:
4524 case RTL_GIGA_MAC_VER_16
:
4525 case RTL_GIGA_MAC_VER_17
:
4526 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
4528 case RTL_GIGA_MAC_VER_18
:
4529 case RTL_GIGA_MAC_VER_19
:
4530 case RTL_GIGA_MAC_VER_20
:
4531 case RTL_GIGA_MAC_VER_21
:
4532 case RTL_GIGA_MAC_VER_22
:
4533 case RTL_GIGA_MAC_VER_23
:
4534 case RTL_GIGA_MAC_VER_24
:
4535 case RTL_GIGA_MAC_VER_34
:
4536 case RTL_GIGA_MAC_VER_35
:
4537 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
4539 case RTL_GIGA_MAC_VER_40
:
4540 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
4542 case RTL_GIGA_MAC_VER_41
:
4543 case RTL_GIGA_MAC_VER_42
:
4544 case RTL_GIGA_MAC_VER_43
:
4545 case RTL_GIGA_MAC_VER_44
:
4546 case RTL_GIGA_MAC_VER_45
:
4547 case RTL_GIGA_MAC_VER_46
:
4548 case RTL_GIGA_MAC_VER_47
:
4549 case RTL_GIGA_MAC_VER_48
:
4550 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
4553 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
4558 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4560 tp
->dirty_tx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4563 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
4565 void __iomem
*ioaddr
= tp
->mmio_addr
;
4567 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4568 rtl_generic_op(tp
, tp
->jumbo_ops
.enable
);
4569 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4572 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
4574 void __iomem
*ioaddr
= tp
->mmio_addr
;
4576 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4577 rtl_generic_op(tp
, tp
->jumbo_ops
.disable
);
4578 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4581 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
4583 void __iomem
*ioaddr
= tp
->mmio_addr
;
4585 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
4586 RTL_W8(Config4
, RTL_R8(Config4
) | Jumbo_En1
);
4587 rtl_tx_performance_tweak(tp
->pci_dev
, 0x2 << MAX_READ_REQUEST_SHIFT
);
4590 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
4592 void __iomem
*ioaddr
= tp
->mmio_addr
;
4594 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
4595 RTL_W8(Config4
, RTL_R8(Config4
) & ~Jumbo_En1
);
4596 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4599 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
4601 void __iomem
*ioaddr
= tp
->mmio_addr
;
4603 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
4606 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
4608 void __iomem
*ioaddr
= tp
->mmio_addr
;
4610 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
4613 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
4615 void __iomem
*ioaddr
= tp
->mmio_addr
;
4617 RTL_W8(MaxTxPacketSize
, 0x3f);
4618 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
4619 RTL_W8(Config4
, RTL_R8(Config4
) | 0x01);
4620 rtl_tx_performance_tweak(tp
->pci_dev
, 0x2 << MAX_READ_REQUEST_SHIFT
);
4623 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
4625 void __iomem
*ioaddr
= tp
->mmio_addr
;
4627 RTL_W8(MaxTxPacketSize
, 0x0c);
4628 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
4629 RTL_W8(Config4
, RTL_R8(Config4
) & ~0x01);
4630 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4633 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
4635 rtl_tx_performance_tweak(tp
->pci_dev
,
4636 (0x2 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4639 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
4641 rtl_tx_performance_tweak(tp
->pci_dev
,
4642 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4645 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
4647 void __iomem
*ioaddr
= tp
->mmio_addr
;
4649 r8168b_0_hw_jumbo_enable(tp
);
4651 RTL_W8(Config4
, RTL_R8(Config4
) | (1 << 0));
4654 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
4656 void __iomem
*ioaddr
= tp
->mmio_addr
;
4658 r8168b_0_hw_jumbo_disable(tp
);
4660 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4663 static void rtl_init_jumbo_ops(struct rtl8169_private
*tp
)
4665 struct jumbo_ops
*ops
= &tp
->jumbo_ops
;
4667 switch (tp
->mac_version
) {
4668 case RTL_GIGA_MAC_VER_11
:
4669 ops
->disable
= r8168b_0_hw_jumbo_disable
;
4670 ops
->enable
= r8168b_0_hw_jumbo_enable
;
4672 case RTL_GIGA_MAC_VER_12
:
4673 case RTL_GIGA_MAC_VER_17
:
4674 ops
->disable
= r8168b_1_hw_jumbo_disable
;
4675 ops
->enable
= r8168b_1_hw_jumbo_enable
;
4677 case RTL_GIGA_MAC_VER_18
: /* Wild guess. Needs info from Realtek. */
4678 case RTL_GIGA_MAC_VER_19
:
4679 case RTL_GIGA_MAC_VER_20
:
4680 case RTL_GIGA_MAC_VER_21
: /* Wild guess. Needs info from Realtek. */
4681 case RTL_GIGA_MAC_VER_22
:
4682 case RTL_GIGA_MAC_VER_23
:
4683 case RTL_GIGA_MAC_VER_24
:
4684 case RTL_GIGA_MAC_VER_25
:
4685 case RTL_GIGA_MAC_VER_26
:
4686 ops
->disable
= r8168c_hw_jumbo_disable
;
4687 ops
->enable
= r8168c_hw_jumbo_enable
;
4689 case RTL_GIGA_MAC_VER_27
:
4690 case RTL_GIGA_MAC_VER_28
:
4691 ops
->disable
= r8168dp_hw_jumbo_disable
;
4692 ops
->enable
= r8168dp_hw_jumbo_enable
;
4694 case RTL_GIGA_MAC_VER_31
: /* Wild guess. Needs info from Realtek. */
4695 case RTL_GIGA_MAC_VER_32
:
4696 case RTL_GIGA_MAC_VER_33
:
4697 case RTL_GIGA_MAC_VER_34
:
4698 ops
->disable
= r8168e_hw_jumbo_disable
;
4699 ops
->enable
= r8168e_hw_jumbo_enable
;
4703 * No action needed for jumbo frames with 8169.
4704 * No jumbo for 810x at all.
4706 case RTL_GIGA_MAC_VER_40
:
4707 case RTL_GIGA_MAC_VER_41
:
4708 case RTL_GIGA_MAC_VER_42
:
4709 case RTL_GIGA_MAC_VER_43
:
4710 case RTL_GIGA_MAC_VER_44
:
4711 case RTL_GIGA_MAC_VER_45
:
4712 case RTL_GIGA_MAC_VER_46
:
4713 case RTL_GIGA_MAC_VER_47
:
4714 case RTL_GIGA_MAC_VER_48
:
4716 ops
->disable
= NULL
;
4722 DECLARE_RTL_COND(rtl_chipcmd_cond
)
4724 void __iomem
*ioaddr
= tp
->mmio_addr
;
4726 return RTL_R8(ChipCmd
) & CmdReset
;
4729 static void rtl_hw_reset(struct rtl8169_private
*tp
)
4731 void __iomem
*ioaddr
= tp
->mmio_addr
;
4733 RTL_W8(ChipCmd
, CmdReset
);
4735 rtl_udelay_loop_wait_low(tp
, &rtl_chipcmd_cond
, 100, 100);
4737 netdev_reset_queue(tp
->dev
);
4740 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
4742 struct rtl_fw
*rtl_fw
;
4746 name
= rtl_lookup_firmware_name(tp
);
4748 goto out_no_firmware
;
4750 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
4754 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
4758 rc
= rtl_check_firmware(tp
, rtl_fw
);
4760 goto err_release_firmware
;
4762 tp
->rtl_fw
= rtl_fw
;
4766 err_release_firmware
:
4767 release_firmware(rtl_fw
->fw
);
4771 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
4778 static void rtl_request_firmware(struct rtl8169_private
*tp
)
4780 if (IS_ERR(tp
->rtl_fw
))
4781 rtl_request_uncached_firmware(tp
);
4784 static void rtl_rx_close(struct rtl8169_private
*tp
)
4786 void __iomem
*ioaddr
= tp
->mmio_addr
;
4788 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
4791 DECLARE_RTL_COND(rtl_npq_cond
)
4793 void __iomem
*ioaddr
= tp
->mmio_addr
;
4795 return RTL_R8(TxPoll
) & NPQ
;
4798 DECLARE_RTL_COND(rtl_txcfg_empty_cond
)
4800 void __iomem
*ioaddr
= tp
->mmio_addr
;
4802 return RTL_R32(TxConfig
) & TXCFG_EMPTY
;
4805 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
4807 void __iomem
*ioaddr
= tp
->mmio_addr
;
4809 /* Disable interrupts */
4810 rtl8169_irq_mask_and_ack(tp
);
4814 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4815 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4816 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4817 rtl_udelay_loop_wait_low(tp
, &rtl_npq_cond
, 20, 42*42);
4818 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
4819 tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
4820 tp
->mac_version
== RTL_GIGA_MAC_VER_36
||
4821 tp
->mac_version
== RTL_GIGA_MAC_VER_37
||
4822 tp
->mac_version
== RTL_GIGA_MAC_VER_38
||
4823 tp
->mac_version
== RTL_GIGA_MAC_VER_40
||
4824 tp
->mac_version
== RTL_GIGA_MAC_VER_41
||
4825 tp
->mac_version
== RTL_GIGA_MAC_VER_42
||
4826 tp
->mac_version
== RTL_GIGA_MAC_VER_43
||
4827 tp
->mac_version
== RTL_GIGA_MAC_VER_44
||
4828 tp
->mac_version
== RTL_GIGA_MAC_VER_45
||
4829 tp
->mac_version
== RTL_GIGA_MAC_VER_46
||
4830 tp
->mac_version
== RTL_GIGA_MAC_VER_47
||
4831 tp
->mac_version
== RTL_GIGA_MAC_VER_48
) {
4832 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4833 rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 666);
4835 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4842 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
4844 void __iomem
*ioaddr
= tp
->mmio_addr
;
4846 /* Set DMA burst size and Interframe Gap Time */
4847 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4848 (InterFrameGap
<< TxInterFrameGapShift
));
4851 static void rtl_hw_start(struct net_device
*dev
)
4853 struct rtl8169_private
*tp
= netdev_priv(dev
);
4857 rtl_irq_enable_all(tp
);
4860 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
4861 void __iomem
*ioaddr
)
4864 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4865 * register to be written before TxDescAddrLow to work.
4866 * Switching from MMIO to I/O access fixes the issue as well.
4868 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4869 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4870 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4871 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4874 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
4878 cmd
= RTL_R16(CPlusCmd
);
4879 RTL_W16(CPlusCmd
, cmd
);
4883 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
4885 /* Low hurts. Let's disable the filtering. */
4886 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
4889 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
4891 static const struct rtl_cfg2_info
{
4896 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
4897 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
4898 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
4899 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
4901 const struct rtl_cfg2_info
*p
= cfg2_info
;
4905 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
4906 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
4907 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
4908 RTL_W32(0x7c, p
->val
);
4914 static void rtl_set_rx_mode(struct net_device
*dev
)
4916 struct rtl8169_private
*tp
= netdev_priv(dev
);
4917 void __iomem
*ioaddr
= tp
->mmio_addr
;
4918 u32 mc_filter
[2]; /* Multicast hash filter */
4922 if (dev
->flags
& IFF_PROMISC
) {
4923 /* Unconditionally log net taps. */
4924 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
4926 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4928 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4929 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
4930 (dev
->flags
& IFF_ALLMULTI
)) {
4931 /* Too many to filter perfectly -- accept all multicasts. */
4932 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4933 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4935 struct netdev_hw_addr
*ha
;
4937 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4938 mc_filter
[1] = mc_filter
[0] = 0;
4939 netdev_for_each_mc_addr(ha
, dev
) {
4940 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
4941 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4942 rx_mode
|= AcceptMulticast
;
4946 if (dev
->features
& NETIF_F_RXALL
)
4947 rx_mode
|= (AcceptErr
| AcceptRunt
);
4949 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
4951 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4952 u32 data
= mc_filter
[0];
4954 mc_filter
[0] = swab32(mc_filter
[1]);
4955 mc_filter
[1] = swab32(data
);
4958 if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
)
4959 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4961 RTL_W32(MAR0
+ 4, mc_filter
[1]);
4962 RTL_W32(MAR0
+ 0, mc_filter
[0]);
4964 RTL_W32(RxConfig
, tmp
);
4967 static void rtl_hw_start_8169(struct net_device
*dev
)
4969 struct rtl8169_private
*tp
= netdev_priv(dev
);
4970 void __iomem
*ioaddr
= tp
->mmio_addr
;
4971 struct pci_dev
*pdev
= tp
->pci_dev
;
4973 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
4974 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
4975 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
4978 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4979 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4980 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4981 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4982 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4983 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4987 RTL_W8(EarlyTxThres
, NoEarlyTx
);
4989 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4991 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4992 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4993 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4994 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4995 rtl_set_rx_tx_config_registers(tp
);
4997 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
4999 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5000 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
5001 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5002 "Bit-3 and bit-14 MUST be 1\n");
5003 tp
->cp_cmd
|= (1 << 14);
5006 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5008 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
5011 * Undocumented corner. Supposedly:
5012 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5014 RTL_W16(IntrMitigate
, 0x0000);
5016 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
5018 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
5019 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
5020 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
5021 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
5022 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5023 rtl_set_rx_tx_config_registers(tp
);
5026 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5028 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5031 RTL_W32(RxMissed
, 0);
5033 rtl_set_rx_mode(dev
);
5035 /* no early-rx interrupts */
5036 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
5039 static void rtl_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5041 if (tp
->csi_ops
.write
)
5042 tp
->csi_ops
.write(tp
, addr
, value
);
5045 static u32
rtl_csi_read(struct rtl8169_private
*tp
, int addr
)
5047 return tp
->csi_ops
.read
? tp
->csi_ops
.read(tp
, addr
) : ~0;
5050 static void rtl_csi_access_enable(struct rtl8169_private
*tp
, u32 bits
)
5054 csi
= rtl_csi_read(tp
, 0x070c) & 0x00ffffff;
5055 rtl_csi_write(tp
, 0x070c, csi
| bits
);
5058 static void rtl_csi_access_enable_1(struct rtl8169_private
*tp
)
5060 rtl_csi_access_enable(tp
, 0x17000000);
5063 static void rtl_csi_access_enable_2(struct rtl8169_private
*tp
)
5065 rtl_csi_access_enable(tp
, 0x27000000);
5068 DECLARE_RTL_COND(rtl_csiar_cond
)
5070 void __iomem
*ioaddr
= tp
->mmio_addr
;
5072 return RTL_R32(CSIAR
) & CSIAR_FLAG
;
5075 static void r8169_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5077 void __iomem
*ioaddr
= tp
->mmio_addr
;
5079 RTL_W32(CSIDR
, value
);
5080 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5081 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5083 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5086 static u32
r8169_csi_read(struct rtl8169_private
*tp
, int addr
)
5088 void __iomem
*ioaddr
= tp
->mmio_addr
;
5090 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
5091 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5093 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5094 RTL_R32(CSIDR
) : ~0;
5097 static void r8402_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5099 void __iomem
*ioaddr
= tp
->mmio_addr
;
5101 RTL_W32(CSIDR
, value
);
5102 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5103 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
|
5106 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5109 static u32
r8402_csi_read(struct rtl8169_private
*tp
, int addr
)
5111 void __iomem
*ioaddr
= tp
->mmio_addr
;
5113 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) | CSIAR_FUNC_NIC
|
5114 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5116 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5117 RTL_R32(CSIDR
) : ~0;
5120 static void r8411_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5122 void __iomem
*ioaddr
= tp
->mmio_addr
;
5124 RTL_W32(CSIDR
, value
);
5125 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5126 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
|
5129 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5132 static u32
r8411_csi_read(struct rtl8169_private
*tp
, int addr
)
5134 void __iomem
*ioaddr
= tp
->mmio_addr
;
5136 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) | CSIAR_FUNC_NIC2
|
5137 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5139 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5140 RTL_R32(CSIDR
) : ~0;
5143 static void rtl_init_csi_ops(struct rtl8169_private
*tp
)
5145 struct csi_ops
*ops
= &tp
->csi_ops
;
5147 switch (tp
->mac_version
) {
5148 case RTL_GIGA_MAC_VER_01
:
5149 case RTL_GIGA_MAC_VER_02
:
5150 case RTL_GIGA_MAC_VER_03
:
5151 case RTL_GIGA_MAC_VER_04
:
5152 case RTL_GIGA_MAC_VER_05
:
5153 case RTL_GIGA_MAC_VER_06
:
5154 case RTL_GIGA_MAC_VER_10
:
5155 case RTL_GIGA_MAC_VER_11
:
5156 case RTL_GIGA_MAC_VER_12
:
5157 case RTL_GIGA_MAC_VER_13
:
5158 case RTL_GIGA_MAC_VER_14
:
5159 case RTL_GIGA_MAC_VER_15
:
5160 case RTL_GIGA_MAC_VER_16
:
5161 case RTL_GIGA_MAC_VER_17
:
5166 case RTL_GIGA_MAC_VER_37
:
5167 case RTL_GIGA_MAC_VER_38
:
5168 ops
->write
= r8402_csi_write
;
5169 ops
->read
= r8402_csi_read
;
5172 case RTL_GIGA_MAC_VER_44
:
5173 ops
->write
= r8411_csi_write
;
5174 ops
->read
= r8411_csi_read
;
5178 ops
->write
= r8169_csi_write
;
5179 ops
->read
= r8169_csi_read
;
5185 unsigned int offset
;
5190 static void rtl_ephy_init(struct rtl8169_private
*tp
, const struct ephy_info
*e
,
5196 w
= (rtl_ephy_read(tp
, e
->offset
) & ~e
->mask
) | e
->bits
;
5197 rtl_ephy_write(tp
, e
->offset
, w
);
5202 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
5204 pcie_capability_clear_word(pdev
, PCI_EXP_LNKCTL
,
5205 PCI_EXP_LNKCTL_CLKREQ_EN
);
5208 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
5210 pcie_capability_set_word(pdev
, PCI_EXP_LNKCTL
,
5211 PCI_EXP_LNKCTL_CLKREQ_EN
);
5214 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private
*tp
, bool enable
)
5216 void __iomem
*ioaddr
= tp
->mmio_addr
;
5219 data
= RTL_R8(Config3
);
5224 data
&= ~Rdy_to_L23
;
5226 RTL_W8(Config3
, data
);
5229 #define R8168_CPCMD_QUIRK_MASK (\
5240 static void rtl_hw_start_8168bb(struct rtl8169_private
*tp
)
5242 void __iomem
*ioaddr
= tp
->mmio_addr
;
5243 struct pci_dev
*pdev
= tp
->pci_dev
;
5245 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5247 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5249 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
5250 rtl_tx_performance_tweak(pdev
, (0x5 << MAX_READ_REQUEST_SHIFT
) |
5251 PCI_EXP_DEVCTL_NOSNOOP_EN
);
5255 static void rtl_hw_start_8168bef(struct rtl8169_private
*tp
)
5257 void __iomem
*ioaddr
= tp
->mmio_addr
;
5259 rtl_hw_start_8168bb(tp
);
5261 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5263 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
5266 static void __rtl_hw_start_8168cp(struct rtl8169_private
*tp
)
5268 void __iomem
*ioaddr
= tp
->mmio_addr
;
5269 struct pci_dev
*pdev
= tp
->pci_dev
;
5271 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
5273 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5275 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5276 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5278 rtl_disable_clock_request(pdev
);
5280 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5283 static void rtl_hw_start_8168cp_1(struct rtl8169_private
*tp
)
5285 static const struct ephy_info e_info_8168cp
[] = {
5286 { 0x01, 0, 0x0001 },
5287 { 0x02, 0x0800, 0x1000 },
5288 { 0x03, 0, 0x0042 },
5289 { 0x06, 0x0080, 0x0000 },
5293 rtl_csi_access_enable_2(tp
);
5295 rtl_ephy_init(tp
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
5297 __rtl_hw_start_8168cp(tp
);
5300 static void rtl_hw_start_8168cp_2(struct rtl8169_private
*tp
)
5302 void __iomem
*ioaddr
= tp
->mmio_addr
;
5303 struct pci_dev
*pdev
= tp
->pci_dev
;
5305 rtl_csi_access_enable_2(tp
);
5307 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5309 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5310 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5312 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5315 static void rtl_hw_start_8168cp_3(struct rtl8169_private
*tp
)
5317 void __iomem
*ioaddr
= tp
->mmio_addr
;
5318 struct pci_dev
*pdev
= tp
->pci_dev
;
5320 rtl_csi_access_enable_2(tp
);
5322 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5325 RTL_W8(DBG_REG
, 0x20);
5327 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5329 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5330 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5332 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5335 static void rtl_hw_start_8168c_1(struct rtl8169_private
*tp
)
5337 void __iomem
*ioaddr
= tp
->mmio_addr
;
5338 static const struct ephy_info e_info_8168c_1
[] = {
5339 { 0x02, 0x0800, 0x1000 },
5340 { 0x03, 0, 0x0002 },
5341 { 0x06, 0x0080, 0x0000 }
5344 rtl_csi_access_enable_2(tp
);
5346 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
5348 rtl_ephy_init(tp
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
5350 __rtl_hw_start_8168cp(tp
);
5353 static void rtl_hw_start_8168c_2(struct rtl8169_private
*tp
)
5355 static const struct ephy_info e_info_8168c_2
[] = {
5356 { 0x01, 0, 0x0001 },
5357 { 0x03, 0x0400, 0x0220 }
5360 rtl_csi_access_enable_2(tp
);
5362 rtl_ephy_init(tp
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
5364 __rtl_hw_start_8168cp(tp
);
5367 static void rtl_hw_start_8168c_3(struct rtl8169_private
*tp
)
5369 rtl_hw_start_8168c_2(tp
);
5372 static void rtl_hw_start_8168c_4(struct rtl8169_private
*tp
)
5374 rtl_csi_access_enable_2(tp
);
5376 __rtl_hw_start_8168cp(tp
);
5379 static void rtl_hw_start_8168d(struct rtl8169_private
*tp
)
5381 void __iomem
*ioaddr
= tp
->mmio_addr
;
5382 struct pci_dev
*pdev
= tp
->pci_dev
;
5384 rtl_csi_access_enable_2(tp
);
5386 rtl_disable_clock_request(pdev
);
5388 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5390 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5391 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5393 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5396 static void rtl_hw_start_8168dp(struct rtl8169_private
*tp
)
5398 void __iomem
*ioaddr
= tp
->mmio_addr
;
5399 struct pci_dev
*pdev
= tp
->pci_dev
;
5401 rtl_csi_access_enable_1(tp
);
5403 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5404 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5406 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5408 rtl_disable_clock_request(pdev
);
5411 static void rtl_hw_start_8168d_4(struct rtl8169_private
*tp
)
5413 void __iomem
*ioaddr
= tp
->mmio_addr
;
5414 struct pci_dev
*pdev
= tp
->pci_dev
;
5415 static const struct ephy_info e_info_8168d_4
[] = {
5417 { 0x19, 0x20, 0x50 },
5422 rtl_csi_access_enable_1(tp
);
5424 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5426 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5428 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
5429 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
5432 w
= rtl_ephy_read(tp
, e
->offset
);
5433 rtl_ephy_write(tp
, 0x03, (w
& e
->mask
) | e
->bits
);
5436 rtl_enable_clock_request(pdev
);
5439 static void rtl_hw_start_8168e_1(struct rtl8169_private
*tp
)
5441 void __iomem
*ioaddr
= tp
->mmio_addr
;
5442 struct pci_dev
*pdev
= tp
->pci_dev
;
5443 static const struct ephy_info e_info_8168e_1
[] = {
5444 { 0x00, 0x0200, 0x0100 },
5445 { 0x00, 0x0000, 0x0004 },
5446 { 0x06, 0x0002, 0x0001 },
5447 { 0x06, 0x0000, 0x0030 },
5448 { 0x07, 0x0000, 0x2000 },
5449 { 0x00, 0x0000, 0x0020 },
5450 { 0x03, 0x5800, 0x2000 },
5451 { 0x03, 0x0000, 0x0001 },
5452 { 0x01, 0x0800, 0x1000 },
5453 { 0x07, 0x0000, 0x4000 },
5454 { 0x1e, 0x0000, 0x2000 },
5455 { 0x19, 0xffff, 0xfe6c },
5456 { 0x0a, 0x0000, 0x0040 }
5459 rtl_csi_access_enable_2(tp
);
5461 rtl_ephy_init(tp
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
5463 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5464 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5466 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5468 rtl_disable_clock_request(pdev
);
5470 /* Reset tx FIFO pointer */
5471 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
5472 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
5474 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5477 static void rtl_hw_start_8168e_2(struct rtl8169_private
*tp
)
5479 void __iomem
*ioaddr
= tp
->mmio_addr
;
5480 struct pci_dev
*pdev
= tp
->pci_dev
;
5481 static const struct ephy_info e_info_8168e_2
[] = {
5482 { 0x09, 0x0000, 0x0080 },
5483 { 0x19, 0x0000, 0x0224 }
5486 rtl_csi_access_enable_1(tp
);
5488 rtl_ephy_init(tp
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
5490 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5491 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5493 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5494 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5495 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
5496 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5497 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
5498 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
5499 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5500 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00, ERIAR_EXGMAC
);
5502 RTL_W8(MaxTxPacketSize
, EarlySize
);
5504 rtl_disable_clock_request(pdev
);
5506 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5507 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
5509 /* Adjust EEE LED frequency */
5510 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
5512 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5513 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
5514 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5517 static void rtl_hw_start_8168f(struct rtl8169_private
*tp
)
5519 void __iomem
*ioaddr
= tp
->mmio_addr
;
5520 struct pci_dev
*pdev
= tp
->pci_dev
;
5522 rtl_csi_access_enable_2(tp
);
5524 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5526 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5527 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5528 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
5529 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5530 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
5531 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
5532 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5533 rtl_w0w1_eri(tp
, 0x1d0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5534 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
5535 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x00000060, ERIAR_EXGMAC
);
5537 RTL_W8(MaxTxPacketSize
, EarlySize
);
5539 rtl_disable_clock_request(pdev
);
5541 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5542 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
5543 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5544 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
5545 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5548 static void rtl_hw_start_8168f_1(struct rtl8169_private
*tp
)
5550 void __iomem
*ioaddr
= tp
->mmio_addr
;
5551 static const struct ephy_info e_info_8168f_1
[] = {
5552 { 0x06, 0x00c0, 0x0020 },
5553 { 0x08, 0x0001, 0x0002 },
5554 { 0x09, 0x0000, 0x0080 },
5555 { 0x19, 0x0000, 0x0224 }
5558 rtl_hw_start_8168f(tp
);
5560 rtl_ephy_init(tp
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
5562 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00, ERIAR_EXGMAC
);
5564 /* Adjust EEE LED frequency */
5565 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
5568 static void rtl_hw_start_8411(struct rtl8169_private
*tp
)
5570 static const struct ephy_info e_info_8168f_1
[] = {
5571 { 0x06, 0x00c0, 0x0020 },
5572 { 0x0f, 0xffff, 0x5200 },
5573 { 0x1e, 0x0000, 0x4000 },
5574 { 0x19, 0x0000, 0x0224 }
5577 rtl_hw_start_8168f(tp
);
5578 rtl_pcie_state_l2l3_enable(tp
, false);
5580 rtl_ephy_init(tp
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
5582 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0x0000, ERIAR_EXGMAC
);
5585 static void rtl_hw_start_8168g_1(struct rtl8169_private
*tp
)
5587 void __iomem
*ioaddr
= tp
->mmio_addr
;
5588 struct pci_dev
*pdev
= tp
->pci_dev
;
5590 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5592 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x080002, ERIAR_EXGMAC
);
5593 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x38, ERIAR_EXGMAC
);
5594 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x48, ERIAR_EXGMAC
);
5595 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5597 rtl_csi_access_enable_1(tp
);
5599 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5601 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
5602 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
5603 rtl_eri_write(tp
, 0x2f8, ERIAR_MASK_0011
, 0x1d8f, ERIAR_EXGMAC
);
5605 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5606 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
5607 RTL_W8(MaxTxPacketSize
, EarlySize
);
5609 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5610 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5612 /* Adjust EEE LED frequency */
5613 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
5615 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06, ERIAR_EXGMAC
);
5616 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, 0x1000, ERIAR_EXGMAC
);
5618 rtl_pcie_state_l2l3_enable(tp
, false);
5621 static void rtl_hw_start_8168g_2(struct rtl8169_private
*tp
)
5623 void __iomem
*ioaddr
= tp
->mmio_addr
;
5624 static const struct ephy_info e_info_8168g_2
[] = {
5625 { 0x00, 0x0000, 0x0008 },
5626 { 0x0c, 0x3df0, 0x0200 },
5627 { 0x19, 0xffff, 0xfc00 },
5628 { 0x1e, 0xffff, 0x20eb }
5631 rtl_hw_start_8168g_1(tp
);
5633 /* disable aspm and clock request before access ephy */
5634 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
5635 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
5636 rtl_ephy_init(tp
, e_info_8168g_2
, ARRAY_SIZE(e_info_8168g_2
));
5639 static void rtl_hw_start_8411_2(struct rtl8169_private
*tp
)
5641 void __iomem
*ioaddr
= tp
->mmio_addr
;
5642 static const struct ephy_info e_info_8411_2
[] = {
5643 { 0x00, 0x0000, 0x0008 },
5644 { 0x0c, 0x3df0, 0x0200 },
5645 { 0x0f, 0xffff, 0x5200 },
5646 { 0x19, 0x0020, 0x0000 },
5647 { 0x1e, 0x0000, 0x2000 }
5650 rtl_hw_start_8168g_1(tp
);
5652 /* disable aspm and clock request before access ephy */
5653 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
5654 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
5655 rtl_ephy_init(tp
, e_info_8411_2
, ARRAY_SIZE(e_info_8411_2
));
5658 static void rtl_hw_start_8168h_1(struct rtl8169_private
*tp
)
5660 void __iomem
*ioaddr
= tp
->mmio_addr
;
5661 struct pci_dev
*pdev
= tp
->pci_dev
;
5664 static const struct ephy_info e_info_8168h_1
[] = {
5665 { 0x1e, 0x0800, 0x0001 },
5666 { 0x1d, 0x0000, 0x0800 },
5667 { 0x05, 0xffff, 0x2089 },
5668 { 0x06, 0xffff, 0x5881 },
5669 { 0x04, 0xffff, 0x154a },
5670 { 0x01, 0xffff, 0x068b }
5673 /* disable aspm and clock request before access ephy */
5674 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
5675 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
5676 rtl_ephy_init(tp
, e_info_8168h_1
, ARRAY_SIZE(e_info_8168h_1
));
5678 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5680 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x00080002, ERIAR_EXGMAC
);
5681 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x38, ERIAR_EXGMAC
);
5682 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x48, ERIAR_EXGMAC
);
5683 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5685 rtl_csi_access_enable_1(tp
);
5687 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5689 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
5690 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
5692 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_1111
, 0x0010, 0x00, ERIAR_EXGMAC
);
5694 rtl_w0w1_eri(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f00, 0x00, ERIAR_EXGMAC
);
5696 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87, ERIAR_EXGMAC
);
5698 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5699 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
5700 RTL_W8(MaxTxPacketSize
, EarlySize
);
5702 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5703 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5705 /* Adjust EEE LED frequency */
5706 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
5708 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
5709 RTL_W8(DLLPR
, RTL_R8(MISC_1
) & ~PFM_D3COLD_EN
);
5711 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~TX_10M_PS_EN
);
5713 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, 0x1000, ERIAR_EXGMAC
);
5715 rtl_pcie_state_l2l3_enable(tp
, false);
5717 rtl_writephy(tp
, 0x1f, 0x0c42);
5718 rg_saw_cnt
= rtl_readphy(tp
, 0x13);
5719 rtl_writephy(tp
, 0x1f, 0x0000);
5720 if (rg_saw_cnt
> 0) {
5723 sw_cnt_1ms_ini
= 16000000/rg_saw_cnt
;
5724 sw_cnt_1ms_ini
&= 0x0fff;
5725 data
= r8168_mac_ocp_read(tp
, 0xd412);
5727 data
|= sw_cnt_1ms_ini
;
5728 r8168_mac_ocp_write(tp
, 0xd412, data
);
5731 data
= r8168_mac_ocp_read(tp
, 0xe056);
5734 r8168_mac_ocp_write(tp
, 0xe056, data
);
5736 data
= r8168_mac_ocp_read(tp
, 0xe052);
5739 r8168_mac_ocp_write(tp
, 0xe052, data
);
5741 data
= r8168_mac_ocp_read(tp
, 0xe0d6);
5744 r8168_mac_ocp_write(tp
, 0xe0d6, data
);
5746 data
= r8168_mac_ocp_read(tp
, 0xd420);
5749 r8168_mac_ocp_write(tp
, 0xd420, data
);
5751 r8168_mac_ocp_write(tp
, 0xe63e, 0x0001);
5752 r8168_mac_ocp_write(tp
, 0xe63e, 0x0000);
5753 r8168_mac_ocp_write(tp
, 0xc094, 0x0000);
5754 r8168_mac_ocp_write(tp
, 0xc09e, 0x0000);
5757 static void rtl_hw_start_8168(struct net_device
*dev
)
5759 struct rtl8169_private
*tp
= netdev_priv(dev
);
5760 void __iomem
*ioaddr
= tp
->mmio_addr
;
5762 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5764 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5766 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
5768 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
5770 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5772 RTL_W16(IntrMitigate
, 0x5151);
5774 /* Work around for RxFIFO overflow. */
5775 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
5776 tp
->event_slow
|= RxFIFOOver
| PCSTimeout
;
5777 tp
->event_slow
&= ~RxOverflow
;
5780 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
5782 rtl_set_rx_tx_config_registers(tp
);
5786 switch (tp
->mac_version
) {
5787 case RTL_GIGA_MAC_VER_11
:
5788 rtl_hw_start_8168bb(tp
);
5791 case RTL_GIGA_MAC_VER_12
:
5792 case RTL_GIGA_MAC_VER_17
:
5793 rtl_hw_start_8168bef(tp
);
5796 case RTL_GIGA_MAC_VER_18
:
5797 rtl_hw_start_8168cp_1(tp
);
5800 case RTL_GIGA_MAC_VER_19
:
5801 rtl_hw_start_8168c_1(tp
);
5804 case RTL_GIGA_MAC_VER_20
:
5805 rtl_hw_start_8168c_2(tp
);
5808 case RTL_GIGA_MAC_VER_21
:
5809 rtl_hw_start_8168c_3(tp
);
5812 case RTL_GIGA_MAC_VER_22
:
5813 rtl_hw_start_8168c_4(tp
);
5816 case RTL_GIGA_MAC_VER_23
:
5817 rtl_hw_start_8168cp_2(tp
);
5820 case RTL_GIGA_MAC_VER_24
:
5821 rtl_hw_start_8168cp_3(tp
);
5824 case RTL_GIGA_MAC_VER_25
:
5825 case RTL_GIGA_MAC_VER_26
:
5826 case RTL_GIGA_MAC_VER_27
:
5827 rtl_hw_start_8168d(tp
);
5830 case RTL_GIGA_MAC_VER_28
:
5831 rtl_hw_start_8168d_4(tp
);
5834 case RTL_GIGA_MAC_VER_31
:
5835 rtl_hw_start_8168dp(tp
);
5838 case RTL_GIGA_MAC_VER_32
:
5839 case RTL_GIGA_MAC_VER_33
:
5840 rtl_hw_start_8168e_1(tp
);
5842 case RTL_GIGA_MAC_VER_34
:
5843 rtl_hw_start_8168e_2(tp
);
5846 case RTL_GIGA_MAC_VER_35
:
5847 case RTL_GIGA_MAC_VER_36
:
5848 rtl_hw_start_8168f_1(tp
);
5851 case RTL_GIGA_MAC_VER_38
:
5852 rtl_hw_start_8411(tp
);
5855 case RTL_GIGA_MAC_VER_40
:
5856 case RTL_GIGA_MAC_VER_41
:
5857 rtl_hw_start_8168g_1(tp
);
5859 case RTL_GIGA_MAC_VER_42
:
5860 rtl_hw_start_8168g_2(tp
);
5863 case RTL_GIGA_MAC_VER_44
:
5864 rtl_hw_start_8411_2(tp
);
5867 case RTL_GIGA_MAC_VER_45
:
5868 case RTL_GIGA_MAC_VER_46
:
5869 rtl_hw_start_8168h_1(tp
);
5873 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
5874 dev
->name
, tp
->mac_version
);
5878 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5880 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5882 rtl_set_rx_mode(dev
);
5884 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
5887 #define R810X_CPCMD_QUIRK_MASK (\
5898 static void rtl_hw_start_8102e_1(struct rtl8169_private
*tp
)
5900 void __iomem
*ioaddr
= tp
->mmio_addr
;
5901 struct pci_dev
*pdev
= tp
->pci_dev
;
5902 static const struct ephy_info e_info_8102e_1
[] = {
5903 { 0x01, 0, 0x6e65 },
5904 { 0x02, 0, 0x091f },
5905 { 0x03, 0, 0xc2f9 },
5906 { 0x06, 0, 0xafb5 },
5907 { 0x07, 0, 0x0e00 },
5908 { 0x19, 0, 0xec80 },
5909 { 0x01, 0, 0x2e65 },
5914 rtl_csi_access_enable_2(tp
);
5916 RTL_W8(DBG_REG
, FIX_NAK_1
);
5918 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5921 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
5922 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5924 cfg1
= RTL_R8(Config1
);
5925 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
5926 RTL_W8(Config1
, cfg1
& ~LEDS0
);
5928 rtl_ephy_init(tp
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
5931 static void rtl_hw_start_8102e_2(struct rtl8169_private
*tp
)
5933 void __iomem
*ioaddr
= tp
->mmio_addr
;
5934 struct pci_dev
*pdev
= tp
->pci_dev
;
5936 rtl_csi_access_enable_2(tp
);
5938 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5940 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
5941 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5944 static void rtl_hw_start_8102e_3(struct rtl8169_private
*tp
)
5946 rtl_hw_start_8102e_2(tp
);
5948 rtl_ephy_write(tp
, 0x03, 0xc2f9);
5951 static void rtl_hw_start_8105e_1(struct rtl8169_private
*tp
)
5953 void __iomem
*ioaddr
= tp
->mmio_addr
;
5954 static const struct ephy_info e_info_8105e_1
[] = {
5955 { 0x07, 0, 0x4000 },
5956 { 0x19, 0, 0x0200 },
5957 { 0x19, 0, 0x0020 },
5958 { 0x1e, 0, 0x2000 },
5959 { 0x03, 0, 0x0001 },
5960 { 0x19, 0, 0x0100 },
5961 { 0x19, 0, 0x0004 },
5965 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5966 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
5968 /* Disable Early Tally Counter */
5969 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
5971 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
5972 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5974 rtl_ephy_init(tp
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
5976 rtl_pcie_state_l2l3_enable(tp
, false);
5979 static void rtl_hw_start_8105e_2(struct rtl8169_private
*tp
)
5981 rtl_hw_start_8105e_1(tp
);
5982 rtl_ephy_write(tp
, 0x1e, rtl_ephy_read(tp
, 0x1e) | 0x8000);
5985 static void rtl_hw_start_8402(struct rtl8169_private
*tp
)
5987 void __iomem
*ioaddr
= tp
->mmio_addr
;
5988 static const struct ephy_info e_info_8402
[] = {
5989 { 0x19, 0xffff, 0xff64 },
5993 rtl_csi_access_enable_2(tp
);
5995 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5996 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
5998 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5999 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
6001 rtl_ephy_init(tp
, e_info_8402
, ARRAY_SIZE(e_info_8402
));
6003 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6005 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00000002, ERIAR_EXGMAC
);
6006 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00000006, ERIAR_EXGMAC
);
6007 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6008 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6009 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6010 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6011 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0e00, 0xff00, ERIAR_EXGMAC
);
6013 rtl_pcie_state_l2l3_enable(tp
, false);
6016 static void rtl_hw_start_8106(struct rtl8169_private
*tp
)
6018 void __iomem
*ioaddr
= tp
->mmio_addr
;
6020 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6021 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
6023 RTL_W32(MISC
, (RTL_R32(MISC
) | DISABLE_LAN_EN
) & ~EARLY_TALLY_EN
);
6024 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
6025 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6027 rtl_pcie_state_l2l3_enable(tp
, false);
6030 static void rtl_hw_start_8101(struct net_device
*dev
)
6032 struct rtl8169_private
*tp
= netdev_priv(dev
);
6033 void __iomem
*ioaddr
= tp
->mmio_addr
;
6034 struct pci_dev
*pdev
= tp
->pci_dev
;
6036 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_30
)
6037 tp
->event_slow
&= ~RxFIFOOver
;
6039 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
6040 tp
->mac_version
== RTL_GIGA_MAC_VER_16
)
6041 pcie_capability_set_word(pdev
, PCI_EXP_DEVCTL
,
6042 PCI_EXP_DEVCTL_NOSNOOP_EN
);
6044 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
6046 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6048 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
6050 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
6051 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
6053 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
6055 rtl_set_rx_tx_config_registers(tp
);
6057 switch (tp
->mac_version
) {
6058 case RTL_GIGA_MAC_VER_07
:
6059 rtl_hw_start_8102e_1(tp
);
6062 case RTL_GIGA_MAC_VER_08
:
6063 rtl_hw_start_8102e_3(tp
);
6066 case RTL_GIGA_MAC_VER_09
:
6067 rtl_hw_start_8102e_2(tp
);
6070 case RTL_GIGA_MAC_VER_29
:
6071 rtl_hw_start_8105e_1(tp
);
6073 case RTL_GIGA_MAC_VER_30
:
6074 rtl_hw_start_8105e_2(tp
);
6077 case RTL_GIGA_MAC_VER_37
:
6078 rtl_hw_start_8402(tp
);
6081 case RTL_GIGA_MAC_VER_39
:
6082 rtl_hw_start_8106(tp
);
6084 case RTL_GIGA_MAC_VER_43
:
6085 rtl_hw_start_8168g_2(tp
);
6087 case RTL_GIGA_MAC_VER_47
:
6088 case RTL_GIGA_MAC_VER_48
:
6089 rtl_hw_start_8168h_1(tp
);
6093 RTL_W8(Cfg9346
, Cfg9346_Lock
);
6095 RTL_W16(IntrMitigate
, 0x0000);
6097 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
6099 rtl_set_rx_mode(dev
);
6103 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
6106 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
6108 struct rtl8169_private
*tp
= netdev_priv(dev
);
6110 if (new_mtu
< ETH_ZLEN
||
6111 new_mtu
> rtl_chip_infos
[tp
->mac_version
].jumbo_max
)
6114 if (new_mtu
> ETH_DATA_LEN
)
6115 rtl_hw_jumbo_enable(tp
);
6117 rtl_hw_jumbo_disable(tp
);
6120 netdev_update_features(dev
);
6125 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
6127 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
6128 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
6131 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
6132 void **data_buff
, struct RxDesc
*desc
)
6134 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
6139 rtl8169_make_unusable_by_asic(desc
);
6142 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
6144 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
6146 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
6149 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
6152 desc
->addr
= cpu_to_le64(mapping
);
6154 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
6157 static inline void *rtl8169_align(void *data
)
6159 return (void *)ALIGN((long)data
, 16);
6162 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
6163 struct RxDesc
*desc
)
6167 struct device
*d
= &tp
->pci_dev
->dev
;
6168 struct net_device
*dev
= tp
->dev
;
6169 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
6171 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
6175 if (rtl8169_align(data
) != data
) {
6177 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
6182 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
6184 if (unlikely(dma_mapping_error(d
, mapping
))) {
6185 if (net_ratelimit())
6186 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
6190 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
6198 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
6202 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
6203 if (tp
->Rx_databuff
[i
]) {
6204 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
6205 tp
->RxDescArray
+ i
);
6210 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
6212 desc
->opts1
|= cpu_to_le32(RingEnd
);
6215 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
6219 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
6222 if (tp
->Rx_databuff
[i
])
6225 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
6227 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
6230 tp
->Rx_databuff
[i
] = data
;
6233 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
6237 rtl8169_rx_clear(tp
);
6241 static int rtl8169_init_ring(struct net_device
*dev
)
6243 struct rtl8169_private
*tp
= netdev_priv(dev
);
6245 rtl8169_init_ring_indexes(tp
);
6247 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
6248 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
6250 return rtl8169_rx_fill(tp
);
6253 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
6254 struct TxDesc
*desc
)
6256 unsigned int len
= tx_skb
->len
;
6258 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
6266 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
6271 for (i
= 0; i
< n
; i
++) {
6272 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
6273 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
6274 unsigned int len
= tx_skb
->len
;
6277 struct sk_buff
*skb
= tx_skb
->skb
;
6279 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
6280 tp
->TxDescArray
+ entry
);
6282 tp
->dev
->stats
.tx_dropped
++;
6283 dev_kfree_skb_any(skb
);
6290 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
6292 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
6293 tp
->cur_tx
= tp
->dirty_tx
= 0;
6296 static void rtl_reset_work(struct rtl8169_private
*tp
)
6298 struct net_device
*dev
= tp
->dev
;
6301 napi_disable(&tp
->napi
);
6302 netif_stop_queue(dev
);
6303 synchronize_sched();
6305 rtl8169_hw_reset(tp
);
6307 for (i
= 0; i
< NUM_RX_DESC
; i
++)
6308 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
6310 rtl8169_tx_clear(tp
);
6311 rtl8169_init_ring_indexes(tp
);
6313 napi_enable(&tp
->napi
);
6315 netif_wake_queue(dev
);
6316 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
6319 static void rtl8169_tx_timeout(struct net_device
*dev
)
6321 struct rtl8169_private
*tp
= netdev_priv(dev
);
6323 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6326 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
6329 struct skb_shared_info
*info
= skb_shinfo(skb
);
6330 unsigned int cur_frag
, entry
;
6331 struct TxDesc
*uninitialized_var(txd
);
6332 struct device
*d
= &tp
->pci_dev
->dev
;
6335 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
6336 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
6341 entry
= (entry
+ 1) % NUM_TX_DESC
;
6343 txd
= tp
->TxDescArray
+ entry
;
6344 len
= skb_frag_size(frag
);
6345 addr
= skb_frag_address(frag
);
6346 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
6347 if (unlikely(dma_mapping_error(d
, mapping
))) {
6348 if (net_ratelimit())
6349 netif_err(tp
, drv
, tp
->dev
,
6350 "Failed to map TX fragments DMA!\n");
6354 /* Anti gcc 2.95.3 bugware (sic) */
6355 status
= opts
[0] | len
|
6356 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
6358 txd
->opts1
= cpu_to_le32(status
);
6359 txd
->opts2
= cpu_to_le32(opts
[1]);
6360 txd
->addr
= cpu_to_le64(mapping
);
6362 tp
->tx_skb
[entry
].len
= len
;
6366 tp
->tx_skb
[entry
].skb
= skb
;
6367 txd
->opts1
|= cpu_to_le32(LastFrag
);
6373 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
6377 static bool rtl_skb_pad(struct sk_buff
*skb
)
6379 if (skb_padto(skb
, ETH_ZLEN
))
6381 skb_put(skb
, ETH_ZLEN
- skb
->len
);
6385 static bool rtl_test_hw_pad_bug(struct rtl8169_private
*tp
, struct sk_buff
*skb
)
6387 return skb
->len
< ETH_ZLEN
&& tp
->mac_version
== RTL_GIGA_MAC_VER_34
;
6390 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
6391 struct net_device
*dev
);
6392 /* r8169_csum_workaround()
6393 * The hw limites the value the transport offset. When the offset is out of the
6394 * range, calculate the checksum by sw.
6396 static void r8169_csum_workaround(struct rtl8169_private
*tp
,
6397 struct sk_buff
*skb
)
6399 if (skb_shinfo(skb
)->gso_size
) {
6400 netdev_features_t features
= tp
->dev
->features
;
6401 struct sk_buff
*segs
, *nskb
;
6403 features
&= ~(NETIF_F_SG
| NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
);
6404 segs
= skb_gso_segment(skb
, features
);
6405 if (IS_ERR(segs
) || !segs
)
6412 rtl8169_start_xmit(nskb
, tp
->dev
);
6416 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6417 if (skb_checksum_help(skb
) < 0)
6420 rtl8169_start_xmit(skb
, tp
->dev
);
6422 struct net_device_stats
*stats
;
6425 stats
= &tp
->dev
->stats
;
6426 stats
->tx_dropped
++;
6431 /* msdn_giant_send_check()
6432 * According to the document of microsoft, the TCP Pseudo Header excludes the
6433 * packet length for IPv6 TCP large packets.
6435 static int msdn_giant_send_check(struct sk_buff
*skb
)
6437 const struct ipv6hdr
*ipv6h
;
6441 ret
= skb_cow_head(skb
, 0);
6445 ipv6h
= ipv6_hdr(skb
);
6449 th
->check
= ~tcp_v6_check(0, &ipv6h
->saddr
, &ipv6h
->daddr
, 0);
6454 static inline __be16
get_protocol(struct sk_buff
*skb
)
6458 if (skb
->protocol
== htons(ETH_P_8021Q
))
6459 protocol
= vlan_eth_hdr(skb
)->h_vlan_encapsulated_proto
;
6461 protocol
= skb
->protocol
;
6466 static bool rtl8169_tso_csum_v1(struct rtl8169_private
*tp
,
6467 struct sk_buff
*skb
, u32
*opts
)
6469 u32 mss
= skb_shinfo(skb
)->gso_size
;
6473 opts
[0] |= min(mss
, TD_MSS_MAX
) << TD0_MSS_SHIFT
;
6474 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6475 const struct iphdr
*ip
= ip_hdr(skb
);
6477 if (ip
->protocol
== IPPROTO_TCP
)
6478 opts
[0] |= TD0_IP_CS
| TD0_TCP_CS
;
6479 else if (ip
->protocol
== IPPROTO_UDP
)
6480 opts
[0] |= TD0_IP_CS
| TD0_UDP_CS
;
6488 static bool rtl8169_tso_csum_v2(struct rtl8169_private
*tp
,
6489 struct sk_buff
*skb
, u32
*opts
)
6491 u32 transport_offset
= (u32
)skb_transport_offset(skb
);
6492 u32 mss
= skb_shinfo(skb
)->gso_size
;
6495 if (transport_offset
> GTTCPHO_MAX
) {
6496 netif_warn(tp
, tx_err
, tp
->dev
,
6497 "Invalid transport offset 0x%x for TSO\n",
6502 switch (get_protocol(skb
)) {
6503 case htons(ETH_P_IP
):
6504 opts
[0] |= TD1_GTSENV4
;
6507 case htons(ETH_P_IPV6
):
6508 if (msdn_giant_send_check(skb
))
6511 opts
[0] |= TD1_GTSENV6
;
6519 opts
[0] |= transport_offset
<< GTTCPHO_SHIFT
;
6520 opts
[1] |= min(mss
, TD_MSS_MAX
) << TD1_MSS_SHIFT
;
6521 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6524 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
6525 return skb_checksum_help(skb
) == 0 && rtl_skb_pad(skb
);
6527 if (transport_offset
> TCPHO_MAX
) {
6528 netif_warn(tp
, tx_err
, tp
->dev
,
6529 "Invalid transport offset 0x%x\n",
6534 switch (get_protocol(skb
)) {
6535 case htons(ETH_P_IP
):
6536 opts
[1] |= TD1_IPv4_CS
;
6537 ip_protocol
= ip_hdr(skb
)->protocol
;
6540 case htons(ETH_P_IPV6
):
6541 opts
[1] |= TD1_IPv6_CS
;
6542 ip_protocol
= ipv6_hdr(skb
)->nexthdr
;
6546 ip_protocol
= IPPROTO_RAW
;
6550 if (ip_protocol
== IPPROTO_TCP
)
6551 opts
[1] |= TD1_TCP_CS
;
6552 else if (ip_protocol
== IPPROTO_UDP
)
6553 opts
[1] |= TD1_UDP_CS
;
6557 opts
[1] |= transport_offset
<< TCPHO_SHIFT
;
6559 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
6560 return rtl_skb_pad(skb
);
6566 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
6567 struct net_device
*dev
)
6569 struct rtl8169_private
*tp
= netdev_priv(dev
);
6570 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
6571 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
6572 void __iomem
*ioaddr
= tp
->mmio_addr
;
6573 struct device
*d
= &tp
->pci_dev
->dev
;
6579 if (unlikely(!TX_FRAGS_READY_FOR(tp
, skb_shinfo(skb
)->nr_frags
))) {
6580 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
6584 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
6587 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb
));
6590 if (!tp
->tso_csum(tp
, skb
, opts
)) {
6591 r8169_csum_workaround(tp
, skb
);
6592 return NETDEV_TX_OK
;
6595 len
= skb_headlen(skb
);
6596 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
6597 if (unlikely(dma_mapping_error(d
, mapping
))) {
6598 if (net_ratelimit())
6599 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
6603 tp
->tx_skb
[entry
].len
= len
;
6604 txd
->addr
= cpu_to_le64(mapping
);
6606 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
6610 opts
[0] |= FirstFrag
;
6612 opts
[0] |= FirstFrag
| LastFrag
;
6613 tp
->tx_skb
[entry
].skb
= skb
;
6616 txd
->opts2
= cpu_to_le32(opts
[1]);
6618 netdev_sent_queue(dev
, skb
->len
);
6620 skb_tx_timestamp(skb
);
6624 /* Anti gcc 2.95.3 bugware (sic) */
6625 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
6626 txd
->opts1
= cpu_to_le32(status
);
6628 tp
->cur_tx
+= frags
+ 1;
6632 RTL_W8(TxPoll
, NPQ
);
6636 if (!TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
)) {
6637 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6638 * not miss a ring update when it notices a stopped queue.
6641 netif_stop_queue(dev
);
6642 /* Sync with rtl_tx:
6643 * - publish queue status and cur_tx ring index (write barrier)
6644 * - refresh dirty_tx ring index (read barrier).
6645 * May the current thread have a pessimistic view of the ring
6646 * status and forget to wake up queue, a racing rtl_tx thread
6650 if (TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
))
6651 netif_wake_queue(dev
);
6654 return NETDEV_TX_OK
;
6657 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
6659 dev_kfree_skb_any(skb
);
6660 dev
->stats
.tx_dropped
++;
6661 return NETDEV_TX_OK
;
6664 netif_stop_queue(dev
);
6665 dev
->stats
.tx_dropped
++;
6666 return NETDEV_TX_BUSY
;
6669 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
6671 struct rtl8169_private
*tp
= netdev_priv(dev
);
6672 struct pci_dev
*pdev
= tp
->pci_dev
;
6673 u16 pci_status
, pci_cmd
;
6675 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
6676 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
6678 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6679 pci_cmd
, pci_status
);
6682 * The recovery sequence below admits a very elaborated explanation:
6683 * - it seems to work;
6684 * - I did not see what else could be done;
6685 * - it makes iop3xx happy.
6687 * Feel free to adjust to your needs.
6689 if (pdev
->broken_parity_status
)
6690 pci_cmd
&= ~PCI_COMMAND_PARITY
;
6692 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
6694 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
6696 pci_write_config_word(pdev
, PCI_STATUS
,
6697 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
6698 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
6699 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
6701 /* The infamous DAC f*ckup only happens at boot time */
6702 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->cur_rx
) {
6703 void __iomem
*ioaddr
= tp
->mmio_addr
;
6705 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
6706 tp
->cp_cmd
&= ~PCIDAC
;
6707 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
6708 dev
->features
&= ~NETIF_F_HIGHDMA
;
6711 rtl8169_hw_reset(tp
);
6713 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6716 static void rtl_tx(struct net_device
*dev
, struct rtl8169_private
*tp
)
6718 unsigned int dirty_tx
, tx_left
;
6719 unsigned int bytes_compl
= 0, pkts_compl
= 0;
6721 dirty_tx
= tp
->dirty_tx
;
6723 tx_left
= tp
->cur_tx
- dirty_tx
;
6725 while (tx_left
> 0) {
6726 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
6727 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
6731 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
6732 if (status
& DescOwn
)
6735 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
6736 tp
->TxDescArray
+ entry
);
6737 if (status
& LastFrag
) {
6739 bytes_compl
+= tx_skb
->skb
->len
;
6740 dev_kfree_skb_any(tx_skb
->skb
);
6747 if (tp
->dirty_tx
!= dirty_tx
) {
6748 netdev_completed_queue(tp
->dev
, pkts_compl
, bytes_compl
);
6750 u64_stats_update_begin(&tp
->tx_stats
.syncp
);
6751 tp
->tx_stats
.packets
+= pkts_compl
;
6752 tp
->tx_stats
.bytes
+= bytes_compl
;
6753 u64_stats_update_end(&tp
->tx_stats
.syncp
);
6755 tp
->dirty_tx
= dirty_tx
;
6756 /* Sync with rtl8169_start_xmit:
6757 * - publish dirty_tx ring index (write barrier)
6758 * - refresh cur_tx ring index and queue status (read barrier)
6759 * May the current thread miss the stopped queue condition,
6760 * a racing xmit thread can only have a right view of the
6764 if (netif_queue_stopped(dev
) &&
6765 TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
)) {
6766 netif_wake_queue(dev
);
6769 * 8168 hack: TxPoll requests are lost when the Tx packets are
6770 * too close. Let's kick an extra TxPoll request when a burst
6771 * of start_xmit activity is detected (if it is not detected,
6772 * it is slow enough). -- FR
6774 if (tp
->cur_tx
!= dirty_tx
) {
6775 void __iomem
*ioaddr
= tp
->mmio_addr
;
6777 RTL_W8(TxPoll
, NPQ
);
6782 static inline int rtl8169_fragmented_frame(u32 status
)
6784 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
6787 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
6789 u32 status
= opts1
& RxProtoMask
;
6791 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
6792 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
6793 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
6795 skb_checksum_none_assert(skb
);
6798 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
6799 struct rtl8169_private
*tp
,
6803 struct sk_buff
*skb
;
6804 struct device
*d
= &tp
->pci_dev
->dev
;
6806 data
= rtl8169_align(data
);
6807 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
6809 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
6811 memcpy(skb
->data
, data
, pkt_size
);
6812 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
6817 static int rtl_rx(struct net_device
*dev
, struct rtl8169_private
*tp
, u32 budget
)
6819 unsigned int cur_rx
, rx_left
;
6822 cur_rx
= tp
->cur_rx
;
6824 for (rx_left
= min(budget
, NUM_RX_DESC
); rx_left
> 0; rx_left
--, cur_rx
++) {
6825 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
6826 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
6830 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
6832 if (status
& DescOwn
)
6834 if (unlikely(status
& RxRES
)) {
6835 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
6837 dev
->stats
.rx_errors
++;
6838 if (status
& (RxRWT
| RxRUNT
))
6839 dev
->stats
.rx_length_errors
++;
6841 dev
->stats
.rx_crc_errors
++;
6842 if (status
& RxFOVF
) {
6843 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6844 dev
->stats
.rx_fifo_errors
++;
6846 if ((status
& (RxRUNT
| RxCRC
)) &&
6847 !(status
& (RxRWT
| RxFOVF
)) &&
6848 (dev
->features
& NETIF_F_RXALL
))
6851 struct sk_buff
*skb
;
6856 addr
= le64_to_cpu(desc
->addr
);
6857 if (likely(!(dev
->features
& NETIF_F_RXFCS
)))
6858 pkt_size
= (status
& 0x00003fff) - 4;
6860 pkt_size
= status
& 0x00003fff;
6863 * The driver does not support incoming fragmented
6864 * frames. They are seen as a symptom of over-mtu
6867 if (unlikely(rtl8169_fragmented_frame(status
))) {
6868 dev
->stats
.rx_dropped
++;
6869 dev
->stats
.rx_length_errors
++;
6870 goto release_descriptor
;
6873 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
6874 tp
, pkt_size
, addr
);
6876 dev
->stats
.rx_dropped
++;
6877 goto release_descriptor
;
6880 rtl8169_rx_csum(skb
, status
);
6881 skb_put(skb
, pkt_size
);
6882 skb
->protocol
= eth_type_trans(skb
, dev
);
6884 rtl8169_rx_vlan_tag(desc
, skb
);
6886 napi_gro_receive(&tp
->napi
, skb
);
6888 u64_stats_update_begin(&tp
->rx_stats
.syncp
);
6889 tp
->rx_stats
.packets
++;
6890 tp
->rx_stats
.bytes
+= pkt_size
;
6891 u64_stats_update_end(&tp
->rx_stats
.syncp
);
6896 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
6899 count
= cur_rx
- tp
->cur_rx
;
6900 tp
->cur_rx
= cur_rx
;
6905 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
6907 struct net_device
*dev
= dev_instance
;
6908 struct rtl8169_private
*tp
= netdev_priv(dev
);
6912 status
= rtl_get_events(tp
);
6913 if (status
&& status
!= 0xffff) {
6914 status
&= RTL_EVENT_NAPI
| tp
->event_slow
;
6918 rtl_irq_disable(tp
);
6919 napi_schedule(&tp
->napi
);
6922 return IRQ_RETVAL(handled
);
6926 * Workqueue context.
6928 static void rtl_slow_event_work(struct rtl8169_private
*tp
)
6930 struct net_device
*dev
= tp
->dev
;
6933 status
= rtl_get_events(tp
) & tp
->event_slow
;
6934 rtl_ack_events(tp
, status
);
6936 if (unlikely(status
& RxFIFOOver
)) {
6937 switch (tp
->mac_version
) {
6938 /* Work around for rx fifo overflow */
6939 case RTL_GIGA_MAC_VER_11
:
6940 netif_stop_queue(dev
);
6941 /* XXX - Hack alert. See rtl_task(). */
6942 set_bit(RTL_FLAG_TASK_RESET_PENDING
, tp
->wk
.flags
);
6948 if (unlikely(status
& SYSErr
))
6949 rtl8169_pcierr_interrupt(dev
);
6951 if (status
& LinkChg
)
6952 __rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
, true);
6954 rtl_irq_enable_all(tp
);
6957 static void rtl_task(struct work_struct
*work
)
6959 static const struct {
6961 void (*action
)(struct rtl8169_private
*);
6963 /* XXX - keep rtl_slow_event_work() as first element. */
6964 { RTL_FLAG_TASK_SLOW_PENDING
, rtl_slow_event_work
},
6965 { RTL_FLAG_TASK_RESET_PENDING
, rtl_reset_work
},
6966 { RTL_FLAG_TASK_PHY_PENDING
, rtl_phy_work
}
6968 struct rtl8169_private
*tp
=
6969 container_of(work
, struct rtl8169_private
, wk
.work
);
6970 struct net_device
*dev
= tp
->dev
;
6975 if (!netif_running(dev
) ||
6976 !test_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
))
6979 for (i
= 0; i
< ARRAY_SIZE(rtl_work
); i
++) {
6982 pending
= test_and_clear_bit(rtl_work
[i
].bitnr
, tp
->wk
.flags
);
6984 rtl_work
[i
].action(tp
);
6988 rtl_unlock_work(tp
);
6991 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
6993 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
6994 struct net_device
*dev
= tp
->dev
;
6995 u16 enable_mask
= RTL_EVENT_NAPI
| tp
->event_slow
;
6999 status
= rtl_get_events(tp
);
7000 rtl_ack_events(tp
, status
& ~tp
->event_slow
);
7002 if (status
& RTL_EVENT_NAPI_RX
)
7003 work_done
= rtl_rx(dev
, tp
, (u32
) budget
);
7005 if (status
& RTL_EVENT_NAPI_TX
)
7008 if (status
& tp
->event_slow
) {
7009 enable_mask
&= ~tp
->event_slow
;
7011 rtl_schedule_task(tp
, RTL_FLAG_TASK_SLOW_PENDING
);
7014 if (work_done
< budget
) {
7015 napi_complete(napi
);
7017 rtl_irq_enable(tp
, enable_mask
);
7024 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
7026 struct rtl8169_private
*tp
= netdev_priv(dev
);
7028 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
7031 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
7032 RTL_W32(RxMissed
, 0);
7035 static void rtl8169_down(struct net_device
*dev
)
7037 struct rtl8169_private
*tp
= netdev_priv(dev
);
7038 void __iomem
*ioaddr
= tp
->mmio_addr
;
7040 del_timer_sync(&tp
->timer
);
7042 napi_disable(&tp
->napi
);
7043 netif_stop_queue(dev
);
7045 rtl8169_hw_reset(tp
);
7047 * At this point device interrupts can not be enabled in any function,
7048 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7049 * and napi is disabled (rtl8169_poll).
7051 rtl8169_rx_missed(dev
, ioaddr
);
7053 /* Give a racing hard_start_xmit a few cycles to complete. */
7054 synchronize_sched();
7056 rtl8169_tx_clear(tp
);
7058 rtl8169_rx_clear(tp
);
7060 rtl_pll_power_down(tp
);
7063 static int rtl8169_close(struct net_device
*dev
)
7065 struct rtl8169_private
*tp
= netdev_priv(dev
);
7066 struct pci_dev
*pdev
= tp
->pci_dev
;
7068 pm_runtime_get_sync(&pdev
->dev
);
7070 /* Update counters before going down */
7071 rtl8169_update_counters(dev
);
7074 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7077 rtl_unlock_work(tp
);
7079 cancel_work_sync(&tp
->wk
.work
);
7081 free_irq(pdev
->irq
, dev
);
7083 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
7085 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
7087 tp
->TxDescArray
= NULL
;
7088 tp
->RxDescArray
= NULL
;
7090 pm_runtime_put_sync(&pdev
->dev
);
7095 #ifdef CONFIG_NET_POLL_CONTROLLER
7096 static void rtl8169_netpoll(struct net_device
*dev
)
7098 struct rtl8169_private
*tp
= netdev_priv(dev
);
7100 rtl8169_interrupt(tp
->pci_dev
->irq
, dev
);
7104 static int rtl_open(struct net_device
*dev
)
7106 struct rtl8169_private
*tp
= netdev_priv(dev
);
7107 void __iomem
*ioaddr
= tp
->mmio_addr
;
7108 struct pci_dev
*pdev
= tp
->pci_dev
;
7109 int retval
= -ENOMEM
;
7111 pm_runtime_get_sync(&pdev
->dev
);
7114 * Rx and Tx descriptors needs 256 bytes alignment.
7115 * dma_alloc_coherent provides more.
7117 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
7118 &tp
->TxPhyAddr
, GFP_KERNEL
);
7119 if (!tp
->TxDescArray
)
7120 goto err_pm_runtime_put
;
7122 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
7123 &tp
->RxPhyAddr
, GFP_KERNEL
);
7124 if (!tp
->RxDescArray
)
7127 retval
= rtl8169_init_ring(dev
);
7131 INIT_WORK(&tp
->wk
.work
, rtl_task
);
7135 rtl_request_firmware(tp
);
7137 retval
= request_irq(pdev
->irq
, rtl8169_interrupt
,
7138 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
7141 goto err_release_fw_2
;
7145 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7147 napi_enable(&tp
->napi
);
7149 rtl8169_init_phy(dev
, tp
);
7151 __rtl8169_set_features(dev
, dev
->features
);
7153 rtl_pll_power_up(tp
);
7157 netif_start_queue(dev
);
7159 rtl_unlock_work(tp
);
7161 tp
->saved_wolopts
= 0;
7162 pm_runtime_put_noidle(&pdev
->dev
);
7164 rtl8169_check_link_status(dev
, tp
, ioaddr
);
7169 rtl_release_firmware(tp
);
7170 rtl8169_rx_clear(tp
);
7172 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
7174 tp
->RxDescArray
= NULL
;
7176 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
7178 tp
->TxDescArray
= NULL
;
7180 pm_runtime_put_noidle(&pdev
->dev
);
7184 static struct rtnl_link_stats64
*
7185 rtl8169_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
7187 struct rtl8169_private
*tp
= netdev_priv(dev
);
7188 void __iomem
*ioaddr
= tp
->mmio_addr
;
7191 if (netif_running(dev
))
7192 rtl8169_rx_missed(dev
, ioaddr
);
7195 start
= u64_stats_fetch_begin_irq(&tp
->rx_stats
.syncp
);
7196 stats
->rx_packets
= tp
->rx_stats
.packets
;
7197 stats
->rx_bytes
= tp
->rx_stats
.bytes
;
7198 } while (u64_stats_fetch_retry_irq(&tp
->rx_stats
.syncp
, start
));
7202 start
= u64_stats_fetch_begin_irq(&tp
->tx_stats
.syncp
);
7203 stats
->tx_packets
= tp
->tx_stats
.packets
;
7204 stats
->tx_bytes
= tp
->tx_stats
.bytes
;
7205 } while (u64_stats_fetch_retry_irq(&tp
->tx_stats
.syncp
, start
));
7207 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
7208 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
7209 stats
->rx_length_errors
= dev
->stats
.rx_length_errors
;
7210 stats
->rx_errors
= dev
->stats
.rx_errors
;
7211 stats
->rx_crc_errors
= dev
->stats
.rx_crc_errors
;
7212 stats
->rx_fifo_errors
= dev
->stats
.rx_fifo_errors
;
7213 stats
->rx_missed_errors
= dev
->stats
.rx_missed_errors
;
7218 static void rtl8169_net_suspend(struct net_device
*dev
)
7220 struct rtl8169_private
*tp
= netdev_priv(dev
);
7222 if (!netif_running(dev
))
7225 netif_device_detach(dev
);
7226 netif_stop_queue(dev
);
7229 napi_disable(&tp
->napi
);
7230 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7231 rtl_unlock_work(tp
);
7233 rtl_pll_power_down(tp
);
7238 static int rtl8169_suspend(struct device
*device
)
7240 struct pci_dev
*pdev
= to_pci_dev(device
);
7241 struct net_device
*dev
= pci_get_drvdata(pdev
);
7243 rtl8169_net_suspend(dev
);
7248 static void __rtl8169_resume(struct net_device
*dev
)
7250 struct rtl8169_private
*tp
= netdev_priv(dev
);
7252 netif_device_attach(dev
);
7254 rtl_pll_power_up(tp
);
7257 napi_enable(&tp
->napi
);
7258 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7259 rtl_unlock_work(tp
);
7261 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
7264 static int rtl8169_resume(struct device
*device
)
7266 struct pci_dev
*pdev
= to_pci_dev(device
);
7267 struct net_device
*dev
= pci_get_drvdata(pdev
);
7268 struct rtl8169_private
*tp
= netdev_priv(dev
);
7270 rtl8169_init_phy(dev
, tp
);
7272 if (netif_running(dev
))
7273 __rtl8169_resume(dev
);
7278 static int rtl8169_runtime_suspend(struct device
*device
)
7280 struct pci_dev
*pdev
= to_pci_dev(device
);
7281 struct net_device
*dev
= pci_get_drvdata(pdev
);
7282 struct rtl8169_private
*tp
= netdev_priv(dev
);
7284 if (!tp
->TxDescArray
)
7288 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
7289 __rtl8169_set_wol(tp
, WAKE_ANY
);
7290 rtl_unlock_work(tp
);
7292 rtl8169_net_suspend(dev
);
7297 static int rtl8169_runtime_resume(struct device
*device
)
7299 struct pci_dev
*pdev
= to_pci_dev(device
);
7300 struct net_device
*dev
= pci_get_drvdata(pdev
);
7301 struct rtl8169_private
*tp
= netdev_priv(dev
);
7303 if (!tp
->TxDescArray
)
7307 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
7308 tp
->saved_wolopts
= 0;
7309 rtl_unlock_work(tp
);
7311 rtl8169_init_phy(dev
, tp
);
7313 __rtl8169_resume(dev
);
7318 static int rtl8169_runtime_idle(struct device
*device
)
7320 struct pci_dev
*pdev
= to_pci_dev(device
);
7321 struct net_device
*dev
= pci_get_drvdata(pdev
);
7322 struct rtl8169_private
*tp
= netdev_priv(dev
);
7324 return tp
->TxDescArray
? -EBUSY
: 0;
7327 static const struct dev_pm_ops rtl8169_pm_ops
= {
7328 .suspend
= rtl8169_suspend
,
7329 .resume
= rtl8169_resume
,
7330 .freeze
= rtl8169_suspend
,
7331 .thaw
= rtl8169_resume
,
7332 .poweroff
= rtl8169_suspend
,
7333 .restore
= rtl8169_resume
,
7334 .runtime_suspend
= rtl8169_runtime_suspend
,
7335 .runtime_resume
= rtl8169_runtime_resume
,
7336 .runtime_idle
= rtl8169_runtime_idle
,
7339 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7341 #else /* !CONFIG_PM */
7343 #define RTL8169_PM_OPS NULL
7345 #endif /* !CONFIG_PM */
7347 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
7349 void __iomem
*ioaddr
= tp
->mmio_addr
;
7351 /* WoL fails with 8168b when the receiver is disabled. */
7352 switch (tp
->mac_version
) {
7353 case RTL_GIGA_MAC_VER_11
:
7354 case RTL_GIGA_MAC_VER_12
:
7355 case RTL_GIGA_MAC_VER_17
:
7356 pci_clear_master(tp
->pci_dev
);
7358 RTL_W8(ChipCmd
, CmdRxEnb
);
7367 static void rtl_shutdown(struct pci_dev
*pdev
)
7369 struct net_device
*dev
= pci_get_drvdata(pdev
);
7370 struct rtl8169_private
*tp
= netdev_priv(dev
);
7371 struct device
*d
= &pdev
->dev
;
7373 pm_runtime_get_sync(d
);
7375 rtl8169_net_suspend(dev
);
7377 /* Restore original MAC address */
7378 rtl_rar_set(tp
, dev
->perm_addr
);
7380 rtl8169_hw_reset(tp
);
7382 if (system_state
== SYSTEM_POWER_OFF
) {
7383 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
7384 rtl_wol_suspend_quirk(tp
);
7385 rtl_wol_shutdown_quirk(tp
);
7388 pci_wake_from_d3(pdev
, true);
7389 pci_set_power_state(pdev
, PCI_D3hot
);
7392 pm_runtime_put_noidle(d
);
7395 static void rtl_remove_one(struct pci_dev
*pdev
)
7397 struct net_device
*dev
= pci_get_drvdata(pdev
);
7398 struct rtl8169_private
*tp
= netdev_priv(dev
);
7400 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
7401 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
7402 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
7403 r8168_check_dash(tp
)) {
7404 rtl8168_driver_stop(tp
);
7407 netif_napi_del(&tp
->napi
);
7409 unregister_netdev(dev
);
7411 rtl_release_firmware(tp
);
7413 if (pci_dev_run_wake(pdev
))
7414 pm_runtime_get_noresume(&pdev
->dev
);
7416 /* restore original MAC address */
7417 rtl_rar_set(tp
, dev
->perm_addr
);
7419 rtl_disable_msi(pdev
, tp
);
7420 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
7423 static const struct net_device_ops rtl_netdev_ops
= {
7424 .ndo_open
= rtl_open
,
7425 .ndo_stop
= rtl8169_close
,
7426 .ndo_get_stats64
= rtl8169_get_stats64
,
7427 .ndo_start_xmit
= rtl8169_start_xmit
,
7428 .ndo_tx_timeout
= rtl8169_tx_timeout
,
7429 .ndo_validate_addr
= eth_validate_addr
,
7430 .ndo_change_mtu
= rtl8169_change_mtu
,
7431 .ndo_fix_features
= rtl8169_fix_features
,
7432 .ndo_set_features
= rtl8169_set_features
,
7433 .ndo_set_mac_address
= rtl_set_mac_address
,
7434 .ndo_do_ioctl
= rtl8169_ioctl
,
7435 .ndo_set_rx_mode
= rtl_set_rx_mode
,
7436 #ifdef CONFIG_NET_POLL_CONTROLLER
7437 .ndo_poll_controller
= rtl8169_netpoll
,
7442 static const struct rtl_cfg_info
{
7443 void (*hw_start
)(struct net_device
*);
7444 unsigned int region
;
7449 } rtl_cfg_infos
[] = {
7451 .hw_start
= rtl_hw_start_8169
,
7454 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
,
7455 .features
= RTL_FEATURE_GMII
,
7456 .default_ver
= RTL_GIGA_MAC_VER_01
,
7459 .hw_start
= rtl_hw_start_8168
,
7462 .event_slow
= SYSErr
| LinkChg
| RxOverflow
,
7463 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
7464 .default_ver
= RTL_GIGA_MAC_VER_11
,
7467 .hw_start
= rtl_hw_start_8101
,
7470 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
|
7472 .features
= RTL_FEATURE_MSI
,
7473 .default_ver
= RTL_GIGA_MAC_VER_13
,
7477 /* Cfg9346_Unlock assumed. */
7478 static unsigned rtl_try_msi(struct rtl8169_private
*tp
,
7479 const struct rtl_cfg_info
*cfg
)
7481 void __iomem
*ioaddr
= tp
->mmio_addr
;
7485 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
7486 if (cfg
->features
& RTL_FEATURE_MSI
) {
7487 if (pci_enable_msi(tp
->pci_dev
)) {
7488 netif_info(tp
, hw
, tp
->dev
, "no MSI. Back to INTx.\n");
7491 msi
= RTL_FEATURE_MSI
;
7494 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
7495 RTL_W8(Config2
, cfg2
);
7499 DECLARE_RTL_COND(rtl_link_list_ready_cond
)
7501 void __iomem
*ioaddr
= tp
->mmio_addr
;
7503 return RTL_R8(MCU
) & LINK_LIST_RDY
;
7506 DECLARE_RTL_COND(rtl_rxtx_empty_cond
)
7508 void __iomem
*ioaddr
= tp
->mmio_addr
;
7510 return (RTL_R8(MCU
) & RXTX_EMPTY
) == RXTX_EMPTY
;
7513 static void rtl_hw_init_8168g(struct rtl8169_private
*tp
)
7515 void __iomem
*ioaddr
= tp
->mmio_addr
;
7518 tp
->ocp_base
= OCP_STD_PHY_BASE
;
7520 RTL_W32(MISC
, RTL_R32(MISC
) | RXDV_GATED_EN
);
7522 if (!rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 42))
7525 if (!rtl_udelay_loop_wait_high(tp
, &rtl_rxtx_empty_cond
, 100, 42))
7528 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) & ~(CmdTxEnb
| CmdRxEnb
));
7530 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
7532 data
= r8168_mac_ocp_read(tp
, 0xe8de);
7534 r8168_mac_ocp_write(tp
, 0xe8de, data
);
7536 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
7539 data
= r8168_mac_ocp_read(tp
, 0xe8de);
7541 r8168_mac_ocp_write(tp
, 0xe8de, data
);
7543 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
7547 static void rtl_hw_initialize(struct rtl8169_private
*tp
)
7549 switch (tp
->mac_version
) {
7550 case RTL_GIGA_MAC_VER_40
:
7551 case RTL_GIGA_MAC_VER_41
:
7552 case RTL_GIGA_MAC_VER_42
:
7553 case RTL_GIGA_MAC_VER_43
:
7554 case RTL_GIGA_MAC_VER_44
:
7555 case RTL_GIGA_MAC_VER_45
:
7556 case RTL_GIGA_MAC_VER_46
:
7557 case RTL_GIGA_MAC_VER_47
:
7558 case RTL_GIGA_MAC_VER_48
:
7559 rtl_hw_init_8168g(tp
);
7567 static int rtl_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
7569 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
7570 const unsigned int region
= cfg
->region
;
7571 struct rtl8169_private
*tp
;
7572 struct mii_if_info
*mii
;
7573 struct net_device
*dev
;
7574 void __iomem
*ioaddr
;
7578 if (netif_msg_drv(&debug
)) {
7579 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
7580 MODULENAME
, RTL8169_VERSION
);
7583 dev
= alloc_etherdev(sizeof (*tp
));
7589 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7590 dev
->netdev_ops
= &rtl_netdev_ops
;
7591 tp
= netdev_priv(dev
);
7594 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
7598 mii
->mdio_read
= rtl_mdio_read
;
7599 mii
->mdio_write
= rtl_mdio_write
;
7600 mii
->phy_id_mask
= 0x1f;
7601 mii
->reg_num_mask
= 0x1f;
7602 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
7604 /* disable ASPM completely as that cause random device stop working
7605 * problems as well as full system hangs for some PCIe devices users */
7606 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
7607 PCIE_LINK_STATE_CLKPM
);
7609 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7610 rc
= pci_enable_device(pdev
);
7612 netif_err(tp
, probe
, dev
, "enable failure\n");
7613 goto err_out_free_dev_1
;
7616 if (pci_set_mwi(pdev
) < 0)
7617 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
7619 /* make sure PCI base addr 1 is MMIO */
7620 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
7621 netif_err(tp
, probe
, dev
,
7622 "region #%d not an MMIO resource, aborting\n",
7628 /* check for weird/broken PCI region reporting */
7629 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
7630 netif_err(tp
, probe
, dev
,
7631 "Invalid PCI region size(s), aborting\n");
7636 rc
= pci_request_regions(pdev
, MODULENAME
);
7638 netif_err(tp
, probe
, dev
, "could not request regions\n");
7644 if ((sizeof(dma_addr_t
) > 4) &&
7645 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
7646 tp
->cp_cmd
|= PCIDAC
;
7647 dev
->features
|= NETIF_F_HIGHDMA
;
7649 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
7651 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
7652 goto err_out_free_res_3
;
7656 /* ioremap MMIO region */
7657 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
7659 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
7661 goto err_out_free_res_3
;
7663 tp
->mmio_addr
= ioaddr
;
7665 if (!pci_is_pcie(pdev
))
7666 netif_info(tp
, probe
, dev
, "not PCI Express\n");
7668 /* Identify chip attached to board */
7669 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
7673 rtl_irq_disable(tp
);
7675 rtl_hw_initialize(tp
);
7679 rtl_ack_events(tp
, 0xffff);
7681 pci_set_master(pdev
);
7683 rtl_init_mdio_ops(tp
);
7684 rtl_init_pll_power_ops(tp
);
7685 rtl_init_jumbo_ops(tp
);
7686 rtl_init_csi_ops(tp
);
7688 rtl8169_print_mac_version(tp
);
7690 chipset
= tp
->mac_version
;
7691 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
7693 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
7694 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
7695 RTL_W8(Config5
, RTL_R8(Config5
) & (BWF
| MWF
| UWF
| LanWake
| PMEStatus
));
7696 switch (tp
->mac_version
) {
7697 case RTL_GIGA_MAC_VER_34
:
7698 case RTL_GIGA_MAC_VER_35
:
7699 case RTL_GIGA_MAC_VER_36
:
7700 case RTL_GIGA_MAC_VER_37
:
7701 case RTL_GIGA_MAC_VER_38
:
7702 case RTL_GIGA_MAC_VER_40
:
7703 case RTL_GIGA_MAC_VER_41
:
7704 case RTL_GIGA_MAC_VER_42
:
7705 case RTL_GIGA_MAC_VER_43
:
7706 case RTL_GIGA_MAC_VER_44
:
7707 case RTL_GIGA_MAC_VER_45
:
7708 case RTL_GIGA_MAC_VER_46
:
7709 case RTL_GIGA_MAC_VER_47
:
7710 case RTL_GIGA_MAC_VER_48
:
7711 if (rtl_eri_read(tp
, 0xdc, ERIAR_EXGMAC
) & MagicPacket_v2
)
7712 tp
->features
|= RTL_FEATURE_WOL
;
7713 if ((RTL_R8(Config3
) & LinkUp
) != 0)
7714 tp
->features
|= RTL_FEATURE_WOL
;
7717 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
7718 tp
->features
|= RTL_FEATURE_WOL
;
7721 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
7722 tp
->features
|= RTL_FEATURE_WOL
;
7723 tp
->features
|= rtl_try_msi(tp
, cfg
);
7724 RTL_W8(Cfg9346
, Cfg9346_Lock
);
7726 if (rtl_tbi_enabled(tp
)) {
7727 tp
->set_speed
= rtl8169_set_speed_tbi
;
7728 tp
->get_settings
= rtl8169_gset_tbi
;
7729 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
7730 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
7731 tp
->link_ok
= rtl8169_tbi_link_ok
;
7732 tp
->do_ioctl
= rtl_tbi_ioctl
;
7734 tp
->set_speed
= rtl8169_set_speed_xmii
;
7735 tp
->get_settings
= rtl8169_gset_xmii
;
7736 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
7737 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
7738 tp
->link_ok
= rtl8169_xmii_link_ok
;
7739 tp
->do_ioctl
= rtl_xmii_ioctl
;
7742 mutex_init(&tp
->wk
.mutex
);
7743 u64_stats_init(&tp
->rx_stats
.syncp
);
7744 u64_stats_init(&tp
->tx_stats
.syncp
);
7746 /* Get MAC address */
7747 if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
7748 tp
->mac_version
== RTL_GIGA_MAC_VER_36
||
7749 tp
->mac_version
== RTL_GIGA_MAC_VER_37
||
7750 tp
->mac_version
== RTL_GIGA_MAC_VER_38
||
7751 tp
->mac_version
== RTL_GIGA_MAC_VER_40
||
7752 tp
->mac_version
== RTL_GIGA_MAC_VER_41
||
7753 tp
->mac_version
== RTL_GIGA_MAC_VER_42
||
7754 tp
->mac_version
== RTL_GIGA_MAC_VER_43
||
7755 tp
->mac_version
== RTL_GIGA_MAC_VER_44
||
7756 tp
->mac_version
== RTL_GIGA_MAC_VER_45
||
7757 tp
->mac_version
== RTL_GIGA_MAC_VER_46
||
7758 tp
->mac_version
== RTL_GIGA_MAC_VER_47
||
7759 tp
->mac_version
== RTL_GIGA_MAC_VER_48
) {
7762 *(u32
*)&mac_addr
[0] = rtl_eri_read(tp
, 0xe0, ERIAR_EXGMAC
);
7763 *(u16
*)&mac_addr
[2] = rtl_eri_read(tp
, 0xe4, ERIAR_EXGMAC
);
7765 if (is_valid_ether_addr((u8
*)mac_addr
))
7766 rtl_rar_set(tp
, (u8
*)mac_addr
);
7768 for (i
= 0; i
< ETH_ALEN
; i
++)
7769 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
7771 dev
->ethtool_ops
= &rtl8169_ethtool_ops
;
7772 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
7774 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
7776 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7777 * properly for all devices */
7778 dev
->features
|= NETIF_F_RXCSUM
|
7779 NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
;
7781 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
7782 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
|
7783 NETIF_F_HW_VLAN_CTAG_RX
;
7784 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
7787 tp
->cp_cmd
|= RxChkSum
| RxVlan
;
7790 * Pretend we are using VLANs; This bypasses a nasty bug where
7791 * Interrupts stop flowing on high load on 8110SCd controllers.
7793 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
7794 /* Disallow toggling */
7795 dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_RX
;
7797 if (tp
->txd_version
== RTL_TD_0
)
7798 tp
->tso_csum
= rtl8169_tso_csum_v1
;
7799 else if (tp
->txd_version
== RTL_TD_1
) {
7800 tp
->tso_csum
= rtl8169_tso_csum_v2
;
7801 dev
->hw_features
|= NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
;
7805 dev
->hw_features
|= NETIF_F_RXALL
;
7806 dev
->hw_features
|= NETIF_F_RXFCS
;
7808 tp
->hw_start
= cfg
->hw_start
;
7809 tp
->event_slow
= cfg
->event_slow
;
7811 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
7812 ~(RxBOVF
| RxFOVF
) : ~0;
7814 init_timer(&tp
->timer
);
7815 tp
->timer
.data
= (unsigned long) dev
;
7816 tp
->timer
.function
= rtl8169_phy_timer
;
7818 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
7820 rc
= register_netdev(dev
);
7824 pci_set_drvdata(pdev
, dev
);
7826 netif_info(tp
, probe
, dev
, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7827 rtl_chip_infos
[chipset
].name
, ioaddr
, dev
->dev_addr
,
7828 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), pdev
->irq
);
7829 if (rtl_chip_infos
[chipset
].jumbo_max
!= JUMBO_1K
) {
7830 netif_info(tp
, probe
, dev
, "jumbo features [frames: %d bytes, "
7831 "tx checksumming: %s]\n",
7832 rtl_chip_infos
[chipset
].jumbo_max
,
7833 rtl_chip_infos
[chipset
].jumbo_tx_csum
? "ok" : "ko");
7836 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
7837 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
7838 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
7839 r8168_check_dash(tp
)) {
7840 rtl8168_driver_start(tp
);
7843 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
7845 if (pci_dev_run_wake(pdev
))
7846 pm_runtime_put_noidle(&pdev
->dev
);
7848 netif_carrier_off(dev
);
7854 netif_napi_del(&tp
->napi
);
7855 rtl_disable_msi(pdev
, tp
);
7858 pci_release_regions(pdev
);
7860 pci_clear_mwi(pdev
);
7861 pci_disable_device(pdev
);
7867 static struct pci_driver rtl8169_pci_driver
= {
7869 .id_table
= rtl8169_pci_tbl
,
7870 .probe
= rtl_init_one
,
7871 .remove
= rtl_remove_one
,
7872 .shutdown
= rtl_shutdown
,
7873 .driver
.pm
= RTL8169_PM_OPS
,
7876 module_pci_driver(rtl8169_pci_driver
);