2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
50 #define assert(expr) \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
53 #expr,__FILE__,__func__,__LINE__); \
55 #define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
58 #define assert(expr) do {} while (0)
59 #define dprintk(fmt, args...) do {} while (0)
60 #endif /* RTL8169_DEBUG */
62 #define R8169_MSG_DEFAULT \
63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
65 #define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit
= 32;
72 /* MAC address length */
73 #define MAC_ADDR_LEN 6
75 #define MAX_READ_REQUEST_SHIFT 12
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
78 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
80 #define R8169_REGS_SIZE 256
81 #define R8169_NAPI_WEIGHT 64
82 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
83 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
84 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
85 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
86 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
88 #define RTL8169_TX_TIMEOUT (6*HZ)
89 #define RTL8169_PHY_TIMEOUT (10*HZ)
91 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
92 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
93 #define RTL_EEPROM_SIG_ADDR 0x0000
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
104 RTL_GIGA_MAC_VER_01
= 0,
140 RTL_GIGA_MAC_NONE
= 0xff,
143 enum rtl_tx_desc_version
{
148 #define _R(NAME,TD,FW) \
149 { .name = NAME, .txd_version = TD, .fw_name = FW }
151 static const struct {
153 enum rtl_tx_desc_version txd_version
;
155 } rtl_chip_infos
[] = {
157 [RTL_GIGA_MAC_VER_01
] =
158 _R("RTL8169", RTL_TD_0
, NULL
),
159 [RTL_GIGA_MAC_VER_02
] =
160 _R("RTL8169s", RTL_TD_0
, NULL
),
161 [RTL_GIGA_MAC_VER_03
] =
162 _R("RTL8110s", RTL_TD_0
, NULL
),
163 [RTL_GIGA_MAC_VER_04
] =
164 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
),
165 [RTL_GIGA_MAC_VER_05
] =
166 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
167 [RTL_GIGA_MAC_VER_06
] =
168 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
170 [RTL_GIGA_MAC_VER_07
] =
171 _R("RTL8102e", RTL_TD_1
, NULL
),
172 [RTL_GIGA_MAC_VER_08
] =
173 _R("RTL8102e", RTL_TD_1
, NULL
),
174 [RTL_GIGA_MAC_VER_09
] =
175 _R("RTL8102e", RTL_TD_1
, NULL
),
176 [RTL_GIGA_MAC_VER_10
] =
177 _R("RTL8101e", RTL_TD_0
, NULL
),
178 [RTL_GIGA_MAC_VER_11
] =
179 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
180 [RTL_GIGA_MAC_VER_12
] =
181 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
182 [RTL_GIGA_MAC_VER_13
] =
183 _R("RTL8101e", RTL_TD_0
, NULL
),
184 [RTL_GIGA_MAC_VER_14
] =
185 _R("RTL8100e", RTL_TD_0
, NULL
),
186 [RTL_GIGA_MAC_VER_15
] =
187 _R("RTL8100e", RTL_TD_0
, NULL
),
188 [RTL_GIGA_MAC_VER_16
] =
189 _R("RTL8101e", RTL_TD_0
, NULL
),
190 [RTL_GIGA_MAC_VER_17
] =
191 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
192 [RTL_GIGA_MAC_VER_18
] =
193 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
194 [RTL_GIGA_MAC_VER_19
] =
195 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
196 [RTL_GIGA_MAC_VER_20
] =
197 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
198 [RTL_GIGA_MAC_VER_21
] =
199 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
200 [RTL_GIGA_MAC_VER_22
] =
201 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
202 [RTL_GIGA_MAC_VER_23
] =
203 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
204 [RTL_GIGA_MAC_VER_24
] =
205 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
206 [RTL_GIGA_MAC_VER_25
] =
207 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
),
208 [RTL_GIGA_MAC_VER_26
] =
209 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
),
210 [RTL_GIGA_MAC_VER_27
] =
211 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
212 [RTL_GIGA_MAC_VER_28
] =
213 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
214 [RTL_GIGA_MAC_VER_29
] =
215 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
216 [RTL_GIGA_MAC_VER_30
] =
217 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
218 [RTL_GIGA_MAC_VER_31
] =
219 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
220 [RTL_GIGA_MAC_VER_32
] =
221 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
),
222 [RTL_GIGA_MAC_VER_33
] =
223 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
),
224 [RTL_GIGA_MAC_VER_34
] =
225 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
),
226 [RTL_GIGA_MAC_VER_35
] =
227 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_1
),
228 [RTL_GIGA_MAC_VER_36
] =
229 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_2
)
239 static void rtl_hw_start_8169(struct net_device
*);
240 static void rtl_hw_start_8168(struct net_device
*);
241 static void rtl_hw_start_8101(struct net_device
*);
243 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
244 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
245 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
246 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
247 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
248 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
249 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
250 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
251 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
252 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
253 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
254 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
256 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
260 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
262 static int rx_buf_sz
= 16383;
269 MAC0
= 0, /* Ethernet hardware address. */
271 MAR0
= 8, /* Multicast filter. */
272 CounterAddrLow
= 0x10,
273 CounterAddrHigh
= 0x14,
274 TxDescStartAddrLow
= 0x20,
275 TxDescStartAddrHigh
= 0x24,
276 TxHDescStartAddrLow
= 0x28,
277 TxHDescStartAddrHigh
= 0x2c,
286 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
287 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
290 #define RX128_INT_EN (1 << 15) /* 8111c and later */
291 #define RX_MULTI_EN (1 << 14) /* 8111c only */
292 #define RXCFG_FIFO_SHIFT 13
293 /* No threshold before first PCI xfer */
294 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
295 #define RXCFG_DMA_SHIFT 8
296 /* Unlimited maximum PCI burst. */
297 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
313 RxDescAddrLow
= 0xe4,
314 RxDescAddrHigh
= 0xe8,
315 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
317 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
319 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
321 #define TxPacketMax (8064 >> 7)
322 #define EarlySize 0x27
325 FuncEventMask
= 0xf4,
326 FuncPresetState
= 0xf8,
327 FuncForceEvent
= 0xfc,
330 enum rtl8110_registers
{
336 enum rtl8168_8101_registers
{
339 #define CSIAR_FLAG 0x80000000
340 #define CSIAR_WRITE_CMD 0x80000000
341 #define CSIAR_BYTE_ENABLE 0x0f
342 #define CSIAR_BYTE_ENABLE_SHIFT 12
343 #define CSIAR_ADDR_MASK 0x0fff
346 #define EPHYAR_FLAG 0x80000000
347 #define EPHYAR_WRITE_CMD 0x80000000
348 #define EPHYAR_REG_MASK 0x1f
349 #define EPHYAR_REG_SHIFT 16
350 #define EPHYAR_DATA_MASK 0xffff
352 #define PFM_EN (1 << 6)
354 #define FIX_NAK_1 (1 << 4)
355 #define FIX_NAK_2 (1 << 3)
358 #define NOW_IS_OOB (1 << 7)
359 #define EN_NDP (1 << 3)
360 #define EN_OOB_RESET (1 << 2)
362 #define EFUSEAR_FLAG 0x80000000
363 #define EFUSEAR_WRITE_CMD 0x80000000
364 #define EFUSEAR_READ_CMD 0x00000000
365 #define EFUSEAR_REG_MASK 0x03ff
366 #define EFUSEAR_REG_SHIFT 8
367 #define EFUSEAR_DATA_MASK 0xff
370 enum rtl8168_registers
{
375 #define ERIAR_FLAG 0x80000000
376 #define ERIAR_WRITE_CMD 0x80000000
377 #define ERIAR_READ_CMD 0x00000000
378 #define ERIAR_ADDR_BYTE_ALIGN 4
379 #define ERIAR_TYPE_SHIFT 16
380 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
381 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
382 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
383 #define ERIAR_MASK_SHIFT 12
384 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
385 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
386 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
387 EPHY_RXER_NUM
= 0x7c,
388 OCPDR
= 0xb0, /* OCP GPHY access */
389 #define OCPDR_WRITE_CMD 0x80000000
390 #define OCPDR_READ_CMD 0x00000000
391 #define OCPDR_REG_MASK 0x7f
392 #define OCPDR_GPHY_REG_SHIFT 16
393 #define OCPDR_DATA_MASK 0xffff
395 #define OCPAR_FLAG 0x80000000
396 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
397 #define OCPAR_GPHY_READ_CMD 0x0000f060
398 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
399 MISC
= 0xf0, /* 8168e only. */
400 #define TXPLA_RST (1 << 29)
401 #define PWM_EN (1 << 22)
404 enum rtl_register_content
{
405 /* InterruptStatusBits */
409 TxDescUnavail
= 0x0080,
433 /* TXPoll register p.5 */
434 HPQ
= 0x80, /* Poll cmd on the high prio queue */
435 NPQ
= 0x40, /* Poll cmd on the low prio queue */
436 FSWInt
= 0x01, /* Forced software interrupt */
440 Cfg9346_Unlock
= 0xc0,
445 AcceptBroadcast
= 0x08,
446 AcceptMulticast
= 0x04,
448 AcceptAllPhys
= 0x01,
449 #define RX_CONFIG_ACCEPT_MASK 0x3f
452 TxInterFrameGapShift
= 24,
453 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
455 /* Config1 register p.24 */
458 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
459 Speed_down
= (1 << 4),
463 PMEnable
= (1 << 0), /* Power Management Enable */
465 /* Config2 register p. 25 */
466 PCI_Clock_66MHz
= 0x01,
467 PCI_Clock_33MHz
= 0x00,
469 /* Config3 register p.25 */
470 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
471 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
472 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
474 /* Config5 register p.27 */
475 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
476 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
477 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
479 LanWake
= (1 << 1), /* LanWake enable/disable */
480 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
483 TBIReset
= 0x80000000,
484 TBILoopback
= 0x40000000,
485 TBINwEnable
= 0x20000000,
486 TBINwRestart
= 0x10000000,
487 TBILinkOk
= 0x02000000,
488 TBINwComplete
= 0x01000000,
491 EnableBist
= (1 << 15), // 8168 8101
492 Mac_dbgo_oe
= (1 << 14), // 8168 8101
493 Normal_mode
= (1 << 13), // unused
494 Force_half_dup
= (1 << 12), // 8168 8101
495 Force_rxflow_en
= (1 << 11), // 8168 8101
496 Force_txflow_en
= (1 << 10), // 8168 8101
497 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
498 ASF
= (1 << 8), // 8168 8101
499 PktCntrDisable
= (1 << 7), // 8168 8101
500 Mac_dbgo_sel
= 0x001c, // 8168
505 INTT_0
= 0x0000, // 8168
506 INTT_1
= 0x0001, // 8168
507 INTT_2
= 0x0002, // 8168
508 INTT_3
= 0x0003, // 8168
510 /* rtl8169_PHYstatus */
521 TBILinkOK
= 0x02000000,
523 /* DumpCounterCommand */
528 /* First doubleword. */
529 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
530 RingEnd
= (1 << 30), /* End of descriptor ring */
531 FirstFrag
= (1 << 29), /* First segment of a packet */
532 LastFrag
= (1 << 28), /* Final segment of a packet */
536 enum rtl_tx_desc_bit
{
537 /* First doubleword. */
538 TD_LSO
= (1 << 27), /* Large Send Offload */
539 #define TD_MSS_MAX 0x07ffu /* MSS value */
541 /* Second doubleword. */
542 TxVlanTag
= (1 << 17), /* Add VLAN tag */
545 /* 8169, 8168b and 810x except 8102e. */
546 enum rtl_tx_desc_bit_0
{
547 /* First doubleword. */
548 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
549 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
550 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
551 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
554 /* 8102e, 8168c and beyond. */
555 enum rtl_tx_desc_bit_1
{
556 /* Second doubleword. */
557 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
558 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
559 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
560 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
563 static const struct rtl_tx_desc_info
{
570 } tx_desc_info
[] = {
573 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
574 .tcp
= TD0_IP_CS
| TD0_TCP_CS
576 .mss_shift
= TD0_MSS_SHIFT
,
581 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
582 .tcp
= TD1_IP_CS
| TD1_TCP_CS
584 .mss_shift
= TD1_MSS_SHIFT
,
589 enum rtl_rx_desc_bit
{
591 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
592 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
594 #define RxProtoUDP (PID1)
595 #define RxProtoTCP (PID0)
596 #define RxProtoIP (PID1 | PID0)
597 #define RxProtoMask RxProtoIP
599 IPFail
= (1 << 16), /* IP checksum failed */
600 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
601 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
602 RxVlanTag
= (1 << 16), /* VLAN tag available */
605 #define RsvdMask 0x3fffc000
622 u8 __pad
[sizeof(void *) - sizeof(u32
)];
626 RTL_FEATURE_WOL
= (1 << 0),
627 RTL_FEATURE_MSI
= (1 << 1),
628 RTL_FEATURE_GMII
= (1 << 2),
631 struct rtl8169_counters
{
638 __le32 tx_one_collision
;
639 __le32 tx_multi_collision
;
647 struct rtl8169_private
{
648 void __iomem
*mmio_addr
; /* memory map physical address */
649 struct pci_dev
*pci_dev
;
650 struct net_device
*dev
;
651 struct napi_struct napi
;
656 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
657 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
660 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
661 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
662 dma_addr_t TxPhyAddr
;
663 dma_addr_t RxPhyAddr
;
664 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
665 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
666 struct timer_list timer
;
673 void (*write
)(void __iomem
*, int, int);
674 int (*read
)(void __iomem
*, int);
677 struct pll_power_ops
{
678 void (*down
)(struct rtl8169_private
*);
679 void (*up
)(struct rtl8169_private
*);
682 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
683 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
684 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
685 void (*hw_start
)(struct net_device
*);
686 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
687 unsigned int (*link_ok
)(void __iomem
*);
688 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
689 struct delayed_work task
;
692 struct mii_if_info mii
;
693 struct rtl8169_counters counters
;
698 const struct firmware
*fw
;
700 #define RTL_VER_SIZE 32
702 char version
[RTL_VER_SIZE
];
704 struct rtl_fw_phy_action
{
709 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
712 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
713 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
714 module_param(use_dac
, int, 0);
715 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
716 module_param_named(debug
, debug
.msg_enable
, int, 0);
717 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
718 MODULE_LICENSE("GPL");
719 MODULE_VERSION(RTL8169_VERSION
);
720 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
721 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
722 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
723 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
724 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
725 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
726 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
727 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
729 static int rtl8169_open(struct net_device
*dev
);
730 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
731 struct net_device
*dev
);
732 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
733 static int rtl8169_init_ring(struct net_device
*dev
);
734 static void rtl_hw_start(struct net_device
*dev
);
735 static int rtl8169_close(struct net_device
*dev
);
736 static void rtl_set_rx_mode(struct net_device
*dev
);
737 static void rtl8169_tx_timeout(struct net_device
*dev
);
738 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
739 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
740 void __iomem
*, u32 budget
);
741 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
742 static void rtl8169_down(struct net_device
*dev
);
743 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
744 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
746 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
748 void __iomem
*ioaddr
= tp
->mmio_addr
;
751 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
752 for (i
= 0; i
< 20; i
++) {
754 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
757 return RTL_R32(OCPDR
);
760 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
762 void __iomem
*ioaddr
= tp
->mmio_addr
;
765 RTL_W32(OCPDR
, data
);
766 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
767 for (i
= 0; i
< 20; i
++) {
769 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
774 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
776 void __iomem
*ioaddr
= tp
->mmio_addr
;
780 RTL_W32(ERIAR
, 0x800010e8);
782 for (i
= 0; i
< 5; i
++) {
784 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
788 ocp_write(tp
, 0x1, 0x30, 0x00000001);
791 #define OOB_CMD_RESET 0x00
792 #define OOB_CMD_DRIVER_START 0x05
793 #define OOB_CMD_DRIVER_STOP 0x06
795 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
797 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
800 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
805 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
807 reg
= rtl8168_get_ocp_reg(tp
);
809 for (i
= 0; i
< 10; i
++) {
811 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
816 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
821 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
823 reg
= rtl8168_get_ocp_reg(tp
);
825 for (i
= 0; i
< 10; i
++) {
827 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
832 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
834 u16 reg
= rtl8168_get_ocp_reg(tp
);
836 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
839 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
843 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
845 for (i
= 20; i
> 0; i
--) {
847 * Check if the RTL8169 has completed writing to the specified
850 if (!(RTL_R32(PHYAR
) & 0x80000000))
855 * According to hardware specs a 20us delay is required after write
856 * complete indication, but before sending next command.
861 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
865 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
867 for (i
= 20; i
> 0; i
--) {
869 * Check if the RTL8169 has completed retrieving data from
870 * the specified MII register.
872 if (RTL_R32(PHYAR
) & 0x80000000) {
873 value
= RTL_R32(PHYAR
) & 0xffff;
879 * According to hardware specs a 20us delay is required after read
880 * complete indication, but before sending next command.
887 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
891 RTL_W32(OCPDR
, data
|
892 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
893 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
894 RTL_W32(EPHY_RXER_NUM
, 0);
896 for (i
= 0; i
< 100; i
++) {
898 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
903 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
905 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
906 (value
& OCPDR_DATA_MASK
));
909 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
913 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
916 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
917 RTL_W32(EPHY_RXER_NUM
, 0);
919 for (i
= 0; i
< 100; i
++) {
921 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
925 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
928 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
930 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
932 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
935 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
937 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
940 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
942 r8168dp_2_mdio_start(ioaddr
);
944 r8169_mdio_write(ioaddr
, reg_addr
, value
);
946 r8168dp_2_mdio_stop(ioaddr
);
949 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
953 r8168dp_2_mdio_start(ioaddr
);
955 value
= r8169_mdio_read(ioaddr
, reg_addr
);
957 r8168dp_2_mdio_stop(ioaddr
);
962 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
964 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
967 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
969 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
972 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
974 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
977 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
981 val
= rtl_readphy(tp
, reg_addr
);
982 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
985 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
988 struct rtl8169_private
*tp
= netdev_priv(dev
);
990 rtl_writephy(tp
, location
, val
);
993 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
995 struct rtl8169_private
*tp
= netdev_priv(dev
);
997 return rtl_readphy(tp
, location
);
1000 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
1004 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1005 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1007 for (i
= 0; i
< 100; i
++) {
1008 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
1014 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
1019 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1021 for (i
= 0; i
< 100; i
++) {
1022 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
1023 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
1032 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
1036 RTL_W32(CSIDR
, value
);
1037 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
1038 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1040 for (i
= 0; i
< 100; i
++) {
1041 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
1047 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
1052 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
1053 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1055 for (i
= 0; i
< 100; i
++) {
1056 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
1057 value
= RTL_R32(CSIDR
);
1067 void rtl_eri_write(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 val
, int type
)
1071 BUG_ON((addr
& 3) || (mask
== 0));
1072 RTL_W32(ERIDR
, val
);
1073 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1075 for (i
= 0; i
< 100; i
++) {
1076 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
1082 static u32
rtl_eri_read(void __iomem
*ioaddr
, int addr
, int type
)
1087 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1089 for (i
= 0; i
< 100; i
++) {
1090 if (RTL_R32(ERIAR
) & ERIAR_FLAG
) {
1091 value
= RTL_R32(ERIDR
);
1101 rtl_w1w0_eri(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 p
, u32 m
, int type
)
1105 val
= rtl_eri_read(ioaddr
, addr
, type
);
1106 rtl_eri_write(ioaddr
, addr
, mask
, (val
& ~m
) | p
, type
);
1115 static void rtl_write_exgmac_batch(void __iomem
*ioaddr
,
1116 const struct exgmac_reg
*r
, int len
)
1119 rtl_eri_write(ioaddr
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1124 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1129 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1131 for (i
= 0; i
< 300; i
++) {
1132 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1133 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1142 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
1144 RTL_W16(IntrMask
, 0x0000);
1146 RTL_W16(IntrStatus
, 0xffff);
1149 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1151 void __iomem
*ioaddr
= tp
->mmio_addr
;
1153 return RTL_R32(TBICSR
) & TBIReset
;
1156 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1158 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1161 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1163 return RTL_R32(TBICSR
) & TBILinkOk
;
1166 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1168 return RTL_R8(PHYstatus
) & LinkStatus
;
1171 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1173 void __iomem
*ioaddr
= tp
->mmio_addr
;
1175 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1178 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1182 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1183 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1186 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1188 void __iomem
*ioaddr
= tp
->mmio_addr
;
1189 struct net_device
*dev
= tp
->dev
;
1191 if (!netif_running(dev
))
1194 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
1195 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1196 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1197 0x00000011, ERIAR_EXGMAC
);
1198 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1199 0x00000005, ERIAR_EXGMAC
);
1200 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1201 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1202 0x0000001f, ERIAR_EXGMAC
);
1203 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1204 0x00000005, ERIAR_EXGMAC
);
1206 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1207 0x0000001f, ERIAR_EXGMAC
);
1208 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1209 0x0000003f, ERIAR_EXGMAC
);
1211 /* Reset packet filter */
1212 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1214 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1216 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1217 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1218 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1219 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1220 0x00000011, ERIAR_EXGMAC
);
1221 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1222 0x00000005, ERIAR_EXGMAC
);
1224 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1225 0x0000001f, ERIAR_EXGMAC
);
1226 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1227 0x0000003f, ERIAR_EXGMAC
);
1232 static void __rtl8169_check_link_status(struct net_device
*dev
,
1233 struct rtl8169_private
*tp
,
1234 void __iomem
*ioaddr
, bool pm
)
1236 unsigned long flags
;
1238 spin_lock_irqsave(&tp
->lock
, flags
);
1239 if (tp
->link_ok(ioaddr
)) {
1240 rtl_link_chg_patch(tp
);
1241 /* This is to cancel a scheduled suspend if there's one. */
1243 pm_request_resume(&tp
->pci_dev
->dev
);
1244 netif_carrier_on(dev
);
1245 if (net_ratelimit())
1246 netif_info(tp
, ifup
, dev
, "link up\n");
1248 netif_carrier_off(dev
);
1249 netif_info(tp
, ifdown
, dev
, "link down\n");
1251 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
1253 spin_unlock_irqrestore(&tp
->lock
, flags
);
1256 static void rtl8169_check_link_status(struct net_device
*dev
,
1257 struct rtl8169_private
*tp
,
1258 void __iomem
*ioaddr
)
1260 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1263 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1265 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1267 void __iomem
*ioaddr
= tp
->mmio_addr
;
1271 options
= RTL_R8(Config1
);
1272 if (!(options
& PMEnable
))
1275 options
= RTL_R8(Config3
);
1276 if (options
& LinkUp
)
1277 wolopts
|= WAKE_PHY
;
1278 if (options
& MagicPacket
)
1279 wolopts
|= WAKE_MAGIC
;
1281 options
= RTL_R8(Config5
);
1283 wolopts
|= WAKE_UCAST
;
1285 wolopts
|= WAKE_BCAST
;
1287 wolopts
|= WAKE_MCAST
;
1292 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1294 struct rtl8169_private
*tp
= netdev_priv(dev
);
1296 spin_lock_irq(&tp
->lock
);
1298 wol
->supported
= WAKE_ANY
;
1299 wol
->wolopts
= __rtl8169_get_wol(tp
);
1301 spin_unlock_irq(&tp
->lock
);
1304 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1306 void __iomem
*ioaddr
= tp
->mmio_addr
;
1308 static const struct {
1313 { WAKE_ANY
, Config1
, PMEnable
},
1314 { WAKE_PHY
, Config3
, LinkUp
},
1315 { WAKE_MAGIC
, Config3
, MagicPacket
},
1316 { WAKE_UCAST
, Config5
, UWF
},
1317 { WAKE_BCAST
, Config5
, BWF
},
1318 { WAKE_MCAST
, Config5
, MWF
},
1319 { WAKE_ANY
, Config5
, LanWake
}
1322 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1324 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1325 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1326 if (wolopts
& cfg
[i
].opt
)
1327 options
|= cfg
[i
].mask
;
1328 RTL_W8(cfg
[i
].reg
, options
);
1331 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1334 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1336 struct rtl8169_private
*tp
= netdev_priv(dev
);
1338 spin_lock_irq(&tp
->lock
);
1341 tp
->features
|= RTL_FEATURE_WOL
;
1343 tp
->features
&= ~RTL_FEATURE_WOL
;
1344 __rtl8169_set_wol(tp
, wol
->wolopts
);
1345 spin_unlock_irq(&tp
->lock
);
1347 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1352 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1354 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1357 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1358 struct ethtool_drvinfo
*info
)
1360 struct rtl8169_private
*tp
= netdev_priv(dev
);
1361 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1363 strcpy(info
->driver
, MODULENAME
);
1364 strcpy(info
->version
, RTL8169_VERSION
);
1365 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
1366 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1367 strcpy(info
->fw_version
, IS_ERR_OR_NULL(rtl_fw
) ? "N/A" :
1371 static int rtl8169_get_regs_len(struct net_device
*dev
)
1373 return R8169_REGS_SIZE
;
1376 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1377 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1379 struct rtl8169_private
*tp
= netdev_priv(dev
);
1380 void __iomem
*ioaddr
= tp
->mmio_addr
;
1384 reg
= RTL_R32(TBICSR
);
1385 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1386 (duplex
== DUPLEX_FULL
)) {
1387 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1388 } else if (autoneg
== AUTONEG_ENABLE
)
1389 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1391 netif_warn(tp
, link
, dev
,
1392 "incorrect speed setting refused in TBI mode\n");
1399 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1400 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1402 struct rtl8169_private
*tp
= netdev_priv(dev
);
1403 int giga_ctrl
, bmcr
;
1406 rtl_writephy(tp
, 0x1f, 0x0000);
1408 if (autoneg
== AUTONEG_ENABLE
) {
1411 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1412 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1413 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1415 if (adv
& ADVERTISED_10baseT_Half
)
1416 auto_nego
|= ADVERTISE_10HALF
;
1417 if (adv
& ADVERTISED_10baseT_Full
)
1418 auto_nego
|= ADVERTISE_10FULL
;
1419 if (adv
& ADVERTISED_100baseT_Half
)
1420 auto_nego
|= ADVERTISE_100HALF
;
1421 if (adv
& ADVERTISED_100baseT_Full
)
1422 auto_nego
|= ADVERTISE_100FULL
;
1424 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1426 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1427 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1429 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1430 if (tp
->mii
.supports_gmii
) {
1431 if (adv
& ADVERTISED_1000baseT_Half
)
1432 giga_ctrl
|= ADVERTISE_1000HALF
;
1433 if (adv
& ADVERTISED_1000baseT_Full
)
1434 giga_ctrl
|= ADVERTISE_1000FULL
;
1435 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1436 ADVERTISED_1000baseT_Full
)) {
1437 netif_info(tp
, link
, dev
,
1438 "PHY does not support 1000Mbps\n");
1442 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1444 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1445 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1449 if (speed
== SPEED_10
)
1451 else if (speed
== SPEED_100
)
1452 bmcr
= BMCR_SPEED100
;
1456 if (duplex
== DUPLEX_FULL
)
1457 bmcr
|= BMCR_FULLDPLX
;
1460 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1462 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1463 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1464 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1465 rtl_writephy(tp
, 0x17, 0x2138);
1466 rtl_writephy(tp
, 0x0e, 0x0260);
1468 rtl_writephy(tp
, 0x17, 0x2108);
1469 rtl_writephy(tp
, 0x0e, 0x0000);
1478 static int rtl8169_set_speed(struct net_device
*dev
,
1479 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1481 struct rtl8169_private
*tp
= netdev_priv(dev
);
1484 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1488 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1489 (advertising
& ADVERTISED_1000baseT_Full
)) {
1490 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1496 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1498 struct rtl8169_private
*tp
= netdev_priv(dev
);
1499 unsigned long flags
;
1502 del_timer_sync(&tp
->timer
);
1504 spin_lock_irqsave(&tp
->lock
, flags
);
1505 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1506 cmd
->duplex
, cmd
->advertising
);
1507 spin_unlock_irqrestore(&tp
->lock
, flags
);
1512 static u32
rtl8169_fix_features(struct net_device
*dev
, u32 features
)
1514 if (dev
->mtu
> TD_MSS_MAX
)
1515 features
&= ~NETIF_F_ALL_TSO
;
1520 static int rtl8169_set_features(struct net_device
*dev
, u32 features
)
1522 struct rtl8169_private
*tp
= netdev_priv(dev
);
1523 void __iomem
*ioaddr
= tp
->mmio_addr
;
1524 unsigned long flags
;
1526 spin_lock_irqsave(&tp
->lock
, flags
);
1528 if (features
& NETIF_F_RXCSUM
)
1529 tp
->cp_cmd
|= RxChkSum
;
1531 tp
->cp_cmd
&= ~RxChkSum
;
1533 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1534 tp
->cp_cmd
|= RxVlan
;
1536 tp
->cp_cmd
&= ~RxVlan
;
1538 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1541 spin_unlock_irqrestore(&tp
->lock
, flags
);
1546 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1547 struct sk_buff
*skb
)
1549 return (vlan_tx_tag_present(skb
)) ?
1550 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1553 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1555 u32 opts2
= le32_to_cpu(desc
->opts2
);
1557 if (opts2
& RxVlanTag
)
1558 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1563 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1565 struct rtl8169_private
*tp
= netdev_priv(dev
);
1566 void __iomem
*ioaddr
= tp
->mmio_addr
;
1570 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1571 cmd
->port
= PORT_FIBRE
;
1572 cmd
->transceiver
= XCVR_INTERNAL
;
1574 status
= RTL_R32(TBICSR
);
1575 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1576 cmd
->autoneg
= !!(status
& TBINwEnable
);
1578 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1579 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1584 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1586 struct rtl8169_private
*tp
= netdev_priv(dev
);
1588 return mii_ethtool_gset(&tp
->mii
, cmd
);
1591 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1593 struct rtl8169_private
*tp
= netdev_priv(dev
);
1594 unsigned long flags
;
1597 spin_lock_irqsave(&tp
->lock
, flags
);
1599 rc
= tp
->get_settings(dev
, cmd
);
1601 spin_unlock_irqrestore(&tp
->lock
, flags
);
1605 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1608 struct rtl8169_private
*tp
= netdev_priv(dev
);
1609 unsigned long flags
;
1611 if (regs
->len
> R8169_REGS_SIZE
)
1612 regs
->len
= R8169_REGS_SIZE
;
1614 spin_lock_irqsave(&tp
->lock
, flags
);
1615 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1616 spin_unlock_irqrestore(&tp
->lock
, flags
);
1619 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1621 struct rtl8169_private
*tp
= netdev_priv(dev
);
1623 return tp
->msg_enable
;
1626 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1628 struct rtl8169_private
*tp
= netdev_priv(dev
);
1630 tp
->msg_enable
= value
;
1633 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1640 "tx_single_collisions",
1641 "tx_multi_collisions",
1649 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1653 return ARRAY_SIZE(rtl8169_gstrings
);
1659 static void rtl8169_update_counters(struct net_device
*dev
)
1661 struct rtl8169_private
*tp
= netdev_priv(dev
);
1662 void __iomem
*ioaddr
= tp
->mmio_addr
;
1663 struct device
*d
= &tp
->pci_dev
->dev
;
1664 struct rtl8169_counters
*counters
;
1670 * Some chips are unable to dump tally counters when the receiver
1673 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1676 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1680 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1681 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1682 RTL_W32(CounterAddrLow
, cmd
);
1683 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1686 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1687 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1693 RTL_W32(CounterAddrLow
, 0);
1694 RTL_W32(CounterAddrHigh
, 0);
1696 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1699 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1700 struct ethtool_stats
*stats
, u64
*data
)
1702 struct rtl8169_private
*tp
= netdev_priv(dev
);
1706 rtl8169_update_counters(dev
);
1708 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1709 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1710 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1711 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1712 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1713 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1714 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1715 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1716 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1717 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1718 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1719 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1720 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1723 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1727 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1732 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1733 .get_drvinfo
= rtl8169_get_drvinfo
,
1734 .get_regs_len
= rtl8169_get_regs_len
,
1735 .get_link
= ethtool_op_get_link
,
1736 .get_settings
= rtl8169_get_settings
,
1737 .set_settings
= rtl8169_set_settings
,
1738 .get_msglevel
= rtl8169_get_msglevel
,
1739 .set_msglevel
= rtl8169_set_msglevel
,
1740 .get_regs
= rtl8169_get_regs
,
1741 .get_wol
= rtl8169_get_wol
,
1742 .set_wol
= rtl8169_set_wol
,
1743 .get_strings
= rtl8169_get_strings
,
1744 .get_sset_count
= rtl8169_get_sset_count
,
1745 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1748 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1749 struct net_device
*dev
, u8 default_version
)
1751 void __iomem
*ioaddr
= tp
->mmio_addr
;
1753 * The driver currently handles the 8168Bf and the 8168Be identically
1754 * but they can be identified more specifically through the test below
1757 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1759 * Same thing for the 8101Eb and the 8101Ec:
1761 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1763 static const struct rtl_mac_info
{
1769 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36
},
1770 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35
},
1773 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
1774 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1775 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1776 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1779 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1780 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1781 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1783 /* 8168DP family. */
1784 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1785 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1786 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1789 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1790 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1791 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1792 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1793 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1794 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1795 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1796 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1797 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1800 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1801 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1802 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1803 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1806 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1807 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1808 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1809 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1810 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1811 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1812 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1813 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1814 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1815 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1816 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1817 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1818 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1819 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1820 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1821 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1822 /* FIXME: where did these entries come from ? -- FR */
1823 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1824 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1827 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1828 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1829 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1830 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1831 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1832 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1835 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1837 const struct rtl_mac_info
*p
= mac_info
;
1840 reg
= RTL_R32(TxConfig
);
1841 while ((reg
& p
->mask
) != p
->val
)
1843 tp
->mac_version
= p
->mac_version
;
1845 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
1846 netif_notice(tp
, probe
, dev
,
1847 "unknown MAC, using family default\n");
1848 tp
->mac_version
= default_version
;
1852 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1854 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1862 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1863 const struct phy_reg
*regs
, int len
)
1866 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1871 #define PHY_READ 0x00000000
1872 #define PHY_DATA_OR 0x10000000
1873 #define PHY_DATA_AND 0x20000000
1874 #define PHY_BJMPN 0x30000000
1875 #define PHY_READ_EFUSE 0x40000000
1876 #define PHY_READ_MAC_BYTE 0x50000000
1877 #define PHY_WRITE_MAC_BYTE 0x60000000
1878 #define PHY_CLEAR_READCOUNT 0x70000000
1879 #define PHY_WRITE 0x80000000
1880 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1881 #define PHY_COMP_EQ_SKIPN 0xa0000000
1882 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1883 #define PHY_WRITE_PREVIOUS 0xc0000000
1884 #define PHY_SKIPN 0xd0000000
1885 #define PHY_DELAY_MS 0xe0000000
1886 #define PHY_WRITE_ERI_WORD 0xf0000000
1890 char version
[RTL_VER_SIZE
];
1896 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1898 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1900 const struct firmware
*fw
= rtl_fw
->fw
;
1901 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
1902 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
1903 char *version
= rtl_fw
->version
;
1906 if (fw
->size
< FW_OPCODE_SIZE
)
1909 if (!fw_info
->magic
) {
1910 size_t i
, size
, start
;
1913 if (fw
->size
< sizeof(*fw_info
))
1916 for (i
= 0; i
< fw
->size
; i
++)
1917 checksum
+= fw
->data
[i
];
1921 start
= le32_to_cpu(fw_info
->fw_start
);
1922 if (start
> fw
->size
)
1925 size
= le32_to_cpu(fw_info
->fw_len
);
1926 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
1929 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
1931 pa
->code
= (__le32
*)(fw
->data
+ start
);
1934 if (fw
->size
% FW_OPCODE_SIZE
)
1937 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
1939 pa
->code
= (__le32
*)fw
->data
;
1940 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
1942 version
[RTL_VER_SIZE
- 1] = 0;
1949 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
1950 struct rtl_fw_phy_action
*pa
)
1955 for (index
= 0; index
< pa
->size
; index
++) {
1956 u32 action
= le32_to_cpu(pa
->code
[index
]);
1957 u32 regno
= (action
& 0x0fff0000) >> 16;
1959 switch(action
& 0xf0000000) {
1963 case PHY_READ_EFUSE
:
1964 case PHY_CLEAR_READCOUNT
:
1966 case PHY_WRITE_PREVIOUS
:
1971 if (regno
> index
) {
1972 netif_err(tp
, ifup
, tp
->dev
,
1973 "Out of range of firmware\n");
1977 case PHY_READCOUNT_EQ_SKIP
:
1978 if (index
+ 2 >= pa
->size
) {
1979 netif_err(tp
, ifup
, tp
->dev
,
1980 "Out of range of firmware\n");
1984 case PHY_COMP_EQ_SKIPN
:
1985 case PHY_COMP_NEQ_SKIPN
:
1987 if (index
+ 1 + regno
>= pa
->size
) {
1988 netif_err(tp
, ifup
, tp
->dev
,
1989 "Out of range of firmware\n");
1994 case PHY_READ_MAC_BYTE
:
1995 case PHY_WRITE_MAC_BYTE
:
1996 case PHY_WRITE_ERI_WORD
:
1998 netif_err(tp
, ifup
, tp
->dev
,
1999 "Invalid action 0x%08x\n", action
);
2008 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2010 struct net_device
*dev
= tp
->dev
;
2013 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2014 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
2018 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2024 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2026 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2030 predata
= count
= 0;
2032 for (index
= 0; index
< pa
->size
; ) {
2033 u32 action
= le32_to_cpu(pa
->code
[index
]);
2034 u32 data
= action
& 0x0000ffff;
2035 u32 regno
= (action
& 0x0fff0000) >> 16;
2040 switch(action
& 0xf0000000) {
2042 predata
= rtl_readphy(tp
, regno
);
2057 case PHY_READ_EFUSE
:
2058 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
2061 case PHY_CLEAR_READCOUNT
:
2066 rtl_writephy(tp
, regno
, data
);
2069 case PHY_READCOUNT_EQ_SKIP
:
2070 index
+= (count
== data
) ? 2 : 1;
2072 case PHY_COMP_EQ_SKIPN
:
2073 if (predata
== data
)
2077 case PHY_COMP_NEQ_SKIPN
:
2078 if (predata
!= data
)
2082 case PHY_WRITE_PREVIOUS
:
2083 rtl_writephy(tp
, regno
, predata
);
2094 case PHY_READ_MAC_BYTE
:
2095 case PHY_WRITE_MAC_BYTE
:
2096 case PHY_WRITE_ERI_WORD
:
2103 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2105 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2106 release_firmware(tp
->rtl_fw
->fw
);
2109 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2112 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2114 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2116 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2117 if (!IS_ERR_OR_NULL(rtl_fw
))
2118 rtl_phy_write_fw(tp
, rtl_fw
);
2121 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2123 if (rtl_readphy(tp
, reg
) != val
)
2124 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2126 rtl_apply_firmware(tp
);
2129 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2131 static const struct phy_reg phy_reg_init
[] = {
2193 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2196 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2198 static const struct phy_reg phy_reg_init
[] = {
2204 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2207 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2209 struct pci_dev
*pdev
= tp
->pci_dev
;
2211 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2212 (pdev
->subsystem_device
!= 0xe000))
2215 rtl_writephy(tp
, 0x1f, 0x0001);
2216 rtl_writephy(tp
, 0x10, 0xf01b);
2217 rtl_writephy(tp
, 0x1f, 0x0000);
2220 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2222 static const struct phy_reg phy_reg_init
[] = {
2262 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2264 rtl8169scd_hw_phy_config_quirk(tp
);
2267 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2269 static const struct phy_reg phy_reg_init
[] = {
2317 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2320 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2322 static const struct phy_reg phy_reg_init
[] = {
2327 rtl_writephy(tp
, 0x1f, 0x0001);
2328 rtl_patchphy(tp
, 0x16, 1 << 0);
2330 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2333 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2335 static const struct phy_reg phy_reg_init
[] = {
2341 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2344 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2346 static const struct phy_reg phy_reg_init
[] = {
2354 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2357 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2359 static const struct phy_reg phy_reg_init
[] = {
2365 rtl_writephy(tp
, 0x1f, 0x0000);
2366 rtl_patchphy(tp
, 0x14, 1 << 5);
2367 rtl_patchphy(tp
, 0x0d, 1 << 5);
2369 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2372 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2374 static const struct phy_reg phy_reg_init
[] = {
2394 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2396 rtl_patchphy(tp
, 0x14, 1 << 5);
2397 rtl_patchphy(tp
, 0x0d, 1 << 5);
2398 rtl_writephy(tp
, 0x1f, 0x0000);
2401 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2403 static const struct phy_reg phy_reg_init
[] = {
2421 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2423 rtl_patchphy(tp
, 0x16, 1 << 0);
2424 rtl_patchphy(tp
, 0x14, 1 << 5);
2425 rtl_patchphy(tp
, 0x0d, 1 << 5);
2426 rtl_writephy(tp
, 0x1f, 0x0000);
2429 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2431 static const struct phy_reg phy_reg_init
[] = {
2443 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2445 rtl_patchphy(tp
, 0x16, 1 << 0);
2446 rtl_patchphy(tp
, 0x14, 1 << 5);
2447 rtl_patchphy(tp
, 0x0d, 1 << 5);
2448 rtl_writephy(tp
, 0x1f, 0x0000);
2451 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2453 rtl8168c_3_hw_phy_config(tp
);
2456 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2458 static const struct phy_reg phy_reg_init_0
[] = {
2459 /* Channel Estimation */
2480 * Enhance line driver power
2489 * Can not link to 1Gbps with bad cable
2490 * Decrease SNR threshold form 21.07dB to 19.04dB
2498 void __iomem
*ioaddr
= tp
->mmio_addr
;
2500 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2504 * Fine Tune Switching regulator parameter
2506 rtl_writephy(tp
, 0x1f, 0x0002);
2507 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2508 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2510 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2511 static const struct phy_reg phy_reg_init
[] = {
2521 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2523 val
= rtl_readphy(tp
, 0x0d);
2525 if ((val
& 0x00ff) != 0x006c) {
2526 static const u32 set
[] = {
2527 0x0065, 0x0066, 0x0067, 0x0068,
2528 0x0069, 0x006a, 0x006b, 0x006c
2532 rtl_writephy(tp
, 0x1f, 0x0002);
2535 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2536 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2539 static const struct phy_reg phy_reg_init
[] = {
2547 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2550 /* RSET couple improve */
2551 rtl_writephy(tp
, 0x1f, 0x0002);
2552 rtl_patchphy(tp
, 0x0d, 0x0300);
2553 rtl_patchphy(tp
, 0x0f, 0x0010);
2555 /* Fine tune PLL performance */
2556 rtl_writephy(tp
, 0x1f, 0x0002);
2557 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2558 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2560 rtl_writephy(tp
, 0x1f, 0x0005);
2561 rtl_writephy(tp
, 0x05, 0x001b);
2563 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2565 rtl_writephy(tp
, 0x1f, 0x0000);
2568 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2570 static const struct phy_reg phy_reg_init_0
[] = {
2571 /* Channel Estimation */
2592 * Enhance line driver power
2601 * Can not link to 1Gbps with bad cable
2602 * Decrease SNR threshold form 21.07dB to 19.04dB
2610 void __iomem
*ioaddr
= tp
->mmio_addr
;
2612 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2614 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2615 static const struct phy_reg phy_reg_init
[] = {
2626 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2628 val
= rtl_readphy(tp
, 0x0d);
2629 if ((val
& 0x00ff) != 0x006c) {
2630 static const u32 set
[] = {
2631 0x0065, 0x0066, 0x0067, 0x0068,
2632 0x0069, 0x006a, 0x006b, 0x006c
2636 rtl_writephy(tp
, 0x1f, 0x0002);
2639 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2640 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2643 static const struct phy_reg phy_reg_init
[] = {
2651 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2654 /* Fine tune PLL performance */
2655 rtl_writephy(tp
, 0x1f, 0x0002);
2656 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2657 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2659 /* Switching regulator Slew rate */
2660 rtl_writephy(tp
, 0x1f, 0x0002);
2661 rtl_patchphy(tp
, 0x0f, 0x0017);
2663 rtl_writephy(tp
, 0x1f, 0x0005);
2664 rtl_writephy(tp
, 0x05, 0x001b);
2666 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2668 rtl_writephy(tp
, 0x1f, 0x0000);
2671 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2673 static const struct phy_reg phy_reg_init
[] = {
2729 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2732 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2734 static const struct phy_reg phy_reg_init
[] = {
2744 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2745 rtl_patchphy(tp
, 0x0d, 1 << 5);
2748 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
2750 static const struct phy_reg phy_reg_init
[] = {
2751 /* Enable Delay cap */
2757 /* Channel estimation fine tune */
2766 /* Update PFM & 10M TX idle timer */
2778 rtl_apply_firmware(tp
);
2780 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2782 /* DCO enable for 10M IDLE Power */
2783 rtl_writephy(tp
, 0x1f, 0x0007);
2784 rtl_writephy(tp
, 0x1e, 0x0023);
2785 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2786 rtl_writephy(tp
, 0x1f, 0x0000);
2788 /* For impedance matching */
2789 rtl_writephy(tp
, 0x1f, 0x0002);
2790 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2791 rtl_writephy(tp
, 0x1f, 0x0000);
2793 /* PHY auto speed down */
2794 rtl_writephy(tp
, 0x1f, 0x0007);
2795 rtl_writephy(tp
, 0x1e, 0x002d);
2796 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2797 rtl_writephy(tp
, 0x1f, 0x0000);
2798 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2800 rtl_writephy(tp
, 0x1f, 0x0005);
2801 rtl_writephy(tp
, 0x05, 0x8b86);
2802 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2803 rtl_writephy(tp
, 0x1f, 0x0000);
2805 rtl_writephy(tp
, 0x1f, 0x0005);
2806 rtl_writephy(tp
, 0x05, 0x8b85);
2807 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2808 rtl_writephy(tp
, 0x1f, 0x0007);
2809 rtl_writephy(tp
, 0x1e, 0x0020);
2810 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2811 rtl_writephy(tp
, 0x1f, 0x0006);
2812 rtl_writephy(tp
, 0x00, 0x5a00);
2813 rtl_writephy(tp
, 0x1f, 0x0000);
2814 rtl_writephy(tp
, 0x0d, 0x0007);
2815 rtl_writephy(tp
, 0x0e, 0x003c);
2816 rtl_writephy(tp
, 0x0d, 0x4007);
2817 rtl_writephy(tp
, 0x0e, 0x0000);
2818 rtl_writephy(tp
, 0x0d, 0x0000);
2821 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
2823 static const struct phy_reg phy_reg_init
[] = {
2824 /* Enable Delay cap */
2833 /* Channel estimation fine tune */
2850 rtl_apply_firmware(tp
);
2852 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2854 /* For 4-corner performance improve */
2855 rtl_writephy(tp
, 0x1f, 0x0005);
2856 rtl_writephy(tp
, 0x05, 0x8b80);
2857 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2858 rtl_writephy(tp
, 0x1f, 0x0000);
2860 /* PHY auto speed down */
2861 rtl_writephy(tp
, 0x1f, 0x0004);
2862 rtl_writephy(tp
, 0x1f, 0x0007);
2863 rtl_writephy(tp
, 0x1e, 0x002d);
2864 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
2865 rtl_writephy(tp
, 0x1f, 0x0002);
2866 rtl_writephy(tp
, 0x1f, 0x0000);
2867 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2869 /* improve 10M EEE waveform */
2870 rtl_writephy(tp
, 0x1f, 0x0005);
2871 rtl_writephy(tp
, 0x05, 0x8b86);
2872 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2873 rtl_writephy(tp
, 0x1f, 0x0000);
2875 /* Improve 2-pair detection performance */
2876 rtl_writephy(tp
, 0x1f, 0x0005);
2877 rtl_writephy(tp
, 0x05, 0x8b85);
2878 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
2879 rtl_writephy(tp
, 0x1f, 0x0000);
2882 rtl_w1w0_eri(tp
->mmio_addr
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003,
2884 rtl_writephy(tp
, 0x1f, 0x0005);
2885 rtl_writephy(tp
, 0x05, 0x8b85);
2886 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2887 rtl_writephy(tp
, 0x1f, 0x0004);
2888 rtl_writephy(tp
, 0x1f, 0x0007);
2889 rtl_writephy(tp
, 0x1e, 0x0020);
2890 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x0100);
2891 rtl_writephy(tp
, 0x1f, 0x0002);
2892 rtl_writephy(tp
, 0x1f, 0x0000);
2893 rtl_writephy(tp
, 0x0d, 0x0007);
2894 rtl_writephy(tp
, 0x0e, 0x003c);
2895 rtl_writephy(tp
, 0x0d, 0x4007);
2896 rtl_writephy(tp
, 0x0e, 0x0000);
2897 rtl_writephy(tp
, 0x0d, 0x0000);
2900 rtl_writephy(tp
, 0x1f, 0x0003);
2901 rtl_w1w0_phy(tp
, 0x19, 0x0000, 0x0001);
2902 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0400);
2903 rtl_writephy(tp
, 0x1f, 0x0000);
2906 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
2908 static const struct phy_reg phy_reg_init
[] = {
2909 /* Channel estimation fine tune */
2914 /* Modify green table for giga & fnet */
2931 /* Modify green table for 10M */
2937 /* Disable hiimpedance detection (RTCT) */
2943 rtl_apply_firmware(tp
);
2945 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2947 /* For 4-corner performance improve */
2948 rtl_writephy(tp
, 0x1f, 0x0005);
2949 rtl_writephy(tp
, 0x05, 0x8b80);
2950 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
2951 rtl_writephy(tp
, 0x1f, 0x0000);
2953 /* PHY auto speed down */
2954 rtl_writephy(tp
, 0x1f, 0x0007);
2955 rtl_writephy(tp
, 0x1e, 0x002d);
2956 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
2957 rtl_writephy(tp
, 0x1f, 0x0000);
2958 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2960 /* Improve 10M EEE waveform */
2961 rtl_writephy(tp
, 0x1f, 0x0005);
2962 rtl_writephy(tp
, 0x05, 0x8b86);
2963 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2964 rtl_writephy(tp
, 0x1f, 0x0000);
2966 /* Improve 2-pair detection performance */
2967 rtl_writephy(tp
, 0x1f, 0x0005);
2968 rtl_writephy(tp
, 0x05, 0x8b85);
2969 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
2970 rtl_writephy(tp
, 0x1f, 0x0000);
2973 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
2975 rtl_apply_firmware(tp
);
2977 /* For 4-corner performance improve */
2978 rtl_writephy(tp
, 0x1f, 0x0005);
2979 rtl_writephy(tp
, 0x05, 0x8b80);
2980 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
2981 rtl_writephy(tp
, 0x1f, 0x0000);
2983 /* PHY auto speed down */
2984 rtl_writephy(tp
, 0x1f, 0x0007);
2985 rtl_writephy(tp
, 0x1e, 0x002d);
2986 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
2987 rtl_writephy(tp
, 0x1f, 0x0000);
2988 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2990 /* Improve 10M EEE waveform */
2991 rtl_writephy(tp
, 0x1f, 0x0005);
2992 rtl_writephy(tp
, 0x05, 0x8b86);
2993 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2994 rtl_writephy(tp
, 0x1f, 0x0000);
2997 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
2999 static const struct phy_reg phy_reg_init
[] = {
3006 rtl_writephy(tp
, 0x1f, 0x0000);
3007 rtl_patchphy(tp
, 0x11, 1 << 12);
3008 rtl_patchphy(tp
, 0x19, 1 << 13);
3009 rtl_patchphy(tp
, 0x10, 1 << 15);
3011 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3014 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
3016 static const struct phy_reg phy_reg_init
[] = {
3030 /* Disable ALDPS before ram code */
3031 rtl_writephy(tp
, 0x1f, 0x0000);
3032 rtl_writephy(tp
, 0x18, 0x0310);
3035 rtl_apply_firmware(tp
);
3037 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3040 static void rtl_hw_phy_config(struct net_device
*dev
)
3042 struct rtl8169_private
*tp
= netdev_priv(dev
);
3044 rtl8169_print_mac_version(tp
);
3046 switch (tp
->mac_version
) {
3047 case RTL_GIGA_MAC_VER_01
:
3049 case RTL_GIGA_MAC_VER_02
:
3050 case RTL_GIGA_MAC_VER_03
:
3051 rtl8169s_hw_phy_config(tp
);
3053 case RTL_GIGA_MAC_VER_04
:
3054 rtl8169sb_hw_phy_config(tp
);
3056 case RTL_GIGA_MAC_VER_05
:
3057 rtl8169scd_hw_phy_config(tp
);
3059 case RTL_GIGA_MAC_VER_06
:
3060 rtl8169sce_hw_phy_config(tp
);
3062 case RTL_GIGA_MAC_VER_07
:
3063 case RTL_GIGA_MAC_VER_08
:
3064 case RTL_GIGA_MAC_VER_09
:
3065 rtl8102e_hw_phy_config(tp
);
3067 case RTL_GIGA_MAC_VER_11
:
3068 rtl8168bb_hw_phy_config(tp
);
3070 case RTL_GIGA_MAC_VER_12
:
3071 rtl8168bef_hw_phy_config(tp
);
3073 case RTL_GIGA_MAC_VER_17
:
3074 rtl8168bef_hw_phy_config(tp
);
3076 case RTL_GIGA_MAC_VER_18
:
3077 rtl8168cp_1_hw_phy_config(tp
);
3079 case RTL_GIGA_MAC_VER_19
:
3080 rtl8168c_1_hw_phy_config(tp
);
3082 case RTL_GIGA_MAC_VER_20
:
3083 rtl8168c_2_hw_phy_config(tp
);
3085 case RTL_GIGA_MAC_VER_21
:
3086 rtl8168c_3_hw_phy_config(tp
);
3088 case RTL_GIGA_MAC_VER_22
:
3089 rtl8168c_4_hw_phy_config(tp
);
3091 case RTL_GIGA_MAC_VER_23
:
3092 case RTL_GIGA_MAC_VER_24
:
3093 rtl8168cp_2_hw_phy_config(tp
);
3095 case RTL_GIGA_MAC_VER_25
:
3096 rtl8168d_1_hw_phy_config(tp
);
3098 case RTL_GIGA_MAC_VER_26
:
3099 rtl8168d_2_hw_phy_config(tp
);
3101 case RTL_GIGA_MAC_VER_27
:
3102 rtl8168d_3_hw_phy_config(tp
);
3104 case RTL_GIGA_MAC_VER_28
:
3105 rtl8168d_4_hw_phy_config(tp
);
3107 case RTL_GIGA_MAC_VER_29
:
3108 case RTL_GIGA_MAC_VER_30
:
3109 rtl8105e_hw_phy_config(tp
);
3111 case RTL_GIGA_MAC_VER_31
:
3114 case RTL_GIGA_MAC_VER_32
:
3115 case RTL_GIGA_MAC_VER_33
:
3116 rtl8168e_1_hw_phy_config(tp
);
3118 case RTL_GIGA_MAC_VER_34
:
3119 rtl8168e_2_hw_phy_config(tp
);
3121 case RTL_GIGA_MAC_VER_35
:
3122 rtl8168f_1_hw_phy_config(tp
);
3124 case RTL_GIGA_MAC_VER_36
:
3125 rtl8168f_2_hw_phy_config(tp
);
3133 static void rtl8169_phy_timer(unsigned long __opaque
)
3135 struct net_device
*dev
= (struct net_device
*)__opaque
;
3136 struct rtl8169_private
*tp
= netdev_priv(dev
);
3137 struct timer_list
*timer
= &tp
->timer
;
3138 void __iomem
*ioaddr
= tp
->mmio_addr
;
3139 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
3141 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
3143 spin_lock_irq(&tp
->lock
);
3145 if (tp
->phy_reset_pending(tp
)) {
3147 * A busy loop could burn quite a few cycles on nowadays CPU.
3148 * Let's delay the execution of the timer for a few ticks.
3154 if (tp
->link_ok(ioaddr
))
3157 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
3159 tp
->phy_reset_enable(tp
);
3162 mod_timer(timer
, jiffies
+ timeout
);
3164 spin_unlock_irq(&tp
->lock
);
3167 #ifdef CONFIG_NET_POLL_CONTROLLER
3169 * Polling 'interrupt' - used by things like netconsole to send skbs
3170 * without having to re-enable interrupts. It's not called while
3171 * the interrupt routine is executing.
3173 static void rtl8169_netpoll(struct net_device
*dev
)
3175 struct rtl8169_private
*tp
= netdev_priv(dev
);
3176 struct pci_dev
*pdev
= tp
->pci_dev
;
3178 disable_irq(pdev
->irq
);
3179 rtl8169_interrupt(pdev
->irq
, dev
);
3180 enable_irq(pdev
->irq
);
3184 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
3185 void __iomem
*ioaddr
)
3188 pci_release_regions(pdev
);
3189 pci_clear_mwi(pdev
);
3190 pci_disable_device(pdev
);
3194 static void rtl8169_phy_reset(struct net_device
*dev
,
3195 struct rtl8169_private
*tp
)
3199 tp
->phy_reset_enable(tp
);
3200 for (i
= 0; i
< 100; i
++) {
3201 if (!tp
->phy_reset_pending(tp
))
3205 netif_err(tp
, link
, dev
, "PHY reset failed\n");
3208 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
3210 void __iomem
*ioaddr
= tp
->mmio_addr
;
3212 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
3213 (RTL_R8(PHYstatus
) & TBI_Enable
);
3216 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
3218 void __iomem
*ioaddr
= tp
->mmio_addr
;
3220 rtl_hw_phy_config(dev
);
3222 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
3223 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3227 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
3229 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3230 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
3232 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
3233 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3235 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3236 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
3239 rtl8169_phy_reset(dev
, tp
);
3241 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
3242 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3243 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
3244 (tp
->mii
.supports_gmii
?
3245 ADVERTISED_1000baseT_Half
|
3246 ADVERTISED_1000baseT_Full
: 0));
3248 if (rtl_tbi_enabled(tp
))
3249 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
3252 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
3254 void __iomem
*ioaddr
= tp
->mmio_addr
;
3258 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
3259 high
= addr
[4] | (addr
[5] << 8);
3261 spin_lock_irq(&tp
->lock
);
3263 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3265 RTL_W32(MAC4
, high
);
3271 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
3272 const struct exgmac_reg e
[] = {
3273 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= low
},
3274 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= high
},
3275 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= low
<< 16 },
3276 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= high
<< 16 |
3280 rtl_write_exgmac_batch(ioaddr
, e
, ARRAY_SIZE(e
));
3283 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3285 spin_unlock_irq(&tp
->lock
);
3288 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
3290 struct rtl8169_private
*tp
= netdev_priv(dev
);
3291 struct sockaddr
*addr
= p
;
3293 if (!is_valid_ether_addr(addr
->sa_data
))
3294 return -EADDRNOTAVAIL
;
3296 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
3298 rtl_rar_set(tp
, dev
->dev_addr
);
3303 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3305 struct rtl8169_private
*tp
= netdev_priv(dev
);
3306 struct mii_ioctl_data
*data
= if_mii(ifr
);
3308 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
3311 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
3312 struct mii_ioctl_data
*data
, int cmd
)
3316 data
->phy_id
= 32; /* Internal PHY */
3320 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
3324 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
3330 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
3335 static const struct rtl_cfg_info
{
3336 void (*hw_start
)(struct net_device
*);
3337 unsigned int region
;
3343 } rtl_cfg_infos
[] = {
3345 .hw_start
= rtl_hw_start_8169
,
3348 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3349 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3350 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3351 .features
= RTL_FEATURE_GMII
,
3352 .default_ver
= RTL_GIGA_MAC_VER_01
,
3355 .hw_start
= rtl_hw_start_8168
,
3358 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3359 TxErr
| TxOK
| RxOK
| RxErr
,
3360 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
3361 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
3362 .default_ver
= RTL_GIGA_MAC_VER_11
,
3365 .hw_start
= rtl_hw_start_8101
,
3368 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
3369 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3370 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3371 .features
= RTL_FEATURE_MSI
,
3372 .default_ver
= RTL_GIGA_MAC_VER_13
,
3376 /* Cfg9346_Unlock assumed. */
3377 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
3378 const struct rtl_cfg_info
*cfg
)
3383 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
3384 if (cfg
->features
& RTL_FEATURE_MSI
) {
3385 if (pci_enable_msi(pdev
)) {
3386 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
3389 msi
= RTL_FEATURE_MSI
;
3392 RTL_W8(Config2
, cfg2
);
3396 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
3398 if (tp
->features
& RTL_FEATURE_MSI
) {
3399 pci_disable_msi(pdev
);
3400 tp
->features
&= ~RTL_FEATURE_MSI
;
3404 static const struct net_device_ops rtl8169_netdev_ops
= {
3405 .ndo_open
= rtl8169_open
,
3406 .ndo_stop
= rtl8169_close
,
3407 .ndo_get_stats
= rtl8169_get_stats
,
3408 .ndo_start_xmit
= rtl8169_start_xmit
,
3409 .ndo_tx_timeout
= rtl8169_tx_timeout
,
3410 .ndo_validate_addr
= eth_validate_addr
,
3411 .ndo_change_mtu
= rtl8169_change_mtu
,
3412 .ndo_fix_features
= rtl8169_fix_features
,
3413 .ndo_set_features
= rtl8169_set_features
,
3414 .ndo_set_mac_address
= rtl_set_mac_address
,
3415 .ndo_do_ioctl
= rtl8169_ioctl
,
3416 .ndo_set_rx_mode
= rtl_set_rx_mode
,
3417 #ifdef CONFIG_NET_POLL_CONTROLLER
3418 .ndo_poll_controller
= rtl8169_netpoll
,
3423 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3425 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3427 switch (tp
->mac_version
) {
3428 case RTL_GIGA_MAC_VER_27
:
3429 ops
->write
= r8168dp_1_mdio_write
;
3430 ops
->read
= r8168dp_1_mdio_read
;
3432 case RTL_GIGA_MAC_VER_28
:
3433 case RTL_GIGA_MAC_VER_31
:
3434 ops
->write
= r8168dp_2_mdio_write
;
3435 ops
->read
= r8168dp_2_mdio_read
;
3438 ops
->write
= r8169_mdio_write
;
3439 ops
->read
= r8169_mdio_read
;
3444 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3446 rtl_writephy(tp
, 0x1f, 0x0000);
3447 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3450 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3452 rtl_writephy(tp
, 0x1f, 0x0000);
3453 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3456 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3458 void __iomem
*ioaddr
= tp
->mmio_addr
;
3460 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3461 rtl_writephy(tp
, 0x1f, 0x0000);
3462 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3464 if (tp
->mac_version
== RTL_GIGA_MAC_VER_29
||
3465 tp
->mac_version
== RTL_GIGA_MAC_VER_30
)
3466 RTL_W32(RxConfig
, RTL_R32(RxConfig
) | AcceptBroadcast
|
3467 AcceptMulticast
| AcceptMyPhys
);
3471 r810x_phy_power_down(tp
);
3474 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3476 r810x_phy_power_up(tp
);
3479 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3481 rtl_writephy(tp
, 0x1f, 0x0000);
3482 switch (tp
->mac_version
) {
3483 case RTL_GIGA_MAC_VER_11
:
3484 case RTL_GIGA_MAC_VER_12
:
3485 case RTL_GIGA_MAC_VER_17
:
3486 case RTL_GIGA_MAC_VER_18
:
3487 case RTL_GIGA_MAC_VER_19
:
3488 case RTL_GIGA_MAC_VER_20
:
3489 case RTL_GIGA_MAC_VER_21
:
3490 case RTL_GIGA_MAC_VER_22
:
3491 case RTL_GIGA_MAC_VER_23
:
3492 case RTL_GIGA_MAC_VER_24
:
3493 case RTL_GIGA_MAC_VER_25
:
3494 case RTL_GIGA_MAC_VER_26
:
3495 case RTL_GIGA_MAC_VER_27
:
3496 case RTL_GIGA_MAC_VER_28
:
3497 case RTL_GIGA_MAC_VER_31
:
3498 rtl_writephy(tp
, 0x0e, 0x0000);
3503 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3506 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3508 rtl_writephy(tp
, 0x1f, 0x0000);
3509 switch (tp
->mac_version
) {
3510 case RTL_GIGA_MAC_VER_32
:
3511 case RTL_GIGA_MAC_VER_33
:
3512 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3515 case RTL_GIGA_MAC_VER_11
:
3516 case RTL_GIGA_MAC_VER_12
:
3517 case RTL_GIGA_MAC_VER_17
:
3518 case RTL_GIGA_MAC_VER_18
:
3519 case RTL_GIGA_MAC_VER_19
:
3520 case RTL_GIGA_MAC_VER_20
:
3521 case RTL_GIGA_MAC_VER_21
:
3522 case RTL_GIGA_MAC_VER_22
:
3523 case RTL_GIGA_MAC_VER_23
:
3524 case RTL_GIGA_MAC_VER_24
:
3525 case RTL_GIGA_MAC_VER_25
:
3526 case RTL_GIGA_MAC_VER_26
:
3527 case RTL_GIGA_MAC_VER_27
:
3528 case RTL_GIGA_MAC_VER_28
:
3529 case RTL_GIGA_MAC_VER_31
:
3530 rtl_writephy(tp
, 0x0e, 0x0200);
3532 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3537 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3539 void __iomem
*ioaddr
= tp
->mmio_addr
;
3541 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3542 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3543 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3544 r8168dp_check_dash(tp
)) {
3548 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
3549 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
3550 (RTL_R16(CPlusCmd
) & ASF
)) {
3554 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3555 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3556 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3558 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3559 rtl_writephy(tp
, 0x1f, 0x0000);
3560 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3562 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3563 tp
->mac_version
== RTL_GIGA_MAC_VER_33
||
3564 tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
3565 RTL_W32(RxConfig
, RTL_R32(RxConfig
) | AcceptBroadcast
|
3566 AcceptMulticast
| AcceptMyPhys
);
3570 r8168_phy_power_down(tp
);
3572 switch (tp
->mac_version
) {
3573 case RTL_GIGA_MAC_VER_25
:
3574 case RTL_GIGA_MAC_VER_26
:
3575 case RTL_GIGA_MAC_VER_27
:
3576 case RTL_GIGA_MAC_VER_28
:
3577 case RTL_GIGA_MAC_VER_31
:
3578 case RTL_GIGA_MAC_VER_32
:
3579 case RTL_GIGA_MAC_VER_33
:
3580 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3585 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3587 void __iomem
*ioaddr
= tp
->mmio_addr
;
3589 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3590 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3591 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3592 r8168dp_check_dash(tp
)) {
3596 switch (tp
->mac_version
) {
3597 case RTL_GIGA_MAC_VER_25
:
3598 case RTL_GIGA_MAC_VER_26
:
3599 case RTL_GIGA_MAC_VER_27
:
3600 case RTL_GIGA_MAC_VER_28
:
3601 case RTL_GIGA_MAC_VER_31
:
3602 case RTL_GIGA_MAC_VER_32
:
3603 case RTL_GIGA_MAC_VER_33
:
3604 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3608 r8168_phy_power_up(tp
);
3611 static void rtl_pll_power_op(struct rtl8169_private
*tp
,
3612 void (*op
)(struct rtl8169_private
*))
3618 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3620 rtl_pll_power_op(tp
, tp
->pll_power_ops
.down
);
3623 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3625 rtl_pll_power_op(tp
, tp
->pll_power_ops
.up
);
3628 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3630 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3632 switch (tp
->mac_version
) {
3633 case RTL_GIGA_MAC_VER_07
:
3634 case RTL_GIGA_MAC_VER_08
:
3635 case RTL_GIGA_MAC_VER_09
:
3636 case RTL_GIGA_MAC_VER_10
:
3637 case RTL_GIGA_MAC_VER_16
:
3638 case RTL_GIGA_MAC_VER_29
:
3639 case RTL_GIGA_MAC_VER_30
:
3640 ops
->down
= r810x_pll_power_down
;
3641 ops
->up
= r810x_pll_power_up
;
3644 case RTL_GIGA_MAC_VER_11
:
3645 case RTL_GIGA_MAC_VER_12
:
3646 case RTL_GIGA_MAC_VER_17
:
3647 case RTL_GIGA_MAC_VER_18
:
3648 case RTL_GIGA_MAC_VER_19
:
3649 case RTL_GIGA_MAC_VER_20
:
3650 case RTL_GIGA_MAC_VER_21
:
3651 case RTL_GIGA_MAC_VER_22
:
3652 case RTL_GIGA_MAC_VER_23
:
3653 case RTL_GIGA_MAC_VER_24
:
3654 case RTL_GIGA_MAC_VER_25
:
3655 case RTL_GIGA_MAC_VER_26
:
3656 case RTL_GIGA_MAC_VER_27
:
3657 case RTL_GIGA_MAC_VER_28
:
3658 case RTL_GIGA_MAC_VER_31
:
3659 case RTL_GIGA_MAC_VER_32
:
3660 case RTL_GIGA_MAC_VER_33
:
3661 case RTL_GIGA_MAC_VER_34
:
3662 case RTL_GIGA_MAC_VER_35
:
3663 case RTL_GIGA_MAC_VER_36
:
3664 ops
->down
= r8168_pll_power_down
;
3665 ops
->up
= r8168_pll_power_up
;
3675 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
3677 void __iomem
*ioaddr
= tp
->mmio_addr
;
3679 switch (tp
->mac_version
) {
3680 case RTL_GIGA_MAC_VER_01
:
3681 case RTL_GIGA_MAC_VER_02
:
3682 case RTL_GIGA_MAC_VER_03
:
3683 case RTL_GIGA_MAC_VER_04
:
3684 case RTL_GIGA_MAC_VER_05
:
3685 case RTL_GIGA_MAC_VER_06
:
3686 case RTL_GIGA_MAC_VER_10
:
3687 case RTL_GIGA_MAC_VER_11
:
3688 case RTL_GIGA_MAC_VER_12
:
3689 case RTL_GIGA_MAC_VER_13
:
3690 case RTL_GIGA_MAC_VER_14
:
3691 case RTL_GIGA_MAC_VER_15
:
3692 case RTL_GIGA_MAC_VER_16
:
3693 case RTL_GIGA_MAC_VER_17
:
3694 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
3696 case RTL_GIGA_MAC_VER_18
:
3697 case RTL_GIGA_MAC_VER_19
:
3698 case RTL_GIGA_MAC_VER_20
:
3699 case RTL_GIGA_MAC_VER_21
:
3700 case RTL_GIGA_MAC_VER_22
:
3701 case RTL_GIGA_MAC_VER_23
:
3702 case RTL_GIGA_MAC_VER_24
:
3703 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
3706 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
3711 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3713 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3716 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3718 void __iomem
*ioaddr
= tp
->mmio_addr
;
3721 /* Soft reset the chip. */
3722 RTL_W8(ChipCmd
, CmdReset
);
3724 /* Check that the chip has finished the reset. */
3725 for (i
= 0; i
< 100; i
++) {
3726 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3731 rtl8169_init_ring_indexes(tp
);
3734 static int __devinit
3735 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3737 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3738 const unsigned int region
= cfg
->region
;
3739 struct rtl8169_private
*tp
;
3740 struct mii_if_info
*mii
;
3741 struct net_device
*dev
;
3742 void __iomem
*ioaddr
;
3746 if (netif_msg_drv(&debug
)) {
3747 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3748 MODULENAME
, RTL8169_VERSION
);
3751 dev
= alloc_etherdev(sizeof (*tp
));
3753 if (netif_msg_drv(&debug
))
3754 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3759 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3760 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3761 tp
= netdev_priv(dev
);
3764 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3768 mii
->mdio_read
= rtl_mdio_read
;
3769 mii
->mdio_write
= rtl_mdio_write
;
3770 mii
->phy_id_mask
= 0x1f;
3771 mii
->reg_num_mask
= 0x1f;
3772 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3774 /* disable ASPM completely as that cause random device stop working
3775 * problems as well as full system hangs for some PCIe devices users */
3776 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3777 PCIE_LINK_STATE_CLKPM
);
3779 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3780 rc
= pci_enable_device(pdev
);
3782 netif_err(tp
, probe
, dev
, "enable failure\n");
3783 goto err_out_free_dev_1
;
3786 if (pci_set_mwi(pdev
) < 0)
3787 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3789 /* make sure PCI base addr 1 is MMIO */
3790 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3791 netif_err(tp
, probe
, dev
,
3792 "region #%d not an MMIO resource, aborting\n",
3798 /* check for weird/broken PCI region reporting */
3799 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3800 netif_err(tp
, probe
, dev
,
3801 "Invalid PCI region size(s), aborting\n");
3806 rc
= pci_request_regions(pdev
, MODULENAME
);
3808 netif_err(tp
, probe
, dev
, "could not request regions\n");
3812 tp
->cp_cmd
= RxChkSum
;
3814 if ((sizeof(dma_addr_t
) > 4) &&
3815 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3816 tp
->cp_cmd
|= PCIDAC
;
3817 dev
->features
|= NETIF_F_HIGHDMA
;
3819 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3821 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3822 goto err_out_free_res_3
;
3826 /* ioremap MMIO region */
3827 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3829 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3831 goto err_out_free_res_3
;
3833 tp
->mmio_addr
= ioaddr
;
3835 if (!pci_is_pcie(pdev
))
3836 netif_info(tp
, probe
, dev
, "not PCI Express\n");
3838 /* Identify chip attached to board */
3839 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
3843 RTL_W16(IntrMask
, 0x0000);
3847 RTL_W16(IntrStatus
, 0xffff);
3849 pci_set_master(pdev
);
3852 * Pretend we are using VLANs; This bypasses a nasty bug where
3853 * Interrupts stop flowing on high load on 8110SCd controllers.
3855 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3856 tp
->cp_cmd
|= RxVlan
;
3858 rtl_init_mdio_ops(tp
);
3859 rtl_init_pll_power_ops(tp
);
3861 rtl8169_print_mac_version(tp
);
3863 chipset
= tp
->mac_version
;
3864 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
3866 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3867 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3868 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3869 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3870 tp
->features
|= RTL_FEATURE_WOL
;
3871 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3872 tp
->features
|= RTL_FEATURE_WOL
;
3873 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3874 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3876 if (rtl_tbi_enabled(tp
)) {
3877 tp
->set_speed
= rtl8169_set_speed_tbi
;
3878 tp
->get_settings
= rtl8169_gset_tbi
;
3879 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3880 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3881 tp
->link_ok
= rtl8169_tbi_link_ok
;
3882 tp
->do_ioctl
= rtl_tbi_ioctl
;
3884 tp
->set_speed
= rtl8169_set_speed_xmii
;
3885 tp
->get_settings
= rtl8169_gset_xmii
;
3886 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3887 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3888 tp
->link_ok
= rtl8169_xmii_link_ok
;
3889 tp
->do_ioctl
= rtl_xmii_ioctl
;
3892 spin_lock_init(&tp
->lock
);
3894 /* Get MAC address */
3895 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3896 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3897 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3899 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3900 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3901 dev
->irq
= pdev
->irq
;
3902 dev
->base_addr
= (unsigned long) ioaddr
;
3904 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3906 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3907 * properly for all devices */
3908 dev
->features
|= NETIF_F_RXCSUM
|
3909 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3911 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3912 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3913 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3916 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3917 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3918 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
3920 tp
->intr_mask
= 0xffff;
3921 tp
->hw_start
= cfg
->hw_start
;
3922 tp
->intr_event
= cfg
->intr_event
;
3923 tp
->napi_event
= cfg
->napi_event
;
3925 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
3926 ~(RxBOVF
| RxFOVF
) : ~0;
3928 init_timer(&tp
->timer
);
3929 tp
->timer
.data
= (unsigned long) dev
;
3930 tp
->timer
.function
= rtl8169_phy_timer
;
3932 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
3934 rc
= register_netdev(dev
);
3938 pci_set_drvdata(pdev
, dev
);
3940 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3941 rtl_chip_infos
[chipset
].name
, dev
->base_addr
, dev
->dev_addr
,
3942 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3944 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3945 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3946 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3947 rtl8168_driver_start(tp
);
3950 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3952 if (pci_dev_run_wake(pdev
))
3953 pm_runtime_put_noidle(&pdev
->dev
);
3955 netif_carrier_off(dev
);
3961 rtl_disable_msi(pdev
, tp
);
3964 pci_release_regions(pdev
);
3966 pci_clear_mwi(pdev
);
3967 pci_disable_device(pdev
);
3973 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3975 struct net_device
*dev
= pci_get_drvdata(pdev
);
3976 struct rtl8169_private
*tp
= netdev_priv(dev
);
3978 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3979 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3980 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3981 rtl8168_driver_stop(tp
);
3984 cancel_delayed_work_sync(&tp
->task
);
3986 unregister_netdev(dev
);
3988 rtl_release_firmware(tp
);
3990 if (pci_dev_run_wake(pdev
))
3991 pm_runtime_get_noresume(&pdev
->dev
);
3993 /* restore original MAC address */
3994 rtl_rar_set(tp
, dev
->perm_addr
);
3996 rtl_disable_msi(pdev
, tp
);
3997 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3998 pci_set_drvdata(pdev
, NULL
);
4001 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
4003 struct rtl_fw
*rtl_fw
;
4007 name
= rtl_lookup_firmware_name(tp
);
4009 goto out_no_firmware
;
4011 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
4015 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
4019 rc
= rtl_check_firmware(tp
, rtl_fw
);
4021 goto err_release_firmware
;
4023 tp
->rtl_fw
= rtl_fw
;
4027 err_release_firmware
:
4028 release_firmware(rtl_fw
->fw
);
4032 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
4039 static void rtl_request_firmware(struct rtl8169_private
*tp
)
4041 if (IS_ERR(tp
->rtl_fw
))
4042 rtl_request_uncached_firmware(tp
);
4045 static int rtl8169_open(struct net_device
*dev
)
4047 struct rtl8169_private
*tp
= netdev_priv(dev
);
4048 void __iomem
*ioaddr
= tp
->mmio_addr
;
4049 struct pci_dev
*pdev
= tp
->pci_dev
;
4050 int retval
= -ENOMEM
;
4052 pm_runtime_get_sync(&pdev
->dev
);
4055 * Rx and Tx desscriptors needs 256 bytes alignment.
4056 * dma_alloc_coherent provides more.
4058 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
4059 &tp
->TxPhyAddr
, GFP_KERNEL
);
4060 if (!tp
->TxDescArray
)
4061 goto err_pm_runtime_put
;
4063 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
4064 &tp
->RxPhyAddr
, GFP_KERNEL
);
4065 if (!tp
->RxDescArray
)
4068 retval
= rtl8169_init_ring(dev
);
4072 INIT_DELAYED_WORK(&tp
->task
, NULL
);
4076 rtl_request_firmware(tp
);
4078 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
4079 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
4082 goto err_release_fw_2
;
4084 napi_enable(&tp
->napi
);
4086 rtl8169_init_phy(dev
, tp
);
4088 rtl8169_set_features(dev
, dev
->features
);
4090 rtl_pll_power_up(tp
);
4094 tp
->saved_wolopts
= 0;
4095 pm_runtime_put_noidle(&pdev
->dev
);
4097 rtl8169_check_link_status(dev
, tp
, ioaddr
);
4102 rtl_release_firmware(tp
);
4103 rtl8169_rx_clear(tp
);
4105 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4107 tp
->RxDescArray
= NULL
;
4109 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4111 tp
->TxDescArray
= NULL
;
4113 pm_runtime_put_noidle(&pdev
->dev
);
4117 static void rtl_rx_close(struct rtl8169_private
*tp
)
4119 void __iomem
*ioaddr
= tp
->mmio_addr
;
4121 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
4124 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
4126 void __iomem
*ioaddr
= tp
->mmio_addr
;
4128 /* Disable interrupts */
4129 rtl8169_irq_mask_and_ack(ioaddr
);
4133 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4134 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4135 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4136 while (RTL_R8(TxPoll
) & NPQ
)
4138 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
4139 tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
4140 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
4141 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4142 while (!(RTL_R32(TxConfig
) & TXCFG_EMPTY
))
4145 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4152 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
4154 void __iomem
*ioaddr
= tp
->mmio_addr
;
4156 /* Set DMA burst size and Interframe Gap Time */
4157 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4158 (InterFrameGap
<< TxInterFrameGapShift
));
4161 static void rtl_hw_start(struct net_device
*dev
)
4163 struct rtl8169_private
*tp
= netdev_priv(dev
);
4167 netif_start_queue(dev
);
4170 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
4171 void __iomem
*ioaddr
)
4174 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4175 * register to be written before TxDescAddrLow to work.
4176 * Switching from MMIO to I/O access fixes the issue as well.
4178 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4179 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4180 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4181 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4184 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
4188 cmd
= RTL_R16(CPlusCmd
);
4189 RTL_W16(CPlusCmd
, cmd
);
4193 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
4195 /* Low hurts. Let's disable the filtering. */
4196 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
4199 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
4201 static const struct rtl_cfg2_info
{
4206 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
4207 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
4208 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
4209 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
4211 const struct rtl_cfg2_info
*p
= cfg2_info
;
4215 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
4216 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
4217 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
4218 RTL_W32(0x7c, p
->val
);
4224 static void rtl_hw_start_8169(struct net_device
*dev
)
4226 struct rtl8169_private
*tp
= netdev_priv(dev
);
4227 void __iomem
*ioaddr
= tp
->mmio_addr
;
4228 struct pci_dev
*pdev
= tp
->pci_dev
;
4230 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
4231 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
4232 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
4235 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4236 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4237 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4238 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4239 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4240 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4244 RTL_W8(EarlyTxThres
, NoEarlyTx
);
4246 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4248 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4249 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4250 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4251 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4252 rtl_set_rx_tx_config_registers(tp
);
4254 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
4256 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4257 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
4258 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4259 "Bit-3 and bit-14 MUST be 1\n");
4260 tp
->cp_cmd
|= (1 << 14);
4263 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4265 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
4268 * Undocumented corner. Supposedly:
4269 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4271 RTL_W16(IntrMitigate
, 0x0000);
4273 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4275 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
4276 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
4277 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
4278 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
4279 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4280 rtl_set_rx_tx_config_registers(tp
);
4283 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4285 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4288 RTL_W32(RxMissed
, 0);
4290 rtl_set_rx_mode(dev
);
4292 /* no early-rx interrupts */
4293 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4295 /* Enable all known interrupts by setting the interrupt mask. */
4296 RTL_W16(IntrMask
, tp
->intr_event
);
4299 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
4301 int cap
= pci_pcie_cap(pdev
);
4306 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
4307 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
4308 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
4312 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
4316 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
4317 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
4320 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
4322 rtl_csi_access_enable(ioaddr
, 0x17000000);
4325 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
4327 rtl_csi_access_enable(ioaddr
, 0x27000000);
4331 unsigned int offset
;
4336 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
4341 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
4342 rtl_ephy_write(ioaddr
, e
->offset
, w
);
4347 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
4349 int cap
= pci_pcie_cap(pdev
);
4354 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4355 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
4356 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4360 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
4362 int cap
= pci_pcie_cap(pdev
);
4367 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4368 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
4369 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4373 #define R8168_CPCMD_QUIRK_MASK (\
4384 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4386 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4388 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4390 rtl_tx_performance_tweak(pdev
,
4391 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4394 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4396 rtl_hw_start_8168bb(ioaddr
, pdev
);
4398 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4400 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4403 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4405 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
4407 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4409 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4411 rtl_disable_clock_request(pdev
);
4413 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4416 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4418 static const struct ephy_info e_info_8168cp
[] = {
4419 { 0x01, 0, 0x0001 },
4420 { 0x02, 0x0800, 0x1000 },
4421 { 0x03, 0, 0x0042 },
4422 { 0x06, 0x0080, 0x0000 },
4426 rtl_csi_access_enable_2(ioaddr
);
4428 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
4430 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4433 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4435 rtl_csi_access_enable_2(ioaddr
);
4437 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4439 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4441 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4444 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4446 rtl_csi_access_enable_2(ioaddr
);
4448 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4451 RTL_W8(DBG_REG
, 0x20);
4453 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4455 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4457 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4460 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4462 static const struct ephy_info e_info_8168c_1
[] = {
4463 { 0x02, 0x0800, 0x1000 },
4464 { 0x03, 0, 0x0002 },
4465 { 0x06, 0x0080, 0x0000 }
4468 rtl_csi_access_enable_2(ioaddr
);
4470 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4472 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
4474 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4477 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4479 static const struct ephy_info e_info_8168c_2
[] = {
4480 { 0x01, 0, 0x0001 },
4481 { 0x03, 0x0400, 0x0220 }
4484 rtl_csi_access_enable_2(ioaddr
);
4486 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
4488 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4491 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4493 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4496 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4498 rtl_csi_access_enable_2(ioaddr
);
4500 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4503 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4505 rtl_csi_access_enable_2(ioaddr
);
4507 rtl_disable_clock_request(pdev
);
4509 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4511 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4513 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4516 static void rtl_hw_start_8168dp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4518 rtl_csi_access_enable_1(ioaddr
);
4520 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4522 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4524 rtl_disable_clock_request(pdev
);
4527 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4529 static const struct ephy_info e_info_8168d_4
[] = {
4531 { 0x19, 0x20, 0x50 },
4536 rtl_csi_access_enable_1(ioaddr
);
4538 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4540 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4542 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4543 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4546 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4547 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4550 rtl_enable_clock_request(pdev
);
4553 static void rtl_hw_start_8168e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4555 static const struct ephy_info e_info_8168e_1
[] = {
4556 { 0x00, 0x0200, 0x0100 },
4557 { 0x00, 0x0000, 0x0004 },
4558 { 0x06, 0x0002, 0x0001 },
4559 { 0x06, 0x0000, 0x0030 },
4560 { 0x07, 0x0000, 0x2000 },
4561 { 0x00, 0x0000, 0x0020 },
4562 { 0x03, 0x5800, 0x2000 },
4563 { 0x03, 0x0000, 0x0001 },
4564 { 0x01, 0x0800, 0x1000 },
4565 { 0x07, 0x0000, 0x4000 },
4566 { 0x1e, 0x0000, 0x2000 },
4567 { 0x19, 0xffff, 0xfe6c },
4568 { 0x0a, 0x0000, 0x0040 }
4571 rtl_csi_access_enable_2(ioaddr
);
4573 rtl_ephy_init(ioaddr
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
4575 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4577 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4579 rtl_disable_clock_request(pdev
);
4581 /* Reset tx FIFO pointer */
4582 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
4583 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
4585 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4588 static void rtl_hw_start_8168e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4590 static const struct ephy_info e_info_8168e_2
[] = {
4591 { 0x09, 0x0000, 0x0080 },
4592 { 0x19, 0x0000, 0x0224 }
4595 rtl_csi_access_enable_1(ioaddr
);
4597 rtl_ephy_init(ioaddr
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
4599 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4601 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4602 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4603 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4604 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4605 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4606 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
4607 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4608 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4611 RTL_W8(MaxTxPacketSize
, EarlySize
);
4613 rtl_disable_clock_request(pdev
);
4615 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4616 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4618 /* Adjust EEE LED frequency */
4619 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4621 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4622 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4623 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4626 static void rtl_hw_start_8168f_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4628 static const struct ephy_info e_info_8168f_1
[] = {
4629 { 0x06, 0x00c0, 0x0020 },
4630 { 0x08, 0x0001, 0x0002 },
4631 { 0x09, 0x0000, 0x0080 },
4632 { 0x19, 0x0000, 0x0224 }
4635 rtl_csi_access_enable_1(ioaddr
);
4637 rtl_ephy_init(ioaddr
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
4639 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4641 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4642 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4643 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4644 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4645 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
4646 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
4647 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4648 rtl_w1w0_eri(ioaddr
, 0x1d0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4649 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4650 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x00000060, ERIAR_EXGMAC
);
4651 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4654 RTL_W8(MaxTxPacketSize
, EarlySize
);
4656 rtl_disable_clock_request(pdev
);
4658 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4659 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4661 /* Adjust EEE LED frequency */
4662 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4664 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4665 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4666 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4669 static void rtl_hw_start_8168(struct net_device
*dev
)
4671 struct rtl8169_private
*tp
= netdev_priv(dev
);
4672 void __iomem
*ioaddr
= tp
->mmio_addr
;
4673 struct pci_dev
*pdev
= tp
->pci_dev
;
4675 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4677 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4679 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4681 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4683 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4685 RTL_W16(IntrMitigate
, 0x5151);
4687 /* Work around for RxFIFO overflow. */
4688 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
4689 tp
->mac_version
== RTL_GIGA_MAC_VER_22
) {
4690 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
4691 tp
->intr_event
&= ~RxOverflow
;
4694 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4696 rtl_set_rx_mode(dev
);
4698 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4699 (InterFrameGap
<< TxInterFrameGapShift
));
4703 switch (tp
->mac_version
) {
4704 case RTL_GIGA_MAC_VER_11
:
4705 rtl_hw_start_8168bb(ioaddr
, pdev
);
4708 case RTL_GIGA_MAC_VER_12
:
4709 case RTL_GIGA_MAC_VER_17
:
4710 rtl_hw_start_8168bef(ioaddr
, pdev
);
4713 case RTL_GIGA_MAC_VER_18
:
4714 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
4717 case RTL_GIGA_MAC_VER_19
:
4718 rtl_hw_start_8168c_1(ioaddr
, pdev
);
4721 case RTL_GIGA_MAC_VER_20
:
4722 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4725 case RTL_GIGA_MAC_VER_21
:
4726 rtl_hw_start_8168c_3(ioaddr
, pdev
);
4729 case RTL_GIGA_MAC_VER_22
:
4730 rtl_hw_start_8168c_4(ioaddr
, pdev
);
4733 case RTL_GIGA_MAC_VER_23
:
4734 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
4737 case RTL_GIGA_MAC_VER_24
:
4738 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
4741 case RTL_GIGA_MAC_VER_25
:
4742 case RTL_GIGA_MAC_VER_26
:
4743 case RTL_GIGA_MAC_VER_27
:
4744 rtl_hw_start_8168d(ioaddr
, pdev
);
4747 case RTL_GIGA_MAC_VER_28
:
4748 rtl_hw_start_8168d_4(ioaddr
, pdev
);
4751 case RTL_GIGA_MAC_VER_31
:
4752 rtl_hw_start_8168dp(ioaddr
, pdev
);
4755 case RTL_GIGA_MAC_VER_32
:
4756 case RTL_GIGA_MAC_VER_33
:
4757 rtl_hw_start_8168e_1(ioaddr
, pdev
);
4759 case RTL_GIGA_MAC_VER_34
:
4760 rtl_hw_start_8168e_2(ioaddr
, pdev
);
4763 case RTL_GIGA_MAC_VER_35
:
4764 case RTL_GIGA_MAC_VER_36
:
4765 rtl_hw_start_8168f_1(ioaddr
, pdev
);
4769 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
4770 dev
->name
, tp
->mac_version
);
4774 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4776 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4778 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4780 RTL_W16(IntrMask
, tp
->intr_event
);
4783 #define R810X_CPCMD_QUIRK_MASK (\
4794 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4796 static const struct ephy_info e_info_8102e_1
[] = {
4797 { 0x01, 0, 0x6e65 },
4798 { 0x02, 0, 0x091f },
4799 { 0x03, 0, 0xc2f9 },
4800 { 0x06, 0, 0xafb5 },
4801 { 0x07, 0, 0x0e00 },
4802 { 0x19, 0, 0xec80 },
4803 { 0x01, 0, 0x2e65 },
4808 rtl_csi_access_enable_2(ioaddr
);
4810 RTL_W8(DBG_REG
, FIX_NAK_1
);
4812 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4815 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
4816 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4818 cfg1
= RTL_R8(Config1
);
4819 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
4820 RTL_W8(Config1
, cfg1
& ~LEDS0
);
4822 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
4825 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4827 rtl_csi_access_enable_2(ioaddr
);
4829 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4831 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
4832 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4835 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4837 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4839 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
4842 static void rtl_hw_start_8105e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4844 static const struct ephy_info e_info_8105e_1
[] = {
4845 { 0x07, 0, 0x4000 },
4846 { 0x19, 0, 0x0200 },
4847 { 0x19, 0, 0x0020 },
4848 { 0x1e, 0, 0x2000 },
4849 { 0x03, 0, 0x0001 },
4850 { 0x19, 0, 0x0100 },
4851 { 0x19, 0, 0x0004 },
4855 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4856 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
4858 /* Disable Early Tally Counter */
4859 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
4861 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
4862 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4864 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
4867 static void rtl_hw_start_8105e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4869 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4870 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
4873 static void rtl_hw_start_8101(struct net_device
*dev
)
4875 struct rtl8169_private
*tp
= netdev_priv(dev
);
4876 void __iomem
*ioaddr
= tp
->mmio_addr
;
4877 struct pci_dev
*pdev
= tp
->pci_dev
;
4879 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
4880 tp
->mac_version
== RTL_GIGA_MAC_VER_16
) {
4881 int cap
= pci_pcie_cap(pdev
);
4884 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
4885 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4889 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4891 switch (tp
->mac_version
) {
4892 case RTL_GIGA_MAC_VER_07
:
4893 rtl_hw_start_8102e_1(ioaddr
, pdev
);
4896 case RTL_GIGA_MAC_VER_08
:
4897 rtl_hw_start_8102e_3(ioaddr
, pdev
);
4900 case RTL_GIGA_MAC_VER_09
:
4901 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4904 case RTL_GIGA_MAC_VER_29
:
4905 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4907 case RTL_GIGA_MAC_VER_30
:
4908 rtl_hw_start_8105e_2(ioaddr
, pdev
);
4912 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4914 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4916 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4918 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
4919 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4921 RTL_W16(IntrMitigate
, 0x0000);
4923 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4925 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4926 rtl_set_rx_tx_config_registers(tp
);
4930 rtl_set_rx_mode(dev
);
4932 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
4934 RTL_W16(IntrMask
, tp
->intr_event
);
4937 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
4939 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
4943 netdev_update_features(dev
);
4948 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
4950 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
4951 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
4954 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
4955 void **data_buff
, struct RxDesc
*desc
)
4957 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
4962 rtl8169_make_unusable_by_asic(desc
);
4965 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
4967 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
4969 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
4972 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
4975 desc
->addr
= cpu_to_le64(mapping
);
4977 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4980 static inline void *rtl8169_align(void *data
)
4982 return (void *)ALIGN((long)data
, 16);
4985 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
4986 struct RxDesc
*desc
)
4990 struct device
*d
= &tp
->pci_dev
->dev
;
4991 struct net_device
*dev
= tp
->dev
;
4992 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
4994 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
4998 if (rtl8169_align(data
) != data
) {
5000 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
5005 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
5007 if (unlikely(dma_mapping_error(d
, mapping
))) {
5008 if (net_ratelimit())
5009 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
5013 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
5021 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
5025 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5026 if (tp
->Rx_databuff
[i
]) {
5027 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
5028 tp
->RxDescArray
+ i
);
5033 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
5035 desc
->opts1
|= cpu_to_le32(RingEnd
);
5038 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
5042 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5045 if (tp
->Rx_databuff
[i
])
5048 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
5050 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
5053 tp
->Rx_databuff
[i
] = data
;
5056 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
5060 rtl8169_rx_clear(tp
);
5064 static int rtl8169_init_ring(struct net_device
*dev
)
5066 struct rtl8169_private
*tp
= netdev_priv(dev
);
5068 rtl8169_init_ring_indexes(tp
);
5070 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
5071 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
5073 return rtl8169_rx_fill(tp
);
5076 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
5077 struct TxDesc
*desc
)
5079 unsigned int len
= tx_skb
->len
;
5081 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
5089 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
5094 for (i
= 0; i
< n
; i
++) {
5095 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
5096 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5097 unsigned int len
= tx_skb
->len
;
5100 struct sk_buff
*skb
= tx_skb
->skb
;
5102 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5103 tp
->TxDescArray
+ entry
);
5105 tp
->dev
->stats
.tx_dropped
++;
5113 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
5115 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
5116 tp
->cur_tx
= tp
->dirty_tx
= 0;
5119 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
5121 struct rtl8169_private
*tp
= netdev_priv(dev
);
5123 PREPARE_DELAYED_WORK(&tp
->task
, task
);
5124 schedule_delayed_work(&tp
->task
, 4);
5127 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
5129 struct rtl8169_private
*tp
= netdev_priv(dev
);
5130 void __iomem
*ioaddr
= tp
->mmio_addr
;
5132 synchronize_irq(dev
->irq
);
5134 /* Wait for any pending NAPI task to complete */
5135 napi_disable(&tp
->napi
);
5137 rtl8169_irq_mask_and_ack(ioaddr
);
5139 tp
->intr_mask
= 0xffff;
5140 RTL_W16(IntrMask
, tp
->intr_event
);
5141 napi_enable(&tp
->napi
);
5144 static void rtl8169_reinit_task(struct work_struct
*work
)
5146 struct rtl8169_private
*tp
=
5147 container_of(work
, struct rtl8169_private
, task
.work
);
5148 struct net_device
*dev
= tp
->dev
;
5153 if (!netif_running(dev
))
5156 rtl8169_wait_for_quiescence(dev
);
5159 ret
= rtl8169_open(dev
);
5160 if (unlikely(ret
< 0)) {
5161 if (net_ratelimit())
5162 netif_err(tp
, drv
, dev
,
5163 "reinit failure (status = %d). Rescheduling\n",
5165 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
5172 static void rtl8169_reset_task(struct work_struct
*work
)
5174 struct rtl8169_private
*tp
=
5175 container_of(work
, struct rtl8169_private
, task
.work
);
5176 struct net_device
*dev
= tp
->dev
;
5181 if (!netif_running(dev
))
5184 rtl8169_wait_for_quiescence(dev
);
5186 for (i
= 0; i
< NUM_RX_DESC
; i
++)
5187 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
5189 rtl8169_tx_clear(tp
);
5191 rtl8169_hw_reset(tp
);
5193 netif_wake_queue(dev
);
5194 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
5200 static void rtl8169_tx_timeout(struct net_device
*dev
)
5202 struct rtl8169_private
*tp
= netdev_priv(dev
);
5204 rtl8169_hw_reset(tp
);
5206 /* Let's wait a bit while any (async) irq lands on */
5207 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5210 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
5213 struct skb_shared_info
*info
= skb_shinfo(skb
);
5214 unsigned int cur_frag
, entry
;
5215 struct TxDesc
* uninitialized_var(txd
);
5216 struct device
*d
= &tp
->pci_dev
->dev
;
5219 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
5220 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
5225 entry
= (entry
+ 1) % NUM_TX_DESC
;
5227 txd
= tp
->TxDescArray
+ entry
;
5229 addr
= skb_frag_address(frag
);
5230 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5231 if (unlikely(dma_mapping_error(d
, mapping
))) {
5232 if (net_ratelimit())
5233 netif_err(tp
, drv
, tp
->dev
,
5234 "Failed to map TX fragments DMA!\n");
5238 /* Anti gcc 2.95.3 bugware (sic) */
5239 status
= opts
[0] | len
|
5240 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5242 txd
->opts1
= cpu_to_le32(status
);
5243 txd
->opts2
= cpu_to_le32(opts
[1]);
5244 txd
->addr
= cpu_to_le64(mapping
);
5246 tp
->tx_skb
[entry
].len
= len
;
5250 tp
->tx_skb
[entry
].skb
= skb
;
5251 txd
->opts1
|= cpu_to_le32(LastFrag
);
5257 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5261 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
5262 struct sk_buff
*skb
, u32
*opts
)
5264 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
5265 u32 mss
= skb_shinfo(skb
)->gso_size
;
5266 int offset
= info
->opts_offset
;
5270 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
5271 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5272 const struct iphdr
*ip
= ip_hdr(skb
);
5274 if (ip
->protocol
== IPPROTO_TCP
)
5275 opts
[offset
] |= info
->checksum
.tcp
;
5276 else if (ip
->protocol
== IPPROTO_UDP
)
5277 opts
[offset
] |= info
->checksum
.udp
;
5283 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5284 struct net_device
*dev
)
5286 struct rtl8169_private
*tp
= netdev_priv(dev
);
5287 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
5288 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
5289 void __iomem
*ioaddr
= tp
->mmio_addr
;
5290 struct device
*d
= &tp
->pci_dev
->dev
;
5296 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
5297 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
5301 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
5304 len
= skb_headlen(skb
);
5305 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
5306 if (unlikely(dma_mapping_error(d
, mapping
))) {
5307 if (net_ratelimit())
5308 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
5312 tp
->tx_skb
[entry
].len
= len
;
5313 txd
->addr
= cpu_to_le64(mapping
);
5315 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
5318 rtl8169_tso_csum(tp
, skb
, opts
);
5320 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
5324 opts
[0] |= FirstFrag
;
5326 opts
[0] |= FirstFrag
| LastFrag
;
5327 tp
->tx_skb
[entry
].skb
= skb
;
5330 txd
->opts2
= cpu_to_le32(opts
[1]);
5334 /* Anti gcc 2.95.3 bugware (sic) */
5335 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5336 txd
->opts1
= cpu_to_le32(status
);
5338 tp
->cur_tx
+= frags
+ 1;
5342 RTL_W8(TxPoll
, NPQ
);
5344 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
5345 netif_stop_queue(dev
);
5347 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
5348 netif_wake_queue(dev
);
5351 return NETDEV_TX_OK
;
5354 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
5357 dev
->stats
.tx_dropped
++;
5358 return NETDEV_TX_OK
;
5361 netif_stop_queue(dev
);
5362 dev
->stats
.tx_dropped
++;
5363 return NETDEV_TX_BUSY
;
5366 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
5368 struct rtl8169_private
*tp
= netdev_priv(dev
);
5369 struct pci_dev
*pdev
= tp
->pci_dev
;
5370 u16 pci_status
, pci_cmd
;
5372 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
5373 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
5375 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5376 pci_cmd
, pci_status
);
5379 * The recovery sequence below admits a very elaborated explanation:
5380 * - it seems to work;
5381 * - I did not see what else could be done;
5382 * - it makes iop3xx happy.
5384 * Feel free to adjust to your needs.
5386 if (pdev
->broken_parity_status
)
5387 pci_cmd
&= ~PCI_COMMAND_PARITY
;
5389 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
5391 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
5393 pci_write_config_word(pdev
, PCI_STATUS
,
5394 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
5395 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
5396 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
5398 /* The infamous DAC f*ckup only happens at boot time */
5399 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
5400 void __iomem
*ioaddr
= tp
->mmio_addr
;
5402 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
5403 tp
->cp_cmd
&= ~PCIDAC
;
5404 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5405 dev
->features
&= ~NETIF_F_HIGHDMA
;
5408 rtl8169_hw_reset(tp
);
5410 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
5413 static void rtl8169_tx_interrupt(struct net_device
*dev
,
5414 struct rtl8169_private
*tp
,
5415 void __iomem
*ioaddr
)
5417 unsigned int dirty_tx
, tx_left
;
5419 dirty_tx
= tp
->dirty_tx
;
5421 tx_left
= tp
->cur_tx
- dirty_tx
;
5423 while (tx_left
> 0) {
5424 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
5425 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5429 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
5430 if (status
& DescOwn
)
5433 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5434 tp
->TxDescArray
+ entry
);
5435 if (status
& LastFrag
) {
5436 dev
->stats
.tx_packets
++;
5437 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
5438 dev_kfree_skb(tx_skb
->skb
);
5445 if (tp
->dirty_tx
!= dirty_tx
) {
5446 tp
->dirty_tx
= dirty_tx
;
5448 if (netif_queue_stopped(dev
) &&
5449 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
5450 netif_wake_queue(dev
);
5453 * 8168 hack: TxPoll requests are lost when the Tx packets are
5454 * too close. Let's kick an extra TxPoll request when a burst
5455 * of start_xmit activity is detected (if it is not detected,
5456 * it is slow enough). -- FR
5459 if (tp
->cur_tx
!= dirty_tx
)
5460 RTL_W8(TxPoll
, NPQ
);
5464 static inline int rtl8169_fragmented_frame(u32 status
)
5466 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
5469 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
5471 u32 status
= opts1
& RxProtoMask
;
5473 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
5474 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
5475 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5477 skb_checksum_none_assert(skb
);
5480 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
5481 struct rtl8169_private
*tp
,
5485 struct sk_buff
*skb
;
5486 struct device
*d
= &tp
->pci_dev
->dev
;
5488 data
= rtl8169_align(data
);
5489 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5491 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
5493 memcpy(skb
->data
, data
, pkt_size
);
5494 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5499 static int rtl8169_rx_interrupt(struct net_device
*dev
,
5500 struct rtl8169_private
*tp
,
5501 void __iomem
*ioaddr
, u32 budget
)
5503 unsigned int cur_rx
, rx_left
;
5506 cur_rx
= tp
->cur_rx
;
5507 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
5508 rx_left
= min(rx_left
, budget
);
5510 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
5511 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
5512 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
5516 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
5518 if (status
& DescOwn
)
5520 if (unlikely(status
& RxRES
)) {
5521 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
5523 dev
->stats
.rx_errors
++;
5524 if (status
& (RxRWT
| RxRUNT
))
5525 dev
->stats
.rx_length_errors
++;
5527 dev
->stats
.rx_crc_errors
++;
5528 if (status
& RxFOVF
) {
5529 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5530 dev
->stats
.rx_fifo_errors
++;
5532 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5534 struct sk_buff
*skb
;
5535 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
5536 int pkt_size
= (status
& 0x00001FFF) - 4;
5539 * The driver does not support incoming fragmented
5540 * frames. They are seen as a symptom of over-mtu
5543 if (unlikely(rtl8169_fragmented_frame(status
))) {
5544 dev
->stats
.rx_dropped
++;
5545 dev
->stats
.rx_length_errors
++;
5546 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5550 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
5551 tp
, pkt_size
, addr
);
5552 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5554 dev
->stats
.rx_dropped
++;
5558 rtl8169_rx_csum(skb
, status
);
5559 skb_put(skb
, pkt_size
);
5560 skb
->protocol
= eth_type_trans(skb
, dev
);
5562 rtl8169_rx_vlan_tag(desc
, skb
);
5564 napi_gro_receive(&tp
->napi
, skb
);
5566 dev
->stats
.rx_bytes
+= pkt_size
;
5567 dev
->stats
.rx_packets
++;
5570 /* Work around for AMD plateform. */
5571 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
5572 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
5578 count
= cur_rx
- tp
->cur_rx
;
5579 tp
->cur_rx
= cur_rx
;
5581 tp
->dirty_rx
+= count
;
5586 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5588 struct net_device
*dev
= dev_instance
;
5589 struct rtl8169_private
*tp
= netdev_priv(dev
);
5590 void __iomem
*ioaddr
= tp
->mmio_addr
;
5594 /* loop handling interrupts until we have no new ones or
5595 * we hit a invalid/hotplug case.
5597 status
= RTL_R16(IntrStatus
);
5598 while (status
&& status
!= 0xffff) {
5601 /* Handle all of the error cases first. These will reset
5602 * the chip, so just exit the loop.
5604 if (unlikely(!netif_running(dev
))) {
5605 rtl8169_hw_reset(tp
);
5609 if (unlikely(status
& RxFIFOOver
)) {
5610 switch (tp
->mac_version
) {
5611 /* Work around for rx fifo overflow */
5612 case RTL_GIGA_MAC_VER_11
:
5613 case RTL_GIGA_MAC_VER_22
:
5614 case RTL_GIGA_MAC_VER_26
:
5615 netif_stop_queue(dev
);
5616 rtl8169_tx_timeout(dev
);
5618 /* Testers needed. */
5619 case RTL_GIGA_MAC_VER_17
:
5620 case RTL_GIGA_MAC_VER_19
:
5621 case RTL_GIGA_MAC_VER_20
:
5622 case RTL_GIGA_MAC_VER_21
:
5623 case RTL_GIGA_MAC_VER_23
:
5624 case RTL_GIGA_MAC_VER_24
:
5625 case RTL_GIGA_MAC_VER_27
:
5626 case RTL_GIGA_MAC_VER_28
:
5627 case RTL_GIGA_MAC_VER_31
:
5628 /* Experimental science. Pktgen proof. */
5629 case RTL_GIGA_MAC_VER_12
:
5630 case RTL_GIGA_MAC_VER_25
:
5631 if (status
== RxFIFOOver
)
5639 if (unlikely(status
& SYSErr
)) {
5640 rtl8169_pcierr_interrupt(dev
);
5644 if (status
& LinkChg
)
5645 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
5647 /* We need to see the lastest version of tp->intr_mask to
5648 * avoid ignoring an MSI interrupt and having to wait for
5649 * another event which may never come.
5652 if (status
& tp
->intr_mask
& tp
->napi_event
) {
5653 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
5654 tp
->intr_mask
= ~tp
->napi_event
;
5656 if (likely(napi_schedule_prep(&tp
->napi
)))
5657 __napi_schedule(&tp
->napi
);
5659 netif_info(tp
, intr
, dev
,
5660 "interrupt %04x in poll\n", status
);
5663 /* We only get a new MSI interrupt when all active irq
5664 * sources on the chip have been acknowledged. So, ack
5665 * everything we've seen and check if new sources have become
5666 * active to avoid blocking all interrupts from the chip.
5669 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
5670 status
= RTL_R16(IntrStatus
);
5673 return IRQ_RETVAL(handled
);
5676 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5678 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5679 struct net_device
*dev
= tp
->dev
;
5680 void __iomem
*ioaddr
= tp
->mmio_addr
;
5683 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
5684 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
5686 if (work_done
< budget
) {
5687 napi_complete(napi
);
5689 /* We need for force the visibility of tp->intr_mask
5690 * for other CPUs, as we can loose an MSI interrupt
5691 * and potentially wait for a retransmit timeout if we don't.
5692 * The posted write to IntrMask is safe, as it will
5693 * eventually make it to the chip and we won't loose anything
5696 tp
->intr_mask
= 0xffff;
5698 RTL_W16(IntrMask
, tp
->intr_event
);
5704 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5706 struct rtl8169_private
*tp
= netdev_priv(dev
);
5708 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5711 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5712 RTL_W32(RxMissed
, 0);
5715 static void rtl8169_down(struct net_device
*dev
)
5717 struct rtl8169_private
*tp
= netdev_priv(dev
);
5718 void __iomem
*ioaddr
= tp
->mmio_addr
;
5720 del_timer_sync(&tp
->timer
);
5722 netif_stop_queue(dev
);
5724 napi_disable(&tp
->napi
);
5726 spin_lock_irq(&tp
->lock
);
5728 rtl8169_hw_reset(tp
);
5730 * At this point device interrupts can not be enabled in any function,
5731 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5732 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5734 rtl8169_rx_missed(dev
, ioaddr
);
5736 spin_unlock_irq(&tp
->lock
);
5738 synchronize_irq(dev
->irq
);
5740 /* Give a racing hard_start_xmit a few cycles to complete. */
5741 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5743 rtl8169_tx_clear(tp
);
5745 rtl8169_rx_clear(tp
);
5747 rtl_pll_power_down(tp
);
5750 static int rtl8169_close(struct net_device
*dev
)
5752 struct rtl8169_private
*tp
= netdev_priv(dev
);
5753 struct pci_dev
*pdev
= tp
->pci_dev
;
5755 pm_runtime_get_sync(&pdev
->dev
);
5757 /* Update counters before going down */
5758 rtl8169_update_counters(dev
);
5762 free_irq(dev
->irq
, dev
);
5764 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5766 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5768 tp
->TxDescArray
= NULL
;
5769 tp
->RxDescArray
= NULL
;
5771 pm_runtime_put_sync(&pdev
->dev
);
5776 static void rtl_set_rx_mode(struct net_device
*dev
)
5778 struct rtl8169_private
*tp
= netdev_priv(dev
);
5779 void __iomem
*ioaddr
= tp
->mmio_addr
;
5780 unsigned long flags
;
5781 u32 mc_filter
[2]; /* Multicast hash filter */
5785 if (dev
->flags
& IFF_PROMISC
) {
5786 /* Unconditionally log net taps. */
5787 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5789 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5791 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5792 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5793 (dev
->flags
& IFF_ALLMULTI
)) {
5794 /* Too many to filter perfectly -- accept all multicasts. */
5795 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5796 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5798 struct netdev_hw_addr
*ha
;
5800 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5801 mc_filter
[1] = mc_filter
[0] = 0;
5802 netdev_for_each_mc_addr(ha
, dev
) {
5803 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5804 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
5805 rx_mode
|= AcceptMulticast
;
5809 spin_lock_irqsave(&tp
->lock
, flags
);
5811 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
5813 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
5814 u32 data
= mc_filter
[0];
5816 mc_filter
[0] = swab32(mc_filter
[1]);
5817 mc_filter
[1] = swab32(data
);
5820 RTL_W32(MAR0
+ 4, mc_filter
[1]);
5821 RTL_W32(MAR0
+ 0, mc_filter
[0]);
5823 RTL_W32(RxConfig
, tmp
);
5825 spin_unlock_irqrestore(&tp
->lock
, flags
);
5829 * rtl8169_get_stats - Get rtl8169 read/write statistics
5830 * @dev: The Ethernet Device to get statistics for
5832 * Get TX/RX statistics for rtl8169
5834 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
5836 struct rtl8169_private
*tp
= netdev_priv(dev
);
5837 void __iomem
*ioaddr
= tp
->mmio_addr
;
5838 unsigned long flags
;
5840 if (netif_running(dev
)) {
5841 spin_lock_irqsave(&tp
->lock
, flags
);
5842 rtl8169_rx_missed(dev
, ioaddr
);
5843 spin_unlock_irqrestore(&tp
->lock
, flags
);
5849 static void rtl8169_net_suspend(struct net_device
*dev
)
5851 struct rtl8169_private
*tp
= netdev_priv(dev
);
5853 if (!netif_running(dev
))
5856 rtl_pll_power_down(tp
);
5858 netif_device_detach(dev
);
5859 netif_stop_queue(dev
);
5864 static int rtl8169_suspend(struct device
*device
)
5866 struct pci_dev
*pdev
= to_pci_dev(device
);
5867 struct net_device
*dev
= pci_get_drvdata(pdev
);
5869 rtl8169_net_suspend(dev
);
5874 static void __rtl8169_resume(struct net_device
*dev
)
5876 struct rtl8169_private
*tp
= netdev_priv(dev
);
5878 netif_device_attach(dev
);
5880 rtl_pll_power_up(tp
);
5882 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5885 static int rtl8169_resume(struct device
*device
)
5887 struct pci_dev
*pdev
= to_pci_dev(device
);
5888 struct net_device
*dev
= pci_get_drvdata(pdev
);
5889 struct rtl8169_private
*tp
= netdev_priv(dev
);
5891 rtl8169_init_phy(dev
, tp
);
5893 if (netif_running(dev
))
5894 __rtl8169_resume(dev
);
5899 static int rtl8169_runtime_suspend(struct device
*device
)
5901 struct pci_dev
*pdev
= to_pci_dev(device
);
5902 struct net_device
*dev
= pci_get_drvdata(pdev
);
5903 struct rtl8169_private
*tp
= netdev_priv(dev
);
5905 if (!tp
->TxDescArray
)
5908 spin_lock_irq(&tp
->lock
);
5909 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
5910 __rtl8169_set_wol(tp
, WAKE_ANY
);
5911 spin_unlock_irq(&tp
->lock
);
5913 rtl8169_net_suspend(dev
);
5918 static int rtl8169_runtime_resume(struct device
*device
)
5920 struct pci_dev
*pdev
= to_pci_dev(device
);
5921 struct net_device
*dev
= pci_get_drvdata(pdev
);
5922 struct rtl8169_private
*tp
= netdev_priv(dev
);
5924 if (!tp
->TxDescArray
)
5927 spin_lock_irq(&tp
->lock
);
5928 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
5929 tp
->saved_wolopts
= 0;
5930 spin_unlock_irq(&tp
->lock
);
5932 rtl8169_init_phy(dev
, tp
);
5934 __rtl8169_resume(dev
);
5939 static int rtl8169_runtime_idle(struct device
*device
)
5941 struct pci_dev
*pdev
= to_pci_dev(device
);
5942 struct net_device
*dev
= pci_get_drvdata(pdev
);
5943 struct rtl8169_private
*tp
= netdev_priv(dev
);
5945 return tp
->TxDescArray
? -EBUSY
: 0;
5948 static const struct dev_pm_ops rtl8169_pm_ops
= {
5949 .suspend
= rtl8169_suspend
,
5950 .resume
= rtl8169_resume
,
5951 .freeze
= rtl8169_suspend
,
5952 .thaw
= rtl8169_resume
,
5953 .poweroff
= rtl8169_suspend
,
5954 .restore
= rtl8169_resume
,
5955 .runtime_suspend
= rtl8169_runtime_suspend
,
5956 .runtime_resume
= rtl8169_runtime_resume
,
5957 .runtime_idle
= rtl8169_runtime_idle
,
5960 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5962 #else /* !CONFIG_PM */
5964 #define RTL8169_PM_OPS NULL
5966 #endif /* !CONFIG_PM */
5968 static void rtl_shutdown(struct pci_dev
*pdev
)
5970 struct net_device
*dev
= pci_get_drvdata(pdev
);
5971 struct rtl8169_private
*tp
= netdev_priv(dev
);
5972 void __iomem
*ioaddr
= tp
->mmio_addr
;
5974 rtl8169_net_suspend(dev
);
5976 /* Restore original MAC address */
5977 rtl_rar_set(tp
, dev
->perm_addr
);
5979 spin_lock_irq(&tp
->lock
);
5981 rtl8169_hw_reset(tp
);
5983 spin_unlock_irq(&tp
->lock
);
5985 if (system_state
== SYSTEM_POWER_OFF
) {
5986 /* WoL fails with 8168b when the receiver is disabled. */
5987 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
5988 tp
->mac_version
== RTL_GIGA_MAC_VER_12
||
5989 tp
->mac_version
== RTL_GIGA_MAC_VER_17
) &&
5990 (tp
->features
& RTL_FEATURE_WOL
)) {
5991 pci_clear_master(pdev
);
5993 RTL_W8(ChipCmd
, CmdRxEnb
);
5998 pci_wake_from_d3(pdev
, true);
5999 pci_set_power_state(pdev
, PCI_D3hot
);
6003 static struct pci_driver rtl8169_pci_driver
= {
6005 .id_table
= rtl8169_pci_tbl
,
6006 .probe
= rtl8169_init_one
,
6007 .remove
= __devexit_p(rtl8169_remove_one
),
6008 .shutdown
= rtl_shutdown
,
6009 .driver
.pm
= RTL8169_PM_OPS
,
6012 static int __init
rtl8169_init_module(void)
6014 return pci_register_driver(&rtl8169_pci_driver
);
6017 static void __exit
rtl8169_cleanup_module(void)
6019 pci_unregister_driver(&rtl8169_pci_driver
);
6022 module_init(rtl8169_init_module
);
6023 module_exit(rtl8169_cleanup_module
);