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c03891be22d030717f16fccda3e9f2122ff7d627
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
32
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
59
60 #ifdef RTL8169_DEBUG
61 #define assert(expr) \
62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
65 }
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
68 #else
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
72
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
75
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
82
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
86
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
100
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
108
109 enum mac_version {
110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
143 RTL_GIGA_MAC_VER_34,
144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
146 RTL_GIGA_MAC_VER_37,
147 RTL_GIGA_MAC_VER_38,
148 RTL_GIGA_MAC_VER_39,
149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
151 RTL_GIGA_MAC_VER_42,
152 RTL_GIGA_MAC_VER_43,
153 RTL_GIGA_MAC_VER_44,
154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
158 RTL_GIGA_MAC_NONE = 0xff,
159 };
160
161 enum rtl_tx_desc_version {
162 RTL_TD_0 = 0,
163 RTL_TD_1 = 1,
164 };
165
166 #define JUMBO_1K ETH_DATA_LEN
167 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
168 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
169 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
170 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
171
172 #define _R(NAME,TD,FW,SZ,B) { \
173 .name = NAME, \
174 .txd_version = TD, \
175 .fw_name = FW, \
176 .jumbo_max = SZ, \
177 .jumbo_tx_csum = B \
178 }
179
180 static const struct {
181 const char *name;
182 enum rtl_tx_desc_version txd_version;
183 const char *fw_name;
184 u16 jumbo_max;
185 bool jumbo_tx_csum;
186 } rtl_chip_infos[] = {
187 /* PCI devices. */
188 [RTL_GIGA_MAC_VER_01] =
189 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
190 [RTL_GIGA_MAC_VER_02] =
191 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
192 [RTL_GIGA_MAC_VER_03] =
193 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
194 [RTL_GIGA_MAC_VER_04] =
195 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
196 [RTL_GIGA_MAC_VER_05] =
197 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
198 [RTL_GIGA_MAC_VER_06] =
199 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
200 /* PCI-E devices. */
201 [RTL_GIGA_MAC_VER_07] =
202 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
203 [RTL_GIGA_MAC_VER_08] =
204 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
205 [RTL_GIGA_MAC_VER_09] =
206 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
207 [RTL_GIGA_MAC_VER_10] =
208 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
209 [RTL_GIGA_MAC_VER_11] =
210 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
211 [RTL_GIGA_MAC_VER_12] =
212 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
213 [RTL_GIGA_MAC_VER_13] =
214 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
215 [RTL_GIGA_MAC_VER_14] =
216 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
217 [RTL_GIGA_MAC_VER_15] =
218 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
219 [RTL_GIGA_MAC_VER_16] =
220 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
221 [RTL_GIGA_MAC_VER_17] =
222 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
223 [RTL_GIGA_MAC_VER_18] =
224 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
225 [RTL_GIGA_MAC_VER_19] =
226 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
227 [RTL_GIGA_MAC_VER_20] =
228 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
229 [RTL_GIGA_MAC_VER_21] =
230 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
231 [RTL_GIGA_MAC_VER_22] =
232 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
233 [RTL_GIGA_MAC_VER_23] =
234 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
235 [RTL_GIGA_MAC_VER_24] =
236 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
237 [RTL_GIGA_MAC_VER_25] =
238 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
239 JUMBO_9K, false),
240 [RTL_GIGA_MAC_VER_26] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
242 JUMBO_9K, false),
243 [RTL_GIGA_MAC_VER_27] =
244 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
245 [RTL_GIGA_MAC_VER_28] =
246 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
247 [RTL_GIGA_MAC_VER_29] =
248 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
249 JUMBO_1K, true),
250 [RTL_GIGA_MAC_VER_30] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
253 [RTL_GIGA_MAC_VER_31] =
254 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
255 [RTL_GIGA_MAC_VER_32] =
256 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
257 JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_33] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
260 JUMBO_9K, false),
261 [RTL_GIGA_MAC_VER_34] =
262 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
263 JUMBO_9K, false),
264 [RTL_GIGA_MAC_VER_35] =
265 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_36] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
269 JUMBO_9K, false),
270 [RTL_GIGA_MAC_VER_37] =
271 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
272 JUMBO_1K, true),
273 [RTL_GIGA_MAC_VER_38] =
274 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
275 JUMBO_9K, false),
276 [RTL_GIGA_MAC_VER_39] =
277 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
278 JUMBO_1K, true),
279 [RTL_GIGA_MAC_VER_40] =
280 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
281 JUMBO_9K, false),
282 [RTL_GIGA_MAC_VER_41] =
283 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
284 [RTL_GIGA_MAC_VER_42] =
285 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
286 JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_43] =
288 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
289 JUMBO_1K, true),
290 [RTL_GIGA_MAC_VER_44] =
291 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
292 JUMBO_9K, false),
293 [RTL_GIGA_MAC_VER_45] =
294 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
295 JUMBO_9K, false),
296 [RTL_GIGA_MAC_VER_46] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_47] =
300 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
301 JUMBO_1K, false),
302 [RTL_GIGA_MAC_VER_48] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
304 JUMBO_1K, false),
305 };
306 #undef _R
307
308 enum cfg_version {
309 RTL_CFG_0 = 0x00,
310 RTL_CFG_1,
311 RTL_CFG_2
312 };
313
314 static const struct pci_device_id rtl8169_pci_tbl[] = {
315 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
316 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
317 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
318 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
319 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
320 { PCI_VENDOR_ID_DLINK, 0x4300,
321 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
322 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
323 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
324 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
325 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
326 { PCI_VENDOR_ID_LINKSYS, 0x1032,
327 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
328 { 0x0001, 0x8168,
329 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
330 {0,},
331 };
332
333 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
334
335 static int rx_buf_sz = 16383;
336 static int use_dac;
337 static struct {
338 u32 msg_enable;
339 } debug = { -1 };
340
341 enum rtl_registers {
342 MAC0 = 0, /* Ethernet hardware address. */
343 MAC4 = 4,
344 MAR0 = 8, /* Multicast filter. */
345 CounterAddrLow = 0x10,
346 CounterAddrHigh = 0x14,
347 TxDescStartAddrLow = 0x20,
348 TxDescStartAddrHigh = 0x24,
349 TxHDescStartAddrLow = 0x28,
350 TxHDescStartAddrHigh = 0x2c,
351 FLASH = 0x30,
352 ERSR = 0x36,
353 ChipCmd = 0x37,
354 TxPoll = 0x38,
355 IntrMask = 0x3c,
356 IntrStatus = 0x3e,
357
358 TxConfig = 0x40,
359 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
360 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
361
362 RxConfig = 0x44,
363 #define RX128_INT_EN (1 << 15) /* 8111c and later */
364 #define RX_MULTI_EN (1 << 14) /* 8111c only */
365 #define RXCFG_FIFO_SHIFT 13
366 /* No threshold before first PCI xfer */
367 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
368 #define RX_EARLY_OFF (1 << 11)
369 #define RXCFG_DMA_SHIFT 8
370 /* Unlimited maximum PCI burst. */
371 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
372
373 RxMissed = 0x4c,
374 Cfg9346 = 0x50,
375 Config0 = 0x51,
376 Config1 = 0x52,
377 Config2 = 0x53,
378 #define PME_SIGNAL (1 << 5) /* 8168c and later */
379
380 Config3 = 0x54,
381 Config4 = 0x55,
382 Config5 = 0x56,
383 MultiIntr = 0x5c,
384 PHYAR = 0x60,
385 PHYstatus = 0x6c,
386 RxMaxSize = 0xda,
387 CPlusCmd = 0xe0,
388 IntrMitigate = 0xe2,
389 RxDescAddrLow = 0xe4,
390 RxDescAddrHigh = 0xe8,
391 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
392
393 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
394
395 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
396
397 #define TxPacketMax (8064 >> 7)
398 #define EarlySize 0x27
399
400 FuncEvent = 0xf0,
401 FuncEventMask = 0xf4,
402 FuncPresetState = 0xf8,
403 FuncForceEvent = 0xfc,
404 };
405
406 enum rtl8110_registers {
407 TBICSR = 0x64,
408 TBI_ANAR = 0x68,
409 TBI_LPAR = 0x6a,
410 };
411
412 enum rtl8168_8101_registers {
413 CSIDR = 0x64,
414 CSIAR = 0x68,
415 #define CSIAR_FLAG 0x80000000
416 #define CSIAR_WRITE_CMD 0x80000000
417 #define CSIAR_BYTE_ENABLE 0x0f
418 #define CSIAR_BYTE_ENABLE_SHIFT 12
419 #define CSIAR_ADDR_MASK 0x0fff
420 #define CSIAR_FUNC_CARD 0x00000000
421 #define CSIAR_FUNC_SDIO 0x00010000
422 #define CSIAR_FUNC_NIC 0x00020000
423 #define CSIAR_FUNC_NIC2 0x00010000
424 PMCH = 0x6f,
425 EPHYAR = 0x80,
426 #define EPHYAR_FLAG 0x80000000
427 #define EPHYAR_WRITE_CMD 0x80000000
428 #define EPHYAR_REG_MASK 0x1f
429 #define EPHYAR_REG_SHIFT 16
430 #define EPHYAR_DATA_MASK 0xffff
431 DLLPR = 0xd0,
432 #define PFM_EN (1 << 6)
433 #define TX_10M_PS_EN (1 << 7)
434 DBG_REG = 0xd1,
435 #define FIX_NAK_1 (1 << 4)
436 #define FIX_NAK_2 (1 << 3)
437 TWSI = 0xd2,
438 MCU = 0xd3,
439 #define NOW_IS_OOB (1 << 7)
440 #define TX_EMPTY (1 << 5)
441 #define RX_EMPTY (1 << 4)
442 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
443 #define EN_NDP (1 << 3)
444 #define EN_OOB_RESET (1 << 2)
445 #define LINK_LIST_RDY (1 << 1)
446 EFUSEAR = 0xdc,
447 #define EFUSEAR_FLAG 0x80000000
448 #define EFUSEAR_WRITE_CMD 0x80000000
449 #define EFUSEAR_READ_CMD 0x00000000
450 #define EFUSEAR_REG_MASK 0x03ff
451 #define EFUSEAR_REG_SHIFT 8
452 #define EFUSEAR_DATA_MASK 0xff
453 MISC_1 = 0xf2,
454 #define PFM_D3COLD_EN (1 << 6)
455 };
456
457 enum rtl8168_registers {
458 LED_FREQ = 0x1a,
459 EEE_LED = 0x1b,
460 ERIDR = 0x70,
461 ERIAR = 0x74,
462 #define ERIAR_FLAG 0x80000000
463 #define ERIAR_WRITE_CMD 0x80000000
464 #define ERIAR_READ_CMD 0x00000000
465 #define ERIAR_ADDR_BYTE_ALIGN 4
466 #define ERIAR_TYPE_SHIFT 16
467 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
468 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
469 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
470 #define ERIAR_MASK_SHIFT 12
471 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
472 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
473 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
474 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
475 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
476 EPHY_RXER_NUM = 0x7c,
477 OCPDR = 0xb0, /* OCP GPHY access */
478 #define OCPDR_WRITE_CMD 0x80000000
479 #define OCPDR_READ_CMD 0x00000000
480 #define OCPDR_REG_MASK 0x7f
481 #define OCPDR_GPHY_REG_SHIFT 16
482 #define OCPDR_DATA_MASK 0xffff
483 OCPAR = 0xb4,
484 #define OCPAR_FLAG 0x80000000
485 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
486 #define OCPAR_GPHY_READ_CMD 0x0000f060
487 GPHY_OCP = 0xb8,
488 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
489 MISC = 0xf0, /* 8168e only. */
490 #define TXPLA_RST (1 << 29)
491 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
492 #define PWM_EN (1 << 22)
493 #define RXDV_GATED_EN (1 << 19)
494 #define EARLY_TALLY_EN (1 << 16)
495 };
496
497 enum rtl_register_content {
498 /* InterruptStatusBits */
499 SYSErr = 0x8000,
500 PCSTimeout = 0x4000,
501 SWInt = 0x0100,
502 TxDescUnavail = 0x0080,
503 RxFIFOOver = 0x0040,
504 LinkChg = 0x0020,
505 RxOverflow = 0x0010,
506 TxErr = 0x0008,
507 TxOK = 0x0004,
508 RxErr = 0x0002,
509 RxOK = 0x0001,
510
511 /* RxStatusDesc */
512 RxBOVF = (1 << 24),
513 RxFOVF = (1 << 23),
514 RxRWT = (1 << 22),
515 RxRES = (1 << 21),
516 RxRUNT = (1 << 20),
517 RxCRC = (1 << 19),
518
519 /* ChipCmdBits */
520 StopReq = 0x80,
521 CmdReset = 0x10,
522 CmdRxEnb = 0x08,
523 CmdTxEnb = 0x04,
524 RxBufEmpty = 0x01,
525
526 /* TXPoll register p.5 */
527 HPQ = 0x80, /* Poll cmd on the high prio queue */
528 NPQ = 0x40, /* Poll cmd on the low prio queue */
529 FSWInt = 0x01, /* Forced software interrupt */
530
531 /* Cfg9346Bits */
532 Cfg9346_Lock = 0x00,
533 Cfg9346_Unlock = 0xc0,
534
535 /* rx_mode_bits */
536 AcceptErr = 0x20,
537 AcceptRunt = 0x10,
538 AcceptBroadcast = 0x08,
539 AcceptMulticast = 0x04,
540 AcceptMyPhys = 0x02,
541 AcceptAllPhys = 0x01,
542 #define RX_CONFIG_ACCEPT_MASK 0x3f
543
544 /* TxConfigBits */
545 TxInterFrameGapShift = 24,
546 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
547
548 /* Config1 register p.24 */
549 LEDS1 = (1 << 7),
550 LEDS0 = (1 << 6),
551 Speed_down = (1 << 4),
552 MEMMAP = (1 << 3),
553 IOMAP = (1 << 2),
554 VPD = (1 << 1),
555 PMEnable = (1 << 0), /* Power Management Enable */
556
557 /* Config2 register p. 25 */
558 ClkReqEn = (1 << 7), /* Clock Request Enable */
559 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
560 PCI_Clock_66MHz = 0x01,
561 PCI_Clock_33MHz = 0x00,
562
563 /* Config3 register p.25 */
564 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
565 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
566 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
567 Rdy_to_L23 = (1 << 1), /* L23 Enable */
568 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
569
570 /* Config4 register */
571 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
572
573 /* Config5 register p.27 */
574 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
575 MWF = (1 << 5), /* Accept Multicast wakeup frame */
576 UWF = (1 << 4), /* Accept Unicast wakeup frame */
577 Spi_en = (1 << 3),
578 LanWake = (1 << 1), /* LanWake enable/disable */
579 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
580 ASPM_en = (1 << 0), /* ASPM enable */
581
582 /* TBICSR p.28 */
583 TBIReset = 0x80000000,
584 TBILoopback = 0x40000000,
585 TBINwEnable = 0x20000000,
586 TBINwRestart = 0x10000000,
587 TBILinkOk = 0x02000000,
588 TBINwComplete = 0x01000000,
589
590 /* CPlusCmd p.31 */
591 EnableBist = (1 << 15), // 8168 8101
592 Mac_dbgo_oe = (1 << 14), // 8168 8101
593 Normal_mode = (1 << 13), // unused
594 Force_half_dup = (1 << 12), // 8168 8101
595 Force_rxflow_en = (1 << 11), // 8168 8101
596 Force_txflow_en = (1 << 10), // 8168 8101
597 Cxpl_dbg_sel = (1 << 9), // 8168 8101
598 ASF = (1 << 8), // 8168 8101
599 PktCntrDisable = (1 << 7), // 8168 8101
600 Mac_dbgo_sel = 0x001c, // 8168
601 RxVlan = (1 << 6),
602 RxChkSum = (1 << 5),
603 PCIDAC = (1 << 4),
604 PCIMulRW = (1 << 3),
605 INTT_0 = 0x0000, // 8168
606 INTT_1 = 0x0001, // 8168
607 INTT_2 = 0x0002, // 8168
608 INTT_3 = 0x0003, // 8168
609
610 /* rtl8169_PHYstatus */
611 TBI_Enable = 0x80,
612 TxFlowCtrl = 0x40,
613 RxFlowCtrl = 0x20,
614 _1000bpsF = 0x10,
615 _100bps = 0x08,
616 _10bps = 0x04,
617 LinkStatus = 0x02,
618 FullDup = 0x01,
619
620 /* _TBICSRBit */
621 TBILinkOK = 0x02000000,
622
623 /* DumpCounterCommand */
624 CounterDump = 0x8,
625
626 /* magic enable v2 */
627 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
628 };
629
630 enum rtl_desc_bit {
631 /* First doubleword. */
632 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
633 RingEnd = (1 << 30), /* End of descriptor ring */
634 FirstFrag = (1 << 29), /* First segment of a packet */
635 LastFrag = (1 << 28), /* Final segment of a packet */
636 };
637
638 /* Generic case. */
639 enum rtl_tx_desc_bit {
640 /* First doubleword. */
641 TD_LSO = (1 << 27), /* Large Send Offload */
642 #define TD_MSS_MAX 0x07ffu /* MSS value */
643
644 /* Second doubleword. */
645 TxVlanTag = (1 << 17), /* Add VLAN tag */
646 };
647
648 /* 8169, 8168b and 810x except 8102e. */
649 enum rtl_tx_desc_bit_0 {
650 /* First doubleword. */
651 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
652 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
653 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
654 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
655 };
656
657 /* 8102e, 8168c and beyond. */
658 enum rtl_tx_desc_bit_1 {
659 /* First doubleword. */
660 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
661 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
662 #define GTTCPHO_SHIFT 18
663 #define GTTCPHO_MAX 0x7fU
664
665 /* Second doubleword. */
666 #define TCPHO_SHIFT 18
667 #define TCPHO_MAX 0x3ffU
668 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
669 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
670 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
671 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
672 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
673 };
674
675 enum rtl_rx_desc_bit {
676 /* Rx private */
677 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
678 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
679
680 #define RxProtoUDP (PID1)
681 #define RxProtoTCP (PID0)
682 #define RxProtoIP (PID1 | PID0)
683 #define RxProtoMask RxProtoIP
684
685 IPFail = (1 << 16), /* IP checksum failed */
686 UDPFail = (1 << 15), /* UDP/IP checksum failed */
687 TCPFail = (1 << 14), /* TCP/IP checksum failed */
688 RxVlanTag = (1 << 16), /* VLAN tag available */
689 };
690
691 #define RsvdMask 0x3fffc000
692
693 struct TxDesc {
694 __le32 opts1;
695 __le32 opts2;
696 __le64 addr;
697 };
698
699 struct RxDesc {
700 __le32 opts1;
701 __le32 opts2;
702 __le64 addr;
703 };
704
705 struct ring_info {
706 struct sk_buff *skb;
707 u32 len;
708 u8 __pad[sizeof(void *) - sizeof(u32)];
709 };
710
711 enum features {
712 RTL_FEATURE_WOL = (1 << 0),
713 RTL_FEATURE_MSI = (1 << 1),
714 RTL_FEATURE_GMII = (1 << 2),
715 };
716
717 struct rtl8169_counters {
718 __le64 tx_packets;
719 __le64 rx_packets;
720 __le64 tx_errors;
721 __le32 rx_errors;
722 __le16 rx_missed;
723 __le16 align_errors;
724 __le32 tx_one_collision;
725 __le32 tx_multi_collision;
726 __le64 rx_unicast;
727 __le64 rx_broadcast;
728 __le32 rx_multicast;
729 __le16 tx_aborted;
730 __le16 tx_underun;
731 };
732
733 enum rtl_flag {
734 RTL_FLAG_TASK_ENABLED,
735 RTL_FLAG_TASK_SLOW_PENDING,
736 RTL_FLAG_TASK_RESET_PENDING,
737 RTL_FLAG_TASK_PHY_PENDING,
738 RTL_FLAG_MAX
739 };
740
741 struct rtl8169_stats {
742 u64 packets;
743 u64 bytes;
744 struct u64_stats_sync syncp;
745 };
746
747 struct rtl8169_private {
748 void __iomem *mmio_addr; /* memory map physical address */
749 struct pci_dev *pci_dev;
750 struct net_device *dev;
751 struct napi_struct napi;
752 u32 msg_enable;
753 u16 txd_version;
754 u16 mac_version;
755 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
756 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
757 u32 dirty_tx;
758 struct rtl8169_stats rx_stats;
759 struct rtl8169_stats tx_stats;
760 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
761 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
762 dma_addr_t TxPhyAddr;
763 dma_addr_t RxPhyAddr;
764 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
765 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
766 struct timer_list timer;
767 u16 cp_cmd;
768
769 u16 event_slow;
770
771 struct mdio_ops {
772 void (*write)(struct rtl8169_private *, int, int);
773 int (*read)(struct rtl8169_private *, int);
774 } mdio_ops;
775
776 struct pll_power_ops {
777 void (*down)(struct rtl8169_private *);
778 void (*up)(struct rtl8169_private *);
779 } pll_power_ops;
780
781 struct jumbo_ops {
782 void (*enable)(struct rtl8169_private *);
783 void (*disable)(struct rtl8169_private *);
784 } jumbo_ops;
785
786 struct csi_ops {
787 void (*write)(struct rtl8169_private *, int, int);
788 u32 (*read)(struct rtl8169_private *, int);
789 } csi_ops;
790
791 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
792 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
793 void (*phy_reset_enable)(struct rtl8169_private *tp);
794 void (*hw_start)(struct net_device *);
795 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
796 unsigned int (*link_ok)(void __iomem *);
797 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
798 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
799
800 struct {
801 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
802 struct mutex mutex;
803 struct work_struct work;
804 } wk;
805
806 unsigned features;
807
808 struct mii_if_info mii;
809 struct rtl8169_counters counters;
810 u32 saved_wolopts;
811 u32 opts1_mask;
812
813 struct rtl_fw {
814 const struct firmware *fw;
815
816 #define RTL_VER_SIZE 32
817
818 char version[RTL_VER_SIZE];
819
820 struct rtl_fw_phy_action {
821 __le32 *code;
822 size_t size;
823 } phy_action;
824 } *rtl_fw;
825 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
826
827 u32 ocp_base;
828 };
829
830 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
831 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
832 module_param(use_dac, int, 0);
833 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
834 module_param_named(debug, debug.msg_enable, int, 0);
835 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
836 MODULE_LICENSE("GPL");
837 MODULE_VERSION(RTL8169_VERSION);
838 MODULE_FIRMWARE(FIRMWARE_8168D_1);
839 MODULE_FIRMWARE(FIRMWARE_8168D_2);
840 MODULE_FIRMWARE(FIRMWARE_8168E_1);
841 MODULE_FIRMWARE(FIRMWARE_8168E_2);
842 MODULE_FIRMWARE(FIRMWARE_8168E_3);
843 MODULE_FIRMWARE(FIRMWARE_8105E_1);
844 MODULE_FIRMWARE(FIRMWARE_8168F_1);
845 MODULE_FIRMWARE(FIRMWARE_8168F_2);
846 MODULE_FIRMWARE(FIRMWARE_8402_1);
847 MODULE_FIRMWARE(FIRMWARE_8411_1);
848 MODULE_FIRMWARE(FIRMWARE_8411_2);
849 MODULE_FIRMWARE(FIRMWARE_8106E_1);
850 MODULE_FIRMWARE(FIRMWARE_8106E_2);
851 MODULE_FIRMWARE(FIRMWARE_8168G_2);
852 MODULE_FIRMWARE(FIRMWARE_8168G_3);
853 MODULE_FIRMWARE(FIRMWARE_8168H_1);
854 MODULE_FIRMWARE(FIRMWARE_8168H_2);
855 MODULE_FIRMWARE(FIRMWARE_8107E_1);
856 MODULE_FIRMWARE(FIRMWARE_8107E_2);
857
858 static void rtl_lock_work(struct rtl8169_private *tp)
859 {
860 mutex_lock(&tp->wk.mutex);
861 }
862
863 static void rtl_unlock_work(struct rtl8169_private *tp)
864 {
865 mutex_unlock(&tp->wk.mutex);
866 }
867
868 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
869 {
870 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
871 PCI_EXP_DEVCTL_READRQ, force);
872 }
873
874 struct rtl_cond {
875 bool (*check)(struct rtl8169_private *);
876 const char *msg;
877 };
878
879 static void rtl_udelay(unsigned int d)
880 {
881 udelay(d);
882 }
883
884 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
885 void (*delay)(unsigned int), unsigned int d, int n,
886 bool high)
887 {
888 int i;
889
890 for (i = 0; i < n; i++) {
891 delay(d);
892 if (c->check(tp) == high)
893 return true;
894 }
895 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
896 c->msg, !high, n, d);
897 return false;
898 }
899
900 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
901 const struct rtl_cond *c,
902 unsigned int d, int n)
903 {
904 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
905 }
906
907 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
908 const struct rtl_cond *c,
909 unsigned int d, int n)
910 {
911 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
912 }
913
914 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
915 const struct rtl_cond *c,
916 unsigned int d, int n)
917 {
918 return rtl_loop_wait(tp, c, msleep, d, n, true);
919 }
920
921 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
922 const struct rtl_cond *c,
923 unsigned int d, int n)
924 {
925 return rtl_loop_wait(tp, c, msleep, d, n, false);
926 }
927
928 #define DECLARE_RTL_COND(name) \
929 static bool name ## _check(struct rtl8169_private *); \
930 \
931 static const struct rtl_cond name = { \
932 .check = name ## _check, \
933 .msg = #name \
934 }; \
935 \
936 static bool name ## _check(struct rtl8169_private *tp)
937
938 DECLARE_RTL_COND(rtl_ocpar_cond)
939 {
940 void __iomem *ioaddr = tp->mmio_addr;
941
942 return RTL_R32(OCPAR) & OCPAR_FLAG;
943 }
944
945 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
946 {
947 void __iomem *ioaddr = tp->mmio_addr;
948
949 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
950
951 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
952 RTL_R32(OCPDR) : ~0;
953 }
954
955 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
956 {
957 void __iomem *ioaddr = tp->mmio_addr;
958
959 RTL_W32(OCPDR, data);
960 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
961
962 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
963 }
964
965 DECLARE_RTL_COND(rtl_eriar_cond)
966 {
967 void __iomem *ioaddr = tp->mmio_addr;
968
969 return RTL_R32(ERIAR) & ERIAR_FLAG;
970 }
971
972 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
973 {
974 if (reg & 0xffff0001) {
975 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
976 return true;
977 }
978 return false;
979 }
980
981 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
982 {
983 void __iomem *ioaddr = tp->mmio_addr;
984
985 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
986 }
987
988 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
989 {
990 void __iomem *ioaddr = tp->mmio_addr;
991
992 if (rtl_ocp_reg_failure(tp, reg))
993 return;
994
995 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
996
997 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
998 }
999
1000 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1001 {
1002 void __iomem *ioaddr = tp->mmio_addr;
1003
1004 if (rtl_ocp_reg_failure(tp, reg))
1005 return 0;
1006
1007 RTL_W32(GPHY_OCP, reg << 15);
1008
1009 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1010 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1011 }
1012
1013 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1014 {
1015 void __iomem *ioaddr = tp->mmio_addr;
1016
1017 if (rtl_ocp_reg_failure(tp, reg))
1018 return;
1019
1020 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1021 }
1022
1023 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1024 {
1025 void __iomem *ioaddr = tp->mmio_addr;
1026
1027 if (rtl_ocp_reg_failure(tp, reg))
1028 return 0;
1029
1030 RTL_W32(OCPDR, reg << 15);
1031
1032 return RTL_R32(OCPDR);
1033 }
1034
1035 #define OCP_STD_PHY_BASE 0xa400
1036
1037 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1038 {
1039 if (reg == 0x1f) {
1040 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1041 return;
1042 }
1043
1044 if (tp->ocp_base != OCP_STD_PHY_BASE)
1045 reg -= 0x10;
1046
1047 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1048 }
1049
1050 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1051 {
1052 if (tp->ocp_base != OCP_STD_PHY_BASE)
1053 reg -= 0x10;
1054
1055 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1056 }
1057
1058 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1059 {
1060 if (reg == 0x1f) {
1061 tp->ocp_base = value << 4;
1062 return;
1063 }
1064
1065 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1066 }
1067
1068 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1069 {
1070 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1071 }
1072
1073 DECLARE_RTL_COND(rtl_phyar_cond)
1074 {
1075 void __iomem *ioaddr = tp->mmio_addr;
1076
1077 return RTL_R32(PHYAR) & 0x80000000;
1078 }
1079
1080 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1081 {
1082 void __iomem *ioaddr = tp->mmio_addr;
1083
1084 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1085
1086 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1087 /*
1088 * According to hardware specs a 20us delay is required after write
1089 * complete indication, but before sending next command.
1090 */
1091 udelay(20);
1092 }
1093
1094 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1095 {
1096 void __iomem *ioaddr = tp->mmio_addr;
1097 int value;
1098
1099 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1100
1101 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1102 RTL_R32(PHYAR) & 0xffff : ~0;
1103
1104 /*
1105 * According to hardware specs a 20us delay is required after read
1106 * complete indication, but before sending next command.
1107 */
1108 udelay(20);
1109
1110 return value;
1111 }
1112
1113 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1114 {
1115 void __iomem *ioaddr = tp->mmio_addr;
1116
1117 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1118 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1119 RTL_W32(EPHY_RXER_NUM, 0);
1120
1121 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1122 }
1123
1124 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1125 {
1126 r8168dp_1_mdio_access(tp, reg,
1127 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1128 }
1129
1130 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1131 {
1132 void __iomem *ioaddr = tp->mmio_addr;
1133
1134 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1135
1136 mdelay(1);
1137 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1138 RTL_W32(EPHY_RXER_NUM, 0);
1139
1140 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1141 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1142 }
1143
1144 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1145
1146 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1147 {
1148 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1149 }
1150
1151 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1152 {
1153 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1154 }
1155
1156 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1157 {
1158 void __iomem *ioaddr = tp->mmio_addr;
1159
1160 r8168dp_2_mdio_start(ioaddr);
1161
1162 r8169_mdio_write(tp, reg, value);
1163
1164 r8168dp_2_mdio_stop(ioaddr);
1165 }
1166
1167 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1168 {
1169 void __iomem *ioaddr = tp->mmio_addr;
1170 int value;
1171
1172 r8168dp_2_mdio_start(ioaddr);
1173
1174 value = r8169_mdio_read(tp, reg);
1175
1176 r8168dp_2_mdio_stop(ioaddr);
1177
1178 return value;
1179 }
1180
1181 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1182 {
1183 tp->mdio_ops.write(tp, location, val);
1184 }
1185
1186 static int rtl_readphy(struct rtl8169_private *tp, int location)
1187 {
1188 return tp->mdio_ops.read(tp, location);
1189 }
1190
1191 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1192 {
1193 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1194 }
1195
1196 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1197 {
1198 int val;
1199
1200 val = rtl_readphy(tp, reg_addr);
1201 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1202 }
1203
1204 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1205 int val)
1206 {
1207 struct rtl8169_private *tp = netdev_priv(dev);
1208
1209 rtl_writephy(tp, location, val);
1210 }
1211
1212 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1213 {
1214 struct rtl8169_private *tp = netdev_priv(dev);
1215
1216 return rtl_readphy(tp, location);
1217 }
1218
1219 DECLARE_RTL_COND(rtl_ephyar_cond)
1220 {
1221 void __iomem *ioaddr = tp->mmio_addr;
1222
1223 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1224 }
1225
1226 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1227 {
1228 void __iomem *ioaddr = tp->mmio_addr;
1229
1230 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1231 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1232
1233 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1234
1235 udelay(10);
1236 }
1237
1238 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1239 {
1240 void __iomem *ioaddr = tp->mmio_addr;
1241
1242 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1243
1244 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1245 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1246 }
1247
1248 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1249 u32 val, int type)
1250 {
1251 void __iomem *ioaddr = tp->mmio_addr;
1252
1253 BUG_ON((addr & 3) || (mask == 0));
1254 RTL_W32(ERIDR, val);
1255 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1256
1257 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1258 }
1259
1260 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1261 {
1262 void __iomem *ioaddr = tp->mmio_addr;
1263
1264 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1265
1266 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1267 RTL_R32(ERIDR) : ~0;
1268 }
1269
1270 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1271 u32 m, int type)
1272 {
1273 u32 val;
1274
1275 val = rtl_eri_read(tp, addr, type);
1276 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1277 }
1278
1279 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1280 {
1281 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1282
1283 ocp_write(tp, 0x1, 0x30, 0x00000001);
1284 }
1285
1286 #define OOB_CMD_RESET 0x00
1287 #define OOB_CMD_DRIVER_START 0x05
1288 #define OOB_CMD_DRIVER_STOP 0x06
1289
1290 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1291 {
1292 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1293 }
1294
1295 DECLARE_RTL_COND(rtl_ocp_read_cond)
1296 {
1297 u16 reg;
1298
1299 reg = rtl8168_get_ocp_reg(tp);
1300
1301 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1302 }
1303
1304 static void rtl8168_driver_start(struct rtl8169_private *tp)
1305 {
1306 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1307
1308 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1309 }
1310
1311 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1312 {
1313 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1314
1315 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1316 }
1317
1318 static int r8168_check_dash(struct rtl8169_private *tp)
1319 {
1320 u16 reg = rtl8168_get_ocp_reg(tp);
1321
1322 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1323 }
1324
1325 struct exgmac_reg {
1326 u16 addr;
1327 u16 mask;
1328 u32 val;
1329 };
1330
1331 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1332 const struct exgmac_reg *r, int len)
1333 {
1334 while (len-- > 0) {
1335 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1336 r++;
1337 }
1338 }
1339
1340 DECLARE_RTL_COND(rtl_efusear_cond)
1341 {
1342 void __iomem *ioaddr = tp->mmio_addr;
1343
1344 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1345 }
1346
1347 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1348 {
1349 void __iomem *ioaddr = tp->mmio_addr;
1350
1351 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1352
1353 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1354 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1355 }
1356
1357 static u16 rtl_get_events(struct rtl8169_private *tp)
1358 {
1359 void __iomem *ioaddr = tp->mmio_addr;
1360
1361 return RTL_R16(IntrStatus);
1362 }
1363
1364 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1365 {
1366 void __iomem *ioaddr = tp->mmio_addr;
1367
1368 RTL_W16(IntrStatus, bits);
1369 mmiowb();
1370 }
1371
1372 static void rtl_irq_disable(struct rtl8169_private *tp)
1373 {
1374 void __iomem *ioaddr = tp->mmio_addr;
1375
1376 RTL_W16(IntrMask, 0);
1377 mmiowb();
1378 }
1379
1380 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1381 {
1382 void __iomem *ioaddr = tp->mmio_addr;
1383
1384 RTL_W16(IntrMask, bits);
1385 }
1386
1387 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1388 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1389 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1390
1391 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1392 {
1393 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1394 }
1395
1396 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1397 {
1398 void __iomem *ioaddr = tp->mmio_addr;
1399
1400 rtl_irq_disable(tp);
1401 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1402 RTL_R8(ChipCmd);
1403 }
1404
1405 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1406 {
1407 void __iomem *ioaddr = tp->mmio_addr;
1408
1409 return RTL_R32(TBICSR) & TBIReset;
1410 }
1411
1412 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1413 {
1414 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1415 }
1416
1417 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1418 {
1419 return RTL_R32(TBICSR) & TBILinkOk;
1420 }
1421
1422 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1423 {
1424 return RTL_R8(PHYstatus) & LinkStatus;
1425 }
1426
1427 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1428 {
1429 void __iomem *ioaddr = tp->mmio_addr;
1430
1431 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1432 }
1433
1434 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1435 {
1436 unsigned int val;
1437
1438 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1439 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1440 }
1441
1442 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1443 {
1444 void __iomem *ioaddr = tp->mmio_addr;
1445 struct net_device *dev = tp->dev;
1446
1447 if (!netif_running(dev))
1448 return;
1449
1450 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1451 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1452 if (RTL_R8(PHYstatus) & _1000bpsF) {
1453 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1454 ERIAR_EXGMAC);
1455 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1456 ERIAR_EXGMAC);
1457 } else if (RTL_R8(PHYstatus) & _100bps) {
1458 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1459 ERIAR_EXGMAC);
1460 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1461 ERIAR_EXGMAC);
1462 } else {
1463 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1464 ERIAR_EXGMAC);
1465 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1466 ERIAR_EXGMAC);
1467 }
1468 /* Reset packet filter */
1469 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1470 ERIAR_EXGMAC);
1471 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1472 ERIAR_EXGMAC);
1473 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1474 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1475 if (RTL_R8(PHYstatus) & _1000bpsF) {
1476 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1477 ERIAR_EXGMAC);
1478 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1479 ERIAR_EXGMAC);
1480 } else {
1481 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1482 ERIAR_EXGMAC);
1483 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1484 ERIAR_EXGMAC);
1485 }
1486 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1487 if (RTL_R8(PHYstatus) & _10bps) {
1488 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1489 ERIAR_EXGMAC);
1490 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1491 ERIAR_EXGMAC);
1492 } else {
1493 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1494 ERIAR_EXGMAC);
1495 }
1496 }
1497 }
1498
1499 static void __rtl8169_check_link_status(struct net_device *dev,
1500 struct rtl8169_private *tp,
1501 void __iomem *ioaddr, bool pm)
1502 {
1503 if (tp->link_ok(ioaddr)) {
1504 rtl_link_chg_patch(tp);
1505 /* This is to cancel a scheduled suspend if there's one. */
1506 if (pm)
1507 pm_request_resume(&tp->pci_dev->dev);
1508 netif_carrier_on(dev);
1509 if (net_ratelimit())
1510 netif_info(tp, ifup, dev, "link up\n");
1511 } else {
1512 netif_carrier_off(dev);
1513 netif_info(tp, ifdown, dev, "link down\n");
1514 if (pm)
1515 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1516 }
1517 }
1518
1519 static void rtl8169_check_link_status(struct net_device *dev,
1520 struct rtl8169_private *tp,
1521 void __iomem *ioaddr)
1522 {
1523 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1524 }
1525
1526 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1527
1528 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1529 {
1530 void __iomem *ioaddr = tp->mmio_addr;
1531 u8 options;
1532 u32 wolopts = 0;
1533
1534 options = RTL_R8(Config1);
1535 if (!(options & PMEnable))
1536 return 0;
1537
1538 options = RTL_R8(Config3);
1539 if (options & LinkUp)
1540 wolopts |= WAKE_PHY;
1541 switch (tp->mac_version) {
1542 case RTL_GIGA_MAC_VER_34:
1543 case RTL_GIGA_MAC_VER_35:
1544 case RTL_GIGA_MAC_VER_36:
1545 case RTL_GIGA_MAC_VER_37:
1546 case RTL_GIGA_MAC_VER_38:
1547 case RTL_GIGA_MAC_VER_40:
1548 case RTL_GIGA_MAC_VER_41:
1549 case RTL_GIGA_MAC_VER_42:
1550 case RTL_GIGA_MAC_VER_43:
1551 case RTL_GIGA_MAC_VER_44:
1552 case RTL_GIGA_MAC_VER_45:
1553 case RTL_GIGA_MAC_VER_46:
1554 case RTL_GIGA_MAC_VER_47:
1555 case RTL_GIGA_MAC_VER_48:
1556 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1557 wolopts |= WAKE_MAGIC;
1558 break;
1559 default:
1560 if (options & MagicPacket)
1561 wolopts |= WAKE_MAGIC;
1562 break;
1563 }
1564
1565 options = RTL_R8(Config5);
1566 if (options & UWF)
1567 wolopts |= WAKE_UCAST;
1568 if (options & BWF)
1569 wolopts |= WAKE_BCAST;
1570 if (options & MWF)
1571 wolopts |= WAKE_MCAST;
1572
1573 return wolopts;
1574 }
1575
1576 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1577 {
1578 struct rtl8169_private *tp = netdev_priv(dev);
1579
1580 rtl_lock_work(tp);
1581
1582 wol->supported = WAKE_ANY;
1583 wol->wolopts = __rtl8169_get_wol(tp);
1584
1585 rtl_unlock_work(tp);
1586 }
1587
1588 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1589 {
1590 void __iomem *ioaddr = tp->mmio_addr;
1591 unsigned int i, tmp;
1592 static const struct {
1593 u32 opt;
1594 u16 reg;
1595 u8 mask;
1596 } cfg[] = {
1597 { WAKE_PHY, Config3, LinkUp },
1598 { WAKE_UCAST, Config5, UWF },
1599 { WAKE_BCAST, Config5, BWF },
1600 { WAKE_MCAST, Config5, MWF },
1601 { WAKE_ANY, Config5, LanWake },
1602 { WAKE_MAGIC, Config3, MagicPacket }
1603 };
1604 u8 options;
1605
1606 RTL_W8(Cfg9346, Cfg9346_Unlock);
1607
1608 switch (tp->mac_version) {
1609 case RTL_GIGA_MAC_VER_34:
1610 case RTL_GIGA_MAC_VER_35:
1611 case RTL_GIGA_MAC_VER_36:
1612 case RTL_GIGA_MAC_VER_37:
1613 case RTL_GIGA_MAC_VER_38:
1614 case RTL_GIGA_MAC_VER_40:
1615 case RTL_GIGA_MAC_VER_41:
1616 case RTL_GIGA_MAC_VER_42:
1617 case RTL_GIGA_MAC_VER_43:
1618 case RTL_GIGA_MAC_VER_44:
1619 case RTL_GIGA_MAC_VER_45:
1620 case RTL_GIGA_MAC_VER_46:
1621 case RTL_GIGA_MAC_VER_47:
1622 case RTL_GIGA_MAC_VER_48:
1623 tmp = ARRAY_SIZE(cfg) - 1;
1624 if (wolopts & WAKE_MAGIC)
1625 rtl_w0w1_eri(tp,
1626 0x0dc,
1627 ERIAR_MASK_0100,
1628 MagicPacket_v2,
1629 0x0000,
1630 ERIAR_EXGMAC);
1631 else
1632 rtl_w0w1_eri(tp,
1633 0x0dc,
1634 ERIAR_MASK_0100,
1635 0x0000,
1636 MagicPacket_v2,
1637 ERIAR_EXGMAC);
1638 break;
1639 default:
1640 tmp = ARRAY_SIZE(cfg);
1641 break;
1642 }
1643
1644 for (i = 0; i < tmp; i++) {
1645 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1646 if (wolopts & cfg[i].opt)
1647 options |= cfg[i].mask;
1648 RTL_W8(cfg[i].reg, options);
1649 }
1650
1651 switch (tp->mac_version) {
1652 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1653 options = RTL_R8(Config1) & ~PMEnable;
1654 if (wolopts)
1655 options |= PMEnable;
1656 RTL_W8(Config1, options);
1657 break;
1658 default:
1659 options = RTL_R8(Config2) & ~PME_SIGNAL;
1660 if (wolopts)
1661 options |= PME_SIGNAL;
1662 RTL_W8(Config2, options);
1663 break;
1664 }
1665
1666 RTL_W8(Cfg9346, Cfg9346_Lock);
1667 }
1668
1669 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1670 {
1671 struct rtl8169_private *tp = netdev_priv(dev);
1672
1673 rtl_lock_work(tp);
1674
1675 if (wol->wolopts)
1676 tp->features |= RTL_FEATURE_WOL;
1677 else
1678 tp->features &= ~RTL_FEATURE_WOL;
1679 __rtl8169_set_wol(tp, wol->wolopts);
1680
1681 rtl_unlock_work(tp);
1682
1683 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1684
1685 return 0;
1686 }
1687
1688 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1689 {
1690 return rtl_chip_infos[tp->mac_version].fw_name;
1691 }
1692
1693 static void rtl8169_get_drvinfo(struct net_device *dev,
1694 struct ethtool_drvinfo *info)
1695 {
1696 struct rtl8169_private *tp = netdev_priv(dev);
1697 struct rtl_fw *rtl_fw = tp->rtl_fw;
1698
1699 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1700 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1701 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1702 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1703 if (!IS_ERR_OR_NULL(rtl_fw))
1704 strlcpy(info->fw_version, rtl_fw->version,
1705 sizeof(info->fw_version));
1706 }
1707
1708 static int rtl8169_get_regs_len(struct net_device *dev)
1709 {
1710 return R8169_REGS_SIZE;
1711 }
1712
1713 static int rtl8169_set_speed_tbi(struct net_device *dev,
1714 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1715 {
1716 struct rtl8169_private *tp = netdev_priv(dev);
1717 void __iomem *ioaddr = tp->mmio_addr;
1718 int ret = 0;
1719 u32 reg;
1720
1721 reg = RTL_R32(TBICSR);
1722 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1723 (duplex == DUPLEX_FULL)) {
1724 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1725 } else if (autoneg == AUTONEG_ENABLE)
1726 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1727 else {
1728 netif_warn(tp, link, dev,
1729 "incorrect speed setting refused in TBI mode\n");
1730 ret = -EOPNOTSUPP;
1731 }
1732
1733 return ret;
1734 }
1735
1736 static int rtl8169_set_speed_xmii(struct net_device *dev,
1737 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1738 {
1739 struct rtl8169_private *tp = netdev_priv(dev);
1740 int giga_ctrl, bmcr;
1741 int rc = -EINVAL;
1742
1743 rtl_writephy(tp, 0x1f, 0x0000);
1744
1745 if (autoneg == AUTONEG_ENABLE) {
1746 int auto_nego;
1747
1748 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1749 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1750 ADVERTISE_100HALF | ADVERTISE_100FULL);
1751
1752 if (adv & ADVERTISED_10baseT_Half)
1753 auto_nego |= ADVERTISE_10HALF;
1754 if (adv & ADVERTISED_10baseT_Full)
1755 auto_nego |= ADVERTISE_10FULL;
1756 if (adv & ADVERTISED_100baseT_Half)
1757 auto_nego |= ADVERTISE_100HALF;
1758 if (adv & ADVERTISED_100baseT_Full)
1759 auto_nego |= ADVERTISE_100FULL;
1760
1761 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1762
1763 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1764 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1765
1766 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1767 if (tp->mii.supports_gmii) {
1768 if (adv & ADVERTISED_1000baseT_Half)
1769 giga_ctrl |= ADVERTISE_1000HALF;
1770 if (adv & ADVERTISED_1000baseT_Full)
1771 giga_ctrl |= ADVERTISE_1000FULL;
1772 } else if (adv & (ADVERTISED_1000baseT_Half |
1773 ADVERTISED_1000baseT_Full)) {
1774 netif_info(tp, link, dev,
1775 "PHY does not support 1000Mbps\n");
1776 goto out;
1777 }
1778
1779 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1780
1781 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1782 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1783 } else {
1784 giga_ctrl = 0;
1785
1786 if (speed == SPEED_10)
1787 bmcr = 0;
1788 else if (speed == SPEED_100)
1789 bmcr = BMCR_SPEED100;
1790 else
1791 goto out;
1792
1793 if (duplex == DUPLEX_FULL)
1794 bmcr |= BMCR_FULLDPLX;
1795 }
1796
1797 rtl_writephy(tp, MII_BMCR, bmcr);
1798
1799 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1800 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1801 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1802 rtl_writephy(tp, 0x17, 0x2138);
1803 rtl_writephy(tp, 0x0e, 0x0260);
1804 } else {
1805 rtl_writephy(tp, 0x17, 0x2108);
1806 rtl_writephy(tp, 0x0e, 0x0000);
1807 }
1808 }
1809
1810 rc = 0;
1811 out:
1812 return rc;
1813 }
1814
1815 static int rtl8169_set_speed(struct net_device *dev,
1816 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1817 {
1818 struct rtl8169_private *tp = netdev_priv(dev);
1819 int ret;
1820
1821 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1822 if (ret < 0)
1823 goto out;
1824
1825 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1826 (advertising & ADVERTISED_1000baseT_Full)) {
1827 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1828 }
1829 out:
1830 return ret;
1831 }
1832
1833 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1834 {
1835 struct rtl8169_private *tp = netdev_priv(dev);
1836 int ret;
1837
1838 del_timer_sync(&tp->timer);
1839
1840 rtl_lock_work(tp);
1841 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1842 cmd->duplex, cmd->advertising);
1843 rtl_unlock_work(tp);
1844
1845 return ret;
1846 }
1847
1848 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1849 netdev_features_t features)
1850 {
1851 struct rtl8169_private *tp = netdev_priv(dev);
1852
1853 if (dev->mtu > TD_MSS_MAX)
1854 features &= ~NETIF_F_ALL_TSO;
1855
1856 if (dev->mtu > JUMBO_1K &&
1857 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1858 features &= ~NETIF_F_IP_CSUM;
1859
1860 return features;
1861 }
1862
1863 static void __rtl8169_set_features(struct net_device *dev,
1864 netdev_features_t features)
1865 {
1866 struct rtl8169_private *tp = netdev_priv(dev);
1867 void __iomem *ioaddr = tp->mmio_addr;
1868 u32 rx_config;
1869
1870 rx_config = RTL_R32(RxConfig);
1871 if (features & NETIF_F_RXALL)
1872 rx_config |= (AcceptErr | AcceptRunt);
1873 else
1874 rx_config &= ~(AcceptErr | AcceptRunt);
1875
1876 RTL_W32(RxConfig, rx_config);
1877
1878 if (features & NETIF_F_RXCSUM)
1879 tp->cp_cmd |= RxChkSum;
1880 else
1881 tp->cp_cmd &= ~RxChkSum;
1882
1883 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1884 tp->cp_cmd |= RxVlan;
1885 else
1886 tp->cp_cmd &= ~RxVlan;
1887
1888 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
1889
1890 RTL_W16(CPlusCmd, tp->cp_cmd);
1891 RTL_R16(CPlusCmd);
1892 }
1893
1894 static int rtl8169_set_features(struct net_device *dev,
1895 netdev_features_t features)
1896 {
1897 struct rtl8169_private *tp = netdev_priv(dev);
1898
1899 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
1900
1901 rtl_lock_work(tp);
1902 if (features ^ dev->features)
1903 __rtl8169_set_features(dev, features);
1904 rtl_unlock_work(tp);
1905
1906 return 0;
1907 }
1908
1909
1910 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1911 {
1912 return (vlan_tx_tag_present(skb)) ?
1913 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1914 }
1915
1916 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1917 {
1918 u32 opts2 = le32_to_cpu(desc->opts2);
1919
1920 if (opts2 & RxVlanTag)
1921 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1922 }
1923
1924 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1925 {
1926 struct rtl8169_private *tp = netdev_priv(dev);
1927 void __iomem *ioaddr = tp->mmio_addr;
1928 u32 status;
1929
1930 cmd->supported =
1931 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1932 cmd->port = PORT_FIBRE;
1933 cmd->transceiver = XCVR_INTERNAL;
1934
1935 status = RTL_R32(TBICSR);
1936 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1937 cmd->autoneg = !!(status & TBINwEnable);
1938
1939 ethtool_cmd_speed_set(cmd, SPEED_1000);
1940 cmd->duplex = DUPLEX_FULL; /* Always set */
1941
1942 return 0;
1943 }
1944
1945 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1946 {
1947 struct rtl8169_private *tp = netdev_priv(dev);
1948
1949 return mii_ethtool_gset(&tp->mii, cmd);
1950 }
1951
1952 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1953 {
1954 struct rtl8169_private *tp = netdev_priv(dev);
1955 int rc;
1956
1957 rtl_lock_work(tp);
1958 rc = tp->get_settings(dev, cmd);
1959 rtl_unlock_work(tp);
1960
1961 return rc;
1962 }
1963
1964 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1965 void *p)
1966 {
1967 struct rtl8169_private *tp = netdev_priv(dev);
1968 u32 __iomem *data = tp->mmio_addr;
1969 u32 *dw = p;
1970 int i;
1971
1972 rtl_lock_work(tp);
1973 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1974 memcpy_fromio(dw++, data++, 4);
1975 rtl_unlock_work(tp);
1976 }
1977
1978 static u32 rtl8169_get_msglevel(struct net_device *dev)
1979 {
1980 struct rtl8169_private *tp = netdev_priv(dev);
1981
1982 return tp->msg_enable;
1983 }
1984
1985 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1986 {
1987 struct rtl8169_private *tp = netdev_priv(dev);
1988
1989 tp->msg_enable = value;
1990 }
1991
1992 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1993 "tx_packets",
1994 "rx_packets",
1995 "tx_errors",
1996 "rx_errors",
1997 "rx_missed",
1998 "align_errors",
1999 "tx_single_collisions",
2000 "tx_multi_collisions",
2001 "unicast",
2002 "broadcast",
2003 "multicast",
2004 "tx_aborted",
2005 "tx_underrun",
2006 };
2007
2008 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2009 {
2010 switch (sset) {
2011 case ETH_SS_STATS:
2012 return ARRAY_SIZE(rtl8169_gstrings);
2013 default:
2014 return -EOPNOTSUPP;
2015 }
2016 }
2017
2018 DECLARE_RTL_COND(rtl_counters_cond)
2019 {
2020 void __iomem *ioaddr = tp->mmio_addr;
2021
2022 return RTL_R32(CounterAddrLow) & CounterDump;
2023 }
2024
2025 static void rtl8169_update_counters(struct net_device *dev)
2026 {
2027 struct rtl8169_private *tp = netdev_priv(dev);
2028 void __iomem *ioaddr = tp->mmio_addr;
2029 struct device *d = &tp->pci_dev->dev;
2030 struct rtl8169_counters *counters;
2031 dma_addr_t paddr;
2032 u32 cmd;
2033
2034 /*
2035 * Some chips are unable to dump tally counters when the receiver
2036 * is disabled.
2037 */
2038 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2039 return;
2040
2041 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
2042 if (!counters)
2043 return;
2044
2045 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2046 cmd = (u64)paddr & DMA_BIT_MASK(32);
2047 RTL_W32(CounterAddrLow, cmd);
2048 RTL_W32(CounterAddrLow, cmd | CounterDump);
2049
2050 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2051 memcpy(&tp->counters, counters, sizeof(*counters));
2052
2053 RTL_W32(CounterAddrLow, 0);
2054 RTL_W32(CounterAddrHigh, 0);
2055
2056 dma_free_coherent(d, sizeof(*counters), counters, paddr);
2057 }
2058
2059 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2060 struct ethtool_stats *stats, u64 *data)
2061 {
2062 struct rtl8169_private *tp = netdev_priv(dev);
2063
2064 ASSERT_RTNL();
2065
2066 rtl8169_update_counters(dev);
2067
2068 data[0] = le64_to_cpu(tp->counters.tx_packets);
2069 data[1] = le64_to_cpu(tp->counters.rx_packets);
2070 data[2] = le64_to_cpu(tp->counters.tx_errors);
2071 data[3] = le32_to_cpu(tp->counters.rx_errors);
2072 data[4] = le16_to_cpu(tp->counters.rx_missed);
2073 data[5] = le16_to_cpu(tp->counters.align_errors);
2074 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2075 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2076 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2077 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2078 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2079 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2080 data[12] = le16_to_cpu(tp->counters.tx_underun);
2081 }
2082
2083 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2084 {
2085 switch(stringset) {
2086 case ETH_SS_STATS:
2087 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2088 break;
2089 }
2090 }
2091
2092 static const struct ethtool_ops rtl8169_ethtool_ops = {
2093 .get_drvinfo = rtl8169_get_drvinfo,
2094 .get_regs_len = rtl8169_get_regs_len,
2095 .get_link = ethtool_op_get_link,
2096 .get_settings = rtl8169_get_settings,
2097 .set_settings = rtl8169_set_settings,
2098 .get_msglevel = rtl8169_get_msglevel,
2099 .set_msglevel = rtl8169_set_msglevel,
2100 .get_regs = rtl8169_get_regs,
2101 .get_wol = rtl8169_get_wol,
2102 .set_wol = rtl8169_set_wol,
2103 .get_strings = rtl8169_get_strings,
2104 .get_sset_count = rtl8169_get_sset_count,
2105 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2106 .get_ts_info = ethtool_op_get_ts_info,
2107 };
2108
2109 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2110 struct net_device *dev, u8 default_version)
2111 {
2112 void __iomem *ioaddr = tp->mmio_addr;
2113 /*
2114 * The driver currently handles the 8168Bf and the 8168Be identically
2115 * but they can be identified more specifically through the test below
2116 * if needed:
2117 *
2118 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2119 *
2120 * Same thing for the 8101Eb and the 8101Ec:
2121 *
2122 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2123 */
2124 static const struct rtl_mac_info {
2125 u32 mask;
2126 u32 val;
2127 int mac_version;
2128 } mac_info[] = {
2129 /* 8168H family. */
2130 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2131 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2132
2133 /* 8168G family. */
2134 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2135 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2136 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2137 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2138
2139 /* 8168F family. */
2140 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2141 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2142 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2143
2144 /* 8168E family. */
2145 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2146 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2147 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2148 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2149
2150 /* 8168D family. */
2151 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2152 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2153 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2154
2155 /* 8168DP family. */
2156 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2157 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2158 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2159
2160 /* 8168C family. */
2161 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2162 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2163 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2164 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2165 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2166 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2167 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2168 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2169 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2170
2171 /* 8168B family. */
2172 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2173 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2174 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2175 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2176
2177 /* 8101 family. */
2178 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2179 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2180 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2181 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2182 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2183 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2184 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2185 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2186 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2187 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2188 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2189 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2190 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2191 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2192 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2193 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2194 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2195 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2196 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2197 /* FIXME: where did these entries come from ? -- FR */
2198 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2199 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2200
2201 /* 8110 family. */
2202 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2203 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2204 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2205 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2206 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2207 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2208
2209 /* Catch-all */
2210 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2211 };
2212 const struct rtl_mac_info *p = mac_info;
2213 u32 reg;
2214
2215 reg = RTL_R32(TxConfig);
2216 while ((reg & p->mask) != p->val)
2217 p++;
2218 tp->mac_version = p->mac_version;
2219
2220 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2221 netif_notice(tp, probe, dev,
2222 "unknown MAC, using family default\n");
2223 tp->mac_version = default_version;
2224 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2225 tp->mac_version = tp->mii.supports_gmii ?
2226 RTL_GIGA_MAC_VER_42 :
2227 RTL_GIGA_MAC_VER_43;
2228 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2229 tp->mac_version = tp->mii.supports_gmii ?
2230 RTL_GIGA_MAC_VER_45 :
2231 RTL_GIGA_MAC_VER_47;
2232 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2233 tp->mac_version = tp->mii.supports_gmii ?
2234 RTL_GIGA_MAC_VER_46 :
2235 RTL_GIGA_MAC_VER_48;
2236 }
2237 }
2238
2239 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2240 {
2241 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2242 }
2243
2244 struct phy_reg {
2245 u16 reg;
2246 u16 val;
2247 };
2248
2249 static void rtl_writephy_batch(struct rtl8169_private *tp,
2250 const struct phy_reg *regs, int len)
2251 {
2252 while (len-- > 0) {
2253 rtl_writephy(tp, regs->reg, regs->val);
2254 regs++;
2255 }
2256 }
2257
2258 #define PHY_READ 0x00000000
2259 #define PHY_DATA_OR 0x10000000
2260 #define PHY_DATA_AND 0x20000000
2261 #define PHY_BJMPN 0x30000000
2262 #define PHY_MDIO_CHG 0x40000000
2263 #define PHY_CLEAR_READCOUNT 0x70000000
2264 #define PHY_WRITE 0x80000000
2265 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2266 #define PHY_COMP_EQ_SKIPN 0xa0000000
2267 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2268 #define PHY_WRITE_PREVIOUS 0xc0000000
2269 #define PHY_SKIPN 0xd0000000
2270 #define PHY_DELAY_MS 0xe0000000
2271
2272 struct fw_info {
2273 u32 magic;
2274 char version[RTL_VER_SIZE];
2275 __le32 fw_start;
2276 __le32 fw_len;
2277 u8 chksum;
2278 } __packed;
2279
2280 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2281
2282 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2283 {
2284 const struct firmware *fw = rtl_fw->fw;
2285 struct fw_info *fw_info = (struct fw_info *)fw->data;
2286 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2287 char *version = rtl_fw->version;
2288 bool rc = false;
2289
2290 if (fw->size < FW_OPCODE_SIZE)
2291 goto out;
2292
2293 if (!fw_info->magic) {
2294 size_t i, size, start;
2295 u8 checksum = 0;
2296
2297 if (fw->size < sizeof(*fw_info))
2298 goto out;
2299
2300 for (i = 0; i < fw->size; i++)
2301 checksum += fw->data[i];
2302 if (checksum != 0)
2303 goto out;
2304
2305 start = le32_to_cpu(fw_info->fw_start);
2306 if (start > fw->size)
2307 goto out;
2308
2309 size = le32_to_cpu(fw_info->fw_len);
2310 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2311 goto out;
2312
2313 memcpy(version, fw_info->version, RTL_VER_SIZE);
2314
2315 pa->code = (__le32 *)(fw->data + start);
2316 pa->size = size;
2317 } else {
2318 if (fw->size % FW_OPCODE_SIZE)
2319 goto out;
2320
2321 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2322
2323 pa->code = (__le32 *)fw->data;
2324 pa->size = fw->size / FW_OPCODE_SIZE;
2325 }
2326 version[RTL_VER_SIZE - 1] = 0;
2327
2328 rc = true;
2329 out:
2330 return rc;
2331 }
2332
2333 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2334 struct rtl_fw_phy_action *pa)
2335 {
2336 bool rc = false;
2337 size_t index;
2338
2339 for (index = 0; index < pa->size; index++) {
2340 u32 action = le32_to_cpu(pa->code[index]);
2341 u32 regno = (action & 0x0fff0000) >> 16;
2342
2343 switch(action & 0xf0000000) {
2344 case PHY_READ:
2345 case PHY_DATA_OR:
2346 case PHY_DATA_AND:
2347 case PHY_MDIO_CHG:
2348 case PHY_CLEAR_READCOUNT:
2349 case PHY_WRITE:
2350 case PHY_WRITE_PREVIOUS:
2351 case PHY_DELAY_MS:
2352 break;
2353
2354 case PHY_BJMPN:
2355 if (regno > index) {
2356 netif_err(tp, ifup, tp->dev,
2357 "Out of range of firmware\n");
2358 goto out;
2359 }
2360 break;
2361 case PHY_READCOUNT_EQ_SKIP:
2362 if (index + 2 >= pa->size) {
2363 netif_err(tp, ifup, tp->dev,
2364 "Out of range of firmware\n");
2365 goto out;
2366 }
2367 break;
2368 case PHY_COMP_EQ_SKIPN:
2369 case PHY_COMP_NEQ_SKIPN:
2370 case PHY_SKIPN:
2371 if (index + 1 + regno >= pa->size) {
2372 netif_err(tp, ifup, tp->dev,
2373 "Out of range of firmware\n");
2374 goto out;
2375 }
2376 break;
2377
2378 default:
2379 netif_err(tp, ifup, tp->dev,
2380 "Invalid action 0x%08x\n", action);
2381 goto out;
2382 }
2383 }
2384 rc = true;
2385 out:
2386 return rc;
2387 }
2388
2389 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2390 {
2391 struct net_device *dev = tp->dev;
2392 int rc = -EINVAL;
2393
2394 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2395 netif_err(tp, ifup, dev, "invalid firwmare\n");
2396 goto out;
2397 }
2398
2399 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2400 rc = 0;
2401 out:
2402 return rc;
2403 }
2404
2405 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2406 {
2407 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2408 struct mdio_ops org, *ops = &tp->mdio_ops;
2409 u32 predata, count;
2410 size_t index;
2411
2412 predata = count = 0;
2413 org.write = ops->write;
2414 org.read = ops->read;
2415
2416 for (index = 0; index < pa->size; ) {
2417 u32 action = le32_to_cpu(pa->code[index]);
2418 u32 data = action & 0x0000ffff;
2419 u32 regno = (action & 0x0fff0000) >> 16;
2420
2421 if (!action)
2422 break;
2423
2424 switch(action & 0xf0000000) {
2425 case PHY_READ:
2426 predata = rtl_readphy(tp, regno);
2427 count++;
2428 index++;
2429 break;
2430 case PHY_DATA_OR:
2431 predata |= data;
2432 index++;
2433 break;
2434 case PHY_DATA_AND:
2435 predata &= data;
2436 index++;
2437 break;
2438 case PHY_BJMPN:
2439 index -= regno;
2440 break;
2441 case PHY_MDIO_CHG:
2442 if (data == 0) {
2443 ops->write = org.write;
2444 ops->read = org.read;
2445 } else if (data == 1) {
2446 ops->write = mac_mcu_write;
2447 ops->read = mac_mcu_read;
2448 }
2449
2450 index++;
2451 break;
2452 case PHY_CLEAR_READCOUNT:
2453 count = 0;
2454 index++;
2455 break;
2456 case PHY_WRITE:
2457 rtl_writephy(tp, regno, data);
2458 index++;
2459 break;
2460 case PHY_READCOUNT_EQ_SKIP:
2461 index += (count == data) ? 2 : 1;
2462 break;
2463 case PHY_COMP_EQ_SKIPN:
2464 if (predata == data)
2465 index += regno;
2466 index++;
2467 break;
2468 case PHY_COMP_NEQ_SKIPN:
2469 if (predata != data)
2470 index += regno;
2471 index++;
2472 break;
2473 case PHY_WRITE_PREVIOUS:
2474 rtl_writephy(tp, regno, predata);
2475 index++;
2476 break;
2477 case PHY_SKIPN:
2478 index += regno + 1;
2479 break;
2480 case PHY_DELAY_MS:
2481 mdelay(data);
2482 index++;
2483 break;
2484
2485 default:
2486 BUG();
2487 }
2488 }
2489
2490 ops->write = org.write;
2491 ops->read = org.read;
2492 }
2493
2494 static void rtl_release_firmware(struct rtl8169_private *tp)
2495 {
2496 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2497 release_firmware(tp->rtl_fw->fw);
2498 kfree(tp->rtl_fw);
2499 }
2500 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2501 }
2502
2503 static void rtl_apply_firmware(struct rtl8169_private *tp)
2504 {
2505 struct rtl_fw *rtl_fw = tp->rtl_fw;
2506
2507 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2508 if (!IS_ERR_OR_NULL(rtl_fw))
2509 rtl_phy_write_fw(tp, rtl_fw);
2510 }
2511
2512 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2513 {
2514 if (rtl_readphy(tp, reg) != val)
2515 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2516 else
2517 rtl_apply_firmware(tp);
2518 }
2519
2520 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2521 {
2522 static const struct phy_reg phy_reg_init[] = {
2523 { 0x1f, 0x0001 },
2524 { 0x06, 0x006e },
2525 { 0x08, 0x0708 },
2526 { 0x15, 0x4000 },
2527 { 0x18, 0x65c7 },
2528
2529 { 0x1f, 0x0001 },
2530 { 0x03, 0x00a1 },
2531 { 0x02, 0x0008 },
2532 { 0x01, 0x0120 },
2533 { 0x00, 0x1000 },
2534 { 0x04, 0x0800 },
2535 { 0x04, 0x0000 },
2536
2537 { 0x03, 0xff41 },
2538 { 0x02, 0xdf60 },
2539 { 0x01, 0x0140 },
2540 { 0x00, 0x0077 },
2541 { 0x04, 0x7800 },
2542 { 0x04, 0x7000 },
2543
2544 { 0x03, 0x802f },
2545 { 0x02, 0x4f02 },
2546 { 0x01, 0x0409 },
2547 { 0x00, 0xf0f9 },
2548 { 0x04, 0x9800 },
2549 { 0x04, 0x9000 },
2550
2551 { 0x03, 0xdf01 },
2552 { 0x02, 0xdf20 },
2553 { 0x01, 0xff95 },
2554 { 0x00, 0xba00 },
2555 { 0x04, 0xa800 },
2556 { 0x04, 0xa000 },
2557
2558 { 0x03, 0xff41 },
2559 { 0x02, 0xdf20 },
2560 { 0x01, 0x0140 },
2561 { 0x00, 0x00bb },
2562 { 0x04, 0xb800 },
2563 { 0x04, 0xb000 },
2564
2565 { 0x03, 0xdf41 },
2566 { 0x02, 0xdc60 },
2567 { 0x01, 0x6340 },
2568 { 0x00, 0x007d },
2569 { 0x04, 0xd800 },
2570 { 0x04, 0xd000 },
2571
2572 { 0x03, 0xdf01 },
2573 { 0x02, 0xdf20 },
2574 { 0x01, 0x100a },
2575 { 0x00, 0xa0ff },
2576 { 0x04, 0xf800 },
2577 { 0x04, 0xf000 },
2578
2579 { 0x1f, 0x0000 },
2580 { 0x0b, 0x0000 },
2581 { 0x00, 0x9200 }
2582 };
2583
2584 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2585 }
2586
2587 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2588 {
2589 static const struct phy_reg phy_reg_init[] = {
2590 { 0x1f, 0x0002 },
2591 { 0x01, 0x90d0 },
2592 { 0x1f, 0x0000 }
2593 };
2594
2595 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2596 }
2597
2598 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2599 {
2600 struct pci_dev *pdev = tp->pci_dev;
2601
2602 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2603 (pdev->subsystem_device != 0xe000))
2604 return;
2605
2606 rtl_writephy(tp, 0x1f, 0x0001);
2607 rtl_writephy(tp, 0x10, 0xf01b);
2608 rtl_writephy(tp, 0x1f, 0x0000);
2609 }
2610
2611 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2612 {
2613 static const struct phy_reg phy_reg_init[] = {
2614 { 0x1f, 0x0001 },
2615 { 0x04, 0x0000 },
2616 { 0x03, 0x00a1 },
2617 { 0x02, 0x0008 },
2618 { 0x01, 0x0120 },
2619 { 0x00, 0x1000 },
2620 { 0x04, 0x0800 },
2621 { 0x04, 0x9000 },
2622 { 0x03, 0x802f },
2623 { 0x02, 0x4f02 },
2624 { 0x01, 0x0409 },
2625 { 0x00, 0xf099 },
2626 { 0x04, 0x9800 },
2627 { 0x04, 0xa000 },
2628 { 0x03, 0xdf01 },
2629 { 0x02, 0xdf20 },
2630 { 0x01, 0xff95 },
2631 { 0x00, 0xba00 },
2632 { 0x04, 0xa800 },
2633 { 0x04, 0xf000 },
2634 { 0x03, 0xdf01 },
2635 { 0x02, 0xdf20 },
2636 { 0x01, 0x101a },
2637 { 0x00, 0xa0ff },
2638 { 0x04, 0xf800 },
2639 { 0x04, 0x0000 },
2640 { 0x1f, 0x0000 },
2641
2642 { 0x1f, 0x0001 },
2643 { 0x10, 0xf41b },
2644 { 0x14, 0xfb54 },
2645 { 0x18, 0xf5c7 },
2646 { 0x1f, 0x0000 },
2647
2648 { 0x1f, 0x0001 },
2649 { 0x17, 0x0cc0 },
2650 { 0x1f, 0x0000 }
2651 };
2652
2653 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2654
2655 rtl8169scd_hw_phy_config_quirk(tp);
2656 }
2657
2658 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2659 {
2660 static const struct phy_reg phy_reg_init[] = {
2661 { 0x1f, 0x0001 },
2662 { 0x04, 0x0000 },
2663 { 0x03, 0x00a1 },
2664 { 0x02, 0x0008 },
2665 { 0x01, 0x0120 },
2666 { 0x00, 0x1000 },
2667 { 0x04, 0x0800 },
2668 { 0x04, 0x9000 },
2669 { 0x03, 0x802f },
2670 { 0x02, 0x4f02 },
2671 { 0x01, 0x0409 },
2672 { 0x00, 0xf099 },
2673 { 0x04, 0x9800 },
2674 { 0x04, 0xa000 },
2675 { 0x03, 0xdf01 },
2676 { 0x02, 0xdf20 },
2677 { 0x01, 0xff95 },
2678 { 0x00, 0xba00 },
2679 { 0x04, 0xa800 },
2680 { 0x04, 0xf000 },
2681 { 0x03, 0xdf01 },
2682 { 0x02, 0xdf20 },
2683 { 0x01, 0x101a },
2684 { 0x00, 0xa0ff },
2685 { 0x04, 0xf800 },
2686 { 0x04, 0x0000 },
2687 { 0x1f, 0x0000 },
2688
2689 { 0x1f, 0x0001 },
2690 { 0x0b, 0x8480 },
2691 { 0x1f, 0x0000 },
2692
2693 { 0x1f, 0x0001 },
2694 { 0x18, 0x67c7 },
2695 { 0x04, 0x2000 },
2696 { 0x03, 0x002f },
2697 { 0x02, 0x4360 },
2698 { 0x01, 0x0109 },
2699 { 0x00, 0x3022 },
2700 { 0x04, 0x2800 },
2701 { 0x1f, 0x0000 },
2702
2703 { 0x1f, 0x0001 },
2704 { 0x17, 0x0cc0 },
2705 { 0x1f, 0x0000 }
2706 };
2707
2708 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2709 }
2710
2711 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2712 {
2713 static const struct phy_reg phy_reg_init[] = {
2714 { 0x10, 0xf41b },
2715 { 0x1f, 0x0000 }
2716 };
2717
2718 rtl_writephy(tp, 0x1f, 0x0001);
2719 rtl_patchphy(tp, 0x16, 1 << 0);
2720
2721 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2722 }
2723
2724 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2725 {
2726 static const struct phy_reg phy_reg_init[] = {
2727 { 0x1f, 0x0001 },
2728 { 0x10, 0xf41b },
2729 { 0x1f, 0x0000 }
2730 };
2731
2732 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2733 }
2734
2735 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2736 {
2737 static const struct phy_reg phy_reg_init[] = {
2738 { 0x1f, 0x0000 },
2739 { 0x1d, 0x0f00 },
2740 { 0x1f, 0x0002 },
2741 { 0x0c, 0x1ec8 },
2742 { 0x1f, 0x0000 }
2743 };
2744
2745 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2746 }
2747
2748 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2749 {
2750 static const struct phy_reg phy_reg_init[] = {
2751 { 0x1f, 0x0001 },
2752 { 0x1d, 0x3d98 },
2753 { 0x1f, 0x0000 }
2754 };
2755
2756 rtl_writephy(tp, 0x1f, 0x0000);
2757 rtl_patchphy(tp, 0x14, 1 << 5);
2758 rtl_patchphy(tp, 0x0d, 1 << 5);
2759
2760 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2761 }
2762
2763 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2764 {
2765 static const struct phy_reg phy_reg_init[] = {
2766 { 0x1f, 0x0001 },
2767 { 0x12, 0x2300 },
2768 { 0x1f, 0x0002 },
2769 { 0x00, 0x88d4 },
2770 { 0x01, 0x82b1 },
2771 { 0x03, 0x7002 },
2772 { 0x08, 0x9e30 },
2773 { 0x09, 0x01f0 },
2774 { 0x0a, 0x5500 },
2775 { 0x0c, 0x00c8 },
2776 { 0x1f, 0x0003 },
2777 { 0x12, 0xc096 },
2778 { 0x16, 0x000a },
2779 { 0x1f, 0x0000 },
2780 { 0x1f, 0x0000 },
2781 { 0x09, 0x2000 },
2782 { 0x09, 0x0000 }
2783 };
2784
2785 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2786
2787 rtl_patchphy(tp, 0x14, 1 << 5);
2788 rtl_patchphy(tp, 0x0d, 1 << 5);
2789 rtl_writephy(tp, 0x1f, 0x0000);
2790 }
2791
2792 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2793 {
2794 static const struct phy_reg phy_reg_init[] = {
2795 { 0x1f, 0x0001 },
2796 { 0x12, 0x2300 },
2797 { 0x03, 0x802f },
2798 { 0x02, 0x4f02 },
2799 { 0x01, 0x0409 },
2800 { 0x00, 0xf099 },
2801 { 0x04, 0x9800 },
2802 { 0x04, 0x9000 },
2803 { 0x1d, 0x3d98 },
2804 { 0x1f, 0x0002 },
2805 { 0x0c, 0x7eb8 },
2806 { 0x06, 0x0761 },
2807 { 0x1f, 0x0003 },
2808 { 0x16, 0x0f0a },
2809 { 0x1f, 0x0000 }
2810 };
2811
2812 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2813
2814 rtl_patchphy(tp, 0x16, 1 << 0);
2815 rtl_patchphy(tp, 0x14, 1 << 5);
2816 rtl_patchphy(tp, 0x0d, 1 << 5);
2817 rtl_writephy(tp, 0x1f, 0x0000);
2818 }
2819
2820 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2821 {
2822 static const struct phy_reg phy_reg_init[] = {
2823 { 0x1f, 0x0001 },
2824 { 0x12, 0x2300 },
2825 { 0x1d, 0x3d98 },
2826 { 0x1f, 0x0002 },
2827 { 0x0c, 0x7eb8 },
2828 { 0x06, 0x5461 },
2829 { 0x1f, 0x0003 },
2830 { 0x16, 0x0f0a },
2831 { 0x1f, 0x0000 }
2832 };
2833
2834 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2835
2836 rtl_patchphy(tp, 0x16, 1 << 0);
2837 rtl_patchphy(tp, 0x14, 1 << 5);
2838 rtl_patchphy(tp, 0x0d, 1 << 5);
2839 rtl_writephy(tp, 0x1f, 0x0000);
2840 }
2841
2842 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2843 {
2844 rtl8168c_3_hw_phy_config(tp);
2845 }
2846
2847 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2848 {
2849 static const struct phy_reg phy_reg_init_0[] = {
2850 /* Channel Estimation */
2851 { 0x1f, 0x0001 },
2852 { 0x06, 0x4064 },
2853 { 0x07, 0x2863 },
2854 { 0x08, 0x059c },
2855 { 0x09, 0x26b4 },
2856 { 0x0a, 0x6a19 },
2857 { 0x0b, 0xdcc8 },
2858 { 0x10, 0xf06d },
2859 { 0x14, 0x7f68 },
2860 { 0x18, 0x7fd9 },
2861 { 0x1c, 0xf0ff },
2862 { 0x1d, 0x3d9c },
2863 { 0x1f, 0x0003 },
2864 { 0x12, 0xf49f },
2865 { 0x13, 0x070b },
2866 { 0x1a, 0x05ad },
2867 { 0x14, 0x94c0 },
2868
2869 /*
2870 * Tx Error Issue
2871 * Enhance line driver power
2872 */
2873 { 0x1f, 0x0002 },
2874 { 0x06, 0x5561 },
2875 { 0x1f, 0x0005 },
2876 { 0x05, 0x8332 },
2877 { 0x06, 0x5561 },
2878
2879 /*
2880 * Can not link to 1Gbps with bad cable
2881 * Decrease SNR threshold form 21.07dB to 19.04dB
2882 */
2883 { 0x1f, 0x0001 },
2884 { 0x17, 0x0cc0 },
2885
2886 { 0x1f, 0x0000 },
2887 { 0x0d, 0xf880 }
2888 };
2889
2890 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2891
2892 /*
2893 * Rx Error Issue
2894 * Fine Tune Switching regulator parameter
2895 */
2896 rtl_writephy(tp, 0x1f, 0x0002);
2897 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2898 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2899
2900 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2901 static const struct phy_reg phy_reg_init[] = {
2902 { 0x1f, 0x0002 },
2903 { 0x05, 0x669a },
2904 { 0x1f, 0x0005 },
2905 { 0x05, 0x8330 },
2906 { 0x06, 0x669a },
2907 { 0x1f, 0x0002 }
2908 };
2909 int val;
2910
2911 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2912
2913 val = rtl_readphy(tp, 0x0d);
2914
2915 if ((val & 0x00ff) != 0x006c) {
2916 static const u32 set[] = {
2917 0x0065, 0x0066, 0x0067, 0x0068,
2918 0x0069, 0x006a, 0x006b, 0x006c
2919 };
2920 int i;
2921
2922 rtl_writephy(tp, 0x1f, 0x0002);
2923
2924 val &= 0xff00;
2925 for (i = 0; i < ARRAY_SIZE(set); i++)
2926 rtl_writephy(tp, 0x0d, val | set[i]);
2927 }
2928 } else {
2929 static const struct phy_reg phy_reg_init[] = {
2930 { 0x1f, 0x0002 },
2931 { 0x05, 0x6662 },
2932 { 0x1f, 0x0005 },
2933 { 0x05, 0x8330 },
2934 { 0x06, 0x6662 }
2935 };
2936
2937 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2938 }
2939
2940 /* RSET couple improve */
2941 rtl_writephy(tp, 0x1f, 0x0002);
2942 rtl_patchphy(tp, 0x0d, 0x0300);
2943 rtl_patchphy(tp, 0x0f, 0x0010);
2944
2945 /* Fine tune PLL performance */
2946 rtl_writephy(tp, 0x1f, 0x0002);
2947 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2948 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2949
2950 rtl_writephy(tp, 0x1f, 0x0005);
2951 rtl_writephy(tp, 0x05, 0x001b);
2952
2953 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2954
2955 rtl_writephy(tp, 0x1f, 0x0000);
2956 }
2957
2958 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2959 {
2960 static const struct phy_reg phy_reg_init_0[] = {
2961 /* Channel Estimation */
2962 { 0x1f, 0x0001 },
2963 { 0x06, 0x4064 },
2964 { 0x07, 0x2863 },
2965 { 0x08, 0x059c },
2966 { 0x09, 0x26b4 },
2967 { 0x0a, 0x6a19 },
2968 { 0x0b, 0xdcc8 },
2969 { 0x10, 0xf06d },
2970 { 0x14, 0x7f68 },
2971 { 0x18, 0x7fd9 },
2972 { 0x1c, 0xf0ff },
2973 { 0x1d, 0x3d9c },
2974 { 0x1f, 0x0003 },
2975 { 0x12, 0xf49f },
2976 { 0x13, 0x070b },
2977 { 0x1a, 0x05ad },
2978 { 0x14, 0x94c0 },
2979
2980 /*
2981 * Tx Error Issue
2982 * Enhance line driver power
2983 */
2984 { 0x1f, 0x0002 },
2985 { 0x06, 0x5561 },
2986 { 0x1f, 0x0005 },
2987 { 0x05, 0x8332 },
2988 { 0x06, 0x5561 },
2989
2990 /*
2991 * Can not link to 1Gbps with bad cable
2992 * Decrease SNR threshold form 21.07dB to 19.04dB
2993 */
2994 { 0x1f, 0x0001 },
2995 { 0x17, 0x0cc0 },
2996
2997 { 0x1f, 0x0000 },
2998 { 0x0d, 0xf880 }
2999 };
3000
3001 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3002
3003 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3004 static const struct phy_reg phy_reg_init[] = {
3005 { 0x1f, 0x0002 },
3006 { 0x05, 0x669a },
3007 { 0x1f, 0x0005 },
3008 { 0x05, 0x8330 },
3009 { 0x06, 0x669a },
3010
3011 { 0x1f, 0x0002 }
3012 };
3013 int val;
3014
3015 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3016
3017 val = rtl_readphy(tp, 0x0d);
3018 if ((val & 0x00ff) != 0x006c) {
3019 static const u32 set[] = {
3020 0x0065, 0x0066, 0x0067, 0x0068,
3021 0x0069, 0x006a, 0x006b, 0x006c
3022 };
3023 int i;
3024
3025 rtl_writephy(tp, 0x1f, 0x0002);
3026
3027 val &= 0xff00;
3028 for (i = 0; i < ARRAY_SIZE(set); i++)
3029 rtl_writephy(tp, 0x0d, val | set[i]);
3030 }
3031 } else {
3032 static const struct phy_reg phy_reg_init[] = {
3033 { 0x1f, 0x0002 },
3034 { 0x05, 0x2642 },
3035 { 0x1f, 0x0005 },
3036 { 0x05, 0x8330 },
3037 { 0x06, 0x2642 }
3038 };
3039
3040 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3041 }
3042
3043 /* Fine tune PLL performance */
3044 rtl_writephy(tp, 0x1f, 0x0002);
3045 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3046 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3047
3048 /* Switching regulator Slew rate */
3049 rtl_writephy(tp, 0x1f, 0x0002);
3050 rtl_patchphy(tp, 0x0f, 0x0017);
3051
3052 rtl_writephy(tp, 0x1f, 0x0005);
3053 rtl_writephy(tp, 0x05, 0x001b);
3054
3055 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3056
3057 rtl_writephy(tp, 0x1f, 0x0000);
3058 }
3059
3060 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3061 {
3062 static const struct phy_reg phy_reg_init[] = {
3063 { 0x1f, 0x0002 },
3064 { 0x10, 0x0008 },
3065 { 0x0d, 0x006c },
3066
3067 { 0x1f, 0x0000 },
3068 { 0x0d, 0xf880 },
3069
3070 { 0x1f, 0x0001 },
3071 { 0x17, 0x0cc0 },
3072
3073 { 0x1f, 0x0001 },
3074 { 0x0b, 0xa4d8 },
3075 { 0x09, 0x281c },
3076 { 0x07, 0x2883 },
3077 { 0x0a, 0x6b35 },
3078 { 0x1d, 0x3da4 },
3079 { 0x1c, 0xeffd },
3080 { 0x14, 0x7f52 },
3081 { 0x18, 0x7fc6 },
3082 { 0x08, 0x0601 },
3083 { 0x06, 0x4063 },
3084 { 0x10, 0xf074 },
3085 { 0x1f, 0x0003 },
3086 { 0x13, 0x0789 },
3087 { 0x12, 0xf4bd },
3088 { 0x1a, 0x04fd },
3089 { 0x14, 0x84b0 },
3090 { 0x1f, 0x0000 },
3091 { 0x00, 0x9200 },
3092
3093 { 0x1f, 0x0005 },
3094 { 0x01, 0x0340 },
3095 { 0x1f, 0x0001 },
3096 { 0x04, 0x4000 },
3097 { 0x03, 0x1d21 },
3098 { 0x02, 0x0c32 },
3099 { 0x01, 0x0200 },
3100 { 0x00, 0x5554 },
3101 { 0x04, 0x4800 },
3102 { 0x04, 0x4000 },
3103 { 0x04, 0xf000 },
3104 { 0x03, 0xdf01 },
3105 { 0x02, 0xdf20 },
3106 { 0x01, 0x101a },
3107 { 0x00, 0xa0ff },
3108 { 0x04, 0xf800 },
3109 { 0x04, 0xf000 },
3110 { 0x1f, 0x0000 },
3111
3112 { 0x1f, 0x0007 },
3113 { 0x1e, 0x0023 },
3114 { 0x16, 0x0000 },
3115 { 0x1f, 0x0000 }
3116 };
3117
3118 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3119 }
3120
3121 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3122 {
3123 static const struct phy_reg phy_reg_init[] = {
3124 { 0x1f, 0x0001 },
3125 { 0x17, 0x0cc0 },
3126
3127 { 0x1f, 0x0007 },
3128 { 0x1e, 0x002d },
3129 { 0x18, 0x0040 },
3130 { 0x1f, 0x0000 }
3131 };
3132
3133 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3134 rtl_patchphy(tp, 0x0d, 1 << 5);
3135 }
3136
3137 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3138 {
3139 static const struct phy_reg phy_reg_init[] = {
3140 /* Enable Delay cap */
3141 { 0x1f, 0x0005 },
3142 { 0x05, 0x8b80 },
3143 { 0x06, 0xc896 },
3144 { 0x1f, 0x0000 },
3145
3146 /* Channel estimation fine tune */
3147 { 0x1f, 0x0001 },
3148 { 0x0b, 0x6c20 },
3149 { 0x07, 0x2872 },
3150 { 0x1c, 0xefff },
3151 { 0x1f, 0x0003 },
3152 { 0x14, 0x6420 },
3153 { 0x1f, 0x0000 },
3154
3155 /* Update PFM & 10M TX idle timer */
3156 { 0x1f, 0x0007 },
3157 { 0x1e, 0x002f },
3158 { 0x15, 0x1919 },
3159 { 0x1f, 0x0000 },
3160
3161 { 0x1f, 0x0007 },
3162 { 0x1e, 0x00ac },
3163 { 0x18, 0x0006 },
3164 { 0x1f, 0x0000 }
3165 };
3166
3167 rtl_apply_firmware(tp);
3168
3169 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3170
3171 /* DCO enable for 10M IDLE Power */
3172 rtl_writephy(tp, 0x1f, 0x0007);
3173 rtl_writephy(tp, 0x1e, 0x0023);
3174 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3175 rtl_writephy(tp, 0x1f, 0x0000);
3176
3177 /* For impedance matching */
3178 rtl_writephy(tp, 0x1f, 0x0002);
3179 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3180 rtl_writephy(tp, 0x1f, 0x0000);
3181
3182 /* PHY auto speed down */
3183 rtl_writephy(tp, 0x1f, 0x0007);
3184 rtl_writephy(tp, 0x1e, 0x002d);
3185 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3186 rtl_writephy(tp, 0x1f, 0x0000);
3187 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3188
3189 rtl_writephy(tp, 0x1f, 0x0005);
3190 rtl_writephy(tp, 0x05, 0x8b86);
3191 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3192 rtl_writephy(tp, 0x1f, 0x0000);
3193
3194 rtl_writephy(tp, 0x1f, 0x0005);
3195 rtl_writephy(tp, 0x05, 0x8b85);
3196 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3197 rtl_writephy(tp, 0x1f, 0x0007);
3198 rtl_writephy(tp, 0x1e, 0x0020);
3199 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3200 rtl_writephy(tp, 0x1f, 0x0006);
3201 rtl_writephy(tp, 0x00, 0x5a00);
3202 rtl_writephy(tp, 0x1f, 0x0000);
3203 rtl_writephy(tp, 0x0d, 0x0007);
3204 rtl_writephy(tp, 0x0e, 0x003c);
3205 rtl_writephy(tp, 0x0d, 0x4007);
3206 rtl_writephy(tp, 0x0e, 0x0000);
3207 rtl_writephy(tp, 0x0d, 0x0000);
3208 }
3209
3210 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3211 {
3212 const u16 w[] = {
3213 addr[0] | (addr[1] << 8),
3214 addr[2] | (addr[3] << 8),
3215 addr[4] | (addr[5] << 8)
3216 };
3217 const struct exgmac_reg e[] = {
3218 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3219 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3220 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3221 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3222 };
3223
3224 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3225 }
3226
3227 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3228 {
3229 static const struct phy_reg phy_reg_init[] = {
3230 /* Enable Delay cap */
3231 { 0x1f, 0x0004 },
3232 { 0x1f, 0x0007 },
3233 { 0x1e, 0x00ac },
3234 { 0x18, 0x0006 },
3235 { 0x1f, 0x0002 },
3236 { 0x1f, 0x0000 },
3237 { 0x1f, 0x0000 },
3238
3239 /* Channel estimation fine tune */
3240 { 0x1f, 0x0003 },
3241 { 0x09, 0xa20f },
3242 { 0x1f, 0x0000 },
3243 { 0x1f, 0x0000 },
3244
3245 /* Green Setting */
3246 { 0x1f, 0x0005 },
3247 { 0x05, 0x8b5b },
3248 { 0x06, 0x9222 },
3249 { 0x05, 0x8b6d },
3250 { 0x06, 0x8000 },
3251 { 0x05, 0x8b76 },
3252 { 0x06, 0x8000 },
3253 { 0x1f, 0x0000 }
3254 };
3255
3256 rtl_apply_firmware(tp);
3257
3258 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3259
3260 /* For 4-corner performance improve */
3261 rtl_writephy(tp, 0x1f, 0x0005);
3262 rtl_writephy(tp, 0x05, 0x8b80);
3263 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3264 rtl_writephy(tp, 0x1f, 0x0000);
3265
3266 /* PHY auto speed down */
3267 rtl_writephy(tp, 0x1f, 0x0004);
3268 rtl_writephy(tp, 0x1f, 0x0007);
3269 rtl_writephy(tp, 0x1e, 0x002d);
3270 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3271 rtl_writephy(tp, 0x1f, 0x0002);
3272 rtl_writephy(tp, 0x1f, 0x0000);
3273 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3274
3275 /* improve 10M EEE waveform */
3276 rtl_writephy(tp, 0x1f, 0x0005);
3277 rtl_writephy(tp, 0x05, 0x8b86);
3278 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3279 rtl_writephy(tp, 0x1f, 0x0000);
3280
3281 /* Improve 2-pair detection performance */
3282 rtl_writephy(tp, 0x1f, 0x0005);
3283 rtl_writephy(tp, 0x05, 0x8b85);
3284 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3285 rtl_writephy(tp, 0x1f, 0x0000);
3286
3287 /* EEE setting */
3288 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3289 rtl_writephy(tp, 0x1f, 0x0005);
3290 rtl_writephy(tp, 0x05, 0x8b85);
3291 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3292 rtl_writephy(tp, 0x1f, 0x0004);
3293 rtl_writephy(tp, 0x1f, 0x0007);
3294 rtl_writephy(tp, 0x1e, 0x0020);
3295 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3296 rtl_writephy(tp, 0x1f, 0x0002);
3297 rtl_writephy(tp, 0x1f, 0x0000);
3298 rtl_writephy(tp, 0x0d, 0x0007);
3299 rtl_writephy(tp, 0x0e, 0x003c);
3300 rtl_writephy(tp, 0x0d, 0x4007);
3301 rtl_writephy(tp, 0x0e, 0x0000);
3302 rtl_writephy(tp, 0x0d, 0x0000);
3303
3304 /* Green feature */
3305 rtl_writephy(tp, 0x1f, 0x0003);
3306 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3307 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3308 rtl_writephy(tp, 0x1f, 0x0000);
3309
3310 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3311 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3312 }
3313
3314 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3315 {
3316 /* For 4-corner performance improve */
3317 rtl_writephy(tp, 0x1f, 0x0005);
3318 rtl_writephy(tp, 0x05, 0x8b80);
3319 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3320 rtl_writephy(tp, 0x1f, 0x0000);
3321
3322 /* PHY auto speed down */
3323 rtl_writephy(tp, 0x1f, 0x0007);
3324 rtl_writephy(tp, 0x1e, 0x002d);
3325 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3326 rtl_writephy(tp, 0x1f, 0x0000);
3327 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3328
3329 /* Improve 10M EEE waveform */
3330 rtl_writephy(tp, 0x1f, 0x0005);
3331 rtl_writephy(tp, 0x05, 0x8b86);
3332 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3333 rtl_writephy(tp, 0x1f, 0x0000);
3334 }
3335
3336 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3337 {
3338 static const struct phy_reg phy_reg_init[] = {
3339 /* Channel estimation fine tune */
3340 { 0x1f, 0x0003 },
3341 { 0x09, 0xa20f },
3342 { 0x1f, 0x0000 },
3343
3344 /* Modify green table for giga & fnet */
3345 { 0x1f, 0x0005 },
3346 { 0x05, 0x8b55 },
3347 { 0x06, 0x0000 },
3348 { 0x05, 0x8b5e },
3349 { 0x06, 0x0000 },
3350 { 0x05, 0x8b67 },
3351 { 0x06, 0x0000 },
3352 { 0x05, 0x8b70 },
3353 { 0x06, 0x0000 },
3354 { 0x1f, 0x0000 },
3355 { 0x1f, 0x0007 },
3356 { 0x1e, 0x0078 },
3357 { 0x17, 0x0000 },
3358 { 0x19, 0x00fb },
3359 { 0x1f, 0x0000 },
3360
3361 /* Modify green table for 10M */
3362 { 0x1f, 0x0005 },
3363 { 0x05, 0x8b79 },
3364 { 0x06, 0xaa00 },
3365 { 0x1f, 0x0000 },
3366
3367 /* Disable hiimpedance detection (RTCT) */
3368 { 0x1f, 0x0003 },
3369 { 0x01, 0x328a },
3370 { 0x1f, 0x0000 }
3371 };
3372
3373 rtl_apply_firmware(tp);
3374
3375 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3376
3377 rtl8168f_hw_phy_config(tp);
3378
3379 /* Improve 2-pair detection performance */
3380 rtl_writephy(tp, 0x1f, 0x0005);
3381 rtl_writephy(tp, 0x05, 0x8b85);
3382 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3383 rtl_writephy(tp, 0x1f, 0x0000);
3384 }
3385
3386 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3387 {
3388 rtl_apply_firmware(tp);
3389
3390 rtl8168f_hw_phy_config(tp);
3391 }
3392
3393 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3394 {
3395 static const struct phy_reg phy_reg_init[] = {
3396 /* Channel estimation fine tune */
3397 { 0x1f, 0x0003 },
3398 { 0x09, 0xa20f },
3399 { 0x1f, 0x0000 },
3400
3401 /* Modify green table for giga & fnet */
3402 { 0x1f, 0x0005 },
3403 { 0x05, 0x8b55 },
3404 { 0x06, 0x0000 },
3405 { 0x05, 0x8b5e },
3406 { 0x06, 0x0000 },
3407 { 0x05, 0x8b67 },
3408 { 0x06, 0x0000 },
3409 { 0x05, 0x8b70 },
3410 { 0x06, 0x0000 },
3411 { 0x1f, 0x0000 },
3412 { 0x1f, 0x0007 },
3413 { 0x1e, 0x0078 },
3414 { 0x17, 0x0000 },
3415 { 0x19, 0x00aa },
3416 { 0x1f, 0x0000 },
3417
3418 /* Modify green table for 10M */
3419 { 0x1f, 0x0005 },
3420 { 0x05, 0x8b79 },
3421 { 0x06, 0xaa00 },
3422 { 0x1f, 0x0000 },
3423
3424 /* Disable hiimpedance detection (RTCT) */
3425 { 0x1f, 0x0003 },
3426 { 0x01, 0x328a },
3427 { 0x1f, 0x0000 }
3428 };
3429
3430
3431 rtl_apply_firmware(tp);
3432
3433 rtl8168f_hw_phy_config(tp);
3434
3435 /* Improve 2-pair detection performance */
3436 rtl_writephy(tp, 0x1f, 0x0005);
3437 rtl_writephy(tp, 0x05, 0x8b85);
3438 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3439 rtl_writephy(tp, 0x1f, 0x0000);
3440
3441 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3442
3443 /* Modify green table for giga */
3444 rtl_writephy(tp, 0x1f, 0x0005);
3445 rtl_writephy(tp, 0x05, 0x8b54);
3446 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3447 rtl_writephy(tp, 0x05, 0x8b5d);
3448 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3449 rtl_writephy(tp, 0x05, 0x8a7c);
3450 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3451 rtl_writephy(tp, 0x05, 0x8a7f);
3452 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3453 rtl_writephy(tp, 0x05, 0x8a82);
3454 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3455 rtl_writephy(tp, 0x05, 0x8a85);
3456 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3457 rtl_writephy(tp, 0x05, 0x8a88);
3458 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3459 rtl_writephy(tp, 0x1f, 0x0000);
3460
3461 /* uc same-seed solution */
3462 rtl_writephy(tp, 0x1f, 0x0005);
3463 rtl_writephy(tp, 0x05, 0x8b85);
3464 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3465 rtl_writephy(tp, 0x1f, 0x0000);
3466
3467 /* eee setting */
3468 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3469 rtl_writephy(tp, 0x1f, 0x0005);
3470 rtl_writephy(tp, 0x05, 0x8b85);
3471 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3472 rtl_writephy(tp, 0x1f, 0x0004);
3473 rtl_writephy(tp, 0x1f, 0x0007);
3474 rtl_writephy(tp, 0x1e, 0x0020);
3475 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3476 rtl_writephy(tp, 0x1f, 0x0000);
3477 rtl_writephy(tp, 0x0d, 0x0007);
3478 rtl_writephy(tp, 0x0e, 0x003c);
3479 rtl_writephy(tp, 0x0d, 0x4007);
3480 rtl_writephy(tp, 0x0e, 0x0000);
3481 rtl_writephy(tp, 0x0d, 0x0000);
3482
3483 /* Green feature */
3484 rtl_writephy(tp, 0x1f, 0x0003);
3485 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3486 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3487 rtl_writephy(tp, 0x1f, 0x0000);
3488 }
3489
3490 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3491 {
3492 rtl_apply_firmware(tp);
3493
3494 rtl_writephy(tp, 0x1f, 0x0a46);
3495 if (rtl_readphy(tp, 0x10) & 0x0100) {
3496 rtl_writephy(tp, 0x1f, 0x0bcc);
3497 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3498 } else {
3499 rtl_writephy(tp, 0x1f, 0x0bcc);
3500 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3501 }
3502
3503 rtl_writephy(tp, 0x1f, 0x0a46);
3504 if (rtl_readphy(tp, 0x13) & 0x0100) {
3505 rtl_writephy(tp, 0x1f, 0x0c41);
3506 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3507 } else {
3508 rtl_writephy(tp, 0x1f, 0x0c41);
3509 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3510 }
3511
3512 /* Enable PHY auto speed down */
3513 rtl_writephy(tp, 0x1f, 0x0a44);
3514 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3515
3516 rtl_writephy(tp, 0x1f, 0x0bcc);
3517 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3518 rtl_writephy(tp, 0x1f, 0x0a44);
3519 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3520 rtl_writephy(tp, 0x1f, 0x0a43);
3521 rtl_writephy(tp, 0x13, 0x8084);
3522 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3523 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3524
3525 /* EEE auto-fallback function */
3526 rtl_writephy(tp, 0x1f, 0x0a4b);
3527 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3528
3529 /* Enable UC LPF tune function */
3530 rtl_writephy(tp, 0x1f, 0x0a43);
3531 rtl_writephy(tp, 0x13, 0x8012);
3532 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3533
3534 rtl_writephy(tp, 0x1f, 0x0c42);
3535 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3536
3537 /* Improve SWR Efficiency */
3538 rtl_writephy(tp, 0x1f, 0x0bcd);
3539 rtl_writephy(tp, 0x14, 0x5065);
3540 rtl_writephy(tp, 0x14, 0xd065);
3541 rtl_writephy(tp, 0x1f, 0x0bc8);
3542 rtl_writephy(tp, 0x11, 0x5655);
3543 rtl_writephy(tp, 0x1f, 0x0bcd);
3544 rtl_writephy(tp, 0x14, 0x1065);
3545 rtl_writephy(tp, 0x14, 0x9065);
3546 rtl_writephy(tp, 0x14, 0x1065);
3547
3548 /* Check ALDPS bit, disable it if enabled */
3549 rtl_writephy(tp, 0x1f, 0x0a43);
3550 if (rtl_readphy(tp, 0x10) & 0x0004)
3551 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3552
3553 rtl_writephy(tp, 0x1f, 0x0000);
3554 }
3555
3556 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3557 {
3558 rtl_apply_firmware(tp);
3559 }
3560
3561 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3562 {
3563 u16 dout_tapbin;
3564 u32 data;
3565
3566 rtl_apply_firmware(tp);
3567
3568 /* CHN EST parameters adjust - giga master */
3569 rtl_writephy(tp, 0x1f, 0x0a43);
3570 rtl_writephy(tp, 0x13, 0x809b);
3571 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3572 rtl_writephy(tp, 0x13, 0x80a2);
3573 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3574 rtl_writephy(tp, 0x13, 0x80a4);
3575 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3576 rtl_writephy(tp, 0x13, 0x809c);
3577 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3578 rtl_writephy(tp, 0x1f, 0x0000);
3579
3580 /* CHN EST parameters adjust - giga slave */
3581 rtl_writephy(tp, 0x1f, 0x0a43);
3582 rtl_writephy(tp, 0x13, 0x80ad);
3583 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3584 rtl_writephy(tp, 0x13, 0x80b4);
3585 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3586 rtl_writephy(tp, 0x13, 0x80ac);
3587 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3588 rtl_writephy(tp, 0x1f, 0x0000);
3589
3590 /* CHN EST parameters adjust - fnet */
3591 rtl_writephy(tp, 0x1f, 0x0a43);
3592 rtl_writephy(tp, 0x13, 0x808e);
3593 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3594 rtl_writephy(tp, 0x13, 0x8090);
3595 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3596 rtl_writephy(tp, 0x13, 0x8092);
3597 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3598 rtl_writephy(tp, 0x1f, 0x0000);
3599
3600 /* enable R-tune & PGA-retune function */
3601 dout_tapbin = 0;
3602 rtl_writephy(tp, 0x1f, 0x0a46);
3603 data = rtl_readphy(tp, 0x13);
3604 data &= 3;
3605 data <<= 2;
3606 dout_tapbin |= data;
3607 data = rtl_readphy(tp, 0x12);
3608 data &= 0xc000;
3609 data >>= 14;
3610 dout_tapbin |= data;
3611 dout_tapbin = ~(dout_tapbin^0x08);
3612 dout_tapbin <<= 12;
3613 dout_tapbin &= 0xf000;
3614 rtl_writephy(tp, 0x1f, 0x0a43);
3615 rtl_writephy(tp, 0x13, 0x827a);
3616 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3617 rtl_writephy(tp, 0x13, 0x827b);
3618 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3619 rtl_writephy(tp, 0x13, 0x827c);
3620 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3621 rtl_writephy(tp, 0x13, 0x827d);
3622 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3623
3624 rtl_writephy(tp, 0x1f, 0x0a43);
3625 rtl_writephy(tp, 0x13, 0x0811);
3626 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3627 rtl_writephy(tp, 0x1f, 0x0a42);
3628 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3629 rtl_writephy(tp, 0x1f, 0x0000);
3630
3631 /* enable GPHY 10M */
3632 rtl_writephy(tp, 0x1f, 0x0a44);
3633 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3634 rtl_writephy(tp, 0x1f, 0x0000);
3635
3636 /* SAR ADC performance */
3637 rtl_writephy(tp, 0x1f, 0x0bca);
3638 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3639 rtl_writephy(tp, 0x1f, 0x0000);
3640
3641 rtl_writephy(tp, 0x1f, 0x0a43);
3642 rtl_writephy(tp, 0x13, 0x803f);
3643 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3644 rtl_writephy(tp, 0x13, 0x8047);
3645 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3646 rtl_writephy(tp, 0x13, 0x804f);
3647 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3648 rtl_writephy(tp, 0x13, 0x8057);
3649 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3650 rtl_writephy(tp, 0x13, 0x805f);
3651 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3652 rtl_writephy(tp, 0x13, 0x8067);
3653 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3654 rtl_writephy(tp, 0x13, 0x806f);
3655 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3656 rtl_writephy(tp, 0x1f, 0x0000);
3657
3658 /* disable phy pfm mode */
3659 rtl_writephy(tp, 0x1f, 0x0a44);
3660 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3661 rtl_writephy(tp, 0x1f, 0x0000);
3662
3663 /* Check ALDPS bit, disable it if enabled */
3664 rtl_writephy(tp, 0x1f, 0x0a43);
3665 if (rtl_readphy(tp, 0x10) & 0x0004)
3666 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3667
3668 rtl_writephy(tp, 0x1f, 0x0000);
3669 }
3670
3671 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3672 {
3673 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3674 u16 rlen;
3675 u32 data;
3676
3677 rtl_apply_firmware(tp);
3678
3679 /* CHIN EST parameter update */
3680 rtl_writephy(tp, 0x1f, 0x0a43);
3681 rtl_writephy(tp, 0x13, 0x808a);
3682 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3683 rtl_writephy(tp, 0x1f, 0x0000);
3684
3685 /* enable R-tune & PGA-retune function */
3686 rtl_writephy(tp, 0x1f, 0x0a43);
3687 rtl_writephy(tp, 0x13, 0x0811);
3688 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3689 rtl_writephy(tp, 0x1f, 0x0a42);
3690 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3691 rtl_writephy(tp, 0x1f, 0x0000);
3692
3693 /* enable GPHY 10M */
3694 rtl_writephy(tp, 0x1f, 0x0a44);
3695 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3696 rtl_writephy(tp, 0x1f, 0x0000);
3697
3698 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3699 data = r8168_mac_ocp_read(tp, 0xdd02);
3700 ioffset_p3 = ((data & 0x80)>>7);
3701 ioffset_p3 <<= 3;
3702
3703 data = r8168_mac_ocp_read(tp, 0xdd00);
3704 ioffset_p3 |= ((data & (0xe000))>>13);
3705 ioffset_p2 = ((data & (0x1e00))>>9);
3706 ioffset_p1 = ((data & (0x01e0))>>5);
3707 ioffset_p0 = ((data & 0x0010)>>4);
3708 ioffset_p0 <<= 3;
3709 ioffset_p0 |= (data & (0x07));
3710 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3711
3712 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3713 (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3714 rtl_writephy(tp, 0x1f, 0x0bcf);
3715 rtl_writephy(tp, 0x16, data);
3716 rtl_writephy(tp, 0x1f, 0x0000);
3717 }
3718
3719 /* Modify rlen (TX LPF corner frequency) level */
3720 rtl_writephy(tp, 0x1f, 0x0bcd);
3721 data = rtl_readphy(tp, 0x16);
3722 data &= 0x000f;
3723 rlen = 0;
3724 if (data > 3)
3725 rlen = data - 3;
3726 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3727 rtl_writephy(tp, 0x17, data);
3728 rtl_writephy(tp, 0x1f, 0x0bcd);
3729 rtl_writephy(tp, 0x1f, 0x0000);
3730
3731 /* disable phy pfm mode */
3732 rtl_writephy(tp, 0x1f, 0x0a44);
3733 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3734 rtl_writephy(tp, 0x1f, 0x0000);
3735
3736 /* Check ALDPS bit, disable it if enabled */
3737 rtl_writephy(tp, 0x1f, 0x0a43);
3738 if (rtl_readphy(tp, 0x10) & 0x0004)
3739 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3740
3741 rtl_writephy(tp, 0x1f, 0x0000);
3742 }
3743
3744 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3745 {
3746 static const struct phy_reg phy_reg_init[] = {
3747 { 0x1f, 0x0003 },
3748 { 0x08, 0x441d },
3749 { 0x01, 0x9100 },
3750 { 0x1f, 0x0000 }
3751 };
3752
3753 rtl_writephy(tp, 0x1f, 0x0000);
3754 rtl_patchphy(tp, 0x11, 1 << 12);
3755 rtl_patchphy(tp, 0x19, 1 << 13);
3756 rtl_patchphy(tp, 0x10, 1 << 15);
3757
3758 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3759 }
3760
3761 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3762 {
3763 static const struct phy_reg phy_reg_init[] = {
3764 { 0x1f, 0x0005 },
3765 { 0x1a, 0x0000 },
3766 { 0x1f, 0x0000 },
3767
3768 { 0x1f, 0x0004 },
3769 { 0x1c, 0x0000 },
3770 { 0x1f, 0x0000 },
3771
3772 { 0x1f, 0x0001 },
3773 { 0x15, 0x7701 },
3774 { 0x1f, 0x0000 }
3775 };
3776
3777 /* Disable ALDPS before ram code */
3778 rtl_writephy(tp, 0x1f, 0x0000);
3779 rtl_writephy(tp, 0x18, 0x0310);
3780 msleep(100);
3781
3782 rtl_apply_firmware(tp);
3783
3784 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3785 }
3786
3787 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3788 {
3789 /* Disable ALDPS before setting firmware */
3790 rtl_writephy(tp, 0x1f, 0x0000);
3791 rtl_writephy(tp, 0x18, 0x0310);
3792 msleep(20);
3793
3794 rtl_apply_firmware(tp);
3795
3796 /* EEE setting */
3797 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3798 rtl_writephy(tp, 0x1f, 0x0004);
3799 rtl_writephy(tp, 0x10, 0x401f);
3800 rtl_writephy(tp, 0x19, 0x7030);
3801 rtl_writephy(tp, 0x1f, 0x0000);
3802 }
3803
3804 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3805 {
3806 static const struct phy_reg phy_reg_init[] = {
3807 { 0x1f, 0x0004 },
3808 { 0x10, 0xc07f },
3809 { 0x19, 0x7030 },
3810 { 0x1f, 0x0000 }
3811 };
3812
3813 /* Disable ALDPS before ram code */
3814 rtl_writephy(tp, 0x1f, 0x0000);
3815 rtl_writephy(tp, 0x18, 0x0310);
3816 msleep(100);
3817
3818 rtl_apply_firmware(tp);
3819
3820 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3821 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3822
3823 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3824 }
3825
3826 static void rtl_hw_phy_config(struct net_device *dev)
3827 {
3828 struct rtl8169_private *tp = netdev_priv(dev);
3829
3830 rtl8169_print_mac_version(tp);
3831
3832 switch (tp->mac_version) {
3833 case RTL_GIGA_MAC_VER_01:
3834 break;
3835 case RTL_GIGA_MAC_VER_02:
3836 case RTL_GIGA_MAC_VER_03:
3837 rtl8169s_hw_phy_config(tp);
3838 break;
3839 case RTL_GIGA_MAC_VER_04:
3840 rtl8169sb_hw_phy_config(tp);
3841 break;
3842 case RTL_GIGA_MAC_VER_05:
3843 rtl8169scd_hw_phy_config(tp);
3844 break;
3845 case RTL_GIGA_MAC_VER_06:
3846 rtl8169sce_hw_phy_config(tp);
3847 break;
3848 case RTL_GIGA_MAC_VER_07:
3849 case RTL_GIGA_MAC_VER_08:
3850 case RTL_GIGA_MAC_VER_09:
3851 rtl8102e_hw_phy_config(tp);
3852 break;
3853 case RTL_GIGA_MAC_VER_11:
3854 rtl8168bb_hw_phy_config(tp);
3855 break;
3856 case RTL_GIGA_MAC_VER_12:
3857 rtl8168bef_hw_phy_config(tp);
3858 break;
3859 case RTL_GIGA_MAC_VER_17:
3860 rtl8168bef_hw_phy_config(tp);
3861 break;
3862 case RTL_GIGA_MAC_VER_18:
3863 rtl8168cp_1_hw_phy_config(tp);
3864 break;
3865 case RTL_GIGA_MAC_VER_19:
3866 rtl8168c_1_hw_phy_config(tp);
3867 break;
3868 case RTL_GIGA_MAC_VER_20:
3869 rtl8168c_2_hw_phy_config(tp);
3870 break;
3871 case RTL_GIGA_MAC_VER_21:
3872 rtl8168c_3_hw_phy_config(tp);
3873 break;
3874 case RTL_GIGA_MAC_VER_22:
3875 rtl8168c_4_hw_phy_config(tp);
3876 break;
3877 case RTL_GIGA_MAC_VER_23:
3878 case RTL_GIGA_MAC_VER_24:
3879 rtl8168cp_2_hw_phy_config(tp);
3880 break;
3881 case RTL_GIGA_MAC_VER_25:
3882 rtl8168d_1_hw_phy_config(tp);
3883 break;
3884 case RTL_GIGA_MAC_VER_26:
3885 rtl8168d_2_hw_phy_config(tp);
3886 break;
3887 case RTL_GIGA_MAC_VER_27:
3888 rtl8168d_3_hw_phy_config(tp);
3889 break;
3890 case RTL_GIGA_MAC_VER_28:
3891 rtl8168d_4_hw_phy_config(tp);
3892 break;
3893 case RTL_GIGA_MAC_VER_29:
3894 case RTL_GIGA_MAC_VER_30:
3895 rtl8105e_hw_phy_config(tp);
3896 break;
3897 case RTL_GIGA_MAC_VER_31:
3898 /* None. */
3899 break;
3900 case RTL_GIGA_MAC_VER_32:
3901 case RTL_GIGA_MAC_VER_33:
3902 rtl8168e_1_hw_phy_config(tp);
3903 break;
3904 case RTL_GIGA_MAC_VER_34:
3905 rtl8168e_2_hw_phy_config(tp);
3906 break;
3907 case RTL_GIGA_MAC_VER_35:
3908 rtl8168f_1_hw_phy_config(tp);
3909 break;
3910 case RTL_GIGA_MAC_VER_36:
3911 rtl8168f_2_hw_phy_config(tp);
3912 break;
3913
3914 case RTL_GIGA_MAC_VER_37:
3915 rtl8402_hw_phy_config(tp);
3916 break;
3917
3918 case RTL_GIGA_MAC_VER_38:
3919 rtl8411_hw_phy_config(tp);
3920 break;
3921
3922 case RTL_GIGA_MAC_VER_39:
3923 rtl8106e_hw_phy_config(tp);
3924 break;
3925
3926 case RTL_GIGA_MAC_VER_40:
3927 rtl8168g_1_hw_phy_config(tp);
3928 break;
3929 case RTL_GIGA_MAC_VER_42:
3930 case RTL_GIGA_MAC_VER_43:
3931 case RTL_GIGA_MAC_VER_44:
3932 rtl8168g_2_hw_phy_config(tp);
3933 break;
3934 case RTL_GIGA_MAC_VER_45:
3935 case RTL_GIGA_MAC_VER_47:
3936 rtl8168h_1_hw_phy_config(tp);
3937 break;
3938 case RTL_GIGA_MAC_VER_46:
3939 case RTL_GIGA_MAC_VER_48:
3940 rtl8168h_2_hw_phy_config(tp);
3941 break;
3942
3943 case RTL_GIGA_MAC_VER_41:
3944 default:
3945 break;
3946 }
3947 }
3948
3949 static void rtl_phy_work(struct rtl8169_private *tp)
3950 {
3951 struct timer_list *timer = &tp->timer;
3952 void __iomem *ioaddr = tp->mmio_addr;
3953 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3954
3955 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3956
3957 if (tp->phy_reset_pending(tp)) {
3958 /*
3959 * A busy loop could burn quite a few cycles on nowadays CPU.
3960 * Let's delay the execution of the timer for a few ticks.
3961 */
3962 timeout = HZ/10;
3963 goto out_mod_timer;
3964 }
3965
3966 if (tp->link_ok(ioaddr))
3967 return;
3968
3969 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
3970
3971 tp->phy_reset_enable(tp);
3972
3973 out_mod_timer:
3974 mod_timer(timer, jiffies + timeout);
3975 }
3976
3977 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3978 {
3979 if (!test_and_set_bit(flag, tp->wk.flags))
3980 schedule_work(&tp->wk.work);
3981 }
3982
3983 static void rtl8169_phy_timer(unsigned long __opaque)
3984 {
3985 struct net_device *dev = (struct net_device *)__opaque;
3986 struct rtl8169_private *tp = netdev_priv(dev);
3987
3988 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3989 }
3990
3991 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3992 void __iomem *ioaddr)
3993 {
3994 iounmap(ioaddr);
3995 pci_release_regions(pdev);
3996 pci_clear_mwi(pdev);
3997 pci_disable_device(pdev);
3998 free_netdev(dev);
3999 }
4000
4001 DECLARE_RTL_COND(rtl_phy_reset_cond)
4002 {
4003 return tp->phy_reset_pending(tp);
4004 }
4005
4006 static void rtl8169_phy_reset(struct net_device *dev,
4007 struct rtl8169_private *tp)
4008 {
4009 tp->phy_reset_enable(tp);
4010 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4011 }
4012
4013 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4014 {
4015 void __iomem *ioaddr = tp->mmio_addr;
4016
4017 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4018 (RTL_R8(PHYstatus) & TBI_Enable);
4019 }
4020
4021 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4022 {
4023 void __iomem *ioaddr = tp->mmio_addr;
4024
4025 rtl_hw_phy_config(dev);
4026
4027 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4028 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4029 RTL_W8(0x82, 0x01);
4030 }
4031
4032 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4033
4034 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4035 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4036
4037 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4038 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4039 RTL_W8(0x82, 0x01);
4040 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4041 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4042 }
4043
4044 rtl8169_phy_reset(dev, tp);
4045
4046 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4047 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4048 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4049 (tp->mii.supports_gmii ?
4050 ADVERTISED_1000baseT_Half |
4051 ADVERTISED_1000baseT_Full : 0));
4052
4053 if (rtl_tbi_enabled(tp))
4054 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4055 }
4056
4057 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4058 {
4059 void __iomem *ioaddr = tp->mmio_addr;
4060
4061 rtl_lock_work(tp);
4062
4063 RTL_W8(Cfg9346, Cfg9346_Unlock);
4064
4065 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4066 RTL_R32(MAC4);
4067
4068 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4069 RTL_R32(MAC0);
4070
4071 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4072 rtl_rar_exgmac_set(tp, addr);
4073
4074 RTL_W8(Cfg9346, Cfg9346_Lock);
4075
4076 rtl_unlock_work(tp);
4077 }
4078
4079 static int rtl_set_mac_address(struct net_device *dev, void *p)
4080 {
4081 struct rtl8169_private *tp = netdev_priv(dev);
4082 struct sockaddr *addr = p;
4083
4084 if (!is_valid_ether_addr(addr->sa_data))
4085 return -EADDRNOTAVAIL;
4086
4087 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4088
4089 rtl_rar_set(tp, dev->dev_addr);
4090
4091 return 0;
4092 }
4093
4094 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4095 {
4096 struct rtl8169_private *tp = netdev_priv(dev);
4097 struct mii_ioctl_data *data = if_mii(ifr);
4098
4099 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4100 }
4101
4102 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4103 struct mii_ioctl_data *data, int cmd)
4104 {
4105 switch (cmd) {
4106 case SIOCGMIIPHY:
4107 data->phy_id = 32; /* Internal PHY */
4108 return 0;
4109
4110 case SIOCGMIIREG:
4111 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4112 return 0;
4113
4114 case SIOCSMIIREG:
4115 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4116 return 0;
4117 }
4118 return -EOPNOTSUPP;
4119 }
4120
4121 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4122 {
4123 return -EOPNOTSUPP;
4124 }
4125
4126 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4127 {
4128 if (tp->features & RTL_FEATURE_MSI) {
4129 pci_disable_msi(pdev);
4130 tp->features &= ~RTL_FEATURE_MSI;
4131 }
4132 }
4133
4134 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4135 {
4136 struct mdio_ops *ops = &tp->mdio_ops;
4137
4138 switch (tp->mac_version) {
4139 case RTL_GIGA_MAC_VER_27:
4140 ops->write = r8168dp_1_mdio_write;
4141 ops->read = r8168dp_1_mdio_read;
4142 break;
4143 case RTL_GIGA_MAC_VER_28:
4144 case RTL_GIGA_MAC_VER_31:
4145 ops->write = r8168dp_2_mdio_write;
4146 ops->read = r8168dp_2_mdio_read;
4147 break;
4148 case RTL_GIGA_MAC_VER_40:
4149 case RTL_GIGA_MAC_VER_41:
4150 case RTL_GIGA_MAC_VER_42:
4151 case RTL_GIGA_MAC_VER_43:
4152 case RTL_GIGA_MAC_VER_44:
4153 case RTL_GIGA_MAC_VER_45:
4154 case RTL_GIGA_MAC_VER_46:
4155 case RTL_GIGA_MAC_VER_47:
4156 case RTL_GIGA_MAC_VER_48:
4157 ops->write = r8168g_mdio_write;
4158 ops->read = r8168g_mdio_read;
4159 break;
4160 default:
4161 ops->write = r8169_mdio_write;
4162 ops->read = r8169_mdio_read;
4163 break;
4164 }
4165 }
4166
4167 static void rtl_speed_down(struct rtl8169_private *tp)
4168 {
4169 u32 adv;
4170 int lpa;
4171
4172 rtl_writephy(tp, 0x1f, 0x0000);
4173 lpa = rtl_readphy(tp, MII_LPA);
4174
4175 if (lpa & (LPA_10HALF | LPA_10FULL))
4176 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4177 else if (lpa & (LPA_100HALF | LPA_100FULL))
4178 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4179 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4180 else
4181 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4182 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4183 (tp->mii.supports_gmii ?
4184 ADVERTISED_1000baseT_Half |
4185 ADVERTISED_1000baseT_Full : 0);
4186
4187 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4188 adv);
4189 }
4190
4191 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4192 {
4193 void __iomem *ioaddr = tp->mmio_addr;
4194
4195 switch (tp->mac_version) {
4196 case RTL_GIGA_MAC_VER_25:
4197 case RTL_GIGA_MAC_VER_26:
4198 case RTL_GIGA_MAC_VER_29:
4199 case RTL_GIGA_MAC_VER_30:
4200 case RTL_GIGA_MAC_VER_32:
4201 case RTL_GIGA_MAC_VER_33:
4202 case RTL_GIGA_MAC_VER_34:
4203 case RTL_GIGA_MAC_VER_37:
4204 case RTL_GIGA_MAC_VER_38:
4205 case RTL_GIGA_MAC_VER_39:
4206 case RTL_GIGA_MAC_VER_40:
4207 case RTL_GIGA_MAC_VER_41:
4208 case RTL_GIGA_MAC_VER_42:
4209 case RTL_GIGA_MAC_VER_43:
4210 case RTL_GIGA_MAC_VER_44:
4211 case RTL_GIGA_MAC_VER_45:
4212 case RTL_GIGA_MAC_VER_46:
4213 case RTL_GIGA_MAC_VER_47:
4214 case RTL_GIGA_MAC_VER_48:
4215 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4216 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4217 break;
4218 default:
4219 break;
4220 }
4221 }
4222
4223 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4224 {
4225 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4226 return false;
4227
4228 rtl_speed_down(tp);
4229 rtl_wol_suspend_quirk(tp);
4230
4231 return true;
4232 }
4233
4234 static void r810x_phy_power_down(struct rtl8169_private *tp)
4235 {
4236 rtl_writephy(tp, 0x1f, 0x0000);
4237 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4238 }
4239
4240 static void r810x_phy_power_up(struct rtl8169_private *tp)
4241 {
4242 rtl_writephy(tp, 0x1f, 0x0000);
4243 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4244 }
4245
4246 static void r810x_pll_power_down(struct rtl8169_private *tp)
4247 {
4248 void __iomem *ioaddr = tp->mmio_addr;
4249
4250 if (rtl_wol_pll_power_down(tp))
4251 return;
4252
4253 r810x_phy_power_down(tp);
4254
4255 switch (tp->mac_version) {
4256 case RTL_GIGA_MAC_VER_07:
4257 case RTL_GIGA_MAC_VER_08:
4258 case RTL_GIGA_MAC_VER_09:
4259 case RTL_GIGA_MAC_VER_10:
4260 case RTL_GIGA_MAC_VER_13:
4261 case RTL_GIGA_MAC_VER_16:
4262 break;
4263 default:
4264 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4265 break;
4266 }
4267 }
4268
4269 static void r810x_pll_power_up(struct rtl8169_private *tp)
4270 {
4271 void __iomem *ioaddr = tp->mmio_addr;
4272
4273 r810x_phy_power_up(tp);
4274
4275 switch (tp->mac_version) {
4276 case RTL_GIGA_MAC_VER_07:
4277 case RTL_GIGA_MAC_VER_08:
4278 case RTL_GIGA_MAC_VER_09:
4279 case RTL_GIGA_MAC_VER_10:
4280 case RTL_GIGA_MAC_VER_13:
4281 case RTL_GIGA_MAC_VER_16:
4282 break;
4283 case RTL_GIGA_MAC_VER_47:
4284 case RTL_GIGA_MAC_VER_48:
4285 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4286 break;
4287 default:
4288 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4289 break;
4290 }
4291 }
4292
4293 static void r8168_phy_power_up(struct rtl8169_private *tp)
4294 {
4295 rtl_writephy(tp, 0x1f, 0x0000);
4296 switch (tp->mac_version) {
4297 case RTL_GIGA_MAC_VER_11:
4298 case RTL_GIGA_MAC_VER_12:
4299 case RTL_GIGA_MAC_VER_17:
4300 case RTL_GIGA_MAC_VER_18:
4301 case RTL_GIGA_MAC_VER_19:
4302 case RTL_GIGA_MAC_VER_20:
4303 case RTL_GIGA_MAC_VER_21:
4304 case RTL_GIGA_MAC_VER_22:
4305 case RTL_GIGA_MAC_VER_23:
4306 case RTL_GIGA_MAC_VER_24:
4307 case RTL_GIGA_MAC_VER_25:
4308 case RTL_GIGA_MAC_VER_26:
4309 case RTL_GIGA_MAC_VER_27:
4310 case RTL_GIGA_MAC_VER_28:
4311 case RTL_GIGA_MAC_VER_31:
4312 rtl_writephy(tp, 0x0e, 0x0000);
4313 break;
4314 default:
4315 break;
4316 }
4317 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4318 }
4319
4320 static void r8168_phy_power_down(struct rtl8169_private *tp)
4321 {
4322 rtl_writephy(tp, 0x1f, 0x0000);
4323 switch (tp->mac_version) {
4324 case RTL_GIGA_MAC_VER_32:
4325 case RTL_GIGA_MAC_VER_33:
4326 case RTL_GIGA_MAC_VER_40:
4327 case RTL_GIGA_MAC_VER_41:
4328 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4329 break;
4330
4331 case RTL_GIGA_MAC_VER_11:
4332 case RTL_GIGA_MAC_VER_12:
4333 case RTL_GIGA_MAC_VER_17:
4334 case RTL_GIGA_MAC_VER_18:
4335 case RTL_GIGA_MAC_VER_19:
4336 case RTL_GIGA_MAC_VER_20:
4337 case RTL_GIGA_MAC_VER_21:
4338 case RTL_GIGA_MAC_VER_22:
4339 case RTL_GIGA_MAC_VER_23:
4340 case RTL_GIGA_MAC_VER_24:
4341 case RTL_GIGA_MAC_VER_25:
4342 case RTL_GIGA_MAC_VER_26:
4343 case RTL_GIGA_MAC_VER_27:
4344 case RTL_GIGA_MAC_VER_28:
4345 case RTL_GIGA_MAC_VER_31:
4346 rtl_writephy(tp, 0x0e, 0x0200);
4347 default:
4348 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4349 break;
4350 }
4351 }
4352
4353 static void r8168_pll_power_down(struct rtl8169_private *tp)
4354 {
4355 void __iomem *ioaddr = tp->mmio_addr;
4356
4357 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4358 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4359 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4360 r8168_check_dash(tp)) {
4361 return;
4362 }
4363
4364 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4365 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4366 (RTL_R16(CPlusCmd) & ASF)) {
4367 return;
4368 }
4369
4370 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4371 tp->mac_version == RTL_GIGA_MAC_VER_33)
4372 rtl_ephy_write(tp, 0x19, 0xff64);
4373
4374 if (rtl_wol_pll_power_down(tp))
4375 return;
4376
4377 r8168_phy_power_down(tp);
4378
4379 switch (tp->mac_version) {
4380 case RTL_GIGA_MAC_VER_25:
4381 case RTL_GIGA_MAC_VER_26:
4382 case RTL_GIGA_MAC_VER_27:
4383 case RTL_GIGA_MAC_VER_28:
4384 case RTL_GIGA_MAC_VER_31:
4385 case RTL_GIGA_MAC_VER_32:
4386 case RTL_GIGA_MAC_VER_33:
4387 case RTL_GIGA_MAC_VER_44:
4388 case RTL_GIGA_MAC_VER_45:
4389 case RTL_GIGA_MAC_VER_46:
4390 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4391 break;
4392 case RTL_GIGA_MAC_VER_40:
4393 case RTL_GIGA_MAC_VER_41:
4394 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4395 0xfc000000, ERIAR_EXGMAC);
4396 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4397 break;
4398 }
4399 }
4400
4401 static void r8168_pll_power_up(struct rtl8169_private *tp)
4402 {
4403 void __iomem *ioaddr = tp->mmio_addr;
4404
4405 switch (tp->mac_version) {
4406 case RTL_GIGA_MAC_VER_25:
4407 case RTL_GIGA_MAC_VER_26:
4408 case RTL_GIGA_MAC_VER_27:
4409 case RTL_GIGA_MAC_VER_28:
4410 case RTL_GIGA_MAC_VER_31:
4411 case RTL_GIGA_MAC_VER_32:
4412 case RTL_GIGA_MAC_VER_33:
4413 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4414 break;
4415 case RTL_GIGA_MAC_VER_44:
4416 case RTL_GIGA_MAC_VER_45:
4417 case RTL_GIGA_MAC_VER_46:
4418 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4419 break;
4420 case RTL_GIGA_MAC_VER_40:
4421 case RTL_GIGA_MAC_VER_41:
4422 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4423 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4424 0x00000000, ERIAR_EXGMAC);
4425 break;
4426 }
4427
4428 r8168_phy_power_up(tp);
4429 }
4430
4431 static void rtl_generic_op(struct rtl8169_private *tp,
4432 void (*op)(struct rtl8169_private *))
4433 {
4434 if (op)
4435 op(tp);
4436 }
4437
4438 static void rtl_pll_power_down(struct rtl8169_private *tp)
4439 {
4440 rtl_generic_op(tp, tp->pll_power_ops.down);
4441 }
4442
4443 static void rtl_pll_power_up(struct rtl8169_private *tp)
4444 {
4445 rtl_generic_op(tp, tp->pll_power_ops.up);
4446 }
4447
4448 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4449 {
4450 struct pll_power_ops *ops = &tp->pll_power_ops;
4451
4452 switch (tp->mac_version) {
4453 case RTL_GIGA_MAC_VER_07:
4454 case RTL_GIGA_MAC_VER_08:
4455 case RTL_GIGA_MAC_VER_09:
4456 case RTL_GIGA_MAC_VER_10:
4457 case RTL_GIGA_MAC_VER_16:
4458 case RTL_GIGA_MAC_VER_29:
4459 case RTL_GIGA_MAC_VER_30:
4460 case RTL_GIGA_MAC_VER_37:
4461 case RTL_GIGA_MAC_VER_39:
4462 case RTL_GIGA_MAC_VER_43:
4463 case RTL_GIGA_MAC_VER_47:
4464 case RTL_GIGA_MAC_VER_48:
4465 ops->down = r810x_pll_power_down;
4466 ops->up = r810x_pll_power_up;
4467 break;
4468
4469 case RTL_GIGA_MAC_VER_11:
4470 case RTL_GIGA_MAC_VER_12:
4471 case RTL_GIGA_MAC_VER_17:
4472 case RTL_GIGA_MAC_VER_18:
4473 case RTL_GIGA_MAC_VER_19:
4474 case RTL_GIGA_MAC_VER_20:
4475 case RTL_GIGA_MAC_VER_21:
4476 case RTL_GIGA_MAC_VER_22:
4477 case RTL_GIGA_MAC_VER_23:
4478 case RTL_GIGA_MAC_VER_24:
4479 case RTL_GIGA_MAC_VER_25:
4480 case RTL_GIGA_MAC_VER_26:
4481 case RTL_GIGA_MAC_VER_27:
4482 case RTL_GIGA_MAC_VER_28:
4483 case RTL_GIGA_MAC_VER_31:
4484 case RTL_GIGA_MAC_VER_32:
4485 case RTL_GIGA_MAC_VER_33:
4486 case RTL_GIGA_MAC_VER_34:
4487 case RTL_GIGA_MAC_VER_35:
4488 case RTL_GIGA_MAC_VER_36:
4489 case RTL_GIGA_MAC_VER_38:
4490 case RTL_GIGA_MAC_VER_40:
4491 case RTL_GIGA_MAC_VER_41:
4492 case RTL_GIGA_MAC_VER_42:
4493 case RTL_GIGA_MAC_VER_44:
4494 case RTL_GIGA_MAC_VER_45:
4495 case RTL_GIGA_MAC_VER_46:
4496 ops->down = r8168_pll_power_down;
4497 ops->up = r8168_pll_power_up;
4498 break;
4499
4500 default:
4501 ops->down = NULL;
4502 ops->up = NULL;
4503 break;
4504 }
4505 }
4506
4507 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4508 {
4509 void __iomem *ioaddr = tp->mmio_addr;
4510
4511 switch (tp->mac_version) {
4512 case RTL_GIGA_MAC_VER_01:
4513 case RTL_GIGA_MAC_VER_02:
4514 case RTL_GIGA_MAC_VER_03:
4515 case RTL_GIGA_MAC_VER_04:
4516 case RTL_GIGA_MAC_VER_05:
4517 case RTL_GIGA_MAC_VER_06:
4518 case RTL_GIGA_MAC_VER_10:
4519 case RTL_GIGA_MAC_VER_11:
4520 case RTL_GIGA_MAC_VER_12:
4521 case RTL_GIGA_MAC_VER_13:
4522 case RTL_GIGA_MAC_VER_14:
4523 case RTL_GIGA_MAC_VER_15:
4524 case RTL_GIGA_MAC_VER_16:
4525 case RTL_GIGA_MAC_VER_17:
4526 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4527 break;
4528 case RTL_GIGA_MAC_VER_18:
4529 case RTL_GIGA_MAC_VER_19:
4530 case RTL_GIGA_MAC_VER_20:
4531 case RTL_GIGA_MAC_VER_21:
4532 case RTL_GIGA_MAC_VER_22:
4533 case RTL_GIGA_MAC_VER_23:
4534 case RTL_GIGA_MAC_VER_24:
4535 case RTL_GIGA_MAC_VER_34:
4536 case RTL_GIGA_MAC_VER_35:
4537 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4538 break;
4539 case RTL_GIGA_MAC_VER_40:
4540 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4541 break;
4542 case RTL_GIGA_MAC_VER_41:
4543 case RTL_GIGA_MAC_VER_42:
4544 case RTL_GIGA_MAC_VER_43:
4545 case RTL_GIGA_MAC_VER_44:
4546 case RTL_GIGA_MAC_VER_45:
4547 case RTL_GIGA_MAC_VER_46:
4548 case RTL_GIGA_MAC_VER_47:
4549 case RTL_GIGA_MAC_VER_48:
4550 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4551 break;
4552 default:
4553 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4554 break;
4555 }
4556 }
4557
4558 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4559 {
4560 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4561 }
4562
4563 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4564 {
4565 void __iomem *ioaddr = tp->mmio_addr;
4566
4567 RTL_W8(Cfg9346, Cfg9346_Unlock);
4568 rtl_generic_op(tp, tp->jumbo_ops.enable);
4569 RTL_W8(Cfg9346, Cfg9346_Lock);
4570 }
4571
4572 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4573 {
4574 void __iomem *ioaddr = tp->mmio_addr;
4575
4576 RTL_W8(Cfg9346, Cfg9346_Unlock);
4577 rtl_generic_op(tp, tp->jumbo_ops.disable);
4578 RTL_W8(Cfg9346, Cfg9346_Lock);
4579 }
4580
4581 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4582 {
4583 void __iomem *ioaddr = tp->mmio_addr;
4584
4585 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4586 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4587 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4588 }
4589
4590 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4591 {
4592 void __iomem *ioaddr = tp->mmio_addr;
4593
4594 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4595 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4596 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4597 }
4598
4599 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4600 {
4601 void __iomem *ioaddr = tp->mmio_addr;
4602
4603 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4604 }
4605
4606 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4607 {
4608 void __iomem *ioaddr = tp->mmio_addr;
4609
4610 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4611 }
4612
4613 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4614 {
4615 void __iomem *ioaddr = tp->mmio_addr;
4616
4617 RTL_W8(MaxTxPacketSize, 0x3f);
4618 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4619 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4620 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4621 }
4622
4623 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4624 {
4625 void __iomem *ioaddr = tp->mmio_addr;
4626
4627 RTL_W8(MaxTxPacketSize, 0x0c);
4628 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4629 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4630 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4631 }
4632
4633 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4634 {
4635 rtl_tx_performance_tweak(tp->pci_dev,
4636 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4637 }
4638
4639 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4640 {
4641 rtl_tx_performance_tweak(tp->pci_dev,
4642 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4643 }
4644
4645 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4646 {
4647 void __iomem *ioaddr = tp->mmio_addr;
4648
4649 r8168b_0_hw_jumbo_enable(tp);
4650
4651 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4652 }
4653
4654 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4655 {
4656 void __iomem *ioaddr = tp->mmio_addr;
4657
4658 r8168b_0_hw_jumbo_disable(tp);
4659
4660 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4661 }
4662
4663 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4664 {
4665 struct jumbo_ops *ops = &tp->jumbo_ops;
4666
4667 switch (tp->mac_version) {
4668 case RTL_GIGA_MAC_VER_11:
4669 ops->disable = r8168b_0_hw_jumbo_disable;
4670 ops->enable = r8168b_0_hw_jumbo_enable;
4671 break;
4672 case RTL_GIGA_MAC_VER_12:
4673 case RTL_GIGA_MAC_VER_17:
4674 ops->disable = r8168b_1_hw_jumbo_disable;
4675 ops->enable = r8168b_1_hw_jumbo_enable;
4676 break;
4677 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4678 case RTL_GIGA_MAC_VER_19:
4679 case RTL_GIGA_MAC_VER_20:
4680 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4681 case RTL_GIGA_MAC_VER_22:
4682 case RTL_GIGA_MAC_VER_23:
4683 case RTL_GIGA_MAC_VER_24:
4684 case RTL_GIGA_MAC_VER_25:
4685 case RTL_GIGA_MAC_VER_26:
4686 ops->disable = r8168c_hw_jumbo_disable;
4687 ops->enable = r8168c_hw_jumbo_enable;
4688 break;
4689 case RTL_GIGA_MAC_VER_27:
4690 case RTL_GIGA_MAC_VER_28:
4691 ops->disable = r8168dp_hw_jumbo_disable;
4692 ops->enable = r8168dp_hw_jumbo_enable;
4693 break;
4694 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4695 case RTL_GIGA_MAC_VER_32:
4696 case RTL_GIGA_MAC_VER_33:
4697 case RTL_GIGA_MAC_VER_34:
4698 ops->disable = r8168e_hw_jumbo_disable;
4699 ops->enable = r8168e_hw_jumbo_enable;
4700 break;
4701
4702 /*
4703 * No action needed for jumbo frames with 8169.
4704 * No jumbo for 810x at all.
4705 */
4706 case RTL_GIGA_MAC_VER_40:
4707 case RTL_GIGA_MAC_VER_41:
4708 case RTL_GIGA_MAC_VER_42:
4709 case RTL_GIGA_MAC_VER_43:
4710 case RTL_GIGA_MAC_VER_44:
4711 case RTL_GIGA_MAC_VER_45:
4712 case RTL_GIGA_MAC_VER_46:
4713 case RTL_GIGA_MAC_VER_47:
4714 case RTL_GIGA_MAC_VER_48:
4715 default:
4716 ops->disable = NULL;
4717 ops->enable = NULL;
4718 break;
4719 }
4720 }
4721
4722 DECLARE_RTL_COND(rtl_chipcmd_cond)
4723 {
4724 void __iomem *ioaddr = tp->mmio_addr;
4725
4726 return RTL_R8(ChipCmd) & CmdReset;
4727 }
4728
4729 static void rtl_hw_reset(struct rtl8169_private *tp)
4730 {
4731 void __iomem *ioaddr = tp->mmio_addr;
4732
4733 RTL_W8(ChipCmd, CmdReset);
4734
4735 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4736 }
4737
4738 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4739 {
4740 struct rtl_fw *rtl_fw;
4741 const char *name;
4742 int rc = -ENOMEM;
4743
4744 name = rtl_lookup_firmware_name(tp);
4745 if (!name)
4746 goto out_no_firmware;
4747
4748 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4749 if (!rtl_fw)
4750 goto err_warn;
4751
4752 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4753 if (rc < 0)
4754 goto err_free;
4755
4756 rc = rtl_check_firmware(tp, rtl_fw);
4757 if (rc < 0)
4758 goto err_release_firmware;
4759
4760 tp->rtl_fw = rtl_fw;
4761 out:
4762 return;
4763
4764 err_release_firmware:
4765 release_firmware(rtl_fw->fw);
4766 err_free:
4767 kfree(rtl_fw);
4768 err_warn:
4769 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4770 name, rc);
4771 out_no_firmware:
4772 tp->rtl_fw = NULL;
4773 goto out;
4774 }
4775
4776 static void rtl_request_firmware(struct rtl8169_private *tp)
4777 {
4778 if (IS_ERR(tp->rtl_fw))
4779 rtl_request_uncached_firmware(tp);
4780 }
4781
4782 static void rtl_rx_close(struct rtl8169_private *tp)
4783 {
4784 void __iomem *ioaddr = tp->mmio_addr;
4785
4786 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4787 }
4788
4789 DECLARE_RTL_COND(rtl_npq_cond)
4790 {
4791 void __iomem *ioaddr = tp->mmio_addr;
4792
4793 return RTL_R8(TxPoll) & NPQ;
4794 }
4795
4796 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4797 {
4798 void __iomem *ioaddr = tp->mmio_addr;
4799
4800 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4801 }
4802
4803 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4804 {
4805 void __iomem *ioaddr = tp->mmio_addr;
4806
4807 /* Disable interrupts */
4808 rtl8169_irq_mask_and_ack(tp);
4809
4810 rtl_rx_close(tp);
4811
4812 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4813 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4814 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4815 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4816 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4817 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4818 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4819 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4820 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
4821 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4822 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4823 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4824 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4825 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4826 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
4827 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
4828 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
4829 tp->mac_version == RTL_GIGA_MAC_VER_48) {
4830 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4831 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4832 } else {
4833 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4834 udelay(100);
4835 }
4836
4837 rtl_hw_reset(tp);
4838 }
4839
4840 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4841 {
4842 void __iomem *ioaddr = tp->mmio_addr;
4843
4844 /* Set DMA burst size and Interframe Gap Time */
4845 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4846 (InterFrameGap << TxInterFrameGapShift));
4847 }
4848
4849 static void rtl_hw_start(struct net_device *dev)
4850 {
4851 struct rtl8169_private *tp = netdev_priv(dev);
4852
4853 tp->hw_start(dev);
4854
4855 rtl_irq_enable_all(tp);
4856 }
4857
4858 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4859 void __iomem *ioaddr)
4860 {
4861 /*
4862 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4863 * register to be written before TxDescAddrLow to work.
4864 * Switching from MMIO to I/O access fixes the issue as well.
4865 */
4866 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4867 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4868 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4869 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4870 }
4871
4872 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4873 {
4874 u16 cmd;
4875
4876 cmd = RTL_R16(CPlusCmd);
4877 RTL_W16(CPlusCmd, cmd);
4878 return cmd;
4879 }
4880
4881 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4882 {
4883 /* Low hurts. Let's disable the filtering. */
4884 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4885 }
4886
4887 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4888 {
4889 static const struct rtl_cfg2_info {
4890 u32 mac_version;
4891 u32 clk;
4892 u32 val;
4893 } cfg2_info [] = {
4894 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4895 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4896 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4897 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4898 };
4899 const struct rtl_cfg2_info *p = cfg2_info;
4900 unsigned int i;
4901 u32 clk;
4902
4903 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4904 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4905 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4906 RTL_W32(0x7c, p->val);
4907 break;
4908 }
4909 }
4910 }
4911
4912 static void rtl_set_rx_mode(struct net_device *dev)
4913 {
4914 struct rtl8169_private *tp = netdev_priv(dev);
4915 void __iomem *ioaddr = tp->mmio_addr;
4916 u32 mc_filter[2]; /* Multicast hash filter */
4917 int rx_mode;
4918 u32 tmp = 0;
4919
4920 if (dev->flags & IFF_PROMISC) {
4921 /* Unconditionally log net taps. */
4922 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4923 rx_mode =
4924 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4925 AcceptAllPhys;
4926 mc_filter[1] = mc_filter[0] = 0xffffffff;
4927 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4928 (dev->flags & IFF_ALLMULTI)) {
4929 /* Too many to filter perfectly -- accept all multicasts. */
4930 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4931 mc_filter[1] = mc_filter[0] = 0xffffffff;
4932 } else {
4933 struct netdev_hw_addr *ha;
4934
4935 rx_mode = AcceptBroadcast | AcceptMyPhys;
4936 mc_filter[1] = mc_filter[0] = 0;
4937 netdev_for_each_mc_addr(ha, dev) {
4938 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4939 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4940 rx_mode |= AcceptMulticast;
4941 }
4942 }
4943
4944 if (dev->features & NETIF_F_RXALL)
4945 rx_mode |= (AcceptErr | AcceptRunt);
4946
4947 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4948
4949 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4950 u32 data = mc_filter[0];
4951
4952 mc_filter[0] = swab32(mc_filter[1]);
4953 mc_filter[1] = swab32(data);
4954 }
4955
4956 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4957 mc_filter[1] = mc_filter[0] = 0xffffffff;
4958
4959 RTL_W32(MAR0 + 4, mc_filter[1]);
4960 RTL_W32(MAR0 + 0, mc_filter[0]);
4961
4962 RTL_W32(RxConfig, tmp);
4963 }
4964
4965 static void rtl_hw_start_8169(struct net_device *dev)
4966 {
4967 struct rtl8169_private *tp = netdev_priv(dev);
4968 void __iomem *ioaddr = tp->mmio_addr;
4969 struct pci_dev *pdev = tp->pci_dev;
4970
4971 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4972 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4973 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4974 }
4975
4976 RTL_W8(Cfg9346, Cfg9346_Unlock);
4977 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4978 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4979 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4980 tp->mac_version == RTL_GIGA_MAC_VER_04)
4981 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4982
4983 rtl_init_rxcfg(tp);
4984
4985 RTL_W8(EarlyTxThres, NoEarlyTx);
4986
4987 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4988
4989 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4990 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4991 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4992 tp->mac_version == RTL_GIGA_MAC_VER_04)
4993 rtl_set_rx_tx_config_registers(tp);
4994
4995 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4996
4997 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4998 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4999 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5000 "Bit-3 and bit-14 MUST be 1\n");
5001 tp->cp_cmd |= (1 << 14);
5002 }
5003
5004 RTL_W16(CPlusCmd, tp->cp_cmd);
5005
5006 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5007
5008 /*
5009 * Undocumented corner. Supposedly:
5010 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5011 */
5012 RTL_W16(IntrMitigate, 0x0000);
5013
5014 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5015
5016 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5017 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5018 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5019 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5020 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5021 rtl_set_rx_tx_config_registers(tp);
5022 }
5023
5024 RTL_W8(Cfg9346, Cfg9346_Lock);
5025
5026 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5027 RTL_R8(IntrMask);
5028
5029 RTL_W32(RxMissed, 0);
5030
5031 rtl_set_rx_mode(dev);
5032
5033 /* no early-rx interrupts */
5034 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5035 }
5036
5037 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5038 {
5039 if (tp->csi_ops.write)
5040 tp->csi_ops.write(tp, addr, value);
5041 }
5042
5043 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5044 {
5045 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5046 }
5047
5048 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5049 {
5050 u32 csi;
5051
5052 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5053 rtl_csi_write(tp, 0x070c, csi | bits);
5054 }
5055
5056 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5057 {
5058 rtl_csi_access_enable(tp, 0x17000000);
5059 }
5060
5061 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5062 {
5063 rtl_csi_access_enable(tp, 0x27000000);
5064 }
5065
5066 DECLARE_RTL_COND(rtl_csiar_cond)
5067 {
5068 void __iomem *ioaddr = tp->mmio_addr;
5069
5070 return RTL_R32(CSIAR) & CSIAR_FLAG;
5071 }
5072
5073 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5074 {
5075 void __iomem *ioaddr = tp->mmio_addr;
5076
5077 RTL_W32(CSIDR, value);
5078 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5079 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5080
5081 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5082 }
5083
5084 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5085 {
5086 void __iomem *ioaddr = tp->mmio_addr;
5087
5088 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5089 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5090
5091 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5092 RTL_R32(CSIDR) : ~0;
5093 }
5094
5095 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5096 {
5097 void __iomem *ioaddr = tp->mmio_addr;
5098
5099 RTL_W32(CSIDR, value);
5100 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5101 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5102 CSIAR_FUNC_NIC);
5103
5104 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5105 }
5106
5107 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5108 {
5109 void __iomem *ioaddr = tp->mmio_addr;
5110
5111 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5112 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5113
5114 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5115 RTL_R32(CSIDR) : ~0;
5116 }
5117
5118 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5119 {
5120 void __iomem *ioaddr = tp->mmio_addr;
5121
5122 RTL_W32(CSIDR, value);
5123 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5124 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5125 CSIAR_FUNC_NIC2);
5126
5127 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5128 }
5129
5130 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5131 {
5132 void __iomem *ioaddr = tp->mmio_addr;
5133
5134 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5135 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5136
5137 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5138 RTL_R32(CSIDR) : ~0;
5139 }
5140
5141 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5142 {
5143 struct csi_ops *ops = &tp->csi_ops;
5144
5145 switch (tp->mac_version) {
5146 case RTL_GIGA_MAC_VER_01:
5147 case RTL_GIGA_MAC_VER_02:
5148 case RTL_GIGA_MAC_VER_03:
5149 case RTL_GIGA_MAC_VER_04:
5150 case RTL_GIGA_MAC_VER_05:
5151 case RTL_GIGA_MAC_VER_06:
5152 case RTL_GIGA_MAC_VER_10:
5153 case RTL_GIGA_MAC_VER_11:
5154 case RTL_GIGA_MAC_VER_12:
5155 case RTL_GIGA_MAC_VER_13:
5156 case RTL_GIGA_MAC_VER_14:
5157 case RTL_GIGA_MAC_VER_15:
5158 case RTL_GIGA_MAC_VER_16:
5159 case RTL_GIGA_MAC_VER_17:
5160 ops->write = NULL;
5161 ops->read = NULL;
5162 break;
5163
5164 case RTL_GIGA_MAC_VER_37:
5165 case RTL_GIGA_MAC_VER_38:
5166 ops->write = r8402_csi_write;
5167 ops->read = r8402_csi_read;
5168 break;
5169
5170 case RTL_GIGA_MAC_VER_44:
5171 ops->write = r8411_csi_write;
5172 ops->read = r8411_csi_read;
5173 break;
5174
5175 default:
5176 ops->write = r8169_csi_write;
5177 ops->read = r8169_csi_read;
5178 break;
5179 }
5180 }
5181
5182 struct ephy_info {
5183 unsigned int offset;
5184 u16 mask;
5185 u16 bits;
5186 };
5187
5188 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5189 int len)
5190 {
5191 u16 w;
5192
5193 while (len-- > 0) {
5194 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5195 rtl_ephy_write(tp, e->offset, w);
5196 e++;
5197 }
5198 }
5199
5200 static void rtl_disable_clock_request(struct pci_dev *pdev)
5201 {
5202 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5203 PCI_EXP_LNKCTL_CLKREQ_EN);
5204 }
5205
5206 static void rtl_enable_clock_request(struct pci_dev *pdev)
5207 {
5208 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5209 PCI_EXP_LNKCTL_CLKREQ_EN);
5210 }
5211
5212 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5213 {
5214 void __iomem *ioaddr = tp->mmio_addr;
5215 u8 data;
5216
5217 data = RTL_R8(Config3);
5218
5219 if (enable)
5220 data |= Rdy_to_L23;
5221 else
5222 data &= ~Rdy_to_L23;
5223
5224 RTL_W8(Config3, data);
5225 }
5226
5227 #define R8168_CPCMD_QUIRK_MASK (\
5228 EnableBist | \
5229 Mac_dbgo_oe | \
5230 Force_half_dup | \
5231 Force_rxflow_en | \
5232 Force_txflow_en | \
5233 Cxpl_dbg_sel | \
5234 ASF | \
5235 PktCntrDisable | \
5236 Mac_dbgo_sel)
5237
5238 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5239 {
5240 void __iomem *ioaddr = tp->mmio_addr;
5241 struct pci_dev *pdev = tp->pci_dev;
5242
5243 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5244
5245 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5246
5247 if (tp->dev->mtu <= ETH_DATA_LEN) {
5248 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5249 PCI_EXP_DEVCTL_NOSNOOP_EN);
5250 }
5251 }
5252
5253 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5254 {
5255 void __iomem *ioaddr = tp->mmio_addr;
5256
5257 rtl_hw_start_8168bb(tp);
5258
5259 RTL_W8(MaxTxPacketSize, TxPacketMax);
5260
5261 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5262 }
5263
5264 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5265 {
5266 void __iomem *ioaddr = tp->mmio_addr;
5267 struct pci_dev *pdev = tp->pci_dev;
5268
5269 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5270
5271 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5272
5273 if (tp->dev->mtu <= ETH_DATA_LEN)
5274 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5275
5276 rtl_disable_clock_request(pdev);
5277
5278 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5279 }
5280
5281 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5282 {
5283 static const struct ephy_info e_info_8168cp[] = {
5284 { 0x01, 0, 0x0001 },
5285 { 0x02, 0x0800, 0x1000 },
5286 { 0x03, 0, 0x0042 },
5287 { 0x06, 0x0080, 0x0000 },
5288 { 0x07, 0, 0x2000 }
5289 };
5290
5291 rtl_csi_access_enable_2(tp);
5292
5293 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5294
5295 __rtl_hw_start_8168cp(tp);
5296 }
5297
5298 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5299 {
5300 void __iomem *ioaddr = tp->mmio_addr;
5301 struct pci_dev *pdev = tp->pci_dev;
5302
5303 rtl_csi_access_enable_2(tp);
5304
5305 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5306
5307 if (tp->dev->mtu <= ETH_DATA_LEN)
5308 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5309
5310 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5311 }
5312
5313 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5314 {
5315 void __iomem *ioaddr = tp->mmio_addr;
5316 struct pci_dev *pdev = tp->pci_dev;
5317
5318 rtl_csi_access_enable_2(tp);
5319
5320 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5321
5322 /* Magic. */
5323 RTL_W8(DBG_REG, 0x20);
5324
5325 RTL_W8(MaxTxPacketSize, TxPacketMax);
5326
5327 if (tp->dev->mtu <= ETH_DATA_LEN)
5328 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5329
5330 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5331 }
5332
5333 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5334 {
5335 void __iomem *ioaddr = tp->mmio_addr;
5336 static const struct ephy_info e_info_8168c_1[] = {
5337 { 0x02, 0x0800, 0x1000 },
5338 { 0x03, 0, 0x0002 },
5339 { 0x06, 0x0080, 0x0000 }
5340 };
5341
5342 rtl_csi_access_enable_2(tp);
5343
5344 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5345
5346 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5347
5348 __rtl_hw_start_8168cp(tp);
5349 }
5350
5351 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5352 {
5353 static const struct ephy_info e_info_8168c_2[] = {
5354 { 0x01, 0, 0x0001 },
5355 { 0x03, 0x0400, 0x0220 }
5356 };
5357
5358 rtl_csi_access_enable_2(tp);
5359
5360 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5361
5362 __rtl_hw_start_8168cp(tp);
5363 }
5364
5365 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5366 {
5367 rtl_hw_start_8168c_2(tp);
5368 }
5369
5370 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5371 {
5372 rtl_csi_access_enable_2(tp);
5373
5374 __rtl_hw_start_8168cp(tp);
5375 }
5376
5377 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5378 {
5379 void __iomem *ioaddr = tp->mmio_addr;
5380 struct pci_dev *pdev = tp->pci_dev;
5381
5382 rtl_csi_access_enable_2(tp);
5383
5384 rtl_disable_clock_request(pdev);
5385
5386 RTL_W8(MaxTxPacketSize, TxPacketMax);
5387
5388 if (tp->dev->mtu <= ETH_DATA_LEN)
5389 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5390
5391 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5392 }
5393
5394 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5395 {
5396 void __iomem *ioaddr = tp->mmio_addr;
5397 struct pci_dev *pdev = tp->pci_dev;
5398
5399 rtl_csi_access_enable_1(tp);
5400
5401 if (tp->dev->mtu <= ETH_DATA_LEN)
5402 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5403
5404 RTL_W8(MaxTxPacketSize, TxPacketMax);
5405
5406 rtl_disable_clock_request(pdev);
5407 }
5408
5409 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5410 {
5411 void __iomem *ioaddr = tp->mmio_addr;
5412 struct pci_dev *pdev = tp->pci_dev;
5413 static const struct ephy_info e_info_8168d_4[] = {
5414 { 0x0b, ~0, 0x48 },
5415 { 0x19, 0x20, 0x50 },
5416 { 0x0c, ~0, 0x20 }
5417 };
5418 int i;
5419
5420 rtl_csi_access_enable_1(tp);
5421
5422 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5423
5424 RTL_W8(MaxTxPacketSize, TxPacketMax);
5425
5426 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5427 const struct ephy_info *e = e_info_8168d_4 + i;
5428 u16 w;
5429
5430 w = rtl_ephy_read(tp, e->offset);
5431 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5432 }
5433
5434 rtl_enable_clock_request(pdev);
5435 }
5436
5437 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5438 {
5439 void __iomem *ioaddr = tp->mmio_addr;
5440 struct pci_dev *pdev = tp->pci_dev;
5441 static const struct ephy_info e_info_8168e_1[] = {
5442 { 0x00, 0x0200, 0x0100 },
5443 { 0x00, 0x0000, 0x0004 },
5444 { 0x06, 0x0002, 0x0001 },
5445 { 0x06, 0x0000, 0x0030 },
5446 { 0x07, 0x0000, 0x2000 },
5447 { 0x00, 0x0000, 0x0020 },
5448 { 0x03, 0x5800, 0x2000 },
5449 { 0x03, 0x0000, 0x0001 },
5450 { 0x01, 0x0800, 0x1000 },
5451 { 0x07, 0x0000, 0x4000 },
5452 { 0x1e, 0x0000, 0x2000 },
5453 { 0x19, 0xffff, 0xfe6c },
5454 { 0x0a, 0x0000, 0x0040 }
5455 };
5456
5457 rtl_csi_access_enable_2(tp);
5458
5459 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5460
5461 if (tp->dev->mtu <= ETH_DATA_LEN)
5462 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5463
5464 RTL_W8(MaxTxPacketSize, TxPacketMax);
5465
5466 rtl_disable_clock_request(pdev);
5467
5468 /* Reset tx FIFO pointer */
5469 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5470 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5471
5472 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5473 }
5474
5475 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5476 {
5477 void __iomem *ioaddr = tp->mmio_addr;
5478 struct pci_dev *pdev = tp->pci_dev;
5479 static const struct ephy_info e_info_8168e_2[] = {
5480 { 0x09, 0x0000, 0x0080 },
5481 { 0x19, 0x0000, 0x0224 }
5482 };
5483
5484 rtl_csi_access_enable_1(tp);
5485
5486 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5487
5488 if (tp->dev->mtu <= ETH_DATA_LEN)
5489 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5490
5491 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5492 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5493 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5494 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5495 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5496 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5497 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5498 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5499
5500 RTL_W8(MaxTxPacketSize, EarlySize);
5501
5502 rtl_disable_clock_request(pdev);
5503
5504 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5505 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5506
5507 /* Adjust EEE LED frequency */
5508 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5509
5510 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5511 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5512 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5513 }
5514
5515 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5516 {
5517 void __iomem *ioaddr = tp->mmio_addr;
5518 struct pci_dev *pdev = tp->pci_dev;
5519
5520 rtl_csi_access_enable_2(tp);
5521
5522 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5523
5524 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5525 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5526 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5527 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5528 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5529 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5530 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5531 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5532 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5533 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5534
5535 RTL_W8(MaxTxPacketSize, EarlySize);
5536
5537 rtl_disable_clock_request(pdev);
5538
5539 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5540 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5541 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5542 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5543 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5544 }
5545
5546 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5547 {
5548 void __iomem *ioaddr = tp->mmio_addr;
5549 static const struct ephy_info e_info_8168f_1[] = {
5550 { 0x06, 0x00c0, 0x0020 },
5551 { 0x08, 0x0001, 0x0002 },
5552 { 0x09, 0x0000, 0x0080 },
5553 { 0x19, 0x0000, 0x0224 }
5554 };
5555
5556 rtl_hw_start_8168f(tp);
5557
5558 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5559
5560 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5561
5562 /* Adjust EEE LED frequency */
5563 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5564 }
5565
5566 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5567 {
5568 static const struct ephy_info e_info_8168f_1[] = {
5569 { 0x06, 0x00c0, 0x0020 },
5570 { 0x0f, 0xffff, 0x5200 },
5571 { 0x1e, 0x0000, 0x4000 },
5572 { 0x19, 0x0000, 0x0224 }
5573 };
5574
5575 rtl_hw_start_8168f(tp);
5576 rtl_pcie_state_l2l3_enable(tp, false);
5577
5578 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5579
5580 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5581 }
5582
5583 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5584 {
5585 void __iomem *ioaddr = tp->mmio_addr;
5586 struct pci_dev *pdev = tp->pci_dev;
5587
5588 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5589
5590 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5591 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5592 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5593 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5594
5595 rtl_csi_access_enable_1(tp);
5596
5597 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5598
5599 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5600 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5601 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5602
5603 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5604 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5605 RTL_W8(MaxTxPacketSize, EarlySize);
5606
5607 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5608 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5609
5610 /* Adjust EEE LED frequency */
5611 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5612
5613 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5614 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5615
5616 rtl_pcie_state_l2l3_enable(tp, false);
5617 }
5618
5619 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5620 {
5621 void __iomem *ioaddr = tp->mmio_addr;
5622 static const struct ephy_info e_info_8168g_2[] = {
5623 { 0x00, 0x0000, 0x0008 },
5624 { 0x0c, 0x3df0, 0x0200 },
5625 { 0x19, 0xffff, 0xfc00 },
5626 { 0x1e, 0xffff, 0x20eb }
5627 };
5628
5629 rtl_hw_start_8168g_1(tp);
5630
5631 /* disable aspm and clock request before access ephy */
5632 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5633 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5634 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5635 }
5636
5637 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5638 {
5639 void __iomem *ioaddr = tp->mmio_addr;
5640 static const struct ephy_info e_info_8411_2[] = {
5641 { 0x00, 0x0000, 0x0008 },
5642 { 0x0c, 0x3df0, 0x0200 },
5643 { 0x0f, 0xffff, 0x5200 },
5644 { 0x19, 0x0020, 0x0000 },
5645 { 0x1e, 0x0000, 0x2000 }
5646 };
5647
5648 rtl_hw_start_8168g_1(tp);
5649
5650 /* disable aspm and clock request before access ephy */
5651 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5652 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5653 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5654 }
5655
5656 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5657 {
5658 void __iomem *ioaddr = tp->mmio_addr;
5659 struct pci_dev *pdev = tp->pci_dev;
5660 u16 rg_saw_cnt;
5661 u32 data;
5662 static const struct ephy_info e_info_8168h_1[] = {
5663 { 0x1e, 0x0800, 0x0001 },
5664 { 0x1d, 0x0000, 0x0800 },
5665 { 0x05, 0xffff, 0x2089 },
5666 { 0x06, 0xffff, 0x5881 },
5667 { 0x04, 0xffff, 0x154a },
5668 { 0x01, 0xffff, 0x068b }
5669 };
5670
5671 /* disable aspm and clock request before access ephy */
5672 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5673 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5674 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5675
5676 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5677
5678 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5679 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5680 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5681 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5682
5683 rtl_csi_access_enable_1(tp);
5684
5685 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5686
5687 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5688 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5689
5690 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5691
5692 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5693
5694 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5695
5696 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5697 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5698 RTL_W8(MaxTxPacketSize, EarlySize);
5699
5700 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5701 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5702
5703 /* Adjust EEE LED frequency */
5704 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5705
5706 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5707 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
5708
5709 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
5710
5711 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5712
5713 rtl_pcie_state_l2l3_enable(tp, false);
5714
5715 rtl_writephy(tp, 0x1f, 0x0c42);
5716 rg_saw_cnt = rtl_readphy(tp, 0x13);
5717 rtl_writephy(tp, 0x1f, 0x0000);
5718 if (rg_saw_cnt > 0) {
5719 u16 sw_cnt_1ms_ini;
5720
5721 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5722 sw_cnt_1ms_ini &= 0x0fff;
5723 data = r8168_mac_ocp_read(tp, 0xd412);
5724 data &= 0x0fff;
5725 data |= sw_cnt_1ms_ini;
5726 r8168_mac_ocp_write(tp, 0xd412, data);
5727 }
5728
5729 data = r8168_mac_ocp_read(tp, 0xe056);
5730 data &= 0xf0;
5731 data |= 0x07;
5732 r8168_mac_ocp_write(tp, 0xe056, data);
5733
5734 data = r8168_mac_ocp_read(tp, 0xe052);
5735 data &= 0x8008;
5736 data |= 0x6000;
5737 r8168_mac_ocp_write(tp, 0xe052, data);
5738
5739 data = r8168_mac_ocp_read(tp, 0xe0d6);
5740 data &= 0x01ff;
5741 data |= 0x017f;
5742 r8168_mac_ocp_write(tp, 0xe0d6, data);
5743
5744 data = r8168_mac_ocp_read(tp, 0xd420);
5745 data &= 0x0fff;
5746 data |= 0x047f;
5747 r8168_mac_ocp_write(tp, 0xd420, data);
5748
5749 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5750 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5751 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5752 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5753 }
5754
5755 static void rtl_hw_start_8168(struct net_device *dev)
5756 {
5757 struct rtl8169_private *tp = netdev_priv(dev);
5758 void __iomem *ioaddr = tp->mmio_addr;
5759
5760 RTL_W8(Cfg9346, Cfg9346_Unlock);
5761
5762 RTL_W8(MaxTxPacketSize, TxPacketMax);
5763
5764 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5765
5766 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5767
5768 RTL_W16(CPlusCmd, tp->cp_cmd);
5769
5770 RTL_W16(IntrMitigate, 0x5151);
5771
5772 /* Work around for RxFIFO overflow. */
5773 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5774 tp->event_slow |= RxFIFOOver | PCSTimeout;
5775 tp->event_slow &= ~RxOverflow;
5776 }
5777
5778 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5779
5780 rtl_set_rx_tx_config_registers(tp);
5781
5782 RTL_R8(IntrMask);
5783
5784 switch (tp->mac_version) {
5785 case RTL_GIGA_MAC_VER_11:
5786 rtl_hw_start_8168bb(tp);
5787 break;
5788
5789 case RTL_GIGA_MAC_VER_12:
5790 case RTL_GIGA_MAC_VER_17:
5791 rtl_hw_start_8168bef(tp);
5792 break;
5793
5794 case RTL_GIGA_MAC_VER_18:
5795 rtl_hw_start_8168cp_1(tp);
5796 break;
5797
5798 case RTL_GIGA_MAC_VER_19:
5799 rtl_hw_start_8168c_1(tp);
5800 break;
5801
5802 case RTL_GIGA_MAC_VER_20:
5803 rtl_hw_start_8168c_2(tp);
5804 break;
5805
5806 case RTL_GIGA_MAC_VER_21:
5807 rtl_hw_start_8168c_3(tp);
5808 break;
5809
5810 case RTL_GIGA_MAC_VER_22:
5811 rtl_hw_start_8168c_4(tp);
5812 break;
5813
5814 case RTL_GIGA_MAC_VER_23:
5815 rtl_hw_start_8168cp_2(tp);
5816 break;
5817
5818 case RTL_GIGA_MAC_VER_24:
5819 rtl_hw_start_8168cp_3(tp);
5820 break;
5821
5822 case RTL_GIGA_MAC_VER_25:
5823 case RTL_GIGA_MAC_VER_26:
5824 case RTL_GIGA_MAC_VER_27:
5825 rtl_hw_start_8168d(tp);
5826 break;
5827
5828 case RTL_GIGA_MAC_VER_28:
5829 rtl_hw_start_8168d_4(tp);
5830 break;
5831
5832 case RTL_GIGA_MAC_VER_31:
5833 rtl_hw_start_8168dp(tp);
5834 break;
5835
5836 case RTL_GIGA_MAC_VER_32:
5837 case RTL_GIGA_MAC_VER_33:
5838 rtl_hw_start_8168e_1(tp);
5839 break;
5840 case RTL_GIGA_MAC_VER_34:
5841 rtl_hw_start_8168e_2(tp);
5842 break;
5843
5844 case RTL_GIGA_MAC_VER_35:
5845 case RTL_GIGA_MAC_VER_36:
5846 rtl_hw_start_8168f_1(tp);
5847 break;
5848
5849 case RTL_GIGA_MAC_VER_38:
5850 rtl_hw_start_8411(tp);
5851 break;
5852
5853 case RTL_GIGA_MAC_VER_40:
5854 case RTL_GIGA_MAC_VER_41:
5855 rtl_hw_start_8168g_1(tp);
5856 break;
5857 case RTL_GIGA_MAC_VER_42:
5858 rtl_hw_start_8168g_2(tp);
5859 break;
5860
5861 case RTL_GIGA_MAC_VER_44:
5862 rtl_hw_start_8411_2(tp);
5863 break;
5864
5865 case RTL_GIGA_MAC_VER_45:
5866 case RTL_GIGA_MAC_VER_46:
5867 rtl_hw_start_8168h_1(tp);
5868 break;
5869
5870 default:
5871 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5872 dev->name, tp->mac_version);
5873 break;
5874 }
5875
5876 RTL_W8(Cfg9346, Cfg9346_Lock);
5877
5878 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5879
5880 rtl_set_rx_mode(dev);
5881
5882 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5883 }
5884
5885 #define R810X_CPCMD_QUIRK_MASK (\
5886 EnableBist | \
5887 Mac_dbgo_oe | \
5888 Force_half_dup | \
5889 Force_rxflow_en | \
5890 Force_txflow_en | \
5891 Cxpl_dbg_sel | \
5892 ASF | \
5893 PktCntrDisable | \
5894 Mac_dbgo_sel)
5895
5896 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5897 {
5898 void __iomem *ioaddr = tp->mmio_addr;
5899 struct pci_dev *pdev = tp->pci_dev;
5900 static const struct ephy_info e_info_8102e_1[] = {
5901 { 0x01, 0, 0x6e65 },
5902 { 0x02, 0, 0x091f },
5903 { 0x03, 0, 0xc2f9 },
5904 { 0x06, 0, 0xafb5 },
5905 { 0x07, 0, 0x0e00 },
5906 { 0x19, 0, 0xec80 },
5907 { 0x01, 0, 0x2e65 },
5908 { 0x01, 0, 0x6e65 }
5909 };
5910 u8 cfg1;
5911
5912 rtl_csi_access_enable_2(tp);
5913
5914 RTL_W8(DBG_REG, FIX_NAK_1);
5915
5916 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5917
5918 RTL_W8(Config1,
5919 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5920 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5921
5922 cfg1 = RTL_R8(Config1);
5923 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5924 RTL_W8(Config1, cfg1 & ~LEDS0);
5925
5926 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5927 }
5928
5929 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5930 {
5931 void __iomem *ioaddr = tp->mmio_addr;
5932 struct pci_dev *pdev = tp->pci_dev;
5933
5934 rtl_csi_access_enable_2(tp);
5935
5936 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5937
5938 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5939 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5940 }
5941
5942 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5943 {
5944 rtl_hw_start_8102e_2(tp);
5945
5946 rtl_ephy_write(tp, 0x03, 0xc2f9);
5947 }
5948
5949 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5950 {
5951 void __iomem *ioaddr = tp->mmio_addr;
5952 static const struct ephy_info e_info_8105e_1[] = {
5953 { 0x07, 0, 0x4000 },
5954 { 0x19, 0, 0x0200 },
5955 { 0x19, 0, 0x0020 },
5956 { 0x1e, 0, 0x2000 },
5957 { 0x03, 0, 0x0001 },
5958 { 0x19, 0, 0x0100 },
5959 { 0x19, 0, 0x0004 },
5960 { 0x0a, 0, 0x0020 }
5961 };
5962
5963 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5964 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5965
5966 /* Disable Early Tally Counter */
5967 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5968
5969 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5970 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5971
5972 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5973
5974 rtl_pcie_state_l2l3_enable(tp, false);
5975 }
5976
5977 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5978 {
5979 rtl_hw_start_8105e_1(tp);
5980 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5981 }
5982
5983 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5984 {
5985 void __iomem *ioaddr = tp->mmio_addr;
5986 static const struct ephy_info e_info_8402[] = {
5987 { 0x19, 0xffff, 0xff64 },
5988 { 0x1e, 0, 0x4000 }
5989 };
5990
5991 rtl_csi_access_enable_2(tp);
5992
5993 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5994 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5995
5996 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5997 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5998
5999 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6000
6001 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6002
6003 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6004 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6005 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6006 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6007 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6008 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6009 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6010
6011 rtl_pcie_state_l2l3_enable(tp, false);
6012 }
6013
6014 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6015 {
6016 void __iomem *ioaddr = tp->mmio_addr;
6017
6018 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6019 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6020
6021 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6022 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6023 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6024
6025 rtl_pcie_state_l2l3_enable(tp, false);
6026 }
6027
6028 static void rtl_hw_start_8101(struct net_device *dev)
6029 {
6030 struct rtl8169_private *tp = netdev_priv(dev);
6031 void __iomem *ioaddr = tp->mmio_addr;
6032 struct pci_dev *pdev = tp->pci_dev;
6033
6034 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6035 tp->event_slow &= ~RxFIFOOver;
6036
6037 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6038 tp->mac_version == RTL_GIGA_MAC_VER_16)
6039 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6040 PCI_EXP_DEVCTL_NOSNOOP_EN);
6041
6042 RTL_W8(Cfg9346, Cfg9346_Unlock);
6043
6044 RTL_W8(MaxTxPacketSize, TxPacketMax);
6045
6046 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6047
6048 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6049 RTL_W16(CPlusCmd, tp->cp_cmd);
6050
6051 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6052
6053 rtl_set_rx_tx_config_registers(tp);
6054
6055 switch (tp->mac_version) {
6056 case RTL_GIGA_MAC_VER_07:
6057 rtl_hw_start_8102e_1(tp);
6058 break;
6059
6060 case RTL_GIGA_MAC_VER_08:
6061 rtl_hw_start_8102e_3(tp);
6062 break;
6063
6064 case RTL_GIGA_MAC_VER_09:
6065 rtl_hw_start_8102e_2(tp);
6066 break;
6067
6068 case RTL_GIGA_MAC_VER_29:
6069 rtl_hw_start_8105e_1(tp);
6070 break;
6071 case RTL_GIGA_MAC_VER_30:
6072 rtl_hw_start_8105e_2(tp);
6073 break;
6074
6075 case RTL_GIGA_MAC_VER_37:
6076 rtl_hw_start_8402(tp);
6077 break;
6078
6079 case RTL_GIGA_MAC_VER_39:
6080 rtl_hw_start_8106(tp);
6081 break;
6082 case RTL_GIGA_MAC_VER_43:
6083 rtl_hw_start_8168g_2(tp);
6084 break;
6085 case RTL_GIGA_MAC_VER_47:
6086 case RTL_GIGA_MAC_VER_48:
6087 rtl_hw_start_8168h_1(tp);
6088 break;
6089 }
6090
6091 RTL_W8(Cfg9346, Cfg9346_Lock);
6092
6093 RTL_W16(IntrMitigate, 0x0000);
6094
6095 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6096
6097 rtl_set_rx_mode(dev);
6098
6099 RTL_R8(IntrMask);
6100
6101 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6102 }
6103
6104 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6105 {
6106 struct rtl8169_private *tp = netdev_priv(dev);
6107
6108 if (new_mtu < ETH_ZLEN ||
6109 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6110 return -EINVAL;
6111
6112 if (new_mtu > ETH_DATA_LEN)
6113 rtl_hw_jumbo_enable(tp);
6114 else
6115 rtl_hw_jumbo_disable(tp);
6116
6117 dev->mtu = new_mtu;
6118 netdev_update_features(dev);
6119
6120 return 0;
6121 }
6122
6123 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6124 {
6125 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6126 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6127 }
6128
6129 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6130 void **data_buff, struct RxDesc *desc)
6131 {
6132 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6133 DMA_FROM_DEVICE);
6134
6135 kfree(*data_buff);
6136 *data_buff = NULL;
6137 rtl8169_make_unusable_by_asic(desc);
6138 }
6139
6140 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6141 {
6142 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6143
6144 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6145 }
6146
6147 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6148 u32 rx_buf_sz)
6149 {
6150 desc->addr = cpu_to_le64(mapping);
6151 wmb();
6152 rtl8169_mark_to_asic(desc, rx_buf_sz);
6153 }
6154
6155 static inline void *rtl8169_align(void *data)
6156 {
6157 return (void *)ALIGN((long)data, 16);
6158 }
6159
6160 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6161 struct RxDesc *desc)
6162 {
6163 void *data;
6164 dma_addr_t mapping;
6165 struct device *d = &tp->pci_dev->dev;
6166 struct net_device *dev = tp->dev;
6167 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6168
6169 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6170 if (!data)
6171 return NULL;
6172
6173 if (rtl8169_align(data) != data) {
6174 kfree(data);
6175 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6176 if (!data)
6177 return NULL;
6178 }
6179
6180 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6181 DMA_FROM_DEVICE);
6182 if (unlikely(dma_mapping_error(d, mapping))) {
6183 if (net_ratelimit())
6184 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6185 goto err_out;
6186 }
6187
6188 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6189 return data;
6190
6191 err_out:
6192 kfree(data);
6193 return NULL;
6194 }
6195
6196 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6197 {
6198 unsigned int i;
6199
6200 for (i = 0; i < NUM_RX_DESC; i++) {
6201 if (tp->Rx_databuff[i]) {
6202 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6203 tp->RxDescArray + i);
6204 }
6205 }
6206 }
6207
6208 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6209 {
6210 desc->opts1 |= cpu_to_le32(RingEnd);
6211 }
6212
6213 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6214 {
6215 unsigned int i;
6216
6217 for (i = 0; i < NUM_RX_DESC; i++) {
6218 void *data;
6219
6220 if (tp->Rx_databuff[i])
6221 continue;
6222
6223 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6224 if (!data) {
6225 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6226 goto err_out;
6227 }
6228 tp->Rx_databuff[i] = data;
6229 }
6230
6231 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6232 return 0;
6233
6234 err_out:
6235 rtl8169_rx_clear(tp);
6236 return -ENOMEM;
6237 }
6238
6239 static int rtl8169_init_ring(struct net_device *dev)
6240 {
6241 struct rtl8169_private *tp = netdev_priv(dev);
6242
6243 rtl8169_init_ring_indexes(tp);
6244
6245 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6246 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6247
6248 return rtl8169_rx_fill(tp);
6249 }
6250
6251 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6252 struct TxDesc *desc)
6253 {
6254 unsigned int len = tx_skb->len;
6255
6256 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6257
6258 desc->opts1 = 0x00;
6259 desc->opts2 = 0x00;
6260 desc->addr = 0x00;
6261 tx_skb->len = 0;
6262 }
6263
6264 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6265 unsigned int n)
6266 {
6267 unsigned int i;
6268
6269 for (i = 0; i < n; i++) {
6270 unsigned int entry = (start + i) % NUM_TX_DESC;
6271 struct ring_info *tx_skb = tp->tx_skb + entry;
6272 unsigned int len = tx_skb->len;
6273
6274 if (len) {
6275 struct sk_buff *skb = tx_skb->skb;
6276
6277 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6278 tp->TxDescArray + entry);
6279 if (skb) {
6280 tp->dev->stats.tx_dropped++;
6281 dev_kfree_skb_any(skb);
6282 tx_skb->skb = NULL;
6283 }
6284 }
6285 }
6286 }
6287
6288 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6289 {
6290 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6291 tp->cur_tx = tp->dirty_tx = 0;
6292 }
6293
6294 static void rtl_reset_work(struct rtl8169_private *tp)
6295 {
6296 struct net_device *dev = tp->dev;
6297 int i;
6298
6299 napi_disable(&tp->napi);
6300 netif_stop_queue(dev);
6301 synchronize_sched();
6302
6303 rtl8169_hw_reset(tp);
6304
6305 for (i = 0; i < NUM_RX_DESC; i++)
6306 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6307
6308 rtl8169_tx_clear(tp);
6309 rtl8169_init_ring_indexes(tp);
6310
6311 napi_enable(&tp->napi);
6312 rtl_hw_start(dev);
6313 netif_wake_queue(dev);
6314 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6315 }
6316
6317 static void rtl8169_tx_timeout(struct net_device *dev)
6318 {
6319 struct rtl8169_private *tp = netdev_priv(dev);
6320
6321 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6322 }
6323
6324 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6325 u32 *opts)
6326 {
6327 struct skb_shared_info *info = skb_shinfo(skb);
6328 unsigned int cur_frag, entry;
6329 struct TxDesc *uninitialized_var(txd);
6330 struct device *d = &tp->pci_dev->dev;
6331
6332 entry = tp->cur_tx;
6333 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6334 const skb_frag_t *frag = info->frags + cur_frag;
6335 dma_addr_t mapping;
6336 u32 status, len;
6337 void *addr;
6338
6339 entry = (entry + 1) % NUM_TX_DESC;
6340
6341 txd = tp->TxDescArray + entry;
6342 len = skb_frag_size(frag);
6343 addr = skb_frag_address(frag);
6344 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6345 if (unlikely(dma_mapping_error(d, mapping))) {
6346 if (net_ratelimit())
6347 netif_err(tp, drv, tp->dev,
6348 "Failed to map TX fragments DMA!\n");
6349 goto err_out;
6350 }
6351
6352 /* Anti gcc 2.95.3 bugware (sic) */
6353 status = opts[0] | len |
6354 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6355
6356 txd->opts1 = cpu_to_le32(status);
6357 txd->opts2 = cpu_to_le32(opts[1]);
6358 txd->addr = cpu_to_le64(mapping);
6359
6360 tp->tx_skb[entry].len = len;
6361 }
6362
6363 if (cur_frag) {
6364 tp->tx_skb[entry].skb = skb;
6365 txd->opts1 |= cpu_to_le32(LastFrag);
6366 }
6367
6368 return cur_frag;
6369
6370 err_out:
6371 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6372 return -EIO;
6373 }
6374
6375 static bool rtl_skb_pad(struct sk_buff *skb)
6376 {
6377 if (skb_padto(skb, ETH_ZLEN))
6378 return false;
6379 skb_put(skb, ETH_ZLEN - skb->len);
6380 return true;
6381 }
6382
6383 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6384 {
6385 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6386 }
6387
6388 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6389 struct net_device *dev);
6390 /* r8169_csum_workaround()
6391 * The hw limites the value the transport offset. When the offset is out of the
6392 * range, calculate the checksum by sw.
6393 */
6394 static void r8169_csum_workaround(struct rtl8169_private *tp,
6395 struct sk_buff *skb)
6396 {
6397 if (skb_shinfo(skb)->gso_size) {
6398 netdev_features_t features = tp->dev->features;
6399 struct sk_buff *segs, *nskb;
6400
6401 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6402 segs = skb_gso_segment(skb, features);
6403 if (IS_ERR(segs) || !segs)
6404 goto drop;
6405
6406 do {
6407 nskb = segs;
6408 segs = segs->next;
6409 nskb->next = NULL;
6410 rtl8169_start_xmit(nskb, tp->dev);
6411 } while (segs);
6412
6413 dev_kfree_skb(skb);
6414 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6415 if (skb_checksum_help(skb) < 0)
6416 goto drop;
6417
6418 rtl8169_start_xmit(skb, tp->dev);
6419 } else {
6420 struct net_device_stats *stats;
6421
6422 drop:
6423 stats = &tp->dev->stats;
6424 stats->tx_dropped++;
6425 dev_kfree_skb(skb);
6426 }
6427 }
6428
6429 /* msdn_giant_send_check()
6430 * According to the document of microsoft, the TCP Pseudo Header excludes the
6431 * packet length for IPv6 TCP large packets.
6432 */
6433 static int msdn_giant_send_check(struct sk_buff *skb)
6434 {
6435 const struct ipv6hdr *ipv6h;
6436 struct tcphdr *th;
6437 int ret;
6438
6439 ret = skb_cow_head(skb, 0);
6440 if (ret)
6441 return ret;
6442
6443 ipv6h = ipv6_hdr(skb);
6444 th = tcp_hdr(skb);
6445
6446 th->check = 0;
6447 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6448
6449 return ret;
6450 }
6451
6452 static inline __be16 get_protocol(struct sk_buff *skb)
6453 {
6454 __be16 protocol;
6455
6456 if (skb->protocol == htons(ETH_P_8021Q))
6457 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6458 else
6459 protocol = skb->protocol;
6460
6461 return protocol;
6462 }
6463
6464 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6465 struct sk_buff *skb, u32 *opts)
6466 {
6467 u32 mss = skb_shinfo(skb)->gso_size;
6468
6469 if (mss) {
6470 opts[0] |= TD_LSO;
6471 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6472 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6473 const struct iphdr *ip = ip_hdr(skb);
6474
6475 if (ip->protocol == IPPROTO_TCP)
6476 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6477 else if (ip->protocol == IPPROTO_UDP)
6478 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6479 else
6480 WARN_ON_ONCE(1);
6481 }
6482
6483 return true;
6484 }
6485
6486 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6487 struct sk_buff *skb, u32 *opts)
6488 {
6489 u32 transport_offset = (u32)skb_transport_offset(skb);
6490 u32 mss = skb_shinfo(skb)->gso_size;
6491
6492 if (mss) {
6493 if (transport_offset > GTTCPHO_MAX) {
6494 netif_warn(tp, tx_err, tp->dev,
6495 "Invalid transport offset 0x%x for TSO\n",
6496 transport_offset);
6497 return false;
6498 }
6499
6500 switch (get_protocol(skb)) {
6501 case htons(ETH_P_IP):
6502 opts[0] |= TD1_GTSENV4;
6503 break;
6504
6505 case htons(ETH_P_IPV6):
6506 if (msdn_giant_send_check(skb))
6507 return false;
6508
6509 opts[0] |= TD1_GTSENV6;
6510 break;
6511
6512 default:
6513 WARN_ON_ONCE(1);
6514 break;
6515 }
6516
6517 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6518 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6519 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6520 u8 ip_protocol;
6521
6522 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6523 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
6524
6525 if (transport_offset > TCPHO_MAX) {
6526 netif_warn(tp, tx_err, tp->dev,
6527 "Invalid transport offset 0x%x\n",
6528 transport_offset);
6529 return false;
6530 }
6531
6532 switch (get_protocol(skb)) {
6533 case htons(ETH_P_IP):
6534 opts[1] |= TD1_IPv4_CS;
6535 ip_protocol = ip_hdr(skb)->protocol;
6536 break;
6537
6538 case htons(ETH_P_IPV6):
6539 opts[1] |= TD1_IPv6_CS;
6540 ip_protocol = ipv6_hdr(skb)->nexthdr;
6541 break;
6542
6543 default:
6544 ip_protocol = IPPROTO_RAW;
6545 break;
6546 }
6547
6548 if (ip_protocol == IPPROTO_TCP)
6549 opts[1] |= TD1_TCP_CS;
6550 else if (ip_protocol == IPPROTO_UDP)
6551 opts[1] |= TD1_UDP_CS;
6552 else
6553 WARN_ON_ONCE(1);
6554
6555 opts[1] |= transport_offset << TCPHO_SHIFT;
6556 } else {
6557 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6558 return rtl_skb_pad(skb);
6559 }
6560
6561 return true;
6562 }
6563
6564 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6565 struct net_device *dev)
6566 {
6567 struct rtl8169_private *tp = netdev_priv(dev);
6568 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6569 struct TxDesc *txd = tp->TxDescArray + entry;
6570 void __iomem *ioaddr = tp->mmio_addr;
6571 struct device *d = &tp->pci_dev->dev;
6572 dma_addr_t mapping;
6573 u32 status, len;
6574 u32 opts[2];
6575 int frags;
6576
6577 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6578 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6579 goto err_stop_0;
6580 }
6581
6582 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6583 goto err_stop_0;
6584
6585 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6586 opts[0] = DescOwn;
6587
6588 if (!tp->tso_csum(tp, skb, opts)) {
6589 r8169_csum_workaround(tp, skb);
6590 return NETDEV_TX_OK;
6591 }
6592
6593 len = skb_headlen(skb);
6594 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6595 if (unlikely(dma_mapping_error(d, mapping))) {
6596 if (net_ratelimit())
6597 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6598 goto err_dma_0;
6599 }
6600
6601 tp->tx_skb[entry].len = len;
6602 txd->addr = cpu_to_le64(mapping);
6603
6604 frags = rtl8169_xmit_frags(tp, skb, opts);
6605 if (frags < 0)
6606 goto err_dma_1;
6607 else if (frags)
6608 opts[0] |= FirstFrag;
6609 else {
6610 opts[0] |= FirstFrag | LastFrag;
6611 tp->tx_skb[entry].skb = skb;
6612 }
6613
6614 txd->opts2 = cpu_to_le32(opts[1]);
6615
6616 skb_tx_timestamp(skb);
6617
6618 wmb();
6619
6620 /* Anti gcc 2.95.3 bugware (sic) */
6621 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6622 txd->opts1 = cpu_to_le32(status);
6623
6624 tp->cur_tx += frags + 1;
6625
6626 wmb();
6627
6628 RTL_W8(TxPoll, NPQ);
6629
6630 mmiowb();
6631
6632 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6633 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6634 * not miss a ring update when it notices a stopped queue.
6635 */
6636 smp_wmb();
6637 netif_stop_queue(dev);
6638 /* Sync with rtl_tx:
6639 * - publish queue status and cur_tx ring index (write barrier)
6640 * - refresh dirty_tx ring index (read barrier).
6641 * May the current thread have a pessimistic view of the ring
6642 * status and forget to wake up queue, a racing rtl_tx thread
6643 * can't.
6644 */
6645 smp_mb();
6646 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6647 netif_wake_queue(dev);
6648 }
6649
6650 return NETDEV_TX_OK;
6651
6652 err_dma_1:
6653 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6654 err_dma_0:
6655 dev_kfree_skb_any(skb);
6656 dev->stats.tx_dropped++;
6657 return NETDEV_TX_OK;
6658
6659 err_stop_0:
6660 netif_stop_queue(dev);
6661 dev->stats.tx_dropped++;
6662 return NETDEV_TX_BUSY;
6663 }
6664
6665 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6666 {
6667 struct rtl8169_private *tp = netdev_priv(dev);
6668 struct pci_dev *pdev = tp->pci_dev;
6669 u16 pci_status, pci_cmd;
6670
6671 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6672 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6673
6674 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6675 pci_cmd, pci_status);
6676
6677 /*
6678 * The recovery sequence below admits a very elaborated explanation:
6679 * - it seems to work;
6680 * - I did not see what else could be done;
6681 * - it makes iop3xx happy.
6682 *
6683 * Feel free to adjust to your needs.
6684 */
6685 if (pdev->broken_parity_status)
6686 pci_cmd &= ~PCI_COMMAND_PARITY;
6687 else
6688 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6689
6690 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6691
6692 pci_write_config_word(pdev, PCI_STATUS,
6693 pci_status & (PCI_STATUS_DETECTED_PARITY |
6694 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6695 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6696
6697 /* The infamous DAC f*ckup only happens at boot time */
6698 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6699 void __iomem *ioaddr = tp->mmio_addr;
6700
6701 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6702 tp->cp_cmd &= ~PCIDAC;
6703 RTL_W16(CPlusCmd, tp->cp_cmd);
6704 dev->features &= ~NETIF_F_HIGHDMA;
6705 }
6706
6707 rtl8169_hw_reset(tp);
6708
6709 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6710 }
6711
6712 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6713 {
6714 unsigned int dirty_tx, tx_left;
6715
6716 dirty_tx = tp->dirty_tx;
6717 smp_rmb();
6718 tx_left = tp->cur_tx - dirty_tx;
6719
6720 while (tx_left > 0) {
6721 unsigned int entry = dirty_tx % NUM_TX_DESC;
6722 struct ring_info *tx_skb = tp->tx_skb + entry;
6723 u32 status;
6724
6725 rmb();
6726 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6727 if (status & DescOwn)
6728 break;
6729
6730 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6731 tp->TxDescArray + entry);
6732 if (status & LastFrag) {
6733 u64_stats_update_begin(&tp->tx_stats.syncp);
6734 tp->tx_stats.packets++;
6735 tp->tx_stats.bytes += tx_skb->skb->len;
6736 u64_stats_update_end(&tp->tx_stats.syncp);
6737 dev_kfree_skb_any(tx_skb->skb);
6738 tx_skb->skb = NULL;
6739 }
6740 dirty_tx++;
6741 tx_left--;
6742 }
6743
6744 if (tp->dirty_tx != dirty_tx) {
6745 tp->dirty_tx = dirty_tx;
6746 /* Sync with rtl8169_start_xmit:
6747 * - publish dirty_tx ring index (write barrier)
6748 * - refresh cur_tx ring index and queue status (read barrier)
6749 * May the current thread miss the stopped queue condition,
6750 * a racing xmit thread can only have a right view of the
6751 * ring status.
6752 */
6753 smp_mb();
6754 if (netif_queue_stopped(dev) &&
6755 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6756 netif_wake_queue(dev);
6757 }
6758 /*
6759 * 8168 hack: TxPoll requests are lost when the Tx packets are
6760 * too close. Let's kick an extra TxPoll request when a burst
6761 * of start_xmit activity is detected (if it is not detected,
6762 * it is slow enough). -- FR
6763 */
6764 if (tp->cur_tx != dirty_tx) {
6765 void __iomem *ioaddr = tp->mmio_addr;
6766
6767 RTL_W8(TxPoll, NPQ);
6768 }
6769 }
6770 }
6771
6772 static inline int rtl8169_fragmented_frame(u32 status)
6773 {
6774 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6775 }
6776
6777 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6778 {
6779 u32 status = opts1 & RxProtoMask;
6780
6781 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6782 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6783 skb->ip_summed = CHECKSUM_UNNECESSARY;
6784 else
6785 skb_checksum_none_assert(skb);
6786 }
6787
6788 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6789 struct rtl8169_private *tp,
6790 int pkt_size,
6791 dma_addr_t addr)
6792 {
6793 struct sk_buff *skb;
6794 struct device *d = &tp->pci_dev->dev;
6795
6796 data = rtl8169_align(data);
6797 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6798 prefetch(data);
6799 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6800 if (skb)
6801 memcpy(skb->data, data, pkt_size);
6802 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6803
6804 return skb;
6805 }
6806
6807 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6808 {
6809 unsigned int cur_rx, rx_left;
6810 unsigned int count;
6811
6812 cur_rx = tp->cur_rx;
6813
6814 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6815 unsigned int entry = cur_rx % NUM_RX_DESC;
6816 struct RxDesc *desc = tp->RxDescArray + entry;
6817 u32 status;
6818
6819 rmb();
6820 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6821
6822 if (status & DescOwn)
6823 break;
6824 if (unlikely(status & RxRES)) {
6825 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6826 status);
6827 dev->stats.rx_errors++;
6828 if (status & (RxRWT | RxRUNT))
6829 dev->stats.rx_length_errors++;
6830 if (status & RxCRC)
6831 dev->stats.rx_crc_errors++;
6832 if (status & RxFOVF) {
6833 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6834 dev->stats.rx_fifo_errors++;
6835 }
6836 if ((status & (RxRUNT | RxCRC)) &&
6837 !(status & (RxRWT | RxFOVF)) &&
6838 (dev->features & NETIF_F_RXALL))
6839 goto process_pkt;
6840 } else {
6841 struct sk_buff *skb;
6842 dma_addr_t addr;
6843 int pkt_size;
6844
6845 process_pkt:
6846 addr = le64_to_cpu(desc->addr);
6847 if (likely(!(dev->features & NETIF_F_RXFCS)))
6848 pkt_size = (status & 0x00003fff) - 4;
6849 else
6850 pkt_size = status & 0x00003fff;
6851
6852 /*
6853 * The driver does not support incoming fragmented
6854 * frames. They are seen as a symptom of over-mtu
6855 * sized frames.
6856 */
6857 if (unlikely(rtl8169_fragmented_frame(status))) {
6858 dev->stats.rx_dropped++;
6859 dev->stats.rx_length_errors++;
6860 goto release_descriptor;
6861 }
6862
6863 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6864 tp, pkt_size, addr);
6865 if (!skb) {
6866 dev->stats.rx_dropped++;
6867 goto release_descriptor;
6868 }
6869
6870 rtl8169_rx_csum(skb, status);
6871 skb_put(skb, pkt_size);
6872 skb->protocol = eth_type_trans(skb, dev);
6873
6874 rtl8169_rx_vlan_tag(desc, skb);
6875
6876 napi_gro_receive(&tp->napi, skb);
6877
6878 u64_stats_update_begin(&tp->rx_stats.syncp);
6879 tp->rx_stats.packets++;
6880 tp->rx_stats.bytes += pkt_size;
6881 u64_stats_update_end(&tp->rx_stats.syncp);
6882 }
6883 release_descriptor:
6884 desc->opts2 = 0;
6885 wmb();
6886 rtl8169_mark_to_asic(desc, rx_buf_sz);
6887 }
6888
6889 count = cur_rx - tp->cur_rx;
6890 tp->cur_rx = cur_rx;
6891
6892 return count;
6893 }
6894
6895 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6896 {
6897 struct net_device *dev = dev_instance;
6898 struct rtl8169_private *tp = netdev_priv(dev);
6899 int handled = 0;
6900 u16 status;
6901
6902 status = rtl_get_events(tp);
6903 if (status && status != 0xffff) {
6904 status &= RTL_EVENT_NAPI | tp->event_slow;
6905 if (status) {
6906 handled = 1;
6907
6908 rtl_irq_disable(tp);
6909 napi_schedule(&tp->napi);
6910 }
6911 }
6912 return IRQ_RETVAL(handled);
6913 }
6914
6915 /*
6916 * Workqueue context.
6917 */
6918 static void rtl_slow_event_work(struct rtl8169_private *tp)
6919 {
6920 struct net_device *dev = tp->dev;
6921 u16 status;
6922
6923 status = rtl_get_events(tp) & tp->event_slow;
6924 rtl_ack_events(tp, status);
6925
6926 if (unlikely(status & RxFIFOOver)) {
6927 switch (tp->mac_version) {
6928 /* Work around for rx fifo overflow */
6929 case RTL_GIGA_MAC_VER_11:
6930 netif_stop_queue(dev);
6931 /* XXX - Hack alert. See rtl_task(). */
6932 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6933 default:
6934 break;
6935 }
6936 }
6937
6938 if (unlikely(status & SYSErr))
6939 rtl8169_pcierr_interrupt(dev);
6940
6941 if (status & LinkChg)
6942 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6943
6944 rtl_irq_enable_all(tp);
6945 }
6946
6947 static void rtl_task(struct work_struct *work)
6948 {
6949 static const struct {
6950 int bitnr;
6951 void (*action)(struct rtl8169_private *);
6952 } rtl_work[] = {
6953 /* XXX - keep rtl_slow_event_work() as first element. */
6954 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6955 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6956 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6957 };
6958 struct rtl8169_private *tp =
6959 container_of(work, struct rtl8169_private, wk.work);
6960 struct net_device *dev = tp->dev;
6961 int i;
6962
6963 rtl_lock_work(tp);
6964
6965 if (!netif_running(dev) ||
6966 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6967 goto out_unlock;
6968
6969 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6970 bool pending;
6971
6972 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6973 if (pending)
6974 rtl_work[i].action(tp);
6975 }
6976
6977 out_unlock:
6978 rtl_unlock_work(tp);
6979 }
6980
6981 static int rtl8169_poll(struct napi_struct *napi, int budget)
6982 {
6983 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6984 struct net_device *dev = tp->dev;
6985 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6986 int work_done= 0;
6987 u16 status;
6988
6989 status = rtl_get_events(tp);
6990 rtl_ack_events(tp, status & ~tp->event_slow);
6991
6992 if (status & RTL_EVENT_NAPI_RX)
6993 work_done = rtl_rx(dev, tp, (u32) budget);
6994
6995 if (status & RTL_EVENT_NAPI_TX)
6996 rtl_tx(dev, tp);
6997
6998 if (status & tp->event_slow) {
6999 enable_mask &= ~tp->event_slow;
7000
7001 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7002 }
7003
7004 if (work_done < budget) {
7005 napi_complete(napi);
7006
7007 rtl_irq_enable(tp, enable_mask);
7008 mmiowb();
7009 }
7010
7011 return work_done;
7012 }
7013
7014 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7015 {
7016 struct rtl8169_private *tp = netdev_priv(dev);
7017
7018 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7019 return;
7020
7021 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7022 RTL_W32(RxMissed, 0);
7023 }
7024
7025 static void rtl8169_down(struct net_device *dev)
7026 {
7027 struct rtl8169_private *tp = netdev_priv(dev);
7028 void __iomem *ioaddr = tp->mmio_addr;
7029
7030 del_timer_sync(&tp->timer);
7031
7032 napi_disable(&tp->napi);
7033 netif_stop_queue(dev);
7034
7035 rtl8169_hw_reset(tp);
7036 /*
7037 * At this point device interrupts can not be enabled in any function,
7038 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7039 * and napi is disabled (rtl8169_poll).
7040 */
7041 rtl8169_rx_missed(dev, ioaddr);
7042
7043 /* Give a racing hard_start_xmit a few cycles to complete. */
7044 synchronize_sched();
7045
7046 rtl8169_tx_clear(tp);
7047
7048 rtl8169_rx_clear(tp);
7049
7050 rtl_pll_power_down(tp);
7051 }
7052
7053 static int rtl8169_close(struct net_device *dev)
7054 {
7055 struct rtl8169_private *tp = netdev_priv(dev);
7056 struct pci_dev *pdev = tp->pci_dev;
7057
7058 pm_runtime_get_sync(&pdev->dev);
7059
7060 /* Update counters before going down */
7061 rtl8169_update_counters(dev);
7062
7063 rtl_lock_work(tp);
7064 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7065
7066 rtl8169_down(dev);
7067 rtl_unlock_work(tp);
7068
7069 cancel_work_sync(&tp->wk.work);
7070
7071 free_irq(pdev->irq, dev);
7072
7073 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7074 tp->RxPhyAddr);
7075 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7076 tp->TxPhyAddr);
7077 tp->TxDescArray = NULL;
7078 tp->RxDescArray = NULL;
7079
7080 pm_runtime_put_sync(&pdev->dev);
7081
7082 return 0;
7083 }
7084
7085 #ifdef CONFIG_NET_POLL_CONTROLLER
7086 static void rtl8169_netpoll(struct net_device *dev)
7087 {
7088 struct rtl8169_private *tp = netdev_priv(dev);
7089
7090 rtl8169_interrupt(tp->pci_dev->irq, dev);
7091 }
7092 #endif
7093
7094 static int rtl_open(struct net_device *dev)
7095 {
7096 struct rtl8169_private *tp = netdev_priv(dev);
7097 void __iomem *ioaddr = tp->mmio_addr;
7098 struct pci_dev *pdev = tp->pci_dev;
7099 int retval = -ENOMEM;
7100
7101 pm_runtime_get_sync(&pdev->dev);
7102
7103 /*
7104 * Rx and Tx descriptors needs 256 bytes alignment.
7105 * dma_alloc_coherent provides more.
7106 */
7107 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7108 &tp->TxPhyAddr, GFP_KERNEL);
7109 if (!tp->TxDescArray)
7110 goto err_pm_runtime_put;
7111
7112 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7113 &tp->RxPhyAddr, GFP_KERNEL);
7114 if (!tp->RxDescArray)
7115 goto err_free_tx_0;
7116
7117 retval = rtl8169_init_ring(dev);
7118 if (retval < 0)
7119 goto err_free_rx_1;
7120
7121 INIT_WORK(&tp->wk.work, rtl_task);
7122
7123 smp_mb();
7124
7125 rtl_request_firmware(tp);
7126
7127 retval = request_irq(pdev->irq, rtl8169_interrupt,
7128 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7129 dev->name, dev);
7130 if (retval < 0)
7131 goto err_release_fw_2;
7132
7133 rtl_lock_work(tp);
7134
7135 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7136
7137 napi_enable(&tp->napi);
7138
7139 rtl8169_init_phy(dev, tp);
7140
7141 __rtl8169_set_features(dev, dev->features);
7142
7143 rtl_pll_power_up(tp);
7144
7145 rtl_hw_start(dev);
7146
7147 netif_start_queue(dev);
7148
7149 rtl_unlock_work(tp);
7150
7151 tp->saved_wolopts = 0;
7152 pm_runtime_put_noidle(&pdev->dev);
7153
7154 rtl8169_check_link_status(dev, tp, ioaddr);
7155 out:
7156 return retval;
7157
7158 err_release_fw_2:
7159 rtl_release_firmware(tp);
7160 rtl8169_rx_clear(tp);
7161 err_free_rx_1:
7162 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7163 tp->RxPhyAddr);
7164 tp->RxDescArray = NULL;
7165 err_free_tx_0:
7166 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7167 tp->TxPhyAddr);
7168 tp->TxDescArray = NULL;
7169 err_pm_runtime_put:
7170 pm_runtime_put_noidle(&pdev->dev);
7171 goto out;
7172 }
7173
7174 static struct rtnl_link_stats64 *
7175 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7176 {
7177 struct rtl8169_private *tp = netdev_priv(dev);
7178 void __iomem *ioaddr = tp->mmio_addr;
7179 unsigned int start;
7180
7181 if (netif_running(dev))
7182 rtl8169_rx_missed(dev, ioaddr);
7183
7184 do {
7185 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7186 stats->rx_packets = tp->rx_stats.packets;
7187 stats->rx_bytes = tp->rx_stats.bytes;
7188 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7189
7190
7191 do {
7192 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7193 stats->tx_packets = tp->tx_stats.packets;
7194 stats->tx_bytes = tp->tx_stats.bytes;
7195 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7196
7197 stats->rx_dropped = dev->stats.rx_dropped;
7198 stats->tx_dropped = dev->stats.tx_dropped;
7199 stats->rx_length_errors = dev->stats.rx_length_errors;
7200 stats->rx_errors = dev->stats.rx_errors;
7201 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7202 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7203 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7204
7205 return stats;
7206 }
7207
7208 static void rtl8169_net_suspend(struct net_device *dev)
7209 {
7210 struct rtl8169_private *tp = netdev_priv(dev);
7211
7212 if (!netif_running(dev))
7213 return;
7214
7215 netif_device_detach(dev);
7216 netif_stop_queue(dev);
7217
7218 rtl_lock_work(tp);
7219 napi_disable(&tp->napi);
7220 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7221 rtl_unlock_work(tp);
7222
7223 rtl_pll_power_down(tp);
7224 }
7225
7226 #ifdef CONFIG_PM
7227
7228 static int rtl8169_suspend(struct device *device)
7229 {
7230 struct pci_dev *pdev = to_pci_dev(device);
7231 struct net_device *dev = pci_get_drvdata(pdev);
7232
7233 rtl8169_net_suspend(dev);
7234
7235 return 0;
7236 }
7237
7238 static void __rtl8169_resume(struct net_device *dev)
7239 {
7240 struct rtl8169_private *tp = netdev_priv(dev);
7241
7242 netif_device_attach(dev);
7243
7244 rtl_pll_power_up(tp);
7245
7246 rtl_lock_work(tp);
7247 napi_enable(&tp->napi);
7248 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7249 rtl_unlock_work(tp);
7250
7251 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7252 }
7253
7254 static int rtl8169_resume(struct device *device)
7255 {
7256 struct pci_dev *pdev = to_pci_dev(device);
7257 struct net_device *dev = pci_get_drvdata(pdev);
7258 struct rtl8169_private *tp = netdev_priv(dev);
7259
7260 rtl8169_init_phy(dev, tp);
7261
7262 if (netif_running(dev))
7263 __rtl8169_resume(dev);
7264
7265 return 0;
7266 }
7267
7268 static int rtl8169_runtime_suspend(struct device *device)
7269 {
7270 struct pci_dev *pdev = to_pci_dev(device);
7271 struct net_device *dev = pci_get_drvdata(pdev);
7272 struct rtl8169_private *tp = netdev_priv(dev);
7273
7274 if (!tp->TxDescArray)
7275 return 0;
7276
7277 rtl_lock_work(tp);
7278 tp->saved_wolopts = __rtl8169_get_wol(tp);
7279 __rtl8169_set_wol(tp, WAKE_ANY);
7280 rtl_unlock_work(tp);
7281
7282 rtl8169_net_suspend(dev);
7283
7284 return 0;
7285 }
7286
7287 static int rtl8169_runtime_resume(struct device *device)
7288 {
7289 struct pci_dev *pdev = to_pci_dev(device);
7290 struct net_device *dev = pci_get_drvdata(pdev);
7291 struct rtl8169_private *tp = netdev_priv(dev);
7292
7293 if (!tp->TxDescArray)
7294 return 0;
7295
7296 rtl_lock_work(tp);
7297 __rtl8169_set_wol(tp, tp->saved_wolopts);
7298 tp->saved_wolopts = 0;
7299 rtl_unlock_work(tp);
7300
7301 rtl8169_init_phy(dev, tp);
7302
7303 __rtl8169_resume(dev);
7304
7305 return 0;
7306 }
7307
7308 static int rtl8169_runtime_idle(struct device *device)
7309 {
7310 struct pci_dev *pdev = to_pci_dev(device);
7311 struct net_device *dev = pci_get_drvdata(pdev);
7312 struct rtl8169_private *tp = netdev_priv(dev);
7313
7314 return tp->TxDescArray ? -EBUSY : 0;
7315 }
7316
7317 static const struct dev_pm_ops rtl8169_pm_ops = {
7318 .suspend = rtl8169_suspend,
7319 .resume = rtl8169_resume,
7320 .freeze = rtl8169_suspend,
7321 .thaw = rtl8169_resume,
7322 .poweroff = rtl8169_suspend,
7323 .restore = rtl8169_resume,
7324 .runtime_suspend = rtl8169_runtime_suspend,
7325 .runtime_resume = rtl8169_runtime_resume,
7326 .runtime_idle = rtl8169_runtime_idle,
7327 };
7328
7329 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7330
7331 #else /* !CONFIG_PM */
7332
7333 #define RTL8169_PM_OPS NULL
7334
7335 #endif /* !CONFIG_PM */
7336
7337 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7338 {
7339 void __iomem *ioaddr = tp->mmio_addr;
7340
7341 /* WoL fails with 8168b when the receiver is disabled. */
7342 switch (tp->mac_version) {
7343 case RTL_GIGA_MAC_VER_11:
7344 case RTL_GIGA_MAC_VER_12:
7345 case RTL_GIGA_MAC_VER_17:
7346 pci_clear_master(tp->pci_dev);
7347
7348 RTL_W8(ChipCmd, CmdRxEnb);
7349 /* PCI commit */
7350 RTL_R8(ChipCmd);
7351 break;
7352 default:
7353 break;
7354 }
7355 }
7356
7357 static void rtl_shutdown(struct pci_dev *pdev)
7358 {
7359 struct net_device *dev = pci_get_drvdata(pdev);
7360 struct rtl8169_private *tp = netdev_priv(dev);
7361 struct device *d = &pdev->dev;
7362
7363 pm_runtime_get_sync(d);
7364
7365 rtl8169_net_suspend(dev);
7366
7367 /* Restore original MAC address */
7368 rtl_rar_set(tp, dev->perm_addr);
7369
7370 rtl8169_hw_reset(tp);
7371
7372 if (system_state == SYSTEM_POWER_OFF) {
7373 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7374 rtl_wol_suspend_quirk(tp);
7375 rtl_wol_shutdown_quirk(tp);
7376 }
7377
7378 pci_wake_from_d3(pdev, true);
7379 pci_set_power_state(pdev, PCI_D3hot);
7380 }
7381
7382 pm_runtime_put_noidle(d);
7383 }
7384
7385 static void rtl_remove_one(struct pci_dev *pdev)
7386 {
7387 struct net_device *dev = pci_get_drvdata(pdev);
7388 struct rtl8169_private *tp = netdev_priv(dev);
7389
7390 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7391 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7392 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
7393 r8168_check_dash(tp)) {
7394 rtl8168_driver_stop(tp);
7395 }
7396
7397 netif_napi_del(&tp->napi);
7398
7399 unregister_netdev(dev);
7400
7401 rtl_release_firmware(tp);
7402
7403 if (pci_dev_run_wake(pdev))
7404 pm_runtime_get_noresume(&pdev->dev);
7405
7406 /* restore original MAC address */
7407 rtl_rar_set(tp, dev->perm_addr);
7408
7409 rtl_disable_msi(pdev, tp);
7410 rtl8169_release_board(pdev, dev, tp->mmio_addr);
7411 }
7412
7413 static const struct net_device_ops rtl_netdev_ops = {
7414 .ndo_open = rtl_open,
7415 .ndo_stop = rtl8169_close,
7416 .ndo_get_stats64 = rtl8169_get_stats64,
7417 .ndo_start_xmit = rtl8169_start_xmit,
7418 .ndo_tx_timeout = rtl8169_tx_timeout,
7419 .ndo_validate_addr = eth_validate_addr,
7420 .ndo_change_mtu = rtl8169_change_mtu,
7421 .ndo_fix_features = rtl8169_fix_features,
7422 .ndo_set_features = rtl8169_set_features,
7423 .ndo_set_mac_address = rtl_set_mac_address,
7424 .ndo_do_ioctl = rtl8169_ioctl,
7425 .ndo_set_rx_mode = rtl_set_rx_mode,
7426 #ifdef CONFIG_NET_POLL_CONTROLLER
7427 .ndo_poll_controller = rtl8169_netpoll,
7428 #endif
7429
7430 };
7431
7432 static const struct rtl_cfg_info {
7433 void (*hw_start)(struct net_device *);
7434 unsigned int region;
7435 unsigned int align;
7436 u16 event_slow;
7437 unsigned features;
7438 u8 default_ver;
7439 } rtl_cfg_infos [] = {
7440 [RTL_CFG_0] = {
7441 .hw_start = rtl_hw_start_8169,
7442 .region = 1,
7443 .align = 0,
7444 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7445 .features = RTL_FEATURE_GMII,
7446 .default_ver = RTL_GIGA_MAC_VER_01,
7447 },
7448 [RTL_CFG_1] = {
7449 .hw_start = rtl_hw_start_8168,
7450 .region = 2,
7451 .align = 8,
7452 .event_slow = SYSErr | LinkChg | RxOverflow,
7453 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7454 .default_ver = RTL_GIGA_MAC_VER_11,
7455 },
7456 [RTL_CFG_2] = {
7457 .hw_start = rtl_hw_start_8101,
7458 .region = 2,
7459 .align = 8,
7460 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7461 PCSTimeout,
7462 .features = RTL_FEATURE_MSI,
7463 .default_ver = RTL_GIGA_MAC_VER_13,
7464 }
7465 };
7466
7467 /* Cfg9346_Unlock assumed. */
7468 static unsigned rtl_try_msi(struct rtl8169_private *tp,
7469 const struct rtl_cfg_info *cfg)
7470 {
7471 void __iomem *ioaddr = tp->mmio_addr;
7472 unsigned msi = 0;
7473 u8 cfg2;
7474
7475 cfg2 = RTL_R8(Config2) & ~MSIEnable;
7476 if (cfg->features & RTL_FEATURE_MSI) {
7477 if (pci_enable_msi(tp->pci_dev)) {
7478 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7479 } else {
7480 cfg2 |= MSIEnable;
7481 msi = RTL_FEATURE_MSI;
7482 }
7483 }
7484 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7485 RTL_W8(Config2, cfg2);
7486 return msi;
7487 }
7488
7489 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7490 {
7491 void __iomem *ioaddr = tp->mmio_addr;
7492
7493 return RTL_R8(MCU) & LINK_LIST_RDY;
7494 }
7495
7496 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7497 {
7498 void __iomem *ioaddr = tp->mmio_addr;
7499
7500 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7501 }
7502
7503 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7504 {
7505 void __iomem *ioaddr = tp->mmio_addr;
7506 u32 data;
7507
7508 tp->ocp_base = OCP_STD_PHY_BASE;
7509
7510 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7511
7512 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7513 return;
7514
7515 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7516 return;
7517
7518 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7519 msleep(1);
7520 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7521
7522 data = r8168_mac_ocp_read(tp, 0xe8de);
7523 data &= ~(1 << 14);
7524 r8168_mac_ocp_write(tp, 0xe8de, data);
7525
7526 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7527 return;
7528
7529 data = r8168_mac_ocp_read(tp, 0xe8de);
7530 data |= (1 << 15);
7531 r8168_mac_ocp_write(tp, 0xe8de, data);
7532
7533 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7534 return;
7535 }
7536
7537 static void rtl_hw_initialize(struct rtl8169_private *tp)
7538 {
7539 switch (tp->mac_version) {
7540 case RTL_GIGA_MAC_VER_40:
7541 case RTL_GIGA_MAC_VER_41:
7542 case RTL_GIGA_MAC_VER_42:
7543 case RTL_GIGA_MAC_VER_43:
7544 case RTL_GIGA_MAC_VER_44:
7545 case RTL_GIGA_MAC_VER_45:
7546 case RTL_GIGA_MAC_VER_46:
7547 case RTL_GIGA_MAC_VER_47:
7548 case RTL_GIGA_MAC_VER_48:
7549 rtl_hw_init_8168g(tp);
7550 break;
7551
7552 default:
7553 break;
7554 }
7555 }
7556
7557 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7558 {
7559 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7560 const unsigned int region = cfg->region;
7561 struct rtl8169_private *tp;
7562 struct mii_if_info *mii;
7563 struct net_device *dev;
7564 void __iomem *ioaddr;
7565 int chipset, i;
7566 int rc;
7567
7568 if (netif_msg_drv(&debug)) {
7569 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7570 MODULENAME, RTL8169_VERSION);
7571 }
7572
7573 dev = alloc_etherdev(sizeof (*tp));
7574 if (!dev) {
7575 rc = -ENOMEM;
7576 goto out;
7577 }
7578
7579 SET_NETDEV_DEV(dev, &pdev->dev);
7580 dev->netdev_ops = &rtl_netdev_ops;
7581 tp = netdev_priv(dev);
7582 tp->dev = dev;
7583 tp->pci_dev = pdev;
7584 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7585
7586 mii = &tp->mii;
7587 mii->dev = dev;
7588 mii->mdio_read = rtl_mdio_read;
7589 mii->mdio_write = rtl_mdio_write;
7590 mii->phy_id_mask = 0x1f;
7591 mii->reg_num_mask = 0x1f;
7592 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
7593
7594 /* disable ASPM completely as that cause random device stop working
7595 * problems as well as full system hangs for some PCIe devices users */
7596 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
7597 PCIE_LINK_STATE_CLKPM);
7598
7599 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7600 rc = pci_enable_device(pdev);
7601 if (rc < 0) {
7602 netif_err(tp, probe, dev, "enable failure\n");
7603 goto err_out_free_dev_1;
7604 }
7605
7606 if (pci_set_mwi(pdev) < 0)
7607 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7608
7609 /* make sure PCI base addr 1 is MMIO */
7610 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7611 netif_err(tp, probe, dev,
7612 "region #%d not an MMIO resource, aborting\n",
7613 region);
7614 rc = -ENODEV;
7615 goto err_out_mwi_2;
7616 }
7617
7618 /* check for weird/broken PCI region reporting */
7619 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7620 netif_err(tp, probe, dev,
7621 "Invalid PCI region size(s), aborting\n");
7622 rc = -ENODEV;
7623 goto err_out_mwi_2;
7624 }
7625
7626 rc = pci_request_regions(pdev, MODULENAME);
7627 if (rc < 0) {
7628 netif_err(tp, probe, dev, "could not request regions\n");
7629 goto err_out_mwi_2;
7630 }
7631
7632 tp->cp_cmd = 0;
7633
7634 if ((sizeof(dma_addr_t) > 4) &&
7635 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7636 tp->cp_cmd |= PCIDAC;
7637 dev->features |= NETIF_F_HIGHDMA;
7638 } else {
7639 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7640 if (rc < 0) {
7641 netif_err(tp, probe, dev, "DMA configuration failed\n");
7642 goto err_out_free_res_3;
7643 }
7644 }
7645
7646 /* ioremap MMIO region */
7647 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7648 if (!ioaddr) {
7649 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7650 rc = -EIO;
7651 goto err_out_free_res_3;
7652 }
7653 tp->mmio_addr = ioaddr;
7654
7655 if (!pci_is_pcie(pdev))
7656 netif_info(tp, probe, dev, "not PCI Express\n");
7657
7658 /* Identify chip attached to board */
7659 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7660
7661 rtl_init_rxcfg(tp);
7662
7663 rtl_irq_disable(tp);
7664
7665 rtl_hw_initialize(tp);
7666
7667 rtl_hw_reset(tp);
7668
7669 rtl_ack_events(tp, 0xffff);
7670
7671 pci_set_master(pdev);
7672
7673 rtl_init_mdio_ops(tp);
7674 rtl_init_pll_power_ops(tp);
7675 rtl_init_jumbo_ops(tp);
7676 rtl_init_csi_ops(tp);
7677
7678 rtl8169_print_mac_version(tp);
7679
7680 chipset = tp->mac_version;
7681 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7682
7683 RTL_W8(Cfg9346, Cfg9346_Unlock);
7684 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7685 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
7686 switch (tp->mac_version) {
7687 case RTL_GIGA_MAC_VER_34:
7688 case RTL_GIGA_MAC_VER_35:
7689 case RTL_GIGA_MAC_VER_36:
7690 case RTL_GIGA_MAC_VER_37:
7691 case RTL_GIGA_MAC_VER_38:
7692 case RTL_GIGA_MAC_VER_40:
7693 case RTL_GIGA_MAC_VER_41:
7694 case RTL_GIGA_MAC_VER_42:
7695 case RTL_GIGA_MAC_VER_43:
7696 case RTL_GIGA_MAC_VER_44:
7697 case RTL_GIGA_MAC_VER_45:
7698 case RTL_GIGA_MAC_VER_46:
7699 case RTL_GIGA_MAC_VER_47:
7700 case RTL_GIGA_MAC_VER_48:
7701 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
7702 tp->features |= RTL_FEATURE_WOL;
7703 if ((RTL_R8(Config3) & LinkUp) != 0)
7704 tp->features |= RTL_FEATURE_WOL;
7705 break;
7706 default:
7707 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7708 tp->features |= RTL_FEATURE_WOL;
7709 break;
7710 }
7711 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7712 tp->features |= RTL_FEATURE_WOL;
7713 tp->features |= rtl_try_msi(tp, cfg);
7714 RTL_W8(Cfg9346, Cfg9346_Lock);
7715
7716 if (rtl_tbi_enabled(tp)) {
7717 tp->set_speed = rtl8169_set_speed_tbi;
7718 tp->get_settings = rtl8169_gset_tbi;
7719 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7720 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7721 tp->link_ok = rtl8169_tbi_link_ok;
7722 tp->do_ioctl = rtl_tbi_ioctl;
7723 } else {
7724 tp->set_speed = rtl8169_set_speed_xmii;
7725 tp->get_settings = rtl8169_gset_xmii;
7726 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7727 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7728 tp->link_ok = rtl8169_xmii_link_ok;
7729 tp->do_ioctl = rtl_xmii_ioctl;
7730 }
7731
7732 mutex_init(&tp->wk.mutex);
7733 u64_stats_init(&tp->rx_stats.syncp);
7734 u64_stats_init(&tp->tx_stats.syncp);
7735
7736 /* Get MAC address */
7737 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7738 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
7739 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
7740 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
7741 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
7742 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
7743 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
7744 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
7745 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
7746 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
7747 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
7748 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
7749 tp->mac_version == RTL_GIGA_MAC_VER_48) {
7750 u16 mac_addr[3];
7751
7752 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7753 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7754
7755 if (is_valid_ether_addr((u8 *)mac_addr))
7756 rtl_rar_set(tp, (u8 *)mac_addr);
7757 }
7758 for (i = 0; i < ETH_ALEN; i++)
7759 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7760
7761 dev->ethtool_ops = &rtl8169_ethtool_ops;
7762 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7763
7764 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7765
7766 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7767 * properly for all devices */
7768 dev->features |= NETIF_F_RXCSUM |
7769 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7770
7771 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7772 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7773 NETIF_F_HW_VLAN_CTAG_RX;
7774 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7775 NETIF_F_HIGHDMA;
7776
7777 tp->cp_cmd |= RxChkSum | RxVlan;
7778
7779 /*
7780 * Pretend we are using VLANs; This bypasses a nasty bug where
7781 * Interrupts stop flowing on high load on 8110SCd controllers.
7782 */
7783 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7784 /* Disallow toggling */
7785 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7786
7787 if (tp->txd_version == RTL_TD_0)
7788 tp->tso_csum = rtl8169_tso_csum_v1;
7789 else if (tp->txd_version == RTL_TD_1) {
7790 tp->tso_csum = rtl8169_tso_csum_v2;
7791 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7792 } else
7793 WARN_ON_ONCE(1);
7794
7795 dev->hw_features |= NETIF_F_RXALL;
7796 dev->hw_features |= NETIF_F_RXFCS;
7797
7798 tp->hw_start = cfg->hw_start;
7799 tp->event_slow = cfg->event_slow;
7800
7801 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7802 ~(RxBOVF | RxFOVF) : ~0;
7803
7804 init_timer(&tp->timer);
7805 tp->timer.data = (unsigned long) dev;
7806 tp->timer.function = rtl8169_phy_timer;
7807
7808 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7809
7810 rc = register_netdev(dev);
7811 if (rc < 0)
7812 goto err_out_msi_4;
7813
7814 pci_set_drvdata(pdev, dev);
7815
7816 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7817 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7818 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7819 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7820 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7821 "tx checksumming: %s]\n",
7822 rtl_chip_infos[chipset].jumbo_max,
7823 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7824 }
7825
7826 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7827 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7828 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
7829 r8168_check_dash(tp)) {
7830 rtl8168_driver_start(tp);
7831 }
7832
7833 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7834
7835 if (pci_dev_run_wake(pdev))
7836 pm_runtime_put_noidle(&pdev->dev);
7837
7838 netif_carrier_off(dev);
7839
7840 out:
7841 return rc;
7842
7843 err_out_msi_4:
7844 netif_napi_del(&tp->napi);
7845 rtl_disable_msi(pdev, tp);
7846 iounmap(ioaddr);
7847 err_out_free_res_3:
7848 pci_release_regions(pdev);
7849 err_out_mwi_2:
7850 pci_clear_mwi(pdev);
7851 pci_disable_device(pdev);
7852 err_out_free_dev_1:
7853 free_netdev(dev);
7854 goto out;
7855 }
7856
7857 static struct pci_driver rtl8169_pci_driver = {
7858 .name = MODULENAME,
7859 .id_table = rtl8169_pci_tbl,
7860 .probe = rtl_init_one,
7861 .remove = rtl_remove_one,
7862 .shutdown = rtl_shutdown,
7863 .driver.pm = RTL8169_PM_OPS,
7864 };
7865
7866 module_pci_driver(rtl8169_pci_driver);
Linux kernel - Deliverables
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