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r8169: fix Config2 MSIEnable bit setting.
[deliverable/linux.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
31
32 #include <asm/system.h>
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48
49 #ifdef RTL8169_DEBUG
50 #define assert(expr) \
51 if (!(expr)) { \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
53 #expr,__FILE__,__func__,__LINE__); \
54 }
55 #define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
57 #else
58 #define assert(expr) do {} while (0)
59 #define dprintk(fmt, args...) do {} while (0)
60 #endif /* RTL8169_DEBUG */
61
62 #define R8169_MSG_DEFAULT \
63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
64
65 #define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
67
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit = 32;
71
72 /* MAC address length */
73 #define MAC_ADDR_LEN 6
74
75 #define MAX_READ_REQUEST_SHIFT 12
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
78 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
79
80 #define R8169_REGS_SIZE 256
81 #define R8169_NAPI_WEIGHT 64
82 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
83 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
84 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
85 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
86 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
87
88 #define RTL8169_TX_TIMEOUT (6*HZ)
89 #define RTL8169_PHY_TIMEOUT (10*HZ)
90
91 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
92 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
93 #define RTL_EEPROM_SIG_ADDR 0x0000
94
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
102
103 enum mac_version {
104 RTL_GIGA_MAC_VER_01 = 0,
105 RTL_GIGA_MAC_VER_02,
106 RTL_GIGA_MAC_VER_03,
107 RTL_GIGA_MAC_VER_04,
108 RTL_GIGA_MAC_VER_05,
109 RTL_GIGA_MAC_VER_06,
110 RTL_GIGA_MAC_VER_07,
111 RTL_GIGA_MAC_VER_08,
112 RTL_GIGA_MAC_VER_09,
113 RTL_GIGA_MAC_VER_10,
114 RTL_GIGA_MAC_VER_11,
115 RTL_GIGA_MAC_VER_12,
116 RTL_GIGA_MAC_VER_13,
117 RTL_GIGA_MAC_VER_14,
118 RTL_GIGA_MAC_VER_15,
119 RTL_GIGA_MAC_VER_16,
120 RTL_GIGA_MAC_VER_17,
121 RTL_GIGA_MAC_VER_18,
122 RTL_GIGA_MAC_VER_19,
123 RTL_GIGA_MAC_VER_20,
124 RTL_GIGA_MAC_VER_21,
125 RTL_GIGA_MAC_VER_22,
126 RTL_GIGA_MAC_VER_23,
127 RTL_GIGA_MAC_VER_24,
128 RTL_GIGA_MAC_VER_25,
129 RTL_GIGA_MAC_VER_26,
130 RTL_GIGA_MAC_VER_27,
131 RTL_GIGA_MAC_VER_28,
132 RTL_GIGA_MAC_VER_29,
133 RTL_GIGA_MAC_VER_30,
134 RTL_GIGA_MAC_VER_31,
135 RTL_GIGA_MAC_VER_32,
136 RTL_GIGA_MAC_VER_33,
137 RTL_GIGA_MAC_VER_34,
138 RTL_GIGA_MAC_VER_35,
139 RTL_GIGA_MAC_VER_36,
140 RTL_GIGA_MAC_NONE = 0xff,
141 };
142
143 enum rtl_tx_desc_version {
144 RTL_TD_0 = 0,
145 RTL_TD_1 = 1,
146 };
147
148 #define JUMBO_1K ETH_DATA_LEN
149 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
150 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
151 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
152 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
153
154 #define _R(NAME,TD,FW,SZ,B) { \
155 .name = NAME, \
156 .txd_version = TD, \
157 .fw_name = FW, \
158 .jumbo_max = SZ, \
159 .jumbo_tx_csum = B \
160 }
161
162 static const struct {
163 const char *name;
164 enum rtl_tx_desc_version txd_version;
165 const char *fw_name;
166 u16 jumbo_max;
167 bool jumbo_tx_csum;
168 } rtl_chip_infos[] = {
169 /* PCI devices. */
170 [RTL_GIGA_MAC_VER_01] =
171 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
172 [RTL_GIGA_MAC_VER_02] =
173 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
174 [RTL_GIGA_MAC_VER_03] =
175 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
176 [RTL_GIGA_MAC_VER_04] =
177 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
178 [RTL_GIGA_MAC_VER_05] =
179 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
180 [RTL_GIGA_MAC_VER_06] =
181 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
182 /* PCI-E devices. */
183 [RTL_GIGA_MAC_VER_07] =
184 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
185 [RTL_GIGA_MAC_VER_08] =
186 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
187 [RTL_GIGA_MAC_VER_09] =
188 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
189 [RTL_GIGA_MAC_VER_10] =
190 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
191 [RTL_GIGA_MAC_VER_11] =
192 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
193 [RTL_GIGA_MAC_VER_12] =
194 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
195 [RTL_GIGA_MAC_VER_13] =
196 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
197 [RTL_GIGA_MAC_VER_14] =
198 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
199 [RTL_GIGA_MAC_VER_15] =
200 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
201 [RTL_GIGA_MAC_VER_16] =
202 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
203 [RTL_GIGA_MAC_VER_17] =
204 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
205 [RTL_GIGA_MAC_VER_18] =
206 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
207 [RTL_GIGA_MAC_VER_19] =
208 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
209 [RTL_GIGA_MAC_VER_20] =
210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
211 [RTL_GIGA_MAC_VER_21] =
212 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
213 [RTL_GIGA_MAC_VER_22] =
214 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
215 [RTL_GIGA_MAC_VER_23] =
216 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
217 [RTL_GIGA_MAC_VER_24] =
218 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
219 [RTL_GIGA_MAC_VER_25] =
220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
221 JUMBO_9K, false),
222 [RTL_GIGA_MAC_VER_26] =
223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
224 JUMBO_9K, false),
225 [RTL_GIGA_MAC_VER_27] =
226 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
227 [RTL_GIGA_MAC_VER_28] =
228 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
229 [RTL_GIGA_MAC_VER_29] =
230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
231 JUMBO_1K, true),
232 [RTL_GIGA_MAC_VER_30] =
233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
234 JUMBO_1K, true),
235 [RTL_GIGA_MAC_VER_31] =
236 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
237 [RTL_GIGA_MAC_VER_32] =
238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
239 JUMBO_9K, false),
240 [RTL_GIGA_MAC_VER_33] =
241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
242 JUMBO_9K, false),
243 [RTL_GIGA_MAC_VER_34] =
244 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
245 JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_35] =
247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
248 JUMBO_9K, false),
249 [RTL_GIGA_MAC_VER_36] =
250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
251 JUMBO_9K, false),
252 };
253 #undef _R
254
255 enum cfg_version {
256 RTL_CFG_0 = 0x00,
257 RTL_CFG_1,
258 RTL_CFG_2
259 };
260
261 static void rtl_hw_start_8169(struct net_device *);
262 static void rtl_hw_start_8168(struct net_device *);
263 static void rtl_hw_start_8101(struct net_device *);
264
265 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
268 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
269 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
270 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
271 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
272 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
273 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
274 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
275 { PCI_VENDOR_ID_LINKSYS, 0x1032,
276 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
277 { 0x0001, 0x8168,
278 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
279 {0,},
280 };
281
282 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
283
284 static int rx_buf_sz = 16383;
285 static int use_dac;
286 static struct {
287 u32 msg_enable;
288 } debug = { -1 };
289
290 enum rtl_registers {
291 MAC0 = 0, /* Ethernet hardware address. */
292 MAC4 = 4,
293 MAR0 = 8, /* Multicast filter. */
294 CounterAddrLow = 0x10,
295 CounterAddrHigh = 0x14,
296 TxDescStartAddrLow = 0x20,
297 TxDescStartAddrHigh = 0x24,
298 TxHDescStartAddrLow = 0x28,
299 TxHDescStartAddrHigh = 0x2c,
300 FLASH = 0x30,
301 ERSR = 0x36,
302 ChipCmd = 0x37,
303 TxPoll = 0x38,
304 IntrMask = 0x3c,
305 IntrStatus = 0x3e,
306
307 TxConfig = 0x40,
308 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
309 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
310
311 RxConfig = 0x44,
312 #define RX128_INT_EN (1 << 15) /* 8111c and later */
313 #define RX_MULTI_EN (1 << 14) /* 8111c only */
314 #define RXCFG_FIFO_SHIFT 13
315 /* No threshold before first PCI xfer */
316 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
317 #define RXCFG_DMA_SHIFT 8
318 /* Unlimited maximum PCI burst. */
319 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
320
321 RxMissed = 0x4c,
322 Cfg9346 = 0x50,
323 Config0 = 0x51,
324 Config1 = 0x52,
325 Config2 = 0x53,
326 Config3 = 0x54,
327 Config4 = 0x55,
328 Config5 = 0x56,
329 MultiIntr = 0x5c,
330 PHYAR = 0x60,
331 PHYstatus = 0x6c,
332 RxMaxSize = 0xda,
333 CPlusCmd = 0xe0,
334 IntrMitigate = 0xe2,
335 RxDescAddrLow = 0xe4,
336 RxDescAddrHigh = 0xe8,
337 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
338
339 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
340
341 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
342
343 #define TxPacketMax (8064 >> 7)
344 #define EarlySize 0x27
345
346 FuncEvent = 0xf0,
347 FuncEventMask = 0xf4,
348 FuncPresetState = 0xf8,
349 FuncForceEvent = 0xfc,
350 };
351
352 enum rtl8110_registers {
353 TBICSR = 0x64,
354 TBI_ANAR = 0x68,
355 TBI_LPAR = 0x6a,
356 };
357
358 enum rtl8168_8101_registers {
359 CSIDR = 0x64,
360 CSIAR = 0x68,
361 #define CSIAR_FLAG 0x80000000
362 #define CSIAR_WRITE_CMD 0x80000000
363 #define CSIAR_BYTE_ENABLE 0x0f
364 #define CSIAR_BYTE_ENABLE_SHIFT 12
365 #define CSIAR_ADDR_MASK 0x0fff
366 PMCH = 0x6f,
367 EPHYAR = 0x80,
368 #define EPHYAR_FLAG 0x80000000
369 #define EPHYAR_WRITE_CMD 0x80000000
370 #define EPHYAR_REG_MASK 0x1f
371 #define EPHYAR_REG_SHIFT 16
372 #define EPHYAR_DATA_MASK 0xffff
373 DLLPR = 0xd0,
374 #define PFM_EN (1 << 6)
375 DBG_REG = 0xd1,
376 #define FIX_NAK_1 (1 << 4)
377 #define FIX_NAK_2 (1 << 3)
378 TWSI = 0xd2,
379 MCU = 0xd3,
380 #define NOW_IS_OOB (1 << 7)
381 #define EN_NDP (1 << 3)
382 #define EN_OOB_RESET (1 << 2)
383 EFUSEAR = 0xdc,
384 #define EFUSEAR_FLAG 0x80000000
385 #define EFUSEAR_WRITE_CMD 0x80000000
386 #define EFUSEAR_READ_CMD 0x00000000
387 #define EFUSEAR_REG_MASK 0x03ff
388 #define EFUSEAR_REG_SHIFT 8
389 #define EFUSEAR_DATA_MASK 0xff
390 };
391
392 enum rtl8168_registers {
393 LED_FREQ = 0x1a,
394 EEE_LED = 0x1b,
395 ERIDR = 0x70,
396 ERIAR = 0x74,
397 #define ERIAR_FLAG 0x80000000
398 #define ERIAR_WRITE_CMD 0x80000000
399 #define ERIAR_READ_CMD 0x00000000
400 #define ERIAR_ADDR_BYTE_ALIGN 4
401 #define ERIAR_TYPE_SHIFT 16
402 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
403 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
404 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
405 #define ERIAR_MASK_SHIFT 12
406 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
407 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
408 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
409 EPHY_RXER_NUM = 0x7c,
410 OCPDR = 0xb0, /* OCP GPHY access */
411 #define OCPDR_WRITE_CMD 0x80000000
412 #define OCPDR_READ_CMD 0x00000000
413 #define OCPDR_REG_MASK 0x7f
414 #define OCPDR_GPHY_REG_SHIFT 16
415 #define OCPDR_DATA_MASK 0xffff
416 OCPAR = 0xb4,
417 #define OCPAR_FLAG 0x80000000
418 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
419 #define OCPAR_GPHY_READ_CMD 0x0000f060
420 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
421 MISC = 0xf0, /* 8168e only. */
422 #define TXPLA_RST (1 << 29)
423 #define PWM_EN (1 << 22)
424 };
425
426 enum rtl_register_content {
427 /* InterruptStatusBits */
428 SYSErr = 0x8000,
429 PCSTimeout = 0x4000,
430 SWInt = 0x0100,
431 TxDescUnavail = 0x0080,
432 RxFIFOOver = 0x0040,
433 LinkChg = 0x0020,
434 RxOverflow = 0x0010,
435 TxErr = 0x0008,
436 TxOK = 0x0004,
437 RxErr = 0x0002,
438 RxOK = 0x0001,
439
440 /* RxStatusDesc */
441 RxBOVF = (1 << 24),
442 RxFOVF = (1 << 23),
443 RxRWT = (1 << 22),
444 RxRES = (1 << 21),
445 RxRUNT = (1 << 20),
446 RxCRC = (1 << 19),
447
448 /* ChipCmdBits */
449 StopReq = 0x80,
450 CmdReset = 0x10,
451 CmdRxEnb = 0x08,
452 CmdTxEnb = 0x04,
453 RxBufEmpty = 0x01,
454
455 /* TXPoll register p.5 */
456 HPQ = 0x80, /* Poll cmd on the high prio queue */
457 NPQ = 0x40, /* Poll cmd on the low prio queue */
458 FSWInt = 0x01, /* Forced software interrupt */
459
460 /* Cfg9346Bits */
461 Cfg9346_Lock = 0x00,
462 Cfg9346_Unlock = 0xc0,
463
464 /* rx_mode_bits */
465 AcceptErr = 0x20,
466 AcceptRunt = 0x10,
467 AcceptBroadcast = 0x08,
468 AcceptMulticast = 0x04,
469 AcceptMyPhys = 0x02,
470 AcceptAllPhys = 0x01,
471 #define RX_CONFIG_ACCEPT_MASK 0x3f
472
473 /* TxConfigBits */
474 TxInterFrameGapShift = 24,
475 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
476
477 /* Config1 register p.24 */
478 LEDS1 = (1 << 7),
479 LEDS0 = (1 << 6),
480 Speed_down = (1 << 4),
481 MEMMAP = (1 << 3),
482 IOMAP = (1 << 2),
483 VPD = (1 << 1),
484 PMEnable = (1 << 0), /* Power Management Enable */
485
486 /* Config2 register p. 25 */
487 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
488 PCI_Clock_66MHz = 0x01,
489 PCI_Clock_33MHz = 0x00,
490
491 /* Config3 register p.25 */
492 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
493 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
494 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
495 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
496
497 /* Config4 register */
498 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
499
500 /* Config5 register p.27 */
501 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
502 MWF = (1 << 5), /* Accept Multicast wakeup frame */
503 UWF = (1 << 4), /* Accept Unicast wakeup frame */
504 Spi_en = (1 << 3),
505 LanWake = (1 << 1), /* LanWake enable/disable */
506 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
507
508 /* TBICSR p.28 */
509 TBIReset = 0x80000000,
510 TBILoopback = 0x40000000,
511 TBINwEnable = 0x20000000,
512 TBINwRestart = 0x10000000,
513 TBILinkOk = 0x02000000,
514 TBINwComplete = 0x01000000,
515
516 /* CPlusCmd p.31 */
517 EnableBist = (1 << 15), // 8168 8101
518 Mac_dbgo_oe = (1 << 14), // 8168 8101
519 Normal_mode = (1 << 13), // unused
520 Force_half_dup = (1 << 12), // 8168 8101
521 Force_rxflow_en = (1 << 11), // 8168 8101
522 Force_txflow_en = (1 << 10), // 8168 8101
523 Cxpl_dbg_sel = (1 << 9), // 8168 8101
524 ASF = (1 << 8), // 8168 8101
525 PktCntrDisable = (1 << 7), // 8168 8101
526 Mac_dbgo_sel = 0x001c, // 8168
527 RxVlan = (1 << 6),
528 RxChkSum = (1 << 5),
529 PCIDAC = (1 << 4),
530 PCIMulRW = (1 << 3),
531 INTT_0 = 0x0000, // 8168
532 INTT_1 = 0x0001, // 8168
533 INTT_2 = 0x0002, // 8168
534 INTT_3 = 0x0003, // 8168
535
536 /* rtl8169_PHYstatus */
537 TBI_Enable = 0x80,
538 TxFlowCtrl = 0x40,
539 RxFlowCtrl = 0x20,
540 _1000bpsF = 0x10,
541 _100bps = 0x08,
542 _10bps = 0x04,
543 LinkStatus = 0x02,
544 FullDup = 0x01,
545
546 /* _TBICSRBit */
547 TBILinkOK = 0x02000000,
548
549 /* DumpCounterCommand */
550 CounterDump = 0x8,
551 };
552
553 enum rtl_desc_bit {
554 /* First doubleword. */
555 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
556 RingEnd = (1 << 30), /* End of descriptor ring */
557 FirstFrag = (1 << 29), /* First segment of a packet */
558 LastFrag = (1 << 28), /* Final segment of a packet */
559 };
560
561 /* Generic case. */
562 enum rtl_tx_desc_bit {
563 /* First doubleword. */
564 TD_LSO = (1 << 27), /* Large Send Offload */
565 #define TD_MSS_MAX 0x07ffu /* MSS value */
566
567 /* Second doubleword. */
568 TxVlanTag = (1 << 17), /* Add VLAN tag */
569 };
570
571 /* 8169, 8168b and 810x except 8102e. */
572 enum rtl_tx_desc_bit_0 {
573 /* First doubleword. */
574 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
575 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
576 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
577 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
578 };
579
580 /* 8102e, 8168c and beyond. */
581 enum rtl_tx_desc_bit_1 {
582 /* Second doubleword. */
583 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
584 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
585 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
586 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
587 };
588
589 static const struct rtl_tx_desc_info {
590 struct {
591 u32 udp;
592 u32 tcp;
593 } checksum;
594 u16 mss_shift;
595 u16 opts_offset;
596 } tx_desc_info [] = {
597 [RTL_TD_0] = {
598 .checksum = {
599 .udp = TD0_IP_CS | TD0_UDP_CS,
600 .tcp = TD0_IP_CS | TD0_TCP_CS
601 },
602 .mss_shift = TD0_MSS_SHIFT,
603 .opts_offset = 0
604 },
605 [RTL_TD_1] = {
606 .checksum = {
607 .udp = TD1_IP_CS | TD1_UDP_CS,
608 .tcp = TD1_IP_CS | TD1_TCP_CS
609 },
610 .mss_shift = TD1_MSS_SHIFT,
611 .opts_offset = 1
612 }
613 };
614
615 enum rtl_rx_desc_bit {
616 /* Rx private */
617 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
618 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
619
620 #define RxProtoUDP (PID1)
621 #define RxProtoTCP (PID0)
622 #define RxProtoIP (PID1 | PID0)
623 #define RxProtoMask RxProtoIP
624
625 IPFail = (1 << 16), /* IP checksum failed */
626 UDPFail = (1 << 15), /* UDP/IP checksum failed */
627 TCPFail = (1 << 14), /* TCP/IP checksum failed */
628 RxVlanTag = (1 << 16), /* VLAN tag available */
629 };
630
631 #define RsvdMask 0x3fffc000
632
633 struct TxDesc {
634 __le32 opts1;
635 __le32 opts2;
636 __le64 addr;
637 };
638
639 struct RxDesc {
640 __le32 opts1;
641 __le32 opts2;
642 __le64 addr;
643 };
644
645 struct ring_info {
646 struct sk_buff *skb;
647 u32 len;
648 u8 __pad[sizeof(void *) - sizeof(u32)];
649 };
650
651 enum features {
652 RTL_FEATURE_WOL = (1 << 0),
653 RTL_FEATURE_MSI = (1 << 1),
654 RTL_FEATURE_GMII = (1 << 2),
655 };
656
657 struct rtl8169_counters {
658 __le64 tx_packets;
659 __le64 rx_packets;
660 __le64 tx_errors;
661 __le32 rx_errors;
662 __le16 rx_missed;
663 __le16 align_errors;
664 __le32 tx_one_collision;
665 __le32 tx_multi_collision;
666 __le64 rx_unicast;
667 __le64 rx_broadcast;
668 __le32 rx_multicast;
669 __le16 tx_aborted;
670 __le16 tx_underun;
671 };
672
673 struct rtl8169_private {
674 void __iomem *mmio_addr; /* memory map physical address */
675 struct pci_dev *pci_dev;
676 struct net_device *dev;
677 struct napi_struct napi;
678 spinlock_t lock;
679 u32 msg_enable;
680 u16 txd_version;
681 u16 mac_version;
682 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
683 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
684 u32 dirty_rx;
685 u32 dirty_tx;
686 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
687 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
688 dma_addr_t TxPhyAddr;
689 dma_addr_t RxPhyAddr;
690 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
691 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
692 struct timer_list timer;
693 u16 cp_cmd;
694 u16 intr_event;
695 u16 napi_event;
696 u16 intr_mask;
697
698 struct mdio_ops {
699 void (*write)(void __iomem *, int, int);
700 int (*read)(void __iomem *, int);
701 } mdio_ops;
702
703 struct pll_power_ops {
704 void (*down)(struct rtl8169_private *);
705 void (*up)(struct rtl8169_private *);
706 } pll_power_ops;
707
708 struct jumbo_ops {
709 void (*enable)(struct rtl8169_private *);
710 void (*disable)(struct rtl8169_private *);
711 } jumbo_ops;
712
713 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
714 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
715 void (*phy_reset_enable)(struct rtl8169_private *tp);
716 void (*hw_start)(struct net_device *);
717 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
718 unsigned int (*link_ok)(void __iomem *);
719 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
720 struct delayed_work task;
721 unsigned features;
722
723 struct mii_if_info mii;
724 struct rtl8169_counters counters;
725 u32 saved_wolopts;
726 u32 opts1_mask;
727
728 struct rtl_fw {
729 const struct firmware *fw;
730
731 #define RTL_VER_SIZE 32
732
733 char version[RTL_VER_SIZE];
734
735 struct rtl_fw_phy_action {
736 __le32 *code;
737 size_t size;
738 } phy_action;
739 } *rtl_fw;
740 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
741 };
742
743 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
744 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
745 module_param(use_dac, int, 0);
746 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
747 module_param_named(debug, debug.msg_enable, int, 0);
748 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
749 MODULE_LICENSE("GPL");
750 MODULE_VERSION(RTL8169_VERSION);
751 MODULE_FIRMWARE(FIRMWARE_8168D_1);
752 MODULE_FIRMWARE(FIRMWARE_8168D_2);
753 MODULE_FIRMWARE(FIRMWARE_8168E_1);
754 MODULE_FIRMWARE(FIRMWARE_8168E_2);
755 MODULE_FIRMWARE(FIRMWARE_8168E_3);
756 MODULE_FIRMWARE(FIRMWARE_8105E_1);
757 MODULE_FIRMWARE(FIRMWARE_8168F_1);
758 MODULE_FIRMWARE(FIRMWARE_8168F_2);
759
760 static int rtl8169_open(struct net_device *dev);
761 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
762 struct net_device *dev);
763 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
764 static int rtl8169_init_ring(struct net_device *dev);
765 static void rtl_hw_start(struct net_device *dev);
766 static int rtl8169_close(struct net_device *dev);
767 static void rtl_set_rx_mode(struct net_device *dev);
768 static void rtl8169_tx_timeout(struct net_device *dev);
769 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
770 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
771 void __iomem *, u32 budget);
772 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
773 static void rtl8169_down(struct net_device *dev);
774 static void rtl8169_rx_clear(struct rtl8169_private *tp);
775 static int rtl8169_poll(struct napi_struct *napi, int budget);
776
777 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
778 {
779 int cap = pci_pcie_cap(pdev);
780
781 if (cap) {
782 u16 ctl;
783
784 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
785 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
786 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
787 }
788 }
789
790 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
791 {
792 void __iomem *ioaddr = tp->mmio_addr;
793 int i;
794
795 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
796 for (i = 0; i < 20; i++) {
797 udelay(100);
798 if (RTL_R32(OCPAR) & OCPAR_FLAG)
799 break;
800 }
801 return RTL_R32(OCPDR);
802 }
803
804 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
805 {
806 void __iomem *ioaddr = tp->mmio_addr;
807 int i;
808
809 RTL_W32(OCPDR, data);
810 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
811 for (i = 0; i < 20; i++) {
812 udelay(100);
813 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
814 break;
815 }
816 }
817
818 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
819 {
820 void __iomem *ioaddr = tp->mmio_addr;
821 int i;
822
823 RTL_W8(ERIDR, cmd);
824 RTL_W32(ERIAR, 0x800010e8);
825 msleep(2);
826 for (i = 0; i < 5; i++) {
827 udelay(100);
828 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
829 break;
830 }
831
832 ocp_write(tp, 0x1, 0x30, 0x00000001);
833 }
834
835 #define OOB_CMD_RESET 0x00
836 #define OOB_CMD_DRIVER_START 0x05
837 #define OOB_CMD_DRIVER_STOP 0x06
838
839 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
840 {
841 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
842 }
843
844 static void rtl8168_driver_start(struct rtl8169_private *tp)
845 {
846 u16 reg;
847 int i;
848
849 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
850
851 reg = rtl8168_get_ocp_reg(tp);
852
853 for (i = 0; i < 10; i++) {
854 msleep(10);
855 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
856 break;
857 }
858 }
859
860 static void rtl8168_driver_stop(struct rtl8169_private *tp)
861 {
862 u16 reg;
863 int i;
864
865 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
866
867 reg = rtl8168_get_ocp_reg(tp);
868
869 for (i = 0; i < 10; i++) {
870 msleep(10);
871 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
872 break;
873 }
874 }
875
876 static int r8168dp_check_dash(struct rtl8169_private *tp)
877 {
878 u16 reg = rtl8168_get_ocp_reg(tp);
879
880 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
881 }
882
883 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
884 {
885 int i;
886
887 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
888
889 for (i = 20; i > 0; i--) {
890 /*
891 * Check if the RTL8169 has completed writing to the specified
892 * MII register.
893 */
894 if (!(RTL_R32(PHYAR) & 0x80000000))
895 break;
896 udelay(25);
897 }
898 /*
899 * According to hardware specs a 20us delay is required after write
900 * complete indication, but before sending next command.
901 */
902 udelay(20);
903 }
904
905 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
906 {
907 int i, value = -1;
908
909 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
910
911 for (i = 20; i > 0; i--) {
912 /*
913 * Check if the RTL8169 has completed retrieving data from
914 * the specified MII register.
915 */
916 if (RTL_R32(PHYAR) & 0x80000000) {
917 value = RTL_R32(PHYAR) & 0xffff;
918 break;
919 }
920 udelay(25);
921 }
922 /*
923 * According to hardware specs a 20us delay is required after read
924 * complete indication, but before sending next command.
925 */
926 udelay(20);
927
928 return value;
929 }
930
931 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
932 {
933 int i;
934
935 RTL_W32(OCPDR, data |
936 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
937 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
938 RTL_W32(EPHY_RXER_NUM, 0);
939
940 for (i = 0; i < 100; i++) {
941 mdelay(1);
942 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
943 break;
944 }
945 }
946
947 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
948 {
949 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
950 (value & OCPDR_DATA_MASK));
951 }
952
953 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
954 {
955 int i;
956
957 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
958
959 mdelay(1);
960 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
961 RTL_W32(EPHY_RXER_NUM, 0);
962
963 for (i = 0; i < 100; i++) {
964 mdelay(1);
965 if (RTL_R32(OCPAR) & OCPAR_FLAG)
966 break;
967 }
968
969 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
970 }
971
972 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
973
974 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
975 {
976 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
977 }
978
979 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
980 {
981 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
982 }
983
984 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
985 {
986 r8168dp_2_mdio_start(ioaddr);
987
988 r8169_mdio_write(ioaddr, reg_addr, value);
989
990 r8168dp_2_mdio_stop(ioaddr);
991 }
992
993 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
994 {
995 int value;
996
997 r8168dp_2_mdio_start(ioaddr);
998
999 value = r8169_mdio_read(ioaddr, reg_addr);
1000
1001 r8168dp_2_mdio_stop(ioaddr);
1002
1003 return value;
1004 }
1005
1006 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1007 {
1008 tp->mdio_ops.write(tp->mmio_addr, location, val);
1009 }
1010
1011 static int rtl_readphy(struct rtl8169_private *tp, int location)
1012 {
1013 return tp->mdio_ops.read(tp->mmio_addr, location);
1014 }
1015
1016 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1017 {
1018 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1019 }
1020
1021 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1022 {
1023 int val;
1024
1025 val = rtl_readphy(tp, reg_addr);
1026 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1027 }
1028
1029 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1030 int val)
1031 {
1032 struct rtl8169_private *tp = netdev_priv(dev);
1033
1034 rtl_writephy(tp, location, val);
1035 }
1036
1037 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1038 {
1039 struct rtl8169_private *tp = netdev_priv(dev);
1040
1041 return rtl_readphy(tp, location);
1042 }
1043
1044 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1045 {
1046 unsigned int i;
1047
1048 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
1051 for (i = 0; i < 100; i++) {
1052 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1053 break;
1054 udelay(10);
1055 }
1056 }
1057
1058 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1059 {
1060 u16 value = 0xffff;
1061 unsigned int i;
1062
1063 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1064
1065 for (i = 0; i < 100; i++) {
1066 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1067 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1068 break;
1069 }
1070 udelay(10);
1071 }
1072
1073 return value;
1074 }
1075
1076 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1077 {
1078 unsigned int i;
1079
1080 RTL_W32(CSIDR, value);
1081 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1082 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1083
1084 for (i = 0; i < 100; i++) {
1085 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1086 break;
1087 udelay(10);
1088 }
1089 }
1090
1091 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1092 {
1093 u32 value = ~0x00;
1094 unsigned int i;
1095
1096 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1097 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1098
1099 for (i = 0; i < 100; i++) {
1100 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1101 value = RTL_R32(CSIDR);
1102 break;
1103 }
1104 udelay(10);
1105 }
1106
1107 return value;
1108 }
1109
1110 static
1111 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1112 {
1113 unsigned int i;
1114
1115 BUG_ON((addr & 3) || (mask == 0));
1116 RTL_W32(ERIDR, val);
1117 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1118
1119 for (i = 0; i < 100; i++) {
1120 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1121 break;
1122 udelay(100);
1123 }
1124 }
1125
1126 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1127 {
1128 u32 value = ~0x00;
1129 unsigned int i;
1130
1131 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1132
1133 for (i = 0; i < 100; i++) {
1134 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1135 value = RTL_R32(ERIDR);
1136 break;
1137 }
1138 udelay(100);
1139 }
1140
1141 return value;
1142 }
1143
1144 static void
1145 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1146 {
1147 u32 val;
1148
1149 val = rtl_eri_read(ioaddr, addr, type);
1150 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1151 }
1152
1153 struct exgmac_reg {
1154 u16 addr;
1155 u16 mask;
1156 u32 val;
1157 };
1158
1159 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1160 const struct exgmac_reg *r, int len)
1161 {
1162 while (len-- > 0) {
1163 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1164 r++;
1165 }
1166 }
1167
1168 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1169 {
1170 u8 value = 0xff;
1171 unsigned int i;
1172
1173 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1174
1175 for (i = 0; i < 300; i++) {
1176 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1177 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1178 break;
1179 }
1180 udelay(100);
1181 }
1182
1183 return value;
1184 }
1185
1186 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1187 {
1188 void __iomem *ioaddr = tp->mmio_addr;
1189
1190 RTL_W16(IntrMask, 0x0000);
1191 RTL_W16(IntrStatus, tp->intr_event);
1192 RTL_R8(ChipCmd);
1193 }
1194
1195 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1196 {
1197 void __iomem *ioaddr = tp->mmio_addr;
1198
1199 return RTL_R32(TBICSR) & TBIReset;
1200 }
1201
1202 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1203 {
1204 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1205 }
1206
1207 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1208 {
1209 return RTL_R32(TBICSR) & TBILinkOk;
1210 }
1211
1212 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1213 {
1214 return RTL_R8(PHYstatus) & LinkStatus;
1215 }
1216
1217 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1218 {
1219 void __iomem *ioaddr = tp->mmio_addr;
1220
1221 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1222 }
1223
1224 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1225 {
1226 unsigned int val;
1227
1228 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1229 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1230 }
1231
1232 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1233 {
1234 void __iomem *ioaddr = tp->mmio_addr;
1235 struct net_device *dev = tp->dev;
1236
1237 if (!netif_running(dev))
1238 return;
1239
1240 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1241 if (RTL_R8(PHYstatus) & _1000bpsF) {
1242 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1243 0x00000011, ERIAR_EXGMAC);
1244 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1245 0x00000005, ERIAR_EXGMAC);
1246 } else if (RTL_R8(PHYstatus) & _100bps) {
1247 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1248 0x0000001f, ERIAR_EXGMAC);
1249 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1250 0x00000005, ERIAR_EXGMAC);
1251 } else {
1252 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1253 0x0000001f, ERIAR_EXGMAC);
1254 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1255 0x0000003f, ERIAR_EXGMAC);
1256 }
1257 /* Reset packet filter */
1258 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1259 ERIAR_EXGMAC);
1260 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1261 ERIAR_EXGMAC);
1262 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1263 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1264 if (RTL_R8(PHYstatus) & _1000bpsF) {
1265 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1266 0x00000011, ERIAR_EXGMAC);
1267 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1268 0x00000005, ERIAR_EXGMAC);
1269 } else {
1270 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1271 0x0000001f, ERIAR_EXGMAC);
1272 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1273 0x0000003f, ERIAR_EXGMAC);
1274 }
1275 }
1276 }
1277
1278 static void __rtl8169_check_link_status(struct net_device *dev,
1279 struct rtl8169_private *tp,
1280 void __iomem *ioaddr, bool pm)
1281 {
1282 unsigned long flags;
1283
1284 spin_lock_irqsave(&tp->lock, flags);
1285 if (tp->link_ok(ioaddr)) {
1286 rtl_link_chg_patch(tp);
1287 /* This is to cancel a scheduled suspend if there's one. */
1288 if (pm)
1289 pm_request_resume(&tp->pci_dev->dev);
1290 netif_carrier_on(dev);
1291 if (net_ratelimit())
1292 netif_info(tp, ifup, dev, "link up\n");
1293 } else {
1294 netif_carrier_off(dev);
1295 netif_info(tp, ifdown, dev, "link down\n");
1296 if (pm)
1297 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1298 }
1299 spin_unlock_irqrestore(&tp->lock, flags);
1300 }
1301
1302 static void rtl8169_check_link_status(struct net_device *dev,
1303 struct rtl8169_private *tp,
1304 void __iomem *ioaddr)
1305 {
1306 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1307 }
1308
1309 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1310
1311 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1312 {
1313 void __iomem *ioaddr = tp->mmio_addr;
1314 u8 options;
1315 u32 wolopts = 0;
1316
1317 options = RTL_R8(Config1);
1318 if (!(options & PMEnable))
1319 return 0;
1320
1321 options = RTL_R8(Config3);
1322 if (options & LinkUp)
1323 wolopts |= WAKE_PHY;
1324 if (options & MagicPacket)
1325 wolopts |= WAKE_MAGIC;
1326
1327 options = RTL_R8(Config5);
1328 if (options & UWF)
1329 wolopts |= WAKE_UCAST;
1330 if (options & BWF)
1331 wolopts |= WAKE_BCAST;
1332 if (options & MWF)
1333 wolopts |= WAKE_MCAST;
1334
1335 return wolopts;
1336 }
1337
1338 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1339 {
1340 struct rtl8169_private *tp = netdev_priv(dev);
1341
1342 spin_lock_irq(&tp->lock);
1343
1344 wol->supported = WAKE_ANY;
1345 wol->wolopts = __rtl8169_get_wol(tp);
1346
1347 spin_unlock_irq(&tp->lock);
1348 }
1349
1350 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1351 {
1352 void __iomem *ioaddr = tp->mmio_addr;
1353 unsigned int i;
1354 static const struct {
1355 u32 opt;
1356 u16 reg;
1357 u8 mask;
1358 } cfg[] = {
1359 { WAKE_ANY, Config1, PMEnable },
1360 { WAKE_PHY, Config3, LinkUp },
1361 { WAKE_MAGIC, Config3, MagicPacket },
1362 { WAKE_UCAST, Config5, UWF },
1363 { WAKE_BCAST, Config5, BWF },
1364 { WAKE_MCAST, Config5, MWF },
1365 { WAKE_ANY, Config5, LanWake }
1366 };
1367
1368 RTL_W8(Cfg9346, Cfg9346_Unlock);
1369
1370 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1371 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1372 if (wolopts & cfg[i].opt)
1373 options |= cfg[i].mask;
1374 RTL_W8(cfg[i].reg, options);
1375 }
1376
1377 RTL_W8(Cfg9346, Cfg9346_Lock);
1378 }
1379
1380 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1381 {
1382 struct rtl8169_private *tp = netdev_priv(dev);
1383
1384 spin_lock_irq(&tp->lock);
1385
1386 if (wol->wolopts)
1387 tp->features |= RTL_FEATURE_WOL;
1388 else
1389 tp->features &= ~RTL_FEATURE_WOL;
1390 __rtl8169_set_wol(tp, wol->wolopts);
1391 spin_unlock_irq(&tp->lock);
1392
1393 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1394
1395 return 0;
1396 }
1397
1398 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1399 {
1400 return rtl_chip_infos[tp->mac_version].fw_name;
1401 }
1402
1403 static void rtl8169_get_drvinfo(struct net_device *dev,
1404 struct ethtool_drvinfo *info)
1405 {
1406 struct rtl8169_private *tp = netdev_priv(dev);
1407 struct rtl_fw *rtl_fw = tp->rtl_fw;
1408
1409 strcpy(info->driver, MODULENAME);
1410 strcpy(info->version, RTL8169_VERSION);
1411 strcpy(info->bus_info, pci_name(tp->pci_dev));
1412 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1413 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1414 rtl_fw->version);
1415 }
1416
1417 static int rtl8169_get_regs_len(struct net_device *dev)
1418 {
1419 return R8169_REGS_SIZE;
1420 }
1421
1422 static int rtl8169_set_speed_tbi(struct net_device *dev,
1423 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1424 {
1425 struct rtl8169_private *tp = netdev_priv(dev);
1426 void __iomem *ioaddr = tp->mmio_addr;
1427 int ret = 0;
1428 u32 reg;
1429
1430 reg = RTL_R32(TBICSR);
1431 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1432 (duplex == DUPLEX_FULL)) {
1433 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1434 } else if (autoneg == AUTONEG_ENABLE)
1435 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1436 else {
1437 netif_warn(tp, link, dev,
1438 "incorrect speed setting refused in TBI mode\n");
1439 ret = -EOPNOTSUPP;
1440 }
1441
1442 return ret;
1443 }
1444
1445 static int rtl8169_set_speed_xmii(struct net_device *dev,
1446 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1447 {
1448 struct rtl8169_private *tp = netdev_priv(dev);
1449 int giga_ctrl, bmcr;
1450 int rc = -EINVAL;
1451
1452 rtl_writephy(tp, 0x1f, 0x0000);
1453
1454 if (autoneg == AUTONEG_ENABLE) {
1455 int auto_nego;
1456
1457 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1458 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1459 ADVERTISE_100HALF | ADVERTISE_100FULL);
1460
1461 if (adv & ADVERTISED_10baseT_Half)
1462 auto_nego |= ADVERTISE_10HALF;
1463 if (adv & ADVERTISED_10baseT_Full)
1464 auto_nego |= ADVERTISE_10FULL;
1465 if (adv & ADVERTISED_100baseT_Half)
1466 auto_nego |= ADVERTISE_100HALF;
1467 if (adv & ADVERTISED_100baseT_Full)
1468 auto_nego |= ADVERTISE_100FULL;
1469
1470 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1471
1472 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1473 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1474
1475 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1476 if (tp->mii.supports_gmii) {
1477 if (adv & ADVERTISED_1000baseT_Half)
1478 giga_ctrl |= ADVERTISE_1000HALF;
1479 if (adv & ADVERTISED_1000baseT_Full)
1480 giga_ctrl |= ADVERTISE_1000FULL;
1481 } else if (adv & (ADVERTISED_1000baseT_Half |
1482 ADVERTISED_1000baseT_Full)) {
1483 netif_info(tp, link, dev,
1484 "PHY does not support 1000Mbps\n");
1485 goto out;
1486 }
1487
1488 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1489
1490 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1491 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1492 } else {
1493 giga_ctrl = 0;
1494
1495 if (speed == SPEED_10)
1496 bmcr = 0;
1497 else if (speed == SPEED_100)
1498 bmcr = BMCR_SPEED100;
1499 else
1500 goto out;
1501
1502 if (duplex == DUPLEX_FULL)
1503 bmcr |= BMCR_FULLDPLX;
1504 }
1505
1506 rtl_writephy(tp, MII_BMCR, bmcr);
1507
1508 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1509 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1510 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1511 rtl_writephy(tp, 0x17, 0x2138);
1512 rtl_writephy(tp, 0x0e, 0x0260);
1513 } else {
1514 rtl_writephy(tp, 0x17, 0x2108);
1515 rtl_writephy(tp, 0x0e, 0x0000);
1516 }
1517 }
1518
1519 rc = 0;
1520 out:
1521 return rc;
1522 }
1523
1524 static int rtl8169_set_speed(struct net_device *dev,
1525 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1526 {
1527 struct rtl8169_private *tp = netdev_priv(dev);
1528 int ret;
1529
1530 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1531 if (ret < 0)
1532 goto out;
1533
1534 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1535 (advertising & ADVERTISED_1000baseT_Full)) {
1536 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1537 }
1538 out:
1539 return ret;
1540 }
1541
1542 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1543 {
1544 struct rtl8169_private *tp = netdev_priv(dev);
1545 unsigned long flags;
1546 int ret;
1547
1548 del_timer_sync(&tp->timer);
1549
1550 spin_lock_irqsave(&tp->lock, flags);
1551 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1552 cmd->duplex, cmd->advertising);
1553 spin_unlock_irqrestore(&tp->lock, flags);
1554
1555 return ret;
1556 }
1557
1558 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1559 {
1560 struct rtl8169_private *tp = netdev_priv(dev);
1561
1562 if (dev->mtu > TD_MSS_MAX)
1563 features &= ~NETIF_F_ALL_TSO;
1564
1565 if (dev->mtu > JUMBO_1K &&
1566 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1567 features &= ~NETIF_F_IP_CSUM;
1568
1569 return features;
1570 }
1571
1572 static int rtl8169_set_features(struct net_device *dev, u32 features)
1573 {
1574 struct rtl8169_private *tp = netdev_priv(dev);
1575 void __iomem *ioaddr = tp->mmio_addr;
1576 unsigned long flags;
1577
1578 spin_lock_irqsave(&tp->lock, flags);
1579
1580 if (features & NETIF_F_RXCSUM)
1581 tp->cp_cmd |= RxChkSum;
1582 else
1583 tp->cp_cmd &= ~RxChkSum;
1584
1585 if (dev->features & NETIF_F_HW_VLAN_RX)
1586 tp->cp_cmd |= RxVlan;
1587 else
1588 tp->cp_cmd &= ~RxVlan;
1589
1590 RTL_W16(CPlusCmd, tp->cp_cmd);
1591 RTL_R16(CPlusCmd);
1592
1593 spin_unlock_irqrestore(&tp->lock, flags);
1594
1595 return 0;
1596 }
1597
1598 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1599 struct sk_buff *skb)
1600 {
1601 return (vlan_tx_tag_present(skb)) ?
1602 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1603 }
1604
1605 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1606 {
1607 u32 opts2 = le32_to_cpu(desc->opts2);
1608
1609 if (opts2 & RxVlanTag)
1610 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1611
1612 desc->opts2 = 0;
1613 }
1614
1615 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1616 {
1617 struct rtl8169_private *tp = netdev_priv(dev);
1618 void __iomem *ioaddr = tp->mmio_addr;
1619 u32 status;
1620
1621 cmd->supported =
1622 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1623 cmd->port = PORT_FIBRE;
1624 cmd->transceiver = XCVR_INTERNAL;
1625
1626 status = RTL_R32(TBICSR);
1627 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1628 cmd->autoneg = !!(status & TBINwEnable);
1629
1630 ethtool_cmd_speed_set(cmd, SPEED_1000);
1631 cmd->duplex = DUPLEX_FULL; /* Always set */
1632
1633 return 0;
1634 }
1635
1636 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1637 {
1638 struct rtl8169_private *tp = netdev_priv(dev);
1639
1640 return mii_ethtool_gset(&tp->mii, cmd);
1641 }
1642
1643 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1644 {
1645 struct rtl8169_private *tp = netdev_priv(dev);
1646 unsigned long flags;
1647 int rc;
1648
1649 spin_lock_irqsave(&tp->lock, flags);
1650
1651 rc = tp->get_settings(dev, cmd);
1652
1653 spin_unlock_irqrestore(&tp->lock, flags);
1654 return rc;
1655 }
1656
1657 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1658 void *p)
1659 {
1660 struct rtl8169_private *tp = netdev_priv(dev);
1661 unsigned long flags;
1662
1663 if (regs->len > R8169_REGS_SIZE)
1664 regs->len = R8169_REGS_SIZE;
1665
1666 spin_lock_irqsave(&tp->lock, flags);
1667 memcpy_fromio(p, tp->mmio_addr, regs->len);
1668 spin_unlock_irqrestore(&tp->lock, flags);
1669 }
1670
1671 static u32 rtl8169_get_msglevel(struct net_device *dev)
1672 {
1673 struct rtl8169_private *tp = netdev_priv(dev);
1674
1675 return tp->msg_enable;
1676 }
1677
1678 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1679 {
1680 struct rtl8169_private *tp = netdev_priv(dev);
1681
1682 tp->msg_enable = value;
1683 }
1684
1685 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1686 "tx_packets",
1687 "rx_packets",
1688 "tx_errors",
1689 "rx_errors",
1690 "rx_missed",
1691 "align_errors",
1692 "tx_single_collisions",
1693 "tx_multi_collisions",
1694 "unicast",
1695 "broadcast",
1696 "multicast",
1697 "tx_aborted",
1698 "tx_underrun",
1699 };
1700
1701 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1702 {
1703 switch (sset) {
1704 case ETH_SS_STATS:
1705 return ARRAY_SIZE(rtl8169_gstrings);
1706 default:
1707 return -EOPNOTSUPP;
1708 }
1709 }
1710
1711 static void rtl8169_update_counters(struct net_device *dev)
1712 {
1713 struct rtl8169_private *tp = netdev_priv(dev);
1714 void __iomem *ioaddr = tp->mmio_addr;
1715 struct device *d = &tp->pci_dev->dev;
1716 struct rtl8169_counters *counters;
1717 dma_addr_t paddr;
1718 u32 cmd;
1719 int wait = 1000;
1720
1721 /*
1722 * Some chips are unable to dump tally counters when the receiver
1723 * is disabled.
1724 */
1725 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1726 return;
1727
1728 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1729 if (!counters)
1730 return;
1731
1732 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1733 cmd = (u64)paddr & DMA_BIT_MASK(32);
1734 RTL_W32(CounterAddrLow, cmd);
1735 RTL_W32(CounterAddrLow, cmd | CounterDump);
1736
1737 while (wait--) {
1738 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1739 memcpy(&tp->counters, counters, sizeof(*counters));
1740 break;
1741 }
1742 udelay(10);
1743 }
1744
1745 RTL_W32(CounterAddrLow, 0);
1746 RTL_W32(CounterAddrHigh, 0);
1747
1748 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1749 }
1750
1751 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1752 struct ethtool_stats *stats, u64 *data)
1753 {
1754 struct rtl8169_private *tp = netdev_priv(dev);
1755
1756 ASSERT_RTNL();
1757
1758 rtl8169_update_counters(dev);
1759
1760 data[0] = le64_to_cpu(tp->counters.tx_packets);
1761 data[1] = le64_to_cpu(tp->counters.rx_packets);
1762 data[2] = le64_to_cpu(tp->counters.tx_errors);
1763 data[3] = le32_to_cpu(tp->counters.rx_errors);
1764 data[4] = le16_to_cpu(tp->counters.rx_missed);
1765 data[5] = le16_to_cpu(tp->counters.align_errors);
1766 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1767 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1768 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1769 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1770 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1771 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1772 data[12] = le16_to_cpu(tp->counters.tx_underun);
1773 }
1774
1775 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1776 {
1777 switch(stringset) {
1778 case ETH_SS_STATS:
1779 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1780 break;
1781 }
1782 }
1783
1784 static const struct ethtool_ops rtl8169_ethtool_ops = {
1785 .get_drvinfo = rtl8169_get_drvinfo,
1786 .get_regs_len = rtl8169_get_regs_len,
1787 .get_link = ethtool_op_get_link,
1788 .get_settings = rtl8169_get_settings,
1789 .set_settings = rtl8169_set_settings,
1790 .get_msglevel = rtl8169_get_msglevel,
1791 .set_msglevel = rtl8169_set_msglevel,
1792 .get_regs = rtl8169_get_regs,
1793 .get_wol = rtl8169_get_wol,
1794 .set_wol = rtl8169_set_wol,
1795 .get_strings = rtl8169_get_strings,
1796 .get_sset_count = rtl8169_get_sset_count,
1797 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1798 };
1799
1800 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1801 struct net_device *dev, u8 default_version)
1802 {
1803 void __iomem *ioaddr = tp->mmio_addr;
1804 /*
1805 * The driver currently handles the 8168Bf and the 8168Be identically
1806 * but they can be identified more specifically through the test below
1807 * if needed:
1808 *
1809 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1810 *
1811 * Same thing for the 8101Eb and the 8101Ec:
1812 *
1813 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1814 */
1815 static const struct rtl_mac_info {
1816 u32 mask;
1817 u32 val;
1818 int mac_version;
1819 } mac_info[] = {
1820 /* 8168F family. */
1821 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1822 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1823
1824 /* 8168E family. */
1825 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1826 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1827 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1828 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1829
1830 /* 8168D family. */
1831 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1832 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1833 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1834
1835 /* 8168DP family. */
1836 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1837 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1838 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1839
1840 /* 8168C family. */
1841 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1842 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1843 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1844 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1845 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1846 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1847 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1848 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1849 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1850
1851 /* 8168B family. */
1852 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1853 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1854 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1855 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1856
1857 /* 8101 family. */
1858 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1859 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1860 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1861 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1862 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1863 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1864 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1865 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1866 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1867 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1868 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1869 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1870 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1871 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1872 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1873 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1874 /* FIXME: where did these entries come from ? -- FR */
1875 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1876 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1877
1878 /* 8110 family. */
1879 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1880 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1881 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1882 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1883 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1884 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1885
1886 /* Catch-all */
1887 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1888 };
1889 const struct rtl_mac_info *p = mac_info;
1890 u32 reg;
1891
1892 reg = RTL_R32(TxConfig);
1893 while ((reg & p->mask) != p->val)
1894 p++;
1895 tp->mac_version = p->mac_version;
1896
1897 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1898 netif_notice(tp, probe, dev,
1899 "unknown MAC, using family default\n");
1900 tp->mac_version = default_version;
1901 }
1902 }
1903
1904 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1905 {
1906 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1907 }
1908
1909 struct phy_reg {
1910 u16 reg;
1911 u16 val;
1912 };
1913
1914 static void rtl_writephy_batch(struct rtl8169_private *tp,
1915 const struct phy_reg *regs, int len)
1916 {
1917 while (len-- > 0) {
1918 rtl_writephy(tp, regs->reg, regs->val);
1919 regs++;
1920 }
1921 }
1922
1923 #define PHY_READ 0x00000000
1924 #define PHY_DATA_OR 0x10000000
1925 #define PHY_DATA_AND 0x20000000
1926 #define PHY_BJMPN 0x30000000
1927 #define PHY_READ_EFUSE 0x40000000
1928 #define PHY_READ_MAC_BYTE 0x50000000
1929 #define PHY_WRITE_MAC_BYTE 0x60000000
1930 #define PHY_CLEAR_READCOUNT 0x70000000
1931 #define PHY_WRITE 0x80000000
1932 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1933 #define PHY_COMP_EQ_SKIPN 0xa0000000
1934 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1935 #define PHY_WRITE_PREVIOUS 0xc0000000
1936 #define PHY_SKIPN 0xd0000000
1937 #define PHY_DELAY_MS 0xe0000000
1938 #define PHY_WRITE_ERI_WORD 0xf0000000
1939
1940 struct fw_info {
1941 u32 magic;
1942 char version[RTL_VER_SIZE];
1943 __le32 fw_start;
1944 __le32 fw_len;
1945 u8 chksum;
1946 } __packed;
1947
1948 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1949
1950 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1951 {
1952 const struct firmware *fw = rtl_fw->fw;
1953 struct fw_info *fw_info = (struct fw_info *)fw->data;
1954 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1955 char *version = rtl_fw->version;
1956 bool rc = false;
1957
1958 if (fw->size < FW_OPCODE_SIZE)
1959 goto out;
1960
1961 if (!fw_info->magic) {
1962 size_t i, size, start;
1963 u8 checksum = 0;
1964
1965 if (fw->size < sizeof(*fw_info))
1966 goto out;
1967
1968 for (i = 0; i < fw->size; i++)
1969 checksum += fw->data[i];
1970 if (checksum != 0)
1971 goto out;
1972
1973 start = le32_to_cpu(fw_info->fw_start);
1974 if (start > fw->size)
1975 goto out;
1976
1977 size = le32_to_cpu(fw_info->fw_len);
1978 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1979 goto out;
1980
1981 memcpy(version, fw_info->version, RTL_VER_SIZE);
1982
1983 pa->code = (__le32 *)(fw->data + start);
1984 pa->size = size;
1985 } else {
1986 if (fw->size % FW_OPCODE_SIZE)
1987 goto out;
1988
1989 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1990
1991 pa->code = (__le32 *)fw->data;
1992 pa->size = fw->size / FW_OPCODE_SIZE;
1993 }
1994 version[RTL_VER_SIZE - 1] = 0;
1995
1996 rc = true;
1997 out:
1998 return rc;
1999 }
2000
2001 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2002 struct rtl_fw_phy_action *pa)
2003 {
2004 bool rc = false;
2005 size_t index;
2006
2007 for (index = 0; index < pa->size; index++) {
2008 u32 action = le32_to_cpu(pa->code[index]);
2009 u32 regno = (action & 0x0fff0000) >> 16;
2010
2011 switch(action & 0xf0000000) {
2012 case PHY_READ:
2013 case PHY_DATA_OR:
2014 case PHY_DATA_AND:
2015 case PHY_READ_EFUSE:
2016 case PHY_CLEAR_READCOUNT:
2017 case PHY_WRITE:
2018 case PHY_WRITE_PREVIOUS:
2019 case PHY_DELAY_MS:
2020 break;
2021
2022 case PHY_BJMPN:
2023 if (regno > index) {
2024 netif_err(tp, ifup, tp->dev,
2025 "Out of range of firmware\n");
2026 goto out;
2027 }
2028 break;
2029 case PHY_READCOUNT_EQ_SKIP:
2030 if (index + 2 >= pa->size) {
2031 netif_err(tp, ifup, tp->dev,
2032 "Out of range of firmware\n");
2033 goto out;
2034 }
2035 break;
2036 case PHY_COMP_EQ_SKIPN:
2037 case PHY_COMP_NEQ_SKIPN:
2038 case PHY_SKIPN:
2039 if (index + 1 + regno >= pa->size) {
2040 netif_err(tp, ifup, tp->dev,
2041 "Out of range of firmware\n");
2042 goto out;
2043 }
2044 break;
2045
2046 case PHY_READ_MAC_BYTE:
2047 case PHY_WRITE_MAC_BYTE:
2048 case PHY_WRITE_ERI_WORD:
2049 default:
2050 netif_err(tp, ifup, tp->dev,
2051 "Invalid action 0x%08x\n", action);
2052 goto out;
2053 }
2054 }
2055 rc = true;
2056 out:
2057 return rc;
2058 }
2059
2060 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2061 {
2062 struct net_device *dev = tp->dev;
2063 int rc = -EINVAL;
2064
2065 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2066 netif_err(tp, ifup, dev, "invalid firwmare\n");
2067 goto out;
2068 }
2069
2070 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2071 rc = 0;
2072 out:
2073 return rc;
2074 }
2075
2076 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2077 {
2078 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2079 u32 predata, count;
2080 size_t index;
2081
2082 predata = count = 0;
2083
2084 for (index = 0; index < pa->size; ) {
2085 u32 action = le32_to_cpu(pa->code[index]);
2086 u32 data = action & 0x0000ffff;
2087 u32 regno = (action & 0x0fff0000) >> 16;
2088
2089 if (!action)
2090 break;
2091
2092 switch(action & 0xf0000000) {
2093 case PHY_READ:
2094 predata = rtl_readphy(tp, regno);
2095 count++;
2096 index++;
2097 break;
2098 case PHY_DATA_OR:
2099 predata |= data;
2100 index++;
2101 break;
2102 case PHY_DATA_AND:
2103 predata &= data;
2104 index++;
2105 break;
2106 case PHY_BJMPN:
2107 index -= regno;
2108 break;
2109 case PHY_READ_EFUSE:
2110 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2111 index++;
2112 break;
2113 case PHY_CLEAR_READCOUNT:
2114 count = 0;
2115 index++;
2116 break;
2117 case PHY_WRITE:
2118 rtl_writephy(tp, regno, data);
2119 index++;
2120 break;
2121 case PHY_READCOUNT_EQ_SKIP:
2122 index += (count == data) ? 2 : 1;
2123 break;
2124 case PHY_COMP_EQ_SKIPN:
2125 if (predata == data)
2126 index += regno;
2127 index++;
2128 break;
2129 case PHY_COMP_NEQ_SKIPN:
2130 if (predata != data)
2131 index += regno;
2132 index++;
2133 break;
2134 case PHY_WRITE_PREVIOUS:
2135 rtl_writephy(tp, regno, predata);
2136 index++;
2137 break;
2138 case PHY_SKIPN:
2139 index += regno + 1;
2140 break;
2141 case PHY_DELAY_MS:
2142 mdelay(data);
2143 index++;
2144 break;
2145
2146 case PHY_READ_MAC_BYTE:
2147 case PHY_WRITE_MAC_BYTE:
2148 case PHY_WRITE_ERI_WORD:
2149 default:
2150 BUG();
2151 }
2152 }
2153 }
2154
2155 static void rtl_release_firmware(struct rtl8169_private *tp)
2156 {
2157 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2158 release_firmware(tp->rtl_fw->fw);
2159 kfree(tp->rtl_fw);
2160 }
2161 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2162 }
2163
2164 static void rtl_apply_firmware(struct rtl8169_private *tp)
2165 {
2166 struct rtl_fw *rtl_fw = tp->rtl_fw;
2167
2168 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2169 if (!IS_ERR_OR_NULL(rtl_fw))
2170 rtl_phy_write_fw(tp, rtl_fw);
2171 }
2172
2173 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2174 {
2175 if (rtl_readphy(tp, reg) != val)
2176 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2177 else
2178 rtl_apply_firmware(tp);
2179 }
2180
2181 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2182 {
2183 static const struct phy_reg phy_reg_init[] = {
2184 { 0x1f, 0x0001 },
2185 { 0x06, 0x006e },
2186 { 0x08, 0x0708 },
2187 { 0x15, 0x4000 },
2188 { 0x18, 0x65c7 },
2189
2190 { 0x1f, 0x0001 },
2191 { 0x03, 0x00a1 },
2192 { 0x02, 0x0008 },
2193 { 0x01, 0x0120 },
2194 { 0x00, 0x1000 },
2195 { 0x04, 0x0800 },
2196 { 0x04, 0x0000 },
2197
2198 { 0x03, 0xff41 },
2199 { 0x02, 0xdf60 },
2200 { 0x01, 0x0140 },
2201 { 0x00, 0x0077 },
2202 { 0x04, 0x7800 },
2203 { 0x04, 0x7000 },
2204
2205 { 0x03, 0x802f },
2206 { 0x02, 0x4f02 },
2207 { 0x01, 0x0409 },
2208 { 0x00, 0xf0f9 },
2209 { 0x04, 0x9800 },
2210 { 0x04, 0x9000 },
2211
2212 { 0x03, 0xdf01 },
2213 { 0x02, 0xdf20 },
2214 { 0x01, 0xff95 },
2215 { 0x00, 0xba00 },
2216 { 0x04, 0xa800 },
2217 { 0x04, 0xa000 },
2218
2219 { 0x03, 0xff41 },
2220 { 0x02, 0xdf20 },
2221 { 0x01, 0x0140 },
2222 { 0x00, 0x00bb },
2223 { 0x04, 0xb800 },
2224 { 0x04, 0xb000 },
2225
2226 { 0x03, 0xdf41 },
2227 { 0x02, 0xdc60 },
2228 { 0x01, 0x6340 },
2229 { 0x00, 0x007d },
2230 { 0x04, 0xd800 },
2231 { 0x04, 0xd000 },
2232
2233 { 0x03, 0xdf01 },
2234 { 0x02, 0xdf20 },
2235 { 0x01, 0x100a },
2236 { 0x00, 0xa0ff },
2237 { 0x04, 0xf800 },
2238 { 0x04, 0xf000 },
2239
2240 { 0x1f, 0x0000 },
2241 { 0x0b, 0x0000 },
2242 { 0x00, 0x9200 }
2243 };
2244
2245 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2246 }
2247
2248 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2249 {
2250 static const struct phy_reg phy_reg_init[] = {
2251 { 0x1f, 0x0002 },
2252 { 0x01, 0x90d0 },
2253 { 0x1f, 0x0000 }
2254 };
2255
2256 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2257 }
2258
2259 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2260 {
2261 struct pci_dev *pdev = tp->pci_dev;
2262
2263 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2264 (pdev->subsystem_device != 0xe000))
2265 return;
2266
2267 rtl_writephy(tp, 0x1f, 0x0001);
2268 rtl_writephy(tp, 0x10, 0xf01b);
2269 rtl_writephy(tp, 0x1f, 0x0000);
2270 }
2271
2272 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2273 {
2274 static const struct phy_reg phy_reg_init[] = {
2275 { 0x1f, 0x0001 },
2276 { 0x04, 0x0000 },
2277 { 0x03, 0x00a1 },
2278 { 0x02, 0x0008 },
2279 { 0x01, 0x0120 },
2280 { 0x00, 0x1000 },
2281 { 0x04, 0x0800 },
2282 { 0x04, 0x9000 },
2283 { 0x03, 0x802f },
2284 { 0x02, 0x4f02 },
2285 { 0x01, 0x0409 },
2286 { 0x00, 0xf099 },
2287 { 0x04, 0x9800 },
2288 { 0x04, 0xa000 },
2289 { 0x03, 0xdf01 },
2290 { 0x02, 0xdf20 },
2291 { 0x01, 0xff95 },
2292 { 0x00, 0xba00 },
2293 { 0x04, 0xa800 },
2294 { 0x04, 0xf000 },
2295 { 0x03, 0xdf01 },
2296 { 0x02, 0xdf20 },
2297 { 0x01, 0x101a },
2298 { 0x00, 0xa0ff },
2299 { 0x04, 0xf800 },
2300 { 0x04, 0x0000 },
2301 { 0x1f, 0x0000 },
2302
2303 { 0x1f, 0x0001 },
2304 { 0x10, 0xf41b },
2305 { 0x14, 0xfb54 },
2306 { 0x18, 0xf5c7 },
2307 { 0x1f, 0x0000 },
2308
2309 { 0x1f, 0x0001 },
2310 { 0x17, 0x0cc0 },
2311 { 0x1f, 0x0000 }
2312 };
2313
2314 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2315
2316 rtl8169scd_hw_phy_config_quirk(tp);
2317 }
2318
2319 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2320 {
2321 static const struct phy_reg phy_reg_init[] = {
2322 { 0x1f, 0x0001 },
2323 { 0x04, 0x0000 },
2324 { 0x03, 0x00a1 },
2325 { 0x02, 0x0008 },
2326 { 0x01, 0x0120 },
2327 { 0x00, 0x1000 },
2328 { 0x04, 0x0800 },
2329 { 0x04, 0x9000 },
2330 { 0x03, 0x802f },
2331 { 0x02, 0x4f02 },
2332 { 0x01, 0x0409 },
2333 { 0x00, 0xf099 },
2334 { 0x04, 0x9800 },
2335 { 0x04, 0xa000 },
2336 { 0x03, 0xdf01 },
2337 { 0x02, 0xdf20 },
2338 { 0x01, 0xff95 },
2339 { 0x00, 0xba00 },
2340 { 0x04, 0xa800 },
2341 { 0x04, 0xf000 },
2342 { 0x03, 0xdf01 },
2343 { 0x02, 0xdf20 },
2344 { 0x01, 0x101a },
2345 { 0x00, 0xa0ff },
2346 { 0x04, 0xf800 },
2347 { 0x04, 0x0000 },
2348 { 0x1f, 0x0000 },
2349
2350 { 0x1f, 0x0001 },
2351 { 0x0b, 0x8480 },
2352 { 0x1f, 0x0000 },
2353
2354 { 0x1f, 0x0001 },
2355 { 0x18, 0x67c7 },
2356 { 0x04, 0x2000 },
2357 { 0x03, 0x002f },
2358 { 0x02, 0x4360 },
2359 { 0x01, 0x0109 },
2360 { 0x00, 0x3022 },
2361 { 0x04, 0x2800 },
2362 { 0x1f, 0x0000 },
2363
2364 { 0x1f, 0x0001 },
2365 { 0x17, 0x0cc0 },
2366 { 0x1f, 0x0000 }
2367 };
2368
2369 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2370 }
2371
2372 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2373 {
2374 static const struct phy_reg phy_reg_init[] = {
2375 { 0x10, 0xf41b },
2376 { 0x1f, 0x0000 }
2377 };
2378
2379 rtl_writephy(tp, 0x1f, 0x0001);
2380 rtl_patchphy(tp, 0x16, 1 << 0);
2381
2382 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2383 }
2384
2385 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2386 {
2387 static const struct phy_reg phy_reg_init[] = {
2388 { 0x1f, 0x0001 },
2389 { 0x10, 0xf41b },
2390 { 0x1f, 0x0000 }
2391 };
2392
2393 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2394 }
2395
2396 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2397 {
2398 static const struct phy_reg phy_reg_init[] = {
2399 { 0x1f, 0x0000 },
2400 { 0x1d, 0x0f00 },
2401 { 0x1f, 0x0002 },
2402 { 0x0c, 0x1ec8 },
2403 { 0x1f, 0x0000 }
2404 };
2405
2406 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2407 }
2408
2409 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2410 {
2411 static const struct phy_reg phy_reg_init[] = {
2412 { 0x1f, 0x0001 },
2413 { 0x1d, 0x3d98 },
2414 { 0x1f, 0x0000 }
2415 };
2416
2417 rtl_writephy(tp, 0x1f, 0x0000);
2418 rtl_patchphy(tp, 0x14, 1 << 5);
2419 rtl_patchphy(tp, 0x0d, 1 << 5);
2420
2421 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2422 }
2423
2424 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2425 {
2426 static const struct phy_reg phy_reg_init[] = {
2427 { 0x1f, 0x0001 },
2428 { 0x12, 0x2300 },
2429 { 0x1f, 0x0002 },
2430 { 0x00, 0x88d4 },
2431 { 0x01, 0x82b1 },
2432 { 0x03, 0x7002 },
2433 { 0x08, 0x9e30 },
2434 { 0x09, 0x01f0 },
2435 { 0x0a, 0x5500 },
2436 { 0x0c, 0x00c8 },
2437 { 0x1f, 0x0003 },
2438 { 0x12, 0xc096 },
2439 { 0x16, 0x000a },
2440 { 0x1f, 0x0000 },
2441 { 0x1f, 0x0000 },
2442 { 0x09, 0x2000 },
2443 { 0x09, 0x0000 }
2444 };
2445
2446 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2447
2448 rtl_patchphy(tp, 0x14, 1 << 5);
2449 rtl_patchphy(tp, 0x0d, 1 << 5);
2450 rtl_writephy(tp, 0x1f, 0x0000);
2451 }
2452
2453 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2454 {
2455 static const struct phy_reg phy_reg_init[] = {
2456 { 0x1f, 0x0001 },
2457 { 0x12, 0x2300 },
2458 { 0x03, 0x802f },
2459 { 0x02, 0x4f02 },
2460 { 0x01, 0x0409 },
2461 { 0x00, 0xf099 },
2462 { 0x04, 0x9800 },
2463 { 0x04, 0x9000 },
2464 { 0x1d, 0x3d98 },
2465 { 0x1f, 0x0002 },
2466 { 0x0c, 0x7eb8 },
2467 { 0x06, 0x0761 },
2468 { 0x1f, 0x0003 },
2469 { 0x16, 0x0f0a },
2470 { 0x1f, 0x0000 }
2471 };
2472
2473 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2474
2475 rtl_patchphy(tp, 0x16, 1 << 0);
2476 rtl_patchphy(tp, 0x14, 1 << 5);
2477 rtl_patchphy(tp, 0x0d, 1 << 5);
2478 rtl_writephy(tp, 0x1f, 0x0000);
2479 }
2480
2481 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2482 {
2483 static const struct phy_reg phy_reg_init[] = {
2484 { 0x1f, 0x0001 },
2485 { 0x12, 0x2300 },
2486 { 0x1d, 0x3d98 },
2487 { 0x1f, 0x0002 },
2488 { 0x0c, 0x7eb8 },
2489 { 0x06, 0x5461 },
2490 { 0x1f, 0x0003 },
2491 { 0x16, 0x0f0a },
2492 { 0x1f, 0x0000 }
2493 };
2494
2495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2496
2497 rtl_patchphy(tp, 0x16, 1 << 0);
2498 rtl_patchphy(tp, 0x14, 1 << 5);
2499 rtl_patchphy(tp, 0x0d, 1 << 5);
2500 rtl_writephy(tp, 0x1f, 0x0000);
2501 }
2502
2503 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2504 {
2505 rtl8168c_3_hw_phy_config(tp);
2506 }
2507
2508 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2509 {
2510 static const struct phy_reg phy_reg_init_0[] = {
2511 /* Channel Estimation */
2512 { 0x1f, 0x0001 },
2513 { 0x06, 0x4064 },
2514 { 0x07, 0x2863 },
2515 { 0x08, 0x059c },
2516 { 0x09, 0x26b4 },
2517 { 0x0a, 0x6a19 },
2518 { 0x0b, 0xdcc8 },
2519 { 0x10, 0xf06d },
2520 { 0x14, 0x7f68 },
2521 { 0x18, 0x7fd9 },
2522 { 0x1c, 0xf0ff },
2523 { 0x1d, 0x3d9c },
2524 { 0x1f, 0x0003 },
2525 { 0x12, 0xf49f },
2526 { 0x13, 0x070b },
2527 { 0x1a, 0x05ad },
2528 { 0x14, 0x94c0 },
2529
2530 /*
2531 * Tx Error Issue
2532 * Enhance line driver power
2533 */
2534 { 0x1f, 0x0002 },
2535 { 0x06, 0x5561 },
2536 { 0x1f, 0x0005 },
2537 { 0x05, 0x8332 },
2538 { 0x06, 0x5561 },
2539
2540 /*
2541 * Can not link to 1Gbps with bad cable
2542 * Decrease SNR threshold form 21.07dB to 19.04dB
2543 */
2544 { 0x1f, 0x0001 },
2545 { 0x17, 0x0cc0 },
2546
2547 { 0x1f, 0x0000 },
2548 { 0x0d, 0xf880 }
2549 };
2550 void __iomem *ioaddr = tp->mmio_addr;
2551
2552 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2553
2554 /*
2555 * Rx Error Issue
2556 * Fine Tune Switching regulator parameter
2557 */
2558 rtl_writephy(tp, 0x1f, 0x0002);
2559 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2560 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2561
2562 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2563 static const struct phy_reg phy_reg_init[] = {
2564 { 0x1f, 0x0002 },
2565 { 0x05, 0x669a },
2566 { 0x1f, 0x0005 },
2567 { 0x05, 0x8330 },
2568 { 0x06, 0x669a },
2569 { 0x1f, 0x0002 }
2570 };
2571 int val;
2572
2573 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2574
2575 val = rtl_readphy(tp, 0x0d);
2576
2577 if ((val & 0x00ff) != 0x006c) {
2578 static const u32 set[] = {
2579 0x0065, 0x0066, 0x0067, 0x0068,
2580 0x0069, 0x006a, 0x006b, 0x006c
2581 };
2582 int i;
2583
2584 rtl_writephy(tp, 0x1f, 0x0002);
2585
2586 val &= 0xff00;
2587 for (i = 0; i < ARRAY_SIZE(set); i++)
2588 rtl_writephy(tp, 0x0d, val | set[i]);
2589 }
2590 } else {
2591 static const struct phy_reg phy_reg_init[] = {
2592 { 0x1f, 0x0002 },
2593 { 0x05, 0x6662 },
2594 { 0x1f, 0x0005 },
2595 { 0x05, 0x8330 },
2596 { 0x06, 0x6662 }
2597 };
2598
2599 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2600 }
2601
2602 /* RSET couple improve */
2603 rtl_writephy(tp, 0x1f, 0x0002);
2604 rtl_patchphy(tp, 0x0d, 0x0300);
2605 rtl_patchphy(tp, 0x0f, 0x0010);
2606
2607 /* Fine tune PLL performance */
2608 rtl_writephy(tp, 0x1f, 0x0002);
2609 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2610 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2611
2612 rtl_writephy(tp, 0x1f, 0x0005);
2613 rtl_writephy(tp, 0x05, 0x001b);
2614
2615 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2616
2617 rtl_writephy(tp, 0x1f, 0x0000);
2618 }
2619
2620 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2621 {
2622 static const struct phy_reg phy_reg_init_0[] = {
2623 /* Channel Estimation */
2624 { 0x1f, 0x0001 },
2625 { 0x06, 0x4064 },
2626 { 0x07, 0x2863 },
2627 { 0x08, 0x059c },
2628 { 0x09, 0x26b4 },
2629 { 0x0a, 0x6a19 },
2630 { 0x0b, 0xdcc8 },
2631 { 0x10, 0xf06d },
2632 { 0x14, 0x7f68 },
2633 { 0x18, 0x7fd9 },
2634 { 0x1c, 0xf0ff },
2635 { 0x1d, 0x3d9c },
2636 { 0x1f, 0x0003 },
2637 { 0x12, 0xf49f },
2638 { 0x13, 0x070b },
2639 { 0x1a, 0x05ad },
2640 { 0x14, 0x94c0 },
2641
2642 /*
2643 * Tx Error Issue
2644 * Enhance line driver power
2645 */
2646 { 0x1f, 0x0002 },
2647 { 0x06, 0x5561 },
2648 { 0x1f, 0x0005 },
2649 { 0x05, 0x8332 },
2650 { 0x06, 0x5561 },
2651
2652 /*
2653 * Can not link to 1Gbps with bad cable
2654 * Decrease SNR threshold form 21.07dB to 19.04dB
2655 */
2656 { 0x1f, 0x0001 },
2657 { 0x17, 0x0cc0 },
2658
2659 { 0x1f, 0x0000 },
2660 { 0x0d, 0xf880 }
2661 };
2662 void __iomem *ioaddr = tp->mmio_addr;
2663
2664 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2665
2666 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2667 static const struct phy_reg phy_reg_init[] = {
2668 { 0x1f, 0x0002 },
2669 { 0x05, 0x669a },
2670 { 0x1f, 0x0005 },
2671 { 0x05, 0x8330 },
2672 { 0x06, 0x669a },
2673
2674 { 0x1f, 0x0002 }
2675 };
2676 int val;
2677
2678 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2679
2680 val = rtl_readphy(tp, 0x0d);
2681 if ((val & 0x00ff) != 0x006c) {
2682 static const u32 set[] = {
2683 0x0065, 0x0066, 0x0067, 0x0068,
2684 0x0069, 0x006a, 0x006b, 0x006c
2685 };
2686 int i;
2687
2688 rtl_writephy(tp, 0x1f, 0x0002);
2689
2690 val &= 0xff00;
2691 for (i = 0; i < ARRAY_SIZE(set); i++)
2692 rtl_writephy(tp, 0x0d, val | set[i]);
2693 }
2694 } else {
2695 static const struct phy_reg phy_reg_init[] = {
2696 { 0x1f, 0x0002 },
2697 { 0x05, 0x2642 },
2698 { 0x1f, 0x0005 },
2699 { 0x05, 0x8330 },
2700 { 0x06, 0x2642 }
2701 };
2702
2703 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2704 }
2705
2706 /* Fine tune PLL performance */
2707 rtl_writephy(tp, 0x1f, 0x0002);
2708 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2709 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2710
2711 /* Switching regulator Slew rate */
2712 rtl_writephy(tp, 0x1f, 0x0002);
2713 rtl_patchphy(tp, 0x0f, 0x0017);
2714
2715 rtl_writephy(tp, 0x1f, 0x0005);
2716 rtl_writephy(tp, 0x05, 0x001b);
2717
2718 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2719
2720 rtl_writephy(tp, 0x1f, 0x0000);
2721 }
2722
2723 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2724 {
2725 static const struct phy_reg phy_reg_init[] = {
2726 { 0x1f, 0x0002 },
2727 { 0x10, 0x0008 },
2728 { 0x0d, 0x006c },
2729
2730 { 0x1f, 0x0000 },
2731 { 0x0d, 0xf880 },
2732
2733 { 0x1f, 0x0001 },
2734 { 0x17, 0x0cc0 },
2735
2736 { 0x1f, 0x0001 },
2737 { 0x0b, 0xa4d8 },
2738 { 0x09, 0x281c },
2739 { 0x07, 0x2883 },
2740 { 0x0a, 0x6b35 },
2741 { 0x1d, 0x3da4 },
2742 { 0x1c, 0xeffd },
2743 { 0x14, 0x7f52 },
2744 { 0x18, 0x7fc6 },
2745 { 0x08, 0x0601 },
2746 { 0x06, 0x4063 },
2747 { 0x10, 0xf074 },
2748 { 0x1f, 0x0003 },
2749 { 0x13, 0x0789 },
2750 { 0x12, 0xf4bd },
2751 { 0x1a, 0x04fd },
2752 { 0x14, 0x84b0 },
2753 { 0x1f, 0x0000 },
2754 { 0x00, 0x9200 },
2755
2756 { 0x1f, 0x0005 },
2757 { 0x01, 0x0340 },
2758 { 0x1f, 0x0001 },
2759 { 0x04, 0x4000 },
2760 { 0x03, 0x1d21 },
2761 { 0x02, 0x0c32 },
2762 { 0x01, 0x0200 },
2763 { 0x00, 0x5554 },
2764 { 0x04, 0x4800 },
2765 { 0x04, 0x4000 },
2766 { 0x04, 0xf000 },
2767 { 0x03, 0xdf01 },
2768 { 0x02, 0xdf20 },
2769 { 0x01, 0x101a },
2770 { 0x00, 0xa0ff },
2771 { 0x04, 0xf800 },
2772 { 0x04, 0xf000 },
2773 { 0x1f, 0x0000 },
2774
2775 { 0x1f, 0x0007 },
2776 { 0x1e, 0x0023 },
2777 { 0x16, 0x0000 },
2778 { 0x1f, 0x0000 }
2779 };
2780
2781 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2782 }
2783
2784 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2785 {
2786 static const struct phy_reg phy_reg_init[] = {
2787 { 0x1f, 0x0001 },
2788 { 0x17, 0x0cc0 },
2789
2790 { 0x1f, 0x0007 },
2791 { 0x1e, 0x002d },
2792 { 0x18, 0x0040 },
2793 { 0x1f, 0x0000 }
2794 };
2795
2796 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2797 rtl_patchphy(tp, 0x0d, 1 << 5);
2798 }
2799
2800 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2801 {
2802 static const struct phy_reg phy_reg_init[] = {
2803 /* Enable Delay cap */
2804 { 0x1f, 0x0005 },
2805 { 0x05, 0x8b80 },
2806 { 0x06, 0xc896 },
2807 { 0x1f, 0x0000 },
2808
2809 /* Channel estimation fine tune */
2810 { 0x1f, 0x0001 },
2811 { 0x0b, 0x6c20 },
2812 { 0x07, 0x2872 },
2813 { 0x1c, 0xefff },
2814 { 0x1f, 0x0003 },
2815 { 0x14, 0x6420 },
2816 { 0x1f, 0x0000 },
2817
2818 /* Update PFM & 10M TX idle timer */
2819 { 0x1f, 0x0007 },
2820 { 0x1e, 0x002f },
2821 { 0x15, 0x1919 },
2822 { 0x1f, 0x0000 },
2823
2824 { 0x1f, 0x0007 },
2825 { 0x1e, 0x00ac },
2826 { 0x18, 0x0006 },
2827 { 0x1f, 0x0000 }
2828 };
2829
2830 rtl_apply_firmware(tp);
2831
2832 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2833
2834 /* DCO enable for 10M IDLE Power */
2835 rtl_writephy(tp, 0x1f, 0x0007);
2836 rtl_writephy(tp, 0x1e, 0x0023);
2837 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2838 rtl_writephy(tp, 0x1f, 0x0000);
2839
2840 /* For impedance matching */
2841 rtl_writephy(tp, 0x1f, 0x0002);
2842 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2843 rtl_writephy(tp, 0x1f, 0x0000);
2844
2845 /* PHY auto speed down */
2846 rtl_writephy(tp, 0x1f, 0x0007);
2847 rtl_writephy(tp, 0x1e, 0x002d);
2848 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2849 rtl_writephy(tp, 0x1f, 0x0000);
2850 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2851
2852 rtl_writephy(tp, 0x1f, 0x0005);
2853 rtl_writephy(tp, 0x05, 0x8b86);
2854 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2855 rtl_writephy(tp, 0x1f, 0x0000);
2856
2857 rtl_writephy(tp, 0x1f, 0x0005);
2858 rtl_writephy(tp, 0x05, 0x8b85);
2859 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2860 rtl_writephy(tp, 0x1f, 0x0007);
2861 rtl_writephy(tp, 0x1e, 0x0020);
2862 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2863 rtl_writephy(tp, 0x1f, 0x0006);
2864 rtl_writephy(tp, 0x00, 0x5a00);
2865 rtl_writephy(tp, 0x1f, 0x0000);
2866 rtl_writephy(tp, 0x0d, 0x0007);
2867 rtl_writephy(tp, 0x0e, 0x003c);
2868 rtl_writephy(tp, 0x0d, 0x4007);
2869 rtl_writephy(tp, 0x0e, 0x0000);
2870 rtl_writephy(tp, 0x0d, 0x0000);
2871 }
2872
2873 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2874 {
2875 static const struct phy_reg phy_reg_init[] = {
2876 /* Enable Delay cap */
2877 { 0x1f, 0x0004 },
2878 { 0x1f, 0x0007 },
2879 { 0x1e, 0x00ac },
2880 { 0x18, 0x0006 },
2881 { 0x1f, 0x0002 },
2882 { 0x1f, 0x0000 },
2883 { 0x1f, 0x0000 },
2884
2885 /* Channel estimation fine tune */
2886 { 0x1f, 0x0003 },
2887 { 0x09, 0xa20f },
2888 { 0x1f, 0x0000 },
2889 { 0x1f, 0x0000 },
2890
2891 /* Green Setting */
2892 { 0x1f, 0x0005 },
2893 { 0x05, 0x8b5b },
2894 { 0x06, 0x9222 },
2895 { 0x05, 0x8b6d },
2896 { 0x06, 0x8000 },
2897 { 0x05, 0x8b76 },
2898 { 0x06, 0x8000 },
2899 { 0x1f, 0x0000 }
2900 };
2901
2902 rtl_apply_firmware(tp);
2903
2904 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2905
2906 /* For 4-corner performance improve */
2907 rtl_writephy(tp, 0x1f, 0x0005);
2908 rtl_writephy(tp, 0x05, 0x8b80);
2909 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2910 rtl_writephy(tp, 0x1f, 0x0000);
2911
2912 /* PHY auto speed down */
2913 rtl_writephy(tp, 0x1f, 0x0004);
2914 rtl_writephy(tp, 0x1f, 0x0007);
2915 rtl_writephy(tp, 0x1e, 0x002d);
2916 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2917 rtl_writephy(tp, 0x1f, 0x0002);
2918 rtl_writephy(tp, 0x1f, 0x0000);
2919 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2920
2921 /* improve 10M EEE waveform */
2922 rtl_writephy(tp, 0x1f, 0x0005);
2923 rtl_writephy(tp, 0x05, 0x8b86);
2924 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2925 rtl_writephy(tp, 0x1f, 0x0000);
2926
2927 /* Improve 2-pair detection performance */
2928 rtl_writephy(tp, 0x1f, 0x0005);
2929 rtl_writephy(tp, 0x05, 0x8b85);
2930 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2931 rtl_writephy(tp, 0x1f, 0x0000);
2932
2933 /* EEE setting */
2934 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2935 ERIAR_EXGMAC);
2936 rtl_writephy(tp, 0x1f, 0x0005);
2937 rtl_writephy(tp, 0x05, 0x8b85);
2938 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2939 rtl_writephy(tp, 0x1f, 0x0004);
2940 rtl_writephy(tp, 0x1f, 0x0007);
2941 rtl_writephy(tp, 0x1e, 0x0020);
2942 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
2943 rtl_writephy(tp, 0x1f, 0x0002);
2944 rtl_writephy(tp, 0x1f, 0x0000);
2945 rtl_writephy(tp, 0x0d, 0x0007);
2946 rtl_writephy(tp, 0x0e, 0x003c);
2947 rtl_writephy(tp, 0x0d, 0x4007);
2948 rtl_writephy(tp, 0x0e, 0x0000);
2949 rtl_writephy(tp, 0x0d, 0x0000);
2950
2951 /* Green feature */
2952 rtl_writephy(tp, 0x1f, 0x0003);
2953 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2954 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2955 rtl_writephy(tp, 0x1f, 0x0000);
2956 }
2957
2958 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2959 {
2960 static const struct phy_reg phy_reg_init[] = {
2961 /* Channel estimation fine tune */
2962 { 0x1f, 0x0003 },
2963 { 0x09, 0xa20f },
2964 { 0x1f, 0x0000 },
2965
2966 /* Modify green table for giga & fnet */
2967 { 0x1f, 0x0005 },
2968 { 0x05, 0x8b55 },
2969 { 0x06, 0x0000 },
2970 { 0x05, 0x8b5e },
2971 { 0x06, 0x0000 },
2972 { 0x05, 0x8b67 },
2973 { 0x06, 0x0000 },
2974 { 0x05, 0x8b70 },
2975 { 0x06, 0x0000 },
2976 { 0x1f, 0x0000 },
2977 { 0x1f, 0x0007 },
2978 { 0x1e, 0x0078 },
2979 { 0x17, 0x0000 },
2980 { 0x19, 0x00fb },
2981 { 0x1f, 0x0000 },
2982
2983 /* Modify green table for 10M */
2984 { 0x1f, 0x0005 },
2985 { 0x05, 0x8b79 },
2986 { 0x06, 0xaa00 },
2987 { 0x1f, 0x0000 },
2988
2989 /* Disable hiimpedance detection (RTCT) */
2990 { 0x1f, 0x0003 },
2991 { 0x01, 0x328a },
2992 { 0x1f, 0x0000 }
2993 };
2994
2995 rtl_apply_firmware(tp);
2996
2997 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2998
2999 /* For 4-corner performance improve */
3000 rtl_writephy(tp, 0x1f, 0x0005);
3001 rtl_writephy(tp, 0x05, 0x8b80);
3002 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3003 rtl_writephy(tp, 0x1f, 0x0000);
3004
3005 /* PHY auto speed down */
3006 rtl_writephy(tp, 0x1f, 0x0007);
3007 rtl_writephy(tp, 0x1e, 0x002d);
3008 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3009 rtl_writephy(tp, 0x1f, 0x0000);
3010 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3011
3012 /* Improve 10M EEE waveform */
3013 rtl_writephy(tp, 0x1f, 0x0005);
3014 rtl_writephy(tp, 0x05, 0x8b86);
3015 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3016 rtl_writephy(tp, 0x1f, 0x0000);
3017
3018 /* Improve 2-pair detection performance */
3019 rtl_writephy(tp, 0x1f, 0x0005);
3020 rtl_writephy(tp, 0x05, 0x8b85);
3021 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3022 rtl_writephy(tp, 0x1f, 0x0000);
3023 }
3024
3025 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3026 {
3027 rtl_apply_firmware(tp);
3028
3029 /* For 4-corner performance improve */
3030 rtl_writephy(tp, 0x1f, 0x0005);
3031 rtl_writephy(tp, 0x05, 0x8b80);
3032 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3033 rtl_writephy(tp, 0x1f, 0x0000);
3034
3035 /* PHY auto speed down */
3036 rtl_writephy(tp, 0x1f, 0x0007);
3037 rtl_writephy(tp, 0x1e, 0x002d);
3038 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3039 rtl_writephy(tp, 0x1f, 0x0000);
3040 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3041
3042 /* Improve 10M EEE waveform */
3043 rtl_writephy(tp, 0x1f, 0x0005);
3044 rtl_writephy(tp, 0x05, 0x8b86);
3045 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3046 rtl_writephy(tp, 0x1f, 0x0000);
3047 }
3048
3049 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3050 {
3051 static const struct phy_reg phy_reg_init[] = {
3052 { 0x1f, 0x0003 },
3053 { 0x08, 0x441d },
3054 { 0x01, 0x9100 },
3055 { 0x1f, 0x0000 }
3056 };
3057
3058 rtl_writephy(tp, 0x1f, 0x0000);
3059 rtl_patchphy(tp, 0x11, 1 << 12);
3060 rtl_patchphy(tp, 0x19, 1 << 13);
3061 rtl_patchphy(tp, 0x10, 1 << 15);
3062
3063 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3064 }
3065
3066 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3067 {
3068 static const struct phy_reg phy_reg_init[] = {
3069 { 0x1f, 0x0005 },
3070 { 0x1a, 0x0000 },
3071 { 0x1f, 0x0000 },
3072
3073 { 0x1f, 0x0004 },
3074 { 0x1c, 0x0000 },
3075 { 0x1f, 0x0000 },
3076
3077 { 0x1f, 0x0001 },
3078 { 0x15, 0x7701 },
3079 { 0x1f, 0x0000 }
3080 };
3081
3082 /* Disable ALDPS before ram code */
3083 rtl_writephy(tp, 0x1f, 0x0000);
3084 rtl_writephy(tp, 0x18, 0x0310);
3085 msleep(100);
3086
3087 rtl_apply_firmware(tp);
3088
3089 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3090 }
3091
3092 static void rtl_hw_phy_config(struct net_device *dev)
3093 {
3094 struct rtl8169_private *tp = netdev_priv(dev);
3095
3096 rtl8169_print_mac_version(tp);
3097
3098 switch (tp->mac_version) {
3099 case RTL_GIGA_MAC_VER_01:
3100 break;
3101 case RTL_GIGA_MAC_VER_02:
3102 case RTL_GIGA_MAC_VER_03:
3103 rtl8169s_hw_phy_config(tp);
3104 break;
3105 case RTL_GIGA_MAC_VER_04:
3106 rtl8169sb_hw_phy_config(tp);
3107 break;
3108 case RTL_GIGA_MAC_VER_05:
3109 rtl8169scd_hw_phy_config(tp);
3110 break;
3111 case RTL_GIGA_MAC_VER_06:
3112 rtl8169sce_hw_phy_config(tp);
3113 break;
3114 case RTL_GIGA_MAC_VER_07:
3115 case RTL_GIGA_MAC_VER_08:
3116 case RTL_GIGA_MAC_VER_09:
3117 rtl8102e_hw_phy_config(tp);
3118 break;
3119 case RTL_GIGA_MAC_VER_11:
3120 rtl8168bb_hw_phy_config(tp);
3121 break;
3122 case RTL_GIGA_MAC_VER_12:
3123 rtl8168bef_hw_phy_config(tp);
3124 break;
3125 case RTL_GIGA_MAC_VER_17:
3126 rtl8168bef_hw_phy_config(tp);
3127 break;
3128 case RTL_GIGA_MAC_VER_18:
3129 rtl8168cp_1_hw_phy_config(tp);
3130 break;
3131 case RTL_GIGA_MAC_VER_19:
3132 rtl8168c_1_hw_phy_config(tp);
3133 break;
3134 case RTL_GIGA_MAC_VER_20:
3135 rtl8168c_2_hw_phy_config(tp);
3136 break;
3137 case RTL_GIGA_MAC_VER_21:
3138 rtl8168c_3_hw_phy_config(tp);
3139 break;
3140 case RTL_GIGA_MAC_VER_22:
3141 rtl8168c_4_hw_phy_config(tp);
3142 break;
3143 case RTL_GIGA_MAC_VER_23:
3144 case RTL_GIGA_MAC_VER_24:
3145 rtl8168cp_2_hw_phy_config(tp);
3146 break;
3147 case RTL_GIGA_MAC_VER_25:
3148 rtl8168d_1_hw_phy_config(tp);
3149 break;
3150 case RTL_GIGA_MAC_VER_26:
3151 rtl8168d_2_hw_phy_config(tp);
3152 break;
3153 case RTL_GIGA_MAC_VER_27:
3154 rtl8168d_3_hw_phy_config(tp);
3155 break;
3156 case RTL_GIGA_MAC_VER_28:
3157 rtl8168d_4_hw_phy_config(tp);
3158 break;
3159 case RTL_GIGA_MAC_VER_29:
3160 case RTL_GIGA_MAC_VER_30:
3161 rtl8105e_hw_phy_config(tp);
3162 break;
3163 case RTL_GIGA_MAC_VER_31:
3164 /* None. */
3165 break;
3166 case RTL_GIGA_MAC_VER_32:
3167 case RTL_GIGA_MAC_VER_33:
3168 rtl8168e_1_hw_phy_config(tp);
3169 break;
3170 case RTL_GIGA_MAC_VER_34:
3171 rtl8168e_2_hw_phy_config(tp);
3172 break;
3173 case RTL_GIGA_MAC_VER_35:
3174 rtl8168f_1_hw_phy_config(tp);
3175 break;
3176 case RTL_GIGA_MAC_VER_36:
3177 rtl8168f_2_hw_phy_config(tp);
3178 break;
3179
3180 default:
3181 break;
3182 }
3183 }
3184
3185 static void rtl8169_phy_timer(unsigned long __opaque)
3186 {
3187 struct net_device *dev = (struct net_device *)__opaque;
3188 struct rtl8169_private *tp = netdev_priv(dev);
3189 struct timer_list *timer = &tp->timer;
3190 void __iomem *ioaddr = tp->mmio_addr;
3191 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3192
3193 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3194
3195 spin_lock_irq(&tp->lock);
3196
3197 if (tp->phy_reset_pending(tp)) {
3198 /*
3199 * A busy loop could burn quite a few cycles on nowadays CPU.
3200 * Let's delay the execution of the timer for a few ticks.
3201 */
3202 timeout = HZ/10;
3203 goto out_mod_timer;
3204 }
3205
3206 if (tp->link_ok(ioaddr))
3207 goto out_unlock;
3208
3209 netif_warn(tp, link, dev, "PHY reset until link up\n");
3210
3211 tp->phy_reset_enable(tp);
3212
3213 out_mod_timer:
3214 mod_timer(timer, jiffies + timeout);
3215 out_unlock:
3216 spin_unlock_irq(&tp->lock);
3217 }
3218
3219 #ifdef CONFIG_NET_POLL_CONTROLLER
3220 /*
3221 * Polling 'interrupt' - used by things like netconsole to send skbs
3222 * without having to re-enable interrupts. It's not called while
3223 * the interrupt routine is executing.
3224 */
3225 static void rtl8169_netpoll(struct net_device *dev)
3226 {
3227 struct rtl8169_private *tp = netdev_priv(dev);
3228 struct pci_dev *pdev = tp->pci_dev;
3229
3230 disable_irq(pdev->irq);
3231 rtl8169_interrupt(pdev->irq, dev);
3232 enable_irq(pdev->irq);
3233 }
3234 #endif
3235
3236 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3237 void __iomem *ioaddr)
3238 {
3239 iounmap(ioaddr);
3240 pci_release_regions(pdev);
3241 pci_clear_mwi(pdev);
3242 pci_disable_device(pdev);
3243 free_netdev(dev);
3244 }
3245
3246 static void rtl8169_phy_reset(struct net_device *dev,
3247 struct rtl8169_private *tp)
3248 {
3249 unsigned int i;
3250
3251 tp->phy_reset_enable(tp);
3252 for (i = 0; i < 100; i++) {
3253 if (!tp->phy_reset_pending(tp))
3254 return;
3255 msleep(1);
3256 }
3257 netif_err(tp, link, dev, "PHY reset failed\n");
3258 }
3259
3260 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3261 {
3262 void __iomem *ioaddr = tp->mmio_addr;
3263
3264 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3265 (RTL_R8(PHYstatus) & TBI_Enable);
3266 }
3267
3268 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3269 {
3270 void __iomem *ioaddr = tp->mmio_addr;
3271
3272 rtl_hw_phy_config(dev);
3273
3274 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3275 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3276 RTL_W8(0x82, 0x01);
3277 }
3278
3279 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3280
3281 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3282 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3283
3284 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3285 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3286 RTL_W8(0x82, 0x01);
3287 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3288 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3289 }
3290
3291 rtl8169_phy_reset(dev, tp);
3292
3293 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3294 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3295 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3296 (tp->mii.supports_gmii ?
3297 ADVERTISED_1000baseT_Half |
3298 ADVERTISED_1000baseT_Full : 0));
3299
3300 if (rtl_tbi_enabled(tp))
3301 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3302 }
3303
3304 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3305 {
3306 void __iomem *ioaddr = tp->mmio_addr;
3307 u32 high;
3308 u32 low;
3309
3310 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3311 high = addr[4] | (addr[5] << 8);
3312
3313 spin_lock_irq(&tp->lock);
3314
3315 RTL_W8(Cfg9346, Cfg9346_Unlock);
3316
3317 RTL_W32(MAC4, high);
3318 RTL_R32(MAC4);
3319
3320 RTL_W32(MAC0, low);
3321 RTL_R32(MAC0);
3322
3323 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3324 const struct exgmac_reg e[] = {
3325 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3326 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3327 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3328 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3329 low >> 16 },
3330 };
3331
3332 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3333 }
3334
3335 RTL_W8(Cfg9346, Cfg9346_Lock);
3336
3337 spin_unlock_irq(&tp->lock);
3338 }
3339
3340 static int rtl_set_mac_address(struct net_device *dev, void *p)
3341 {
3342 struct rtl8169_private *tp = netdev_priv(dev);
3343 struct sockaddr *addr = p;
3344
3345 if (!is_valid_ether_addr(addr->sa_data))
3346 return -EADDRNOTAVAIL;
3347
3348 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3349
3350 rtl_rar_set(tp, dev->dev_addr);
3351
3352 return 0;
3353 }
3354
3355 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3356 {
3357 struct rtl8169_private *tp = netdev_priv(dev);
3358 struct mii_ioctl_data *data = if_mii(ifr);
3359
3360 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3361 }
3362
3363 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3364 struct mii_ioctl_data *data, int cmd)
3365 {
3366 switch (cmd) {
3367 case SIOCGMIIPHY:
3368 data->phy_id = 32; /* Internal PHY */
3369 return 0;
3370
3371 case SIOCGMIIREG:
3372 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3373 return 0;
3374
3375 case SIOCSMIIREG:
3376 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3377 return 0;
3378 }
3379 return -EOPNOTSUPP;
3380 }
3381
3382 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3383 {
3384 return -EOPNOTSUPP;
3385 }
3386
3387 static const struct rtl_cfg_info {
3388 void (*hw_start)(struct net_device *);
3389 unsigned int region;
3390 unsigned int align;
3391 u16 intr_event;
3392 u16 napi_event;
3393 unsigned features;
3394 u8 default_ver;
3395 } rtl_cfg_infos [] = {
3396 [RTL_CFG_0] = {
3397 .hw_start = rtl_hw_start_8169,
3398 .region = 1,
3399 .align = 0,
3400 .intr_event = SYSErr | LinkChg | RxOverflow |
3401 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3402 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3403 .features = RTL_FEATURE_GMII,
3404 .default_ver = RTL_GIGA_MAC_VER_01,
3405 },
3406 [RTL_CFG_1] = {
3407 .hw_start = rtl_hw_start_8168,
3408 .region = 2,
3409 .align = 8,
3410 .intr_event = SYSErr | LinkChg | RxOverflow |
3411 TxErr | TxOK | RxOK | RxErr,
3412 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
3413 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3414 .default_ver = RTL_GIGA_MAC_VER_11,
3415 },
3416 [RTL_CFG_2] = {
3417 .hw_start = rtl_hw_start_8101,
3418 .region = 2,
3419 .align = 8,
3420 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3421 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3422 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3423 .features = RTL_FEATURE_MSI,
3424 .default_ver = RTL_GIGA_MAC_VER_13,
3425 }
3426 };
3427
3428 /* Cfg9346_Unlock assumed. */
3429 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3430 const struct rtl_cfg_info *cfg)
3431 {
3432 void __iomem *ioaddr = tp->mmio_addr;
3433 unsigned msi = 0;
3434 u8 cfg2;
3435
3436 cfg2 = RTL_R8(Config2) & ~MSIEnable;
3437 if (cfg->features & RTL_FEATURE_MSI) {
3438 if (pci_enable_msi(tp->pci_dev)) {
3439 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3440 } else {
3441 cfg2 |= MSIEnable;
3442 msi = RTL_FEATURE_MSI;
3443 }
3444 }
3445 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3446 RTL_W8(Config2, cfg2);
3447 return msi;
3448 }
3449
3450 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3451 {
3452 if (tp->features & RTL_FEATURE_MSI) {
3453 pci_disable_msi(pdev);
3454 tp->features &= ~RTL_FEATURE_MSI;
3455 }
3456 }
3457
3458 static const struct net_device_ops rtl8169_netdev_ops = {
3459 .ndo_open = rtl8169_open,
3460 .ndo_stop = rtl8169_close,
3461 .ndo_get_stats = rtl8169_get_stats,
3462 .ndo_start_xmit = rtl8169_start_xmit,
3463 .ndo_tx_timeout = rtl8169_tx_timeout,
3464 .ndo_validate_addr = eth_validate_addr,
3465 .ndo_change_mtu = rtl8169_change_mtu,
3466 .ndo_fix_features = rtl8169_fix_features,
3467 .ndo_set_features = rtl8169_set_features,
3468 .ndo_set_mac_address = rtl_set_mac_address,
3469 .ndo_do_ioctl = rtl8169_ioctl,
3470 .ndo_set_rx_mode = rtl_set_rx_mode,
3471 #ifdef CONFIG_NET_POLL_CONTROLLER
3472 .ndo_poll_controller = rtl8169_netpoll,
3473 #endif
3474
3475 };
3476
3477 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3478 {
3479 struct mdio_ops *ops = &tp->mdio_ops;
3480
3481 switch (tp->mac_version) {
3482 case RTL_GIGA_MAC_VER_27:
3483 ops->write = r8168dp_1_mdio_write;
3484 ops->read = r8168dp_1_mdio_read;
3485 break;
3486 case RTL_GIGA_MAC_VER_28:
3487 case RTL_GIGA_MAC_VER_31:
3488 ops->write = r8168dp_2_mdio_write;
3489 ops->read = r8168dp_2_mdio_read;
3490 break;
3491 default:
3492 ops->write = r8169_mdio_write;
3493 ops->read = r8169_mdio_read;
3494 break;
3495 }
3496 }
3497
3498 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3499 {
3500 void __iomem *ioaddr = tp->mmio_addr;
3501
3502 switch (tp->mac_version) {
3503 case RTL_GIGA_MAC_VER_29:
3504 case RTL_GIGA_MAC_VER_30:
3505 case RTL_GIGA_MAC_VER_32:
3506 case RTL_GIGA_MAC_VER_33:
3507 case RTL_GIGA_MAC_VER_34:
3508 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3509 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3510 break;
3511 default:
3512 break;
3513 }
3514 }
3515
3516 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3517 {
3518 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3519 return false;
3520
3521 rtl_writephy(tp, 0x1f, 0x0000);
3522 rtl_writephy(tp, MII_BMCR, 0x0000);
3523
3524 rtl_wol_suspend_quirk(tp);
3525
3526 return true;
3527 }
3528
3529 static void r810x_phy_power_down(struct rtl8169_private *tp)
3530 {
3531 rtl_writephy(tp, 0x1f, 0x0000);
3532 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3533 }
3534
3535 static void r810x_phy_power_up(struct rtl8169_private *tp)
3536 {
3537 rtl_writephy(tp, 0x1f, 0x0000);
3538 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3539 }
3540
3541 static void r810x_pll_power_down(struct rtl8169_private *tp)
3542 {
3543 if (rtl_wol_pll_power_down(tp))
3544 return;
3545
3546 r810x_phy_power_down(tp);
3547 }
3548
3549 static void r810x_pll_power_up(struct rtl8169_private *tp)
3550 {
3551 r810x_phy_power_up(tp);
3552 }
3553
3554 static void r8168_phy_power_up(struct rtl8169_private *tp)
3555 {
3556 rtl_writephy(tp, 0x1f, 0x0000);
3557 switch (tp->mac_version) {
3558 case RTL_GIGA_MAC_VER_11:
3559 case RTL_GIGA_MAC_VER_12:
3560 case RTL_GIGA_MAC_VER_17:
3561 case RTL_GIGA_MAC_VER_18:
3562 case RTL_GIGA_MAC_VER_19:
3563 case RTL_GIGA_MAC_VER_20:
3564 case RTL_GIGA_MAC_VER_21:
3565 case RTL_GIGA_MAC_VER_22:
3566 case RTL_GIGA_MAC_VER_23:
3567 case RTL_GIGA_MAC_VER_24:
3568 case RTL_GIGA_MAC_VER_25:
3569 case RTL_GIGA_MAC_VER_26:
3570 case RTL_GIGA_MAC_VER_27:
3571 case RTL_GIGA_MAC_VER_28:
3572 case RTL_GIGA_MAC_VER_31:
3573 rtl_writephy(tp, 0x0e, 0x0000);
3574 break;
3575 default:
3576 break;
3577 }
3578 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3579 }
3580
3581 static void r8168_phy_power_down(struct rtl8169_private *tp)
3582 {
3583 rtl_writephy(tp, 0x1f, 0x0000);
3584 switch (tp->mac_version) {
3585 case RTL_GIGA_MAC_VER_32:
3586 case RTL_GIGA_MAC_VER_33:
3587 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3588 break;
3589
3590 case RTL_GIGA_MAC_VER_11:
3591 case RTL_GIGA_MAC_VER_12:
3592 case RTL_GIGA_MAC_VER_17:
3593 case RTL_GIGA_MAC_VER_18:
3594 case RTL_GIGA_MAC_VER_19:
3595 case RTL_GIGA_MAC_VER_20:
3596 case RTL_GIGA_MAC_VER_21:
3597 case RTL_GIGA_MAC_VER_22:
3598 case RTL_GIGA_MAC_VER_23:
3599 case RTL_GIGA_MAC_VER_24:
3600 case RTL_GIGA_MAC_VER_25:
3601 case RTL_GIGA_MAC_VER_26:
3602 case RTL_GIGA_MAC_VER_27:
3603 case RTL_GIGA_MAC_VER_28:
3604 case RTL_GIGA_MAC_VER_31:
3605 rtl_writephy(tp, 0x0e, 0x0200);
3606 default:
3607 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3608 break;
3609 }
3610 }
3611
3612 static void r8168_pll_power_down(struct rtl8169_private *tp)
3613 {
3614 void __iomem *ioaddr = tp->mmio_addr;
3615
3616 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3617 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3618 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3619 r8168dp_check_dash(tp)) {
3620 return;
3621 }
3622
3623 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3624 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3625 (RTL_R16(CPlusCmd) & ASF)) {
3626 return;
3627 }
3628
3629 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3630 tp->mac_version == RTL_GIGA_MAC_VER_33)
3631 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3632
3633 if (rtl_wol_pll_power_down(tp))
3634 return;
3635
3636 r8168_phy_power_down(tp);
3637
3638 switch (tp->mac_version) {
3639 case RTL_GIGA_MAC_VER_25:
3640 case RTL_GIGA_MAC_VER_26:
3641 case RTL_GIGA_MAC_VER_27:
3642 case RTL_GIGA_MAC_VER_28:
3643 case RTL_GIGA_MAC_VER_31:
3644 case RTL_GIGA_MAC_VER_32:
3645 case RTL_GIGA_MAC_VER_33:
3646 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3647 break;
3648 }
3649 }
3650
3651 static void r8168_pll_power_up(struct rtl8169_private *tp)
3652 {
3653 void __iomem *ioaddr = tp->mmio_addr;
3654
3655 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3656 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3657 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3658 r8168dp_check_dash(tp)) {
3659 return;
3660 }
3661
3662 switch (tp->mac_version) {
3663 case RTL_GIGA_MAC_VER_25:
3664 case RTL_GIGA_MAC_VER_26:
3665 case RTL_GIGA_MAC_VER_27:
3666 case RTL_GIGA_MAC_VER_28:
3667 case RTL_GIGA_MAC_VER_31:
3668 case RTL_GIGA_MAC_VER_32:
3669 case RTL_GIGA_MAC_VER_33:
3670 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3671 break;
3672 }
3673
3674 r8168_phy_power_up(tp);
3675 }
3676
3677 static void rtl_generic_op(struct rtl8169_private *tp,
3678 void (*op)(struct rtl8169_private *))
3679 {
3680 if (op)
3681 op(tp);
3682 }
3683
3684 static void rtl_pll_power_down(struct rtl8169_private *tp)
3685 {
3686 rtl_generic_op(tp, tp->pll_power_ops.down);
3687 }
3688
3689 static void rtl_pll_power_up(struct rtl8169_private *tp)
3690 {
3691 rtl_generic_op(tp, tp->pll_power_ops.up);
3692 }
3693
3694 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3695 {
3696 struct pll_power_ops *ops = &tp->pll_power_ops;
3697
3698 switch (tp->mac_version) {
3699 case RTL_GIGA_MAC_VER_07:
3700 case RTL_GIGA_MAC_VER_08:
3701 case RTL_GIGA_MAC_VER_09:
3702 case RTL_GIGA_MAC_VER_10:
3703 case RTL_GIGA_MAC_VER_16:
3704 case RTL_GIGA_MAC_VER_29:
3705 case RTL_GIGA_MAC_VER_30:
3706 ops->down = r810x_pll_power_down;
3707 ops->up = r810x_pll_power_up;
3708 break;
3709
3710 case RTL_GIGA_MAC_VER_11:
3711 case RTL_GIGA_MAC_VER_12:
3712 case RTL_GIGA_MAC_VER_17:
3713 case RTL_GIGA_MAC_VER_18:
3714 case RTL_GIGA_MAC_VER_19:
3715 case RTL_GIGA_MAC_VER_20:
3716 case RTL_GIGA_MAC_VER_21:
3717 case RTL_GIGA_MAC_VER_22:
3718 case RTL_GIGA_MAC_VER_23:
3719 case RTL_GIGA_MAC_VER_24:
3720 case RTL_GIGA_MAC_VER_25:
3721 case RTL_GIGA_MAC_VER_26:
3722 case RTL_GIGA_MAC_VER_27:
3723 case RTL_GIGA_MAC_VER_28:
3724 case RTL_GIGA_MAC_VER_31:
3725 case RTL_GIGA_MAC_VER_32:
3726 case RTL_GIGA_MAC_VER_33:
3727 case RTL_GIGA_MAC_VER_34:
3728 case RTL_GIGA_MAC_VER_35:
3729 case RTL_GIGA_MAC_VER_36:
3730 ops->down = r8168_pll_power_down;
3731 ops->up = r8168_pll_power_up;
3732 break;
3733
3734 default:
3735 ops->down = NULL;
3736 ops->up = NULL;
3737 break;
3738 }
3739 }
3740
3741 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3742 {
3743 void __iomem *ioaddr = tp->mmio_addr;
3744
3745 switch (tp->mac_version) {
3746 case RTL_GIGA_MAC_VER_01:
3747 case RTL_GIGA_MAC_VER_02:
3748 case RTL_GIGA_MAC_VER_03:
3749 case RTL_GIGA_MAC_VER_04:
3750 case RTL_GIGA_MAC_VER_05:
3751 case RTL_GIGA_MAC_VER_06:
3752 case RTL_GIGA_MAC_VER_10:
3753 case RTL_GIGA_MAC_VER_11:
3754 case RTL_GIGA_MAC_VER_12:
3755 case RTL_GIGA_MAC_VER_13:
3756 case RTL_GIGA_MAC_VER_14:
3757 case RTL_GIGA_MAC_VER_15:
3758 case RTL_GIGA_MAC_VER_16:
3759 case RTL_GIGA_MAC_VER_17:
3760 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3761 break;
3762 case RTL_GIGA_MAC_VER_18:
3763 case RTL_GIGA_MAC_VER_19:
3764 case RTL_GIGA_MAC_VER_20:
3765 case RTL_GIGA_MAC_VER_21:
3766 case RTL_GIGA_MAC_VER_22:
3767 case RTL_GIGA_MAC_VER_23:
3768 case RTL_GIGA_MAC_VER_24:
3769 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3770 break;
3771 default:
3772 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3773 break;
3774 }
3775 }
3776
3777 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3778 {
3779 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3780 }
3781
3782 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3783 {
3784 rtl_generic_op(tp, tp->jumbo_ops.enable);
3785 }
3786
3787 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3788 {
3789 rtl_generic_op(tp, tp->jumbo_ops.disable);
3790 }
3791
3792 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3793 {
3794 void __iomem *ioaddr = tp->mmio_addr;
3795
3796 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3797 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3798 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3799 }
3800
3801 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3802 {
3803 void __iomem *ioaddr = tp->mmio_addr;
3804
3805 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3806 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3807 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3808 }
3809
3810 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3811 {
3812 void __iomem *ioaddr = tp->mmio_addr;
3813
3814 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3815 }
3816
3817 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3818 {
3819 void __iomem *ioaddr = tp->mmio_addr;
3820
3821 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3822 }
3823
3824 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3825 {
3826 void __iomem *ioaddr = tp->mmio_addr;
3827 struct pci_dev *pdev = tp->pci_dev;
3828
3829 RTL_W8(MaxTxPacketSize, 0x3f);
3830 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3831 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3832 pci_write_config_byte(pdev, 0x79, 0x20);
3833 }
3834
3835 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3836 {
3837 void __iomem *ioaddr = tp->mmio_addr;
3838 struct pci_dev *pdev = tp->pci_dev;
3839
3840 RTL_W8(MaxTxPacketSize, 0x0c);
3841 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3842 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3843 pci_write_config_byte(pdev, 0x79, 0x50);
3844 }
3845
3846 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3847 {
3848 rtl_tx_performance_tweak(tp->pci_dev,
3849 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3850 }
3851
3852 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3853 {
3854 rtl_tx_performance_tweak(tp->pci_dev,
3855 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3856 }
3857
3858 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3859 {
3860 void __iomem *ioaddr = tp->mmio_addr;
3861
3862 r8168b_0_hw_jumbo_enable(tp);
3863
3864 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3865 }
3866
3867 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3868 {
3869 void __iomem *ioaddr = tp->mmio_addr;
3870
3871 r8168b_0_hw_jumbo_disable(tp);
3872
3873 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3874 }
3875
3876 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3877 {
3878 struct jumbo_ops *ops = &tp->jumbo_ops;
3879
3880 switch (tp->mac_version) {
3881 case RTL_GIGA_MAC_VER_11:
3882 ops->disable = r8168b_0_hw_jumbo_disable;
3883 ops->enable = r8168b_0_hw_jumbo_enable;
3884 break;
3885 case RTL_GIGA_MAC_VER_12:
3886 case RTL_GIGA_MAC_VER_17:
3887 ops->disable = r8168b_1_hw_jumbo_disable;
3888 ops->enable = r8168b_1_hw_jumbo_enable;
3889 break;
3890 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3891 case RTL_GIGA_MAC_VER_19:
3892 case RTL_GIGA_MAC_VER_20:
3893 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3894 case RTL_GIGA_MAC_VER_22:
3895 case RTL_GIGA_MAC_VER_23:
3896 case RTL_GIGA_MAC_VER_24:
3897 case RTL_GIGA_MAC_VER_25:
3898 case RTL_GIGA_MAC_VER_26:
3899 ops->disable = r8168c_hw_jumbo_disable;
3900 ops->enable = r8168c_hw_jumbo_enable;
3901 break;
3902 case RTL_GIGA_MAC_VER_27:
3903 case RTL_GIGA_MAC_VER_28:
3904 ops->disable = r8168dp_hw_jumbo_disable;
3905 ops->enable = r8168dp_hw_jumbo_enable;
3906 break;
3907 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3908 case RTL_GIGA_MAC_VER_32:
3909 case RTL_GIGA_MAC_VER_33:
3910 case RTL_GIGA_MAC_VER_34:
3911 ops->disable = r8168e_hw_jumbo_disable;
3912 ops->enable = r8168e_hw_jumbo_enable;
3913 break;
3914
3915 /*
3916 * No action needed for jumbo frames with 8169.
3917 * No jumbo for 810x at all.
3918 */
3919 default:
3920 ops->disable = NULL;
3921 ops->enable = NULL;
3922 break;
3923 }
3924 }
3925
3926 static void rtl_hw_reset(struct rtl8169_private *tp)
3927 {
3928 void __iomem *ioaddr = tp->mmio_addr;
3929 int i;
3930
3931 /* Soft reset the chip. */
3932 RTL_W8(ChipCmd, CmdReset);
3933
3934 /* Check that the chip has finished the reset. */
3935 for (i = 0; i < 100; i++) {
3936 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3937 break;
3938 udelay(100);
3939 }
3940 }
3941
3942 static int __devinit
3943 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3944 {
3945 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3946 const unsigned int region = cfg->region;
3947 struct rtl8169_private *tp;
3948 struct mii_if_info *mii;
3949 struct net_device *dev;
3950 void __iomem *ioaddr;
3951 int chipset, i;
3952 int rc;
3953
3954 if (netif_msg_drv(&debug)) {
3955 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3956 MODULENAME, RTL8169_VERSION);
3957 }
3958
3959 dev = alloc_etherdev(sizeof (*tp));
3960 if (!dev) {
3961 if (netif_msg_drv(&debug))
3962 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3963 rc = -ENOMEM;
3964 goto out;
3965 }
3966
3967 SET_NETDEV_DEV(dev, &pdev->dev);
3968 dev->netdev_ops = &rtl8169_netdev_ops;
3969 tp = netdev_priv(dev);
3970 tp->dev = dev;
3971 tp->pci_dev = pdev;
3972 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3973
3974 mii = &tp->mii;
3975 mii->dev = dev;
3976 mii->mdio_read = rtl_mdio_read;
3977 mii->mdio_write = rtl_mdio_write;
3978 mii->phy_id_mask = 0x1f;
3979 mii->reg_num_mask = 0x1f;
3980 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3981
3982 /* disable ASPM completely as that cause random device stop working
3983 * problems as well as full system hangs for some PCIe devices users */
3984 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3985 PCIE_LINK_STATE_CLKPM);
3986
3987 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3988 rc = pci_enable_device(pdev);
3989 if (rc < 0) {
3990 netif_err(tp, probe, dev, "enable failure\n");
3991 goto err_out_free_dev_1;
3992 }
3993
3994 if (pci_set_mwi(pdev) < 0)
3995 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3996
3997 /* make sure PCI base addr 1 is MMIO */
3998 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3999 netif_err(tp, probe, dev,
4000 "region #%d not an MMIO resource, aborting\n",
4001 region);
4002 rc = -ENODEV;
4003 goto err_out_mwi_2;
4004 }
4005
4006 /* check for weird/broken PCI region reporting */
4007 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4008 netif_err(tp, probe, dev,
4009 "Invalid PCI region size(s), aborting\n");
4010 rc = -ENODEV;
4011 goto err_out_mwi_2;
4012 }
4013
4014 rc = pci_request_regions(pdev, MODULENAME);
4015 if (rc < 0) {
4016 netif_err(tp, probe, dev, "could not request regions\n");
4017 goto err_out_mwi_2;
4018 }
4019
4020 tp->cp_cmd = RxChkSum;
4021
4022 if ((sizeof(dma_addr_t) > 4) &&
4023 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
4024 tp->cp_cmd |= PCIDAC;
4025 dev->features |= NETIF_F_HIGHDMA;
4026 } else {
4027 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4028 if (rc < 0) {
4029 netif_err(tp, probe, dev, "DMA configuration failed\n");
4030 goto err_out_free_res_3;
4031 }
4032 }
4033
4034 /* ioremap MMIO region */
4035 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4036 if (!ioaddr) {
4037 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
4038 rc = -EIO;
4039 goto err_out_free_res_3;
4040 }
4041 tp->mmio_addr = ioaddr;
4042
4043 if (!pci_is_pcie(pdev))
4044 netif_info(tp, probe, dev, "not PCI Express\n");
4045
4046 /* Identify chip attached to board */
4047 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4048
4049 rtl_init_rxcfg(tp);
4050
4051 RTL_W16(IntrMask, 0x0000);
4052
4053 rtl_hw_reset(tp);
4054
4055 RTL_W16(IntrStatus, 0xffff);
4056
4057 pci_set_master(pdev);
4058
4059 /*
4060 * Pretend we are using VLANs; This bypasses a nasty bug where
4061 * Interrupts stop flowing on high load on 8110SCd controllers.
4062 */
4063 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4064 tp->cp_cmd |= RxVlan;
4065
4066 rtl_init_mdio_ops(tp);
4067 rtl_init_pll_power_ops(tp);
4068 rtl_init_jumbo_ops(tp);
4069
4070 rtl8169_print_mac_version(tp);
4071
4072 chipset = tp->mac_version;
4073 tp->txd_version = rtl_chip_infos[chipset].txd_version;
4074
4075 RTL_W8(Cfg9346, Cfg9346_Unlock);
4076 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4077 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
4078 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4079 tp->features |= RTL_FEATURE_WOL;
4080 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4081 tp->features |= RTL_FEATURE_WOL;
4082 tp->features |= rtl_try_msi(tp, cfg);
4083 RTL_W8(Cfg9346, Cfg9346_Lock);
4084
4085 if (rtl_tbi_enabled(tp)) {
4086 tp->set_speed = rtl8169_set_speed_tbi;
4087 tp->get_settings = rtl8169_gset_tbi;
4088 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4089 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4090 tp->link_ok = rtl8169_tbi_link_ok;
4091 tp->do_ioctl = rtl_tbi_ioctl;
4092 } else {
4093 tp->set_speed = rtl8169_set_speed_xmii;
4094 tp->get_settings = rtl8169_gset_xmii;
4095 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4096 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4097 tp->link_ok = rtl8169_xmii_link_ok;
4098 tp->do_ioctl = rtl_xmii_ioctl;
4099 }
4100
4101 spin_lock_init(&tp->lock);
4102
4103 /* Get MAC address */
4104 for (i = 0; i < MAC_ADDR_LEN; i++)
4105 dev->dev_addr[i] = RTL_R8(MAC0 + i);
4106 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4107
4108 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
4109 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4110 dev->irq = pdev->irq;
4111 dev->base_addr = (unsigned long) ioaddr;
4112
4113 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
4114
4115 /* don't enable SG, IP_CSUM and TSO by default - it might not work
4116 * properly for all devices */
4117 dev->features |= NETIF_F_RXCSUM |
4118 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4119
4120 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4121 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4122 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4123 NETIF_F_HIGHDMA;
4124
4125 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4126 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4127 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
4128
4129 tp->intr_mask = 0xffff;
4130 tp->hw_start = cfg->hw_start;
4131 tp->intr_event = cfg->intr_event;
4132 tp->napi_event = cfg->napi_event;
4133
4134 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4135 ~(RxBOVF | RxFOVF) : ~0;
4136
4137 init_timer(&tp->timer);
4138 tp->timer.data = (unsigned long) dev;
4139 tp->timer.function = rtl8169_phy_timer;
4140
4141 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
4142
4143 rc = register_netdev(dev);
4144 if (rc < 0)
4145 goto err_out_msi_4;
4146
4147 pci_set_drvdata(pdev, dev);
4148
4149 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4150 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
4151 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
4152 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4153 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4154 "tx checksumming: %s]\n",
4155 rtl_chip_infos[chipset].jumbo_max,
4156 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4157 }
4158
4159 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4160 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4161 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4162 rtl8168_driver_start(tp);
4163 }
4164
4165 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
4166
4167 if (pci_dev_run_wake(pdev))
4168 pm_runtime_put_noidle(&pdev->dev);
4169
4170 netif_carrier_off(dev);
4171
4172 out:
4173 return rc;
4174
4175 err_out_msi_4:
4176 rtl_disable_msi(pdev, tp);
4177 iounmap(ioaddr);
4178 err_out_free_res_3:
4179 pci_release_regions(pdev);
4180 err_out_mwi_2:
4181 pci_clear_mwi(pdev);
4182 pci_disable_device(pdev);
4183 err_out_free_dev_1:
4184 free_netdev(dev);
4185 goto out;
4186 }
4187
4188 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
4189 {
4190 struct net_device *dev = pci_get_drvdata(pdev);
4191 struct rtl8169_private *tp = netdev_priv(dev);
4192
4193 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4194 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4195 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4196 rtl8168_driver_stop(tp);
4197 }
4198
4199 cancel_delayed_work_sync(&tp->task);
4200
4201 unregister_netdev(dev);
4202
4203 rtl_release_firmware(tp);
4204
4205 if (pci_dev_run_wake(pdev))
4206 pm_runtime_get_noresume(&pdev->dev);
4207
4208 /* restore original MAC address */
4209 rtl_rar_set(tp, dev->perm_addr);
4210
4211 rtl_disable_msi(pdev, tp);
4212 rtl8169_release_board(pdev, dev, tp->mmio_addr);
4213 pci_set_drvdata(pdev, NULL);
4214 }
4215
4216 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4217 {
4218 struct rtl_fw *rtl_fw;
4219 const char *name;
4220 int rc = -ENOMEM;
4221
4222 name = rtl_lookup_firmware_name(tp);
4223 if (!name)
4224 goto out_no_firmware;
4225
4226 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4227 if (!rtl_fw)
4228 goto err_warn;
4229
4230 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4231 if (rc < 0)
4232 goto err_free;
4233
4234 rc = rtl_check_firmware(tp, rtl_fw);
4235 if (rc < 0)
4236 goto err_release_firmware;
4237
4238 tp->rtl_fw = rtl_fw;
4239 out:
4240 return;
4241
4242 err_release_firmware:
4243 release_firmware(rtl_fw->fw);
4244 err_free:
4245 kfree(rtl_fw);
4246 err_warn:
4247 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4248 name, rc);
4249 out_no_firmware:
4250 tp->rtl_fw = NULL;
4251 goto out;
4252 }
4253
4254 static void rtl_request_firmware(struct rtl8169_private *tp)
4255 {
4256 if (IS_ERR(tp->rtl_fw))
4257 rtl_request_uncached_firmware(tp);
4258 }
4259
4260 static int rtl8169_open(struct net_device *dev)
4261 {
4262 struct rtl8169_private *tp = netdev_priv(dev);
4263 void __iomem *ioaddr = tp->mmio_addr;
4264 struct pci_dev *pdev = tp->pci_dev;
4265 int retval = -ENOMEM;
4266
4267 pm_runtime_get_sync(&pdev->dev);
4268
4269 /*
4270 * Rx and Tx desscriptors needs 256 bytes alignment.
4271 * dma_alloc_coherent provides more.
4272 */
4273 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4274 &tp->TxPhyAddr, GFP_KERNEL);
4275 if (!tp->TxDescArray)
4276 goto err_pm_runtime_put;
4277
4278 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4279 &tp->RxPhyAddr, GFP_KERNEL);
4280 if (!tp->RxDescArray)
4281 goto err_free_tx_0;
4282
4283 retval = rtl8169_init_ring(dev);
4284 if (retval < 0)
4285 goto err_free_rx_1;
4286
4287 INIT_DELAYED_WORK(&tp->task, NULL);
4288
4289 smp_mb();
4290
4291 rtl_request_firmware(tp);
4292
4293 retval = request_irq(dev->irq, rtl8169_interrupt,
4294 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4295 dev->name, dev);
4296 if (retval < 0)
4297 goto err_release_fw_2;
4298
4299 napi_enable(&tp->napi);
4300
4301 rtl8169_init_phy(dev, tp);
4302
4303 rtl8169_set_features(dev, dev->features);
4304
4305 rtl_pll_power_up(tp);
4306
4307 rtl_hw_start(dev);
4308
4309 tp->saved_wolopts = 0;
4310 pm_runtime_put_noidle(&pdev->dev);
4311
4312 rtl8169_check_link_status(dev, tp, ioaddr);
4313 out:
4314 return retval;
4315
4316 err_release_fw_2:
4317 rtl_release_firmware(tp);
4318 rtl8169_rx_clear(tp);
4319 err_free_rx_1:
4320 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4321 tp->RxPhyAddr);
4322 tp->RxDescArray = NULL;
4323 err_free_tx_0:
4324 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4325 tp->TxPhyAddr);
4326 tp->TxDescArray = NULL;
4327 err_pm_runtime_put:
4328 pm_runtime_put_noidle(&pdev->dev);
4329 goto out;
4330 }
4331
4332 static void rtl_rx_close(struct rtl8169_private *tp)
4333 {
4334 void __iomem *ioaddr = tp->mmio_addr;
4335
4336 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4337 }
4338
4339 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4340 {
4341 void __iomem *ioaddr = tp->mmio_addr;
4342
4343 /* Disable interrupts */
4344 rtl8169_irq_mask_and_ack(tp);
4345
4346 rtl_rx_close(tp);
4347
4348 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4349 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4350 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4351 while (RTL_R8(TxPoll) & NPQ)
4352 udelay(20);
4353 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4354 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4355 tp->mac_version == RTL_GIGA_MAC_VER_36) {
4356 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4357 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4358 udelay(100);
4359 } else {
4360 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4361 udelay(100);
4362 }
4363
4364 rtl_hw_reset(tp);
4365 }
4366
4367 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4368 {
4369 void __iomem *ioaddr = tp->mmio_addr;
4370
4371 /* Set DMA burst size and Interframe Gap Time */
4372 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4373 (InterFrameGap << TxInterFrameGapShift));
4374 }
4375
4376 static void rtl_hw_start(struct net_device *dev)
4377 {
4378 struct rtl8169_private *tp = netdev_priv(dev);
4379
4380 tp->hw_start(dev);
4381
4382 netif_start_queue(dev);
4383 }
4384
4385 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4386 void __iomem *ioaddr)
4387 {
4388 /*
4389 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4390 * register to be written before TxDescAddrLow to work.
4391 * Switching from MMIO to I/O access fixes the issue as well.
4392 */
4393 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4394 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4395 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4396 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4397 }
4398
4399 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4400 {
4401 u16 cmd;
4402
4403 cmd = RTL_R16(CPlusCmd);
4404 RTL_W16(CPlusCmd, cmd);
4405 return cmd;
4406 }
4407
4408 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4409 {
4410 /* Low hurts. Let's disable the filtering. */
4411 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4412 }
4413
4414 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4415 {
4416 static const struct rtl_cfg2_info {
4417 u32 mac_version;
4418 u32 clk;
4419 u32 val;
4420 } cfg2_info [] = {
4421 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4422 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4423 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4424 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4425 };
4426 const struct rtl_cfg2_info *p = cfg2_info;
4427 unsigned int i;
4428 u32 clk;
4429
4430 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4431 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4432 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4433 RTL_W32(0x7c, p->val);
4434 break;
4435 }
4436 }
4437 }
4438
4439 static void rtl_hw_start_8169(struct net_device *dev)
4440 {
4441 struct rtl8169_private *tp = netdev_priv(dev);
4442 void __iomem *ioaddr = tp->mmio_addr;
4443 struct pci_dev *pdev = tp->pci_dev;
4444
4445 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4446 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4447 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4448 }
4449
4450 RTL_W8(Cfg9346, Cfg9346_Unlock);
4451 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4452 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4453 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4454 tp->mac_version == RTL_GIGA_MAC_VER_04)
4455 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4456
4457 rtl_init_rxcfg(tp);
4458
4459 RTL_W8(EarlyTxThres, NoEarlyTx);
4460
4461 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4462
4463 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4464 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4465 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4466 tp->mac_version == RTL_GIGA_MAC_VER_04)
4467 rtl_set_rx_tx_config_registers(tp);
4468
4469 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4470
4471 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4472 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4473 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4474 "Bit-3 and bit-14 MUST be 1\n");
4475 tp->cp_cmd |= (1 << 14);
4476 }
4477
4478 RTL_W16(CPlusCmd, tp->cp_cmd);
4479
4480 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4481
4482 /*
4483 * Undocumented corner. Supposedly:
4484 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4485 */
4486 RTL_W16(IntrMitigate, 0x0000);
4487
4488 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4489
4490 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4491 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4492 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4493 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4494 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4495 rtl_set_rx_tx_config_registers(tp);
4496 }
4497
4498 RTL_W8(Cfg9346, Cfg9346_Lock);
4499
4500 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4501 RTL_R8(IntrMask);
4502
4503 RTL_W32(RxMissed, 0);
4504
4505 rtl_set_rx_mode(dev);
4506
4507 /* no early-rx interrupts */
4508 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4509
4510 /* Enable all known interrupts by setting the interrupt mask. */
4511 RTL_W16(IntrMask, tp->intr_event);
4512 }
4513
4514 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4515 {
4516 u32 csi;
4517
4518 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4519 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4520 }
4521
4522 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4523 {
4524 rtl_csi_access_enable(ioaddr, 0x17000000);
4525 }
4526
4527 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4528 {
4529 rtl_csi_access_enable(ioaddr, 0x27000000);
4530 }
4531
4532 struct ephy_info {
4533 unsigned int offset;
4534 u16 mask;
4535 u16 bits;
4536 };
4537
4538 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4539 {
4540 u16 w;
4541
4542 while (len-- > 0) {
4543 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4544 rtl_ephy_write(ioaddr, e->offset, w);
4545 e++;
4546 }
4547 }
4548
4549 static void rtl_disable_clock_request(struct pci_dev *pdev)
4550 {
4551 int cap = pci_pcie_cap(pdev);
4552
4553 if (cap) {
4554 u16 ctl;
4555
4556 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4557 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4558 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4559 }
4560 }
4561
4562 static void rtl_enable_clock_request(struct pci_dev *pdev)
4563 {
4564 int cap = pci_pcie_cap(pdev);
4565
4566 if (cap) {
4567 u16 ctl;
4568
4569 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4570 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4571 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4572 }
4573 }
4574
4575 #define R8168_CPCMD_QUIRK_MASK (\
4576 EnableBist | \
4577 Mac_dbgo_oe | \
4578 Force_half_dup | \
4579 Force_rxflow_en | \
4580 Force_txflow_en | \
4581 Cxpl_dbg_sel | \
4582 ASF | \
4583 PktCntrDisable | \
4584 Mac_dbgo_sel)
4585
4586 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4587 {
4588 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4589
4590 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4591
4592 rtl_tx_performance_tweak(pdev,
4593 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4594 }
4595
4596 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4597 {
4598 rtl_hw_start_8168bb(ioaddr, pdev);
4599
4600 RTL_W8(MaxTxPacketSize, TxPacketMax);
4601
4602 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4603 }
4604
4605 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4606 {
4607 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4608
4609 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4610
4611 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4612
4613 rtl_disable_clock_request(pdev);
4614
4615 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4616 }
4617
4618 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4619 {
4620 static const struct ephy_info e_info_8168cp[] = {
4621 { 0x01, 0, 0x0001 },
4622 { 0x02, 0x0800, 0x1000 },
4623 { 0x03, 0, 0x0042 },
4624 { 0x06, 0x0080, 0x0000 },
4625 { 0x07, 0, 0x2000 }
4626 };
4627
4628 rtl_csi_access_enable_2(ioaddr);
4629
4630 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4631
4632 __rtl_hw_start_8168cp(ioaddr, pdev);
4633 }
4634
4635 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4636 {
4637 rtl_csi_access_enable_2(ioaddr);
4638
4639 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4640
4641 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4642
4643 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4644 }
4645
4646 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4647 {
4648 rtl_csi_access_enable_2(ioaddr);
4649
4650 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4651
4652 /* Magic. */
4653 RTL_W8(DBG_REG, 0x20);
4654
4655 RTL_W8(MaxTxPacketSize, TxPacketMax);
4656
4657 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4658
4659 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4660 }
4661
4662 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4663 {
4664 static const struct ephy_info e_info_8168c_1[] = {
4665 { 0x02, 0x0800, 0x1000 },
4666 { 0x03, 0, 0x0002 },
4667 { 0x06, 0x0080, 0x0000 }
4668 };
4669
4670 rtl_csi_access_enable_2(ioaddr);
4671
4672 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4673
4674 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4675
4676 __rtl_hw_start_8168cp(ioaddr, pdev);
4677 }
4678
4679 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4680 {
4681 static const struct ephy_info e_info_8168c_2[] = {
4682 { 0x01, 0, 0x0001 },
4683 { 0x03, 0x0400, 0x0220 }
4684 };
4685
4686 rtl_csi_access_enable_2(ioaddr);
4687
4688 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4689
4690 __rtl_hw_start_8168cp(ioaddr, pdev);
4691 }
4692
4693 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4694 {
4695 rtl_hw_start_8168c_2(ioaddr, pdev);
4696 }
4697
4698 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4699 {
4700 rtl_csi_access_enable_2(ioaddr);
4701
4702 __rtl_hw_start_8168cp(ioaddr, pdev);
4703 }
4704
4705 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4706 {
4707 rtl_csi_access_enable_2(ioaddr);
4708
4709 rtl_disable_clock_request(pdev);
4710
4711 RTL_W8(MaxTxPacketSize, TxPacketMax);
4712
4713 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4714
4715 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4716 }
4717
4718 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4719 {
4720 rtl_csi_access_enable_1(ioaddr);
4721
4722 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4723
4724 RTL_W8(MaxTxPacketSize, TxPacketMax);
4725
4726 rtl_disable_clock_request(pdev);
4727 }
4728
4729 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4730 {
4731 static const struct ephy_info e_info_8168d_4[] = {
4732 { 0x0b, ~0, 0x48 },
4733 { 0x19, 0x20, 0x50 },
4734 { 0x0c, ~0, 0x20 }
4735 };
4736 int i;
4737
4738 rtl_csi_access_enable_1(ioaddr);
4739
4740 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4741
4742 RTL_W8(MaxTxPacketSize, TxPacketMax);
4743
4744 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4745 const struct ephy_info *e = e_info_8168d_4 + i;
4746 u16 w;
4747
4748 w = rtl_ephy_read(ioaddr, e->offset);
4749 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4750 }
4751
4752 rtl_enable_clock_request(pdev);
4753 }
4754
4755 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4756 {
4757 static const struct ephy_info e_info_8168e_1[] = {
4758 { 0x00, 0x0200, 0x0100 },
4759 { 0x00, 0x0000, 0x0004 },
4760 { 0x06, 0x0002, 0x0001 },
4761 { 0x06, 0x0000, 0x0030 },
4762 { 0x07, 0x0000, 0x2000 },
4763 { 0x00, 0x0000, 0x0020 },
4764 { 0x03, 0x5800, 0x2000 },
4765 { 0x03, 0x0000, 0x0001 },
4766 { 0x01, 0x0800, 0x1000 },
4767 { 0x07, 0x0000, 0x4000 },
4768 { 0x1e, 0x0000, 0x2000 },
4769 { 0x19, 0xffff, 0xfe6c },
4770 { 0x0a, 0x0000, 0x0040 }
4771 };
4772
4773 rtl_csi_access_enable_2(ioaddr);
4774
4775 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4776
4777 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4778
4779 RTL_W8(MaxTxPacketSize, TxPacketMax);
4780
4781 rtl_disable_clock_request(pdev);
4782
4783 /* Reset tx FIFO pointer */
4784 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4785 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4786
4787 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4788 }
4789
4790 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4791 {
4792 static const struct ephy_info e_info_8168e_2[] = {
4793 { 0x09, 0x0000, 0x0080 },
4794 { 0x19, 0x0000, 0x0224 }
4795 };
4796
4797 rtl_csi_access_enable_1(ioaddr);
4798
4799 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4800
4801 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4802
4803 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4804 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4805 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4806 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4807 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4808 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4809 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4810 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4811 ERIAR_EXGMAC);
4812
4813 RTL_W8(MaxTxPacketSize, EarlySize);
4814
4815 rtl_disable_clock_request(pdev);
4816
4817 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4818 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4819
4820 /* Adjust EEE LED frequency */
4821 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4822
4823 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4824 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4825 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4826 }
4827
4828 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4829 {
4830 static const struct ephy_info e_info_8168f_1[] = {
4831 { 0x06, 0x00c0, 0x0020 },
4832 { 0x08, 0x0001, 0x0002 },
4833 { 0x09, 0x0000, 0x0080 },
4834 { 0x19, 0x0000, 0x0224 }
4835 };
4836
4837 rtl_csi_access_enable_1(ioaddr);
4838
4839 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4840
4841 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4842
4843 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4844 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4845 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4846 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4847 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4848 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4849 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4850 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4851 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4852 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4853 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4854 ERIAR_EXGMAC);
4855
4856 RTL_W8(MaxTxPacketSize, EarlySize);
4857
4858 rtl_disable_clock_request(pdev);
4859
4860 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4861 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4862
4863 /* Adjust EEE LED frequency */
4864 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4865
4866 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4867 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4868 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4869 }
4870
4871 static void rtl_hw_start_8168(struct net_device *dev)
4872 {
4873 struct rtl8169_private *tp = netdev_priv(dev);
4874 void __iomem *ioaddr = tp->mmio_addr;
4875 struct pci_dev *pdev = tp->pci_dev;
4876
4877 RTL_W8(Cfg9346, Cfg9346_Unlock);
4878
4879 RTL_W8(MaxTxPacketSize, TxPacketMax);
4880
4881 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4882
4883 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4884
4885 RTL_W16(CPlusCmd, tp->cp_cmd);
4886
4887 RTL_W16(IntrMitigate, 0x5151);
4888
4889 /* Work around for RxFIFO overflow. */
4890 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4891 tp->intr_event |= RxFIFOOver | PCSTimeout;
4892 tp->intr_event &= ~RxOverflow;
4893 }
4894
4895 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4896
4897 rtl_set_rx_mode(dev);
4898
4899 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4900 (InterFrameGap << TxInterFrameGapShift));
4901
4902 RTL_R8(IntrMask);
4903
4904 switch (tp->mac_version) {
4905 case RTL_GIGA_MAC_VER_11:
4906 rtl_hw_start_8168bb(ioaddr, pdev);
4907 break;
4908
4909 case RTL_GIGA_MAC_VER_12:
4910 case RTL_GIGA_MAC_VER_17:
4911 rtl_hw_start_8168bef(ioaddr, pdev);
4912 break;
4913
4914 case RTL_GIGA_MAC_VER_18:
4915 rtl_hw_start_8168cp_1(ioaddr, pdev);
4916 break;
4917
4918 case RTL_GIGA_MAC_VER_19:
4919 rtl_hw_start_8168c_1(ioaddr, pdev);
4920 break;
4921
4922 case RTL_GIGA_MAC_VER_20:
4923 rtl_hw_start_8168c_2(ioaddr, pdev);
4924 break;
4925
4926 case RTL_GIGA_MAC_VER_21:
4927 rtl_hw_start_8168c_3(ioaddr, pdev);
4928 break;
4929
4930 case RTL_GIGA_MAC_VER_22:
4931 rtl_hw_start_8168c_4(ioaddr, pdev);
4932 break;
4933
4934 case RTL_GIGA_MAC_VER_23:
4935 rtl_hw_start_8168cp_2(ioaddr, pdev);
4936 break;
4937
4938 case RTL_GIGA_MAC_VER_24:
4939 rtl_hw_start_8168cp_3(ioaddr, pdev);
4940 break;
4941
4942 case RTL_GIGA_MAC_VER_25:
4943 case RTL_GIGA_MAC_VER_26:
4944 case RTL_GIGA_MAC_VER_27:
4945 rtl_hw_start_8168d(ioaddr, pdev);
4946 break;
4947
4948 case RTL_GIGA_MAC_VER_28:
4949 rtl_hw_start_8168d_4(ioaddr, pdev);
4950 break;
4951
4952 case RTL_GIGA_MAC_VER_31:
4953 rtl_hw_start_8168dp(ioaddr, pdev);
4954 break;
4955
4956 case RTL_GIGA_MAC_VER_32:
4957 case RTL_GIGA_MAC_VER_33:
4958 rtl_hw_start_8168e_1(ioaddr, pdev);
4959 break;
4960 case RTL_GIGA_MAC_VER_34:
4961 rtl_hw_start_8168e_2(ioaddr, pdev);
4962 break;
4963
4964 case RTL_GIGA_MAC_VER_35:
4965 case RTL_GIGA_MAC_VER_36:
4966 rtl_hw_start_8168f_1(ioaddr, pdev);
4967 break;
4968
4969 default:
4970 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4971 dev->name, tp->mac_version);
4972 break;
4973 }
4974
4975 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4976
4977 RTL_W8(Cfg9346, Cfg9346_Lock);
4978
4979 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4980
4981 RTL_W16(IntrMask, tp->intr_event);
4982 }
4983
4984 #define R810X_CPCMD_QUIRK_MASK (\
4985 EnableBist | \
4986 Mac_dbgo_oe | \
4987 Force_half_dup | \
4988 Force_rxflow_en | \
4989 Force_txflow_en | \
4990 Cxpl_dbg_sel | \
4991 ASF | \
4992 PktCntrDisable | \
4993 Mac_dbgo_sel)
4994
4995 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4996 {
4997 static const struct ephy_info e_info_8102e_1[] = {
4998 { 0x01, 0, 0x6e65 },
4999 { 0x02, 0, 0x091f },
5000 { 0x03, 0, 0xc2f9 },
5001 { 0x06, 0, 0xafb5 },
5002 { 0x07, 0, 0x0e00 },
5003 { 0x19, 0, 0xec80 },
5004 { 0x01, 0, 0x2e65 },
5005 { 0x01, 0, 0x6e65 }
5006 };
5007 u8 cfg1;
5008
5009 rtl_csi_access_enable_2(ioaddr);
5010
5011 RTL_W8(DBG_REG, FIX_NAK_1);
5012
5013 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5014
5015 RTL_W8(Config1,
5016 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5017 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5018
5019 cfg1 = RTL_R8(Config1);
5020 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5021 RTL_W8(Config1, cfg1 & ~LEDS0);
5022
5023 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5024 }
5025
5026 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5027 {
5028 rtl_csi_access_enable_2(ioaddr);
5029
5030 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5031
5032 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5033 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5034 }
5035
5036 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5037 {
5038 rtl_hw_start_8102e_2(ioaddr, pdev);
5039
5040 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5041 }
5042
5043 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5044 {
5045 static const struct ephy_info e_info_8105e_1[] = {
5046 { 0x07, 0, 0x4000 },
5047 { 0x19, 0, 0x0200 },
5048 { 0x19, 0, 0x0020 },
5049 { 0x1e, 0, 0x2000 },
5050 { 0x03, 0, 0x0001 },
5051 { 0x19, 0, 0x0100 },
5052 { 0x19, 0, 0x0004 },
5053 { 0x0a, 0, 0x0020 }
5054 };
5055
5056 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5057 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5058
5059 /* Disable Early Tally Counter */
5060 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5061
5062 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5063 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5064
5065 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5066 }
5067
5068 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5069 {
5070 rtl_hw_start_8105e_1(ioaddr, pdev);
5071 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5072 }
5073
5074 static void rtl_hw_start_8101(struct net_device *dev)
5075 {
5076 struct rtl8169_private *tp = netdev_priv(dev);
5077 void __iomem *ioaddr = tp->mmio_addr;
5078 struct pci_dev *pdev = tp->pci_dev;
5079
5080 if (tp->mac_version >= RTL_GIGA_MAC_VER_30) {
5081 tp->intr_event &= ~RxFIFOOver;
5082 tp->napi_event &= ~RxFIFOOver;
5083 }
5084
5085 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5086 tp->mac_version == RTL_GIGA_MAC_VER_16) {
5087 int cap = pci_pcie_cap(pdev);
5088
5089 if (cap) {
5090 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5091 PCI_EXP_DEVCTL_NOSNOOP_EN);
5092 }
5093 }
5094
5095 RTL_W8(Cfg9346, Cfg9346_Unlock);
5096
5097 switch (tp->mac_version) {
5098 case RTL_GIGA_MAC_VER_07:
5099 rtl_hw_start_8102e_1(ioaddr, pdev);
5100 break;
5101
5102 case RTL_GIGA_MAC_VER_08:
5103 rtl_hw_start_8102e_3(ioaddr, pdev);
5104 break;
5105
5106 case RTL_GIGA_MAC_VER_09:
5107 rtl_hw_start_8102e_2(ioaddr, pdev);
5108 break;
5109
5110 case RTL_GIGA_MAC_VER_29:
5111 rtl_hw_start_8105e_1(ioaddr, pdev);
5112 break;
5113 case RTL_GIGA_MAC_VER_30:
5114 rtl_hw_start_8105e_2(ioaddr, pdev);
5115 break;
5116 }
5117
5118 RTL_W8(Cfg9346, Cfg9346_Lock);
5119
5120 RTL_W8(MaxTxPacketSize, TxPacketMax);
5121
5122 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5123
5124 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5125 RTL_W16(CPlusCmd, tp->cp_cmd);
5126
5127 RTL_W16(IntrMitigate, 0x0000);
5128
5129 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5130
5131 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5132 rtl_set_rx_tx_config_registers(tp);
5133
5134 RTL_R8(IntrMask);
5135
5136 rtl_set_rx_mode(dev);
5137
5138 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5139
5140 RTL_W16(IntrMask, tp->intr_event);
5141 }
5142
5143 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5144 {
5145 struct rtl8169_private *tp = netdev_priv(dev);
5146
5147 if (new_mtu < ETH_ZLEN ||
5148 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5149 return -EINVAL;
5150
5151 if (new_mtu > ETH_DATA_LEN)
5152 rtl_hw_jumbo_enable(tp);
5153 else
5154 rtl_hw_jumbo_disable(tp);
5155
5156 dev->mtu = new_mtu;
5157 netdev_update_features(dev);
5158
5159 return 0;
5160 }
5161
5162 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5163 {
5164 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5165 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5166 }
5167
5168 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5169 void **data_buff, struct RxDesc *desc)
5170 {
5171 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5172 DMA_FROM_DEVICE);
5173
5174 kfree(*data_buff);
5175 *data_buff = NULL;
5176 rtl8169_make_unusable_by_asic(desc);
5177 }
5178
5179 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5180 {
5181 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5182
5183 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5184 }
5185
5186 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5187 u32 rx_buf_sz)
5188 {
5189 desc->addr = cpu_to_le64(mapping);
5190 wmb();
5191 rtl8169_mark_to_asic(desc, rx_buf_sz);
5192 }
5193
5194 static inline void *rtl8169_align(void *data)
5195 {
5196 return (void *)ALIGN((long)data, 16);
5197 }
5198
5199 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5200 struct RxDesc *desc)
5201 {
5202 void *data;
5203 dma_addr_t mapping;
5204 struct device *d = &tp->pci_dev->dev;
5205 struct net_device *dev = tp->dev;
5206 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5207
5208 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5209 if (!data)
5210 return NULL;
5211
5212 if (rtl8169_align(data) != data) {
5213 kfree(data);
5214 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5215 if (!data)
5216 return NULL;
5217 }
5218
5219 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5220 DMA_FROM_DEVICE);
5221 if (unlikely(dma_mapping_error(d, mapping))) {
5222 if (net_ratelimit())
5223 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5224 goto err_out;
5225 }
5226
5227 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5228 return data;
5229
5230 err_out:
5231 kfree(data);
5232 return NULL;
5233 }
5234
5235 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5236 {
5237 unsigned int i;
5238
5239 for (i = 0; i < NUM_RX_DESC; i++) {
5240 if (tp->Rx_databuff[i]) {
5241 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5242 tp->RxDescArray + i);
5243 }
5244 }
5245 }
5246
5247 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5248 {
5249 desc->opts1 |= cpu_to_le32(RingEnd);
5250 }
5251
5252 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5253 {
5254 unsigned int i;
5255
5256 for (i = 0; i < NUM_RX_DESC; i++) {
5257 void *data;
5258
5259 if (tp->Rx_databuff[i])
5260 continue;
5261
5262 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5263 if (!data) {
5264 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5265 goto err_out;
5266 }
5267 tp->Rx_databuff[i] = data;
5268 }
5269
5270 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5271 return 0;
5272
5273 err_out:
5274 rtl8169_rx_clear(tp);
5275 return -ENOMEM;
5276 }
5277
5278 static int rtl8169_init_ring(struct net_device *dev)
5279 {
5280 struct rtl8169_private *tp = netdev_priv(dev);
5281
5282 rtl8169_init_ring_indexes(tp);
5283
5284 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5285 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5286
5287 return rtl8169_rx_fill(tp);
5288 }
5289
5290 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5291 struct TxDesc *desc)
5292 {
5293 unsigned int len = tx_skb->len;
5294
5295 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5296
5297 desc->opts1 = 0x00;
5298 desc->opts2 = 0x00;
5299 desc->addr = 0x00;
5300 tx_skb->len = 0;
5301 }
5302
5303 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5304 unsigned int n)
5305 {
5306 unsigned int i;
5307
5308 for (i = 0; i < n; i++) {
5309 unsigned int entry = (start + i) % NUM_TX_DESC;
5310 struct ring_info *tx_skb = tp->tx_skb + entry;
5311 unsigned int len = tx_skb->len;
5312
5313 if (len) {
5314 struct sk_buff *skb = tx_skb->skb;
5315
5316 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5317 tp->TxDescArray + entry);
5318 if (skb) {
5319 tp->dev->stats.tx_dropped++;
5320 dev_kfree_skb(skb);
5321 tx_skb->skb = NULL;
5322 }
5323 }
5324 }
5325 }
5326
5327 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5328 {
5329 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5330 tp->cur_tx = tp->dirty_tx = 0;
5331 }
5332
5333 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
5334 {
5335 struct rtl8169_private *tp = netdev_priv(dev);
5336
5337 PREPARE_DELAYED_WORK(&tp->task, task);
5338 schedule_delayed_work(&tp->task, 4);
5339 }
5340
5341 static void rtl8169_wait_for_quiescence(struct net_device *dev)
5342 {
5343 struct rtl8169_private *tp = netdev_priv(dev);
5344 void __iomem *ioaddr = tp->mmio_addr;
5345
5346 synchronize_irq(dev->irq);
5347
5348 /* Wait for any pending NAPI task to complete */
5349 napi_disable(&tp->napi);
5350
5351 rtl8169_irq_mask_and_ack(tp);
5352
5353 tp->intr_mask = 0xffff;
5354 RTL_W16(IntrMask, tp->intr_event);
5355 napi_enable(&tp->napi);
5356 }
5357
5358 static void rtl8169_reinit_task(struct work_struct *work)
5359 {
5360 struct rtl8169_private *tp =
5361 container_of(work, struct rtl8169_private, task.work);
5362 struct net_device *dev = tp->dev;
5363 int ret;
5364
5365 rtnl_lock();
5366
5367 if (!netif_running(dev))
5368 goto out_unlock;
5369
5370 rtl8169_wait_for_quiescence(dev);
5371 rtl8169_close(dev);
5372
5373 ret = rtl8169_open(dev);
5374 if (unlikely(ret < 0)) {
5375 if (net_ratelimit())
5376 netif_err(tp, drv, dev,
5377 "reinit failure (status = %d). Rescheduling\n",
5378 ret);
5379 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5380 }
5381
5382 out_unlock:
5383 rtnl_unlock();
5384 }
5385
5386 static void rtl8169_reset_task(struct work_struct *work)
5387 {
5388 struct rtl8169_private *tp =
5389 container_of(work, struct rtl8169_private, task.work);
5390 struct net_device *dev = tp->dev;
5391 int i;
5392
5393 rtnl_lock();
5394
5395 if (!netif_running(dev))
5396 goto out_unlock;
5397
5398 rtl8169_hw_reset(tp);
5399
5400 rtl8169_wait_for_quiescence(dev);
5401
5402 for (i = 0; i < NUM_RX_DESC; i++)
5403 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5404
5405 rtl8169_tx_clear(tp);
5406 rtl8169_init_ring_indexes(tp);
5407
5408 rtl_hw_start(dev);
5409 netif_wake_queue(dev);
5410 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5411
5412 out_unlock:
5413 rtnl_unlock();
5414 }
5415
5416 static void rtl8169_tx_timeout(struct net_device *dev)
5417 {
5418 rtl8169_schedule_work(dev, rtl8169_reset_task);
5419 }
5420
5421 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5422 u32 *opts)
5423 {
5424 struct skb_shared_info *info = skb_shinfo(skb);
5425 unsigned int cur_frag, entry;
5426 struct TxDesc * uninitialized_var(txd);
5427 struct device *d = &tp->pci_dev->dev;
5428
5429 entry = tp->cur_tx;
5430 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5431 const skb_frag_t *frag = info->frags + cur_frag;
5432 dma_addr_t mapping;
5433 u32 status, len;
5434 void *addr;
5435
5436 entry = (entry + 1) % NUM_TX_DESC;
5437
5438 txd = tp->TxDescArray + entry;
5439 len = skb_frag_size(frag);
5440 addr = skb_frag_address(frag);
5441 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5442 if (unlikely(dma_mapping_error(d, mapping))) {
5443 if (net_ratelimit())
5444 netif_err(tp, drv, tp->dev,
5445 "Failed to map TX fragments DMA!\n");
5446 goto err_out;
5447 }
5448
5449 /* Anti gcc 2.95.3 bugware (sic) */
5450 status = opts[0] | len |
5451 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5452
5453 txd->opts1 = cpu_to_le32(status);
5454 txd->opts2 = cpu_to_le32(opts[1]);
5455 txd->addr = cpu_to_le64(mapping);
5456
5457 tp->tx_skb[entry].len = len;
5458 }
5459
5460 if (cur_frag) {
5461 tp->tx_skb[entry].skb = skb;
5462 txd->opts1 |= cpu_to_le32(LastFrag);
5463 }
5464
5465 return cur_frag;
5466
5467 err_out:
5468 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5469 return -EIO;
5470 }
5471
5472 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5473 struct sk_buff *skb, u32 *opts)
5474 {
5475 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5476 u32 mss = skb_shinfo(skb)->gso_size;
5477 int offset = info->opts_offset;
5478
5479 if (mss) {
5480 opts[0] |= TD_LSO;
5481 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5482 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5483 const struct iphdr *ip = ip_hdr(skb);
5484
5485 if (ip->protocol == IPPROTO_TCP)
5486 opts[offset] |= info->checksum.tcp;
5487 else if (ip->protocol == IPPROTO_UDP)
5488 opts[offset] |= info->checksum.udp;
5489 else
5490 WARN_ON_ONCE(1);
5491 }
5492 }
5493
5494 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5495 struct net_device *dev)
5496 {
5497 struct rtl8169_private *tp = netdev_priv(dev);
5498 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5499 struct TxDesc *txd = tp->TxDescArray + entry;
5500 void __iomem *ioaddr = tp->mmio_addr;
5501 struct device *d = &tp->pci_dev->dev;
5502 dma_addr_t mapping;
5503 u32 status, len;
5504 u32 opts[2];
5505 int frags;
5506
5507 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5508 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5509 goto err_stop_0;
5510 }
5511
5512 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5513 goto err_stop_0;
5514
5515 len = skb_headlen(skb);
5516 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5517 if (unlikely(dma_mapping_error(d, mapping))) {
5518 if (net_ratelimit())
5519 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5520 goto err_dma_0;
5521 }
5522
5523 tp->tx_skb[entry].len = len;
5524 txd->addr = cpu_to_le64(mapping);
5525
5526 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5527 opts[0] = DescOwn;
5528
5529 rtl8169_tso_csum(tp, skb, opts);
5530
5531 frags = rtl8169_xmit_frags(tp, skb, opts);
5532 if (frags < 0)
5533 goto err_dma_1;
5534 else if (frags)
5535 opts[0] |= FirstFrag;
5536 else {
5537 opts[0] |= FirstFrag | LastFrag;
5538 tp->tx_skb[entry].skb = skb;
5539 }
5540
5541 txd->opts2 = cpu_to_le32(opts[1]);
5542
5543 wmb();
5544
5545 /* Anti gcc 2.95.3 bugware (sic) */
5546 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5547 txd->opts1 = cpu_to_le32(status);
5548
5549 tp->cur_tx += frags + 1;
5550
5551 wmb();
5552
5553 RTL_W8(TxPoll, NPQ);
5554
5555 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5556 netif_stop_queue(dev);
5557 smp_rmb();
5558 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5559 netif_wake_queue(dev);
5560 }
5561
5562 return NETDEV_TX_OK;
5563
5564 err_dma_1:
5565 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5566 err_dma_0:
5567 dev_kfree_skb(skb);
5568 dev->stats.tx_dropped++;
5569 return NETDEV_TX_OK;
5570
5571 err_stop_0:
5572 netif_stop_queue(dev);
5573 dev->stats.tx_dropped++;
5574 return NETDEV_TX_BUSY;
5575 }
5576
5577 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5578 {
5579 struct rtl8169_private *tp = netdev_priv(dev);
5580 struct pci_dev *pdev = tp->pci_dev;
5581 u16 pci_status, pci_cmd;
5582
5583 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5584 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5585
5586 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5587 pci_cmd, pci_status);
5588
5589 /*
5590 * The recovery sequence below admits a very elaborated explanation:
5591 * - it seems to work;
5592 * - I did not see what else could be done;
5593 * - it makes iop3xx happy.
5594 *
5595 * Feel free to adjust to your needs.
5596 */
5597 if (pdev->broken_parity_status)
5598 pci_cmd &= ~PCI_COMMAND_PARITY;
5599 else
5600 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5601
5602 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5603
5604 pci_write_config_word(pdev, PCI_STATUS,
5605 pci_status & (PCI_STATUS_DETECTED_PARITY |
5606 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5607 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5608
5609 /* The infamous DAC f*ckup only happens at boot time */
5610 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5611 void __iomem *ioaddr = tp->mmio_addr;
5612
5613 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5614 tp->cp_cmd &= ~PCIDAC;
5615 RTL_W16(CPlusCmd, tp->cp_cmd);
5616 dev->features &= ~NETIF_F_HIGHDMA;
5617 }
5618
5619 rtl8169_hw_reset(tp);
5620
5621 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5622 }
5623
5624 static void rtl8169_tx_interrupt(struct net_device *dev,
5625 struct rtl8169_private *tp,
5626 void __iomem *ioaddr)
5627 {
5628 unsigned int dirty_tx, tx_left;
5629
5630 dirty_tx = tp->dirty_tx;
5631 smp_rmb();
5632 tx_left = tp->cur_tx - dirty_tx;
5633
5634 while (tx_left > 0) {
5635 unsigned int entry = dirty_tx % NUM_TX_DESC;
5636 struct ring_info *tx_skb = tp->tx_skb + entry;
5637 u32 status;
5638
5639 rmb();
5640 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5641 if (status & DescOwn)
5642 break;
5643
5644 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5645 tp->TxDescArray + entry);
5646 if (status & LastFrag) {
5647 dev->stats.tx_packets++;
5648 dev->stats.tx_bytes += tx_skb->skb->len;
5649 dev_kfree_skb(tx_skb->skb);
5650 tx_skb->skb = NULL;
5651 }
5652 dirty_tx++;
5653 tx_left--;
5654 }
5655
5656 if (tp->dirty_tx != dirty_tx) {
5657 tp->dirty_tx = dirty_tx;
5658 smp_wmb();
5659 if (netif_queue_stopped(dev) &&
5660 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5661 netif_wake_queue(dev);
5662 }
5663 /*
5664 * 8168 hack: TxPoll requests are lost when the Tx packets are
5665 * too close. Let's kick an extra TxPoll request when a burst
5666 * of start_xmit activity is detected (if it is not detected,
5667 * it is slow enough). -- FR
5668 */
5669 smp_rmb();
5670 if (tp->cur_tx != dirty_tx)
5671 RTL_W8(TxPoll, NPQ);
5672 }
5673 }
5674
5675 static inline int rtl8169_fragmented_frame(u32 status)
5676 {
5677 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5678 }
5679
5680 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5681 {
5682 u32 status = opts1 & RxProtoMask;
5683
5684 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5685 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5686 skb->ip_summed = CHECKSUM_UNNECESSARY;
5687 else
5688 skb_checksum_none_assert(skb);
5689 }
5690
5691 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5692 struct rtl8169_private *tp,
5693 int pkt_size,
5694 dma_addr_t addr)
5695 {
5696 struct sk_buff *skb;
5697 struct device *d = &tp->pci_dev->dev;
5698
5699 data = rtl8169_align(data);
5700 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5701 prefetch(data);
5702 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5703 if (skb)
5704 memcpy(skb->data, data, pkt_size);
5705 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5706
5707 return skb;
5708 }
5709
5710 static int rtl8169_rx_interrupt(struct net_device *dev,
5711 struct rtl8169_private *tp,
5712 void __iomem *ioaddr, u32 budget)
5713 {
5714 unsigned int cur_rx, rx_left;
5715 unsigned int count;
5716
5717 cur_rx = tp->cur_rx;
5718 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5719 rx_left = min(rx_left, budget);
5720
5721 for (; rx_left > 0; rx_left--, cur_rx++) {
5722 unsigned int entry = cur_rx % NUM_RX_DESC;
5723 struct RxDesc *desc = tp->RxDescArray + entry;
5724 u32 status;
5725
5726 rmb();
5727 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5728
5729 if (status & DescOwn)
5730 break;
5731 if (unlikely(status & RxRES)) {
5732 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5733 status);
5734 dev->stats.rx_errors++;
5735 if (status & (RxRWT | RxRUNT))
5736 dev->stats.rx_length_errors++;
5737 if (status & RxCRC)
5738 dev->stats.rx_crc_errors++;
5739 if (status & RxFOVF) {
5740 rtl8169_schedule_work(dev, rtl8169_reset_task);
5741 dev->stats.rx_fifo_errors++;
5742 }
5743 rtl8169_mark_to_asic(desc, rx_buf_sz);
5744 } else {
5745 struct sk_buff *skb;
5746 dma_addr_t addr = le64_to_cpu(desc->addr);
5747 int pkt_size = (status & 0x00003fff) - 4;
5748
5749 /*
5750 * The driver does not support incoming fragmented
5751 * frames. They are seen as a symptom of over-mtu
5752 * sized frames.
5753 */
5754 if (unlikely(rtl8169_fragmented_frame(status))) {
5755 dev->stats.rx_dropped++;
5756 dev->stats.rx_length_errors++;
5757 rtl8169_mark_to_asic(desc, rx_buf_sz);
5758 continue;
5759 }
5760
5761 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5762 tp, pkt_size, addr);
5763 rtl8169_mark_to_asic(desc, rx_buf_sz);
5764 if (!skb) {
5765 dev->stats.rx_dropped++;
5766 continue;
5767 }
5768
5769 rtl8169_rx_csum(skb, status);
5770 skb_put(skb, pkt_size);
5771 skb->protocol = eth_type_trans(skb, dev);
5772
5773 rtl8169_rx_vlan_tag(desc, skb);
5774
5775 napi_gro_receive(&tp->napi, skb);
5776
5777 dev->stats.rx_bytes += pkt_size;
5778 dev->stats.rx_packets++;
5779 }
5780
5781 /* Work around for AMD plateform. */
5782 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5783 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5784 desc->opts2 = 0;
5785 cur_rx++;
5786 }
5787 }
5788
5789 count = cur_rx - tp->cur_rx;
5790 tp->cur_rx = cur_rx;
5791
5792 tp->dirty_rx += count;
5793
5794 return count;
5795 }
5796
5797 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5798 {
5799 struct net_device *dev = dev_instance;
5800 struct rtl8169_private *tp = netdev_priv(dev);
5801 void __iomem *ioaddr = tp->mmio_addr;
5802 int handled = 0;
5803 int status;
5804
5805 /* loop handling interrupts until we have no new ones or
5806 * we hit a invalid/hotplug case.
5807 */
5808 status = RTL_R16(IntrStatus);
5809 while (status && status != 0xffff) {
5810 status &= tp->intr_event;
5811 if (!status)
5812 break;
5813
5814 handled = 1;
5815
5816 /* Handle all of the error cases first. These will reset
5817 * the chip, so just exit the loop.
5818 */
5819 if (unlikely(!netif_running(dev))) {
5820 rtl8169_hw_reset(tp);
5821 break;
5822 }
5823
5824 if (unlikely(status & RxFIFOOver)) {
5825 switch (tp->mac_version) {
5826 /* Work around for rx fifo overflow */
5827 case RTL_GIGA_MAC_VER_11:
5828 netif_stop_queue(dev);
5829 rtl8169_tx_timeout(dev);
5830 goto done;
5831 default:
5832 break;
5833 }
5834 }
5835
5836 if (unlikely(status & SYSErr)) {
5837 rtl8169_pcierr_interrupt(dev);
5838 break;
5839 }
5840
5841 if (status & LinkChg)
5842 __rtl8169_check_link_status(dev, tp, ioaddr, true);
5843
5844 /* We need to see the lastest version of tp->intr_mask to
5845 * avoid ignoring an MSI interrupt and having to wait for
5846 * another event which may never come.
5847 */
5848 smp_rmb();
5849 if (status & tp->intr_mask & tp->napi_event) {
5850 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5851 tp->intr_mask = ~tp->napi_event;
5852
5853 if (likely(napi_schedule_prep(&tp->napi)))
5854 __napi_schedule(&tp->napi);
5855 else
5856 netif_info(tp, intr, dev,
5857 "interrupt %04x in poll\n", status);
5858 }
5859
5860 /* We only get a new MSI interrupt when all active irq
5861 * sources on the chip have been acknowledged. So, ack
5862 * everything we've seen and check if new sources have become
5863 * active to avoid blocking all interrupts from the chip.
5864 */
5865 RTL_W16(IntrStatus,
5866 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5867 status = RTL_R16(IntrStatus);
5868 }
5869 done:
5870 return IRQ_RETVAL(handled);
5871 }
5872
5873 static int rtl8169_poll(struct napi_struct *napi, int budget)
5874 {
5875 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5876 struct net_device *dev = tp->dev;
5877 void __iomem *ioaddr = tp->mmio_addr;
5878 int work_done;
5879
5880 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5881 rtl8169_tx_interrupt(dev, tp, ioaddr);
5882
5883 if (work_done < budget) {
5884 napi_complete(napi);
5885
5886 /* We need for force the visibility of tp->intr_mask
5887 * for other CPUs, as we can loose an MSI interrupt
5888 * and potentially wait for a retransmit timeout if we don't.
5889 * The posted write to IntrMask is safe, as it will
5890 * eventually make it to the chip and we won't loose anything
5891 * until it does.
5892 */
5893 tp->intr_mask = 0xffff;
5894 wmb();
5895 RTL_W16(IntrMask, tp->intr_event);
5896 }
5897
5898 return work_done;
5899 }
5900
5901 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5902 {
5903 struct rtl8169_private *tp = netdev_priv(dev);
5904
5905 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5906 return;
5907
5908 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5909 RTL_W32(RxMissed, 0);
5910 }
5911
5912 static void rtl8169_down(struct net_device *dev)
5913 {
5914 struct rtl8169_private *tp = netdev_priv(dev);
5915 void __iomem *ioaddr = tp->mmio_addr;
5916
5917 del_timer_sync(&tp->timer);
5918
5919 netif_stop_queue(dev);
5920
5921 napi_disable(&tp->napi);
5922
5923 spin_lock_irq(&tp->lock);
5924
5925 rtl8169_hw_reset(tp);
5926 /*
5927 * At this point device interrupts can not be enabled in any function,
5928 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5929 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5930 */
5931 rtl8169_rx_missed(dev, ioaddr);
5932
5933 spin_unlock_irq(&tp->lock);
5934
5935 synchronize_irq(dev->irq);
5936
5937 /* Give a racing hard_start_xmit a few cycles to complete. */
5938 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5939
5940 rtl8169_tx_clear(tp);
5941
5942 rtl8169_rx_clear(tp);
5943
5944 rtl_pll_power_down(tp);
5945 }
5946
5947 static int rtl8169_close(struct net_device *dev)
5948 {
5949 struct rtl8169_private *tp = netdev_priv(dev);
5950 struct pci_dev *pdev = tp->pci_dev;
5951
5952 pm_runtime_get_sync(&pdev->dev);
5953
5954 /* Update counters before going down */
5955 rtl8169_update_counters(dev);
5956
5957 rtl8169_down(dev);
5958
5959 free_irq(dev->irq, dev);
5960
5961 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5962 tp->RxPhyAddr);
5963 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5964 tp->TxPhyAddr);
5965 tp->TxDescArray = NULL;
5966 tp->RxDescArray = NULL;
5967
5968 pm_runtime_put_sync(&pdev->dev);
5969
5970 return 0;
5971 }
5972
5973 static void rtl_set_rx_mode(struct net_device *dev)
5974 {
5975 struct rtl8169_private *tp = netdev_priv(dev);
5976 void __iomem *ioaddr = tp->mmio_addr;
5977 unsigned long flags;
5978 u32 mc_filter[2]; /* Multicast hash filter */
5979 int rx_mode;
5980 u32 tmp = 0;
5981
5982 if (dev->flags & IFF_PROMISC) {
5983 /* Unconditionally log net taps. */
5984 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5985 rx_mode =
5986 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5987 AcceptAllPhys;
5988 mc_filter[1] = mc_filter[0] = 0xffffffff;
5989 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5990 (dev->flags & IFF_ALLMULTI)) {
5991 /* Too many to filter perfectly -- accept all multicasts. */
5992 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5993 mc_filter[1] = mc_filter[0] = 0xffffffff;
5994 } else {
5995 struct netdev_hw_addr *ha;
5996
5997 rx_mode = AcceptBroadcast | AcceptMyPhys;
5998 mc_filter[1] = mc_filter[0] = 0;
5999 netdev_for_each_mc_addr(ha, dev) {
6000 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
6001 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6002 rx_mode |= AcceptMulticast;
6003 }
6004 }
6005
6006 spin_lock_irqsave(&tp->lock, flags);
6007
6008 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
6009
6010 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
6011 u32 data = mc_filter[0];
6012
6013 mc_filter[0] = swab32(mc_filter[1]);
6014 mc_filter[1] = swab32(data);
6015 }
6016
6017 RTL_W32(MAR0 + 4, mc_filter[1]);
6018 RTL_W32(MAR0 + 0, mc_filter[0]);
6019
6020 RTL_W32(RxConfig, tmp);
6021
6022 spin_unlock_irqrestore(&tp->lock, flags);
6023 }
6024
6025 /**
6026 * rtl8169_get_stats - Get rtl8169 read/write statistics
6027 * @dev: The Ethernet Device to get statistics for
6028 *
6029 * Get TX/RX statistics for rtl8169
6030 */
6031 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6032 {
6033 struct rtl8169_private *tp = netdev_priv(dev);
6034 void __iomem *ioaddr = tp->mmio_addr;
6035 unsigned long flags;
6036
6037 if (netif_running(dev)) {
6038 spin_lock_irqsave(&tp->lock, flags);
6039 rtl8169_rx_missed(dev, ioaddr);
6040 spin_unlock_irqrestore(&tp->lock, flags);
6041 }
6042
6043 return &dev->stats;
6044 }
6045
6046 static void rtl8169_net_suspend(struct net_device *dev)
6047 {
6048 struct rtl8169_private *tp = netdev_priv(dev);
6049
6050 if (!netif_running(dev))
6051 return;
6052
6053 rtl_pll_power_down(tp);
6054
6055 netif_device_detach(dev);
6056 netif_stop_queue(dev);
6057 }
6058
6059 #ifdef CONFIG_PM
6060
6061 static int rtl8169_suspend(struct device *device)
6062 {
6063 struct pci_dev *pdev = to_pci_dev(device);
6064 struct net_device *dev = pci_get_drvdata(pdev);
6065
6066 rtl8169_net_suspend(dev);
6067
6068 return 0;
6069 }
6070
6071 static void __rtl8169_resume(struct net_device *dev)
6072 {
6073 struct rtl8169_private *tp = netdev_priv(dev);
6074
6075 netif_device_attach(dev);
6076
6077 rtl_pll_power_up(tp);
6078
6079 rtl8169_schedule_work(dev, rtl8169_reset_task);
6080 }
6081
6082 static int rtl8169_resume(struct device *device)
6083 {
6084 struct pci_dev *pdev = to_pci_dev(device);
6085 struct net_device *dev = pci_get_drvdata(pdev);
6086 struct rtl8169_private *tp = netdev_priv(dev);
6087
6088 rtl8169_init_phy(dev, tp);
6089
6090 if (netif_running(dev))
6091 __rtl8169_resume(dev);
6092
6093 return 0;
6094 }
6095
6096 static int rtl8169_runtime_suspend(struct device *device)
6097 {
6098 struct pci_dev *pdev = to_pci_dev(device);
6099 struct net_device *dev = pci_get_drvdata(pdev);
6100 struct rtl8169_private *tp = netdev_priv(dev);
6101
6102 if (!tp->TxDescArray)
6103 return 0;
6104
6105 spin_lock_irq(&tp->lock);
6106 tp->saved_wolopts = __rtl8169_get_wol(tp);
6107 __rtl8169_set_wol(tp, WAKE_ANY);
6108 spin_unlock_irq(&tp->lock);
6109
6110 rtl8169_net_suspend(dev);
6111
6112 return 0;
6113 }
6114
6115 static int rtl8169_runtime_resume(struct device *device)
6116 {
6117 struct pci_dev *pdev = to_pci_dev(device);
6118 struct net_device *dev = pci_get_drvdata(pdev);
6119 struct rtl8169_private *tp = netdev_priv(dev);
6120
6121 if (!tp->TxDescArray)
6122 return 0;
6123
6124 spin_lock_irq(&tp->lock);
6125 __rtl8169_set_wol(tp, tp->saved_wolopts);
6126 tp->saved_wolopts = 0;
6127 spin_unlock_irq(&tp->lock);
6128
6129 rtl8169_init_phy(dev, tp);
6130
6131 __rtl8169_resume(dev);
6132
6133 return 0;
6134 }
6135
6136 static int rtl8169_runtime_idle(struct device *device)
6137 {
6138 struct pci_dev *pdev = to_pci_dev(device);
6139 struct net_device *dev = pci_get_drvdata(pdev);
6140 struct rtl8169_private *tp = netdev_priv(dev);
6141
6142 return tp->TxDescArray ? -EBUSY : 0;
6143 }
6144
6145 static const struct dev_pm_ops rtl8169_pm_ops = {
6146 .suspend = rtl8169_suspend,
6147 .resume = rtl8169_resume,
6148 .freeze = rtl8169_suspend,
6149 .thaw = rtl8169_resume,
6150 .poweroff = rtl8169_suspend,
6151 .restore = rtl8169_resume,
6152 .runtime_suspend = rtl8169_runtime_suspend,
6153 .runtime_resume = rtl8169_runtime_resume,
6154 .runtime_idle = rtl8169_runtime_idle,
6155 };
6156
6157 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6158
6159 #else /* !CONFIG_PM */
6160
6161 #define RTL8169_PM_OPS NULL
6162
6163 #endif /* !CONFIG_PM */
6164
6165 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6166 {
6167 void __iomem *ioaddr = tp->mmio_addr;
6168
6169 /* WoL fails with 8168b when the receiver is disabled. */
6170 switch (tp->mac_version) {
6171 case RTL_GIGA_MAC_VER_11:
6172 case RTL_GIGA_MAC_VER_12:
6173 case RTL_GIGA_MAC_VER_17:
6174 pci_clear_master(tp->pci_dev);
6175
6176 RTL_W8(ChipCmd, CmdRxEnb);
6177 /* PCI commit */
6178 RTL_R8(ChipCmd);
6179 break;
6180 default:
6181 break;
6182 }
6183 }
6184
6185 static void rtl_shutdown(struct pci_dev *pdev)
6186 {
6187 struct net_device *dev = pci_get_drvdata(pdev);
6188 struct rtl8169_private *tp = netdev_priv(dev);
6189
6190 rtl8169_net_suspend(dev);
6191
6192 /* Restore original MAC address */
6193 rtl_rar_set(tp, dev->perm_addr);
6194
6195 spin_lock_irq(&tp->lock);
6196
6197 rtl8169_hw_reset(tp);
6198
6199 spin_unlock_irq(&tp->lock);
6200
6201 if (system_state == SYSTEM_POWER_OFF) {
6202 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6203 rtl_wol_suspend_quirk(tp);
6204 rtl_wol_shutdown_quirk(tp);
6205 }
6206
6207 pci_wake_from_d3(pdev, true);
6208 pci_set_power_state(pdev, PCI_D3hot);
6209 }
6210 }
6211
6212 static struct pci_driver rtl8169_pci_driver = {
6213 .name = MODULENAME,
6214 .id_table = rtl8169_pci_tbl,
6215 .probe = rtl8169_init_one,
6216 .remove = __devexit_p(rtl8169_remove_one),
6217 .shutdown = rtl_shutdown,
6218 .driver.pm = RTL8169_PM_OPS,
6219 };
6220
6221 static int __init rtl8169_init_module(void)
6222 {
6223 return pci_register_driver(&rtl8169_pci_driver);
6224 }
6225
6226 static void __exit rtl8169_cleanup_module(void)
6227 {
6228 pci_unregister_driver(&rtl8169_pci_driver);
6229 }
6230
6231 module_init(rtl8169_init_module);
6232 module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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