1 /* Renesas Ethernet AVB device driver
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 * Based on the SuperH Ethernet driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
35 #include <asm/div64.h>
39 #define RAVB_DEF_MSG_ENABLE \
45 void ravb_modify(struct net_device
*ndev
, enum ravb_reg reg
, u32 clear
,
48 ravb_write(ndev
, (ravb_read(ndev
, reg
) & ~clear
) | set
, reg
);
51 int ravb_wait(struct net_device
*ndev
, enum ravb_reg reg
, u32 mask
, u32 value
)
55 for (i
= 0; i
< 10000; i
++) {
56 if ((ravb_read(ndev
, reg
) & mask
) == value
)
63 static int ravb_config(struct net_device
*ndev
)
68 ravb_modify(ndev
, CCC
, CCC_OPC
, CCC_OPC_CONFIG
);
69 /* Check if the operating mode is changed to the config mode */
70 error
= ravb_wait(ndev
, CSR
, CSR_OPS
, CSR_OPS_CONFIG
);
72 netdev_err(ndev
, "failed to switch device to config mode\n");
77 static void ravb_set_duplex(struct net_device
*ndev
)
79 struct ravb_private
*priv
= netdev_priv(ndev
);
81 ravb_modify(ndev
, ECMR
, ECMR_DM
, priv
->duplex
? ECMR_DM
: 0);
84 static void ravb_set_rate(struct net_device
*ndev
)
86 struct ravb_private
*priv
= netdev_priv(ndev
);
88 switch (priv
->speed
) {
89 case 100: /* 100BASE */
90 ravb_write(ndev
, GECMR_SPEED_100
, GECMR
);
92 case 1000: /* 1000BASE */
93 ravb_write(ndev
, GECMR_SPEED_1000
, GECMR
);
98 static void ravb_set_buffer_align(struct sk_buff
*skb
)
100 u32 reserve
= (unsigned long)skb
->data
& (RAVB_ALIGN
- 1);
103 skb_reserve(skb
, RAVB_ALIGN
- reserve
);
106 /* Get MAC address from the MAC address registers
108 * Ethernet AVB device doesn't have ROM for MAC address.
109 * This function gets the MAC address that was used by a bootloader.
111 static void ravb_read_mac_address(struct net_device
*ndev
, const u8
*mac
)
114 ether_addr_copy(ndev
->dev_addr
, mac
);
116 u32 mahr
= ravb_read(ndev
, MAHR
);
117 u32 malr
= ravb_read(ndev
, MALR
);
119 ndev
->dev_addr
[0] = (mahr
>> 24) & 0xFF;
120 ndev
->dev_addr
[1] = (mahr
>> 16) & 0xFF;
121 ndev
->dev_addr
[2] = (mahr
>> 8) & 0xFF;
122 ndev
->dev_addr
[3] = (mahr
>> 0) & 0xFF;
123 ndev
->dev_addr
[4] = (malr
>> 8) & 0xFF;
124 ndev
->dev_addr
[5] = (malr
>> 0) & 0xFF;
128 static void ravb_mdio_ctrl(struct mdiobb_ctrl
*ctrl
, u32 mask
, int set
)
130 struct ravb_private
*priv
= container_of(ctrl
, struct ravb_private
,
133 ravb_modify(priv
->ndev
, PIR
, mask
, set
? mask
: 0);
136 /* MDC pin control */
137 static void ravb_set_mdc(struct mdiobb_ctrl
*ctrl
, int level
)
139 ravb_mdio_ctrl(ctrl
, PIR_MDC
, level
);
142 /* Data I/O pin control */
143 static void ravb_set_mdio_dir(struct mdiobb_ctrl
*ctrl
, int output
)
145 ravb_mdio_ctrl(ctrl
, PIR_MMD
, output
);
149 static void ravb_set_mdio_data(struct mdiobb_ctrl
*ctrl
, int value
)
151 ravb_mdio_ctrl(ctrl
, PIR_MDO
, value
);
155 static int ravb_get_mdio_data(struct mdiobb_ctrl
*ctrl
)
157 struct ravb_private
*priv
= container_of(ctrl
, struct ravb_private
,
160 return (ravb_read(priv
->ndev
, PIR
) & PIR_MDI
) != 0;
163 /* MDIO bus control struct */
164 static struct mdiobb_ops bb_ops
= {
165 .owner
= THIS_MODULE
,
166 .set_mdc
= ravb_set_mdc
,
167 .set_mdio_dir
= ravb_set_mdio_dir
,
168 .set_mdio_data
= ravb_set_mdio_data
,
169 .get_mdio_data
= ravb_get_mdio_data
,
172 /* Free skb's and DMA buffers for Ethernet AVB */
173 static void ravb_ring_free(struct net_device
*ndev
, int q
)
175 struct ravb_private
*priv
= netdev_priv(ndev
);
179 /* Free RX skb ringbuffer */
180 if (priv
->rx_skb
[q
]) {
181 for (i
= 0; i
< priv
->num_rx_ring
[q
]; i
++)
182 dev_kfree_skb(priv
->rx_skb
[q
][i
]);
184 kfree(priv
->rx_skb
[q
]);
185 priv
->rx_skb
[q
] = NULL
;
187 /* Free TX skb ringbuffer */
188 if (priv
->tx_skb
[q
]) {
189 for (i
= 0; i
< priv
->num_tx_ring
[q
]; i
++)
190 dev_kfree_skb(priv
->tx_skb
[q
][i
]);
192 kfree(priv
->tx_skb
[q
]);
193 priv
->tx_skb
[q
] = NULL
;
195 /* Free aligned TX buffers */
196 kfree(priv
->tx_align
[q
]);
197 priv
->tx_align
[q
] = NULL
;
199 if (priv
->rx_ring
[q
]) {
200 ring_size
= sizeof(struct ravb_ex_rx_desc
) *
201 (priv
->num_rx_ring
[q
] + 1);
202 dma_free_coherent(ndev
->dev
.parent
, ring_size
, priv
->rx_ring
[q
],
203 priv
->rx_desc_dma
[q
]);
204 priv
->rx_ring
[q
] = NULL
;
207 if (priv
->tx_ring
[q
]) {
208 ring_size
= sizeof(struct ravb_tx_desc
) *
209 (priv
->num_tx_ring
[q
] * NUM_TX_DESC
+ 1);
210 dma_free_coherent(ndev
->dev
.parent
, ring_size
, priv
->tx_ring
[q
],
211 priv
->tx_desc_dma
[q
]);
212 priv
->tx_ring
[q
] = NULL
;
216 /* Format skb and descriptor buffer for Ethernet AVB */
217 static void ravb_ring_format(struct net_device
*ndev
, int q
)
219 struct ravb_private
*priv
= netdev_priv(ndev
);
220 struct ravb_ex_rx_desc
*rx_desc
;
221 struct ravb_tx_desc
*tx_desc
;
222 struct ravb_desc
*desc
;
223 int rx_ring_size
= sizeof(*rx_desc
) * priv
->num_rx_ring
[q
];
224 int tx_ring_size
= sizeof(*tx_desc
) * priv
->num_tx_ring
[q
] *
231 priv
->dirty_rx
[q
] = 0;
232 priv
->dirty_tx
[q
] = 0;
234 memset(priv
->rx_ring
[q
], 0, rx_ring_size
);
235 /* Build RX ring buffer */
236 for (i
= 0; i
< priv
->num_rx_ring
[q
]; i
++) {
238 rx_desc
= &priv
->rx_ring
[q
][i
];
239 /* The size of the buffer should be on 16-byte boundary. */
240 rx_desc
->ds_cc
= cpu_to_le16(ALIGN(PKT_BUF_SZ
, 16));
241 dma_addr
= dma_map_single(ndev
->dev
.parent
, priv
->rx_skb
[q
][i
]->data
,
242 ALIGN(PKT_BUF_SZ
, 16),
244 /* We just set the data size to 0 for a failed mapping which
245 * should prevent DMA from happening...
247 if (dma_mapping_error(ndev
->dev
.parent
, dma_addr
))
248 rx_desc
->ds_cc
= cpu_to_le16(0);
249 rx_desc
->dptr
= cpu_to_le32(dma_addr
);
250 rx_desc
->die_dt
= DT_FEMPTY
;
252 rx_desc
= &priv
->rx_ring
[q
][i
];
253 rx_desc
->dptr
= cpu_to_le32((u32
)priv
->rx_desc_dma
[q
]);
254 rx_desc
->die_dt
= DT_LINKFIX
; /* type */
256 memset(priv
->tx_ring
[q
], 0, tx_ring_size
);
257 /* Build TX ring buffer */
258 for (i
= 0, tx_desc
= priv
->tx_ring
[q
]; i
< priv
->num_tx_ring
[q
];
260 tx_desc
->die_dt
= DT_EEMPTY
;
262 tx_desc
->die_dt
= DT_EEMPTY
;
264 tx_desc
->dptr
= cpu_to_le32((u32
)priv
->tx_desc_dma
[q
]);
265 tx_desc
->die_dt
= DT_LINKFIX
; /* type */
267 /* RX descriptor base address for best effort */
268 desc
= &priv
->desc_bat
[RX_QUEUE_OFFSET
+ q
];
269 desc
->die_dt
= DT_LINKFIX
; /* type */
270 desc
->dptr
= cpu_to_le32((u32
)priv
->rx_desc_dma
[q
]);
272 /* TX descriptor base address for best effort */
273 desc
= &priv
->desc_bat
[q
];
274 desc
->die_dt
= DT_LINKFIX
; /* type */
275 desc
->dptr
= cpu_to_le32((u32
)priv
->tx_desc_dma
[q
]);
278 /* Init skb and descriptor buffer for Ethernet AVB */
279 static int ravb_ring_init(struct net_device
*ndev
, int q
)
281 struct ravb_private
*priv
= netdev_priv(ndev
);
286 /* Allocate RX and TX skb rings */
287 priv
->rx_skb
[q
] = kcalloc(priv
->num_rx_ring
[q
],
288 sizeof(*priv
->rx_skb
[q
]), GFP_KERNEL
);
289 priv
->tx_skb
[q
] = kcalloc(priv
->num_tx_ring
[q
],
290 sizeof(*priv
->tx_skb
[q
]), GFP_KERNEL
);
291 if (!priv
->rx_skb
[q
] || !priv
->tx_skb
[q
])
294 for (i
= 0; i
< priv
->num_rx_ring
[q
]; i
++) {
295 skb
= netdev_alloc_skb(ndev
, PKT_BUF_SZ
+ RAVB_ALIGN
- 1);
298 ravb_set_buffer_align(skb
);
299 priv
->rx_skb
[q
][i
] = skb
;
302 /* Allocate rings for the aligned buffers */
303 priv
->tx_align
[q
] = kmalloc(DPTR_ALIGN
* priv
->num_tx_ring
[q
] +
304 DPTR_ALIGN
- 1, GFP_KERNEL
);
305 if (!priv
->tx_align
[q
])
308 /* Allocate all RX descriptors. */
309 ring_size
= sizeof(struct ravb_ex_rx_desc
) * (priv
->num_rx_ring
[q
] + 1);
310 priv
->rx_ring
[q
] = dma_alloc_coherent(ndev
->dev
.parent
, ring_size
,
311 &priv
->rx_desc_dma
[q
],
313 if (!priv
->rx_ring
[q
])
316 priv
->dirty_rx
[q
] = 0;
318 /* Allocate all TX descriptors. */
319 ring_size
= sizeof(struct ravb_tx_desc
) *
320 (priv
->num_tx_ring
[q
] * NUM_TX_DESC
+ 1);
321 priv
->tx_ring
[q
] = dma_alloc_coherent(ndev
->dev
.parent
, ring_size
,
322 &priv
->tx_desc_dma
[q
],
324 if (!priv
->tx_ring
[q
])
330 ravb_ring_free(ndev
, q
);
335 /* E-MAC init function */
336 static void ravb_emac_init(struct net_device
*ndev
)
338 struct ravb_private
*priv
= netdev_priv(ndev
);
340 /* Receive frame limit set register */
341 ravb_write(ndev
, ndev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
+ ETH_FCS_LEN
, RFLR
);
343 /* PAUSE prohibition */
344 ravb_write(ndev
, ECMR_ZPF
| (priv
->duplex
? ECMR_DM
: 0) |
345 ECMR_TE
| ECMR_RE
, ECMR
);
349 /* Set MAC address */
351 (ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
352 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]), MAHR
);
354 (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]), MALR
);
356 ravb_write(ndev
, 1, MPR
);
358 /* E-MAC status register clear */
359 ravb_write(ndev
, ECSR_ICD
| ECSR_MPD
, ECSR
);
361 /* E-MAC interrupt enable register */
362 ravb_write(ndev
, ECSIPR_ICDIP
| ECSIPR_MPDIP
| ECSIPR_LCHNGIP
, ECSIPR
);
365 /* Device init function for Ethernet AVB */
366 static int ravb_dmac_init(struct net_device
*ndev
)
370 /* Set CONFIG mode */
371 error
= ravb_config(ndev
);
375 error
= ravb_ring_init(ndev
, RAVB_BE
);
378 error
= ravb_ring_init(ndev
, RAVB_NC
);
380 ravb_ring_free(ndev
, RAVB_BE
);
384 /* Descriptor format */
385 ravb_ring_format(ndev
, RAVB_BE
);
386 ravb_ring_format(ndev
, RAVB_NC
);
388 #if defined(__LITTLE_ENDIAN)
389 ravb_modify(ndev
, CCC
, CCC_BOC
, 0);
391 ravb_modify(ndev
, CCC
, CCC_BOC
, CCC_BOC
);
395 ravb_write(ndev
, RCR_EFFS
| RCR_ENCF
| RCR_ETS0
| 0x18000000, RCR
);
398 ravb_write(ndev
, TGC_TQP_AVBMODE1
| 0x00222200, TGC
);
400 /* Timestamp enable */
401 ravb_write(ndev
, TCCR_TFEN
, TCCR
);
403 /* Interrupt init: */
405 ravb_write(ndev
, RIC0_FRE0
| RIC0_FRE1
, RIC0
);
406 /* Disable FIFO full warning */
407 ravb_write(ndev
, 0, RIC1
);
408 /* Receive FIFO full error, descriptor empty */
409 ravb_write(ndev
, RIC2_QFE0
| RIC2_QFE1
| RIC2_RFFE
, RIC2
);
410 /* Frame transmitted, timestamp FIFO updated */
411 ravb_write(ndev
, TIC_FTE0
| TIC_FTE1
| TIC_TFUE
, TIC
);
413 /* Setting the control will start the AVB-DMAC process. */
414 ravb_modify(ndev
, CCC
, CCC_OPC
, CCC_OPC_OPERATION
);
419 /* Free TX skb function for AVB-IP */
420 static int ravb_tx_free(struct net_device
*ndev
, int q
)
422 struct ravb_private
*priv
= netdev_priv(ndev
);
423 struct net_device_stats
*stats
= &priv
->stats
[q
];
424 struct ravb_tx_desc
*desc
;
429 for (; priv
->cur_tx
[q
] - priv
->dirty_tx
[q
] > 0; priv
->dirty_tx
[q
]++) {
430 entry
= priv
->dirty_tx
[q
] % (priv
->num_tx_ring
[q
] *
432 desc
= &priv
->tx_ring
[q
][entry
];
433 if (desc
->die_dt
!= DT_FEMPTY
)
435 /* Descriptor type must be checked before all other reads */
437 size
= le16_to_cpu(desc
->ds_tagl
) & TX_DS
;
438 /* Free the original skb. */
439 if (priv
->tx_skb
[q
][entry
/ NUM_TX_DESC
]) {
440 dma_unmap_single(ndev
->dev
.parent
, le32_to_cpu(desc
->dptr
),
441 size
, DMA_TO_DEVICE
);
442 /* Last packet descriptor? */
443 if (entry
% NUM_TX_DESC
== NUM_TX_DESC
- 1) {
444 entry
/= NUM_TX_DESC
;
445 dev_kfree_skb_any(priv
->tx_skb
[q
][entry
]);
446 priv
->tx_skb
[q
][entry
] = NULL
;
451 stats
->tx_bytes
+= size
;
452 desc
->die_dt
= DT_EEMPTY
;
457 static void ravb_get_tx_tstamp(struct net_device
*ndev
)
459 struct ravb_private
*priv
= netdev_priv(ndev
);
460 struct ravb_tstamp_skb
*ts_skb
, *ts_skb2
;
461 struct skb_shared_hwtstamps shhwtstamps
;
463 struct timespec64 ts
;
468 count
= (ravb_read(ndev
, TSR
) & TSR_TFFL
) >> 8;
470 tfa2
= ravb_read(ndev
, TFA2
);
471 tfa_tag
= (tfa2
& TFA2_TST
) >> 16;
472 ts
.tv_nsec
= (u64
)ravb_read(ndev
, TFA0
);
473 ts
.tv_sec
= ((u64
)(tfa2
& TFA2_TSV
) << 32) |
474 ravb_read(ndev
, TFA1
);
475 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
476 shhwtstamps
.hwtstamp
= timespec64_to_ktime(ts
);
477 list_for_each_entry_safe(ts_skb
, ts_skb2
, &priv
->ts_skb_list
,
481 list_del(&ts_skb
->list
);
483 if (tag
== tfa_tag
) {
484 skb_tstamp_tx(skb
, &shhwtstamps
);
488 ravb_modify(ndev
, TCCR
, TCCR_TFR
, TCCR_TFR
);
492 /* Packet receive function for Ethernet AVB */
493 static bool ravb_rx(struct net_device
*ndev
, int *quota
, int q
)
495 struct ravb_private
*priv
= netdev_priv(ndev
);
496 int entry
= priv
->cur_rx
[q
] % priv
->num_rx_ring
[q
];
497 int boguscnt
= (priv
->dirty_rx
[q
] + priv
->num_rx_ring
[q
]) -
499 struct net_device_stats
*stats
= &priv
->stats
[q
];
500 struct ravb_ex_rx_desc
*desc
;
503 struct timespec64 ts
;
508 boguscnt
= min(boguscnt
, *quota
);
510 desc
= &priv
->rx_ring
[q
][entry
];
511 while (desc
->die_dt
!= DT_FEMPTY
) {
512 /* Descriptor type must be checked before all other reads */
514 desc_status
= desc
->msc
;
515 pkt_len
= le16_to_cpu(desc
->ds_cc
) & RX_DS
;
520 /* We use 0-byte descriptors to mark the DMA mapping errors */
524 if (desc_status
& MSC_MC
)
527 if (desc_status
& (MSC_CRC
| MSC_RFE
| MSC_RTSF
| MSC_RTLF
|
530 if (desc_status
& MSC_CRC
)
531 stats
->rx_crc_errors
++;
532 if (desc_status
& MSC_RFE
)
533 stats
->rx_frame_errors
++;
534 if (desc_status
& (MSC_RTLF
| MSC_RTSF
))
535 stats
->rx_length_errors
++;
536 if (desc_status
& MSC_CEEF
)
537 stats
->rx_missed_errors
++;
539 u32 get_ts
= priv
->tstamp_rx_ctrl
& RAVB_RXTSTAMP_TYPE
;
541 skb
= priv
->rx_skb
[q
][entry
];
542 priv
->rx_skb
[q
][entry
] = NULL
;
543 dma_unmap_single(ndev
->dev
.parent
, le32_to_cpu(desc
->dptr
),
544 ALIGN(PKT_BUF_SZ
, 16),
546 get_ts
&= (q
== RAVB_NC
) ?
547 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT
:
548 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT
;
550 struct skb_shared_hwtstamps
*shhwtstamps
;
552 shhwtstamps
= skb_hwtstamps(skb
);
553 memset(shhwtstamps
, 0, sizeof(*shhwtstamps
));
554 ts
.tv_sec
= ((u64
) le16_to_cpu(desc
->ts_sh
) <<
555 32) | le32_to_cpu(desc
->ts_sl
);
556 ts
.tv_nsec
= le32_to_cpu(desc
->ts_n
);
557 shhwtstamps
->hwtstamp
= timespec64_to_ktime(ts
);
559 skb_put(skb
, pkt_len
);
560 skb
->protocol
= eth_type_trans(skb
, ndev
);
561 napi_gro_receive(&priv
->napi
[q
], skb
);
563 stats
->rx_bytes
+= pkt_len
;
566 entry
= (++priv
->cur_rx
[q
]) % priv
->num_rx_ring
[q
];
567 desc
= &priv
->rx_ring
[q
][entry
];
570 /* Refill the RX ring buffers. */
571 for (; priv
->cur_rx
[q
] - priv
->dirty_rx
[q
] > 0; priv
->dirty_rx
[q
]++) {
572 entry
= priv
->dirty_rx
[q
] % priv
->num_rx_ring
[q
];
573 desc
= &priv
->rx_ring
[q
][entry
];
574 /* The size of the buffer should be on 16-byte boundary. */
575 desc
->ds_cc
= cpu_to_le16(ALIGN(PKT_BUF_SZ
, 16));
577 if (!priv
->rx_skb
[q
][entry
]) {
578 skb
= netdev_alloc_skb(ndev
,
579 PKT_BUF_SZ
+ RAVB_ALIGN
- 1);
581 break; /* Better luck next round. */
582 ravb_set_buffer_align(skb
);
583 dma_addr
= dma_map_single(ndev
->dev
.parent
, skb
->data
,
584 le16_to_cpu(desc
->ds_cc
),
586 skb_checksum_none_assert(skb
);
587 /* We just set the data size to 0 for a failed mapping
588 * which should prevent DMA from happening...
590 if (dma_mapping_error(ndev
->dev
.parent
, dma_addr
))
591 desc
->ds_cc
= cpu_to_le16(0);
592 desc
->dptr
= cpu_to_le32(dma_addr
);
593 priv
->rx_skb
[q
][entry
] = skb
;
595 /* Descriptor type must be set after all the above writes */
597 desc
->die_dt
= DT_FEMPTY
;
600 *quota
-= limit
- (++boguscnt
);
602 return boguscnt
<= 0;
605 static void ravb_rcv_snd_disable(struct net_device
*ndev
)
607 /* Disable TX and RX */
608 ravb_modify(ndev
, ECMR
, ECMR_RE
| ECMR_TE
, 0);
611 static void ravb_rcv_snd_enable(struct net_device
*ndev
)
613 /* Enable TX and RX */
614 ravb_modify(ndev
, ECMR
, ECMR_RE
| ECMR_TE
, ECMR_RE
| ECMR_TE
);
617 /* function for waiting dma process finished */
618 static int ravb_stop_dma(struct net_device
*ndev
)
622 /* Wait for stopping the hardware TX process */
623 error
= ravb_wait(ndev
, TCCR
,
624 TCCR_TSRQ0
| TCCR_TSRQ1
| TCCR_TSRQ2
| TCCR_TSRQ3
, 0);
628 error
= ravb_wait(ndev
, CSR
, CSR_TPO0
| CSR_TPO1
| CSR_TPO2
| CSR_TPO3
,
633 /* Stop the E-MAC's RX/TX processes. */
634 ravb_rcv_snd_disable(ndev
);
636 /* Wait for stopping the RX DMA process */
637 error
= ravb_wait(ndev
, CSR
, CSR_RPO
, 0);
641 /* Stop AVB-DMAC process */
642 return ravb_config(ndev
);
645 /* E-MAC interrupt handler */
646 static void ravb_emac_interrupt(struct net_device
*ndev
)
648 struct ravb_private
*priv
= netdev_priv(ndev
);
651 ecsr
= ravb_read(ndev
, ECSR
);
652 ravb_write(ndev
, ecsr
, ECSR
); /* clear interrupt */
654 ndev
->stats
.tx_carrier_errors
++;
655 if (ecsr
& ECSR_LCHNG
) {
657 if (priv
->no_avb_link
)
659 psr
= ravb_read(ndev
, PSR
);
660 if (priv
->avb_link_active_low
)
662 if (!(psr
& PSR_LMON
)) {
663 /* DIsable RX and TX */
664 ravb_rcv_snd_disable(ndev
);
666 /* Enable RX and TX */
667 ravb_rcv_snd_enable(ndev
);
672 /* Error interrupt handler */
673 static void ravb_error_interrupt(struct net_device
*ndev
)
675 struct ravb_private
*priv
= netdev_priv(ndev
);
678 eis
= ravb_read(ndev
, EIS
);
679 ravb_write(ndev
, ~EIS_QFS
, EIS
);
681 ris2
= ravb_read(ndev
, RIS2
);
682 ravb_write(ndev
, ~(RIS2_QFF0
| RIS2_RFFF
), RIS2
);
684 /* Receive Descriptor Empty int */
685 if (ris2
& RIS2_QFF0
)
686 priv
->stats
[RAVB_BE
].rx_over_errors
++;
688 /* Receive Descriptor Empty int */
689 if (ris2
& RIS2_QFF1
)
690 priv
->stats
[RAVB_NC
].rx_over_errors
++;
692 /* Receive FIFO Overflow int */
693 if (ris2
& RIS2_RFFF
)
694 priv
->rx_fifo_errors
++;
698 static irqreturn_t
ravb_interrupt(int irq
, void *dev_id
)
700 struct net_device
*ndev
= dev_id
;
701 struct ravb_private
*priv
= netdev_priv(ndev
);
702 irqreturn_t result
= IRQ_NONE
;
705 spin_lock(&priv
->lock
);
706 /* Get interrupt status */
707 iss
= ravb_read(ndev
, ISS
);
709 /* Received and transmitted interrupts */
710 if (iss
& (ISS_FRS
| ISS_FTS
| ISS_TFUS
)) {
711 u32 ris0
= ravb_read(ndev
, RIS0
);
712 u32 ric0
= ravb_read(ndev
, RIC0
);
713 u32 tis
= ravb_read(ndev
, TIS
);
714 u32 tic
= ravb_read(ndev
, TIC
);
717 /* Timestamp updated */
718 if (tis
& TIS_TFUF
) {
719 ravb_write(ndev
, ~TIS_TFUF
, TIS
);
720 ravb_get_tx_tstamp(ndev
);
721 result
= IRQ_HANDLED
;
724 /* Network control and best effort queue RX/TX */
725 for (q
= RAVB_NC
; q
>= RAVB_BE
; q
--) {
726 if (((ris0
& ric0
) & BIT(q
)) ||
727 ((tis
& tic
) & BIT(q
))) {
728 if (napi_schedule_prep(&priv
->napi
[q
])) {
729 /* Mask RX and TX interrupts */
732 ravb_write(ndev
, ric0
, RIC0
);
733 ravb_write(ndev
, tic
, TIC
);
734 __napi_schedule(&priv
->napi
[q
]);
737 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
740 " tx status 0x%08x, tx mask 0x%08x.\n",
743 result
= IRQ_HANDLED
;
748 /* E-MAC status summary */
750 ravb_emac_interrupt(ndev
);
751 result
= IRQ_HANDLED
;
754 /* Error status summary */
756 ravb_error_interrupt(ndev
);
757 result
= IRQ_HANDLED
;
760 if ((iss
& ISS_CGIS
) && ravb_ptp_interrupt(ndev
) == IRQ_HANDLED
)
761 result
= IRQ_HANDLED
;
764 spin_unlock(&priv
->lock
);
768 static int ravb_poll(struct napi_struct
*napi
, int budget
)
770 struct net_device
*ndev
= napi
->dev
;
771 struct ravb_private
*priv
= netdev_priv(ndev
);
773 int q
= napi
- priv
->napi
;
779 tis
= ravb_read(ndev
, TIS
);
780 ris0
= ravb_read(ndev
, RIS0
);
781 if (!((ris0
& mask
) || (tis
& mask
)))
784 /* Processing RX Descriptor Ring */
786 /* Clear RX interrupt */
787 ravb_write(ndev
, ~mask
, RIS0
);
788 if (ravb_rx(ndev
, "a
, q
))
791 /* Processing TX Descriptor Ring */
793 spin_lock_irqsave(&priv
->lock
, flags
);
794 /* Clear TX interrupt */
795 ravb_write(ndev
, ~mask
, TIS
);
796 ravb_tx_free(ndev
, q
);
797 netif_wake_subqueue(ndev
, q
);
799 spin_unlock_irqrestore(&priv
->lock
, flags
);
805 /* Re-enable RX/TX interrupts */
806 spin_lock_irqsave(&priv
->lock
, flags
);
807 ravb_modify(ndev
, RIC0
, mask
, mask
);
808 ravb_modify(ndev
, TIC
, mask
, mask
);
810 spin_unlock_irqrestore(&priv
->lock
, flags
);
812 /* Receive error message handling */
813 priv
->rx_over_errors
= priv
->stats
[RAVB_BE
].rx_over_errors
;
814 priv
->rx_over_errors
+= priv
->stats
[RAVB_NC
].rx_over_errors
;
815 if (priv
->rx_over_errors
!= ndev
->stats
.rx_over_errors
) {
816 ndev
->stats
.rx_over_errors
= priv
->rx_over_errors
;
817 netif_err(priv
, rx_err
, ndev
, "Receive Descriptor Empty\n");
819 if (priv
->rx_fifo_errors
!= ndev
->stats
.rx_fifo_errors
) {
820 ndev
->stats
.rx_fifo_errors
= priv
->rx_fifo_errors
;
821 netif_err(priv
, rx_err
, ndev
, "Receive FIFO Overflow\n");
824 return budget
- quota
;
827 /* PHY state control function */
828 static void ravb_adjust_link(struct net_device
*ndev
)
830 struct ravb_private
*priv
= netdev_priv(ndev
);
831 struct phy_device
*phydev
= priv
->phydev
;
832 bool new_state
= false;
835 if (phydev
->duplex
!= priv
->duplex
) {
837 priv
->duplex
= phydev
->duplex
;
838 ravb_set_duplex(ndev
);
841 if (phydev
->speed
!= priv
->speed
) {
843 priv
->speed
= phydev
->speed
;
847 ravb_modify(ndev
, ECMR
, ECMR_TXF
, 0);
849 priv
->link
= phydev
->link
;
850 if (priv
->no_avb_link
)
851 ravb_rcv_snd_enable(ndev
);
853 } else if (priv
->link
) {
858 if (priv
->no_avb_link
)
859 ravb_rcv_snd_disable(ndev
);
862 if (new_state
&& netif_msg_link(priv
))
863 phy_print_status(phydev
);
866 /* PHY init function */
867 static int ravb_phy_init(struct net_device
*ndev
)
869 struct device_node
*np
= ndev
->dev
.parent
->of_node
;
870 struct ravb_private
*priv
= netdev_priv(ndev
);
871 struct phy_device
*phydev
;
872 struct device_node
*pn
;
879 /* Try connecting to PHY */
880 pn
= of_parse_phandle(np
, "phy-handle", 0);
882 /* In the case of a fixed PHY, the DT node associated
883 * to the PHY is the Ethernet MAC DT node.
885 if (of_phy_is_fixed_link(np
)) {
886 err
= of_phy_register_fixed_link(np
);
890 pn
= of_node_get(np
);
892 phydev
= of_phy_connect(ndev
, pn
, ravb_adjust_link
, 0,
893 priv
->phy_interface
);
895 netdev_err(ndev
, "failed to connect PHY\n");
899 /* This driver only support 10/100Mbit speeds on Gen3
902 if (priv
->chip_id
== RCAR_GEN3
) {
905 err
= phy_set_max_speed(phydev
, SPEED_100
);
907 netdev_err(ndev
, "failed to limit PHY to 100Mbit/s\n");
908 phy_disconnect(phydev
);
912 netdev_info(ndev
, "limited PHY to 100Mbit/s\n");
915 /* 10BASE is not supported */
916 phydev
->supported
&= ~PHY_10BT_FEATURES
;
918 phy_attached_info(phydev
);
920 priv
->phydev
= phydev
;
925 /* PHY control start function */
926 static int ravb_phy_start(struct net_device
*ndev
)
928 struct ravb_private
*priv
= netdev_priv(ndev
);
931 error
= ravb_phy_init(ndev
);
935 phy_start(priv
->phydev
);
940 static int ravb_get_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
942 struct ravb_private
*priv
= netdev_priv(ndev
);
947 spin_lock_irqsave(&priv
->lock
, flags
);
948 error
= phy_ethtool_gset(priv
->phydev
, ecmd
);
949 spin_unlock_irqrestore(&priv
->lock
, flags
);
955 static int ravb_set_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
957 struct ravb_private
*priv
= netdev_priv(ndev
);
964 spin_lock_irqsave(&priv
->lock
, flags
);
966 /* Disable TX and RX */
967 ravb_rcv_snd_disable(ndev
);
969 error
= phy_ethtool_sset(priv
->phydev
, ecmd
);
973 if (ecmd
->duplex
== DUPLEX_FULL
)
978 ravb_set_duplex(ndev
);
983 /* Enable TX and RX */
984 ravb_rcv_snd_enable(ndev
);
987 spin_unlock_irqrestore(&priv
->lock
, flags
);
992 static int ravb_nway_reset(struct net_device
*ndev
)
994 struct ravb_private
*priv
= netdev_priv(ndev
);
999 spin_lock_irqsave(&priv
->lock
, flags
);
1000 error
= phy_start_aneg(priv
->phydev
);
1001 spin_unlock_irqrestore(&priv
->lock
, flags
);
1007 static u32
ravb_get_msglevel(struct net_device
*ndev
)
1009 struct ravb_private
*priv
= netdev_priv(ndev
);
1011 return priv
->msg_enable
;
1014 static void ravb_set_msglevel(struct net_device
*ndev
, u32 value
)
1016 struct ravb_private
*priv
= netdev_priv(ndev
);
1018 priv
->msg_enable
= value
;
1021 static const char ravb_gstrings_stats
[][ETH_GSTRING_LEN
] = {
1022 "rx_queue_0_current",
1023 "tx_queue_0_current",
1026 "rx_queue_0_packets",
1027 "tx_queue_0_packets",
1030 "rx_queue_0_mcast_packets",
1031 "rx_queue_0_errors",
1032 "rx_queue_0_crc_errors",
1033 "rx_queue_0_frame_errors",
1034 "rx_queue_0_length_errors",
1035 "rx_queue_0_missed_errors",
1036 "rx_queue_0_over_errors",
1038 "rx_queue_1_current",
1039 "tx_queue_1_current",
1042 "rx_queue_1_packets",
1043 "tx_queue_1_packets",
1046 "rx_queue_1_mcast_packets",
1047 "rx_queue_1_errors",
1048 "rx_queue_1_crc_errors",
1049 "rx_queue_1_frame_errors",
1050 "rx_queue_1_length_errors",
1051 "rx_queue_1_missed_errors",
1052 "rx_queue_1_over_errors",
1055 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1057 static int ravb_get_sset_count(struct net_device
*netdev
, int sset
)
1061 return RAVB_STATS_LEN
;
1067 static void ravb_get_ethtool_stats(struct net_device
*ndev
,
1068 struct ethtool_stats
*stats
, u64
*data
)
1070 struct ravb_private
*priv
= netdev_priv(ndev
);
1074 /* Device-specific stats */
1075 for (q
= RAVB_BE
; q
< NUM_RX_QUEUE
; q
++) {
1076 struct net_device_stats
*stats
= &priv
->stats
[q
];
1078 data
[i
++] = priv
->cur_rx
[q
];
1079 data
[i
++] = priv
->cur_tx
[q
];
1080 data
[i
++] = priv
->dirty_rx
[q
];
1081 data
[i
++] = priv
->dirty_tx
[q
];
1082 data
[i
++] = stats
->rx_packets
;
1083 data
[i
++] = stats
->tx_packets
;
1084 data
[i
++] = stats
->rx_bytes
;
1085 data
[i
++] = stats
->tx_bytes
;
1086 data
[i
++] = stats
->multicast
;
1087 data
[i
++] = stats
->rx_errors
;
1088 data
[i
++] = stats
->rx_crc_errors
;
1089 data
[i
++] = stats
->rx_frame_errors
;
1090 data
[i
++] = stats
->rx_length_errors
;
1091 data
[i
++] = stats
->rx_missed_errors
;
1092 data
[i
++] = stats
->rx_over_errors
;
1096 static void ravb_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1098 switch (stringset
) {
1100 memcpy(data
, *ravb_gstrings_stats
, sizeof(ravb_gstrings_stats
));
1105 static void ravb_get_ringparam(struct net_device
*ndev
,
1106 struct ethtool_ringparam
*ring
)
1108 struct ravb_private
*priv
= netdev_priv(ndev
);
1110 ring
->rx_max_pending
= BE_RX_RING_MAX
;
1111 ring
->tx_max_pending
= BE_TX_RING_MAX
;
1112 ring
->rx_pending
= priv
->num_rx_ring
[RAVB_BE
];
1113 ring
->tx_pending
= priv
->num_tx_ring
[RAVB_BE
];
1116 static int ravb_set_ringparam(struct net_device
*ndev
,
1117 struct ethtool_ringparam
*ring
)
1119 struct ravb_private
*priv
= netdev_priv(ndev
);
1122 if (ring
->tx_pending
> BE_TX_RING_MAX
||
1123 ring
->rx_pending
> BE_RX_RING_MAX
||
1124 ring
->tx_pending
< BE_TX_RING_MIN
||
1125 ring
->rx_pending
< BE_RX_RING_MIN
)
1127 if (ring
->rx_mini_pending
|| ring
->rx_jumbo_pending
)
1130 if (netif_running(ndev
)) {
1131 netif_device_detach(ndev
);
1132 /* Stop PTP Clock driver */
1133 if (priv
->chip_id
== RCAR_GEN2
)
1134 ravb_ptp_stop(ndev
);
1135 /* Wait for DMA stopping */
1136 error
= ravb_stop_dma(ndev
);
1139 "cannot set ringparam! Any AVB processes are still running?\n");
1142 synchronize_irq(ndev
->irq
);
1144 /* Free all the skb's in the RX queue and the DMA buffers. */
1145 ravb_ring_free(ndev
, RAVB_BE
);
1146 ravb_ring_free(ndev
, RAVB_NC
);
1149 /* Set new parameters */
1150 priv
->num_rx_ring
[RAVB_BE
] = ring
->rx_pending
;
1151 priv
->num_tx_ring
[RAVB_BE
] = ring
->tx_pending
;
1153 if (netif_running(ndev
)) {
1154 error
= ravb_dmac_init(ndev
);
1157 "%s: ravb_dmac_init() failed, error %d\n",
1162 ravb_emac_init(ndev
);
1164 /* Initialise PTP Clock driver */
1165 if (priv
->chip_id
== RCAR_GEN2
)
1166 ravb_ptp_init(ndev
, priv
->pdev
);
1168 netif_device_attach(ndev
);
1174 static int ravb_get_ts_info(struct net_device
*ndev
,
1175 struct ethtool_ts_info
*info
)
1177 struct ravb_private
*priv
= netdev_priv(ndev
);
1179 info
->so_timestamping
=
1180 SOF_TIMESTAMPING_TX_SOFTWARE
|
1181 SOF_TIMESTAMPING_RX_SOFTWARE
|
1182 SOF_TIMESTAMPING_SOFTWARE
|
1183 SOF_TIMESTAMPING_TX_HARDWARE
|
1184 SOF_TIMESTAMPING_RX_HARDWARE
|
1185 SOF_TIMESTAMPING_RAW_HARDWARE
;
1186 info
->tx_types
= (1 << HWTSTAMP_TX_OFF
) | (1 << HWTSTAMP_TX_ON
);
1188 (1 << HWTSTAMP_FILTER_NONE
) |
1189 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT
) |
1190 (1 << HWTSTAMP_FILTER_ALL
);
1191 info
->phc_index
= ptp_clock_index(priv
->ptp
.clock
);
1196 static const struct ethtool_ops ravb_ethtool_ops
= {
1197 .get_settings
= ravb_get_settings
,
1198 .set_settings
= ravb_set_settings
,
1199 .nway_reset
= ravb_nway_reset
,
1200 .get_msglevel
= ravb_get_msglevel
,
1201 .set_msglevel
= ravb_set_msglevel
,
1202 .get_link
= ethtool_op_get_link
,
1203 .get_strings
= ravb_get_strings
,
1204 .get_ethtool_stats
= ravb_get_ethtool_stats
,
1205 .get_sset_count
= ravb_get_sset_count
,
1206 .get_ringparam
= ravb_get_ringparam
,
1207 .set_ringparam
= ravb_set_ringparam
,
1208 .get_ts_info
= ravb_get_ts_info
,
1211 /* Network device open function for Ethernet AVB */
1212 static int ravb_open(struct net_device
*ndev
)
1214 struct ravb_private
*priv
= netdev_priv(ndev
);
1217 napi_enable(&priv
->napi
[RAVB_BE
]);
1218 napi_enable(&priv
->napi
[RAVB_NC
]);
1220 error
= request_irq(ndev
->irq
, ravb_interrupt
, IRQF_SHARED
, ndev
->name
,
1223 netdev_err(ndev
, "cannot request IRQ\n");
1227 if (priv
->chip_id
== RCAR_GEN3
) {
1228 error
= request_irq(priv
->emac_irq
, ravb_interrupt
,
1229 IRQF_SHARED
, ndev
->name
, ndev
);
1231 netdev_err(ndev
, "cannot request IRQ\n");
1237 error
= ravb_dmac_init(ndev
);
1240 ravb_emac_init(ndev
);
1242 /* Initialise PTP Clock driver */
1243 if (priv
->chip_id
== RCAR_GEN2
)
1244 ravb_ptp_init(ndev
, priv
->pdev
);
1246 netif_tx_start_all_queues(ndev
);
1248 /* PHY control start */
1249 error
= ravb_phy_start(ndev
);
1256 /* Stop PTP Clock driver */
1257 if (priv
->chip_id
== RCAR_GEN2
)
1258 ravb_ptp_stop(ndev
);
1260 if (priv
->chip_id
== RCAR_GEN3
)
1261 free_irq(priv
->emac_irq
, ndev
);
1263 free_irq(ndev
->irq
, ndev
);
1265 napi_disable(&priv
->napi
[RAVB_NC
]);
1266 napi_disable(&priv
->napi
[RAVB_BE
]);
1270 /* Timeout function for Ethernet AVB */
1271 static void ravb_tx_timeout(struct net_device
*ndev
)
1273 struct ravb_private
*priv
= netdev_priv(ndev
);
1275 netif_err(priv
, tx_err
, ndev
,
1276 "transmit timed out, status %08x, resetting...\n",
1277 ravb_read(ndev
, ISS
));
1279 /* tx_errors count up */
1280 ndev
->stats
.tx_errors
++;
1282 schedule_work(&priv
->work
);
1285 static void ravb_tx_timeout_work(struct work_struct
*work
)
1287 struct ravb_private
*priv
= container_of(work
, struct ravb_private
,
1289 struct net_device
*ndev
= priv
->ndev
;
1291 netif_tx_stop_all_queues(ndev
);
1293 /* Stop PTP Clock driver */
1294 if (priv
->chip_id
== RCAR_GEN2
)
1295 ravb_ptp_stop(ndev
);
1297 /* Wait for DMA stopping */
1298 ravb_stop_dma(ndev
);
1300 ravb_ring_free(ndev
, RAVB_BE
);
1301 ravb_ring_free(ndev
, RAVB_NC
);
1304 ravb_dmac_init(ndev
);
1305 ravb_emac_init(ndev
);
1307 /* Initialise PTP Clock driver */
1308 if (priv
->chip_id
== RCAR_GEN2
)
1309 ravb_ptp_init(ndev
, priv
->pdev
);
1311 netif_tx_start_all_queues(ndev
);
1314 /* Packet transmit function for Ethernet AVB */
1315 static netdev_tx_t
ravb_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1317 struct ravb_private
*priv
= netdev_priv(ndev
);
1318 u16 q
= skb_get_queue_mapping(skb
);
1319 struct ravb_tstamp_skb
*ts_skb
;
1320 struct ravb_tx_desc
*desc
;
1321 unsigned long flags
;
1327 spin_lock_irqsave(&priv
->lock
, flags
);
1328 if (priv
->cur_tx
[q
] - priv
->dirty_tx
[q
] > (priv
->num_tx_ring
[q
] - 1) *
1330 netif_err(priv
, tx_queued
, ndev
,
1331 "still transmitting with the full ring!\n");
1332 netif_stop_subqueue(ndev
, q
);
1333 spin_unlock_irqrestore(&priv
->lock
, flags
);
1334 return NETDEV_TX_BUSY
;
1336 entry
= priv
->cur_tx
[q
] % (priv
->num_tx_ring
[q
] * NUM_TX_DESC
);
1337 priv
->tx_skb
[q
][entry
/ NUM_TX_DESC
] = skb
;
1339 if (skb_put_padto(skb
, ETH_ZLEN
))
1342 buffer
= PTR_ALIGN(priv
->tx_align
[q
], DPTR_ALIGN
) +
1343 entry
/ NUM_TX_DESC
* DPTR_ALIGN
;
1344 len
= PTR_ALIGN(skb
->data
, DPTR_ALIGN
) - skb
->data
;
1345 memcpy(buffer
, skb
->data
, len
);
1346 dma_addr
= dma_map_single(ndev
->dev
.parent
, buffer
, len
, DMA_TO_DEVICE
);
1347 if (dma_mapping_error(ndev
->dev
.parent
, dma_addr
))
1350 desc
= &priv
->tx_ring
[q
][entry
];
1351 desc
->ds_tagl
= cpu_to_le16(len
);
1352 desc
->dptr
= cpu_to_le32(dma_addr
);
1354 buffer
= skb
->data
+ len
;
1355 len
= skb
->len
- len
;
1356 dma_addr
= dma_map_single(ndev
->dev
.parent
, buffer
, len
, DMA_TO_DEVICE
);
1357 if (dma_mapping_error(ndev
->dev
.parent
, dma_addr
))
1361 desc
->ds_tagl
= cpu_to_le16(len
);
1362 desc
->dptr
= cpu_to_le32(dma_addr
);
1364 /* TX timestamp required */
1366 ts_skb
= kmalloc(sizeof(*ts_skb
), GFP_ATOMIC
);
1369 dma_unmap_single(ndev
->dev
.parent
, dma_addr
, len
,
1374 ts_skb
->tag
= priv
->ts_skb_tag
++;
1375 priv
->ts_skb_tag
&= 0x3ff;
1376 list_add_tail(&ts_skb
->list
, &priv
->ts_skb_list
);
1378 /* TAG and timestamp required flag */
1379 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
1380 skb_tx_timestamp(skb
);
1381 desc
->tagh_tsr
= (ts_skb
->tag
>> 4) | TX_TSR
;
1382 desc
->ds_tagl
|= le16_to_cpu(ts_skb
->tag
<< 12);
1385 /* Descriptor type must be set after all the above writes */
1387 desc
->die_dt
= DT_FEND
;
1389 desc
->die_dt
= DT_FSTART
;
1391 ravb_modify(ndev
, TCCR
, TCCR_TSRQ0
<< q
, TCCR_TSRQ0
<< q
);
1393 priv
->cur_tx
[q
] += NUM_TX_DESC
;
1394 if (priv
->cur_tx
[q
] - priv
->dirty_tx
[q
] >
1395 (priv
->num_tx_ring
[q
] - 1) * NUM_TX_DESC
&& !ravb_tx_free(ndev
, q
))
1396 netif_stop_subqueue(ndev
, q
);
1400 spin_unlock_irqrestore(&priv
->lock
, flags
);
1401 return NETDEV_TX_OK
;
1404 dma_unmap_single(ndev
->dev
.parent
, le32_to_cpu(desc
->dptr
),
1405 le16_to_cpu(desc
->ds_tagl
), DMA_TO_DEVICE
);
1407 dev_kfree_skb_any(skb
);
1408 priv
->tx_skb
[q
][entry
/ NUM_TX_DESC
] = NULL
;
1412 static u16
ravb_select_queue(struct net_device
*ndev
, struct sk_buff
*skb
,
1413 void *accel_priv
, select_queue_fallback_t fallback
)
1415 /* If skb needs TX timestamp, it is handled in network control queue */
1416 return (skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) ? RAVB_NC
:
1421 static struct net_device_stats
*ravb_get_stats(struct net_device
*ndev
)
1423 struct ravb_private
*priv
= netdev_priv(ndev
);
1424 struct net_device_stats
*nstats
, *stats0
, *stats1
;
1426 nstats
= &ndev
->stats
;
1427 stats0
= &priv
->stats
[RAVB_BE
];
1428 stats1
= &priv
->stats
[RAVB_NC
];
1430 nstats
->tx_dropped
+= ravb_read(ndev
, TROCR
);
1431 ravb_write(ndev
, 0, TROCR
); /* (write clear) */
1432 nstats
->collisions
+= ravb_read(ndev
, CDCR
);
1433 ravb_write(ndev
, 0, CDCR
); /* (write clear) */
1434 nstats
->tx_carrier_errors
+= ravb_read(ndev
, LCCR
);
1435 ravb_write(ndev
, 0, LCCR
); /* (write clear) */
1437 nstats
->tx_carrier_errors
+= ravb_read(ndev
, CERCR
);
1438 ravb_write(ndev
, 0, CERCR
); /* (write clear) */
1439 nstats
->tx_carrier_errors
+= ravb_read(ndev
, CEECR
);
1440 ravb_write(ndev
, 0, CEECR
); /* (write clear) */
1442 nstats
->rx_packets
= stats0
->rx_packets
+ stats1
->rx_packets
;
1443 nstats
->tx_packets
= stats0
->tx_packets
+ stats1
->tx_packets
;
1444 nstats
->rx_bytes
= stats0
->rx_bytes
+ stats1
->rx_bytes
;
1445 nstats
->tx_bytes
= stats0
->tx_bytes
+ stats1
->tx_bytes
;
1446 nstats
->multicast
= stats0
->multicast
+ stats1
->multicast
;
1447 nstats
->rx_errors
= stats0
->rx_errors
+ stats1
->rx_errors
;
1448 nstats
->rx_crc_errors
= stats0
->rx_crc_errors
+ stats1
->rx_crc_errors
;
1449 nstats
->rx_frame_errors
=
1450 stats0
->rx_frame_errors
+ stats1
->rx_frame_errors
;
1451 nstats
->rx_length_errors
=
1452 stats0
->rx_length_errors
+ stats1
->rx_length_errors
;
1453 nstats
->rx_missed_errors
=
1454 stats0
->rx_missed_errors
+ stats1
->rx_missed_errors
;
1455 nstats
->rx_over_errors
=
1456 stats0
->rx_over_errors
+ stats1
->rx_over_errors
;
1461 /* Update promiscuous bit */
1462 static void ravb_set_rx_mode(struct net_device
*ndev
)
1464 struct ravb_private
*priv
= netdev_priv(ndev
);
1465 unsigned long flags
;
1467 spin_lock_irqsave(&priv
->lock
, flags
);
1468 ravb_modify(ndev
, ECMR
, ECMR_PRM
,
1469 ndev
->flags
& IFF_PROMISC
? ECMR_PRM
: 0);
1471 spin_unlock_irqrestore(&priv
->lock
, flags
);
1474 /* Device close function for Ethernet AVB */
1475 static int ravb_close(struct net_device
*ndev
)
1477 struct ravb_private
*priv
= netdev_priv(ndev
);
1478 struct ravb_tstamp_skb
*ts_skb
, *ts_skb2
;
1480 netif_tx_stop_all_queues(ndev
);
1482 /* Disable interrupts by clearing the interrupt masks. */
1483 ravb_write(ndev
, 0, RIC0
);
1484 ravb_write(ndev
, 0, RIC2
);
1485 ravb_write(ndev
, 0, TIC
);
1487 /* Stop PTP Clock driver */
1488 if (priv
->chip_id
== RCAR_GEN2
)
1489 ravb_ptp_stop(ndev
);
1491 /* Set the config mode to stop the AVB-DMAC's processes */
1492 if (ravb_stop_dma(ndev
) < 0)
1494 "device will be stopped after h/w processes are done.\n");
1496 /* Clear the timestamp list */
1497 list_for_each_entry_safe(ts_skb
, ts_skb2
, &priv
->ts_skb_list
, list
) {
1498 list_del(&ts_skb
->list
);
1502 /* PHY disconnect */
1504 phy_stop(priv
->phydev
);
1505 phy_disconnect(priv
->phydev
);
1506 priv
->phydev
= NULL
;
1509 free_irq(ndev
->irq
, ndev
);
1511 napi_disable(&priv
->napi
[RAVB_NC
]);
1512 napi_disable(&priv
->napi
[RAVB_BE
]);
1514 /* Free all the skb's in the RX queue and the DMA buffers. */
1515 ravb_ring_free(ndev
, RAVB_BE
);
1516 ravb_ring_free(ndev
, RAVB_NC
);
1521 static int ravb_hwtstamp_get(struct net_device
*ndev
, struct ifreq
*req
)
1523 struct ravb_private
*priv
= netdev_priv(ndev
);
1524 struct hwtstamp_config config
;
1527 config
.tx_type
= priv
->tstamp_tx_ctrl
? HWTSTAMP_TX_ON
:
1529 if (priv
->tstamp_rx_ctrl
& RAVB_RXTSTAMP_TYPE_V2_L2_EVENT
)
1530 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L2_EVENT
;
1531 else if (priv
->tstamp_rx_ctrl
& RAVB_RXTSTAMP_TYPE_ALL
)
1532 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
1534 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
1536 return copy_to_user(req
->ifr_data
, &config
, sizeof(config
)) ?
1540 /* Control hardware time stamping */
1541 static int ravb_hwtstamp_set(struct net_device
*ndev
, struct ifreq
*req
)
1543 struct ravb_private
*priv
= netdev_priv(ndev
);
1544 struct hwtstamp_config config
;
1545 u32 tstamp_rx_ctrl
= RAVB_RXTSTAMP_ENABLED
;
1548 if (copy_from_user(&config
, req
->ifr_data
, sizeof(config
)))
1551 /* Reserved for future extensions */
1555 switch (config
.tx_type
) {
1556 case HWTSTAMP_TX_OFF
:
1559 case HWTSTAMP_TX_ON
:
1560 tstamp_tx_ctrl
= RAVB_TXTSTAMP_ENABLED
;
1566 switch (config
.rx_filter
) {
1567 case HWTSTAMP_FILTER_NONE
:
1570 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
1571 tstamp_rx_ctrl
|= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT
;
1574 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
1575 tstamp_rx_ctrl
|= RAVB_RXTSTAMP_TYPE_ALL
;
1578 priv
->tstamp_tx_ctrl
= tstamp_tx_ctrl
;
1579 priv
->tstamp_rx_ctrl
= tstamp_rx_ctrl
;
1581 return copy_to_user(req
->ifr_data
, &config
, sizeof(config
)) ?
1585 /* ioctl to device function */
1586 static int ravb_do_ioctl(struct net_device
*ndev
, struct ifreq
*req
, int cmd
)
1588 struct ravb_private
*priv
= netdev_priv(ndev
);
1589 struct phy_device
*phydev
= priv
->phydev
;
1591 if (!netif_running(ndev
))
1599 return ravb_hwtstamp_get(ndev
, req
);
1601 return ravb_hwtstamp_set(ndev
, req
);
1604 return phy_mii_ioctl(phydev
, req
, cmd
);
1607 static const struct net_device_ops ravb_netdev_ops
= {
1608 .ndo_open
= ravb_open
,
1609 .ndo_stop
= ravb_close
,
1610 .ndo_start_xmit
= ravb_start_xmit
,
1611 .ndo_select_queue
= ravb_select_queue
,
1612 .ndo_get_stats
= ravb_get_stats
,
1613 .ndo_set_rx_mode
= ravb_set_rx_mode
,
1614 .ndo_tx_timeout
= ravb_tx_timeout
,
1615 .ndo_do_ioctl
= ravb_do_ioctl
,
1616 .ndo_validate_addr
= eth_validate_addr
,
1617 .ndo_set_mac_address
= eth_mac_addr
,
1618 .ndo_change_mtu
= eth_change_mtu
,
1621 /* MDIO bus init function */
1622 static int ravb_mdio_init(struct ravb_private
*priv
)
1624 struct platform_device
*pdev
= priv
->pdev
;
1625 struct device
*dev
= &pdev
->dev
;
1629 priv
->mdiobb
.ops
= &bb_ops
;
1631 /* MII controller setting */
1632 priv
->mii_bus
= alloc_mdio_bitbang(&priv
->mdiobb
);
1636 /* Hook up MII support for ethtool */
1637 priv
->mii_bus
->name
= "ravb_mii";
1638 priv
->mii_bus
->parent
= dev
;
1639 snprintf(priv
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
1640 pdev
->name
, pdev
->id
);
1642 /* Register MDIO bus */
1643 error
= of_mdiobus_register(priv
->mii_bus
, dev
->of_node
);
1650 free_mdio_bitbang(priv
->mii_bus
);
1654 /* MDIO bus release function */
1655 static int ravb_mdio_release(struct ravb_private
*priv
)
1657 /* Unregister mdio bus */
1658 mdiobus_unregister(priv
->mii_bus
);
1660 /* Free bitbang info */
1661 free_mdio_bitbang(priv
->mii_bus
);
1666 static const struct of_device_id ravb_match_table
[] = {
1667 { .compatible
= "renesas,etheravb-r8a7790", .data
= (void *)RCAR_GEN2
},
1668 { .compatible
= "renesas,etheravb-r8a7794", .data
= (void *)RCAR_GEN2
},
1669 { .compatible
= "renesas,etheravb-rcar-gen2", .data
= (void *)RCAR_GEN2
},
1670 { .compatible
= "renesas,etheravb-r8a7795", .data
= (void *)RCAR_GEN3
},
1671 { .compatible
= "renesas,etheravb-rcar-gen3", .data
= (void *)RCAR_GEN3
},
1674 MODULE_DEVICE_TABLE(of
, ravb_match_table
);
1676 static int ravb_set_gti(struct net_device
*ndev
)
1679 struct device
*dev
= ndev
->dev
.parent
;
1680 struct device_node
*np
= dev
->of_node
;
1685 clk
= of_clk_get(np
, 0);
1687 dev_err(dev
, "could not get clock\n");
1688 return PTR_ERR(clk
);
1691 rate
= clk_get_rate(clk
);
1694 inc
= 1000000000ULL << 20;
1697 if (inc
< GTI_TIV_MIN
|| inc
> GTI_TIV_MAX
) {
1698 dev_err(dev
, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1699 inc
, GTI_TIV_MIN
, GTI_TIV_MAX
);
1703 ravb_write(ndev
, inc
, GTI
);
1708 static int ravb_probe(struct platform_device
*pdev
)
1710 struct device_node
*np
= pdev
->dev
.of_node
;
1711 struct ravb_private
*priv
;
1712 enum ravb_chip_id chip_id
;
1713 struct net_device
*ndev
;
1715 struct resource
*res
;
1719 "this driver is required to be instantiated from device tree\n");
1723 /* Get base address */
1724 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1726 dev_err(&pdev
->dev
, "invalid resource\n");
1730 ndev
= alloc_etherdev_mqs(sizeof(struct ravb_private
),
1731 NUM_TX_QUEUE
, NUM_RX_QUEUE
);
1735 pm_runtime_enable(&pdev
->dev
);
1736 pm_runtime_get_sync(&pdev
->dev
);
1738 /* The Ether-specific entries in the device structure. */
1739 ndev
->base_addr
= res
->start
;
1742 chip_id
= (enum ravb_chip_id
)of_device_get_match_data(&pdev
->dev
);
1744 if (chip_id
== RCAR_GEN3
)
1745 irq
= platform_get_irq_byname(pdev
, "ch22");
1747 irq
= platform_get_irq(pdev
, 0);
1754 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1756 priv
= netdev_priv(ndev
);
1759 priv
->num_tx_ring
[RAVB_BE
] = BE_TX_RING_SIZE
;
1760 priv
->num_rx_ring
[RAVB_BE
] = BE_RX_RING_SIZE
;
1761 priv
->num_tx_ring
[RAVB_NC
] = NC_TX_RING_SIZE
;
1762 priv
->num_rx_ring
[RAVB_NC
] = NC_RX_RING_SIZE
;
1763 priv
->addr
= devm_ioremap_resource(&pdev
->dev
, res
);
1764 if (IS_ERR(priv
->addr
)) {
1765 error
= PTR_ERR(priv
->addr
);
1769 spin_lock_init(&priv
->lock
);
1770 INIT_WORK(&priv
->work
, ravb_tx_timeout_work
);
1772 priv
->phy_interface
= of_get_phy_mode(np
);
1774 priv
->no_avb_link
= of_property_read_bool(np
, "renesas,no-ether-link");
1775 priv
->avb_link_active_low
=
1776 of_property_read_bool(np
, "renesas,ether-link-active-low");
1778 if (chip_id
== RCAR_GEN3
) {
1779 irq
= platform_get_irq_byname(pdev
, "ch24");
1784 priv
->emac_irq
= irq
;
1787 priv
->chip_id
= chip_id
;
1790 ndev
->netdev_ops
= &ravb_netdev_ops
;
1791 ndev
->ethtool_ops
= &ravb_ethtool_ops
;
1793 /* Set AVB config mode */
1794 if (chip_id
== RCAR_GEN2
) {
1795 ravb_modify(ndev
, CCC
, CCC_OPC
, CCC_OPC_CONFIG
);
1796 /* Set CSEL value */
1797 ravb_modify(ndev
, CCC
, CCC_CSEL
, CCC_CSEL_HPB
);
1799 ravb_modify(ndev
, CCC
, CCC_OPC
, CCC_OPC_CONFIG
|
1800 CCC_GAC
| CCC_CSEL_HPB
);
1804 error
= ravb_set_gti(ndev
);
1808 /* Request GTI loading */
1809 ravb_modify(ndev
, GCCR
, GCCR_LTI
, GCCR_LTI
);
1811 /* Allocate descriptor base address table */
1812 priv
->desc_bat_size
= sizeof(struct ravb_desc
) * DBAT_ENTRY_NUM
;
1813 priv
->desc_bat
= dma_alloc_coherent(ndev
->dev
.parent
, priv
->desc_bat_size
,
1814 &priv
->desc_bat_dma
, GFP_KERNEL
);
1815 if (!priv
->desc_bat
) {
1817 "Cannot allocate desc base address table (size %d bytes)\n",
1818 priv
->desc_bat_size
);
1822 for (q
= RAVB_BE
; q
< DBAT_ENTRY_NUM
; q
++)
1823 priv
->desc_bat
[q
].die_dt
= DT_EOS
;
1824 ravb_write(ndev
, priv
->desc_bat_dma
, DBAT
);
1826 /* Initialise HW timestamp list */
1827 INIT_LIST_HEAD(&priv
->ts_skb_list
);
1829 /* Initialise PTP Clock driver */
1830 if (chip_id
!= RCAR_GEN2
)
1831 ravb_ptp_init(ndev
, pdev
);
1833 /* Debug message level */
1834 priv
->msg_enable
= RAVB_DEF_MSG_ENABLE
;
1836 /* Read and set MAC address */
1837 ravb_read_mac_address(ndev
, of_get_mac_address(np
));
1838 if (!is_valid_ether_addr(ndev
->dev_addr
)) {
1839 dev_warn(&pdev
->dev
,
1840 "no valid MAC address supplied, using a random one\n");
1841 eth_hw_addr_random(ndev
);
1845 error
= ravb_mdio_init(priv
);
1847 dev_err(&pdev
->dev
, "failed to initialize MDIO\n");
1851 netif_napi_add(ndev
, &priv
->napi
[RAVB_BE
], ravb_poll
, 64);
1852 netif_napi_add(ndev
, &priv
->napi
[RAVB_NC
], ravb_poll
, 64);
1854 /* Network device register */
1855 error
= register_netdev(ndev
);
1859 /* Print device information */
1860 netdev_info(ndev
, "Base address at %#x, %pM, IRQ %d.\n",
1861 (u32
)ndev
->base_addr
, ndev
->dev_addr
, ndev
->irq
);
1863 platform_set_drvdata(pdev
, ndev
);
1868 netif_napi_del(&priv
->napi
[RAVB_NC
]);
1869 netif_napi_del(&priv
->napi
[RAVB_BE
]);
1870 ravb_mdio_release(priv
);
1872 dma_free_coherent(ndev
->dev
.parent
, priv
->desc_bat_size
, priv
->desc_bat
,
1873 priv
->desc_bat_dma
);
1875 /* Stop PTP Clock driver */
1876 if (chip_id
!= RCAR_GEN2
)
1877 ravb_ptp_stop(ndev
);
1882 pm_runtime_put(&pdev
->dev
);
1883 pm_runtime_disable(&pdev
->dev
);
1887 static int ravb_remove(struct platform_device
*pdev
)
1889 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1890 struct ravb_private
*priv
= netdev_priv(ndev
);
1892 /* Stop PTP Clock driver */
1893 if (priv
->chip_id
!= RCAR_GEN2
)
1894 ravb_ptp_stop(ndev
);
1896 dma_free_coherent(ndev
->dev
.parent
, priv
->desc_bat_size
, priv
->desc_bat
,
1897 priv
->desc_bat_dma
);
1898 /* Set reset mode */
1899 ravb_write(ndev
, CCC_OPC_RESET
, CCC
);
1900 pm_runtime_put_sync(&pdev
->dev
);
1901 unregister_netdev(ndev
);
1902 netif_napi_del(&priv
->napi
[RAVB_NC
]);
1903 netif_napi_del(&priv
->napi
[RAVB_BE
]);
1904 ravb_mdio_release(priv
);
1905 pm_runtime_disable(&pdev
->dev
);
1907 platform_set_drvdata(pdev
, NULL
);
1913 static int ravb_runtime_nop(struct device
*dev
)
1915 /* Runtime PM callback shared between ->runtime_suspend()
1916 * and ->runtime_resume(). Simply returns success.
1918 * This driver re-initializes all registers after
1919 * pm_runtime_get_sync() anyway so there is no need
1920 * to save and restore registers here.
1925 static const struct dev_pm_ops ravb_dev_pm_ops
= {
1926 .runtime_suspend
= ravb_runtime_nop
,
1927 .runtime_resume
= ravb_runtime_nop
,
1930 #define RAVB_PM_OPS (&ravb_dev_pm_ops)
1932 #define RAVB_PM_OPS NULL
1935 static struct platform_driver ravb_driver
= {
1936 .probe
= ravb_probe
,
1937 .remove
= ravb_remove
,
1941 .of_match_table
= ravb_match_table
,
1945 module_platform_driver(ravb_driver
);
1947 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
1948 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
1949 MODULE_LICENSE("GPL v2");