2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/spinlock.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/mdio-bitbang.h>
34 #include <linux/netdevice.h>
35 #include <linux/phy.h>
36 #include <linux/cache.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/slab.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/clk.h>
43 #include <linux/sh_eth.h>
47 #define SH_ETH_DEF_MSG_ENABLE \
53 static const u16 sh_eth_offset_gigabit
[SH_ETH_MAX_REGISTER_OFFSET
] = {
107 [TSU_CTRST
] = 0x0004,
108 [TSU_FWEN0
] = 0x0010,
109 [TSU_FWEN1
] = 0x0014,
111 [TSU_BSYSL0
] = 0x0020,
112 [TSU_BSYSL1
] = 0x0024,
113 [TSU_PRISL0
] = 0x0028,
114 [TSU_PRISL1
] = 0x002c,
115 [TSU_FWSL0
] = 0x0030,
116 [TSU_FWSL1
] = 0x0034,
117 [TSU_FWSLC
] = 0x0038,
118 [TSU_QTAG0
] = 0x0040,
119 [TSU_QTAG1
] = 0x0044,
121 [TSU_FWINMK
] = 0x0054,
122 [TSU_ADQT0
] = 0x0048,
123 [TSU_ADQT1
] = 0x004c,
124 [TSU_VTAG0
] = 0x0058,
125 [TSU_VTAG1
] = 0x005c,
126 [TSU_ADSBSY
] = 0x0060,
128 [TSU_POST1
] = 0x0070,
129 [TSU_POST2
] = 0x0074,
130 [TSU_POST3
] = 0x0078,
131 [TSU_POST4
] = 0x007c,
132 [TSU_ADRH0
] = 0x0100,
133 [TSU_ADRL0
] = 0x0104,
134 [TSU_ADRH31
] = 0x01f8,
135 [TSU_ADRL31
] = 0x01fc,
151 static const u16 sh_eth_offset_fast_rcar
[SH_ETH_MAX_REGISTER_OFFSET
] = {
196 static const u16 sh_eth_offset_fast_sh4
[SH_ETH_MAX_REGISTER_OFFSET
] = {
248 static const u16 sh_eth_offset_fast_sh3_sh2
[SH_ETH_MAX_REGISTER_OFFSET
] = {
274 [TSU_CTRST
] = 0x0004,
275 [TSU_FWEN0
] = 0x0010,
276 [TSU_FWEN1
] = 0x0014,
278 [TSU_BSYSL0
] = 0x0020,
279 [TSU_BSYSL1
] = 0x0024,
280 [TSU_PRISL0
] = 0x0028,
281 [TSU_PRISL1
] = 0x002c,
282 [TSU_FWSL0
] = 0x0030,
283 [TSU_FWSL1
] = 0x0034,
284 [TSU_FWSLC
] = 0x0038,
285 [TSU_QTAGM0
] = 0x0040,
286 [TSU_QTAGM1
] = 0x0044,
287 [TSU_ADQT0
] = 0x0048,
288 [TSU_ADQT1
] = 0x004c,
290 [TSU_FWINMK
] = 0x0054,
291 [TSU_ADSBSY
] = 0x0060,
293 [TSU_POST1
] = 0x0070,
294 [TSU_POST2
] = 0x0074,
295 [TSU_POST3
] = 0x0078,
296 [TSU_POST4
] = 0x007c,
311 [TSU_ADRH0
] = 0x0100,
312 [TSU_ADRL0
] = 0x0104,
313 [TSU_ADRL31
] = 0x01fc,
316 #if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
317 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
318 defined(CONFIG_ARCH_R8A7740)
319 static void sh_eth_select_mii(struct net_device
*ndev
)
322 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
324 switch (mdp
->phy_interface
) {
325 case PHY_INTERFACE_MODE_GMII
:
328 case PHY_INTERFACE_MODE_MII
:
331 case PHY_INTERFACE_MODE_RMII
:
335 pr_warn("PHY interface mode was not setup. Set to MII.\n");
340 sh_eth_write(ndev
, value
, RMII_MII
);
344 /* There is CPU dependent code */
345 #if defined(CONFIG_ARCH_R8A7779)
346 #define SH_ETH_RESET_DEFAULT 1
347 static void sh_eth_set_duplex(struct net_device
*ndev
)
349 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
351 if (mdp
->duplex
) /* Full */
352 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
354 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
357 static void sh_eth_set_rate(struct net_device
*ndev
)
359 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
361 switch (mdp
->speed
) {
362 case 10: /* 10BASE */
363 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_ELB
, ECMR
);
365 case 100:/* 100BASE */
366 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_ELB
, ECMR
);
374 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
375 .set_duplex
= sh_eth_set_duplex
,
376 .set_rate
= sh_eth_set_rate
,
378 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
379 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
380 .eesipr_value
= 0x01ff009f,
382 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
383 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
384 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
385 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
392 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
393 #define SH_ETH_RESET_DEFAULT 1
394 static void sh_eth_set_duplex(struct net_device
*ndev
)
396 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
398 if (mdp
->duplex
) /* Full */
399 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
401 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
404 static void sh_eth_set_rate(struct net_device
*ndev
)
406 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
408 switch (mdp
->speed
) {
409 case 10: /* 10BASE */
410 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_RTM
, ECMR
);
412 case 100:/* 100BASE */
413 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_RTM
, ECMR
);
421 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
422 .set_duplex
= sh_eth_set_duplex
,
423 .set_rate
= sh_eth_set_rate
,
425 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
426 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
427 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x01ff009f,
429 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
430 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
431 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
432 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
439 .rpadir_value
= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
441 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
442 #define SH_ETH_HAS_BOTH_MODULES 1
443 #define SH_ETH_HAS_TSU 1
444 static int sh_eth_check_reset(struct net_device
*ndev
);
446 static void sh_eth_set_duplex(struct net_device
*ndev
)
448 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
450 if (mdp
->duplex
) /* Full */
451 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
453 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
456 static void sh_eth_set_rate(struct net_device
*ndev
)
458 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
460 switch (mdp
->speed
) {
461 case 10: /* 10BASE */
462 sh_eth_write(ndev
, 0, RTRATE
);
464 case 100:/* 100BASE */
465 sh_eth_write(ndev
, 1, RTRATE
);
473 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
474 .set_duplex
= sh_eth_set_duplex
,
475 .set_rate
= sh_eth_set_rate
,
477 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
478 .rmcr_value
= 0x00000001,
480 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
481 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
482 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
483 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
491 .rpadir_value
= 2 << 16,
494 #define SH_GIGA_ETH_BASE 0xfee00000
495 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
496 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
497 static void sh_eth_chip_reset_giga(struct net_device
*ndev
)
500 unsigned long mahr
[2], malr
[2];
502 /* save MAHR and MALR */
503 for (i
= 0; i
< 2; i
++) {
504 malr
[i
] = ioread32((void *)GIGA_MALR(i
));
505 mahr
[i
] = ioread32((void *)GIGA_MAHR(i
));
509 iowrite32(ARSTR_ARSTR
, (void *)(SH_GIGA_ETH_BASE
+ 0x1800));
512 /* restore MAHR and MALR */
513 for (i
= 0; i
< 2; i
++) {
514 iowrite32(malr
[i
], (void *)GIGA_MALR(i
));
515 iowrite32(mahr
[i
], (void *)GIGA_MAHR(i
));
519 static int sh_eth_is_gether(struct sh_eth_private
*mdp
);
520 static int sh_eth_reset(struct net_device
*ndev
)
522 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
525 if (sh_eth_is_gether(mdp
)) {
526 sh_eth_write(ndev
, 0x03, EDSR
);
527 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
,
530 ret
= sh_eth_check_reset(ndev
);
535 sh_eth_write(ndev
, 0x0, TDLAR
);
536 sh_eth_write(ndev
, 0x0, TDFAR
);
537 sh_eth_write(ndev
, 0x0, TDFXR
);
538 sh_eth_write(ndev
, 0x0, TDFFR
);
539 sh_eth_write(ndev
, 0x0, RDLAR
);
540 sh_eth_write(ndev
, 0x0, RDFAR
);
541 sh_eth_write(ndev
, 0x0, RDFXR
);
542 sh_eth_write(ndev
, 0x0, RDFFR
);
544 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
,
547 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
,
555 static void sh_eth_set_duplex_giga(struct net_device
*ndev
)
557 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
559 if (mdp
->duplex
) /* Full */
560 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
562 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
565 static void sh_eth_set_rate_giga(struct net_device
*ndev
)
567 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
569 switch (mdp
->speed
) {
570 case 10: /* 10BASE */
571 sh_eth_write(ndev
, 0x00000000, GECMR
);
573 case 100:/* 100BASE */
574 sh_eth_write(ndev
, 0x00000010, GECMR
);
576 case 1000: /* 1000BASE */
577 sh_eth_write(ndev
, 0x00000020, GECMR
);
584 /* SH7757(GETHERC) */
585 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga
= {
586 .chip_reset
= sh_eth_chip_reset_giga
,
587 .set_duplex
= sh_eth_set_duplex_giga
,
588 .set_rate
= sh_eth_set_rate_giga
,
590 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
591 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
592 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
594 .tx_check
= EESR_TC1
| EESR_FTC
,
595 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
596 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
598 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
600 .fdr_value
= 0x0000072f,
601 .rmcr_value
= 0x00000001,
609 .rpadir_value
= 2 << 16,
615 static struct sh_eth_cpu_data
*sh_eth_get_cpu_data(struct sh_eth_private
*mdp
)
617 if (sh_eth_is_gether(mdp
))
618 return &sh_eth_my_cpu_data_giga
;
620 return &sh_eth_my_cpu_data
;
623 #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
624 #define SH_ETH_HAS_TSU 1
625 static int sh_eth_check_reset(struct net_device
*ndev
);
626 static void sh_eth_reset_hw_crc(struct net_device
*ndev
);
628 static void sh_eth_chip_reset(struct net_device
*ndev
)
630 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
633 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
637 static void sh_eth_set_duplex(struct net_device
*ndev
)
639 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
641 if (mdp
->duplex
) /* Full */
642 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
644 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
647 static void sh_eth_set_rate(struct net_device
*ndev
)
649 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
651 switch (mdp
->speed
) {
652 case 10: /* 10BASE */
653 sh_eth_write(ndev
, GECMR_10
, GECMR
);
655 case 100:/* 100BASE */
656 sh_eth_write(ndev
, GECMR_100
, GECMR
);
658 case 1000: /* 1000BASE */
659 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
667 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
668 .chip_reset
= sh_eth_chip_reset
,
669 .set_duplex
= sh_eth_set_duplex
,
670 .set_rate
= sh_eth_set_rate
,
672 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
673 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
674 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
676 .tx_check
= EESR_TC1
| EESR_FTC
,
677 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
678 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
680 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
691 #if defined(CONFIG_CPU_SUBTYPE_SH7734)
697 static int sh_eth_reset(struct net_device
*ndev
)
701 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
702 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
, EDMR
);
704 ret
= sh_eth_check_reset(ndev
);
709 sh_eth_write(ndev
, 0x0, TDLAR
);
710 sh_eth_write(ndev
, 0x0, TDFAR
);
711 sh_eth_write(ndev
, 0x0, TDFXR
);
712 sh_eth_write(ndev
, 0x0, TDFFR
);
713 sh_eth_write(ndev
, 0x0, RDLAR
);
714 sh_eth_write(ndev
, 0x0, RDFAR
);
715 sh_eth_write(ndev
, 0x0, RDFXR
);
716 sh_eth_write(ndev
, 0x0, RDFFR
);
718 /* Reset HW CRC register */
719 sh_eth_reset_hw_crc(ndev
);
721 /* Select MII mode */
722 if (sh_eth_my_cpu_data
.select_mii
)
723 sh_eth_select_mii(ndev
);
728 static void sh_eth_reset_hw_crc(struct net_device
*ndev
)
730 if (sh_eth_my_cpu_data
.hw_crc
)
731 sh_eth_write(ndev
, 0x0, CSMR
);
734 #elif defined(CONFIG_ARCH_R8A7740)
735 #define SH_ETH_HAS_TSU 1
736 static int sh_eth_check_reset(struct net_device
*ndev
);
738 static void sh_eth_chip_reset(struct net_device
*ndev
)
740 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
743 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
746 sh_eth_select_mii(ndev
);
749 static int sh_eth_reset(struct net_device
*ndev
)
753 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
754 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
, EDMR
);
756 ret
= sh_eth_check_reset(ndev
);
761 sh_eth_write(ndev
, 0x0, TDLAR
);
762 sh_eth_write(ndev
, 0x0, TDFAR
);
763 sh_eth_write(ndev
, 0x0, TDFXR
);
764 sh_eth_write(ndev
, 0x0, TDFFR
);
765 sh_eth_write(ndev
, 0x0, RDLAR
);
766 sh_eth_write(ndev
, 0x0, RDFAR
);
767 sh_eth_write(ndev
, 0x0, RDFXR
);
768 sh_eth_write(ndev
, 0x0, RDFFR
);
774 static void sh_eth_set_duplex(struct net_device
*ndev
)
776 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
778 if (mdp
->duplex
) /* Full */
779 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
781 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
784 static void sh_eth_set_rate(struct net_device
*ndev
)
786 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
788 switch (mdp
->speed
) {
789 case 10: /* 10BASE */
790 sh_eth_write(ndev
, GECMR_10
, GECMR
);
792 case 100:/* 100BASE */
793 sh_eth_write(ndev
, GECMR_100
, GECMR
);
795 case 1000: /* 1000BASE */
796 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
804 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
805 .chip_reset
= sh_eth_chip_reset
,
806 .set_duplex
= sh_eth_set_duplex
,
807 .set_rate
= sh_eth_set_rate
,
809 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
810 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
811 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
813 .tx_check
= EESR_TC1
| EESR_FTC
,
814 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
815 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
817 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
831 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
832 #define SH_ETH_RESET_DEFAULT 1
833 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
834 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
841 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
842 #define SH_ETH_RESET_DEFAULT 1
843 #define SH_ETH_HAS_TSU 1
844 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
845 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
850 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data
*cd
)
853 cd
->ecsr_value
= DEFAULT_ECSR_INIT
;
855 if (!cd
->ecsipr_value
)
856 cd
->ecsipr_value
= DEFAULT_ECSIPR_INIT
;
858 if (!cd
->fcftr_value
)
859 cd
->fcftr_value
= DEFAULT_FIFO_F_D_RFF
| \
860 DEFAULT_FIFO_F_D_RFD
;
863 cd
->fdr_value
= DEFAULT_FDR_INIT
;
866 cd
->rmcr_value
= DEFAULT_RMCR_VALUE
;
869 cd
->tx_check
= DEFAULT_TX_CHECK
;
871 if (!cd
->eesr_err_check
)
872 cd
->eesr_err_check
= DEFAULT_EESR_ERR_CHECK
;
874 if (!cd
->tx_error_check
)
875 cd
->tx_error_check
= DEFAULT_TX_ERROR_CHECK
;
878 #if defined(SH_ETH_RESET_DEFAULT)
880 static int sh_eth_reset(struct net_device
*ndev
)
882 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
, EDMR
);
884 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
, EDMR
);
889 static int sh_eth_check_reset(struct net_device
*ndev
)
895 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
901 pr_err("Device reset fail\n");
908 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
909 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
913 reserve
= SH4_SKB_RX_ALIGN
- ((u32
)skb
->data
& (SH4_SKB_RX_ALIGN
- 1));
915 skb_reserve(skb
, reserve
);
918 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
920 skb_reserve(skb
, SH2_SH3_SKB_RX_ALIGN
);
925 /* CPU <-> EDMAC endian convert */
926 static inline __u32
cpu_to_edmac(struct sh_eth_private
*mdp
, u32 x
)
928 switch (mdp
->edmac_endian
) {
929 case EDMAC_LITTLE_ENDIAN
:
930 return cpu_to_le32(x
);
931 case EDMAC_BIG_ENDIAN
:
932 return cpu_to_be32(x
);
937 static inline __u32
edmac_to_cpu(struct sh_eth_private
*mdp
, u32 x
)
939 switch (mdp
->edmac_endian
) {
940 case EDMAC_LITTLE_ENDIAN
:
941 return le32_to_cpu(x
);
942 case EDMAC_BIG_ENDIAN
:
943 return be32_to_cpu(x
);
949 * Program the hardware MAC address from dev->dev_addr.
951 static void update_mac_address(struct net_device
*ndev
)
954 (ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
955 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]), MAHR
);
957 (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]), MALR
);
961 * Get MAC address from SuperH MAC address register
963 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
964 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
965 * When you want use this device, you must set MAC address in bootloader.
968 static void read_mac_address(struct net_device
*ndev
, unsigned char *mac
)
970 if (mac
[0] || mac
[1] || mac
[2] || mac
[3] || mac
[4] || mac
[5]) {
971 memcpy(ndev
->dev_addr
, mac
, 6);
973 ndev
->dev_addr
[0] = (sh_eth_read(ndev
, MAHR
) >> 24);
974 ndev
->dev_addr
[1] = (sh_eth_read(ndev
, MAHR
) >> 16) & 0xFF;
975 ndev
->dev_addr
[2] = (sh_eth_read(ndev
, MAHR
) >> 8) & 0xFF;
976 ndev
->dev_addr
[3] = (sh_eth_read(ndev
, MAHR
) & 0xFF);
977 ndev
->dev_addr
[4] = (sh_eth_read(ndev
, MALR
) >> 8) & 0xFF;
978 ndev
->dev_addr
[5] = (sh_eth_read(ndev
, MALR
) & 0xFF);
982 static int sh_eth_is_gether(struct sh_eth_private
*mdp
)
984 if (mdp
->reg_offset
== sh_eth_offset_gigabit
)
990 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private
*mdp
)
992 if (sh_eth_is_gether(mdp
))
993 return EDTRR_TRNS_GETHER
;
995 return EDTRR_TRNS_ETHER
;
999 void (*set_gate
)(void *addr
);
1000 struct mdiobb_ctrl ctrl
;
1002 u32 mmd_msk
;/* MMD */
1009 static void bb_set(void *addr
, u32 msk
)
1011 iowrite32(ioread32(addr
) | msk
, addr
);
1015 static void bb_clr(void *addr
, u32 msk
)
1017 iowrite32((ioread32(addr
) & ~msk
), addr
);
1021 static int bb_read(void *addr
, u32 msk
)
1023 return (ioread32(addr
) & msk
) != 0;
1026 /* Data I/O pin control */
1027 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
1029 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1031 if (bitbang
->set_gate
)
1032 bitbang
->set_gate(bitbang
->addr
);
1035 bb_set(bitbang
->addr
, bitbang
->mmd_msk
);
1037 bb_clr(bitbang
->addr
, bitbang
->mmd_msk
);
1041 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
1043 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1045 if (bitbang
->set_gate
)
1046 bitbang
->set_gate(bitbang
->addr
);
1049 bb_set(bitbang
->addr
, bitbang
->mdo_msk
);
1051 bb_clr(bitbang
->addr
, bitbang
->mdo_msk
);
1055 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
1057 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1059 if (bitbang
->set_gate
)
1060 bitbang
->set_gate(bitbang
->addr
);
1062 return bb_read(bitbang
->addr
, bitbang
->mdi_msk
);
1065 /* MDC pin control */
1066 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
1068 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1070 if (bitbang
->set_gate
)
1071 bitbang
->set_gate(bitbang
->addr
);
1074 bb_set(bitbang
->addr
, bitbang
->mdc_msk
);
1076 bb_clr(bitbang
->addr
, bitbang
->mdc_msk
);
1079 /* mdio bus control struct */
1080 static struct mdiobb_ops bb_ops
= {
1081 .owner
= THIS_MODULE
,
1082 .set_mdc
= sh_mdc_ctrl
,
1083 .set_mdio_dir
= sh_mmd_ctrl
,
1084 .set_mdio_data
= sh_set_mdio
,
1085 .get_mdio_data
= sh_get_mdio
,
1088 /* free skb and descriptor buffer */
1089 static void sh_eth_ring_free(struct net_device
*ndev
)
1091 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1094 /* Free Rx skb ringbuffer */
1095 if (mdp
->rx_skbuff
) {
1096 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
1097 if (mdp
->rx_skbuff
[i
])
1098 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
1101 kfree(mdp
->rx_skbuff
);
1102 mdp
->rx_skbuff
= NULL
;
1104 /* Free Tx skb ringbuffer */
1105 if (mdp
->tx_skbuff
) {
1106 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
1107 if (mdp
->tx_skbuff
[i
])
1108 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
1111 kfree(mdp
->tx_skbuff
);
1112 mdp
->tx_skbuff
= NULL
;
1115 /* format skb and descriptor buffer */
1116 static void sh_eth_ring_format(struct net_device
*ndev
)
1118 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1120 struct sk_buff
*skb
;
1121 struct sh_eth_rxdesc
*rxdesc
= NULL
;
1122 struct sh_eth_txdesc
*txdesc
= NULL
;
1123 int rx_ringsize
= sizeof(*rxdesc
) * mdp
->num_rx_ring
;
1124 int tx_ringsize
= sizeof(*txdesc
) * mdp
->num_tx_ring
;
1126 mdp
->cur_rx
= mdp
->cur_tx
= 0;
1127 mdp
->dirty_rx
= mdp
->dirty_tx
= 0;
1129 memset(mdp
->rx_ring
, 0, rx_ringsize
);
1131 /* build Rx ring buffer */
1132 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
1134 mdp
->rx_skbuff
[i
] = NULL
;
1135 skb
= netdev_alloc_skb(ndev
, mdp
->rx_buf_sz
);
1136 mdp
->rx_skbuff
[i
] = skb
;
1139 dma_map_single(&ndev
->dev
, skb
->data
, mdp
->rx_buf_sz
,
1141 sh_eth_set_receive_align(skb
);
1144 rxdesc
= &mdp
->rx_ring
[i
];
1145 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
1146 rxdesc
->status
= cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
1148 /* The size of the buffer is 16 byte boundary. */
1149 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
1150 /* Rx descriptor address set */
1152 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDLAR
);
1153 if (sh_eth_is_gether(mdp
))
1154 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDFAR
);
1158 mdp
->dirty_rx
= (u32
) (i
- mdp
->num_rx_ring
);
1160 /* Mark the last entry as wrapping the ring. */
1161 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RDEL
);
1163 memset(mdp
->tx_ring
, 0, tx_ringsize
);
1165 /* build Tx ring buffer */
1166 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
1167 mdp
->tx_skbuff
[i
] = NULL
;
1168 txdesc
= &mdp
->tx_ring
[i
];
1169 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
1170 txdesc
->buffer_length
= 0;
1172 /* Tx descriptor address set */
1173 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDLAR
);
1174 if (sh_eth_is_gether(mdp
))
1175 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDFAR
);
1179 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
1182 /* Get skb and descriptor buffer */
1183 static int sh_eth_ring_init(struct net_device
*ndev
)
1185 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1186 int rx_ringsize
, tx_ringsize
, ret
= 0;
1189 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1190 * card needs room to do 8 byte alignment, +2 so we can reserve
1191 * the first 2 bytes, and +16 gets room for the status word from the
1194 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
1195 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
1196 if (mdp
->cd
->rpadir
)
1197 mdp
->rx_buf_sz
+= NET_IP_ALIGN
;
1199 /* Allocate RX and TX skb rings */
1200 mdp
->rx_skbuff
= kmalloc_array(mdp
->num_rx_ring
,
1201 sizeof(*mdp
->rx_skbuff
), GFP_KERNEL
);
1202 if (!mdp
->rx_skbuff
) {
1207 mdp
->tx_skbuff
= kmalloc_array(mdp
->num_tx_ring
,
1208 sizeof(*mdp
->tx_skbuff
), GFP_KERNEL
);
1209 if (!mdp
->tx_skbuff
) {
1214 /* Allocate all Rx descriptors. */
1215 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * mdp
->num_rx_ring
;
1216 mdp
->rx_ring
= dma_alloc_coherent(NULL
, rx_ringsize
, &mdp
->rx_desc_dma
,
1218 if (!mdp
->rx_ring
) {
1220 goto desc_ring_free
;
1225 /* Allocate all Tx descriptors. */
1226 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * mdp
->num_tx_ring
;
1227 mdp
->tx_ring
= dma_alloc_coherent(NULL
, tx_ringsize
, &mdp
->tx_desc_dma
,
1229 if (!mdp
->tx_ring
) {
1231 goto desc_ring_free
;
1236 /* free DMA buffer */
1237 dma_free_coherent(NULL
, rx_ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
1240 /* Free Rx and Tx skb ring buffer */
1241 sh_eth_ring_free(ndev
);
1242 mdp
->tx_ring
= NULL
;
1243 mdp
->rx_ring
= NULL
;
1248 static void sh_eth_free_dma_buffer(struct sh_eth_private
*mdp
)
1253 ringsize
= sizeof(struct sh_eth_rxdesc
) * mdp
->num_rx_ring
;
1254 dma_free_coherent(NULL
, ringsize
, mdp
->rx_ring
,
1256 mdp
->rx_ring
= NULL
;
1260 ringsize
= sizeof(struct sh_eth_txdesc
) * mdp
->num_tx_ring
;
1261 dma_free_coherent(NULL
, ringsize
, mdp
->tx_ring
,
1263 mdp
->tx_ring
= NULL
;
1267 static int sh_eth_dev_init(struct net_device
*ndev
, bool start
)
1270 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1274 ret
= sh_eth_reset(ndev
);
1278 /* Descriptor format */
1279 sh_eth_ring_format(ndev
);
1280 if (mdp
->cd
->rpadir
)
1281 sh_eth_write(ndev
, mdp
->cd
->rpadir_value
, RPADIR
);
1283 /* all sh_eth int mask */
1284 sh_eth_write(ndev
, 0, EESIPR
);
1286 #if defined(__LITTLE_ENDIAN)
1287 if (mdp
->cd
->hw_swap
)
1288 sh_eth_write(ndev
, EDMR_EL
, EDMR
);
1291 sh_eth_write(ndev
, 0, EDMR
);
1294 sh_eth_write(ndev
, mdp
->cd
->fdr_value
, FDR
);
1295 sh_eth_write(ndev
, 0, TFTR
);
1297 /* Frame recv control */
1298 sh_eth_write(ndev
, mdp
->cd
->rmcr_value
, RMCR
);
1300 sh_eth_write(ndev
, DESC_I_RINT8
| DESC_I_RINT5
| DESC_I_TINT2
, TRSCER
);
1303 sh_eth_write(ndev
, 0x800, BCULR
); /* Burst sycle set */
1305 sh_eth_write(ndev
, mdp
->cd
->fcftr_value
, FCFTR
);
1307 if (!mdp
->cd
->no_trimd
)
1308 sh_eth_write(ndev
, 0, TRIMD
);
1310 /* Recv frame limit set register */
1311 sh_eth_write(ndev
, ndev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
+ ETH_FCS_LEN
,
1314 sh_eth_write(ndev
, sh_eth_read(ndev
, EESR
), EESR
);
1316 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1318 /* PAUSE Prohibition */
1319 val
= (sh_eth_read(ndev
, ECMR
) & ECMR_DM
) |
1320 ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) | ECMR_TE
| ECMR_RE
;
1322 sh_eth_write(ndev
, val
, ECMR
);
1324 if (mdp
->cd
->set_rate
)
1325 mdp
->cd
->set_rate(ndev
);
1327 /* E-MAC Status Register clear */
1328 sh_eth_write(ndev
, mdp
->cd
->ecsr_value
, ECSR
);
1330 /* E-MAC Interrupt Enable register */
1332 sh_eth_write(ndev
, mdp
->cd
->ecsipr_value
, ECSIPR
);
1334 /* Set MAC address */
1335 update_mac_address(ndev
);
1339 sh_eth_write(ndev
, APR_AP
, APR
);
1341 sh_eth_write(ndev
, MPR_MP
, MPR
);
1342 if (mdp
->cd
->tpauser
)
1343 sh_eth_write(ndev
, TPAUSER_UNLIMITED
, TPAUSER
);
1346 /* Setting the Rx mode will start the Rx process. */
1347 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1349 netif_start_queue(ndev
);
1356 /* free Tx skb function */
1357 static int sh_eth_txfree(struct net_device
*ndev
)
1359 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1360 struct sh_eth_txdesc
*txdesc
;
1364 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
1365 entry
= mdp
->dirty_tx
% mdp
->num_tx_ring
;
1366 txdesc
= &mdp
->tx_ring
[entry
];
1367 if (txdesc
->status
& cpu_to_edmac(mdp
, TD_TACT
))
1369 /* Free the original skb. */
1370 if (mdp
->tx_skbuff
[entry
]) {
1371 dma_unmap_single(&ndev
->dev
, txdesc
->addr
,
1372 txdesc
->buffer_length
, DMA_TO_DEVICE
);
1373 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
1374 mdp
->tx_skbuff
[entry
] = NULL
;
1377 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
1378 if (entry
>= mdp
->num_tx_ring
- 1)
1379 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
1381 ndev
->stats
.tx_packets
++;
1382 ndev
->stats
.tx_bytes
+= txdesc
->buffer_length
;
1387 /* Packet receive function */
1388 static int sh_eth_rx(struct net_device
*ndev
, u32 intr_status
)
1390 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1391 struct sh_eth_rxdesc
*rxdesc
;
1393 int entry
= mdp
->cur_rx
% mdp
->num_rx_ring
;
1394 int boguscnt
= (mdp
->dirty_rx
+ mdp
->num_rx_ring
) - mdp
->cur_rx
;
1395 struct sk_buff
*skb
;
1399 rxdesc
= &mdp
->rx_ring
[entry
];
1400 while (!(rxdesc
->status
& cpu_to_edmac(mdp
, RD_RACT
))) {
1401 desc_status
= edmac_to_cpu(mdp
, rxdesc
->status
);
1402 pkt_len
= rxdesc
->frame_length
;
1404 #if defined(CONFIG_ARCH_R8A7740)
1411 if (!(desc_status
& RDFEND
))
1412 ndev
->stats
.rx_length_errors
++;
1414 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
1415 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
1416 ndev
->stats
.rx_errors
++;
1417 if (desc_status
& RD_RFS1
)
1418 ndev
->stats
.rx_crc_errors
++;
1419 if (desc_status
& RD_RFS2
)
1420 ndev
->stats
.rx_frame_errors
++;
1421 if (desc_status
& RD_RFS3
)
1422 ndev
->stats
.rx_length_errors
++;
1423 if (desc_status
& RD_RFS4
)
1424 ndev
->stats
.rx_length_errors
++;
1425 if (desc_status
& RD_RFS6
)
1426 ndev
->stats
.rx_missed_errors
++;
1427 if (desc_status
& RD_RFS10
)
1428 ndev
->stats
.rx_over_errors
++;
1430 if (!mdp
->cd
->hw_swap
)
1432 phys_to_virt(ALIGN(rxdesc
->addr
, 4)),
1434 skb
= mdp
->rx_skbuff
[entry
];
1435 mdp
->rx_skbuff
[entry
] = NULL
;
1436 if (mdp
->cd
->rpadir
)
1437 skb_reserve(skb
, NET_IP_ALIGN
);
1438 skb_put(skb
, pkt_len
);
1439 skb
->protocol
= eth_type_trans(skb
, ndev
);
1441 ndev
->stats
.rx_packets
++;
1442 ndev
->stats
.rx_bytes
+= pkt_len
;
1444 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RACT
);
1445 entry
= (++mdp
->cur_rx
) % mdp
->num_rx_ring
;
1446 rxdesc
= &mdp
->rx_ring
[entry
];
1449 /* Refill the Rx ring buffers. */
1450 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
1451 entry
= mdp
->dirty_rx
% mdp
->num_rx_ring
;
1452 rxdesc
= &mdp
->rx_ring
[entry
];
1453 /* The size of the buffer is 16 byte boundary. */
1454 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
1456 if (mdp
->rx_skbuff
[entry
] == NULL
) {
1457 skb
= netdev_alloc_skb(ndev
, mdp
->rx_buf_sz
);
1458 mdp
->rx_skbuff
[entry
] = skb
;
1460 break; /* Better luck next round. */
1461 dma_map_single(&ndev
->dev
, skb
->data
, mdp
->rx_buf_sz
,
1463 sh_eth_set_receive_align(skb
);
1465 skb_checksum_none_assert(skb
);
1466 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
1468 if (entry
>= mdp
->num_rx_ring
- 1)
1470 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
| RD_RDEL
);
1473 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
1476 /* Restart Rx engine if stopped. */
1477 /* If we don't need to check status, don't. -KDU */
1478 if (!(sh_eth_read(ndev
, EDRRR
) & EDRRR_R
)) {
1479 /* fix the values for the next receiving if RDE is set */
1480 if (intr_status
& EESR_RDE
)
1481 mdp
->cur_rx
= mdp
->dirty_rx
=
1482 (sh_eth_read(ndev
, RDFAR
) -
1483 sh_eth_read(ndev
, RDLAR
)) >> 4;
1484 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1490 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
)
1492 /* disable tx and rx */
1493 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) &
1494 ~(ECMR_RE
| ECMR_TE
), ECMR
);
1497 static void sh_eth_rcv_snd_enable(struct net_device
*ndev
)
1499 /* enable tx and rx */
1500 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) |
1501 (ECMR_RE
| ECMR_TE
), ECMR
);
1504 /* error control function */
1505 static void sh_eth_error(struct net_device
*ndev
, int intr_status
)
1507 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1512 if (intr_status
& EESR_ECI
) {
1513 felic_stat
= sh_eth_read(ndev
, ECSR
);
1514 sh_eth_write(ndev
, felic_stat
, ECSR
); /* clear int */
1515 if (felic_stat
& ECSR_ICD
)
1516 ndev
->stats
.tx_carrier_errors
++;
1517 if (felic_stat
& ECSR_LCHNG
) {
1519 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
) {
1522 link_stat
= (sh_eth_read(ndev
, PSR
));
1523 if (mdp
->ether_link_active_low
)
1524 link_stat
= ~link_stat
;
1526 if (!(link_stat
& PHY_ST_LINK
))
1527 sh_eth_rcv_snd_disable(ndev
);
1530 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) &
1531 ~DMAC_M_ECI
, EESIPR
);
1533 sh_eth_write(ndev
, sh_eth_read(ndev
, ECSR
),
1535 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) |
1536 DMAC_M_ECI
, EESIPR
);
1537 /* enable tx and rx */
1538 sh_eth_rcv_snd_enable(ndev
);
1544 if (intr_status
& EESR_TWB
) {
1545 /* Write buck end. unused write back interrupt */
1546 if (intr_status
& EESR_TABT
) /* Transmit Abort int */
1547 ndev
->stats
.tx_aborted_errors
++;
1548 if (netif_msg_tx_err(mdp
))
1549 dev_err(&ndev
->dev
, "Transmit Abort\n");
1552 if (intr_status
& EESR_RABT
) {
1553 /* Receive Abort int */
1554 if (intr_status
& EESR_RFRMER
) {
1555 /* Receive Frame Overflow int */
1556 ndev
->stats
.rx_frame_errors
++;
1557 if (netif_msg_rx_err(mdp
))
1558 dev_err(&ndev
->dev
, "Receive Abort\n");
1562 if (intr_status
& EESR_TDE
) {
1563 /* Transmit Descriptor Empty int */
1564 ndev
->stats
.tx_fifo_errors
++;
1565 if (netif_msg_tx_err(mdp
))
1566 dev_err(&ndev
->dev
, "Transmit Descriptor Empty\n");
1569 if (intr_status
& EESR_TFE
) {
1570 /* FIFO under flow */
1571 ndev
->stats
.tx_fifo_errors
++;
1572 if (netif_msg_tx_err(mdp
))
1573 dev_err(&ndev
->dev
, "Transmit FIFO Under flow\n");
1576 if (intr_status
& EESR_RDE
) {
1577 /* Receive Descriptor Empty int */
1578 ndev
->stats
.rx_over_errors
++;
1580 if (netif_msg_rx_err(mdp
))
1581 dev_err(&ndev
->dev
, "Receive Descriptor Empty\n");
1584 if (intr_status
& EESR_RFE
) {
1585 /* Receive FIFO Overflow int */
1586 ndev
->stats
.rx_fifo_errors
++;
1587 if (netif_msg_rx_err(mdp
))
1588 dev_err(&ndev
->dev
, "Receive FIFO Overflow\n");
1591 if (!mdp
->cd
->no_ade
&& (intr_status
& EESR_ADE
)) {
1593 ndev
->stats
.tx_fifo_errors
++;
1594 if (netif_msg_tx_err(mdp
))
1595 dev_err(&ndev
->dev
, "Address Error\n");
1598 mask
= EESR_TWB
| EESR_TABT
| EESR_ADE
| EESR_TDE
| EESR_TFE
;
1599 if (mdp
->cd
->no_ade
)
1601 if (intr_status
& mask
) {
1603 u32 edtrr
= sh_eth_read(ndev
, EDTRR
);
1605 dev_err(&ndev
->dev
, "TX error. status=%8.8x cur_tx=%8.8x ",
1606 intr_status
, mdp
->cur_tx
);
1607 dev_err(&ndev
->dev
, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1608 mdp
->dirty_tx
, (u32
) ndev
->state
, edtrr
);
1609 /* dirty buffer free */
1610 sh_eth_txfree(ndev
);
1613 if (edtrr
^ sh_eth_get_edtrr_trns(mdp
)) {
1615 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1618 netif_wake_queue(ndev
);
1622 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
1624 struct net_device
*ndev
= netdev
;
1625 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1626 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
1627 irqreturn_t ret
= IRQ_NONE
;
1628 unsigned long intr_status
;
1630 spin_lock(&mdp
->lock
);
1632 /* Get interrupt status */
1633 intr_status
= sh_eth_read(ndev
, EESR
);
1634 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1635 * enabled since it's the one that comes thru regardless of the mask,
1636 * and we need to fully handle it in sh_eth_error() in order to quench
1637 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1639 intr_status
&= sh_eth_read(ndev
, EESIPR
) | DMAC_M_ECI
;
1640 /* Clear interrupt */
1641 if (intr_status
& (EESR_FRC
| EESR_RMAF
| EESR_RRF
|
1642 EESR_RTLF
| EESR_RTSF
| EESR_PRE
| EESR_CERF
|
1643 cd
->tx_check
| cd
->eesr_err_check
)) {
1644 sh_eth_write(ndev
, intr_status
, EESR
);
1649 if (intr_status
& (EESR_FRC
| /* Frame recv*/
1650 EESR_RMAF
| /* Multi cast address recv*/
1651 EESR_RRF
| /* Bit frame recv */
1652 EESR_RTLF
| /* Long frame recv*/
1653 EESR_RTSF
| /* short frame recv */
1654 EESR_PRE
| /* PHY-LSI recv error */
1655 EESR_CERF
)){ /* recv frame CRC error */
1656 sh_eth_rx(ndev
, intr_status
);
1660 if (intr_status
& cd
->tx_check
) {
1661 sh_eth_txfree(ndev
);
1662 netif_wake_queue(ndev
);
1665 if (intr_status
& cd
->eesr_err_check
)
1666 sh_eth_error(ndev
, intr_status
);
1669 spin_unlock(&mdp
->lock
);
1674 /* PHY state control function */
1675 static void sh_eth_adjust_link(struct net_device
*ndev
)
1677 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1678 struct phy_device
*phydev
= mdp
->phydev
;
1682 if (phydev
->duplex
!= mdp
->duplex
) {
1684 mdp
->duplex
= phydev
->duplex
;
1685 if (mdp
->cd
->set_duplex
)
1686 mdp
->cd
->set_duplex(ndev
);
1689 if (phydev
->speed
!= mdp
->speed
) {
1691 mdp
->speed
= phydev
->speed
;
1692 if (mdp
->cd
->set_rate
)
1693 mdp
->cd
->set_rate(ndev
);
1697 (sh_eth_read(ndev
, ECMR
) & ~ECMR_TXF
), ECMR
);
1699 mdp
->link
= phydev
->link
;
1700 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1701 sh_eth_rcv_snd_enable(ndev
);
1703 } else if (mdp
->link
) {
1708 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1709 sh_eth_rcv_snd_disable(ndev
);
1712 if (new_state
&& netif_msg_link(mdp
))
1713 phy_print_status(phydev
);
1716 /* PHY init function */
1717 static int sh_eth_phy_init(struct net_device
*ndev
)
1719 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1720 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1721 struct phy_device
*phydev
= NULL
;
1723 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
,
1724 mdp
->mii_bus
->id
, mdp
->phy_id
);
1730 /* Try connect to PHY */
1731 phydev
= phy_connect(ndev
, phy_id
, sh_eth_adjust_link
,
1732 mdp
->phy_interface
);
1733 if (IS_ERR(phydev
)) {
1734 dev_err(&ndev
->dev
, "phy_connect failed\n");
1735 return PTR_ERR(phydev
);
1738 dev_info(&ndev
->dev
, "attached phy %i to driver %s\n",
1739 phydev
->addr
, phydev
->drv
->name
);
1741 mdp
->phydev
= phydev
;
1746 /* PHY control start function */
1747 static int sh_eth_phy_start(struct net_device
*ndev
)
1749 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1752 ret
= sh_eth_phy_init(ndev
);
1756 /* reset phy - this also wakes it from PDOWN */
1757 phy_write(mdp
->phydev
, MII_BMCR
, BMCR_RESET
);
1758 phy_start(mdp
->phydev
);
1763 static int sh_eth_get_settings(struct net_device
*ndev
,
1764 struct ethtool_cmd
*ecmd
)
1766 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1767 unsigned long flags
;
1770 spin_lock_irqsave(&mdp
->lock
, flags
);
1771 ret
= phy_ethtool_gset(mdp
->phydev
, ecmd
);
1772 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1777 static int sh_eth_set_settings(struct net_device
*ndev
,
1778 struct ethtool_cmd
*ecmd
)
1780 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1781 unsigned long flags
;
1784 spin_lock_irqsave(&mdp
->lock
, flags
);
1786 /* disable tx and rx */
1787 sh_eth_rcv_snd_disable(ndev
);
1789 ret
= phy_ethtool_sset(mdp
->phydev
, ecmd
);
1793 if (ecmd
->duplex
== DUPLEX_FULL
)
1798 if (mdp
->cd
->set_duplex
)
1799 mdp
->cd
->set_duplex(ndev
);
1804 /* enable tx and rx */
1805 sh_eth_rcv_snd_enable(ndev
);
1807 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1812 static int sh_eth_nway_reset(struct net_device
*ndev
)
1814 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1815 unsigned long flags
;
1818 spin_lock_irqsave(&mdp
->lock
, flags
);
1819 ret
= phy_start_aneg(mdp
->phydev
);
1820 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1825 static u32
sh_eth_get_msglevel(struct net_device
*ndev
)
1827 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1828 return mdp
->msg_enable
;
1831 static void sh_eth_set_msglevel(struct net_device
*ndev
, u32 value
)
1833 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1834 mdp
->msg_enable
= value
;
1837 static const char sh_eth_gstrings_stats
[][ETH_GSTRING_LEN
] = {
1838 "rx_current", "tx_current",
1839 "rx_dirty", "tx_dirty",
1841 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1843 static int sh_eth_get_sset_count(struct net_device
*netdev
, int sset
)
1847 return SH_ETH_STATS_LEN
;
1853 static void sh_eth_get_ethtool_stats(struct net_device
*ndev
,
1854 struct ethtool_stats
*stats
, u64
*data
)
1856 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1859 /* device-specific stats */
1860 data
[i
++] = mdp
->cur_rx
;
1861 data
[i
++] = mdp
->cur_tx
;
1862 data
[i
++] = mdp
->dirty_rx
;
1863 data
[i
++] = mdp
->dirty_tx
;
1866 static void sh_eth_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1868 switch (stringset
) {
1870 memcpy(data
, *sh_eth_gstrings_stats
,
1871 sizeof(sh_eth_gstrings_stats
));
1876 static void sh_eth_get_ringparam(struct net_device
*ndev
,
1877 struct ethtool_ringparam
*ring
)
1879 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1881 ring
->rx_max_pending
= RX_RING_MAX
;
1882 ring
->tx_max_pending
= TX_RING_MAX
;
1883 ring
->rx_pending
= mdp
->num_rx_ring
;
1884 ring
->tx_pending
= mdp
->num_tx_ring
;
1887 static int sh_eth_set_ringparam(struct net_device
*ndev
,
1888 struct ethtool_ringparam
*ring
)
1890 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1893 if (ring
->tx_pending
> TX_RING_MAX
||
1894 ring
->rx_pending
> RX_RING_MAX
||
1895 ring
->tx_pending
< TX_RING_MIN
||
1896 ring
->rx_pending
< RX_RING_MIN
)
1898 if (ring
->rx_mini_pending
|| ring
->rx_jumbo_pending
)
1901 if (netif_running(ndev
)) {
1902 netif_tx_disable(ndev
);
1903 /* Disable interrupts by clearing the interrupt mask. */
1904 sh_eth_write(ndev
, 0x0000, EESIPR
);
1905 /* Stop the chip's Tx and Rx processes. */
1906 sh_eth_write(ndev
, 0, EDTRR
);
1907 sh_eth_write(ndev
, 0, EDRRR
);
1908 synchronize_irq(ndev
->irq
);
1911 /* Free all the skbuffs in the Rx queue. */
1912 sh_eth_ring_free(ndev
);
1913 /* Free DMA buffer */
1914 sh_eth_free_dma_buffer(mdp
);
1916 /* Set new parameters */
1917 mdp
->num_rx_ring
= ring
->rx_pending
;
1918 mdp
->num_tx_ring
= ring
->tx_pending
;
1920 ret
= sh_eth_ring_init(ndev
);
1922 dev_err(&ndev
->dev
, "%s: sh_eth_ring_init failed.\n", __func__
);
1925 ret
= sh_eth_dev_init(ndev
, false);
1927 dev_err(&ndev
->dev
, "%s: sh_eth_dev_init failed.\n", __func__
);
1931 if (netif_running(ndev
)) {
1932 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1933 /* Setting the Rx mode will start the Rx process. */
1934 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1935 netif_wake_queue(ndev
);
1941 static const struct ethtool_ops sh_eth_ethtool_ops
= {
1942 .get_settings
= sh_eth_get_settings
,
1943 .set_settings
= sh_eth_set_settings
,
1944 .nway_reset
= sh_eth_nway_reset
,
1945 .get_msglevel
= sh_eth_get_msglevel
,
1946 .set_msglevel
= sh_eth_set_msglevel
,
1947 .get_link
= ethtool_op_get_link
,
1948 .get_strings
= sh_eth_get_strings
,
1949 .get_ethtool_stats
= sh_eth_get_ethtool_stats
,
1950 .get_sset_count
= sh_eth_get_sset_count
,
1951 .get_ringparam
= sh_eth_get_ringparam
,
1952 .set_ringparam
= sh_eth_set_ringparam
,
1955 /* network device open function */
1956 static int sh_eth_open(struct net_device
*ndev
)
1959 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1961 pm_runtime_get_sync(&mdp
->pdev
->dev
);
1963 ret
= request_irq(ndev
->irq
, sh_eth_interrupt
,
1964 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1965 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1966 defined(CONFIG_CPU_SUBTYPE_SH7757)
1973 dev_err(&ndev
->dev
, "Can not assign IRQ number\n");
1977 /* Descriptor set */
1978 ret
= sh_eth_ring_init(ndev
);
1983 ret
= sh_eth_dev_init(ndev
, true);
1987 /* PHY control start*/
1988 ret
= sh_eth_phy_start(ndev
);
1995 free_irq(ndev
->irq
, ndev
);
1996 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2000 /* Timeout function */
2001 static void sh_eth_tx_timeout(struct net_device
*ndev
)
2003 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2004 struct sh_eth_rxdesc
*rxdesc
;
2007 netif_stop_queue(ndev
);
2009 if (netif_msg_timer(mdp
))
2010 dev_err(&ndev
->dev
, "%s: transmit timed out, status %8.8x,"
2011 " resetting...\n", ndev
->name
, (int)sh_eth_read(ndev
, EESR
));
2013 /* tx_errors count up */
2014 ndev
->stats
.tx_errors
++;
2016 /* Free all the skbuffs in the Rx queue. */
2017 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
2018 rxdesc
= &mdp
->rx_ring
[i
];
2020 rxdesc
->addr
= 0xBADF00D0;
2021 if (mdp
->rx_skbuff
[i
])
2022 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
2023 mdp
->rx_skbuff
[i
] = NULL
;
2025 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
2026 if (mdp
->tx_skbuff
[i
])
2027 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
2028 mdp
->tx_skbuff
[i
] = NULL
;
2032 sh_eth_dev_init(ndev
, true);
2035 /* Packet transmit function */
2036 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
2038 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2039 struct sh_eth_txdesc
*txdesc
;
2041 unsigned long flags
;
2043 spin_lock_irqsave(&mdp
->lock
, flags
);
2044 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (mdp
->num_tx_ring
- 4)) {
2045 if (!sh_eth_txfree(ndev
)) {
2046 if (netif_msg_tx_queued(mdp
))
2047 dev_warn(&ndev
->dev
, "TxFD exhausted.\n");
2048 netif_stop_queue(ndev
);
2049 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2050 return NETDEV_TX_BUSY
;
2053 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2055 entry
= mdp
->cur_tx
% mdp
->num_tx_ring
;
2056 mdp
->tx_skbuff
[entry
] = skb
;
2057 txdesc
= &mdp
->tx_ring
[entry
];
2059 if (!mdp
->cd
->hw_swap
)
2060 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc
->addr
, 4)),
2062 txdesc
->addr
= dma_map_single(&ndev
->dev
, skb
->data
, skb
->len
,
2064 if (skb
->len
< ETHERSMALL
)
2065 txdesc
->buffer_length
= ETHERSMALL
;
2067 txdesc
->buffer_length
= skb
->len
;
2069 if (entry
>= mdp
->num_tx_ring
- 1)
2070 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
| TD_TDLE
);
2072 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
);
2076 if (!(sh_eth_read(ndev
, EDTRR
) & sh_eth_get_edtrr_trns(mdp
)))
2077 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
2079 return NETDEV_TX_OK
;
2082 /* device close function */
2083 static int sh_eth_close(struct net_device
*ndev
)
2085 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2087 netif_stop_queue(ndev
);
2089 /* Disable interrupts by clearing the interrupt mask. */
2090 sh_eth_write(ndev
, 0x0000, EESIPR
);
2092 /* Stop the chip's Tx and Rx processes. */
2093 sh_eth_write(ndev
, 0, EDTRR
);
2094 sh_eth_write(ndev
, 0, EDRRR
);
2096 /* PHY Disconnect */
2098 phy_stop(mdp
->phydev
);
2099 phy_disconnect(mdp
->phydev
);
2102 free_irq(ndev
->irq
, ndev
);
2104 /* Free all the skbuffs in the Rx queue. */
2105 sh_eth_ring_free(ndev
);
2107 /* free DMA buffer */
2108 sh_eth_free_dma_buffer(mdp
);
2110 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2115 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
2117 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2119 pm_runtime_get_sync(&mdp
->pdev
->dev
);
2121 ndev
->stats
.tx_dropped
+= sh_eth_read(ndev
, TROCR
);
2122 sh_eth_write(ndev
, 0, TROCR
); /* (write clear) */
2123 ndev
->stats
.collisions
+= sh_eth_read(ndev
, CDCR
);
2124 sh_eth_write(ndev
, 0, CDCR
); /* (write clear) */
2125 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, LCCR
);
2126 sh_eth_write(ndev
, 0, LCCR
); /* (write clear) */
2127 if (sh_eth_is_gether(mdp
)) {
2128 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CERCR
);
2129 sh_eth_write(ndev
, 0, CERCR
); /* (write clear) */
2130 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CEECR
);
2131 sh_eth_write(ndev
, 0, CEECR
); /* (write clear) */
2133 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CNDCR
);
2134 sh_eth_write(ndev
, 0, CNDCR
); /* (write clear) */
2136 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2138 return &ndev
->stats
;
2141 /* ioctl to device function */
2142 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
,
2145 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2146 struct phy_device
*phydev
= mdp
->phydev
;
2148 if (!netif_running(ndev
))
2154 return phy_mii_ioctl(phydev
, rq
, cmd
);
2157 #if defined(SH_ETH_HAS_TSU)
2158 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2159 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private
*mdp
,
2162 return sh_eth_tsu_get_offset(mdp
, TSU_POST1
) + (entry
/ 8 * 4);
2165 static u32
sh_eth_tsu_get_post_mask(int entry
)
2167 return 0x0f << (28 - ((entry
% 8) * 4));
2170 static u32
sh_eth_tsu_get_post_bit(struct sh_eth_private
*mdp
, int entry
)
2172 return (0x08 >> (mdp
->port
<< 1)) << (28 - ((entry
% 8) * 4));
2175 static void sh_eth_tsu_enable_cam_entry_post(struct net_device
*ndev
,
2178 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2182 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
2183 tmp
= ioread32(reg_offset
);
2184 iowrite32(tmp
| sh_eth_tsu_get_post_bit(mdp
, entry
), reg_offset
);
2187 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device
*ndev
,
2190 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2191 u32 post_mask
, ref_mask
, tmp
;
2194 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
2195 post_mask
= sh_eth_tsu_get_post_mask(entry
);
2196 ref_mask
= sh_eth_tsu_get_post_bit(mdp
, entry
) & ~post_mask
;
2198 tmp
= ioread32(reg_offset
);
2199 iowrite32(tmp
& ~post_mask
, reg_offset
);
2201 /* If other port enables, the function returns "true" */
2202 return tmp
& ref_mask
;
2205 static int sh_eth_tsu_busy(struct net_device
*ndev
)
2207 int timeout
= SH_ETH_TSU_TIMEOUT_MS
* 100;
2208 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2210 while ((sh_eth_tsu_read(mdp
, TSU_ADSBSY
) & TSU_ADSBSY_0
)) {
2214 dev_err(&ndev
->dev
, "%s: timeout\n", __func__
);
2222 static int sh_eth_tsu_write_entry(struct net_device
*ndev
, void *reg
,
2227 val
= addr
[0] << 24 | addr
[1] << 16 | addr
[2] << 8 | addr
[3];
2228 iowrite32(val
, reg
);
2229 if (sh_eth_tsu_busy(ndev
) < 0)
2232 val
= addr
[4] << 8 | addr
[5];
2233 iowrite32(val
, reg
+ 4);
2234 if (sh_eth_tsu_busy(ndev
) < 0)
2240 static void sh_eth_tsu_read_entry(void *reg
, u8
*addr
)
2244 val
= ioread32(reg
);
2245 addr
[0] = (val
>> 24) & 0xff;
2246 addr
[1] = (val
>> 16) & 0xff;
2247 addr
[2] = (val
>> 8) & 0xff;
2248 addr
[3] = val
& 0xff;
2249 val
= ioread32(reg
+ 4);
2250 addr
[4] = (val
>> 8) & 0xff;
2251 addr
[5] = val
& 0xff;
2255 static int sh_eth_tsu_find_entry(struct net_device
*ndev
, const u8
*addr
)
2257 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2258 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2260 u8 c_addr
[ETH_ALEN
];
2262 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
2263 sh_eth_tsu_read_entry(reg_offset
, c_addr
);
2264 if (memcmp(addr
, c_addr
, ETH_ALEN
) == 0)
2271 static int sh_eth_tsu_find_empty(struct net_device
*ndev
)
2276 memset(blank
, 0, sizeof(blank
));
2277 entry
= sh_eth_tsu_find_entry(ndev
, blank
);
2278 return (entry
< 0) ? -ENOMEM
: entry
;
2281 static int sh_eth_tsu_disable_cam_entry_table(struct net_device
*ndev
,
2284 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2285 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2289 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) &
2290 ~(1 << (31 - entry
)), TSU_TEN
);
2292 memset(blank
, 0, sizeof(blank
));
2293 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ entry
* 8, blank
);
2299 static int sh_eth_tsu_add_entry(struct net_device
*ndev
, const u8
*addr
)
2301 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2302 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2308 i
= sh_eth_tsu_find_entry(ndev
, addr
);
2310 /* No entry found, create one */
2311 i
= sh_eth_tsu_find_empty(ndev
);
2314 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ i
* 8, addr
);
2318 /* Enable the entry */
2319 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) |
2320 (1 << (31 - i
)), TSU_TEN
);
2323 /* Entry found or created, enable POST */
2324 sh_eth_tsu_enable_cam_entry_post(ndev
, i
);
2329 static int sh_eth_tsu_del_entry(struct net_device
*ndev
, const u8
*addr
)
2331 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2337 i
= sh_eth_tsu_find_entry(ndev
, addr
);
2340 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
2343 /* Disable the entry if both ports was disabled */
2344 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
2352 static int sh_eth_tsu_purge_all(struct net_device
*ndev
)
2354 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2357 if (unlikely(!mdp
->cd
->tsu
))
2360 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++) {
2361 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
2364 /* Disable the entry if both ports was disabled */
2365 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
2373 static void sh_eth_tsu_purge_mcast(struct net_device
*ndev
)
2375 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2377 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2380 if (unlikely(!mdp
->cd
->tsu
))
2383 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
2384 sh_eth_tsu_read_entry(reg_offset
, addr
);
2385 if (is_multicast_ether_addr(addr
))
2386 sh_eth_tsu_del_entry(ndev
, addr
);
2390 /* Multicast reception directions set */
2391 static void sh_eth_set_multicast_list(struct net_device
*ndev
)
2393 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2396 unsigned long flags
;
2398 spin_lock_irqsave(&mdp
->lock
, flags
);
2400 * Initial condition is MCT = 1, PRM = 0.
2401 * Depending on ndev->flags, set PRM or clear MCT
2403 ecmr_bits
= (sh_eth_read(ndev
, ECMR
) & ~ECMR_PRM
) | ECMR_MCT
;
2405 if (!(ndev
->flags
& IFF_MULTICAST
)) {
2406 sh_eth_tsu_purge_mcast(ndev
);
2409 if (ndev
->flags
& IFF_ALLMULTI
) {
2410 sh_eth_tsu_purge_mcast(ndev
);
2411 ecmr_bits
&= ~ECMR_MCT
;
2415 if (ndev
->flags
& IFF_PROMISC
) {
2416 sh_eth_tsu_purge_all(ndev
);
2417 ecmr_bits
= (ecmr_bits
& ~ECMR_MCT
) | ECMR_PRM
;
2418 } else if (mdp
->cd
->tsu
) {
2419 struct netdev_hw_addr
*ha
;
2420 netdev_for_each_mc_addr(ha
, ndev
) {
2421 if (mcast_all
&& is_multicast_ether_addr(ha
->addr
))
2424 if (sh_eth_tsu_add_entry(ndev
, ha
->addr
) < 0) {
2426 sh_eth_tsu_purge_mcast(ndev
);
2427 ecmr_bits
&= ~ECMR_MCT
;
2433 /* Normal, unicast/broadcast-only mode. */
2434 ecmr_bits
= (ecmr_bits
& ~ECMR_PRM
) | ECMR_MCT
;
2437 /* update the ethernet mode */
2438 sh_eth_write(ndev
, ecmr_bits
, ECMR
);
2440 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2443 static int sh_eth_get_vtag_index(struct sh_eth_private
*mdp
)
2451 static int sh_eth_vlan_rx_add_vid(struct net_device
*ndev
, u16 vid
)
2453 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2454 int vtag_reg_index
= sh_eth_get_vtag_index(mdp
);
2456 if (unlikely(!mdp
->cd
->tsu
))
2459 /* No filtering if vid = 0 */
2463 mdp
->vlan_num_ids
++;
2466 * The controller has one VLAN tag HW filter. So, if the filter is
2467 * already enabled, the driver disables it and the filte
2469 if (mdp
->vlan_num_ids
> 1) {
2470 /* disable VLAN filter */
2471 sh_eth_tsu_write(mdp
, 0, vtag_reg_index
);
2475 sh_eth_tsu_write(mdp
, TSU_VTAG_ENABLE
| (vid
& TSU_VTAG_VID_MASK
),
2481 static int sh_eth_vlan_rx_kill_vid(struct net_device
*ndev
, u16 vid
)
2483 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2484 int vtag_reg_index
= sh_eth_get_vtag_index(mdp
);
2486 if (unlikely(!mdp
->cd
->tsu
))
2489 /* No filtering if vid = 0 */
2493 mdp
->vlan_num_ids
--;
2494 sh_eth_tsu_write(mdp
, 0, vtag_reg_index
);
2498 #endif /* SH_ETH_HAS_TSU */
2500 /* SuperH's TSU register init function */
2501 static void sh_eth_tsu_init(struct sh_eth_private
*mdp
)
2503 sh_eth_tsu_write(mdp
, 0, TSU_FWEN0
); /* Disable forward(0->1) */
2504 sh_eth_tsu_write(mdp
, 0, TSU_FWEN1
); /* Disable forward(1->0) */
2505 sh_eth_tsu_write(mdp
, 0, TSU_FCM
); /* forward fifo 3k-3k */
2506 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL0
);
2507 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL1
);
2508 sh_eth_tsu_write(mdp
, 0, TSU_PRISL0
);
2509 sh_eth_tsu_write(mdp
, 0, TSU_PRISL1
);
2510 sh_eth_tsu_write(mdp
, 0, TSU_FWSL0
);
2511 sh_eth_tsu_write(mdp
, 0, TSU_FWSL1
);
2512 sh_eth_tsu_write(mdp
, TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, TSU_FWSLC
);
2513 if (sh_eth_is_gether(mdp
)) {
2514 sh_eth_tsu_write(mdp
, 0, TSU_QTAG0
); /* Disable QTAG(0->1) */
2515 sh_eth_tsu_write(mdp
, 0, TSU_QTAG1
); /* Disable QTAG(1->0) */
2517 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM0
); /* Disable QTAG(0->1) */
2518 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM1
); /* Disable QTAG(1->0) */
2520 sh_eth_tsu_write(mdp
, 0, TSU_FWSR
); /* all interrupt status clear */
2521 sh_eth_tsu_write(mdp
, 0, TSU_FWINMK
); /* Disable all interrupt */
2522 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
2523 sh_eth_tsu_write(mdp
, 0, TSU_POST1
); /* Disable CAM entry [ 0- 7] */
2524 sh_eth_tsu_write(mdp
, 0, TSU_POST2
); /* Disable CAM entry [ 8-15] */
2525 sh_eth_tsu_write(mdp
, 0, TSU_POST3
); /* Disable CAM entry [16-23] */
2526 sh_eth_tsu_write(mdp
, 0, TSU_POST4
); /* Disable CAM entry [24-31] */
2529 /* MDIO bus release function */
2530 static int sh_mdio_release(struct net_device
*ndev
)
2532 struct mii_bus
*bus
= dev_get_drvdata(&ndev
->dev
);
2534 /* unregister mdio bus */
2535 mdiobus_unregister(bus
);
2537 /* remove mdio bus info from net_device */
2538 dev_set_drvdata(&ndev
->dev
, NULL
);
2540 /* free bitbang info */
2541 free_mdio_bitbang(bus
);
2546 /* MDIO bus init function */
2547 static int sh_mdio_init(struct net_device
*ndev
, int id
,
2548 struct sh_eth_plat_data
*pd
)
2551 struct bb_info
*bitbang
;
2552 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2554 /* create bit control struct for PHY */
2555 bitbang
= devm_kzalloc(&ndev
->dev
, sizeof(struct bb_info
),
2563 bitbang
->addr
= mdp
->addr
+ mdp
->reg_offset
[PIR
];
2564 bitbang
->set_gate
= pd
->set_mdio_gate
;
2565 bitbang
->mdi_msk
= PIR_MDI
;
2566 bitbang
->mdo_msk
= PIR_MDO
;
2567 bitbang
->mmd_msk
= PIR_MMD
;
2568 bitbang
->mdc_msk
= PIR_MDC
;
2569 bitbang
->ctrl
.ops
= &bb_ops
;
2571 /* MII controller setting */
2572 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
2573 if (!mdp
->mii_bus
) {
2578 /* Hook up MII support for ethtool */
2579 mdp
->mii_bus
->name
= "sh_mii";
2580 mdp
->mii_bus
->parent
= &ndev
->dev
;
2581 snprintf(mdp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
2582 mdp
->pdev
->name
, id
);
2585 mdp
->mii_bus
->irq
= devm_kzalloc(&ndev
->dev
,
2586 sizeof(int) * PHY_MAX_ADDR
,
2588 if (!mdp
->mii_bus
->irq
) {
2593 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
2594 mdp
->mii_bus
->irq
[i
] = PHY_POLL
;
2596 /* register mdio bus */
2597 ret
= mdiobus_register(mdp
->mii_bus
);
2601 dev_set_drvdata(&ndev
->dev
, mdp
->mii_bus
);
2606 free_mdio_bitbang(mdp
->mii_bus
);
2612 static const u16
*sh_eth_get_register_offset(int register_type
)
2614 const u16
*reg_offset
= NULL
;
2616 switch (register_type
) {
2617 case SH_ETH_REG_GIGABIT
:
2618 reg_offset
= sh_eth_offset_gigabit
;
2620 case SH_ETH_REG_FAST_RCAR
:
2621 reg_offset
= sh_eth_offset_fast_rcar
;
2623 case SH_ETH_REG_FAST_SH4
:
2624 reg_offset
= sh_eth_offset_fast_sh4
;
2626 case SH_ETH_REG_FAST_SH3_SH2
:
2627 reg_offset
= sh_eth_offset_fast_sh3_sh2
;
2630 pr_err("Unknown register type (%d)\n", register_type
);
2637 static const struct net_device_ops sh_eth_netdev_ops
= {
2638 .ndo_open
= sh_eth_open
,
2639 .ndo_stop
= sh_eth_close
,
2640 .ndo_start_xmit
= sh_eth_start_xmit
,
2641 .ndo_get_stats
= sh_eth_get_stats
,
2642 #if defined(SH_ETH_HAS_TSU)
2643 .ndo_set_rx_mode
= sh_eth_set_multicast_list
,
2644 .ndo_vlan_rx_add_vid
= sh_eth_vlan_rx_add_vid
,
2645 .ndo_vlan_rx_kill_vid
= sh_eth_vlan_rx_kill_vid
,
2647 .ndo_tx_timeout
= sh_eth_tx_timeout
,
2648 .ndo_do_ioctl
= sh_eth_do_ioctl
,
2649 .ndo_validate_addr
= eth_validate_addr
,
2650 .ndo_set_mac_address
= eth_mac_addr
,
2651 .ndo_change_mtu
= eth_change_mtu
,
2654 static int sh_eth_drv_probe(struct platform_device
*pdev
)
2657 struct resource
*res
;
2658 struct net_device
*ndev
= NULL
;
2659 struct sh_eth_private
*mdp
= NULL
;
2660 struct sh_eth_plat_data
*pd
= pdev
->dev
.platform_data
;
2663 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2664 if (unlikely(res
== NULL
)) {
2665 dev_err(&pdev
->dev
, "invalid resource\n");
2670 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
2676 /* The sh Ether-specific entries in the device structure. */
2677 ndev
->base_addr
= res
->start
;
2683 ret
= platform_get_irq(pdev
, 0);
2690 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2692 /* Fill in the fields of the device structure with ethernet values. */
2695 mdp
= netdev_priv(ndev
);
2696 mdp
->num_tx_ring
= TX_RING_SIZE
;
2697 mdp
->num_rx_ring
= RX_RING_SIZE
;
2698 mdp
->addr
= devm_ioremap_resource(&pdev
->dev
, res
);
2699 if (IS_ERR(mdp
->addr
)) {
2700 ret
= PTR_ERR(mdp
->addr
);
2704 spin_lock_init(&mdp
->lock
);
2706 pm_runtime_enable(&pdev
->dev
);
2707 pm_runtime_resume(&pdev
->dev
);
2710 mdp
->phy_id
= pd
->phy
;
2711 mdp
->phy_interface
= pd
->phy_interface
;
2713 mdp
->edmac_endian
= pd
->edmac_endian
;
2714 mdp
->no_ether_link
= pd
->no_ether_link
;
2715 mdp
->ether_link_active_low
= pd
->ether_link_active_low
;
2716 mdp
->reg_offset
= sh_eth_get_register_offset(pd
->register_type
);
2719 #if defined(SH_ETH_HAS_BOTH_MODULES)
2720 mdp
->cd
= sh_eth_get_cpu_data(mdp
);
2722 mdp
->cd
= &sh_eth_my_cpu_data
;
2724 sh_eth_set_default_cpu_data(mdp
->cd
);
2727 ndev
->netdev_ops
= &sh_eth_netdev_ops
;
2728 SET_ETHTOOL_OPS(ndev
, &sh_eth_ethtool_ops
);
2729 ndev
->watchdog_timeo
= TX_TIMEOUT
;
2731 /* debug message level */
2732 mdp
->msg_enable
= SH_ETH_DEF_MSG_ENABLE
;
2734 /* read and set MAC address */
2735 read_mac_address(ndev
, pd
->mac_addr
);
2737 /* ioremap the TSU registers */
2739 struct resource
*rtsu
;
2740 rtsu
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2742 dev_err(&pdev
->dev
, "Not found TSU resource\n");
2746 mdp
->tsu_addr
= devm_ioremap_resource(&pdev
->dev
, rtsu
);
2747 if (IS_ERR(mdp
->tsu_addr
)) {
2748 ret
= PTR_ERR(mdp
->tsu_addr
);
2751 mdp
->port
= devno
% 2;
2752 ndev
->features
= NETIF_F_HW_VLAN_CTAG_FILTER
;
2755 /* initialize first or needed device */
2756 if (!devno
|| pd
->needs_init
) {
2757 if (mdp
->cd
->chip_reset
)
2758 mdp
->cd
->chip_reset(ndev
);
2761 /* TSU init (Init only)*/
2762 sh_eth_tsu_init(mdp
);
2766 /* network device register */
2767 ret
= register_netdev(ndev
);
2772 ret
= sh_mdio_init(ndev
, pdev
->id
, pd
);
2774 goto out_unregister
;
2776 /* print device information */
2777 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2778 (u32
)ndev
->base_addr
, ndev
->dev_addr
, ndev
->irq
);
2780 platform_set_drvdata(pdev
, ndev
);
2785 unregister_netdev(ndev
);
2796 static int sh_eth_drv_remove(struct platform_device
*pdev
)
2798 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2800 sh_mdio_release(ndev
);
2801 unregister_netdev(ndev
);
2802 pm_runtime_disable(&pdev
->dev
);
2804 platform_set_drvdata(pdev
, NULL
);
2809 static int sh_eth_runtime_nop(struct device
*dev
)
2812 * Runtime PM callback shared between ->runtime_suspend()
2813 * and ->runtime_resume(). Simply returns success.
2815 * This driver re-initializes all registers after
2816 * pm_runtime_get_sync() anyway so there is no need
2817 * to save and restore registers here.
2822 static struct dev_pm_ops sh_eth_dev_pm_ops
= {
2823 .runtime_suspend
= sh_eth_runtime_nop
,
2824 .runtime_resume
= sh_eth_runtime_nop
,
2827 static struct platform_driver sh_eth_driver
= {
2828 .probe
= sh_eth_drv_probe
,
2829 .remove
= sh_eth_drv_remove
,
2832 .pm
= &sh_eth_dev_pm_ops
,
2836 module_platform_driver(sh_eth_driver
);
2838 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2839 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2840 MODULE_LICENSE("GPL v2");