2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/spinlock.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/mdio-bitbang.h>
34 #include <linux/netdevice.h>
35 #include <linux/phy.h>
36 #include <linux/cache.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/slab.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/clk.h>
43 #include <linux/sh_eth.h>
47 #define SH_ETH_DEF_MSG_ENABLE \
53 static const u16 sh_eth_offset_gigabit
[SH_ETH_MAX_REGISTER_OFFSET
] = {
107 [TSU_CTRST
] = 0x0004,
108 [TSU_FWEN0
] = 0x0010,
109 [TSU_FWEN1
] = 0x0014,
111 [TSU_BSYSL0
] = 0x0020,
112 [TSU_BSYSL1
] = 0x0024,
113 [TSU_PRISL0
] = 0x0028,
114 [TSU_PRISL1
] = 0x002c,
115 [TSU_FWSL0
] = 0x0030,
116 [TSU_FWSL1
] = 0x0034,
117 [TSU_FWSLC
] = 0x0038,
118 [TSU_QTAG0
] = 0x0040,
119 [TSU_QTAG1
] = 0x0044,
121 [TSU_FWINMK
] = 0x0054,
122 [TSU_ADQT0
] = 0x0048,
123 [TSU_ADQT1
] = 0x004c,
124 [TSU_VTAG0
] = 0x0058,
125 [TSU_VTAG1
] = 0x005c,
126 [TSU_ADSBSY
] = 0x0060,
128 [TSU_POST1
] = 0x0070,
129 [TSU_POST2
] = 0x0074,
130 [TSU_POST3
] = 0x0078,
131 [TSU_POST4
] = 0x007c,
132 [TSU_ADRH0
] = 0x0100,
133 [TSU_ADRL0
] = 0x0104,
134 [TSU_ADRH31
] = 0x01f8,
135 [TSU_ADRL31
] = 0x01fc,
151 static const u16 sh_eth_offset_fast_rcar
[SH_ETH_MAX_REGISTER_OFFSET
] = {
196 static const u16 sh_eth_offset_fast_sh4
[SH_ETH_MAX_REGISTER_OFFSET
] = {
248 static const u16 sh_eth_offset_fast_sh3_sh2
[SH_ETH_MAX_REGISTER_OFFSET
] = {
274 [TSU_CTRST
] = 0x0004,
275 [TSU_FWEN0
] = 0x0010,
276 [TSU_FWEN1
] = 0x0014,
278 [TSU_BSYSL0
] = 0x0020,
279 [TSU_BSYSL1
] = 0x0024,
280 [TSU_PRISL0
] = 0x0028,
281 [TSU_PRISL1
] = 0x002c,
282 [TSU_FWSL0
] = 0x0030,
283 [TSU_FWSL1
] = 0x0034,
284 [TSU_FWSLC
] = 0x0038,
285 [TSU_QTAGM0
] = 0x0040,
286 [TSU_QTAGM1
] = 0x0044,
287 [TSU_ADQT0
] = 0x0048,
288 [TSU_ADQT1
] = 0x004c,
290 [TSU_FWINMK
] = 0x0054,
291 [TSU_ADSBSY
] = 0x0060,
293 [TSU_POST1
] = 0x0070,
294 [TSU_POST2
] = 0x0074,
295 [TSU_POST3
] = 0x0078,
296 [TSU_POST4
] = 0x007c,
311 [TSU_ADRH0
] = 0x0100,
312 [TSU_ADRL0
] = 0x0104,
313 [TSU_ADRL31
] = 0x01fc,
316 #if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
317 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
318 defined(CONFIG_ARCH_R8A7740)
319 static void sh_eth_select_mii(struct net_device
*ndev
)
322 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
324 switch (mdp
->phy_interface
) {
325 case PHY_INTERFACE_MODE_GMII
:
328 case PHY_INTERFACE_MODE_MII
:
331 case PHY_INTERFACE_MODE_RMII
:
335 pr_warn("PHY interface mode was not setup. Set to MII.\n");
340 sh_eth_write(ndev
, value
, RMII_MII
);
344 /* There is CPU dependent code */
345 #if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779)
346 #define SH_ETH_RESET_DEFAULT 1
347 static void sh_eth_set_duplex(struct net_device
*ndev
)
349 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
351 if (mdp
->duplex
) /* Full */
352 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
354 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
357 static void sh_eth_set_rate(struct net_device
*ndev
)
359 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
361 switch (mdp
->speed
) {
362 case 10: /* 10BASE */
363 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_ELB
, ECMR
);
365 case 100:/* 100BASE */
366 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_ELB
, ECMR
);
374 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
375 .set_duplex
= sh_eth_set_duplex
,
376 .set_rate
= sh_eth_set_rate
,
378 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
379 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
380 .eesipr_value
= 0x01ff009f,
382 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
383 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
384 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
385 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
392 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
393 #define SH_ETH_RESET_DEFAULT 1
394 static void sh_eth_set_duplex(struct net_device
*ndev
)
396 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
398 if (mdp
->duplex
) /* Full */
399 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
401 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
404 static void sh_eth_set_rate(struct net_device
*ndev
)
406 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
408 switch (mdp
->speed
) {
409 case 10: /* 10BASE */
410 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_RTM
, ECMR
);
412 case 100:/* 100BASE */
413 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_RTM
, ECMR
);
421 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
422 .set_duplex
= sh_eth_set_duplex
,
423 .set_rate
= sh_eth_set_rate
,
425 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
426 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
427 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x01ff009f,
429 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
430 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
431 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
432 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
439 .rpadir_value
= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
441 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
442 #define SH_ETH_HAS_BOTH_MODULES 1
443 #define SH_ETH_HAS_TSU 1
444 static int sh_eth_check_reset(struct net_device
*ndev
);
446 static void sh_eth_set_duplex(struct net_device
*ndev
)
448 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
450 if (mdp
->duplex
) /* Full */
451 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
453 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
456 static void sh_eth_set_rate(struct net_device
*ndev
)
458 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
460 switch (mdp
->speed
) {
461 case 10: /* 10BASE */
462 sh_eth_write(ndev
, 0, RTRATE
);
464 case 100:/* 100BASE */
465 sh_eth_write(ndev
, 1, RTRATE
);
473 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
474 .set_duplex
= sh_eth_set_duplex
,
475 .set_rate
= sh_eth_set_rate
,
477 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
478 .rmcr_value
= 0x00000001,
480 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
481 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
482 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
483 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
491 .rpadir_value
= 2 << 16,
494 #define SH_GIGA_ETH_BASE 0xfee00000
495 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
496 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
497 static void sh_eth_chip_reset_giga(struct net_device
*ndev
)
500 unsigned long mahr
[2], malr
[2];
502 /* save MAHR and MALR */
503 for (i
= 0; i
< 2; i
++) {
504 malr
[i
] = ioread32((void *)GIGA_MALR(i
));
505 mahr
[i
] = ioread32((void *)GIGA_MAHR(i
));
509 iowrite32(ARSTR_ARSTR
, (void *)(SH_GIGA_ETH_BASE
+ 0x1800));
512 /* restore MAHR and MALR */
513 for (i
= 0; i
< 2; i
++) {
514 iowrite32(malr
[i
], (void *)GIGA_MALR(i
));
515 iowrite32(mahr
[i
], (void *)GIGA_MAHR(i
));
519 static int sh_eth_is_gether(struct sh_eth_private
*mdp
);
520 static int sh_eth_reset(struct net_device
*ndev
)
522 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
525 if (sh_eth_is_gether(mdp
)) {
526 sh_eth_write(ndev
, 0x03, EDSR
);
527 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
,
530 ret
= sh_eth_check_reset(ndev
);
535 sh_eth_write(ndev
, 0x0, TDLAR
);
536 sh_eth_write(ndev
, 0x0, TDFAR
);
537 sh_eth_write(ndev
, 0x0, TDFXR
);
538 sh_eth_write(ndev
, 0x0, TDFFR
);
539 sh_eth_write(ndev
, 0x0, RDLAR
);
540 sh_eth_write(ndev
, 0x0, RDFAR
);
541 sh_eth_write(ndev
, 0x0, RDFXR
);
542 sh_eth_write(ndev
, 0x0, RDFFR
);
544 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
,
547 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
,
555 static void sh_eth_set_duplex_giga(struct net_device
*ndev
)
557 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
559 if (mdp
->duplex
) /* Full */
560 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
562 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
565 static void sh_eth_set_rate_giga(struct net_device
*ndev
)
567 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
569 switch (mdp
->speed
) {
570 case 10: /* 10BASE */
571 sh_eth_write(ndev
, 0x00000000, GECMR
);
573 case 100:/* 100BASE */
574 sh_eth_write(ndev
, 0x00000010, GECMR
);
576 case 1000: /* 1000BASE */
577 sh_eth_write(ndev
, 0x00000020, GECMR
);
584 /* SH7757(GETHERC) */
585 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga
= {
586 .chip_reset
= sh_eth_chip_reset_giga
,
587 .set_duplex
= sh_eth_set_duplex_giga
,
588 .set_rate
= sh_eth_set_rate_giga
,
590 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
591 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
592 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
594 .tx_check
= EESR_TC1
| EESR_FTC
,
595 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
596 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
598 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
600 .fdr_value
= 0x0000072f,
601 .rmcr_value
= 0x00000001,
609 .rpadir_value
= 2 << 16,
615 static struct sh_eth_cpu_data
*sh_eth_get_cpu_data(struct sh_eth_private
*mdp
)
617 if (sh_eth_is_gether(mdp
))
618 return &sh_eth_my_cpu_data_giga
;
620 return &sh_eth_my_cpu_data
;
623 #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
624 #define SH_ETH_HAS_TSU 1
625 static int sh_eth_check_reset(struct net_device
*ndev
);
626 static void sh_eth_reset_hw_crc(struct net_device
*ndev
);
628 static void sh_eth_chip_reset(struct net_device
*ndev
)
630 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
633 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
637 static void sh_eth_set_duplex(struct net_device
*ndev
)
639 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
641 if (mdp
->duplex
) /* Full */
642 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
644 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
647 static void sh_eth_set_rate(struct net_device
*ndev
)
649 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
651 switch (mdp
->speed
) {
652 case 10: /* 10BASE */
653 sh_eth_write(ndev
, GECMR_10
, GECMR
);
655 case 100:/* 100BASE */
656 sh_eth_write(ndev
, GECMR_100
, GECMR
);
658 case 1000: /* 1000BASE */
659 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
667 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
668 .chip_reset
= sh_eth_chip_reset
,
669 .set_duplex
= sh_eth_set_duplex
,
670 .set_rate
= sh_eth_set_rate
,
672 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
673 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
674 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
676 .tx_check
= EESR_TC1
| EESR_FTC
,
677 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
678 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
680 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
691 #if defined(CONFIG_CPU_SUBTYPE_SH7734)
697 static int sh_eth_reset(struct net_device
*ndev
)
701 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
702 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
, EDMR
);
704 ret
= sh_eth_check_reset(ndev
);
709 sh_eth_write(ndev
, 0x0, TDLAR
);
710 sh_eth_write(ndev
, 0x0, TDFAR
);
711 sh_eth_write(ndev
, 0x0, TDFXR
);
712 sh_eth_write(ndev
, 0x0, TDFFR
);
713 sh_eth_write(ndev
, 0x0, RDLAR
);
714 sh_eth_write(ndev
, 0x0, RDFAR
);
715 sh_eth_write(ndev
, 0x0, RDFXR
);
716 sh_eth_write(ndev
, 0x0, RDFFR
);
718 /* Reset HW CRC register */
719 sh_eth_reset_hw_crc(ndev
);
721 /* Select MII mode */
722 if (sh_eth_my_cpu_data
.select_mii
)
723 sh_eth_select_mii(ndev
);
728 static void sh_eth_reset_hw_crc(struct net_device
*ndev
)
730 if (sh_eth_my_cpu_data
.hw_crc
)
731 sh_eth_write(ndev
, 0x0, CSMR
);
734 #elif defined(CONFIG_ARCH_R8A7740)
735 #define SH_ETH_HAS_TSU 1
736 static int sh_eth_check_reset(struct net_device
*ndev
);
738 static void sh_eth_chip_reset(struct net_device
*ndev
)
740 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
743 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
746 sh_eth_select_mii(ndev
);
749 static int sh_eth_reset(struct net_device
*ndev
)
753 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
754 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
, EDMR
);
756 ret
= sh_eth_check_reset(ndev
);
761 sh_eth_write(ndev
, 0x0, TDLAR
);
762 sh_eth_write(ndev
, 0x0, TDFAR
);
763 sh_eth_write(ndev
, 0x0, TDFXR
);
764 sh_eth_write(ndev
, 0x0, TDFFR
);
765 sh_eth_write(ndev
, 0x0, RDLAR
);
766 sh_eth_write(ndev
, 0x0, RDFAR
);
767 sh_eth_write(ndev
, 0x0, RDFXR
);
768 sh_eth_write(ndev
, 0x0, RDFFR
);
774 static void sh_eth_set_duplex(struct net_device
*ndev
)
776 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
778 if (mdp
->duplex
) /* Full */
779 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
781 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
784 static void sh_eth_set_rate(struct net_device
*ndev
)
786 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
788 switch (mdp
->speed
) {
789 case 10: /* 10BASE */
790 sh_eth_write(ndev
, GECMR_10
, GECMR
);
792 case 100:/* 100BASE */
793 sh_eth_write(ndev
, GECMR_100
, GECMR
);
795 case 1000: /* 1000BASE */
796 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
804 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
805 .chip_reset
= sh_eth_chip_reset
,
806 .set_duplex
= sh_eth_set_duplex
,
807 .set_rate
= sh_eth_set_rate
,
809 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
810 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
811 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
813 .tx_check
= EESR_TC1
| EESR_FTC
,
814 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
815 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
817 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
831 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
832 #define SH_ETH_RESET_DEFAULT 1
833 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
834 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
841 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
842 #define SH_ETH_RESET_DEFAULT 1
843 #define SH_ETH_HAS_TSU 1
844 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
845 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
850 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data
*cd
)
853 cd
->ecsr_value
= DEFAULT_ECSR_INIT
;
855 if (!cd
->ecsipr_value
)
856 cd
->ecsipr_value
= DEFAULT_ECSIPR_INIT
;
858 if (!cd
->fcftr_value
)
859 cd
->fcftr_value
= DEFAULT_FIFO_F_D_RFF
| \
860 DEFAULT_FIFO_F_D_RFD
;
863 cd
->fdr_value
= DEFAULT_FDR_INIT
;
866 cd
->rmcr_value
= DEFAULT_RMCR_VALUE
;
869 cd
->tx_check
= DEFAULT_TX_CHECK
;
871 if (!cd
->eesr_err_check
)
872 cd
->eesr_err_check
= DEFAULT_EESR_ERR_CHECK
;
874 if (!cd
->tx_error_check
)
875 cd
->tx_error_check
= DEFAULT_TX_ERROR_CHECK
;
878 #if defined(SH_ETH_RESET_DEFAULT)
880 static int sh_eth_reset(struct net_device
*ndev
)
882 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
, EDMR
);
884 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
, EDMR
);
889 static int sh_eth_check_reset(struct net_device
*ndev
)
895 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
901 pr_err("Device reset failed\n");
908 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
909 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
913 reserve
= SH4_SKB_RX_ALIGN
- ((u32
)skb
->data
& (SH4_SKB_RX_ALIGN
- 1));
915 skb_reserve(skb
, reserve
);
918 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
920 skb_reserve(skb
, SH2_SH3_SKB_RX_ALIGN
);
925 /* CPU <-> EDMAC endian convert */
926 static inline __u32
cpu_to_edmac(struct sh_eth_private
*mdp
, u32 x
)
928 switch (mdp
->edmac_endian
) {
929 case EDMAC_LITTLE_ENDIAN
:
930 return cpu_to_le32(x
);
931 case EDMAC_BIG_ENDIAN
:
932 return cpu_to_be32(x
);
937 static inline __u32
edmac_to_cpu(struct sh_eth_private
*mdp
, u32 x
)
939 switch (mdp
->edmac_endian
) {
940 case EDMAC_LITTLE_ENDIAN
:
941 return le32_to_cpu(x
);
942 case EDMAC_BIG_ENDIAN
:
943 return be32_to_cpu(x
);
949 * Program the hardware MAC address from dev->dev_addr.
951 static void update_mac_address(struct net_device
*ndev
)
954 (ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
955 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]), MAHR
);
957 (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]), MALR
);
961 * Get MAC address from SuperH MAC address register
963 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
964 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
965 * When you want use this device, you must set MAC address in bootloader.
968 static void read_mac_address(struct net_device
*ndev
, unsigned char *mac
)
970 if (mac
[0] || mac
[1] || mac
[2] || mac
[3] || mac
[4] || mac
[5]) {
971 memcpy(ndev
->dev_addr
, mac
, 6);
973 ndev
->dev_addr
[0] = (sh_eth_read(ndev
, MAHR
) >> 24);
974 ndev
->dev_addr
[1] = (sh_eth_read(ndev
, MAHR
) >> 16) & 0xFF;
975 ndev
->dev_addr
[2] = (sh_eth_read(ndev
, MAHR
) >> 8) & 0xFF;
976 ndev
->dev_addr
[3] = (sh_eth_read(ndev
, MAHR
) & 0xFF);
977 ndev
->dev_addr
[4] = (sh_eth_read(ndev
, MALR
) >> 8) & 0xFF;
978 ndev
->dev_addr
[5] = (sh_eth_read(ndev
, MALR
) & 0xFF);
982 static int sh_eth_is_gether(struct sh_eth_private
*mdp
)
984 if (mdp
->reg_offset
== sh_eth_offset_gigabit
)
990 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private
*mdp
)
992 if (sh_eth_is_gether(mdp
))
993 return EDTRR_TRNS_GETHER
;
995 return EDTRR_TRNS_ETHER
;
999 void (*set_gate
)(void *addr
);
1000 struct mdiobb_ctrl ctrl
;
1002 u32 mmd_msk
;/* MMD */
1009 static void bb_set(void *addr
, u32 msk
)
1011 iowrite32(ioread32(addr
) | msk
, addr
);
1015 static void bb_clr(void *addr
, u32 msk
)
1017 iowrite32((ioread32(addr
) & ~msk
), addr
);
1021 static int bb_read(void *addr
, u32 msk
)
1023 return (ioread32(addr
) & msk
) != 0;
1026 /* Data I/O pin control */
1027 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
1029 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1031 if (bitbang
->set_gate
)
1032 bitbang
->set_gate(bitbang
->addr
);
1035 bb_set(bitbang
->addr
, bitbang
->mmd_msk
);
1037 bb_clr(bitbang
->addr
, bitbang
->mmd_msk
);
1041 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
1043 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1045 if (bitbang
->set_gate
)
1046 bitbang
->set_gate(bitbang
->addr
);
1049 bb_set(bitbang
->addr
, bitbang
->mdo_msk
);
1051 bb_clr(bitbang
->addr
, bitbang
->mdo_msk
);
1055 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
1057 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1059 if (bitbang
->set_gate
)
1060 bitbang
->set_gate(bitbang
->addr
);
1062 return bb_read(bitbang
->addr
, bitbang
->mdi_msk
);
1065 /* MDC pin control */
1066 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
1068 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1070 if (bitbang
->set_gate
)
1071 bitbang
->set_gate(bitbang
->addr
);
1074 bb_set(bitbang
->addr
, bitbang
->mdc_msk
);
1076 bb_clr(bitbang
->addr
, bitbang
->mdc_msk
);
1079 /* mdio bus control struct */
1080 static struct mdiobb_ops bb_ops
= {
1081 .owner
= THIS_MODULE
,
1082 .set_mdc
= sh_mdc_ctrl
,
1083 .set_mdio_dir
= sh_mmd_ctrl
,
1084 .set_mdio_data
= sh_set_mdio
,
1085 .get_mdio_data
= sh_get_mdio
,
1088 /* free skb and descriptor buffer */
1089 static void sh_eth_ring_free(struct net_device
*ndev
)
1091 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1094 /* Free Rx skb ringbuffer */
1095 if (mdp
->rx_skbuff
) {
1096 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
1097 if (mdp
->rx_skbuff
[i
])
1098 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
1101 kfree(mdp
->rx_skbuff
);
1102 mdp
->rx_skbuff
= NULL
;
1104 /* Free Tx skb ringbuffer */
1105 if (mdp
->tx_skbuff
) {
1106 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
1107 if (mdp
->tx_skbuff
[i
])
1108 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
1111 kfree(mdp
->tx_skbuff
);
1112 mdp
->tx_skbuff
= NULL
;
1115 /* format skb and descriptor buffer */
1116 static void sh_eth_ring_format(struct net_device
*ndev
)
1118 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1120 struct sk_buff
*skb
;
1121 struct sh_eth_rxdesc
*rxdesc
= NULL
;
1122 struct sh_eth_txdesc
*txdesc
= NULL
;
1123 int rx_ringsize
= sizeof(*rxdesc
) * mdp
->num_rx_ring
;
1124 int tx_ringsize
= sizeof(*txdesc
) * mdp
->num_tx_ring
;
1126 mdp
->cur_rx
= mdp
->cur_tx
= 0;
1127 mdp
->dirty_rx
= mdp
->dirty_tx
= 0;
1129 memset(mdp
->rx_ring
, 0, rx_ringsize
);
1131 /* build Rx ring buffer */
1132 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
1134 mdp
->rx_skbuff
[i
] = NULL
;
1135 skb
= netdev_alloc_skb(ndev
, mdp
->rx_buf_sz
);
1136 mdp
->rx_skbuff
[i
] = skb
;
1139 dma_map_single(&ndev
->dev
, skb
->data
, mdp
->rx_buf_sz
,
1141 sh_eth_set_receive_align(skb
);
1144 rxdesc
= &mdp
->rx_ring
[i
];
1145 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
1146 rxdesc
->status
= cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
1148 /* The size of the buffer is 16 byte boundary. */
1149 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
1150 /* Rx descriptor address set */
1152 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDLAR
);
1153 if (sh_eth_is_gether(mdp
))
1154 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDFAR
);
1158 mdp
->dirty_rx
= (u32
) (i
- mdp
->num_rx_ring
);
1160 /* Mark the last entry as wrapping the ring. */
1161 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RDEL
);
1163 memset(mdp
->tx_ring
, 0, tx_ringsize
);
1165 /* build Tx ring buffer */
1166 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
1167 mdp
->tx_skbuff
[i
] = NULL
;
1168 txdesc
= &mdp
->tx_ring
[i
];
1169 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
1170 txdesc
->buffer_length
= 0;
1172 /* Tx descriptor address set */
1173 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDLAR
);
1174 if (sh_eth_is_gether(mdp
))
1175 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDFAR
);
1179 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
1182 /* Get skb and descriptor buffer */
1183 static int sh_eth_ring_init(struct net_device
*ndev
)
1185 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1186 int rx_ringsize
, tx_ringsize
, ret
= 0;
1189 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1190 * card needs room to do 8 byte alignment, +2 so we can reserve
1191 * the first 2 bytes, and +16 gets room for the status word from the
1194 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
1195 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
1196 if (mdp
->cd
->rpadir
)
1197 mdp
->rx_buf_sz
+= NET_IP_ALIGN
;
1199 /* Allocate RX and TX skb rings */
1200 mdp
->rx_skbuff
= kmalloc_array(mdp
->num_rx_ring
,
1201 sizeof(*mdp
->rx_skbuff
), GFP_KERNEL
);
1202 if (!mdp
->rx_skbuff
) {
1207 mdp
->tx_skbuff
= kmalloc_array(mdp
->num_tx_ring
,
1208 sizeof(*mdp
->tx_skbuff
), GFP_KERNEL
);
1209 if (!mdp
->tx_skbuff
) {
1214 /* Allocate all Rx descriptors. */
1215 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * mdp
->num_rx_ring
;
1216 mdp
->rx_ring
= dma_alloc_coherent(NULL
, rx_ringsize
, &mdp
->rx_desc_dma
,
1218 if (!mdp
->rx_ring
) {
1220 goto desc_ring_free
;
1225 /* Allocate all Tx descriptors. */
1226 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * mdp
->num_tx_ring
;
1227 mdp
->tx_ring
= dma_alloc_coherent(NULL
, tx_ringsize
, &mdp
->tx_desc_dma
,
1229 if (!mdp
->tx_ring
) {
1231 goto desc_ring_free
;
1236 /* free DMA buffer */
1237 dma_free_coherent(NULL
, rx_ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
1240 /* Free Rx and Tx skb ring buffer */
1241 sh_eth_ring_free(ndev
);
1242 mdp
->tx_ring
= NULL
;
1243 mdp
->rx_ring
= NULL
;
1248 static void sh_eth_free_dma_buffer(struct sh_eth_private
*mdp
)
1253 ringsize
= sizeof(struct sh_eth_rxdesc
) * mdp
->num_rx_ring
;
1254 dma_free_coherent(NULL
, ringsize
, mdp
->rx_ring
,
1256 mdp
->rx_ring
= NULL
;
1260 ringsize
= sizeof(struct sh_eth_txdesc
) * mdp
->num_tx_ring
;
1261 dma_free_coherent(NULL
, ringsize
, mdp
->tx_ring
,
1263 mdp
->tx_ring
= NULL
;
1267 static int sh_eth_dev_init(struct net_device
*ndev
, bool start
)
1270 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1274 ret
= sh_eth_reset(ndev
);
1278 /* Descriptor format */
1279 sh_eth_ring_format(ndev
);
1280 if (mdp
->cd
->rpadir
)
1281 sh_eth_write(ndev
, mdp
->cd
->rpadir_value
, RPADIR
);
1283 /* all sh_eth int mask */
1284 sh_eth_write(ndev
, 0, EESIPR
);
1286 #if defined(__LITTLE_ENDIAN)
1287 if (mdp
->cd
->hw_swap
)
1288 sh_eth_write(ndev
, EDMR_EL
, EDMR
);
1291 sh_eth_write(ndev
, 0, EDMR
);
1294 sh_eth_write(ndev
, mdp
->cd
->fdr_value
, FDR
);
1295 sh_eth_write(ndev
, 0, TFTR
);
1297 /* Frame recv control */
1298 sh_eth_write(ndev
, mdp
->cd
->rmcr_value
, RMCR
);
1300 sh_eth_write(ndev
, DESC_I_RINT8
| DESC_I_RINT5
| DESC_I_TINT2
, TRSCER
);
1303 sh_eth_write(ndev
, 0x800, BCULR
); /* Burst sycle set */
1305 sh_eth_write(ndev
, mdp
->cd
->fcftr_value
, FCFTR
);
1307 if (!mdp
->cd
->no_trimd
)
1308 sh_eth_write(ndev
, 0, TRIMD
);
1310 /* Recv frame limit set register */
1311 sh_eth_write(ndev
, ndev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
+ ETH_FCS_LEN
,
1314 sh_eth_write(ndev
, sh_eth_read(ndev
, EESR
), EESR
);
1316 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1318 /* PAUSE Prohibition */
1319 val
= (sh_eth_read(ndev
, ECMR
) & ECMR_DM
) |
1320 ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) | ECMR_TE
| ECMR_RE
;
1322 sh_eth_write(ndev
, val
, ECMR
);
1324 if (mdp
->cd
->set_rate
)
1325 mdp
->cd
->set_rate(ndev
);
1327 /* E-MAC Status Register clear */
1328 sh_eth_write(ndev
, mdp
->cd
->ecsr_value
, ECSR
);
1330 /* E-MAC Interrupt Enable register */
1332 sh_eth_write(ndev
, mdp
->cd
->ecsipr_value
, ECSIPR
);
1334 /* Set MAC address */
1335 update_mac_address(ndev
);
1339 sh_eth_write(ndev
, APR_AP
, APR
);
1341 sh_eth_write(ndev
, MPR_MP
, MPR
);
1342 if (mdp
->cd
->tpauser
)
1343 sh_eth_write(ndev
, TPAUSER_UNLIMITED
, TPAUSER
);
1346 /* Setting the Rx mode will start the Rx process. */
1347 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1349 netif_start_queue(ndev
);
1356 /* free Tx skb function */
1357 static int sh_eth_txfree(struct net_device
*ndev
)
1359 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1360 struct sh_eth_txdesc
*txdesc
;
1364 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
1365 entry
= mdp
->dirty_tx
% mdp
->num_tx_ring
;
1366 txdesc
= &mdp
->tx_ring
[entry
];
1367 if (txdesc
->status
& cpu_to_edmac(mdp
, TD_TACT
))
1369 /* Free the original skb. */
1370 if (mdp
->tx_skbuff
[entry
]) {
1371 dma_unmap_single(&ndev
->dev
, txdesc
->addr
,
1372 txdesc
->buffer_length
, DMA_TO_DEVICE
);
1373 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
1374 mdp
->tx_skbuff
[entry
] = NULL
;
1377 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
1378 if (entry
>= mdp
->num_tx_ring
- 1)
1379 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
1381 ndev
->stats
.tx_packets
++;
1382 ndev
->stats
.tx_bytes
+= txdesc
->buffer_length
;
1387 /* Packet receive function */
1388 static int sh_eth_rx(struct net_device
*ndev
, u32 intr_status
)
1390 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1391 struct sh_eth_rxdesc
*rxdesc
;
1393 int entry
= mdp
->cur_rx
% mdp
->num_rx_ring
;
1394 int boguscnt
= (mdp
->dirty_rx
+ mdp
->num_rx_ring
) - mdp
->cur_rx
;
1395 struct sk_buff
*skb
;
1399 rxdesc
= &mdp
->rx_ring
[entry
];
1400 while (!(rxdesc
->status
& cpu_to_edmac(mdp
, RD_RACT
))) {
1401 desc_status
= edmac_to_cpu(mdp
, rxdesc
->status
);
1402 pkt_len
= rxdesc
->frame_length
;
1407 if (!(desc_status
& RDFEND
))
1408 ndev
->stats
.rx_length_errors
++;
1410 #if defined(CONFIG_ARCH_R8A7740)
1412 * In case of almost all GETHER/ETHERs, the Receive Frame State
1413 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1414 * bit 0. However, in case of the R8A7740's GETHER, the RFS
1415 * bits are from bit 25 to bit 16. So, the driver needs right
1421 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
1422 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
1423 ndev
->stats
.rx_errors
++;
1424 if (desc_status
& RD_RFS1
)
1425 ndev
->stats
.rx_crc_errors
++;
1426 if (desc_status
& RD_RFS2
)
1427 ndev
->stats
.rx_frame_errors
++;
1428 if (desc_status
& RD_RFS3
)
1429 ndev
->stats
.rx_length_errors
++;
1430 if (desc_status
& RD_RFS4
)
1431 ndev
->stats
.rx_length_errors
++;
1432 if (desc_status
& RD_RFS6
)
1433 ndev
->stats
.rx_missed_errors
++;
1434 if (desc_status
& RD_RFS10
)
1435 ndev
->stats
.rx_over_errors
++;
1437 if (!mdp
->cd
->hw_swap
)
1439 phys_to_virt(ALIGN(rxdesc
->addr
, 4)),
1441 skb
= mdp
->rx_skbuff
[entry
];
1442 mdp
->rx_skbuff
[entry
] = NULL
;
1443 if (mdp
->cd
->rpadir
)
1444 skb_reserve(skb
, NET_IP_ALIGN
);
1445 skb_put(skb
, pkt_len
);
1446 skb
->protocol
= eth_type_trans(skb
, ndev
);
1448 ndev
->stats
.rx_packets
++;
1449 ndev
->stats
.rx_bytes
+= pkt_len
;
1451 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RACT
);
1452 entry
= (++mdp
->cur_rx
) % mdp
->num_rx_ring
;
1453 rxdesc
= &mdp
->rx_ring
[entry
];
1456 /* Refill the Rx ring buffers. */
1457 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
1458 entry
= mdp
->dirty_rx
% mdp
->num_rx_ring
;
1459 rxdesc
= &mdp
->rx_ring
[entry
];
1460 /* The size of the buffer is 16 byte boundary. */
1461 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
1463 if (mdp
->rx_skbuff
[entry
] == NULL
) {
1464 skb
= netdev_alloc_skb(ndev
, mdp
->rx_buf_sz
);
1465 mdp
->rx_skbuff
[entry
] = skb
;
1467 break; /* Better luck next round. */
1468 dma_map_single(&ndev
->dev
, skb
->data
, mdp
->rx_buf_sz
,
1470 sh_eth_set_receive_align(skb
);
1472 skb_checksum_none_assert(skb
);
1473 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
1475 if (entry
>= mdp
->num_rx_ring
- 1)
1477 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
| RD_RDEL
);
1480 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
1483 /* Restart Rx engine if stopped. */
1484 /* If we don't need to check status, don't. -KDU */
1485 if (!(sh_eth_read(ndev
, EDRRR
) & EDRRR_R
)) {
1486 /* fix the values for the next receiving if RDE is set */
1487 if (intr_status
& EESR_RDE
)
1488 mdp
->cur_rx
= mdp
->dirty_rx
=
1489 (sh_eth_read(ndev
, RDFAR
) -
1490 sh_eth_read(ndev
, RDLAR
)) >> 4;
1491 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1497 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
)
1499 /* disable tx and rx */
1500 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) &
1501 ~(ECMR_RE
| ECMR_TE
), ECMR
);
1504 static void sh_eth_rcv_snd_enable(struct net_device
*ndev
)
1506 /* enable tx and rx */
1507 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) |
1508 (ECMR_RE
| ECMR_TE
), ECMR
);
1511 /* error control function */
1512 static void sh_eth_error(struct net_device
*ndev
, int intr_status
)
1514 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1519 if (intr_status
& EESR_ECI
) {
1520 felic_stat
= sh_eth_read(ndev
, ECSR
);
1521 sh_eth_write(ndev
, felic_stat
, ECSR
); /* clear int */
1522 if (felic_stat
& ECSR_ICD
)
1523 ndev
->stats
.tx_carrier_errors
++;
1524 if (felic_stat
& ECSR_LCHNG
) {
1526 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
) {
1529 link_stat
= (sh_eth_read(ndev
, PSR
));
1530 if (mdp
->ether_link_active_low
)
1531 link_stat
= ~link_stat
;
1533 if (!(link_stat
& PHY_ST_LINK
))
1534 sh_eth_rcv_snd_disable(ndev
);
1537 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) &
1538 ~DMAC_M_ECI
, EESIPR
);
1540 sh_eth_write(ndev
, sh_eth_read(ndev
, ECSR
),
1542 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) |
1543 DMAC_M_ECI
, EESIPR
);
1544 /* enable tx and rx */
1545 sh_eth_rcv_snd_enable(ndev
);
1551 if (intr_status
& EESR_TWB
) {
1552 /* Write buck end. unused write back interrupt */
1553 if (intr_status
& EESR_TABT
) /* Transmit Abort int */
1554 ndev
->stats
.tx_aborted_errors
++;
1555 if (netif_msg_tx_err(mdp
))
1556 dev_err(&ndev
->dev
, "Transmit Abort\n");
1559 if (intr_status
& EESR_RABT
) {
1560 /* Receive Abort int */
1561 if (intr_status
& EESR_RFRMER
) {
1562 /* Receive Frame Overflow int */
1563 ndev
->stats
.rx_frame_errors
++;
1564 if (netif_msg_rx_err(mdp
))
1565 dev_err(&ndev
->dev
, "Receive Abort\n");
1569 if (intr_status
& EESR_TDE
) {
1570 /* Transmit Descriptor Empty int */
1571 ndev
->stats
.tx_fifo_errors
++;
1572 if (netif_msg_tx_err(mdp
))
1573 dev_err(&ndev
->dev
, "Transmit Descriptor Empty\n");
1576 if (intr_status
& EESR_TFE
) {
1577 /* FIFO under flow */
1578 ndev
->stats
.tx_fifo_errors
++;
1579 if (netif_msg_tx_err(mdp
))
1580 dev_err(&ndev
->dev
, "Transmit FIFO Under flow\n");
1583 if (intr_status
& EESR_RDE
) {
1584 /* Receive Descriptor Empty int */
1585 ndev
->stats
.rx_over_errors
++;
1587 if (netif_msg_rx_err(mdp
))
1588 dev_err(&ndev
->dev
, "Receive Descriptor Empty\n");
1591 if (intr_status
& EESR_RFE
) {
1592 /* Receive FIFO Overflow int */
1593 ndev
->stats
.rx_fifo_errors
++;
1594 if (netif_msg_rx_err(mdp
))
1595 dev_err(&ndev
->dev
, "Receive FIFO Overflow\n");
1598 if (!mdp
->cd
->no_ade
&& (intr_status
& EESR_ADE
)) {
1600 ndev
->stats
.tx_fifo_errors
++;
1601 if (netif_msg_tx_err(mdp
))
1602 dev_err(&ndev
->dev
, "Address Error\n");
1605 mask
= EESR_TWB
| EESR_TABT
| EESR_ADE
| EESR_TDE
| EESR_TFE
;
1606 if (mdp
->cd
->no_ade
)
1608 if (intr_status
& mask
) {
1610 u32 edtrr
= sh_eth_read(ndev
, EDTRR
);
1612 dev_err(&ndev
->dev
, "TX error. status=%8.8x cur_tx=%8.8x ",
1613 intr_status
, mdp
->cur_tx
);
1614 dev_err(&ndev
->dev
, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1615 mdp
->dirty_tx
, (u32
) ndev
->state
, edtrr
);
1616 /* dirty buffer free */
1617 sh_eth_txfree(ndev
);
1620 if (edtrr
^ sh_eth_get_edtrr_trns(mdp
)) {
1622 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1625 netif_wake_queue(ndev
);
1629 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
1631 struct net_device
*ndev
= netdev
;
1632 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1633 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
1634 irqreturn_t ret
= IRQ_NONE
;
1635 unsigned long intr_status
;
1637 spin_lock(&mdp
->lock
);
1639 /* Get interrupt status */
1640 intr_status
= sh_eth_read(ndev
, EESR
);
1641 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1642 * enabled since it's the one that comes thru regardless of the mask,
1643 * and we need to fully handle it in sh_eth_error() in order to quench
1644 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1646 intr_status
&= sh_eth_read(ndev
, EESIPR
) | DMAC_M_ECI
;
1647 /* Clear interrupt */
1648 if (intr_status
& (EESR_FRC
| EESR_RMAF
| EESR_RRF
|
1649 EESR_RTLF
| EESR_RTSF
| EESR_PRE
| EESR_CERF
|
1650 cd
->tx_check
| cd
->eesr_err_check
)) {
1651 sh_eth_write(ndev
, intr_status
, EESR
);
1656 if (intr_status
& (EESR_FRC
| /* Frame recv*/
1657 EESR_RMAF
| /* Multi cast address recv*/
1658 EESR_RRF
| /* Bit frame recv */
1659 EESR_RTLF
| /* Long frame recv*/
1660 EESR_RTSF
| /* short frame recv */
1661 EESR_PRE
| /* PHY-LSI recv error */
1662 EESR_CERF
)){ /* recv frame CRC error */
1663 sh_eth_rx(ndev
, intr_status
);
1667 if (intr_status
& cd
->tx_check
) {
1668 sh_eth_txfree(ndev
);
1669 netif_wake_queue(ndev
);
1672 if (intr_status
& cd
->eesr_err_check
)
1673 sh_eth_error(ndev
, intr_status
);
1676 spin_unlock(&mdp
->lock
);
1681 /* PHY state control function */
1682 static void sh_eth_adjust_link(struct net_device
*ndev
)
1684 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1685 struct phy_device
*phydev
= mdp
->phydev
;
1689 if (phydev
->duplex
!= mdp
->duplex
) {
1691 mdp
->duplex
= phydev
->duplex
;
1692 if (mdp
->cd
->set_duplex
)
1693 mdp
->cd
->set_duplex(ndev
);
1696 if (phydev
->speed
!= mdp
->speed
) {
1698 mdp
->speed
= phydev
->speed
;
1699 if (mdp
->cd
->set_rate
)
1700 mdp
->cd
->set_rate(ndev
);
1704 (sh_eth_read(ndev
, ECMR
) & ~ECMR_TXF
), ECMR
);
1706 mdp
->link
= phydev
->link
;
1707 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1708 sh_eth_rcv_snd_enable(ndev
);
1710 } else if (mdp
->link
) {
1715 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1716 sh_eth_rcv_snd_disable(ndev
);
1719 if (new_state
&& netif_msg_link(mdp
))
1720 phy_print_status(phydev
);
1723 /* PHY init function */
1724 static int sh_eth_phy_init(struct net_device
*ndev
)
1726 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1727 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1728 struct phy_device
*phydev
= NULL
;
1730 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
,
1731 mdp
->mii_bus
->id
, mdp
->phy_id
);
1737 /* Try connect to PHY */
1738 phydev
= phy_connect(ndev
, phy_id
, sh_eth_adjust_link
,
1739 mdp
->phy_interface
);
1740 if (IS_ERR(phydev
)) {
1741 dev_err(&ndev
->dev
, "phy_connect failed\n");
1742 return PTR_ERR(phydev
);
1745 dev_info(&ndev
->dev
, "attached phy %i to driver %s\n",
1746 phydev
->addr
, phydev
->drv
->name
);
1748 mdp
->phydev
= phydev
;
1753 /* PHY control start function */
1754 static int sh_eth_phy_start(struct net_device
*ndev
)
1756 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1759 ret
= sh_eth_phy_init(ndev
);
1763 /* reset phy - this also wakes it from PDOWN */
1764 phy_write(mdp
->phydev
, MII_BMCR
, BMCR_RESET
);
1765 phy_start(mdp
->phydev
);
1770 static int sh_eth_get_settings(struct net_device
*ndev
,
1771 struct ethtool_cmd
*ecmd
)
1773 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1774 unsigned long flags
;
1777 spin_lock_irqsave(&mdp
->lock
, flags
);
1778 ret
= phy_ethtool_gset(mdp
->phydev
, ecmd
);
1779 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1784 static int sh_eth_set_settings(struct net_device
*ndev
,
1785 struct ethtool_cmd
*ecmd
)
1787 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1788 unsigned long flags
;
1791 spin_lock_irqsave(&mdp
->lock
, flags
);
1793 /* disable tx and rx */
1794 sh_eth_rcv_snd_disable(ndev
);
1796 ret
= phy_ethtool_sset(mdp
->phydev
, ecmd
);
1800 if (ecmd
->duplex
== DUPLEX_FULL
)
1805 if (mdp
->cd
->set_duplex
)
1806 mdp
->cd
->set_duplex(ndev
);
1811 /* enable tx and rx */
1812 sh_eth_rcv_snd_enable(ndev
);
1814 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1819 static int sh_eth_nway_reset(struct net_device
*ndev
)
1821 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1822 unsigned long flags
;
1825 spin_lock_irqsave(&mdp
->lock
, flags
);
1826 ret
= phy_start_aneg(mdp
->phydev
);
1827 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1832 static u32
sh_eth_get_msglevel(struct net_device
*ndev
)
1834 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1835 return mdp
->msg_enable
;
1838 static void sh_eth_set_msglevel(struct net_device
*ndev
, u32 value
)
1840 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1841 mdp
->msg_enable
= value
;
1844 static const char sh_eth_gstrings_stats
[][ETH_GSTRING_LEN
] = {
1845 "rx_current", "tx_current",
1846 "rx_dirty", "tx_dirty",
1848 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1850 static int sh_eth_get_sset_count(struct net_device
*netdev
, int sset
)
1854 return SH_ETH_STATS_LEN
;
1860 static void sh_eth_get_ethtool_stats(struct net_device
*ndev
,
1861 struct ethtool_stats
*stats
, u64
*data
)
1863 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1866 /* device-specific stats */
1867 data
[i
++] = mdp
->cur_rx
;
1868 data
[i
++] = mdp
->cur_tx
;
1869 data
[i
++] = mdp
->dirty_rx
;
1870 data
[i
++] = mdp
->dirty_tx
;
1873 static void sh_eth_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1875 switch (stringset
) {
1877 memcpy(data
, *sh_eth_gstrings_stats
,
1878 sizeof(sh_eth_gstrings_stats
));
1883 static void sh_eth_get_ringparam(struct net_device
*ndev
,
1884 struct ethtool_ringparam
*ring
)
1886 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1888 ring
->rx_max_pending
= RX_RING_MAX
;
1889 ring
->tx_max_pending
= TX_RING_MAX
;
1890 ring
->rx_pending
= mdp
->num_rx_ring
;
1891 ring
->tx_pending
= mdp
->num_tx_ring
;
1894 static int sh_eth_set_ringparam(struct net_device
*ndev
,
1895 struct ethtool_ringparam
*ring
)
1897 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1900 if (ring
->tx_pending
> TX_RING_MAX
||
1901 ring
->rx_pending
> RX_RING_MAX
||
1902 ring
->tx_pending
< TX_RING_MIN
||
1903 ring
->rx_pending
< RX_RING_MIN
)
1905 if (ring
->rx_mini_pending
|| ring
->rx_jumbo_pending
)
1908 if (netif_running(ndev
)) {
1909 netif_tx_disable(ndev
);
1910 /* Disable interrupts by clearing the interrupt mask. */
1911 sh_eth_write(ndev
, 0x0000, EESIPR
);
1912 /* Stop the chip's Tx and Rx processes. */
1913 sh_eth_write(ndev
, 0, EDTRR
);
1914 sh_eth_write(ndev
, 0, EDRRR
);
1915 synchronize_irq(ndev
->irq
);
1918 /* Free all the skbuffs in the Rx queue. */
1919 sh_eth_ring_free(ndev
);
1920 /* Free DMA buffer */
1921 sh_eth_free_dma_buffer(mdp
);
1923 /* Set new parameters */
1924 mdp
->num_rx_ring
= ring
->rx_pending
;
1925 mdp
->num_tx_ring
= ring
->tx_pending
;
1927 ret
= sh_eth_ring_init(ndev
);
1929 dev_err(&ndev
->dev
, "%s: sh_eth_ring_init failed.\n", __func__
);
1932 ret
= sh_eth_dev_init(ndev
, false);
1934 dev_err(&ndev
->dev
, "%s: sh_eth_dev_init failed.\n", __func__
);
1938 if (netif_running(ndev
)) {
1939 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1940 /* Setting the Rx mode will start the Rx process. */
1941 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1942 netif_wake_queue(ndev
);
1948 static const struct ethtool_ops sh_eth_ethtool_ops
= {
1949 .get_settings
= sh_eth_get_settings
,
1950 .set_settings
= sh_eth_set_settings
,
1951 .nway_reset
= sh_eth_nway_reset
,
1952 .get_msglevel
= sh_eth_get_msglevel
,
1953 .set_msglevel
= sh_eth_set_msglevel
,
1954 .get_link
= ethtool_op_get_link
,
1955 .get_strings
= sh_eth_get_strings
,
1956 .get_ethtool_stats
= sh_eth_get_ethtool_stats
,
1957 .get_sset_count
= sh_eth_get_sset_count
,
1958 .get_ringparam
= sh_eth_get_ringparam
,
1959 .set_ringparam
= sh_eth_set_ringparam
,
1962 /* network device open function */
1963 static int sh_eth_open(struct net_device
*ndev
)
1966 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1968 pm_runtime_get_sync(&mdp
->pdev
->dev
);
1970 ret
= request_irq(ndev
->irq
, sh_eth_interrupt
,
1971 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1972 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1973 defined(CONFIG_CPU_SUBTYPE_SH7757)
1980 dev_err(&ndev
->dev
, "Can not assign IRQ number\n");
1984 /* Descriptor set */
1985 ret
= sh_eth_ring_init(ndev
);
1990 ret
= sh_eth_dev_init(ndev
, true);
1994 /* PHY control start*/
1995 ret
= sh_eth_phy_start(ndev
);
2002 free_irq(ndev
->irq
, ndev
);
2003 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2007 /* Timeout function */
2008 static void sh_eth_tx_timeout(struct net_device
*ndev
)
2010 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2011 struct sh_eth_rxdesc
*rxdesc
;
2014 netif_stop_queue(ndev
);
2016 if (netif_msg_timer(mdp
))
2017 dev_err(&ndev
->dev
, "%s: transmit timed out, status %8.8x,"
2018 " resetting...\n", ndev
->name
, (int)sh_eth_read(ndev
, EESR
));
2020 /* tx_errors count up */
2021 ndev
->stats
.tx_errors
++;
2023 /* Free all the skbuffs in the Rx queue. */
2024 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
2025 rxdesc
= &mdp
->rx_ring
[i
];
2027 rxdesc
->addr
= 0xBADF00D0;
2028 if (mdp
->rx_skbuff
[i
])
2029 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
2030 mdp
->rx_skbuff
[i
] = NULL
;
2032 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
2033 if (mdp
->tx_skbuff
[i
])
2034 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
2035 mdp
->tx_skbuff
[i
] = NULL
;
2039 sh_eth_dev_init(ndev
, true);
2042 /* Packet transmit function */
2043 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
2045 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2046 struct sh_eth_txdesc
*txdesc
;
2048 unsigned long flags
;
2050 spin_lock_irqsave(&mdp
->lock
, flags
);
2051 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (mdp
->num_tx_ring
- 4)) {
2052 if (!sh_eth_txfree(ndev
)) {
2053 if (netif_msg_tx_queued(mdp
))
2054 dev_warn(&ndev
->dev
, "TxFD exhausted.\n");
2055 netif_stop_queue(ndev
);
2056 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2057 return NETDEV_TX_BUSY
;
2060 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2062 entry
= mdp
->cur_tx
% mdp
->num_tx_ring
;
2063 mdp
->tx_skbuff
[entry
] = skb
;
2064 txdesc
= &mdp
->tx_ring
[entry
];
2066 if (!mdp
->cd
->hw_swap
)
2067 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc
->addr
, 4)),
2069 txdesc
->addr
= dma_map_single(&ndev
->dev
, skb
->data
, skb
->len
,
2071 if (skb
->len
< ETHERSMALL
)
2072 txdesc
->buffer_length
= ETHERSMALL
;
2074 txdesc
->buffer_length
= skb
->len
;
2076 if (entry
>= mdp
->num_tx_ring
- 1)
2077 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
| TD_TDLE
);
2079 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
);
2083 if (!(sh_eth_read(ndev
, EDTRR
) & sh_eth_get_edtrr_trns(mdp
)))
2084 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
2086 return NETDEV_TX_OK
;
2089 /* device close function */
2090 static int sh_eth_close(struct net_device
*ndev
)
2092 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2094 netif_stop_queue(ndev
);
2096 /* Disable interrupts by clearing the interrupt mask. */
2097 sh_eth_write(ndev
, 0x0000, EESIPR
);
2099 /* Stop the chip's Tx and Rx processes. */
2100 sh_eth_write(ndev
, 0, EDTRR
);
2101 sh_eth_write(ndev
, 0, EDRRR
);
2103 /* PHY Disconnect */
2105 phy_stop(mdp
->phydev
);
2106 phy_disconnect(mdp
->phydev
);
2109 free_irq(ndev
->irq
, ndev
);
2111 /* Free all the skbuffs in the Rx queue. */
2112 sh_eth_ring_free(ndev
);
2114 /* free DMA buffer */
2115 sh_eth_free_dma_buffer(mdp
);
2117 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2122 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
2124 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2126 pm_runtime_get_sync(&mdp
->pdev
->dev
);
2128 ndev
->stats
.tx_dropped
+= sh_eth_read(ndev
, TROCR
);
2129 sh_eth_write(ndev
, 0, TROCR
); /* (write clear) */
2130 ndev
->stats
.collisions
+= sh_eth_read(ndev
, CDCR
);
2131 sh_eth_write(ndev
, 0, CDCR
); /* (write clear) */
2132 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, LCCR
);
2133 sh_eth_write(ndev
, 0, LCCR
); /* (write clear) */
2134 if (sh_eth_is_gether(mdp
)) {
2135 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CERCR
);
2136 sh_eth_write(ndev
, 0, CERCR
); /* (write clear) */
2137 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CEECR
);
2138 sh_eth_write(ndev
, 0, CEECR
); /* (write clear) */
2140 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CNDCR
);
2141 sh_eth_write(ndev
, 0, CNDCR
); /* (write clear) */
2143 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2145 return &ndev
->stats
;
2148 /* ioctl to device function */
2149 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
,
2152 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2153 struct phy_device
*phydev
= mdp
->phydev
;
2155 if (!netif_running(ndev
))
2161 return phy_mii_ioctl(phydev
, rq
, cmd
);
2164 #if defined(SH_ETH_HAS_TSU)
2165 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2166 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private
*mdp
,
2169 return sh_eth_tsu_get_offset(mdp
, TSU_POST1
) + (entry
/ 8 * 4);
2172 static u32
sh_eth_tsu_get_post_mask(int entry
)
2174 return 0x0f << (28 - ((entry
% 8) * 4));
2177 static u32
sh_eth_tsu_get_post_bit(struct sh_eth_private
*mdp
, int entry
)
2179 return (0x08 >> (mdp
->port
<< 1)) << (28 - ((entry
% 8) * 4));
2182 static void sh_eth_tsu_enable_cam_entry_post(struct net_device
*ndev
,
2185 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2189 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
2190 tmp
= ioread32(reg_offset
);
2191 iowrite32(tmp
| sh_eth_tsu_get_post_bit(mdp
, entry
), reg_offset
);
2194 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device
*ndev
,
2197 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2198 u32 post_mask
, ref_mask
, tmp
;
2201 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
2202 post_mask
= sh_eth_tsu_get_post_mask(entry
);
2203 ref_mask
= sh_eth_tsu_get_post_bit(mdp
, entry
) & ~post_mask
;
2205 tmp
= ioread32(reg_offset
);
2206 iowrite32(tmp
& ~post_mask
, reg_offset
);
2208 /* If other port enables, the function returns "true" */
2209 return tmp
& ref_mask
;
2212 static int sh_eth_tsu_busy(struct net_device
*ndev
)
2214 int timeout
= SH_ETH_TSU_TIMEOUT_MS
* 100;
2215 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2217 while ((sh_eth_tsu_read(mdp
, TSU_ADSBSY
) & TSU_ADSBSY_0
)) {
2221 dev_err(&ndev
->dev
, "%s: timeout\n", __func__
);
2229 static int sh_eth_tsu_write_entry(struct net_device
*ndev
, void *reg
,
2234 val
= addr
[0] << 24 | addr
[1] << 16 | addr
[2] << 8 | addr
[3];
2235 iowrite32(val
, reg
);
2236 if (sh_eth_tsu_busy(ndev
) < 0)
2239 val
= addr
[4] << 8 | addr
[5];
2240 iowrite32(val
, reg
+ 4);
2241 if (sh_eth_tsu_busy(ndev
) < 0)
2247 static void sh_eth_tsu_read_entry(void *reg
, u8
*addr
)
2251 val
= ioread32(reg
);
2252 addr
[0] = (val
>> 24) & 0xff;
2253 addr
[1] = (val
>> 16) & 0xff;
2254 addr
[2] = (val
>> 8) & 0xff;
2255 addr
[3] = val
& 0xff;
2256 val
= ioread32(reg
+ 4);
2257 addr
[4] = (val
>> 8) & 0xff;
2258 addr
[5] = val
& 0xff;
2262 static int sh_eth_tsu_find_entry(struct net_device
*ndev
, const u8
*addr
)
2264 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2265 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2267 u8 c_addr
[ETH_ALEN
];
2269 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
2270 sh_eth_tsu_read_entry(reg_offset
, c_addr
);
2271 if (memcmp(addr
, c_addr
, ETH_ALEN
) == 0)
2278 static int sh_eth_tsu_find_empty(struct net_device
*ndev
)
2283 memset(blank
, 0, sizeof(blank
));
2284 entry
= sh_eth_tsu_find_entry(ndev
, blank
);
2285 return (entry
< 0) ? -ENOMEM
: entry
;
2288 static int sh_eth_tsu_disable_cam_entry_table(struct net_device
*ndev
,
2291 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2292 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2296 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) &
2297 ~(1 << (31 - entry
)), TSU_TEN
);
2299 memset(blank
, 0, sizeof(blank
));
2300 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ entry
* 8, blank
);
2306 static int sh_eth_tsu_add_entry(struct net_device
*ndev
, const u8
*addr
)
2308 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2309 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2315 i
= sh_eth_tsu_find_entry(ndev
, addr
);
2317 /* No entry found, create one */
2318 i
= sh_eth_tsu_find_empty(ndev
);
2321 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ i
* 8, addr
);
2325 /* Enable the entry */
2326 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) |
2327 (1 << (31 - i
)), TSU_TEN
);
2330 /* Entry found or created, enable POST */
2331 sh_eth_tsu_enable_cam_entry_post(ndev
, i
);
2336 static int sh_eth_tsu_del_entry(struct net_device
*ndev
, const u8
*addr
)
2338 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2344 i
= sh_eth_tsu_find_entry(ndev
, addr
);
2347 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
2350 /* Disable the entry if both ports was disabled */
2351 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
2359 static int sh_eth_tsu_purge_all(struct net_device
*ndev
)
2361 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2364 if (unlikely(!mdp
->cd
->tsu
))
2367 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++) {
2368 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
2371 /* Disable the entry if both ports was disabled */
2372 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
2380 static void sh_eth_tsu_purge_mcast(struct net_device
*ndev
)
2382 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2384 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2387 if (unlikely(!mdp
->cd
->tsu
))
2390 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
2391 sh_eth_tsu_read_entry(reg_offset
, addr
);
2392 if (is_multicast_ether_addr(addr
))
2393 sh_eth_tsu_del_entry(ndev
, addr
);
2397 /* Multicast reception directions set */
2398 static void sh_eth_set_multicast_list(struct net_device
*ndev
)
2400 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2403 unsigned long flags
;
2405 spin_lock_irqsave(&mdp
->lock
, flags
);
2407 * Initial condition is MCT = 1, PRM = 0.
2408 * Depending on ndev->flags, set PRM or clear MCT
2410 ecmr_bits
= (sh_eth_read(ndev
, ECMR
) & ~ECMR_PRM
) | ECMR_MCT
;
2412 if (!(ndev
->flags
& IFF_MULTICAST
)) {
2413 sh_eth_tsu_purge_mcast(ndev
);
2416 if (ndev
->flags
& IFF_ALLMULTI
) {
2417 sh_eth_tsu_purge_mcast(ndev
);
2418 ecmr_bits
&= ~ECMR_MCT
;
2422 if (ndev
->flags
& IFF_PROMISC
) {
2423 sh_eth_tsu_purge_all(ndev
);
2424 ecmr_bits
= (ecmr_bits
& ~ECMR_MCT
) | ECMR_PRM
;
2425 } else if (mdp
->cd
->tsu
) {
2426 struct netdev_hw_addr
*ha
;
2427 netdev_for_each_mc_addr(ha
, ndev
) {
2428 if (mcast_all
&& is_multicast_ether_addr(ha
->addr
))
2431 if (sh_eth_tsu_add_entry(ndev
, ha
->addr
) < 0) {
2433 sh_eth_tsu_purge_mcast(ndev
);
2434 ecmr_bits
&= ~ECMR_MCT
;
2440 /* Normal, unicast/broadcast-only mode. */
2441 ecmr_bits
= (ecmr_bits
& ~ECMR_PRM
) | ECMR_MCT
;
2444 /* update the ethernet mode */
2445 sh_eth_write(ndev
, ecmr_bits
, ECMR
);
2447 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2450 static int sh_eth_get_vtag_index(struct sh_eth_private
*mdp
)
2458 static int sh_eth_vlan_rx_add_vid(struct net_device
*ndev
,
2459 __be16 proto
, u16 vid
)
2461 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2462 int vtag_reg_index
= sh_eth_get_vtag_index(mdp
);
2464 if (unlikely(!mdp
->cd
->tsu
))
2467 /* No filtering if vid = 0 */
2471 mdp
->vlan_num_ids
++;
2474 * The controller has one VLAN tag HW filter. So, if the filter is
2475 * already enabled, the driver disables it and the filte
2477 if (mdp
->vlan_num_ids
> 1) {
2478 /* disable VLAN filter */
2479 sh_eth_tsu_write(mdp
, 0, vtag_reg_index
);
2483 sh_eth_tsu_write(mdp
, TSU_VTAG_ENABLE
| (vid
& TSU_VTAG_VID_MASK
),
2489 static int sh_eth_vlan_rx_kill_vid(struct net_device
*ndev
,
2490 __be16 proto
, u16 vid
)
2492 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2493 int vtag_reg_index
= sh_eth_get_vtag_index(mdp
);
2495 if (unlikely(!mdp
->cd
->tsu
))
2498 /* No filtering if vid = 0 */
2502 mdp
->vlan_num_ids
--;
2503 sh_eth_tsu_write(mdp
, 0, vtag_reg_index
);
2507 #endif /* SH_ETH_HAS_TSU */
2509 /* SuperH's TSU register init function */
2510 static void sh_eth_tsu_init(struct sh_eth_private
*mdp
)
2512 sh_eth_tsu_write(mdp
, 0, TSU_FWEN0
); /* Disable forward(0->1) */
2513 sh_eth_tsu_write(mdp
, 0, TSU_FWEN1
); /* Disable forward(1->0) */
2514 sh_eth_tsu_write(mdp
, 0, TSU_FCM
); /* forward fifo 3k-3k */
2515 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL0
);
2516 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL1
);
2517 sh_eth_tsu_write(mdp
, 0, TSU_PRISL0
);
2518 sh_eth_tsu_write(mdp
, 0, TSU_PRISL1
);
2519 sh_eth_tsu_write(mdp
, 0, TSU_FWSL0
);
2520 sh_eth_tsu_write(mdp
, 0, TSU_FWSL1
);
2521 sh_eth_tsu_write(mdp
, TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, TSU_FWSLC
);
2522 if (sh_eth_is_gether(mdp
)) {
2523 sh_eth_tsu_write(mdp
, 0, TSU_QTAG0
); /* Disable QTAG(0->1) */
2524 sh_eth_tsu_write(mdp
, 0, TSU_QTAG1
); /* Disable QTAG(1->0) */
2526 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM0
); /* Disable QTAG(0->1) */
2527 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM1
); /* Disable QTAG(1->0) */
2529 sh_eth_tsu_write(mdp
, 0, TSU_FWSR
); /* all interrupt status clear */
2530 sh_eth_tsu_write(mdp
, 0, TSU_FWINMK
); /* Disable all interrupt */
2531 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
2532 sh_eth_tsu_write(mdp
, 0, TSU_POST1
); /* Disable CAM entry [ 0- 7] */
2533 sh_eth_tsu_write(mdp
, 0, TSU_POST2
); /* Disable CAM entry [ 8-15] */
2534 sh_eth_tsu_write(mdp
, 0, TSU_POST3
); /* Disable CAM entry [16-23] */
2535 sh_eth_tsu_write(mdp
, 0, TSU_POST4
); /* Disable CAM entry [24-31] */
2538 /* MDIO bus release function */
2539 static int sh_mdio_release(struct net_device
*ndev
)
2541 struct mii_bus
*bus
= dev_get_drvdata(&ndev
->dev
);
2543 /* unregister mdio bus */
2544 mdiobus_unregister(bus
);
2546 /* remove mdio bus info from net_device */
2547 dev_set_drvdata(&ndev
->dev
, NULL
);
2549 /* free bitbang info */
2550 free_mdio_bitbang(bus
);
2555 /* MDIO bus init function */
2556 static int sh_mdio_init(struct net_device
*ndev
, int id
,
2557 struct sh_eth_plat_data
*pd
)
2560 struct bb_info
*bitbang
;
2561 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2563 /* create bit control struct for PHY */
2564 bitbang
= devm_kzalloc(&ndev
->dev
, sizeof(struct bb_info
),
2572 bitbang
->addr
= mdp
->addr
+ mdp
->reg_offset
[PIR
];
2573 bitbang
->set_gate
= pd
->set_mdio_gate
;
2574 bitbang
->mdi_msk
= PIR_MDI
;
2575 bitbang
->mdo_msk
= PIR_MDO
;
2576 bitbang
->mmd_msk
= PIR_MMD
;
2577 bitbang
->mdc_msk
= PIR_MDC
;
2578 bitbang
->ctrl
.ops
= &bb_ops
;
2580 /* MII controller setting */
2581 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
2582 if (!mdp
->mii_bus
) {
2587 /* Hook up MII support for ethtool */
2588 mdp
->mii_bus
->name
= "sh_mii";
2589 mdp
->mii_bus
->parent
= &ndev
->dev
;
2590 snprintf(mdp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
2591 mdp
->pdev
->name
, id
);
2594 mdp
->mii_bus
->irq
= devm_kzalloc(&ndev
->dev
,
2595 sizeof(int) * PHY_MAX_ADDR
,
2597 if (!mdp
->mii_bus
->irq
) {
2602 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
2603 mdp
->mii_bus
->irq
[i
] = PHY_POLL
;
2605 /* register mdio bus */
2606 ret
= mdiobus_register(mdp
->mii_bus
);
2610 dev_set_drvdata(&ndev
->dev
, mdp
->mii_bus
);
2615 free_mdio_bitbang(mdp
->mii_bus
);
2621 static const u16
*sh_eth_get_register_offset(int register_type
)
2623 const u16
*reg_offset
= NULL
;
2625 switch (register_type
) {
2626 case SH_ETH_REG_GIGABIT
:
2627 reg_offset
= sh_eth_offset_gigabit
;
2629 case SH_ETH_REG_FAST_RCAR
:
2630 reg_offset
= sh_eth_offset_fast_rcar
;
2632 case SH_ETH_REG_FAST_SH4
:
2633 reg_offset
= sh_eth_offset_fast_sh4
;
2635 case SH_ETH_REG_FAST_SH3_SH2
:
2636 reg_offset
= sh_eth_offset_fast_sh3_sh2
;
2639 pr_err("Unknown register type (%d)\n", register_type
);
2646 static const struct net_device_ops sh_eth_netdev_ops
= {
2647 .ndo_open
= sh_eth_open
,
2648 .ndo_stop
= sh_eth_close
,
2649 .ndo_start_xmit
= sh_eth_start_xmit
,
2650 .ndo_get_stats
= sh_eth_get_stats
,
2651 #if defined(SH_ETH_HAS_TSU)
2652 .ndo_set_rx_mode
= sh_eth_set_multicast_list
,
2653 .ndo_vlan_rx_add_vid
= sh_eth_vlan_rx_add_vid
,
2654 .ndo_vlan_rx_kill_vid
= sh_eth_vlan_rx_kill_vid
,
2656 .ndo_tx_timeout
= sh_eth_tx_timeout
,
2657 .ndo_do_ioctl
= sh_eth_do_ioctl
,
2658 .ndo_validate_addr
= eth_validate_addr
,
2659 .ndo_set_mac_address
= eth_mac_addr
,
2660 .ndo_change_mtu
= eth_change_mtu
,
2663 static int sh_eth_drv_probe(struct platform_device
*pdev
)
2666 struct resource
*res
;
2667 struct net_device
*ndev
= NULL
;
2668 struct sh_eth_private
*mdp
= NULL
;
2669 struct sh_eth_plat_data
*pd
= pdev
->dev
.platform_data
;
2672 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2673 if (unlikely(res
== NULL
)) {
2674 dev_err(&pdev
->dev
, "invalid resource\n");
2679 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
2685 /* The sh Ether-specific entries in the device structure. */
2686 ndev
->base_addr
= res
->start
;
2692 ret
= platform_get_irq(pdev
, 0);
2699 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2701 /* Fill in the fields of the device structure with ethernet values. */
2704 mdp
= netdev_priv(ndev
);
2705 mdp
->num_tx_ring
= TX_RING_SIZE
;
2706 mdp
->num_rx_ring
= RX_RING_SIZE
;
2707 mdp
->addr
= devm_ioremap_resource(&pdev
->dev
, res
);
2708 if (IS_ERR(mdp
->addr
)) {
2709 ret
= PTR_ERR(mdp
->addr
);
2713 spin_lock_init(&mdp
->lock
);
2715 pm_runtime_enable(&pdev
->dev
);
2716 pm_runtime_resume(&pdev
->dev
);
2719 mdp
->phy_id
= pd
->phy
;
2720 mdp
->phy_interface
= pd
->phy_interface
;
2722 mdp
->edmac_endian
= pd
->edmac_endian
;
2723 mdp
->no_ether_link
= pd
->no_ether_link
;
2724 mdp
->ether_link_active_low
= pd
->ether_link_active_low
;
2725 mdp
->reg_offset
= sh_eth_get_register_offset(pd
->register_type
);
2728 #if defined(SH_ETH_HAS_BOTH_MODULES)
2729 mdp
->cd
= sh_eth_get_cpu_data(mdp
);
2731 mdp
->cd
= &sh_eth_my_cpu_data
;
2733 sh_eth_set_default_cpu_data(mdp
->cd
);
2736 ndev
->netdev_ops
= &sh_eth_netdev_ops
;
2737 SET_ETHTOOL_OPS(ndev
, &sh_eth_ethtool_ops
);
2738 ndev
->watchdog_timeo
= TX_TIMEOUT
;
2740 /* debug message level */
2741 mdp
->msg_enable
= SH_ETH_DEF_MSG_ENABLE
;
2743 /* read and set MAC address */
2744 read_mac_address(ndev
, pd
->mac_addr
);
2745 if (!is_valid_ether_addr(ndev
->dev_addr
)) {
2746 dev_warn(&pdev
->dev
,
2747 "no valid MAC address supplied, using a random one.\n");
2748 eth_hw_addr_random(ndev
);
2751 /* ioremap the TSU registers */
2753 struct resource
*rtsu
;
2754 rtsu
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2755 mdp
->tsu_addr
= devm_ioremap_resource(&pdev
->dev
, rtsu
);
2756 if (IS_ERR(mdp
->tsu_addr
)) {
2757 ret
= PTR_ERR(mdp
->tsu_addr
);
2760 mdp
->port
= devno
% 2;
2761 ndev
->features
= NETIF_F_HW_VLAN_CTAG_FILTER
;
2764 /* initialize first or needed device */
2765 if (!devno
|| pd
->needs_init
) {
2766 if (mdp
->cd
->chip_reset
)
2767 mdp
->cd
->chip_reset(ndev
);
2770 /* TSU init (Init only)*/
2771 sh_eth_tsu_init(mdp
);
2775 /* network device register */
2776 ret
= register_netdev(ndev
);
2781 ret
= sh_mdio_init(ndev
, pdev
->id
, pd
);
2783 goto out_unregister
;
2785 /* print device information */
2786 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2787 (u32
)ndev
->base_addr
, ndev
->dev_addr
, ndev
->irq
);
2789 platform_set_drvdata(pdev
, ndev
);
2794 unregister_netdev(ndev
);
2805 static int sh_eth_drv_remove(struct platform_device
*pdev
)
2807 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2809 sh_mdio_release(ndev
);
2810 unregister_netdev(ndev
);
2811 pm_runtime_disable(&pdev
->dev
);
2813 platform_set_drvdata(pdev
, NULL
);
2818 static int sh_eth_runtime_nop(struct device
*dev
)
2821 * Runtime PM callback shared between ->runtime_suspend()
2822 * and ->runtime_resume(). Simply returns success.
2824 * This driver re-initializes all registers after
2825 * pm_runtime_get_sync() anyway so there is no need
2826 * to save and restore registers here.
2831 static struct dev_pm_ops sh_eth_dev_pm_ops
= {
2832 .runtime_suspend
= sh_eth_runtime_nop
,
2833 .runtime_resume
= sh_eth_runtime_nop
,
2836 static struct platform_driver sh_eth_driver
= {
2837 .probe
= sh_eth_drv_probe
,
2838 .remove
= sh_eth_drv_remove
,
2841 .pm
= &sh_eth_dev_pm_ops
,
2845 module_platform_driver(sh_eth_driver
);
2847 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2848 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2849 MODULE_LICENSE("GPL v2");