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x86: Move call to print_modules() out of show_regs()
[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.c
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2012 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/spinlock.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/etherdevice.h>
30 #include <linux/delay.h>
31 #include <linux/platform_device.h>
32 #include <linux/mdio-bitbang.h>
33 #include <linux/netdevice.h>
34 #include <linux/phy.h>
35 #include <linux/cache.h>
36 #include <linux/io.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/slab.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/clk.h>
42 #include <linux/sh_eth.h>
43
44 #include "sh_eth.h"
45
46 #define SH_ETH_DEF_MSG_ENABLE \
47 (NETIF_MSG_LINK | \
48 NETIF_MSG_TIMER | \
49 NETIF_MSG_RX_ERR| \
50 NETIF_MSG_TX_ERR)
51
52 /* There is CPU dependent code */
53 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
54 #define SH_ETH_RESET_DEFAULT 1
55 static void sh_eth_set_duplex(struct net_device *ndev)
56 {
57 struct sh_eth_private *mdp = netdev_priv(ndev);
58
59 if (mdp->duplex) /* Full */
60 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
61 else /* Half */
62 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
63 }
64
65 static void sh_eth_set_rate(struct net_device *ndev)
66 {
67 struct sh_eth_private *mdp = netdev_priv(ndev);
68
69 switch (mdp->speed) {
70 case 10: /* 10BASE */
71 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
72 break;
73 case 100:/* 100BASE */
74 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
75 break;
76 default:
77 break;
78 }
79 }
80
81 /* SH7724 */
82 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
83 .set_duplex = sh_eth_set_duplex,
84 .set_rate = sh_eth_set_rate,
85
86 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
87 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
88 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
89
90 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
91 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
92 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
93 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
94
95 .apr = 1,
96 .mpr = 1,
97 .tpauser = 1,
98 .hw_swap = 1,
99 .rpadir = 1,
100 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
101 };
102 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
103 #define SH_ETH_HAS_BOTH_MODULES 1
104 #define SH_ETH_HAS_TSU 1
105 static void sh_eth_set_duplex(struct net_device *ndev)
106 {
107 struct sh_eth_private *mdp = netdev_priv(ndev);
108
109 if (mdp->duplex) /* Full */
110 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
111 else /* Half */
112 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
113 }
114
115 static void sh_eth_set_rate(struct net_device *ndev)
116 {
117 struct sh_eth_private *mdp = netdev_priv(ndev);
118
119 switch (mdp->speed) {
120 case 10: /* 10BASE */
121 sh_eth_write(ndev, 0, RTRATE);
122 break;
123 case 100:/* 100BASE */
124 sh_eth_write(ndev, 1, RTRATE);
125 break;
126 default:
127 break;
128 }
129 }
130
131 /* SH7757 */
132 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
133 .set_duplex = sh_eth_set_duplex,
134 .set_rate = sh_eth_set_rate,
135
136 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
137 .rmcr_value = 0x00000001,
138
139 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
140 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
141 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
142 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
143
144 .apr = 1,
145 .mpr = 1,
146 .tpauser = 1,
147 .hw_swap = 1,
148 .no_ade = 1,
149 .rpadir = 1,
150 .rpadir_value = 2 << 16,
151 };
152
153 #define SH_GIGA_ETH_BASE 0xfee00000
154 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
155 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
156 static void sh_eth_chip_reset_giga(struct net_device *ndev)
157 {
158 int i;
159 unsigned long mahr[2], malr[2];
160
161 /* save MAHR and MALR */
162 for (i = 0; i < 2; i++) {
163 malr[i] = ioread32((void *)GIGA_MALR(i));
164 mahr[i] = ioread32((void *)GIGA_MAHR(i));
165 }
166
167 /* reset device */
168 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
169 mdelay(1);
170
171 /* restore MAHR and MALR */
172 for (i = 0; i < 2; i++) {
173 iowrite32(malr[i], (void *)GIGA_MALR(i));
174 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
175 }
176 }
177
178 static int sh_eth_is_gether(struct sh_eth_private *mdp);
179 static void sh_eth_reset(struct net_device *ndev)
180 {
181 struct sh_eth_private *mdp = netdev_priv(ndev);
182 int cnt = 100;
183
184 if (sh_eth_is_gether(mdp)) {
185 sh_eth_write(ndev, 0x03, EDSR);
186 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
187 EDMR);
188 while (cnt > 0) {
189 if (!(sh_eth_read(ndev, EDMR) & 0x3))
190 break;
191 mdelay(1);
192 cnt--;
193 }
194 if (cnt < 0)
195 printk(KERN_ERR "Device reset fail\n");
196
197 /* Table Init */
198 sh_eth_write(ndev, 0x0, TDLAR);
199 sh_eth_write(ndev, 0x0, TDFAR);
200 sh_eth_write(ndev, 0x0, TDFXR);
201 sh_eth_write(ndev, 0x0, TDFFR);
202 sh_eth_write(ndev, 0x0, RDLAR);
203 sh_eth_write(ndev, 0x0, RDFAR);
204 sh_eth_write(ndev, 0x0, RDFXR);
205 sh_eth_write(ndev, 0x0, RDFFR);
206 } else {
207 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
208 EDMR);
209 mdelay(3);
210 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
211 EDMR);
212 }
213 }
214
215 static void sh_eth_set_duplex_giga(struct net_device *ndev)
216 {
217 struct sh_eth_private *mdp = netdev_priv(ndev);
218
219 if (mdp->duplex) /* Full */
220 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
221 else /* Half */
222 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
223 }
224
225 static void sh_eth_set_rate_giga(struct net_device *ndev)
226 {
227 struct sh_eth_private *mdp = netdev_priv(ndev);
228
229 switch (mdp->speed) {
230 case 10: /* 10BASE */
231 sh_eth_write(ndev, 0x00000000, GECMR);
232 break;
233 case 100:/* 100BASE */
234 sh_eth_write(ndev, 0x00000010, GECMR);
235 break;
236 case 1000: /* 1000BASE */
237 sh_eth_write(ndev, 0x00000020, GECMR);
238 break;
239 default:
240 break;
241 }
242 }
243
244 /* SH7757(GETHERC) */
245 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
246 .chip_reset = sh_eth_chip_reset_giga,
247 .set_duplex = sh_eth_set_duplex_giga,
248 .set_rate = sh_eth_set_rate_giga,
249
250 .ecsr_value = ECSR_ICD | ECSR_MPD,
251 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
252 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
253
254 .tx_check = EESR_TC1 | EESR_FTC,
255 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
256 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
257 EESR_ECI,
258 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
259 EESR_TFE,
260 .fdr_value = 0x0000072f,
261 .rmcr_value = 0x00000001,
262
263 .apr = 1,
264 .mpr = 1,
265 .tpauser = 1,
266 .bculr = 1,
267 .hw_swap = 1,
268 .rpadir = 1,
269 .rpadir_value = 2 << 16,
270 .no_trimd = 1,
271 .no_ade = 1,
272 .tsu = 1,
273 };
274
275 static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
276 {
277 if (sh_eth_is_gether(mdp))
278 return &sh_eth_my_cpu_data_giga;
279 else
280 return &sh_eth_my_cpu_data;
281 }
282
283 #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
284 #define SH_ETH_HAS_TSU 1
285 static void sh_eth_reset_hw_crc(struct net_device *ndev);
286 static void sh_eth_chip_reset(struct net_device *ndev)
287 {
288 struct sh_eth_private *mdp = netdev_priv(ndev);
289
290 /* reset device */
291 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
292 mdelay(1);
293 }
294
295 static void sh_eth_reset(struct net_device *ndev)
296 {
297 int cnt = 100;
298
299 sh_eth_write(ndev, EDSR_ENALL, EDSR);
300 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
301 while (cnt > 0) {
302 if (!(sh_eth_read(ndev, EDMR) & 0x3))
303 break;
304 mdelay(1);
305 cnt--;
306 }
307 if (cnt == 0)
308 printk(KERN_ERR "Device reset fail\n");
309
310 /* Table Init */
311 sh_eth_write(ndev, 0x0, TDLAR);
312 sh_eth_write(ndev, 0x0, TDFAR);
313 sh_eth_write(ndev, 0x0, TDFXR);
314 sh_eth_write(ndev, 0x0, TDFFR);
315 sh_eth_write(ndev, 0x0, RDLAR);
316 sh_eth_write(ndev, 0x0, RDFAR);
317 sh_eth_write(ndev, 0x0, RDFXR);
318 sh_eth_write(ndev, 0x0, RDFFR);
319
320 /* Reset HW CRC register */
321 sh_eth_reset_hw_crc(ndev);
322 }
323
324 static void sh_eth_set_duplex(struct net_device *ndev)
325 {
326 struct sh_eth_private *mdp = netdev_priv(ndev);
327
328 if (mdp->duplex) /* Full */
329 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
330 else /* Half */
331 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
332 }
333
334 static void sh_eth_set_rate(struct net_device *ndev)
335 {
336 struct sh_eth_private *mdp = netdev_priv(ndev);
337
338 switch (mdp->speed) {
339 case 10: /* 10BASE */
340 sh_eth_write(ndev, GECMR_10, GECMR);
341 break;
342 case 100:/* 100BASE */
343 sh_eth_write(ndev, GECMR_100, GECMR);
344 break;
345 case 1000: /* 1000BASE */
346 sh_eth_write(ndev, GECMR_1000, GECMR);
347 break;
348 default:
349 break;
350 }
351 }
352
353 /* sh7763 */
354 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
355 .chip_reset = sh_eth_chip_reset,
356 .set_duplex = sh_eth_set_duplex,
357 .set_rate = sh_eth_set_rate,
358
359 .ecsr_value = ECSR_ICD | ECSR_MPD,
360 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
361 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
362
363 .tx_check = EESR_TC1 | EESR_FTC,
364 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
365 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
366 EESR_ECI,
367 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
368 EESR_TFE,
369
370 .apr = 1,
371 .mpr = 1,
372 .tpauser = 1,
373 .bculr = 1,
374 .hw_swap = 1,
375 .no_trimd = 1,
376 .no_ade = 1,
377 .tsu = 1,
378 #if defined(CONFIG_CPU_SUBTYPE_SH7734)
379 .hw_crc = 1,
380 #endif
381 };
382
383 static void sh_eth_reset_hw_crc(struct net_device *ndev)
384 {
385 if (sh_eth_my_cpu_data.hw_crc)
386 sh_eth_write(ndev, 0x0, CSMR);
387 }
388
389 #elif defined(CONFIG_ARCH_R8A7740)
390 #define SH_ETH_HAS_TSU 1
391 static void sh_eth_chip_reset(struct net_device *ndev)
392 {
393 struct sh_eth_private *mdp = netdev_priv(ndev);
394 unsigned long mii;
395
396 /* reset device */
397 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
398 mdelay(1);
399
400 switch (mdp->phy_interface) {
401 case PHY_INTERFACE_MODE_GMII:
402 mii = 2;
403 break;
404 case PHY_INTERFACE_MODE_MII:
405 mii = 1;
406 break;
407 case PHY_INTERFACE_MODE_RMII:
408 default:
409 mii = 0;
410 break;
411 }
412 sh_eth_write(ndev, mii, RMII_MII);
413 }
414
415 static void sh_eth_reset(struct net_device *ndev)
416 {
417 int cnt = 100;
418
419 sh_eth_write(ndev, EDSR_ENALL, EDSR);
420 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
421 while (cnt > 0) {
422 if (!(sh_eth_read(ndev, EDMR) & 0x3))
423 break;
424 mdelay(1);
425 cnt--;
426 }
427 if (cnt == 0)
428 printk(KERN_ERR "Device reset fail\n");
429
430 /* Table Init */
431 sh_eth_write(ndev, 0x0, TDLAR);
432 sh_eth_write(ndev, 0x0, TDFAR);
433 sh_eth_write(ndev, 0x0, TDFXR);
434 sh_eth_write(ndev, 0x0, TDFFR);
435 sh_eth_write(ndev, 0x0, RDLAR);
436 sh_eth_write(ndev, 0x0, RDFAR);
437 sh_eth_write(ndev, 0x0, RDFXR);
438 sh_eth_write(ndev, 0x0, RDFFR);
439 }
440
441 static void sh_eth_set_duplex(struct net_device *ndev)
442 {
443 struct sh_eth_private *mdp = netdev_priv(ndev);
444
445 if (mdp->duplex) /* Full */
446 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
447 else /* Half */
448 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
449 }
450
451 static void sh_eth_set_rate(struct net_device *ndev)
452 {
453 struct sh_eth_private *mdp = netdev_priv(ndev);
454
455 switch (mdp->speed) {
456 case 10: /* 10BASE */
457 sh_eth_write(ndev, GECMR_10, GECMR);
458 break;
459 case 100:/* 100BASE */
460 sh_eth_write(ndev, GECMR_100, GECMR);
461 break;
462 case 1000: /* 1000BASE */
463 sh_eth_write(ndev, GECMR_1000, GECMR);
464 break;
465 default:
466 break;
467 }
468 }
469
470 /* R8A7740 */
471 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
472 .chip_reset = sh_eth_chip_reset,
473 .set_duplex = sh_eth_set_duplex,
474 .set_rate = sh_eth_set_rate,
475
476 .ecsr_value = ECSR_ICD | ECSR_MPD,
477 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
478 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
479
480 .tx_check = EESR_TC1 | EESR_FTC,
481 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
482 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
483 EESR_ECI,
484 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
485 EESR_TFE,
486
487 .apr = 1,
488 .mpr = 1,
489 .tpauser = 1,
490 .bculr = 1,
491 .hw_swap = 1,
492 .no_trimd = 1,
493 .no_ade = 1,
494 .tsu = 1,
495 };
496
497 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
498 #define SH_ETH_RESET_DEFAULT 1
499 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
500 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
501
502 .apr = 1,
503 .mpr = 1,
504 .tpauser = 1,
505 .hw_swap = 1,
506 };
507 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
508 #define SH_ETH_RESET_DEFAULT 1
509 #define SH_ETH_HAS_TSU 1
510 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
511 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
512 .tsu = 1,
513 };
514 #endif
515
516 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
517 {
518 if (!cd->ecsr_value)
519 cd->ecsr_value = DEFAULT_ECSR_INIT;
520
521 if (!cd->ecsipr_value)
522 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
523
524 if (!cd->fcftr_value)
525 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
526 DEFAULT_FIFO_F_D_RFD;
527
528 if (!cd->fdr_value)
529 cd->fdr_value = DEFAULT_FDR_INIT;
530
531 if (!cd->rmcr_value)
532 cd->rmcr_value = DEFAULT_RMCR_VALUE;
533
534 if (!cd->tx_check)
535 cd->tx_check = DEFAULT_TX_CHECK;
536
537 if (!cd->eesr_err_check)
538 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
539
540 if (!cd->tx_error_check)
541 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
542 }
543
544 #if defined(SH_ETH_RESET_DEFAULT)
545 /* Chip Reset */
546 static void sh_eth_reset(struct net_device *ndev)
547 {
548 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
549 mdelay(3);
550 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
551 }
552 #endif
553
554 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
555 static void sh_eth_set_receive_align(struct sk_buff *skb)
556 {
557 int reserve;
558
559 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
560 if (reserve)
561 skb_reserve(skb, reserve);
562 }
563 #else
564 static void sh_eth_set_receive_align(struct sk_buff *skb)
565 {
566 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
567 }
568 #endif
569
570
571 /* CPU <-> EDMAC endian convert */
572 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
573 {
574 switch (mdp->edmac_endian) {
575 case EDMAC_LITTLE_ENDIAN:
576 return cpu_to_le32(x);
577 case EDMAC_BIG_ENDIAN:
578 return cpu_to_be32(x);
579 }
580 return x;
581 }
582
583 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
584 {
585 switch (mdp->edmac_endian) {
586 case EDMAC_LITTLE_ENDIAN:
587 return le32_to_cpu(x);
588 case EDMAC_BIG_ENDIAN:
589 return be32_to_cpu(x);
590 }
591 return x;
592 }
593
594 /*
595 * Program the hardware MAC address from dev->dev_addr.
596 */
597 static void update_mac_address(struct net_device *ndev)
598 {
599 sh_eth_write(ndev,
600 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
601 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
602 sh_eth_write(ndev,
603 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
604 }
605
606 /*
607 * Get MAC address from SuperH MAC address register
608 *
609 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
610 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
611 * When you want use this device, you must set MAC address in bootloader.
612 *
613 */
614 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
615 {
616 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
617 memcpy(ndev->dev_addr, mac, 6);
618 } else {
619 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
620 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
621 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
622 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
623 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
624 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
625 }
626 }
627
628 static int sh_eth_is_gether(struct sh_eth_private *mdp)
629 {
630 if (mdp->reg_offset == sh_eth_offset_gigabit)
631 return 1;
632 else
633 return 0;
634 }
635
636 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
637 {
638 if (sh_eth_is_gether(mdp))
639 return EDTRR_TRNS_GETHER;
640 else
641 return EDTRR_TRNS_ETHER;
642 }
643
644 struct bb_info {
645 void (*set_gate)(void *addr);
646 struct mdiobb_ctrl ctrl;
647 void *addr;
648 u32 mmd_msk;/* MMD */
649 u32 mdo_msk;
650 u32 mdi_msk;
651 u32 mdc_msk;
652 };
653
654 /* PHY bit set */
655 static void bb_set(void *addr, u32 msk)
656 {
657 iowrite32(ioread32(addr) | msk, addr);
658 }
659
660 /* PHY bit clear */
661 static void bb_clr(void *addr, u32 msk)
662 {
663 iowrite32((ioread32(addr) & ~msk), addr);
664 }
665
666 /* PHY bit read */
667 static int bb_read(void *addr, u32 msk)
668 {
669 return (ioread32(addr) & msk) != 0;
670 }
671
672 /* Data I/O pin control */
673 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
674 {
675 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
676
677 if (bitbang->set_gate)
678 bitbang->set_gate(bitbang->addr);
679
680 if (bit)
681 bb_set(bitbang->addr, bitbang->mmd_msk);
682 else
683 bb_clr(bitbang->addr, bitbang->mmd_msk);
684 }
685
686 /* Set bit data*/
687 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
688 {
689 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
690
691 if (bitbang->set_gate)
692 bitbang->set_gate(bitbang->addr);
693
694 if (bit)
695 bb_set(bitbang->addr, bitbang->mdo_msk);
696 else
697 bb_clr(bitbang->addr, bitbang->mdo_msk);
698 }
699
700 /* Get bit data*/
701 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
702 {
703 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
704
705 if (bitbang->set_gate)
706 bitbang->set_gate(bitbang->addr);
707
708 return bb_read(bitbang->addr, bitbang->mdi_msk);
709 }
710
711 /* MDC pin control */
712 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
713 {
714 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
715
716 if (bitbang->set_gate)
717 bitbang->set_gate(bitbang->addr);
718
719 if (bit)
720 bb_set(bitbang->addr, bitbang->mdc_msk);
721 else
722 bb_clr(bitbang->addr, bitbang->mdc_msk);
723 }
724
725 /* mdio bus control struct */
726 static struct mdiobb_ops bb_ops = {
727 .owner = THIS_MODULE,
728 .set_mdc = sh_mdc_ctrl,
729 .set_mdio_dir = sh_mmd_ctrl,
730 .set_mdio_data = sh_set_mdio,
731 .get_mdio_data = sh_get_mdio,
732 };
733
734 /* free skb and descriptor buffer */
735 static void sh_eth_ring_free(struct net_device *ndev)
736 {
737 struct sh_eth_private *mdp = netdev_priv(ndev);
738 int i;
739
740 /* Free Rx skb ringbuffer */
741 if (mdp->rx_skbuff) {
742 for (i = 0; i < RX_RING_SIZE; i++) {
743 if (mdp->rx_skbuff[i])
744 dev_kfree_skb(mdp->rx_skbuff[i]);
745 }
746 }
747 kfree(mdp->rx_skbuff);
748
749 /* Free Tx skb ringbuffer */
750 if (mdp->tx_skbuff) {
751 for (i = 0; i < TX_RING_SIZE; i++) {
752 if (mdp->tx_skbuff[i])
753 dev_kfree_skb(mdp->tx_skbuff[i]);
754 }
755 }
756 kfree(mdp->tx_skbuff);
757 }
758
759 /* format skb and descriptor buffer */
760 static void sh_eth_ring_format(struct net_device *ndev)
761 {
762 struct sh_eth_private *mdp = netdev_priv(ndev);
763 int i;
764 struct sk_buff *skb;
765 struct sh_eth_rxdesc *rxdesc = NULL;
766 struct sh_eth_txdesc *txdesc = NULL;
767 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
768 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
769
770 mdp->cur_rx = mdp->cur_tx = 0;
771 mdp->dirty_rx = mdp->dirty_tx = 0;
772
773 memset(mdp->rx_ring, 0, rx_ringsize);
774
775 /* build Rx ring buffer */
776 for (i = 0; i < RX_RING_SIZE; i++) {
777 /* skb */
778 mdp->rx_skbuff[i] = NULL;
779 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
780 mdp->rx_skbuff[i] = skb;
781 if (skb == NULL)
782 break;
783 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
784 DMA_FROM_DEVICE);
785 sh_eth_set_receive_align(skb);
786
787 /* RX descriptor */
788 rxdesc = &mdp->rx_ring[i];
789 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
790 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
791
792 /* The size of the buffer is 16 byte boundary. */
793 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
794 /* Rx descriptor address set */
795 if (i == 0) {
796 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
797 if (sh_eth_is_gether(mdp))
798 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
799 }
800 }
801
802 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
803
804 /* Mark the last entry as wrapping the ring. */
805 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
806
807 memset(mdp->tx_ring, 0, tx_ringsize);
808
809 /* build Tx ring buffer */
810 for (i = 0; i < TX_RING_SIZE; i++) {
811 mdp->tx_skbuff[i] = NULL;
812 txdesc = &mdp->tx_ring[i];
813 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
814 txdesc->buffer_length = 0;
815 if (i == 0) {
816 /* Tx descriptor address set */
817 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
818 if (sh_eth_is_gether(mdp))
819 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
820 }
821 }
822
823 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
824 }
825
826 /* Get skb and descriptor buffer */
827 static int sh_eth_ring_init(struct net_device *ndev)
828 {
829 struct sh_eth_private *mdp = netdev_priv(ndev);
830 int rx_ringsize, tx_ringsize, ret = 0;
831
832 /*
833 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
834 * card needs room to do 8 byte alignment, +2 so we can reserve
835 * the first 2 bytes, and +16 gets room for the status word from the
836 * card.
837 */
838 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
839 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
840 if (mdp->cd->rpadir)
841 mdp->rx_buf_sz += NET_IP_ALIGN;
842
843 /* Allocate RX and TX skb rings */
844 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
845 GFP_KERNEL);
846 if (!mdp->rx_skbuff) {
847 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
848 ret = -ENOMEM;
849 return ret;
850 }
851
852 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
853 GFP_KERNEL);
854 if (!mdp->tx_skbuff) {
855 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
856 ret = -ENOMEM;
857 goto skb_ring_free;
858 }
859
860 /* Allocate all Rx descriptors. */
861 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
862 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
863 GFP_KERNEL);
864
865 if (!mdp->rx_ring) {
866 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
867 rx_ringsize);
868 ret = -ENOMEM;
869 goto desc_ring_free;
870 }
871
872 mdp->dirty_rx = 0;
873
874 /* Allocate all Tx descriptors. */
875 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
876 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
877 GFP_KERNEL);
878 if (!mdp->tx_ring) {
879 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
880 tx_ringsize);
881 ret = -ENOMEM;
882 goto desc_ring_free;
883 }
884 return ret;
885
886 desc_ring_free:
887 /* free DMA buffer */
888 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
889
890 skb_ring_free:
891 /* Free Rx and Tx skb ring buffer */
892 sh_eth_ring_free(ndev);
893
894 return ret;
895 }
896
897 static int sh_eth_dev_init(struct net_device *ndev)
898 {
899 int ret = 0;
900 struct sh_eth_private *mdp = netdev_priv(ndev);
901 u_int32_t rx_int_var, tx_int_var;
902 u32 val;
903
904 /* Soft Reset */
905 sh_eth_reset(ndev);
906
907 /* Descriptor format */
908 sh_eth_ring_format(ndev);
909 if (mdp->cd->rpadir)
910 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
911
912 /* all sh_eth int mask */
913 sh_eth_write(ndev, 0, EESIPR);
914
915 #if defined(__LITTLE_ENDIAN)
916 if (mdp->cd->hw_swap)
917 sh_eth_write(ndev, EDMR_EL, EDMR);
918 else
919 #endif
920 sh_eth_write(ndev, 0, EDMR);
921
922 /* FIFO size set */
923 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
924 sh_eth_write(ndev, 0, TFTR);
925
926 /* Frame recv control */
927 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
928
929 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
930 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
931 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
932
933 if (mdp->cd->bculr)
934 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
935
936 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
937
938 if (!mdp->cd->no_trimd)
939 sh_eth_write(ndev, 0, TRIMD);
940
941 /* Recv frame limit set register */
942 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
943 RFLR);
944
945 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
946 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
947
948 /* PAUSE Prohibition */
949 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
950 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
951
952 sh_eth_write(ndev, val, ECMR);
953
954 if (mdp->cd->set_rate)
955 mdp->cd->set_rate(ndev);
956
957 /* E-MAC Status Register clear */
958 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
959
960 /* E-MAC Interrupt Enable register */
961 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
962
963 /* Set MAC address */
964 update_mac_address(ndev);
965
966 /* mask reset */
967 if (mdp->cd->apr)
968 sh_eth_write(ndev, APR_AP, APR);
969 if (mdp->cd->mpr)
970 sh_eth_write(ndev, MPR_MP, MPR);
971 if (mdp->cd->tpauser)
972 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
973
974 /* Setting the Rx mode will start the Rx process. */
975 sh_eth_write(ndev, EDRRR_R, EDRRR);
976
977 netif_start_queue(ndev);
978
979 return ret;
980 }
981
982 /* free Tx skb function */
983 static int sh_eth_txfree(struct net_device *ndev)
984 {
985 struct sh_eth_private *mdp = netdev_priv(ndev);
986 struct sh_eth_txdesc *txdesc;
987 int freeNum = 0;
988 int entry = 0;
989
990 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
991 entry = mdp->dirty_tx % TX_RING_SIZE;
992 txdesc = &mdp->tx_ring[entry];
993 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
994 break;
995 /* Free the original skb. */
996 if (mdp->tx_skbuff[entry]) {
997 dma_unmap_single(&ndev->dev, txdesc->addr,
998 txdesc->buffer_length, DMA_TO_DEVICE);
999 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1000 mdp->tx_skbuff[entry] = NULL;
1001 freeNum++;
1002 }
1003 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1004 if (entry >= TX_RING_SIZE - 1)
1005 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1006
1007 ndev->stats.tx_packets++;
1008 ndev->stats.tx_bytes += txdesc->buffer_length;
1009 }
1010 return freeNum;
1011 }
1012
1013 /* Packet receive function */
1014 static int sh_eth_rx(struct net_device *ndev)
1015 {
1016 struct sh_eth_private *mdp = netdev_priv(ndev);
1017 struct sh_eth_rxdesc *rxdesc;
1018
1019 int entry = mdp->cur_rx % RX_RING_SIZE;
1020 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
1021 struct sk_buff *skb;
1022 u16 pkt_len = 0;
1023 u32 desc_status;
1024
1025 rxdesc = &mdp->rx_ring[entry];
1026 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1027 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1028 pkt_len = rxdesc->frame_length;
1029
1030 #if defined(CONFIG_ARCH_R8A7740)
1031 desc_status >>= 16;
1032 #endif
1033
1034 if (--boguscnt < 0)
1035 break;
1036
1037 if (!(desc_status & RDFEND))
1038 ndev->stats.rx_length_errors++;
1039
1040 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1041 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1042 ndev->stats.rx_errors++;
1043 if (desc_status & RD_RFS1)
1044 ndev->stats.rx_crc_errors++;
1045 if (desc_status & RD_RFS2)
1046 ndev->stats.rx_frame_errors++;
1047 if (desc_status & RD_RFS3)
1048 ndev->stats.rx_length_errors++;
1049 if (desc_status & RD_RFS4)
1050 ndev->stats.rx_length_errors++;
1051 if (desc_status & RD_RFS6)
1052 ndev->stats.rx_missed_errors++;
1053 if (desc_status & RD_RFS10)
1054 ndev->stats.rx_over_errors++;
1055 } else {
1056 if (!mdp->cd->hw_swap)
1057 sh_eth_soft_swap(
1058 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1059 pkt_len + 2);
1060 skb = mdp->rx_skbuff[entry];
1061 mdp->rx_skbuff[entry] = NULL;
1062 if (mdp->cd->rpadir)
1063 skb_reserve(skb, NET_IP_ALIGN);
1064 skb_put(skb, pkt_len);
1065 skb->protocol = eth_type_trans(skb, ndev);
1066 netif_rx(skb);
1067 ndev->stats.rx_packets++;
1068 ndev->stats.rx_bytes += pkt_len;
1069 }
1070 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1071 entry = (++mdp->cur_rx) % RX_RING_SIZE;
1072 rxdesc = &mdp->rx_ring[entry];
1073 }
1074
1075 /* Refill the Rx ring buffers. */
1076 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1077 entry = mdp->dirty_rx % RX_RING_SIZE;
1078 rxdesc = &mdp->rx_ring[entry];
1079 /* The size of the buffer is 16 byte boundary. */
1080 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1081
1082 if (mdp->rx_skbuff[entry] == NULL) {
1083 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1084 mdp->rx_skbuff[entry] = skb;
1085 if (skb == NULL)
1086 break; /* Better luck next round. */
1087 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1088 DMA_FROM_DEVICE);
1089 sh_eth_set_receive_align(skb);
1090
1091 skb_checksum_none_assert(skb);
1092 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1093 }
1094 if (entry >= RX_RING_SIZE - 1)
1095 rxdesc->status |=
1096 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1097 else
1098 rxdesc->status |=
1099 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1100 }
1101
1102 /* Restart Rx engine if stopped. */
1103 /* If we don't need to check status, don't. -KDU */
1104 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1105 /* fix the values for the next receiving */
1106 mdp->cur_rx = mdp->dirty_rx = (sh_eth_read(ndev, RDFAR) -
1107 sh_eth_read(ndev, RDLAR)) >> 4;
1108 sh_eth_write(ndev, EDRRR_R, EDRRR);
1109 }
1110
1111 return 0;
1112 }
1113
1114 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1115 {
1116 /* disable tx and rx */
1117 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1118 ~(ECMR_RE | ECMR_TE), ECMR);
1119 }
1120
1121 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1122 {
1123 /* enable tx and rx */
1124 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1125 (ECMR_RE | ECMR_TE), ECMR);
1126 }
1127
1128 /* error control function */
1129 static void sh_eth_error(struct net_device *ndev, int intr_status)
1130 {
1131 struct sh_eth_private *mdp = netdev_priv(ndev);
1132 u32 felic_stat;
1133 u32 link_stat;
1134 u32 mask;
1135
1136 if (intr_status & EESR_ECI) {
1137 felic_stat = sh_eth_read(ndev, ECSR);
1138 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1139 if (felic_stat & ECSR_ICD)
1140 ndev->stats.tx_carrier_errors++;
1141 if (felic_stat & ECSR_LCHNG) {
1142 /* Link Changed */
1143 if (mdp->cd->no_psr || mdp->no_ether_link) {
1144 if (mdp->link == PHY_DOWN)
1145 link_stat = 0;
1146 else
1147 link_stat = PHY_ST_LINK;
1148 } else {
1149 link_stat = (sh_eth_read(ndev, PSR));
1150 if (mdp->ether_link_active_low)
1151 link_stat = ~link_stat;
1152 }
1153 if (!(link_stat & PHY_ST_LINK))
1154 sh_eth_rcv_snd_disable(ndev);
1155 else {
1156 /* Link Up */
1157 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1158 ~DMAC_M_ECI, EESIPR);
1159 /*clear int */
1160 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1161 ECSR);
1162 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1163 DMAC_M_ECI, EESIPR);
1164 /* enable tx and rx */
1165 sh_eth_rcv_snd_enable(ndev);
1166 }
1167 }
1168 }
1169
1170 if (intr_status & EESR_TWB) {
1171 /* Write buck end. unused write back interrupt */
1172 if (intr_status & EESR_TABT) /* Transmit Abort int */
1173 ndev->stats.tx_aborted_errors++;
1174 if (netif_msg_tx_err(mdp))
1175 dev_err(&ndev->dev, "Transmit Abort\n");
1176 }
1177
1178 if (intr_status & EESR_RABT) {
1179 /* Receive Abort int */
1180 if (intr_status & EESR_RFRMER) {
1181 /* Receive Frame Overflow int */
1182 ndev->stats.rx_frame_errors++;
1183 if (netif_msg_rx_err(mdp))
1184 dev_err(&ndev->dev, "Receive Abort\n");
1185 }
1186 }
1187
1188 if (intr_status & EESR_TDE) {
1189 /* Transmit Descriptor Empty int */
1190 ndev->stats.tx_fifo_errors++;
1191 if (netif_msg_tx_err(mdp))
1192 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1193 }
1194
1195 if (intr_status & EESR_TFE) {
1196 /* FIFO under flow */
1197 ndev->stats.tx_fifo_errors++;
1198 if (netif_msg_tx_err(mdp))
1199 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1200 }
1201
1202 if (intr_status & EESR_RDE) {
1203 /* Receive Descriptor Empty int */
1204 ndev->stats.rx_over_errors++;
1205
1206 if (netif_msg_rx_err(mdp))
1207 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1208 }
1209
1210 if (intr_status & EESR_RFE) {
1211 /* Receive FIFO Overflow int */
1212 ndev->stats.rx_fifo_errors++;
1213 if (netif_msg_rx_err(mdp))
1214 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1215 }
1216
1217 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1218 /* Address Error */
1219 ndev->stats.tx_fifo_errors++;
1220 if (netif_msg_tx_err(mdp))
1221 dev_err(&ndev->dev, "Address Error\n");
1222 }
1223
1224 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1225 if (mdp->cd->no_ade)
1226 mask &= ~EESR_ADE;
1227 if (intr_status & mask) {
1228 /* Tx error */
1229 u32 edtrr = sh_eth_read(ndev, EDTRR);
1230 /* dmesg */
1231 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1232 intr_status, mdp->cur_tx);
1233 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1234 mdp->dirty_tx, (u32) ndev->state, edtrr);
1235 /* dirty buffer free */
1236 sh_eth_txfree(ndev);
1237
1238 /* SH7712 BUG */
1239 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1240 /* tx dma start */
1241 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1242 }
1243 /* wakeup */
1244 netif_wake_queue(ndev);
1245 }
1246 }
1247
1248 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1249 {
1250 struct net_device *ndev = netdev;
1251 struct sh_eth_private *mdp = netdev_priv(ndev);
1252 struct sh_eth_cpu_data *cd = mdp->cd;
1253 irqreturn_t ret = IRQ_NONE;
1254 u32 intr_status = 0;
1255
1256 spin_lock(&mdp->lock);
1257
1258 /* Get interrpt stat */
1259 intr_status = sh_eth_read(ndev, EESR);
1260 /* Clear interrupt */
1261 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1262 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1263 cd->tx_check | cd->eesr_err_check)) {
1264 sh_eth_write(ndev, intr_status, EESR);
1265 ret = IRQ_HANDLED;
1266 } else
1267 goto other_irq;
1268
1269 if (intr_status & (EESR_FRC | /* Frame recv*/
1270 EESR_RMAF | /* Multi cast address recv*/
1271 EESR_RRF | /* Bit frame recv */
1272 EESR_RTLF | /* Long frame recv*/
1273 EESR_RTSF | /* short frame recv */
1274 EESR_PRE | /* PHY-LSI recv error */
1275 EESR_CERF)){ /* recv frame CRC error */
1276 sh_eth_rx(ndev);
1277 }
1278
1279 /* Tx Check */
1280 if (intr_status & cd->tx_check) {
1281 sh_eth_txfree(ndev);
1282 netif_wake_queue(ndev);
1283 }
1284
1285 if (intr_status & cd->eesr_err_check)
1286 sh_eth_error(ndev, intr_status);
1287
1288 other_irq:
1289 spin_unlock(&mdp->lock);
1290
1291 return ret;
1292 }
1293
1294 static void sh_eth_timer(unsigned long data)
1295 {
1296 struct net_device *ndev = (struct net_device *)data;
1297 struct sh_eth_private *mdp = netdev_priv(ndev);
1298
1299 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1300 }
1301
1302 /* PHY state control function */
1303 static void sh_eth_adjust_link(struct net_device *ndev)
1304 {
1305 struct sh_eth_private *mdp = netdev_priv(ndev);
1306 struct phy_device *phydev = mdp->phydev;
1307 int new_state = 0;
1308
1309 if (phydev->link != PHY_DOWN) {
1310 if (phydev->duplex != mdp->duplex) {
1311 new_state = 1;
1312 mdp->duplex = phydev->duplex;
1313 if (mdp->cd->set_duplex)
1314 mdp->cd->set_duplex(ndev);
1315 }
1316
1317 if (phydev->speed != mdp->speed) {
1318 new_state = 1;
1319 mdp->speed = phydev->speed;
1320 if (mdp->cd->set_rate)
1321 mdp->cd->set_rate(ndev);
1322 }
1323 if (mdp->link == PHY_DOWN) {
1324 sh_eth_write(ndev,
1325 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1326 new_state = 1;
1327 mdp->link = phydev->link;
1328 }
1329 } else if (mdp->link) {
1330 new_state = 1;
1331 mdp->link = PHY_DOWN;
1332 mdp->speed = 0;
1333 mdp->duplex = -1;
1334 }
1335
1336 if (new_state && netif_msg_link(mdp))
1337 phy_print_status(phydev);
1338 }
1339
1340 /* PHY init function */
1341 static int sh_eth_phy_init(struct net_device *ndev)
1342 {
1343 struct sh_eth_private *mdp = netdev_priv(ndev);
1344 char phy_id[MII_BUS_ID_SIZE + 3];
1345 struct phy_device *phydev = NULL;
1346
1347 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1348 mdp->mii_bus->id , mdp->phy_id);
1349
1350 mdp->link = PHY_DOWN;
1351 mdp->speed = 0;
1352 mdp->duplex = -1;
1353
1354 /* Try connect to PHY */
1355 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1356 0, mdp->phy_interface);
1357 if (IS_ERR(phydev)) {
1358 dev_err(&ndev->dev, "phy_connect failed\n");
1359 return PTR_ERR(phydev);
1360 }
1361
1362 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1363 phydev->addr, phydev->drv->name);
1364
1365 mdp->phydev = phydev;
1366
1367 return 0;
1368 }
1369
1370 /* PHY control start function */
1371 static int sh_eth_phy_start(struct net_device *ndev)
1372 {
1373 struct sh_eth_private *mdp = netdev_priv(ndev);
1374 int ret;
1375
1376 ret = sh_eth_phy_init(ndev);
1377 if (ret)
1378 return ret;
1379
1380 /* reset phy - this also wakes it from PDOWN */
1381 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1382 phy_start(mdp->phydev);
1383
1384 return 0;
1385 }
1386
1387 static int sh_eth_get_settings(struct net_device *ndev,
1388 struct ethtool_cmd *ecmd)
1389 {
1390 struct sh_eth_private *mdp = netdev_priv(ndev);
1391 unsigned long flags;
1392 int ret;
1393
1394 spin_lock_irqsave(&mdp->lock, flags);
1395 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1396 spin_unlock_irqrestore(&mdp->lock, flags);
1397
1398 return ret;
1399 }
1400
1401 static int sh_eth_set_settings(struct net_device *ndev,
1402 struct ethtool_cmd *ecmd)
1403 {
1404 struct sh_eth_private *mdp = netdev_priv(ndev);
1405 unsigned long flags;
1406 int ret;
1407
1408 spin_lock_irqsave(&mdp->lock, flags);
1409
1410 /* disable tx and rx */
1411 sh_eth_rcv_snd_disable(ndev);
1412
1413 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1414 if (ret)
1415 goto error_exit;
1416
1417 if (ecmd->duplex == DUPLEX_FULL)
1418 mdp->duplex = 1;
1419 else
1420 mdp->duplex = 0;
1421
1422 if (mdp->cd->set_duplex)
1423 mdp->cd->set_duplex(ndev);
1424
1425 error_exit:
1426 mdelay(1);
1427
1428 /* enable tx and rx */
1429 sh_eth_rcv_snd_enable(ndev);
1430
1431 spin_unlock_irqrestore(&mdp->lock, flags);
1432
1433 return ret;
1434 }
1435
1436 static int sh_eth_nway_reset(struct net_device *ndev)
1437 {
1438 struct sh_eth_private *mdp = netdev_priv(ndev);
1439 unsigned long flags;
1440 int ret;
1441
1442 spin_lock_irqsave(&mdp->lock, flags);
1443 ret = phy_start_aneg(mdp->phydev);
1444 spin_unlock_irqrestore(&mdp->lock, flags);
1445
1446 return ret;
1447 }
1448
1449 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1450 {
1451 struct sh_eth_private *mdp = netdev_priv(ndev);
1452 return mdp->msg_enable;
1453 }
1454
1455 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1456 {
1457 struct sh_eth_private *mdp = netdev_priv(ndev);
1458 mdp->msg_enable = value;
1459 }
1460
1461 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1462 "rx_current", "tx_current",
1463 "rx_dirty", "tx_dirty",
1464 };
1465 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1466
1467 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1468 {
1469 switch (sset) {
1470 case ETH_SS_STATS:
1471 return SH_ETH_STATS_LEN;
1472 default:
1473 return -EOPNOTSUPP;
1474 }
1475 }
1476
1477 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1478 struct ethtool_stats *stats, u64 *data)
1479 {
1480 struct sh_eth_private *mdp = netdev_priv(ndev);
1481 int i = 0;
1482
1483 /* device-specific stats */
1484 data[i++] = mdp->cur_rx;
1485 data[i++] = mdp->cur_tx;
1486 data[i++] = mdp->dirty_rx;
1487 data[i++] = mdp->dirty_tx;
1488 }
1489
1490 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1491 {
1492 switch (stringset) {
1493 case ETH_SS_STATS:
1494 memcpy(data, *sh_eth_gstrings_stats,
1495 sizeof(sh_eth_gstrings_stats));
1496 break;
1497 }
1498 }
1499
1500 static const struct ethtool_ops sh_eth_ethtool_ops = {
1501 .get_settings = sh_eth_get_settings,
1502 .set_settings = sh_eth_set_settings,
1503 .nway_reset = sh_eth_nway_reset,
1504 .get_msglevel = sh_eth_get_msglevel,
1505 .set_msglevel = sh_eth_set_msglevel,
1506 .get_link = ethtool_op_get_link,
1507 .get_strings = sh_eth_get_strings,
1508 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1509 .get_sset_count = sh_eth_get_sset_count,
1510 };
1511
1512 /* network device open function */
1513 static int sh_eth_open(struct net_device *ndev)
1514 {
1515 int ret = 0;
1516 struct sh_eth_private *mdp = netdev_priv(ndev);
1517
1518 pm_runtime_get_sync(&mdp->pdev->dev);
1519
1520 ret = request_irq(ndev->irq, sh_eth_interrupt,
1521 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1522 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1523 defined(CONFIG_CPU_SUBTYPE_SH7757)
1524 IRQF_SHARED,
1525 #else
1526 0,
1527 #endif
1528 ndev->name, ndev);
1529 if (ret) {
1530 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1531 return ret;
1532 }
1533
1534 /* Descriptor set */
1535 ret = sh_eth_ring_init(ndev);
1536 if (ret)
1537 goto out_free_irq;
1538
1539 /* device init */
1540 ret = sh_eth_dev_init(ndev);
1541 if (ret)
1542 goto out_free_irq;
1543
1544 /* PHY control start*/
1545 ret = sh_eth_phy_start(ndev);
1546 if (ret)
1547 goto out_free_irq;
1548
1549 /* Set the timer to check for link beat. */
1550 init_timer(&mdp->timer);
1551 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1552 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1553
1554 return ret;
1555
1556 out_free_irq:
1557 free_irq(ndev->irq, ndev);
1558 pm_runtime_put_sync(&mdp->pdev->dev);
1559 return ret;
1560 }
1561
1562 /* Timeout function */
1563 static void sh_eth_tx_timeout(struct net_device *ndev)
1564 {
1565 struct sh_eth_private *mdp = netdev_priv(ndev);
1566 struct sh_eth_rxdesc *rxdesc;
1567 int i;
1568
1569 netif_stop_queue(ndev);
1570
1571 if (netif_msg_timer(mdp))
1572 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1573 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1574
1575 /* tx_errors count up */
1576 ndev->stats.tx_errors++;
1577
1578 /* timer off */
1579 del_timer_sync(&mdp->timer);
1580
1581 /* Free all the skbuffs in the Rx queue. */
1582 for (i = 0; i < RX_RING_SIZE; i++) {
1583 rxdesc = &mdp->rx_ring[i];
1584 rxdesc->status = 0;
1585 rxdesc->addr = 0xBADF00D0;
1586 if (mdp->rx_skbuff[i])
1587 dev_kfree_skb(mdp->rx_skbuff[i]);
1588 mdp->rx_skbuff[i] = NULL;
1589 }
1590 for (i = 0; i < TX_RING_SIZE; i++) {
1591 if (mdp->tx_skbuff[i])
1592 dev_kfree_skb(mdp->tx_skbuff[i]);
1593 mdp->tx_skbuff[i] = NULL;
1594 }
1595
1596 /* device init */
1597 sh_eth_dev_init(ndev);
1598
1599 /* timer on */
1600 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1601 add_timer(&mdp->timer);
1602 }
1603
1604 /* Packet transmit function */
1605 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1606 {
1607 struct sh_eth_private *mdp = netdev_priv(ndev);
1608 struct sh_eth_txdesc *txdesc;
1609 u32 entry;
1610 unsigned long flags;
1611
1612 spin_lock_irqsave(&mdp->lock, flags);
1613 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1614 if (!sh_eth_txfree(ndev)) {
1615 if (netif_msg_tx_queued(mdp))
1616 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1617 netif_stop_queue(ndev);
1618 spin_unlock_irqrestore(&mdp->lock, flags);
1619 return NETDEV_TX_BUSY;
1620 }
1621 }
1622 spin_unlock_irqrestore(&mdp->lock, flags);
1623
1624 entry = mdp->cur_tx % TX_RING_SIZE;
1625 mdp->tx_skbuff[entry] = skb;
1626 txdesc = &mdp->tx_ring[entry];
1627 /* soft swap. */
1628 if (!mdp->cd->hw_swap)
1629 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1630 skb->len + 2);
1631 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1632 DMA_TO_DEVICE);
1633 if (skb->len < ETHERSMALL)
1634 txdesc->buffer_length = ETHERSMALL;
1635 else
1636 txdesc->buffer_length = skb->len;
1637
1638 if (entry >= TX_RING_SIZE - 1)
1639 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1640 else
1641 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1642
1643 mdp->cur_tx++;
1644
1645 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1646 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1647
1648 return NETDEV_TX_OK;
1649 }
1650
1651 /* device close function */
1652 static int sh_eth_close(struct net_device *ndev)
1653 {
1654 struct sh_eth_private *mdp = netdev_priv(ndev);
1655 int ringsize;
1656
1657 netif_stop_queue(ndev);
1658
1659 /* Disable interrupts by clearing the interrupt mask. */
1660 sh_eth_write(ndev, 0x0000, EESIPR);
1661
1662 /* Stop the chip's Tx and Rx processes. */
1663 sh_eth_write(ndev, 0, EDTRR);
1664 sh_eth_write(ndev, 0, EDRRR);
1665
1666 /* PHY Disconnect */
1667 if (mdp->phydev) {
1668 phy_stop(mdp->phydev);
1669 phy_disconnect(mdp->phydev);
1670 }
1671
1672 free_irq(ndev->irq, ndev);
1673
1674 del_timer_sync(&mdp->timer);
1675
1676 /* Free all the skbuffs in the Rx queue. */
1677 sh_eth_ring_free(ndev);
1678
1679 /* free DMA buffer */
1680 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1681 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1682
1683 /* free DMA buffer */
1684 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1685 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1686
1687 pm_runtime_put_sync(&mdp->pdev->dev);
1688
1689 return 0;
1690 }
1691
1692 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1693 {
1694 struct sh_eth_private *mdp = netdev_priv(ndev);
1695
1696 pm_runtime_get_sync(&mdp->pdev->dev);
1697
1698 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1699 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1700 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
1701 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1702 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1703 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
1704 if (sh_eth_is_gether(mdp)) {
1705 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1706 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1707 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1708 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1709 } else {
1710 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1711 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1712 }
1713 pm_runtime_put_sync(&mdp->pdev->dev);
1714
1715 return &ndev->stats;
1716 }
1717
1718 /* ioctl to device function */
1719 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1720 int cmd)
1721 {
1722 struct sh_eth_private *mdp = netdev_priv(ndev);
1723 struct phy_device *phydev = mdp->phydev;
1724
1725 if (!netif_running(ndev))
1726 return -EINVAL;
1727
1728 if (!phydev)
1729 return -ENODEV;
1730
1731 return phy_mii_ioctl(phydev, rq, cmd);
1732 }
1733
1734 #if defined(SH_ETH_HAS_TSU)
1735 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
1736 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
1737 int entry)
1738 {
1739 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
1740 }
1741
1742 static u32 sh_eth_tsu_get_post_mask(int entry)
1743 {
1744 return 0x0f << (28 - ((entry % 8) * 4));
1745 }
1746
1747 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
1748 {
1749 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
1750 }
1751
1752 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
1753 int entry)
1754 {
1755 struct sh_eth_private *mdp = netdev_priv(ndev);
1756 u32 tmp;
1757 void *reg_offset;
1758
1759 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
1760 tmp = ioread32(reg_offset);
1761 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
1762 }
1763
1764 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
1765 int entry)
1766 {
1767 struct sh_eth_private *mdp = netdev_priv(ndev);
1768 u32 post_mask, ref_mask, tmp;
1769 void *reg_offset;
1770
1771 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
1772 post_mask = sh_eth_tsu_get_post_mask(entry);
1773 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
1774
1775 tmp = ioread32(reg_offset);
1776 iowrite32(tmp & ~post_mask, reg_offset);
1777
1778 /* If other port enables, the function returns "true" */
1779 return tmp & ref_mask;
1780 }
1781
1782 static int sh_eth_tsu_busy(struct net_device *ndev)
1783 {
1784 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
1785 struct sh_eth_private *mdp = netdev_priv(ndev);
1786
1787 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
1788 udelay(10);
1789 timeout--;
1790 if (timeout <= 0) {
1791 dev_err(&ndev->dev, "%s: timeout\n", __func__);
1792 return -ETIMEDOUT;
1793 }
1794 }
1795
1796 return 0;
1797 }
1798
1799 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
1800 const u8 *addr)
1801 {
1802 u32 val;
1803
1804 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
1805 iowrite32(val, reg);
1806 if (sh_eth_tsu_busy(ndev) < 0)
1807 return -EBUSY;
1808
1809 val = addr[4] << 8 | addr[5];
1810 iowrite32(val, reg + 4);
1811 if (sh_eth_tsu_busy(ndev) < 0)
1812 return -EBUSY;
1813
1814 return 0;
1815 }
1816
1817 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
1818 {
1819 u32 val;
1820
1821 val = ioread32(reg);
1822 addr[0] = (val >> 24) & 0xff;
1823 addr[1] = (val >> 16) & 0xff;
1824 addr[2] = (val >> 8) & 0xff;
1825 addr[3] = val & 0xff;
1826 val = ioread32(reg + 4);
1827 addr[4] = (val >> 8) & 0xff;
1828 addr[5] = val & 0xff;
1829 }
1830
1831
1832 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
1833 {
1834 struct sh_eth_private *mdp = netdev_priv(ndev);
1835 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1836 int i;
1837 u8 c_addr[ETH_ALEN];
1838
1839 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
1840 sh_eth_tsu_read_entry(reg_offset, c_addr);
1841 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
1842 return i;
1843 }
1844
1845 return -ENOENT;
1846 }
1847
1848 static int sh_eth_tsu_find_empty(struct net_device *ndev)
1849 {
1850 u8 blank[ETH_ALEN];
1851 int entry;
1852
1853 memset(blank, 0, sizeof(blank));
1854 entry = sh_eth_tsu_find_entry(ndev, blank);
1855 return (entry < 0) ? -ENOMEM : entry;
1856 }
1857
1858 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
1859 int entry)
1860 {
1861 struct sh_eth_private *mdp = netdev_priv(ndev);
1862 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1863 int ret;
1864 u8 blank[ETH_ALEN];
1865
1866 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
1867 ~(1 << (31 - entry)), TSU_TEN);
1868
1869 memset(blank, 0, sizeof(blank));
1870 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
1871 if (ret < 0)
1872 return ret;
1873 return 0;
1874 }
1875
1876 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
1877 {
1878 struct sh_eth_private *mdp = netdev_priv(ndev);
1879 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1880 int i, ret;
1881
1882 if (!mdp->cd->tsu)
1883 return 0;
1884
1885 i = sh_eth_tsu_find_entry(ndev, addr);
1886 if (i < 0) {
1887 /* No entry found, create one */
1888 i = sh_eth_tsu_find_empty(ndev);
1889 if (i < 0)
1890 return -ENOMEM;
1891 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
1892 if (ret < 0)
1893 return ret;
1894
1895 /* Enable the entry */
1896 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
1897 (1 << (31 - i)), TSU_TEN);
1898 }
1899
1900 /* Entry found or created, enable POST */
1901 sh_eth_tsu_enable_cam_entry_post(ndev, i);
1902
1903 return 0;
1904 }
1905
1906 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
1907 {
1908 struct sh_eth_private *mdp = netdev_priv(ndev);
1909 int i, ret;
1910
1911 if (!mdp->cd->tsu)
1912 return 0;
1913
1914 i = sh_eth_tsu_find_entry(ndev, addr);
1915 if (i) {
1916 /* Entry found */
1917 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
1918 goto done;
1919
1920 /* Disable the entry if both ports was disabled */
1921 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
1922 if (ret < 0)
1923 return ret;
1924 }
1925 done:
1926 return 0;
1927 }
1928
1929 static int sh_eth_tsu_purge_all(struct net_device *ndev)
1930 {
1931 struct sh_eth_private *mdp = netdev_priv(ndev);
1932 int i, ret;
1933
1934 if (unlikely(!mdp->cd->tsu))
1935 return 0;
1936
1937 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
1938 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
1939 continue;
1940
1941 /* Disable the entry if both ports was disabled */
1942 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
1943 if (ret < 0)
1944 return ret;
1945 }
1946
1947 return 0;
1948 }
1949
1950 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
1951 {
1952 struct sh_eth_private *mdp = netdev_priv(ndev);
1953 u8 addr[ETH_ALEN];
1954 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1955 int i;
1956
1957 if (unlikely(!mdp->cd->tsu))
1958 return;
1959
1960 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
1961 sh_eth_tsu_read_entry(reg_offset, addr);
1962 if (is_multicast_ether_addr(addr))
1963 sh_eth_tsu_del_entry(ndev, addr);
1964 }
1965 }
1966
1967 /* Multicast reception directions set */
1968 static void sh_eth_set_multicast_list(struct net_device *ndev)
1969 {
1970 struct sh_eth_private *mdp = netdev_priv(ndev);
1971 u32 ecmr_bits;
1972 int mcast_all = 0;
1973 unsigned long flags;
1974
1975 spin_lock_irqsave(&mdp->lock, flags);
1976 /*
1977 * Initial condition is MCT = 1, PRM = 0.
1978 * Depending on ndev->flags, set PRM or clear MCT
1979 */
1980 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
1981
1982 if (!(ndev->flags & IFF_MULTICAST)) {
1983 sh_eth_tsu_purge_mcast(ndev);
1984 mcast_all = 1;
1985 }
1986 if (ndev->flags & IFF_ALLMULTI) {
1987 sh_eth_tsu_purge_mcast(ndev);
1988 ecmr_bits &= ~ECMR_MCT;
1989 mcast_all = 1;
1990 }
1991
1992 if (ndev->flags & IFF_PROMISC) {
1993 sh_eth_tsu_purge_all(ndev);
1994 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
1995 } else if (mdp->cd->tsu) {
1996 struct netdev_hw_addr *ha;
1997 netdev_for_each_mc_addr(ha, ndev) {
1998 if (mcast_all && is_multicast_ether_addr(ha->addr))
1999 continue;
2000
2001 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2002 if (!mcast_all) {
2003 sh_eth_tsu_purge_mcast(ndev);
2004 ecmr_bits &= ~ECMR_MCT;
2005 mcast_all = 1;
2006 }
2007 }
2008 }
2009 } else {
2010 /* Normal, unicast/broadcast-only mode. */
2011 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2012 }
2013
2014 /* update the ethernet mode */
2015 sh_eth_write(ndev, ecmr_bits, ECMR);
2016
2017 spin_unlock_irqrestore(&mdp->lock, flags);
2018 }
2019
2020 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2021 {
2022 if (!mdp->port)
2023 return TSU_VTAG0;
2024 else
2025 return TSU_VTAG1;
2026 }
2027
2028 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
2029 {
2030 struct sh_eth_private *mdp = netdev_priv(ndev);
2031 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2032
2033 if (unlikely(!mdp->cd->tsu))
2034 return -EPERM;
2035
2036 /* No filtering if vid = 0 */
2037 if (!vid)
2038 return 0;
2039
2040 mdp->vlan_num_ids++;
2041
2042 /*
2043 * The controller has one VLAN tag HW filter. So, if the filter is
2044 * already enabled, the driver disables it and the filte
2045 */
2046 if (mdp->vlan_num_ids > 1) {
2047 /* disable VLAN filter */
2048 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2049 return 0;
2050 }
2051
2052 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2053 vtag_reg_index);
2054
2055 return 0;
2056 }
2057
2058 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
2059 {
2060 struct sh_eth_private *mdp = netdev_priv(ndev);
2061 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2062
2063 if (unlikely(!mdp->cd->tsu))
2064 return -EPERM;
2065
2066 /* No filtering if vid = 0 */
2067 if (!vid)
2068 return 0;
2069
2070 mdp->vlan_num_ids--;
2071 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2072
2073 return 0;
2074 }
2075 #endif /* SH_ETH_HAS_TSU */
2076
2077 /* SuperH's TSU register init function */
2078 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2079 {
2080 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2081 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2082 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2083 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2084 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2085 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2086 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2087 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2088 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2089 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2090 if (sh_eth_is_gether(mdp)) {
2091 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2092 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2093 } else {
2094 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2095 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2096 }
2097 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2098 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2099 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2100 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2101 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2102 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2103 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2104 }
2105
2106 /* MDIO bus release function */
2107 static int sh_mdio_release(struct net_device *ndev)
2108 {
2109 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2110
2111 /* unregister mdio bus */
2112 mdiobus_unregister(bus);
2113
2114 /* remove mdio bus info from net_device */
2115 dev_set_drvdata(&ndev->dev, NULL);
2116
2117 /* free interrupts memory */
2118 kfree(bus->irq);
2119
2120 /* free bitbang info */
2121 free_mdio_bitbang(bus);
2122
2123 return 0;
2124 }
2125
2126 /* MDIO bus init function */
2127 static int sh_mdio_init(struct net_device *ndev, int id,
2128 struct sh_eth_plat_data *pd)
2129 {
2130 int ret, i;
2131 struct bb_info *bitbang;
2132 struct sh_eth_private *mdp = netdev_priv(ndev);
2133
2134 /* create bit control struct for PHY */
2135 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
2136 if (!bitbang) {
2137 ret = -ENOMEM;
2138 goto out;
2139 }
2140
2141 /* bitbang init */
2142 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2143 bitbang->set_gate = pd->set_mdio_gate;
2144 bitbang->mdi_msk = 0x08;
2145 bitbang->mdo_msk = 0x04;
2146 bitbang->mmd_msk = 0x02;/* MMD */
2147 bitbang->mdc_msk = 0x01;
2148 bitbang->ctrl.ops = &bb_ops;
2149
2150 /* MII controller setting */
2151 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2152 if (!mdp->mii_bus) {
2153 ret = -ENOMEM;
2154 goto out_free_bitbang;
2155 }
2156
2157 /* Hook up MII support for ethtool */
2158 mdp->mii_bus->name = "sh_mii";
2159 mdp->mii_bus->parent = &ndev->dev;
2160 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2161 mdp->pdev->name, id);
2162
2163 /* PHY IRQ */
2164 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
2165 if (!mdp->mii_bus->irq) {
2166 ret = -ENOMEM;
2167 goto out_free_bus;
2168 }
2169
2170 for (i = 0; i < PHY_MAX_ADDR; i++)
2171 mdp->mii_bus->irq[i] = PHY_POLL;
2172
2173 /* regist mdio bus */
2174 ret = mdiobus_register(mdp->mii_bus);
2175 if (ret)
2176 goto out_free_irq;
2177
2178 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2179
2180 return 0;
2181
2182 out_free_irq:
2183 kfree(mdp->mii_bus->irq);
2184
2185 out_free_bus:
2186 free_mdio_bitbang(mdp->mii_bus);
2187
2188 out_free_bitbang:
2189 kfree(bitbang);
2190
2191 out:
2192 return ret;
2193 }
2194
2195 static const u16 *sh_eth_get_register_offset(int register_type)
2196 {
2197 const u16 *reg_offset = NULL;
2198
2199 switch (register_type) {
2200 case SH_ETH_REG_GIGABIT:
2201 reg_offset = sh_eth_offset_gigabit;
2202 break;
2203 case SH_ETH_REG_FAST_SH4:
2204 reg_offset = sh_eth_offset_fast_sh4;
2205 break;
2206 case SH_ETH_REG_FAST_SH3_SH2:
2207 reg_offset = sh_eth_offset_fast_sh3_sh2;
2208 break;
2209 default:
2210 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
2211 break;
2212 }
2213
2214 return reg_offset;
2215 }
2216
2217 static const struct net_device_ops sh_eth_netdev_ops = {
2218 .ndo_open = sh_eth_open,
2219 .ndo_stop = sh_eth_close,
2220 .ndo_start_xmit = sh_eth_start_xmit,
2221 .ndo_get_stats = sh_eth_get_stats,
2222 #if defined(SH_ETH_HAS_TSU)
2223 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2224 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2225 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2226 #endif
2227 .ndo_tx_timeout = sh_eth_tx_timeout,
2228 .ndo_do_ioctl = sh_eth_do_ioctl,
2229 .ndo_validate_addr = eth_validate_addr,
2230 .ndo_set_mac_address = eth_mac_addr,
2231 .ndo_change_mtu = eth_change_mtu,
2232 };
2233
2234 static int sh_eth_drv_probe(struct platform_device *pdev)
2235 {
2236 int ret, devno = 0;
2237 struct resource *res;
2238 struct net_device *ndev = NULL;
2239 struct sh_eth_private *mdp = NULL;
2240 struct sh_eth_plat_data *pd;
2241
2242 /* get base addr */
2243 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2244 if (unlikely(res == NULL)) {
2245 dev_err(&pdev->dev, "invalid resource\n");
2246 ret = -EINVAL;
2247 goto out;
2248 }
2249
2250 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2251 if (!ndev) {
2252 ret = -ENOMEM;
2253 goto out;
2254 }
2255
2256 /* The sh Ether-specific entries in the device structure. */
2257 ndev->base_addr = res->start;
2258 devno = pdev->id;
2259 if (devno < 0)
2260 devno = 0;
2261
2262 ndev->dma = -1;
2263 ret = platform_get_irq(pdev, 0);
2264 if (ret < 0) {
2265 ret = -ENODEV;
2266 goto out_release;
2267 }
2268 ndev->irq = ret;
2269
2270 SET_NETDEV_DEV(ndev, &pdev->dev);
2271
2272 /* Fill in the fields of the device structure with ethernet values. */
2273 ether_setup(ndev);
2274
2275 mdp = netdev_priv(ndev);
2276 mdp->addr = ioremap(res->start, resource_size(res));
2277 if (mdp->addr == NULL) {
2278 ret = -ENOMEM;
2279 dev_err(&pdev->dev, "ioremap failed.\n");
2280 goto out_release;
2281 }
2282
2283 spin_lock_init(&mdp->lock);
2284 mdp->pdev = pdev;
2285 pm_runtime_enable(&pdev->dev);
2286 pm_runtime_resume(&pdev->dev);
2287
2288 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
2289 /* get PHY ID */
2290 mdp->phy_id = pd->phy;
2291 mdp->phy_interface = pd->phy_interface;
2292 /* EDMAC endian */
2293 mdp->edmac_endian = pd->edmac_endian;
2294 mdp->no_ether_link = pd->no_ether_link;
2295 mdp->ether_link_active_low = pd->ether_link_active_low;
2296 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2297
2298 /* set cpu data */
2299 #if defined(SH_ETH_HAS_BOTH_MODULES)
2300 mdp->cd = sh_eth_get_cpu_data(mdp);
2301 #else
2302 mdp->cd = &sh_eth_my_cpu_data;
2303 #endif
2304 sh_eth_set_default_cpu_data(mdp->cd);
2305
2306 /* set function */
2307 ndev->netdev_ops = &sh_eth_netdev_ops;
2308 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2309 ndev->watchdog_timeo = TX_TIMEOUT;
2310
2311 /* debug message level */
2312 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2313 mdp->post_rx = POST_RX >> (devno << 1);
2314 mdp->post_fw = POST_FW >> (devno << 1);
2315
2316 /* read and set MAC address */
2317 read_mac_address(ndev, pd->mac_addr);
2318
2319 /* ioremap the TSU registers */
2320 if (mdp->cd->tsu) {
2321 struct resource *rtsu;
2322 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2323 if (!rtsu) {
2324 dev_err(&pdev->dev, "Not found TSU resource\n");
2325 goto out_release;
2326 }
2327 mdp->tsu_addr = ioremap(rtsu->start,
2328 resource_size(rtsu));
2329 mdp->port = devno % 2;
2330 ndev->features = NETIF_F_HW_VLAN_FILTER;
2331 }
2332
2333 /* initialize first or needed device */
2334 if (!devno || pd->needs_init) {
2335 if (mdp->cd->chip_reset)
2336 mdp->cd->chip_reset(ndev);
2337
2338 if (mdp->cd->tsu) {
2339 /* TSU init (Init only)*/
2340 sh_eth_tsu_init(mdp);
2341 }
2342 }
2343
2344 /* network device register */
2345 ret = register_netdev(ndev);
2346 if (ret)
2347 goto out_release;
2348
2349 /* mdio bus init */
2350 ret = sh_mdio_init(ndev, pdev->id, pd);
2351 if (ret)
2352 goto out_unregister;
2353
2354 /* print device information */
2355 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2356 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2357
2358 platform_set_drvdata(pdev, ndev);
2359
2360 return ret;
2361
2362 out_unregister:
2363 unregister_netdev(ndev);
2364
2365 out_release:
2366 /* net_dev free */
2367 if (mdp && mdp->addr)
2368 iounmap(mdp->addr);
2369 if (mdp && mdp->tsu_addr)
2370 iounmap(mdp->tsu_addr);
2371 if (ndev)
2372 free_netdev(ndev);
2373
2374 out:
2375 return ret;
2376 }
2377
2378 static int sh_eth_drv_remove(struct platform_device *pdev)
2379 {
2380 struct net_device *ndev = platform_get_drvdata(pdev);
2381 struct sh_eth_private *mdp = netdev_priv(ndev);
2382
2383 if (mdp->cd->tsu)
2384 iounmap(mdp->tsu_addr);
2385 sh_mdio_release(ndev);
2386 unregister_netdev(ndev);
2387 pm_runtime_disable(&pdev->dev);
2388 iounmap(mdp->addr);
2389 free_netdev(ndev);
2390 platform_set_drvdata(pdev, NULL);
2391
2392 return 0;
2393 }
2394
2395 static int sh_eth_runtime_nop(struct device *dev)
2396 {
2397 /*
2398 * Runtime PM callback shared between ->runtime_suspend()
2399 * and ->runtime_resume(). Simply returns success.
2400 *
2401 * This driver re-initializes all registers after
2402 * pm_runtime_get_sync() anyway so there is no need
2403 * to save and restore registers here.
2404 */
2405 return 0;
2406 }
2407
2408 static struct dev_pm_ops sh_eth_dev_pm_ops = {
2409 .runtime_suspend = sh_eth_runtime_nop,
2410 .runtime_resume = sh_eth_runtime_nop,
2411 };
2412
2413 static struct platform_driver sh_eth_driver = {
2414 .probe = sh_eth_drv_probe,
2415 .remove = sh_eth_drv_remove,
2416 .driver = {
2417 .name = CARDNAME,
2418 .pm = &sh_eth_dev_pm_ops,
2419 },
2420 };
2421
2422 module_platform_driver(sh_eth_driver);
2423
2424 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2425 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2426 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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