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Merge branch 'acpi-lpss'
[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.c
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2012 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/spinlock.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/etherdevice.h>
30 #include <linux/delay.h>
31 #include <linux/platform_device.h>
32 #include <linux/mdio-bitbang.h>
33 #include <linux/netdevice.h>
34 #include <linux/phy.h>
35 #include <linux/cache.h>
36 #include <linux/io.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/slab.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/clk.h>
42 #include <linux/sh_eth.h>
43
44 #include "sh_eth.h"
45
46 #define SH_ETH_DEF_MSG_ENABLE \
47 (NETIF_MSG_LINK | \
48 NETIF_MSG_TIMER | \
49 NETIF_MSG_RX_ERR| \
50 NETIF_MSG_TX_ERR)
51
52 #if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
53 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
54 defined(CONFIG_ARCH_R8A7740)
55 static void sh_eth_select_mii(struct net_device *ndev)
56 {
57 u32 value = 0x0;
58 struct sh_eth_private *mdp = netdev_priv(ndev);
59
60 switch (mdp->phy_interface) {
61 case PHY_INTERFACE_MODE_GMII:
62 value = 0x2;
63 break;
64 case PHY_INTERFACE_MODE_MII:
65 value = 0x1;
66 break;
67 case PHY_INTERFACE_MODE_RMII:
68 value = 0x0;
69 break;
70 default:
71 pr_warn("PHY interface mode was not setup. Set to MII.\n");
72 value = 0x1;
73 break;
74 }
75
76 sh_eth_write(ndev, value, RMII_MII);
77 }
78 #endif
79
80 /* There is CPU dependent code */
81 #if defined(CONFIG_CPU_SUBTYPE_SH7724) || defined(CONFIG_ARCH_R8A7779)
82 #define SH_ETH_RESET_DEFAULT 1
83 static void sh_eth_set_duplex(struct net_device *ndev)
84 {
85 struct sh_eth_private *mdp = netdev_priv(ndev);
86
87 if (mdp->duplex) /* Full */
88 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
89 else /* Half */
90 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
91 }
92
93 static void sh_eth_set_rate(struct net_device *ndev)
94 {
95 struct sh_eth_private *mdp = netdev_priv(ndev);
96 unsigned int bits = ECMR_RTM;
97
98 #if defined(CONFIG_ARCH_R8A7779)
99 bits |= ECMR_ELB;
100 #endif
101
102 switch (mdp->speed) {
103 case 10: /* 10BASE */
104 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~bits, ECMR);
105 break;
106 case 100:/* 100BASE */
107 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | bits, ECMR);
108 break;
109 default:
110 break;
111 }
112 }
113
114 /* SH7724 */
115 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
116 .set_duplex = sh_eth_set_duplex,
117 .set_rate = sh_eth_set_rate,
118
119 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
120 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
121 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
122
123 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
124 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
125 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
126 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
127
128 .apr = 1,
129 .mpr = 1,
130 .tpauser = 1,
131 .hw_swap = 1,
132 .rpadir = 1,
133 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
134 };
135 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
136 #define SH_ETH_HAS_BOTH_MODULES 1
137 #define SH_ETH_HAS_TSU 1
138 static int sh_eth_check_reset(struct net_device *ndev);
139
140 static void sh_eth_set_duplex(struct net_device *ndev)
141 {
142 struct sh_eth_private *mdp = netdev_priv(ndev);
143
144 if (mdp->duplex) /* Full */
145 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
146 else /* Half */
147 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
148 }
149
150 static void sh_eth_set_rate(struct net_device *ndev)
151 {
152 struct sh_eth_private *mdp = netdev_priv(ndev);
153
154 switch (mdp->speed) {
155 case 10: /* 10BASE */
156 sh_eth_write(ndev, 0, RTRATE);
157 break;
158 case 100:/* 100BASE */
159 sh_eth_write(ndev, 1, RTRATE);
160 break;
161 default:
162 break;
163 }
164 }
165
166 /* SH7757 */
167 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
168 .set_duplex = sh_eth_set_duplex,
169 .set_rate = sh_eth_set_rate,
170
171 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
172 .rmcr_value = 0x00000001,
173
174 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
175 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
176 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
177 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
178
179 .apr = 1,
180 .mpr = 1,
181 .tpauser = 1,
182 .hw_swap = 1,
183 .no_ade = 1,
184 .rpadir = 1,
185 .rpadir_value = 2 << 16,
186 };
187
188 #define SH_GIGA_ETH_BASE 0xfee00000
189 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
190 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
191 static void sh_eth_chip_reset_giga(struct net_device *ndev)
192 {
193 int i;
194 unsigned long mahr[2], malr[2];
195
196 /* save MAHR and MALR */
197 for (i = 0; i < 2; i++) {
198 malr[i] = ioread32((void *)GIGA_MALR(i));
199 mahr[i] = ioread32((void *)GIGA_MAHR(i));
200 }
201
202 /* reset device */
203 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
204 mdelay(1);
205
206 /* restore MAHR and MALR */
207 for (i = 0; i < 2; i++) {
208 iowrite32(malr[i], (void *)GIGA_MALR(i));
209 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
210 }
211 }
212
213 static int sh_eth_is_gether(struct sh_eth_private *mdp);
214 static int sh_eth_reset(struct net_device *ndev)
215 {
216 struct sh_eth_private *mdp = netdev_priv(ndev);
217 int ret = 0;
218
219 if (sh_eth_is_gether(mdp)) {
220 sh_eth_write(ndev, 0x03, EDSR);
221 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
222 EDMR);
223
224 ret = sh_eth_check_reset(ndev);
225 if (ret)
226 goto out;
227
228 /* Table Init */
229 sh_eth_write(ndev, 0x0, TDLAR);
230 sh_eth_write(ndev, 0x0, TDFAR);
231 sh_eth_write(ndev, 0x0, TDFXR);
232 sh_eth_write(ndev, 0x0, TDFFR);
233 sh_eth_write(ndev, 0x0, RDLAR);
234 sh_eth_write(ndev, 0x0, RDFAR);
235 sh_eth_write(ndev, 0x0, RDFXR);
236 sh_eth_write(ndev, 0x0, RDFFR);
237 } else {
238 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
239 EDMR);
240 mdelay(3);
241 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
242 EDMR);
243 }
244
245 out:
246 return ret;
247 }
248
249 static void sh_eth_set_duplex_giga(struct net_device *ndev)
250 {
251 struct sh_eth_private *mdp = netdev_priv(ndev);
252
253 if (mdp->duplex) /* Full */
254 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
255 else /* Half */
256 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
257 }
258
259 static void sh_eth_set_rate_giga(struct net_device *ndev)
260 {
261 struct sh_eth_private *mdp = netdev_priv(ndev);
262
263 switch (mdp->speed) {
264 case 10: /* 10BASE */
265 sh_eth_write(ndev, 0x00000000, GECMR);
266 break;
267 case 100:/* 100BASE */
268 sh_eth_write(ndev, 0x00000010, GECMR);
269 break;
270 case 1000: /* 1000BASE */
271 sh_eth_write(ndev, 0x00000020, GECMR);
272 break;
273 default:
274 break;
275 }
276 }
277
278 /* SH7757(GETHERC) */
279 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
280 .chip_reset = sh_eth_chip_reset_giga,
281 .set_duplex = sh_eth_set_duplex_giga,
282 .set_rate = sh_eth_set_rate_giga,
283
284 .ecsr_value = ECSR_ICD | ECSR_MPD,
285 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
286 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
287
288 .tx_check = EESR_TC1 | EESR_FTC,
289 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
290 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
291 EESR_ECI,
292 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
293 EESR_TFE,
294 .fdr_value = 0x0000072f,
295 .rmcr_value = 0x00000001,
296
297 .apr = 1,
298 .mpr = 1,
299 .tpauser = 1,
300 .bculr = 1,
301 .hw_swap = 1,
302 .rpadir = 1,
303 .rpadir_value = 2 << 16,
304 .no_trimd = 1,
305 .no_ade = 1,
306 .tsu = 1,
307 };
308
309 static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
310 {
311 if (sh_eth_is_gether(mdp))
312 return &sh_eth_my_cpu_data_giga;
313 else
314 return &sh_eth_my_cpu_data;
315 }
316
317 #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
318 #define SH_ETH_HAS_TSU 1
319 static int sh_eth_check_reset(struct net_device *ndev);
320 static void sh_eth_reset_hw_crc(struct net_device *ndev);
321
322 static void sh_eth_chip_reset(struct net_device *ndev)
323 {
324 struct sh_eth_private *mdp = netdev_priv(ndev);
325
326 /* reset device */
327 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
328 mdelay(1);
329 }
330
331 static void sh_eth_set_duplex(struct net_device *ndev)
332 {
333 struct sh_eth_private *mdp = netdev_priv(ndev);
334
335 if (mdp->duplex) /* Full */
336 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
337 else /* Half */
338 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
339 }
340
341 static void sh_eth_set_rate(struct net_device *ndev)
342 {
343 struct sh_eth_private *mdp = netdev_priv(ndev);
344
345 switch (mdp->speed) {
346 case 10: /* 10BASE */
347 sh_eth_write(ndev, GECMR_10, GECMR);
348 break;
349 case 100:/* 100BASE */
350 sh_eth_write(ndev, GECMR_100, GECMR);
351 break;
352 case 1000: /* 1000BASE */
353 sh_eth_write(ndev, GECMR_1000, GECMR);
354 break;
355 default:
356 break;
357 }
358 }
359
360 /* sh7763 */
361 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
362 .chip_reset = sh_eth_chip_reset,
363 .set_duplex = sh_eth_set_duplex,
364 .set_rate = sh_eth_set_rate,
365
366 .ecsr_value = ECSR_ICD | ECSR_MPD,
367 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
368 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
369
370 .tx_check = EESR_TC1 | EESR_FTC,
371 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
372 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
373 EESR_ECI,
374 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
375 EESR_TFE,
376
377 .apr = 1,
378 .mpr = 1,
379 .tpauser = 1,
380 .bculr = 1,
381 .hw_swap = 1,
382 .no_trimd = 1,
383 .no_ade = 1,
384 .tsu = 1,
385 #if defined(CONFIG_CPU_SUBTYPE_SH7734)
386 .hw_crc = 1,
387 .select_mii = 1,
388 #endif
389 };
390
391 static int sh_eth_reset(struct net_device *ndev)
392 {
393 int ret = 0;
394
395 sh_eth_write(ndev, EDSR_ENALL, EDSR);
396 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
397
398 ret = sh_eth_check_reset(ndev);
399 if (ret)
400 goto out;
401
402 /* Table Init */
403 sh_eth_write(ndev, 0x0, TDLAR);
404 sh_eth_write(ndev, 0x0, TDFAR);
405 sh_eth_write(ndev, 0x0, TDFXR);
406 sh_eth_write(ndev, 0x0, TDFFR);
407 sh_eth_write(ndev, 0x0, RDLAR);
408 sh_eth_write(ndev, 0x0, RDFAR);
409 sh_eth_write(ndev, 0x0, RDFXR);
410 sh_eth_write(ndev, 0x0, RDFFR);
411
412 /* Reset HW CRC register */
413 sh_eth_reset_hw_crc(ndev);
414
415 /* Select MII mode */
416 if (sh_eth_my_cpu_data.select_mii)
417 sh_eth_select_mii(ndev);
418 out:
419 return ret;
420 }
421
422 static void sh_eth_reset_hw_crc(struct net_device *ndev)
423 {
424 if (sh_eth_my_cpu_data.hw_crc)
425 sh_eth_write(ndev, 0x0, CSMR);
426 }
427
428 #elif defined(CONFIG_ARCH_R8A7740)
429 #define SH_ETH_HAS_TSU 1
430 static int sh_eth_check_reset(struct net_device *ndev);
431
432 static void sh_eth_chip_reset(struct net_device *ndev)
433 {
434 struct sh_eth_private *mdp = netdev_priv(ndev);
435
436 /* reset device */
437 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
438 mdelay(1);
439
440 sh_eth_select_mii(ndev);
441 }
442
443 static int sh_eth_reset(struct net_device *ndev)
444 {
445 int ret = 0;
446
447 sh_eth_write(ndev, EDSR_ENALL, EDSR);
448 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
449
450 ret = sh_eth_check_reset(ndev);
451 if (ret)
452 goto out;
453
454 /* Table Init */
455 sh_eth_write(ndev, 0x0, TDLAR);
456 sh_eth_write(ndev, 0x0, TDFAR);
457 sh_eth_write(ndev, 0x0, TDFXR);
458 sh_eth_write(ndev, 0x0, TDFFR);
459 sh_eth_write(ndev, 0x0, RDLAR);
460 sh_eth_write(ndev, 0x0, RDFAR);
461 sh_eth_write(ndev, 0x0, RDFXR);
462 sh_eth_write(ndev, 0x0, RDFFR);
463
464 out:
465 return ret;
466 }
467
468 static void sh_eth_set_duplex(struct net_device *ndev)
469 {
470 struct sh_eth_private *mdp = netdev_priv(ndev);
471
472 if (mdp->duplex) /* Full */
473 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
474 else /* Half */
475 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
476 }
477
478 static void sh_eth_set_rate(struct net_device *ndev)
479 {
480 struct sh_eth_private *mdp = netdev_priv(ndev);
481
482 switch (mdp->speed) {
483 case 10: /* 10BASE */
484 sh_eth_write(ndev, GECMR_10, GECMR);
485 break;
486 case 100:/* 100BASE */
487 sh_eth_write(ndev, GECMR_100, GECMR);
488 break;
489 case 1000: /* 1000BASE */
490 sh_eth_write(ndev, GECMR_1000, GECMR);
491 break;
492 default:
493 break;
494 }
495 }
496
497 /* R8A7740 */
498 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
499 .chip_reset = sh_eth_chip_reset,
500 .set_duplex = sh_eth_set_duplex,
501 .set_rate = sh_eth_set_rate,
502
503 .ecsr_value = ECSR_ICD | ECSR_MPD,
504 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
505 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
506
507 .tx_check = EESR_TC1 | EESR_FTC,
508 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
509 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
510 EESR_ECI,
511 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
512 EESR_TFE,
513
514 .apr = 1,
515 .mpr = 1,
516 .tpauser = 1,
517 .bculr = 1,
518 .hw_swap = 1,
519 .no_trimd = 1,
520 .no_ade = 1,
521 .tsu = 1,
522 .select_mii = 1,
523 };
524
525 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
526 #define SH_ETH_RESET_DEFAULT 1
527 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
528 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
529
530 .apr = 1,
531 .mpr = 1,
532 .tpauser = 1,
533 .hw_swap = 1,
534 };
535 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
536 #define SH_ETH_RESET_DEFAULT 1
537 #define SH_ETH_HAS_TSU 1
538 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
539 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
540 .tsu = 1,
541 };
542 #endif
543
544 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
545 {
546 if (!cd->ecsr_value)
547 cd->ecsr_value = DEFAULT_ECSR_INIT;
548
549 if (!cd->ecsipr_value)
550 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
551
552 if (!cd->fcftr_value)
553 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
554 DEFAULT_FIFO_F_D_RFD;
555
556 if (!cd->fdr_value)
557 cd->fdr_value = DEFAULT_FDR_INIT;
558
559 if (!cd->rmcr_value)
560 cd->rmcr_value = DEFAULT_RMCR_VALUE;
561
562 if (!cd->tx_check)
563 cd->tx_check = DEFAULT_TX_CHECK;
564
565 if (!cd->eesr_err_check)
566 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
567
568 if (!cd->tx_error_check)
569 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
570 }
571
572 #if defined(SH_ETH_RESET_DEFAULT)
573 /* Chip Reset */
574 static int sh_eth_reset(struct net_device *ndev)
575 {
576 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
577 mdelay(3);
578 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
579
580 return 0;
581 }
582 #else
583 static int sh_eth_check_reset(struct net_device *ndev)
584 {
585 int ret = 0;
586 int cnt = 100;
587
588 while (cnt > 0) {
589 if (!(sh_eth_read(ndev, EDMR) & 0x3))
590 break;
591 mdelay(1);
592 cnt--;
593 }
594 if (cnt < 0) {
595 printk(KERN_ERR "Device reset fail\n");
596 ret = -ETIMEDOUT;
597 }
598 return ret;
599 }
600 #endif
601
602 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
603 static void sh_eth_set_receive_align(struct sk_buff *skb)
604 {
605 int reserve;
606
607 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
608 if (reserve)
609 skb_reserve(skb, reserve);
610 }
611 #else
612 static void sh_eth_set_receive_align(struct sk_buff *skb)
613 {
614 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
615 }
616 #endif
617
618
619 /* CPU <-> EDMAC endian convert */
620 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
621 {
622 switch (mdp->edmac_endian) {
623 case EDMAC_LITTLE_ENDIAN:
624 return cpu_to_le32(x);
625 case EDMAC_BIG_ENDIAN:
626 return cpu_to_be32(x);
627 }
628 return x;
629 }
630
631 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
632 {
633 switch (mdp->edmac_endian) {
634 case EDMAC_LITTLE_ENDIAN:
635 return le32_to_cpu(x);
636 case EDMAC_BIG_ENDIAN:
637 return be32_to_cpu(x);
638 }
639 return x;
640 }
641
642 /*
643 * Program the hardware MAC address from dev->dev_addr.
644 */
645 static void update_mac_address(struct net_device *ndev)
646 {
647 sh_eth_write(ndev,
648 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
649 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
650 sh_eth_write(ndev,
651 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
652 }
653
654 /*
655 * Get MAC address from SuperH MAC address register
656 *
657 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
658 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
659 * When you want use this device, you must set MAC address in bootloader.
660 *
661 */
662 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
663 {
664 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
665 memcpy(ndev->dev_addr, mac, 6);
666 } else {
667 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
668 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
669 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
670 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
671 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
672 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
673 }
674 }
675
676 static int sh_eth_is_gether(struct sh_eth_private *mdp)
677 {
678 if (mdp->reg_offset == sh_eth_offset_gigabit)
679 return 1;
680 else
681 return 0;
682 }
683
684 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
685 {
686 if (sh_eth_is_gether(mdp))
687 return EDTRR_TRNS_GETHER;
688 else
689 return EDTRR_TRNS_ETHER;
690 }
691
692 struct bb_info {
693 void (*set_gate)(void *addr);
694 struct mdiobb_ctrl ctrl;
695 void *addr;
696 u32 mmd_msk;/* MMD */
697 u32 mdo_msk;
698 u32 mdi_msk;
699 u32 mdc_msk;
700 };
701
702 /* PHY bit set */
703 static void bb_set(void *addr, u32 msk)
704 {
705 iowrite32(ioread32(addr) | msk, addr);
706 }
707
708 /* PHY bit clear */
709 static void bb_clr(void *addr, u32 msk)
710 {
711 iowrite32((ioread32(addr) & ~msk), addr);
712 }
713
714 /* PHY bit read */
715 static int bb_read(void *addr, u32 msk)
716 {
717 return (ioread32(addr) & msk) != 0;
718 }
719
720 /* Data I/O pin control */
721 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
722 {
723 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
724
725 if (bitbang->set_gate)
726 bitbang->set_gate(bitbang->addr);
727
728 if (bit)
729 bb_set(bitbang->addr, bitbang->mmd_msk);
730 else
731 bb_clr(bitbang->addr, bitbang->mmd_msk);
732 }
733
734 /* Set bit data*/
735 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
736 {
737 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
738
739 if (bitbang->set_gate)
740 bitbang->set_gate(bitbang->addr);
741
742 if (bit)
743 bb_set(bitbang->addr, bitbang->mdo_msk);
744 else
745 bb_clr(bitbang->addr, bitbang->mdo_msk);
746 }
747
748 /* Get bit data*/
749 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
750 {
751 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
752
753 if (bitbang->set_gate)
754 bitbang->set_gate(bitbang->addr);
755
756 return bb_read(bitbang->addr, bitbang->mdi_msk);
757 }
758
759 /* MDC pin control */
760 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
761 {
762 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
763
764 if (bitbang->set_gate)
765 bitbang->set_gate(bitbang->addr);
766
767 if (bit)
768 bb_set(bitbang->addr, bitbang->mdc_msk);
769 else
770 bb_clr(bitbang->addr, bitbang->mdc_msk);
771 }
772
773 /* mdio bus control struct */
774 static struct mdiobb_ops bb_ops = {
775 .owner = THIS_MODULE,
776 .set_mdc = sh_mdc_ctrl,
777 .set_mdio_dir = sh_mmd_ctrl,
778 .set_mdio_data = sh_set_mdio,
779 .get_mdio_data = sh_get_mdio,
780 };
781
782 /* free skb and descriptor buffer */
783 static void sh_eth_ring_free(struct net_device *ndev)
784 {
785 struct sh_eth_private *mdp = netdev_priv(ndev);
786 int i;
787
788 /* Free Rx skb ringbuffer */
789 if (mdp->rx_skbuff) {
790 for (i = 0; i < mdp->num_rx_ring; i++) {
791 if (mdp->rx_skbuff[i])
792 dev_kfree_skb(mdp->rx_skbuff[i]);
793 }
794 }
795 kfree(mdp->rx_skbuff);
796 mdp->rx_skbuff = NULL;
797
798 /* Free Tx skb ringbuffer */
799 if (mdp->tx_skbuff) {
800 for (i = 0; i < mdp->num_tx_ring; i++) {
801 if (mdp->tx_skbuff[i])
802 dev_kfree_skb(mdp->tx_skbuff[i]);
803 }
804 }
805 kfree(mdp->tx_skbuff);
806 mdp->tx_skbuff = NULL;
807 }
808
809 /* format skb and descriptor buffer */
810 static void sh_eth_ring_format(struct net_device *ndev)
811 {
812 struct sh_eth_private *mdp = netdev_priv(ndev);
813 int i;
814 struct sk_buff *skb;
815 struct sh_eth_rxdesc *rxdesc = NULL;
816 struct sh_eth_txdesc *txdesc = NULL;
817 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
818 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
819
820 mdp->cur_rx = mdp->cur_tx = 0;
821 mdp->dirty_rx = mdp->dirty_tx = 0;
822
823 memset(mdp->rx_ring, 0, rx_ringsize);
824
825 /* build Rx ring buffer */
826 for (i = 0; i < mdp->num_rx_ring; i++) {
827 /* skb */
828 mdp->rx_skbuff[i] = NULL;
829 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
830 mdp->rx_skbuff[i] = skb;
831 if (skb == NULL)
832 break;
833 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
834 DMA_FROM_DEVICE);
835 sh_eth_set_receive_align(skb);
836
837 /* RX descriptor */
838 rxdesc = &mdp->rx_ring[i];
839 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
840 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
841
842 /* The size of the buffer is 16 byte boundary. */
843 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
844 /* Rx descriptor address set */
845 if (i == 0) {
846 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
847 if (sh_eth_is_gether(mdp))
848 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
849 }
850 }
851
852 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
853
854 /* Mark the last entry as wrapping the ring. */
855 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
856
857 memset(mdp->tx_ring, 0, tx_ringsize);
858
859 /* build Tx ring buffer */
860 for (i = 0; i < mdp->num_tx_ring; i++) {
861 mdp->tx_skbuff[i] = NULL;
862 txdesc = &mdp->tx_ring[i];
863 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
864 txdesc->buffer_length = 0;
865 if (i == 0) {
866 /* Tx descriptor address set */
867 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
868 if (sh_eth_is_gether(mdp))
869 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
870 }
871 }
872
873 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
874 }
875
876 /* Get skb and descriptor buffer */
877 static int sh_eth_ring_init(struct net_device *ndev)
878 {
879 struct sh_eth_private *mdp = netdev_priv(ndev);
880 int rx_ringsize, tx_ringsize, ret = 0;
881
882 /*
883 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
884 * card needs room to do 8 byte alignment, +2 so we can reserve
885 * the first 2 bytes, and +16 gets room for the status word from the
886 * card.
887 */
888 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
889 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
890 if (mdp->cd->rpadir)
891 mdp->rx_buf_sz += NET_IP_ALIGN;
892
893 /* Allocate RX and TX skb rings */
894 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
895 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
896 if (!mdp->rx_skbuff) {
897 ret = -ENOMEM;
898 return ret;
899 }
900
901 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
902 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
903 if (!mdp->tx_skbuff) {
904 ret = -ENOMEM;
905 goto skb_ring_free;
906 }
907
908 /* Allocate all Rx descriptors. */
909 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
910 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
911 GFP_KERNEL);
912
913 if (!mdp->rx_ring) {
914 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
915 rx_ringsize);
916 ret = -ENOMEM;
917 goto desc_ring_free;
918 }
919
920 mdp->dirty_rx = 0;
921
922 /* Allocate all Tx descriptors. */
923 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
924 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
925 GFP_KERNEL);
926 if (!mdp->tx_ring) {
927 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
928 tx_ringsize);
929 ret = -ENOMEM;
930 goto desc_ring_free;
931 }
932 return ret;
933
934 desc_ring_free:
935 /* free DMA buffer */
936 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
937
938 skb_ring_free:
939 /* Free Rx and Tx skb ring buffer */
940 sh_eth_ring_free(ndev);
941 mdp->tx_ring = NULL;
942 mdp->rx_ring = NULL;
943
944 return ret;
945 }
946
947 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
948 {
949 int ringsize;
950
951 if (mdp->rx_ring) {
952 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
953 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
954 mdp->rx_desc_dma);
955 mdp->rx_ring = NULL;
956 }
957
958 if (mdp->tx_ring) {
959 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
960 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
961 mdp->tx_desc_dma);
962 mdp->tx_ring = NULL;
963 }
964 }
965
966 static int sh_eth_dev_init(struct net_device *ndev, bool start)
967 {
968 int ret = 0;
969 struct sh_eth_private *mdp = netdev_priv(ndev);
970 u32 val;
971
972 /* Soft Reset */
973 ret = sh_eth_reset(ndev);
974 if (ret)
975 goto out;
976
977 /* Descriptor format */
978 sh_eth_ring_format(ndev);
979 if (mdp->cd->rpadir)
980 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
981
982 /* all sh_eth int mask */
983 sh_eth_write(ndev, 0, EESIPR);
984
985 #if defined(__LITTLE_ENDIAN)
986 if (mdp->cd->hw_swap)
987 sh_eth_write(ndev, EDMR_EL, EDMR);
988 else
989 #endif
990 sh_eth_write(ndev, 0, EDMR);
991
992 /* FIFO size set */
993 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
994 sh_eth_write(ndev, 0, TFTR);
995
996 /* Frame recv control */
997 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
998
999 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1000
1001 if (mdp->cd->bculr)
1002 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1003
1004 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1005
1006 if (!mdp->cd->no_trimd)
1007 sh_eth_write(ndev, 0, TRIMD);
1008
1009 /* Recv frame limit set register */
1010 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1011 RFLR);
1012
1013 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1014 if (start)
1015 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1016
1017 /* PAUSE Prohibition */
1018 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1019 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1020
1021 sh_eth_write(ndev, val, ECMR);
1022
1023 if (mdp->cd->set_rate)
1024 mdp->cd->set_rate(ndev);
1025
1026 /* E-MAC Status Register clear */
1027 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1028
1029 /* E-MAC Interrupt Enable register */
1030 if (start)
1031 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1032
1033 /* Set MAC address */
1034 update_mac_address(ndev);
1035
1036 /* mask reset */
1037 if (mdp->cd->apr)
1038 sh_eth_write(ndev, APR_AP, APR);
1039 if (mdp->cd->mpr)
1040 sh_eth_write(ndev, MPR_MP, MPR);
1041 if (mdp->cd->tpauser)
1042 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1043
1044 if (start) {
1045 /* Setting the Rx mode will start the Rx process. */
1046 sh_eth_write(ndev, EDRRR_R, EDRRR);
1047
1048 netif_start_queue(ndev);
1049 }
1050
1051 out:
1052 return ret;
1053 }
1054
1055 /* free Tx skb function */
1056 static int sh_eth_txfree(struct net_device *ndev)
1057 {
1058 struct sh_eth_private *mdp = netdev_priv(ndev);
1059 struct sh_eth_txdesc *txdesc;
1060 int freeNum = 0;
1061 int entry = 0;
1062
1063 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1064 entry = mdp->dirty_tx % mdp->num_tx_ring;
1065 txdesc = &mdp->tx_ring[entry];
1066 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1067 break;
1068 /* Free the original skb. */
1069 if (mdp->tx_skbuff[entry]) {
1070 dma_unmap_single(&ndev->dev, txdesc->addr,
1071 txdesc->buffer_length, DMA_TO_DEVICE);
1072 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1073 mdp->tx_skbuff[entry] = NULL;
1074 freeNum++;
1075 }
1076 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1077 if (entry >= mdp->num_tx_ring - 1)
1078 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1079
1080 ndev->stats.tx_packets++;
1081 ndev->stats.tx_bytes += txdesc->buffer_length;
1082 }
1083 return freeNum;
1084 }
1085
1086 /* Packet receive function */
1087 static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
1088 {
1089 struct sh_eth_private *mdp = netdev_priv(ndev);
1090 struct sh_eth_rxdesc *rxdesc;
1091
1092 int entry = mdp->cur_rx % mdp->num_rx_ring;
1093 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1094 struct sk_buff *skb;
1095 u16 pkt_len = 0;
1096 u32 desc_status;
1097
1098 rxdesc = &mdp->rx_ring[entry];
1099 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1100 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1101 pkt_len = rxdesc->frame_length;
1102
1103 #if defined(CONFIG_ARCH_R8A7740)
1104 desc_status >>= 16;
1105 #endif
1106
1107 if (--boguscnt < 0)
1108 break;
1109
1110 if (!(desc_status & RDFEND))
1111 ndev->stats.rx_length_errors++;
1112
1113 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1114 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1115 ndev->stats.rx_errors++;
1116 if (desc_status & RD_RFS1)
1117 ndev->stats.rx_crc_errors++;
1118 if (desc_status & RD_RFS2)
1119 ndev->stats.rx_frame_errors++;
1120 if (desc_status & RD_RFS3)
1121 ndev->stats.rx_length_errors++;
1122 if (desc_status & RD_RFS4)
1123 ndev->stats.rx_length_errors++;
1124 if (desc_status & RD_RFS6)
1125 ndev->stats.rx_missed_errors++;
1126 if (desc_status & RD_RFS10)
1127 ndev->stats.rx_over_errors++;
1128 } else {
1129 if (!mdp->cd->hw_swap)
1130 sh_eth_soft_swap(
1131 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1132 pkt_len + 2);
1133 skb = mdp->rx_skbuff[entry];
1134 mdp->rx_skbuff[entry] = NULL;
1135 if (mdp->cd->rpadir)
1136 skb_reserve(skb, NET_IP_ALIGN);
1137 skb_put(skb, pkt_len);
1138 skb->protocol = eth_type_trans(skb, ndev);
1139 netif_rx(skb);
1140 ndev->stats.rx_packets++;
1141 ndev->stats.rx_bytes += pkt_len;
1142 }
1143 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1144 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1145 rxdesc = &mdp->rx_ring[entry];
1146 }
1147
1148 /* Refill the Rx ring buffers. */
1149 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1150 entry = mdp->dirty_rx % mdp->num_rx_ring;
1151 rxdesc = &mdp->rx_ring[entry];
1152 /* The size of the buffer is 16 byte boundary. */
1153 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1154
1155 if (mdp->rx_skbuff[entry] == NULL) {
1156 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1157 mdp->rx_skbuff[entry] = skb;
1158 if (skb == NULL)
1159 break; /* Better luck next round. */
1160 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1161 DMA_FROM_DEVICE);
1162 sh_eth_set_receive_align(skb);
1163
1164 skb_checksum_none_assert(skb);
1165 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1166 }
1167 if (entry >= mdp->num_rx_ring - 1)
1168 rxdesc->status |=
1169 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1170 else
1171 rxdesc->status |=
1172 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1173 }
1174
1175 /* Restart Rx engine if stopped. */
1176 /* If we don't need to check status, don't. -KDU */
1177 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1178 /* fix the values for the next receiving if RDE is set */
1179 if (intr_status & EESR_RDE)
1180 mdp->cur_rx = mdp->dirty_rx =
1181 (sh_eth_read(ndev, RDFAR) -
1182 sh_eth_read(ndev, RDLAR)) >> 4;
1183 sh_eth_write(ndev, EDRRR_R, EDRRR);
1184 }
1185
1186 return 0;
1187 }
1188
1189 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1190 {
1191 /* disable tx and rx */
1192 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1193 ~(ECMR_RE | ECMR_TE), ECMR);
1194 }
1195
1196 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1197 {
1198 /* enable tx and rx */
1199 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1200 (ECMR_RE | ECMR_TE), ECMR);
1201 }
1202
1203 /* error control function */
1204 static void sh_eth_error(struct net_device *ndev, int intr_status)
1205 {
1206 struct sh_eth_private *mdp = netdev_priv(ndev);
1207 u32 felic_stat;
1208 u32 link_stat;
1209 u32 mask;
1210
1211 if (intr_status & EESR_ECI) {
1212 felic_stat = sh_eth_read(ndev, ECSR);
1213 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1214 if (felic_stat & ECSR_ICD)
1215 ndev->stats.tx_carrier_errors++;
1216 if (felic_stat & ECSR_LCHNG) {
1217 /* Link Changed */
1218 if (mdp->cd->no_psr || mdp->no_ether_link) {
1219 goto ignore_link;
1220 } else {
1221 link_stat = (sh_eth_read(ndev, PSR));
1222 if (mdp->ether_link_active_low)
1223 link_stat = ~link_stat;
1224 }
1225 if (!(link_stat & PHY_ST_LINK))
1226 sh_eth_rcv_snd_disable(ndev);
1227 else {
1228 /* Link Up */
1229 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1230 ~DMAC_M_ECI, EESIPR);
1231 /*clear int */
1232 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1233 ECSR);
1234 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1235 DMAC_M_ECI, EESIPR);
1236 /* enable tx and rx */
1237 sh_eth_rcv_snd_enable(ndev);
1238 }
1239 }
1240 }
1241
1242 ignore_link:
1243 if (intr_status & EESR_TWB) {
1244 /* Write buck end. unused write back interrupt */
1245 if (intr_status & EESR_TABT) /* Transmit Abort int */
1246 ndev->stats.tx_aborted_errors++;
1247 if (netif_msg_tx_err(mdp))
1248 dev_err(&ndev->dev, "Transmit Abort\n");
1249 }
1250
1251 if (intr_status & EESR_RABT) {
1252 /* Receive Abort int */
1253 if (intr_status & EESR_RFRMER) {
1254 /* Receive Frame Overflow int */
1255 ndev->stats.rx_frame_errors++;
1256 if (netif_msg_rx_err(mdp))
1257 dev_err(&ndev->dev, "Receive Abort\n");
1258 }
1259 }
1260
1261 if (intr_status & EESR_TDE) {
1262 /* Transmit Descriptor Empty int */
1263 ndev->stats.tx_fifo_errors++;
1264 if (netif_msg_tx_err(mdp))
1265 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1266 }
1267
1268 if (intr_status & EESR_TFE) {
1269 /* FIFO under flow */
1270 ndev->stats.tx_fifo_errors++;
1271 if (netif_msg_tx_err(mdp))
1272 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1273 }
1274
1275 if (intr_status & EESR_RDE) {
1276 /* Receive Descriptor Empty int */
1277 ndev->stats.rx_over_errors++;
1278
1279 if (netif_msg_rx_err(mdp))
1280 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1281 }
1282
1283 if (intr_status & EESR_RFE) {
1284 /* Receive FIFO Overflow int */
1285 ndev->stats.rx_fifo_errors++;
1286 if (netif_msg_rx_err(mdp))
1287 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1288 }
1289
1290 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1291 /* Address Error */
1292 ndev->stats.tx_fifo_errors++;
1293 if (netif_msg_tx_err(mdp))
1294 dev_err(&ndev->dev, "Address Error\n");
1295 }
1296
1297 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1298 if (mdp->cd->no_ade)
1299 mask &= ~EESR_ADE;
1300 if (intr_status & mask) {
1301 /* Tx error */
1302 u32 edtrr = sh_eth_read(ndev, EDTRR);
1303 /* dmesg */
1304 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1305 intr_status, mdp->cur_tx);
1306 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1307 mdp->dirty_tx, (u32) ndev->state, edtrr);
1308 /* dirty buffer free */
1309 sh_eth_txfree(ndev);
1310
1311 /* SH7712 BUG */
1312 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1313 /* tx dma start */
1314 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1315 }
1316 /* wakeup */
1317 netif_wake_queue(ndev);
1318 }
1319 }
1320
1321 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1322 {
1323 struct net_device *ndev = netdev;
1324 struct sh_eth_private *mdp = netdev_priv(ndev);
1325 struct sh_eth_cpu_data *cd = mdp->cd;
1326 irqreturn_t ret = IRQ_NONE;
1327 unsigned long intr_status;
1328
1329 spin_lock(&mdp->lock);
1330
1331 /* Get interrupt status */
1332 intr_status = sh_eth_read(ndev, EESR);
1333 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1334 * enabled since it's the one that comes thru regardless of the mask,
1335 * and we need to fully handle it in sh_eth_error() in order to quench
1336 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1337 */
1338 intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
1339 /* Clear interrupt */
1340 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1341 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1342 cd->tx_check | cd->eesr_err_check)) {
1343 sh_eth_write(ndev, intr_status, EESR);
1344 ret = IRQ_HANDLED;
1345 } else
1346 goto other_irq;
1347
1348 if (intr_status & (EESR_FRC | /* Frame recv*/
1349 EESR_RMAF | /* Multi cast address recv*/
1350 EESR_RRF | /* Bit frame recv */
1351 EESR_RTLF | /* Long frame recv*/
1352 EESR_RTSF | /* short frame recv */
1353 EESR_PRE | /* PHY-LSI recv error */
1354 EESR_CERF)){ /* recv frame CRC error */
1355 sh_eth_rx(ndev, intr_status);
1356 }
1357
1358 /* Tx Check */
1359 if (intr_status & cd->tx_check) {
1360 sh_eth_txfree(ndev);
1361 netif_wake_queue(ndev);
1362 }
1363
1364 if (intr_status & cd->eesr_err_check)
1365 sh_eth_error(ndev, intr_status);
1366
1367 other_irq:
1368 spin_unlock(&mdp->lock);
1369
1370 return ret;
1371 }
1372
1373 /* PHY state control function */
1374 static void sh_eth_adjust_link(struct net_device *ndev)
1375 {
1376 struct sh_eth_private *mdp = netdev_priv(ndev);
1377 struct phy_device *phydev = mdp->phydev;
1378 int new_state = 0;
1379
1380 if (phydev->link) {
1381 if (phydev->duplex != mdp->duplex) {
1382 new_state = 1;
1383 mdp->duplex = phydev->duplex;
1384 if (mdp->cd->set_duplex)
1385 mdp->cd->set_duplex(ndev);
1386 }
1387
1388 if (phydev->speed != mdp->speed) {
1389 new_state = 1;
1390 mdp->speed = phydev->speed;
1391 if (mdp->cd->set_rate)
1392 mdp->cd->set_rate(ndev);
1393 }
1394 if (!mdp->link) {
1395 sh_eth_write(ndev,
1396 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1397 new_state = 1;
1398 mdp->link = phydev->link;
1399 if (mdp->cd->no_psr || mdp->no_ether_link)
1400 sh_eth_rcv_snd_enable(ndev);
1401 }
1402 } else if (mdp->link) {
1403 new_state = 1;
1404 mdp->link = 0;
1405 mdp->speed = 0;
1406 mdp->duplex = -1;
1407 if (mdp->cd->no_psr || mdp->no_ether_link)
1408 sh_eth_rcv_snd_disable(ndev);
1409 }
1410
1411 if (new_state && netif_msg_link(mdp))
1412 phy_print_status(phydev);
1413 }
1414
1415 /* PHY init function */
1416 static int sh_eth_phy_init(struct net_device *ndev)
1417 {
1418 struct sh_eth_private *mdp = netdev_priv(ndev);
1419 char phy_id[MII_BUS_ID_SIZE + 3];
1420 struct phy_device *phydev = NULL;
1421
1422 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1423 mdp->mii_bus->id , mdp->phy_id);
1424
1425 mdp->link = 0;
1426 mdp->speed = 0;
1427 mdp->duplex = -1;
1428
1429 /* Try connect to PHY */
1430 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1431 mdp->phy_interface);
1432 if (IS_ERR(phydev)) {
1433 dev_err(&ndev->dev, "phy_connect failed\n");
1434 return PTR_ERR(phydev);
1435 }
1436
1437 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1438 phydev->addr, phydev->drv->name);
1439
1440 mdp->phydev = phydev;
1441
1442 return 0;
1443 }
1444
1445 /* PHY control start function */
1446 static int sh_eth_phy_start(struct net_device *ndev)
1447 {
1448 struct sh_eth_private *mdp = netdev_priv(ndev);
1449 int ret;
1450
1451 ret = sh_eth_phy_init(ndev);
1452 if (ret)
1453 return ret;
1454
1455 /* reset phy - this also wakes it from PDOWN */
1456 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1457 phy_start(mdp->phydev);
1458
1459 return 0;
1460 }
1461
1462 static int sh_eth_get_settings(struct net_device *ndev,
1463 struct ethtool_cmd *ecmd)
1464 {
1465 struct sh_eth_private *mdp = netdev_priv(ndev);
1466 unsigned long flags;
1467 int ret;
1468
1469 spin_lock_irqsave(&mdp->lock, flags);
1470 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1471 spin_unlock_irqrestore(&mdp->lock, flags);
1472
1473 return ret;
1474 }
1475
1476 static int sh_eth_set_settings(struct net_device *ndev,
1477 struct ethtool_cmd *ecmd)
1478 {
1479 struct sh_eth_private *mdp = netdev_priv(ndev);
1480 unsigned long flags;
1481 int ret;
1482
1483 spin_lock_irqsave(&mdp->lock, flags);
1484
1485 /* disable tx and rx */
1486 sh_eth_rcv_snd_disable(ndev);
1487
1488 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1489 if (ret)
1490 goto error_exit;
1491
1492 if (ecmd->duplex == DUPLEX_FULL)
1493 mdp->duplex = 1;
1494 else
1495 mdp->duplex = 0;
1496
1497 if (mdp->cd->set_duplex)
1498 mdp->cd->set_duplex(ndev);
1499
1500 error_exit:
1501 mdelay(1);
1502
1503 /* enable tx and rx */
1504 sh_eth_rcv_snd_enable(ndev);
1505
1506 spin_unlock_irqrestore(&mdp->lock, flags);
1507
1508 return ret;
1509 }
1510
1511 static int sh_eth_nway_reset(struct net_device *ndev)
1512 {
1513 struct sh_eth_private *mdp = netdev_priv(ndev);
1514 unsigned long flags;
1515 int ret;
1516
1517 spin_lock_irqsave(&mdp->lock, flags);
1518 ret = phy_start_aneg(mdp->phydev);
1519 spin_unlock_irqrestore(&mdp->lock, flags);
1520
1521 return ret;
1522 }
1523
1524 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1525 {
1526 struct sh_eth_private *mdp = netdev_priv(ndev);
1527 return mdp->msg_enable;
1528 }
1529
1530 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1531 {
1532 struct sh_eth_private *mdp = netdev_priv(ndev);
1533 mdp->msg_enable = value;
1534 }
1535
1536 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1537 "rx_current", "tx_current",
1538 "rx_dirty", "tx_dirty",
1539 };
1540 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1541
1542 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1543 {
1544 switch (sset) {
1545 case ETH_SS_STATS:
1546 return SH_ETH_STATS_LEN;
1547 default:
1548 return -EOPNOTSUPP;
1549 }
1550 }
1551
1552 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1553 struct ethtool_stats *stats, u64 *data)
1554 {
1555 struct sh_eth_private *mdp = netdev_priv(ndev);
1556 int i = 0;
1557
1558 /* device-specific stats */
1559 data[i++] = mdp->cur_rx;
1560 data[i++] = mdp->cur_tx;
1561 data[i++] = mdp->dirty_rx;
1562 data[i++] = mdp->dirty_tx;
1563 }
1564
1565 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1566 {
1567 switch (stringset) {
1568 case ETH_SS_STATS:
1569 memcpy(data, *sh_eth_gstrings_stats,
1570 sizeof(sh_eth_gstrings_stats));
1571 break;
1572 }
1573 }
1574
1575 static void sh_eth_get_ringparam(struct net_device *ndev,
1576 struct ethtool_ringparam *ring)
1577 {
1578 struct sh_eth_private *mdp = netdev_priv(ndev);
1579
1580 ring->rx_max_pending = RX_RING_MAX;
1581 ring->tx_max_pending = TX_RING_MAX;
1582 ring->rx_pending = mdp->num_rx_ring;
1583 ring->tx_pending = mdp->num_tx_ring;
1584 }
1585
1586 static int sh_eth_set_ringparam(struct net_device *ndev,
1587 struct ethtool_ringparam *ring)
1588 {
1589 struct sh_eth_private *mdp = netdev_priv(ndev);
1590 int ret;
1591
1592 if (ring->tx_pending > TX_RING_MAX ||
1593 ring->rx_pending > RX_RING_MAX ||
1594 ring->tx_pending < TX_RING_MIN ||
1595 ring->rx_pending < RX_RING_MIN)
1596 return -EINVAL;
1597 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1598 return -EINVAL;
1599
1600 if (netif_running(ndev)) {
1601 netif_tx_disable(ndev);
1602 /* Disable interrupts by clearing the interrupt mask. */
1603 sh_eth_write(ndev, 0x0000, EESIPR);
1604 /* Stop the chip's Tx and Rx processes. */
1605 sh_eth_write(ndev, 0, EDTRR);
1606 sh_eth_write(ndev, 0, EDRRR);
1607 synchronize_irq(ndev->irq);
1608 }
1609
1610 /* Free all the skbuffs in the Rx queue. */
1611 sh_eth_ring_free(ndev);
1612 /* Free DMA buffer */
1613 sh_eth_free_dma_buffer(mdp);
1614
1615 /* Set new parameters */
1616 mdp->num_rx_ring = ring->rx_pending;
1617 mdp->num_tx_ring = ring->tx_pending;
1618
1619 ret = sh_eth_ring_init(ndev);
1620 if (ret < 0) {
1621 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1622 return ret;
1623 }
1624 ret = sh_eth_dev_init(ndev, false);
1625 if (ret < 0) {
1626 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1627 return ret;
1628 }
1629
1630 if (netif_running(ndev)) {
1631 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1632 /* Setting the Rx mode will start the Rx process. */
1633 sh_eth_write(ndev, EDRRR_R, EDRRR);
1634 netif_wake_queue(ndev);
1635 }
1636
1637 return 0;
1638 }
1639
1640 static const struct ethtool_ops sh_eth_ethtool_ops = {
1641 .get_settings = sh_eth_get_settings,
1642 .set_settings = sh_eth_set_settings,
1643 .nway_reset = sh_eth_nway_reset,
1644 .get_msglevel = sh_eth_get_msglevel,
1645 .set_msglevel = sh_eth_set_msglevel,
1646 .get_link = ethtool_op_get_link,
1647 .get_strings = sh_eth_get_strings,
1648 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1649 .get_sset_count = sh_eth_get_sset_count,
1650 .get_ringparam = sh_eth_get_ringparam,
1651 .set_ringparam = sh_eth_set_ringparam,
1652 };
1653
1654 /* network device open function */
1655 static int sh_eth_open(struct net_device *ndev)
1656 {
1657 int ret = 0;
1658 struct sh_eth_private *mdp = netdev_priv(ndev);
1659
1660 pm_runtime_get_sync(&mdp->pdev->dev);
1661
1662 ret = request_irq(ndev->irq, sh_eth_interrupt,
1663 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1664 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1665 defined(CONFIG_CPU_SUBTYPE_SH7757)
1666 IRQF_SHARED,
1667 #else
1668 0,
1669 #endif
1670 ndev->name, ndev);
1671 if (ret) {
1672 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1673 return ret;
1674 }
1675
1676 /* Descriptor set */
1677 ret = sh_eth_ring_init(ndev);
1678 if (ret)
1679 goto out_free_irq;
1680
1681 /* device init */
1682 ret = sh_eth_dev_init(ndev, true);
1683 if (ret)
1684 goto out_free_irq;
1685
1686 /* PHY control start*/
1687 ret = sh_eth_phy_start(ndev);
1688 if (ret)
1689 goto out_free_irq;
1690
1691 return ret;
1692
1693 out_free_irq:
1694 free_irq(ndev->irq, ndev);
1695 pm_runtime_put_sync(&mdp->pdev->dev);
1696 return ret;
1697 }
1698
1699 /* Timeout function */
1700 static void sh_eth_tx_timeout(struct net_device *ndev)
1701 {
1702 struct sh_eth_private *mdp = netdev_priv(ndev);
1703 struct sh_eth_rxdesc *rxdesc;
1704 int i;
1705
1706 netif_stop_queue(ndev);
1707
1708 if (netif_msg_timer(mdp))
1709 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1710 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1711
1712 /* tx_errors count up */
1713 ndev->stats.tx_errors++;
1714
1715 /* Free all the skbuffs in the Rx queue. */
1716 for (i = 0; i < mdp->num_rx_ring; i++) {
1717 rxdesc = &mdp->rx_ring[i];
1718 rxdesc->status = 0;
1719 rxdesc->addr = 0xBADF00D0;
1720 if (mdp->rx_skbuff[i])
1721 dev_kfree_skb(mdp->rx_skbuff[i]);
1722 mdp->rx_skbuff[i] = NULL;
1723 }
1724 for (i = 0; i < mdp->num_tx_ring; i++) {
1725 if (mdp->tx_skbuff[i])
1726 dev_kfree_skb(mdp->tx_skbuff[i]);
1727 mdp->tx_skbuff[i] = NULL;
1728 }
1729
1730 /* device init */
1731 sh_eth_dev_init(ndev, true);
1732 }
1733
1734 /* Packet transmit function */
1735 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1736 {
1737 struct sh_eth_private *mdp = netdev_priv(ndev);
1738 struct sh_eth_txdesc *txdesc;
1739 u32 entry;
1740 unsigned long flags;
1741
1742 spin_lock_irqsave(&mdp->lock, flags);
1743 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1744 if (!sh_eth_txfree(ndev)) {
1745 if (netif_msg_tx_queued(mdp))
1746 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1747 netif_stop_queue(ndev);
1748 spin_unlock_irqrestore(&mdp->lock, flags);
1749 return NETDEV_TX_BUSY;
1750 }
1751 }
1752 spin_unlock_irqrestore(&mdp->lock, flags);
1753
1754 entry = mdp->cur_tx % mdp->num_tx_ring;
1755 mdp->tx_skbuff[entry] = skb;
1756 txdesc = &mdp->tx_ring[entry];
1757 /* soft swap. */
1758 if (!mdp->cd->hw_swap)
1759 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1760 skb->len + 2);
1761 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1762 DMA_TO_DEVICE);
1763 if (skb->len < ETHERSMALL)
1764 txdesc->buffer_length = ETHERSMALL;
1765 else
1766 txdesc->buffer_length = skb->len;
1767
1768 if (entry >= mdp->num_tx_ring - 1)
1769 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1770 else
1771 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1772
1773 mdp->cur_tx++;
1774
1775 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1776 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1777
1778 return NETDEV_TX_OK;
1779 }
1780
1781 /* device close function */
1782 static int sh_eth_close(struct net_device *ndev)
1783 {
1784 struct sh_eth_private *mdp = netdev_priv(ndev);
1785
1786 netif_stop_queue(ndev);
1787
1788 /* Disable interrupts by clearing the interrupt mask. */
1789 sh_eth_write(ndev, 0x0000, EESIPR);
1790
1791 /* Stop the chip's Tx and Rx processes. */
1792 sh_eth_write(ndev, 0, EDTRR);
1793 sh_eth_write(ndev, 0, EDRRR);
1794
1795 /* PHY Disconnect */
1796 if (mdp->phydev) {
1797 phy_stop(mdp->phydev);
1798 phy_disconnect(mdp->phydev);
1799 }
1800
1801 free_irq(ndev->irq, ndev);
1802
1803 /* Free all the skbuffs in the Rx queue. */
1804 sh_eth_ring_free(ndev);
1805
1806 /* free DMA buffer */
1807 sh_eth_free_dma_buffer(mdp);
1808
1809 pm_runtime_put_sync(&mdp->pdev->dev);
1810
1811 return 0;
1812 }
1813
1814 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1815 {
1816 struct sh_eth_private *mdp = netdev_priv(ndev);
1817
1818 pm_runtime_get_sync(&mdp->pdev->dev);
1819
1820 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1821 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1822 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
1823 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1824 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1825 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
1826 if (sh_eth_is_gether(mdp)) {
1827 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1828 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1829 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1830 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1831 } else {
1832 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1833 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1834 }
1835 pm_runtime_put_sync(&mdp->pdev->dev);
1836
1837 return &ndev->stats;
1838 }
1839
1840 /* ioctl to device function */
1841 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1842 int cmd)
1843 {
1844 struct sh_eth_private *mdp = netdev_priv(ndev);
1845 struct phy_device *phydev = mdp->phydev;
1846
1847 if (!netif_running(ndev))
1848 return -EINVAL;
1849
1850 if (!phydev)
1851 return -ENODEV;
1852
1853 return phy_mii_ioctl(phydev, rq, cmd);
1854 }
1855
1856 #if defined(SH_ETH_HAS_TSU)
1857 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
1858 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
1859 int entry)
1860 {
1861 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
1862 }
1863
1864 static u32 sh_eth_tsu_get_post_mask(int entry)
1865 {
1866 return 0x0f << (28 - ((entry % 8) * 4));
1867 }
1868
1869 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
1870 {
1871 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
1872 }
1873
1874 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
1875 int entry)
1876 {
1877 struct sh_eth_private *mdp = netdev_priv(ndev);
1878 u32 tmp;
1879 void *reg_offset;
1880
1881 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
1882 tmp = ioread32(reg_offset);
1883 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
1884 }
1885
1886 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
1887 int entry)
1888 {
1889 struct sh_eth_private *mdp = netdev_priv(ndev);
1890 u32 post_mask, ref_mask, tmp;
1891 void *reg_offset;
1892
1893 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
1894 post_mask = sh_eth_tsu_get_post_mask(entry);
1895 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
1896
1897 tmp = ioread32(reg_offset);
1898 iowrite32(tmp & ~post_mask, reg_offset);
1899
1900 /* If other port enables, the function returns "true" */
1901 return tmp & ref_mask;
1902 }
1903
1904 static int sh_eth_tsu_busy(struct net_device *ndev)
1905 {
1906 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
1907 struct sh_eth_private *mdp = netdev_priv(ndev);
1908
1909 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
1910 udelay(10);
1911 timeout--;
1912 if (timeout <= 0) {
1913 dev_err(&ndev->dev, "%s: timeout\n", __func__);
1914 return -ETIMEDOUT;
1915 }
1916 }
1917
1918 return 0;
1919 }
1920
1921 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
1922 const u8 *addr)
1923 {
1924 u32 val;
1925
1926 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
1927 iowrite32(val, reg);
1928 if (sh_eth_tsu_busy(ndev) < 0)
1929 return -EBUSY;
1930
1931 val = addr[4] << 8 | addr[5];
1932 iowrite32(val, reg + 4);
1933 if (sh_eth_tsu_busy(ndev) < 0)
1934 return -EBUSY;
1935
1936 return 0;
1937 }
1938
1939 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
1940 {
1941 u32 val;
1942
1943 val = ioread32(reg);
1944 addr[0] = (val >> 24) & 0xff;
1945 addr[1] = (val >> 16) & 0xff;
1946 addr[2] = (val >> 8) & 0xff;
1947 addr[3] = val & 0xff;
1948 val = ioread32(reg + 4);
1949 addr[4] = (val >> 8) & 0xff;
1950 addr[5] = val & 0xff;
1951 }
1952
1953
1954 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
1955 {
1956 struct sh_eth_private *mdp = netdev_priv(ndev);
1957 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1958 int i;
1959 u8 c_addr[ETH_ALEN];
1960
1961 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
1962 sh_eth_tsu_read_entry(reg_offset, c_addr);
1963 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
1964 return i;
1965 }
1966
1967 return -ENOENT;
1968 }
1969
1970 static int sh_eth_tsu_find_empty(struct net_device *ndev)
1971 {
1972 u8 blank[ETH_ALEN];
1973 int entry;
1974
1975 memset(blank, 0, sizeof(blank));
1976 entry = sh_eth_tsu_find_entry(ndev, blank);
1977 return (entry < 0) ? -ENOMEM : entry;
1978 }
1979
1980 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
1981 int entry)
1982 {
1983 struct sh_eth_private *mdp = netdev_priv(ndev);
1984 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1985 int ret;
1986 u8 blank[ETH_ALEN];
1987
1988 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
1989 ~(1 << (31 - entry)), TSU_TEN);
1990
1991 memset(blank, 0, sizeof(blank));
1992 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
1993 if (ret < 0)
1994 return ret;
1995 return 0;
1996 }
1997
1998 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
1999 {
2000 struct sh_eth_private *mdp = netdev_priv(ndev);
2001 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2002 int i, ret;
2003
2004 if (!mdp->cd->tsu)
2005 return 0;
2006
2007 i = sh_eth_tsu_find_entry(ndev, addr);
2008 if (i < 0) {
2009 /* No entry found, create one */
2010 i = sh_eth_tsu_find_empty(ndev);
2011 if (i < 0)
2012 return -ENOMEM;
2013 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2014 if (ret < 0)
2015 return ret;
2016
2017 /* Enable the entry */
2018 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2019 (1 << (31 - i)), TSU_TEN);
2020 }
2021
2022 /* Entry found or created, enable POST */
2023 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2024
2025 return 0;
2026 }
2027
2028 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2029 {
2030 struct sh_eth_private *mdp = netdev_priv(ndev);
2031 int i, ret;
2032
2033 if (!mdp->cd->tsu)
2034 return 0;
2035
2036 i = sh_eth_tsu_find_entry(ndev, addr);
2037 if (i) {
2038 /* Entry found */
2039 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2040 goto done;
2041
2042 /* Disable the entry if both ports was disabled */
2043 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2044 if (ret < 0)
2045 return ret;
2046 }
2047 done:
2048 return 0;
2049 }
2050
2051 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2052 {
2053 struct sh_eth_private *mdp = netdev_priv(ndev);
2054 int i, ret;
2055
2056 if (unlikely(!mdp->cd->tsu))
2057 return 0;
2058
2059 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2060 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2061 continue;
2062
2063 /* Disable the entry if both ports was disabled */
2064 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2065 if (ret < 0)
2066 return ret;
2067 }
2068
2069 return 0;
2070 }
2071
2072 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2073 {
2074 struct sh_eth_private *mdp = netdev_priv(ndev);
2075 u8 addr[ETH_ALEN];
2076 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2077 int i;
2078
2079 if (unlikely(!mdp->cd->tsu))
2080 return;
2081
2082 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2083 sh_eth_tsu_read_entry(reg_offset, addr);
2084 if (is_multicast_ether_addr(addr))
2085 sh_eth_tsu_del_entry(ndev, addr);
2086 }
2087 }
2088
2089 /* Multicast reception directions set */
2090 static void sh_eth_set_multicast_list(struct net_device *ndev)
2091 {
2092 struct sh_eth_private *mdp = netdev_priv(ndev);
2093 u32 ecmr_bits;
2094 int mcast_all = 0;
2095 unsigned long flags;
2096
2097 spin_lock_irqsave(&mdp->lock, flags);
2098 /*
2099 * Initial condition is MCT = 1, PRM = 0.
2100 * Depending on ndev->flags, set PRM or clear MCT
2101 */
2102 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2103
2104 if (!(ndev->flags & IFF_MULTICAST)) {
2105 sh_eth_tsu_purge_mcast(ndev);
2106 mcast_all = 1;
2107 }
2108 if (ndev->flags & IFF_ALLMULTI) {
2109 sh_eth_tsu_purge_mcast(ndev);
2110 ecmr_bits &= ~ECMR_MCT;
2111 mcast_all = 1;
2112 }
2113
2114 if (ndev->flags & IFF_PROMISC) {
2115 sh_eth_tsu_purge_all(ndev);
2116 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2117 } else if (mdp->cd->tsu) {
2118 struct netdev_hw_addr *ha;
2119 netdev_for_each_mc_addr(ha, ndev) {
2120 if (mcast_all && is_multicast_ether_addr(ha->addr))
2121 continue;
2122
2123 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2124 if (!mcast_all) {
2125 sh_eth_tsu_purge_mcast(ndev);
2126 ecmr_bits &= ~ECMR_MCT;
2127 mcast_all = 1;
2128 }
2129 }
2130 }
2131 } else {
2132 /* Normal, unicast/broadcast-only mode. */
2133 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2134 }
2135
2136 /* update the ethernet mode */
2137 sh_eth_write(ndev, ecmr_bits, ECMR);
2138
2139 spin_unlock_irqrestore(&mdp->lock, flags);
2140 }
2141
2142 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2143 {
2144 if (!mdp->port)
2145 return TSU_VTAG0;
2146 else
2147 return TSU_VTAG1;
2148 }
2149
2150 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
2151 {
2152 struct sh_eth_private *mdp = netdev_priv(ndev);
2153 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2154
2155 if (unlikely(!mdp->cd->tsu))
2156 return -EPERM;
2157
2158 /* No filtering if vid = 0 */
2159 if (!vid)
2160 return 0;
2161
2162 mdp->vlan_num_ids++;
2163
2164 /*
2165 * The controller has one VLAN tag HW filter. So, if the filter is
2166 * already enabled, the driver disables it and the filte
2167 */
2168 if (mdp->vlan_num_ids > 1) {
2169 /* disable VLAN filter */
2170 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2171 return 0;
2172 }
2173
2174 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2175 vtag_reg_index);
2176
2177 return 0;
2178 }
2179
2180 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
2181 {
2182 struct sh_eth_private *mdp = netdev_priv(ndev);
2183 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2184
2185 if (unlikely(!mdp->cd->tsu))
2186 return -EPERM;
2187
2188 /* No filtering if vid = 0 */
2189 if (!vid)
2190 return 0;
2191
2192 mdp->vlan_num_ids--;
2193 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2194
2195 return 0;
2196 }
2197 #endif /* SH_ETH_HAS_TSU */
2198
2199 /* SuperH's TSU register init function */
2200 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2201 {
2202 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2203 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2204 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2205 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2206 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2207 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2208 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2209 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2210 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2211 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2212 if (sh_eth_is_gether(mdp)) {
2213 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2214 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2215 } else {
2216 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2217 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2218 }
2219 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2220 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2221 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2222 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2223 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2224 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2225 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2226 }
2227
2228 /* MDIO bus release function */
2229 static int sh_mdio_release(struct net_device *ndev)
2230 {
2231 struct sh_eth_private *mdp = netdev_priv(ndev);
2232 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2233
2234 /* unregister mdio bus */
2235 mdiobus_unregister(bus);
2236
2237 /* remove mdio bus info from net_device */
2238 dev_set_drvdata(&ndev->dev, NULL);
2239
2240 /* free interrupts memory */
2241 kfree(bus->irq);
2242
2243 /* free bitbang info */
2244 free_mdio_bitbang(bus);
2245
2246 /* free bitbang memory */
2247 kfree(mdp->bitbang);
2248
2249 return 0;
2250 }
2251
2252 /* MDIO bus init function */
2253 static int sh_mdio_init(struct net_device *ndev, int id,
2254 struct sh_eth_plat_data *pd)
2255 {
2256 int ret, i;
2257 struct bb_info *bitbang;
2258 struct sh_eth_private *mdp = netdev_priv(ndev);
2259
2260 /* create bit control struct for PHY */
2261 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
2262 if (!bitbang) {
2263 ret = -ENOMEM;
2264 goto out;
2265 }
2266
2267 /* bitbang init */
2268 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2269 bitbang->set_gate = pd->set_mdio_gate;
2270 bitbang->mdi_msk = 0x08;
2271 bitbang->mdo_msk = 0x04;
2272 bitbang->mmd_msk = 0x02;/* MMD */
2273 bitbang->mdc_msk = 0x01;
2274 bitbang->ctrl.ops = &bb_ops;
2275
2276 /* MII controller setting */
2277 mdp->bitbang = bitbang;
2278 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2279 if (!mdp->mii_bus) {
2280 ret = -ENOMEM;
2281 goto out_free_bitbang;
2282 }
2283
2284 /* Hook up MII support for ethtool */
2285 mdp->mii_bus->name = "sh_mii";
2286 mdp->mii_bus->parent = &ndev->dev;
2287 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2288 mdp->pdev->name, id);
2289
2290 /* PHY IRQ */
2291 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
2292 if (!mdp->mii_bus->irq) {
2293 ret = -ENOMEM;
2294 goto out_free_bus;
2295 }
2296
2297 for (i = 0; i < PHY_MAX_ADDR; i++)
2298 mdp->mii_bus->irq[i] = PHY_POLL;
2299
2300 /* register mdio bus */
2301 ret = mdiobus_register(mdp->mii_bus);
2302 if (ret)
2303 goto out_free_irq;
2304
2305 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2306
2307 return 0;
2308
2309 out_free_irq:
2310 kfree(mdp->mii_bus->irq);
2311
2312 out_free_bus:
2313 free_mdio_bitbang(mdp->mii_bus);
2314
2315 out_free_bitbang:
2316 kfree(bitbang);
2317
2318 out:
2319 return ret;
2320 }
2321
2322 static const u16 *sh_eth_get_register_offset(int register_type)
2323 {
2324 const u16 *reg_offset = NULL;
2325
2326 switch (register_type) {
2327 case SH_ETH_REG_GIGABIT:
2328 reg_offset = sh_eth_offset_gigabit;
2329 break;
2330 case SH_ETH_REG_FAST_SH4:
2331 reg_offset = sh_eth_offset_fast_sh4;
2332 break;
2333 case SH_ETH_REG_FAST_SH3_SH2:
2334 reg_offset = sh_eth_offset_fast_sh3_sh2;
2335 break;
2336 default:
2337 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
2338 break;
2339 }
2340
2341 return reg_offset;
2342 }
2343
2344 static const struct net_device_ops sh_eth_netdev_ops = {
2345 .ndo_open = sh_eth_open,
2346 .ndo_stop = sh_eth_close,
2347 .ndo_start_xmit = sh_eth_start_xmit,
2348 .ndo_get_stats = sh_eth_get_stats,
2349 #if defined(SH_ETH_HAS_TSU)
2350 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2351 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2352 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2353 #endif
2354 .ndo_tx_timeout = sh_eth_tx_timeout,
2355 .ndo_do_ioctl = sh_eth_do_ioctl,
2356 .ndo_validate_addr = eth_validate_addr,
2357 .ndo_set_mac_address = eth_mac_addr,
2358 .ndo_change_mtu = eth_change_mtu,
2359 };
2360
2361 static int sh_eth_drv_probe(struct platform_device *pdev)
2362 {
2363 int ret, devno = 0;
2364 struct resource *res;
2365 struct net_device *ndev = NULL;
2366 struct sh_eth_private *mdp = NULL;
2367 struct sh_eth_plat_data *pd;
2368
2369 /* get base addr */
2370 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2371 if (unlikely(res == NULL)) {
2372 dev_err(&pdev->dev, "invalid resource\n");
2373 ret = -EINVAL;
2374 goto out;
2375 }
2376
2377 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2378 if (!ndev) {
2379 ret = -ENOMEM;
2380 goto out;
2381 }
2382
2383 /* The sh Ether-specific entries in the device structure. */
2384 ndev->base_addr = res->start;
2385 devno = pdev->id;
2386 if (devno < 0)
2387 devno = 0;
2388
2389 ndev->dma = -1;
2390 ret = platform_get_irq(pdev, 0);
2391 if (ret < 0) {
2392 ret = -ENODEV;
2393 goto out_release;
2394 }
2395 ndev->irq = ret;
2396
2397 SET_NETDEV_DEV(ndev, &pdev->dev);
2398
2399 /* Fill in the fields of the device structure with ethernet values. */
2400 ether_setup(ndev);
2401
2402 mdp = netdev_priv(ndev);
2403 mdp->num_tx_ring = TX_RING_SIZE;
2404 mdp->num_rx_ring = RX_RING_SIZE;
2405 mdp->addr = ioremap(res->start, resource_size(res));
2406 if (mdp->addr == NULL) {
2407 ret = -ENOMEM;
2408 dev_err(&pdev->dev, "ioremap failed.\n");
2409 goto out_release;
2410 }
2411
2412 spin_lock_init(&mdp->lock);
2413 mdp->pdev = pdev;
2414 pm_runtime_enable(&pdev->dev);
2415 pm_runtime_resume(&pdev->dev);
2416
2417 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
2418 /* get PHY ID */
2419 mdp->phy_id = pd->phy;
2420 mdp->phy_interface = pd->phy_interface;
2421 /* EDMAC endian */
2422 mdp->edmac_endian = pd->edmac_endian;
2423 mdp->no_ether_link = pd->no_ether_link;
2424 mdp->ether_link_active_low = pd->ether_link_active_low;
2425 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2426
2427 /* set cpu data */
2428 #if defined(SH_ETH_HAS_BOTH_MODULES)
2429 mdp->cd = sh_eth_get_cpu_data(mdp);
2430 #else
2431 mdp->cd = &sh_eth_my_cpu_data;
2432 #endif
2433 sh_eth_set_default_cpu_data(mdp->cd);
2434
2435 /* set function */
2436 ndev->netdev_ops = &sh_eth_netdev_ops;
2437 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2438 ndev->watchdog_timeo = TX_TIMEOUT;
2439
2440 /* debug message level */
2441 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2442
2443 /* read and set MAC address */
2444 read_mac_address(ndev, pd->mac_addr);
2445
2446 /* ioremap the TSU registers */
2447 if (mdp->cd->tsu) {
2448 struct resource *rtsu;
2449 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2450 if (!rtsu) {
2451 dev_err(&pdev->dev, "Not found TSU resource\n");
2452 ret = -ENODEV;
2453 goto out_release;
2454 }
2455 mdp->tsu_addr = ioremap(rtsu->start,
2456 resource_size(rtsu));
2457 if (mdp->tsu_addr == NULL) {
2458 ret = -ENOMEM;
2459 dev_err(&pdev->dev, "TSU ioremap failed.\n");
2460 goto out_release;
2461 }
2462 mdp->port = devno % 2;
2463 ndev->features = NETIF_F_HW_VLAN_FILTER;
2464 }
2465
2466 /* initialize first or needed device */
2467 if (!devno || pd->needs_init) {
2468 if (mdp->cd->chip_reset)
2469 mdp->cd->chip_reset(ndev);
2470
2471 if (mdp->cd->tsu) {
2472 /* TSU init (Init only)*/
2473 sh_eth_tsu_init(mdp);
2474 }
2475 }
2476
2477 /* network device register */
2478 ret = register_netdev(ndev);
2479 if (ret)
2480 goto out_release;
2481
2482 /* mdio bus init */
2483 ret = sh_mdio_init(ndev, pdev->id, pd);
2484 if (ret)
2485 goto out_unregister;
2486
2487 /* print device information */
2488 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2489 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2490
2491 platform_set_drvdata(pdev, ndev);
2492
2493 return ret;
2494
2495 out_unregister:
2496 unregister_netdev(ndev);
2497
2498 out_release:
2499 /* net_dev free */
2500 if (mdp && mdp->addr)
2501 iounmap(mdp->addr);
2502 if (mdp && mdp->tsu_addr)
2503 iounmap(mdp->tsu_addr);
2504 if (ndev)
2505 free_netdev(ndev);
2506
2507 out:
2508 return ret;
2509 }
2510
2511 static int sh_eth_drv_remove(struct platform_device *pdev)
2512 {
2513 struct net_device *ndev = platform_get_drvdata(pdev);
2514 struct sh_eth_private *mdp = netdev_priv(ndev);
2515
2516 if (mdp->cd->tsu)
2517 iounmap(mdp->tsu_addr);
2518 sh_mdio_release(ndev);
2519 unregister_netdev(ndev);
2520 pm_runtime_disable(&pdev->dev);
2521 iounmap(mdp->addr);
2522 free_netdev(ndev);
2523 platform_set_drvdata(pdev, NULL);
2524
2525 return 0;
2526 }
2527
2528 static int sh_eth_runtime_nop(struct device *dev)
2529 {
2530 /*
2531 * Runtime PM callback shared between ->runtime_suspend()
2532 * and ->runtime_resume(). Simply returns success.
2533 *
2534 * This driver re-initializes all registers after
2535 * pm_runtime_get_sync() anyway so there is no need
2536 * to save and restore registers here.
2537 */
2538 return 0;
2539 }
2540
2541 static struct dev_pm_ops sh_eth_dev_pm_ops = {
2542 .runtime_suspend = sh_eth_runtime_nop,
2543 .runtime_resume = sh_eth_runtime_nop,
2544 };
2545
2546 static struct platform_driver sh_eth_driver = {
2547 .probe = sh_eth_drv_probe,
2548 .remove = sh_eth_drv_remove,
2549 .driver = {
2550 .name = CARDNAME,
2551 .pm = &sh_eth_dev_pm_ops,
2552 },
2553 };
2554
2555 module_platform_driver(sh_eth_driver);
2556
2557 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2558 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2559 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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