1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
49 #define SH_ETH_DEF_MSG_ENABLE \
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
60 static const u16 sh_eth_offset_gigabit
[SH_ETH_MAX_REGISTER_OFFSET
] = {
61 SH_ETH_OFFSET_DEFAULTS
,
116 [TSU_CTRST
] = 0x0004,
117 [TSU_FWEN0
] = 0x0010,
118 [TSU_FWEN1
] = 0x0014,
120 [TSU_BSYSL0
] = 0x0020,
121 [TSU_BSYSL1
] = 0x0024,
122 [TSU_PRISL0
] = 0x0028,
123 [TSU_PRISL1
] = 0x002c,
124 [TSU_FWSL0
] = 0x0030,
125 [TSU_FWSL1
] = 0x0034,
126 [TSU_FWSLC
] = 0x0038,
127 [TSU_QTAG0
] = 0x0040,
128 [TSU_QTAG1
] = 0x0044,
130 [TSU_FWINMK
] = 0x0054,
131 [TSU_ADQT0
] = 0x0048,
132 [TSU_ADQT1
] = 0x004c,
133 [TSU_VTAG0
] = 0x0058,
134 [TSU_VTAG1
] = 0x005c,
135 [TSU_ADSBSY
] = 0x0060,
137 [TSU_POST1
] = 0x0070,
138 [TSU_POST2
] = 0x0074,
139 [TSU_POST3
] = 0x0078,
140 [TSU_POST4
] = 0x007c,
141 [TSU_ADRH0
] = 0x0100,
157 static const u16 sh_eth_offset_fast_rz
[SH_ETH_MAX_REGISTER_OFFSET
] = {
158 SH_ETH_OFFSET_DEFAULTS
,
203 [TSU_CTRST
] = 0x0004,
204 [TSU_VTAG0
] = 0x0058,
205 [TSU_ADSBSY
] = 0x0060,
207 [TSU_ADRH0
] = 0x0100,
215 static const u16 sh_eth_offset_fast_rcar
[SH_ETH_MAX_REGISTER_OFFSET
] = {
216 SH_ETH_OFFSET_DEFAULTS
,
263 static const u16 sh_eth_offset_fast_sh4
[SH_ETH_MAX_REGISTER_OFFSET
] = {
264 SH_ETH_OFFSET_DEFAULTS
,
317 static const u16 sh_eth_offset_fast_sh3_sh2
[SH_ETH_MAX_REGISTER_OFFSET
] = {
318 SH_ETH_OFFSET_DEFAULTS
,
366 [TSU_CTRST
] = 0x0004,
367 [TSU_FWEN0
] = 0x0010,
368 [TSU_FWEN1
] = 0x0014,
370 [TSU_BSYSL0
] = 0x0020,
371 [TSU_BSYSL1
] = 0x0024,
372 [TSU_PRISL0
] = 0x0028,
373 [TSU_PRISL1
] = 0x002c,
374 [TSU_FWSL0
] = 0x0030,
375 [TSU_FWSL1
] = 0x0034,
376 [TSU_FWSLC
] = 0x0038,
377 [TSU_QTAGM0
] = 0x0040,
378 [TSU_QTAGM1
] = 0x0044,
379 [TSU_ADQT0
] = 0x0048,
380 [TSU_ADQT1
] = 0x004c,
382 [TSU_FWINMK
] = 0x0054,
383 [TSU_ADSBSY
] = 0x0060,
385 [TSU_POST1
] = 0x0070,
386 [TSU_POST2
] = 0x0074,
387 [TSU_POST3
] = 0x0078,
388 [TSU_POST4
] = 0x007c,
403 [TSU_ADRH0
] = 0x0100,
406 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
);
407 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
);
409 static void sh_eth_write(struct net_device
*ndev
, u32 data
, int enum_index
)
411 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
412 u16 offset
= mdp
->reg_offset
[enum_index
];
414 if (WARN_ON(offset
== SH_ETH_OFFSET_INVALID
))
417 iowrite32(data
, mdp
->addr
+ offset
);
420 static u32
sh_eth_read(struct net_device
*ndev
, int enum_index
)
422 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
423 u16 offset
= mdp
->reg_offset
[enum_index
];
425 if (WARN_ON(offset
== SH_ETH_OFFSET_INVALID
))
428 return ioread32(mdp
->addr
+ offset
);
431 static void sh_eth_modify(struct net_device
*ndev
, int enum_index
, u32 clear
,
434 sh_eth_write(ndev
, (sh_eth_read(ndev
, enum_index
) & ~clear
) | set
,
438 static bool sh_eth_is_gether(struct sh_eth_private
*mdp
)
440 return mdp
->reg_offset
== sh_eth_offset_gigabit
;
443 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private
*mdp
)
445 return mdp
->reg_offset
== sh_eth_offset_fast_rz
;
448 static void sh_eth_select_mii(struct net_device
*ndev
)
451 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
453 switch (mdp
->phy_interface
) {
454 case PHY_INTERFACE_MODE_GMII
:
457 case PHY_INTERFACE_MODE_MII
:
460 case PHY_INTERFACE_MODE_RMII
:
465 "PHY interface mode was not setup. Set to MII.\n");
470 sh_eth_write(ndev
, value
, RMII_MII
);
473 static void sh_eth_set_duplex(struct net_device
*ndev
)
475 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
477 sh_eth_modify(ndev
, ECMR
, ECMR_DM
, mdp
->duplex
? ECMR_DM
: 0);
480 static void sh_eth_chip_reset(struct net_device
*ndev
)
482 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
485 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
489 static void sh_eth_set_rate_gether(struct net_device
*ndev
)
491 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
493 switch (mdp
->speed
) {
494 case 10: /* 10BASE */
495 sh_eth_write(ndev
, GECMR_10
, GECMR
);
497 case 100:/* 100BASE */
498 sh_eth_write(ndev
, GECMR_100
, GECMR
);
500 case 1000: /* 1000BASE */
501 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
508 static struct sh_eth_cpu_data r7s72100_data
= {
509 .chip_reset
= sh_eth_chip_reset
,
510 .set_duplex
= sh_eth_set_duplex
,
512 .register_type
= SH_ETH_REG_FAST_RZ
,
514 .ecsr_value
= ECSR_ICD
,
515 .ecsipr_value
= ECSIPR_ICDIP
,
516 .eesipr_value
= 0xff7f009f,
518 .tx_check
= EESR_TC1
| EESR_FTC
,
519 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
520 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
522 .fdr_value
= 0x0000070f,
530 .rpadir_value
= 2 << 16,
538 static void sh_eth_chip_reset_r8a7740(struct net_device
*ndev
)
540 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
543 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
546 sh_eth_select_mii(ndev
);
550 static struct sh_eth_cpu_data r8a7740_data
= {
551 .chip_reset
= sh_eth_chip_reset_r8a7740
,
552 .set_duplex
= sh_eth_set_duplex
,
553 .set_rate
= sh_eth_set_rate_gether
,
555 .register_type
= SH_ETH_REG_GIGABIT
,
557 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
558 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
559 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
561 .tx_check
= EESR_TC1
| EESR_FTC
,
562 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
563 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
565 .fdr_value
= 0x0000070f,
573 .rpadir_value
= 2 << 16,
581 /* There is CPU dependent code */
582 static void sh_eth_set_rate_r8a777x(struct net_device
*ndev
)
584 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
586 switch (mdp
->speed
) {
587 case 10: /* 10BASE */
588 sh_eth_modify(ndev
, ECMR
, ECMR_ELB
, 0);
590 case 100:/* 100BASE */
591 sh_eth_modify(ndev
, ECMR
, ECMR_ELB
, ECMR_ELB
);
597 static struct sh_eth_cpu_data r8a777x_data
= {
598 .set_duplex
= sh_eth_set_duplex
,
599 .set_rate
= sh_eth_set_rate_r8a777x
,
601 .register_type
= SH_ETH_REG_FAST_RCAR
,
603 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
604 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
605 .eesipr_value
= 0x01ff009f,
607 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
608 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
609 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
|
611 .fdr_value
= 0x00000f0f,
620 static struct sh_eth_cpu_data r8a779x_data
= {
621 .set_duplex
= sh_eth_set_duplex
,
622 .set_rate
= sh_eth_set_rate_r8a777x
,
624 .register_type
= SH_ETH_REG_FAST_RCAR
,
626 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
627 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
628 .eesipr_value
= 0x01ff009f,
630 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
631 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
632 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
|
634 .fdr_value
= 0x00000f0f,
636 .trscer_err_mask
= DESC_I_RINT8
,
644 #endif /* CONFIG_OF */
646 static void sh_eth_set_rate_sh7724(struct net_device
*ndev
)
648 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
650 switch (mdp
->speed
) {
651 case 10: /* 10BASE */
652 sh_eth_modify(ndev
, ECMR
, ECMR_RTM
, 0);
654 case 100:/* 100BASE */
655 sh_eth_modify(ndev
, ECMR
, ECMR_RTM
, ECMR_RTM
);
661 static struct sh_eth_cpu_data sh7724_data
= {
662 .set_duplex
= sh_eth_set_duplex
,
663 .set_rate
= sh_eth_set_rate_sh7724
,
665 .register_type
= SH_ETH_REG_FAST_SH4
,
667 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
668 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
669 .eesipr_value
= 0x01ff009f,
671 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
672 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
673 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
|
681 .rpadir_value
= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
684 static void sh_eth_set_rate_sh7757(struct net_device
*ndev
)
686 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
688 switch (mdp
->speed
) {
689 case 10: /* 10BASE */
690 sh_eth_write(ndev
, 0, RTRATE
);
692 case 100:/* 100BASE */
693 sh_eth_write(ndev
, 1, RTRATE
);
699 static struct sh_eth_cpu_data sh7757_data
= {
700 .set_duplex
= sh_eth_set_duplex
,
701 .set_rate
= sh_eth_set_rate_sh7757
,
703 .register_type
= SH_ETH_REG_FAST_SH4
,
705 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
707 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
708 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
709 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
|
712 .irq_flags
= IRQF_SHARED
,
719 .rpadir_value
= 2 << 16,
723 #define SH_GIGA_ETH_BASE 0xfee00000UL
724 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
725 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
726 static void sh_eth_chip_reset_giga(struct net_device
*ndev
)
729 u32 mahr
[2], malr
[2];
731 /* save MAHR and MALR */
732 for (i
= 0; i
< 2; i
++) {
733 malr
[i
] = ioread32((void *)GIGA_MALR(i
));
734 mahr
[i
] = ioread32((void *)GIGA_MAHR(i
));
738 iowrite32(ARSTR_ARSTR
, (void *)(SH_GIGA_ETH_BASE
+ 0x1800));
741 /* restore MAHR and MALR */
742 for (i
= 0; i
< 2; i
++) {
743 iowrite32(malr
[i
], (void *)GIGA_MALR(i
));
744 iowrite32(mahr
[i
], (void *)GIGA_MAHR(i
));
748 static void sh_eth_set_rate_giga(struct net_device
*ndev
)
750 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
752 switch (mdp
->speed
) {
753 case 10: /* 10BASE */
754 sh_eth_write(ndev
, 0x00000000, GECMR
);
756 case 100:/* 100BASE */
757 sh_eth_write(ndev
, 0x00000010, GECMR
);
759 case 1000: /* 1000BASE */
760 sh_eth_write(ndev
, 0x00000020, GECMR
);
765 /* SH7757(GETHERC) */
766 static struct sh_eth_cpu_data sh7757_data_giga
= {
767 .chip_reset
= sh_eth_chip_reset_giga
,
768 .set_duplex
= sh_eth_set_duplex
,
769 .set_rate
= sh_eth_set_rate_giga
,
771 .register_type
= SH_ETH_REG_GIGABIT
,
773 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
774 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
775 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
777 .tx_check
= EESR_TC1
| EESR_FTC
,
778 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
779 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
781 .fdr_value
= 0x0000072f,
783 .irq_flags
= IRQF_SHARED
,
790 .rpadir_value
= 2 << 16,
797 static struct sh_eth_cpu_data sh7734_data
= {
798 .chip_reset
= sh_eth_chip_reset
,
799 .set_duplex
= sh_eth_set_duplex
,
800 .set_rate
= sh_eth_set_rate_gether
,
802 .register_type
= SH_ETH_REG_GIGABIT
,
804 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
805 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
806 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
808 .tx_check
= EESR_TC1
| EESR_FTC
,
809 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
810 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
826 static struct sh_eth_cpu_data sh7763_data
= {
827 .chip_reset
= sh_eth_chip_reset
,
828 .set_duplex
= sh_eth_set_duplex
,
829 .set_rate
= sh_eth_set_rate_gether
,
831 .register_type
= SH_ETH_REG_GIGABIT
,
833 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
834 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
835 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
837 .tx_check
= EESR_TC1
| EESR_FTC
,
838 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
839 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
|
850 .irq_flags
= IRQF_SHARED
,
853 static struct sh_eth_cpu_data sh7619_data
= {
854 .register_type
= SH_ETH_REG_FAST_SH3_SH2
,
856 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
864 static struct sh_eth_cpu_data sh771x_data
= {
865 .register_type
= SH_ETH_REG_FAST_SH3_SH2
,
867 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
871 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data
*cd
)
874 cd
->ecsr_value
= DEFAULT_ECSR_INIT
;
876 if (!cd
->ecsipr_value
)
877 cd
->ecsipr_value
= DEFAULT_ECSIPR_INIT
;
879 if (!cd
->fcftr_value
)
880 cd
->fcftr_value
= DEFAULT_FIFO_F_D_RFF
|
881 DEFAULT_FIFO_F_D_RFD
;
884 cd
->fdr_value
= DEFAULT_FDR_INIT
;
887 cd
->tx_check
= DEFAULT_TX_CHECK
;
889 if (!cd
->eesr_err_check
)
890 cd
->eesr_err_check
= DEFAULT_EESR_ERR_CHECK
;
892 if (!cd
->trscer_err_mask
)
893 cd
->trscer_err_mask
= DEFAULT_TRSCER_ERR_MASK
;
896 static int sh_eth_check_reset(struct net_device
*ndev
)
902 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
908 netdev_err(ndev
, "Device reset failed\n");
914 static int sh_eth_reset(struct net_device
*ndev
)
916 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
919 if (sh_eth_is_gether(mdp
) || sh_eth_is_rz_fast_ether(mdp
)) {
920 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
921 sh_eth_modify(ndev
, EDMR
, EDMR_SRST_GETHER
, EDMR_SRST_GETHER
);
923 ret
= sh_eth_check_reset(ndev
);
928 sh_eth_write(ndev
, 0x0, TDLAR
);
929 sh_eth_write(ndev
, 0x0, TDFAR
);
930 sh_eth_write(ndev
, 0x0, TDFXR
);
931 sh_eth_write(ndev
, 0x0, TDFFR
);
932 sh_eth_write(ndev
, 0x0, RDLAR
);
933 sh_eth_write(ndev
, 0x0, RDFAR
);
934 sh_eth_write(ndev
, 0x0, RDFXR
);
935 sh_eth_write(ndev
, 0x0, RDFFR
);
937 /* Reset HW CRC register */
939 sh_eth_write(ndev
, 0x0, CSMR
);
941 /* Select MII mode */
942 if (mdp
->cd
->select_mii
)
943 sh_eth_select_mii(ndev
);
945 sh_eth_modify(ndev
, EDMR
, EDMR_SRST_ETHER
, EDMR_SRST_ETHER
);
947 sh_eth_modify(ndev
, EDMR
, EDMR_SRST_ETHER
, 0);
953 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
955 uintptr_t reserve
= (uintptr_t)skb
->data
& (SH_ETH_RX_ALIGN
- 1);
958 skb_reserve(skb
, SH_ETH_RX_ALIGN
- reserve
);
961 /* Program the hardware MAC address from dev->dev_addr. */
962 static void update_mac_address(struct net_device
*ndev
)
965 (ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
966 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]), MAHR
);
968 (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]), MALR
);
971 /* Get MAC address from SuperH MAC address register
973 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
974 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
975 * When you want use this device, you must set MAC address in bootloader.
978 static void read_mac_address(struct net_device
*ndev
, unsigned char *mac
)
980 if (mac
[0] || mac
[1] || mac
[2] || mac
[3] || mac
[4] || mac
[5]) {
981 memcpy(ndev
->dev_addr
, mac
, ETH_ALEN
);
983 u32 mahr
= sh_eth_read(ndev
, MAHR
);
984 u32 malr
= sh_eth_read(ndev
, MALR
);
986 ndev
->dev_addr
[0] = (mahr
>> 24) & 0xFF;
987 ndev
->dev_addr
[1] = (mahr
>> 16) & 0xFF;
988 ndev
->dev_addr
[2] = (mahr
>> 8) & 0xFF;
989 ndev
->dev_addr
[3] = (mahr
>> 0) & 0xFF;
990 ndev
->dev_addr
[4] = (malr
>> 8) & 0xFF;
991 ndev
->dev_addr
[5] = (malr
>> 0) & 0xFF;
995 static u32
sh_eth_get_edtrr_trns(struct sh_eth_private
*mdp
)
997 if (sh_eth_is_gether(mdp
) || sh_eth_is_rz_fast_ether(mdp
))
998 return EDTRR_TRNS_GETHER
;
1000 return EDTRR_TRNS_ETHER
;
1004 void (*set_gate
)(void *addr
);
1005 struct mdiobb_ctrl ctrl
;
1009 static void sh_mdio_ctrl(struct mdiobb_ctrl
*ctrl
, u32 mask
, int set
)
1011 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1014 if (bitbang
->set_gate
)
1015 bitbang
->set_gate(bitbang
->addr
);
1017 pir
= ioread32(bitbang
->addr
);
1022 iowrite32(pir
, bitbang
->addr
);
1025 /* Data I/O pin control */
1026 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
1028 sh_mdio_ctrl(ctrl
, PIR_MMD
, bit
);
1032 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
1034 sh_mdio_ctrl(ctrl
, PIR_MDO
, bit
);
1038 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
1040 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1042 if (bitbang
->set_gate
)
1043 bitbang
->set_gate(bitbang
->addr
);
1045 return (ioread32(bitbang
->addr
) & PIR_MDI
) != 0;
1048 /* MDC pin control */
1049 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
1051 sh_mdio_ctrl(ctrl
, PIR_MDC
, bit
);
1054 /* mdio bus control struct */
1055 static struct mdiobb_ops bb_ops
= {
1056 .owner
= THIS_MODULE
,
1057 .set_mdc
= sh_mdc_ctrl
,
1058 .set_mdio_dir
= sh_mmd_ctrl
,
1059 .set_mdio_data
= sh_set_mdio
,
1060 .get_mdio_data
= sh_get_mdio
,
1063 /* free skb and descriptor buffer */
1064 static void sh_eth_ring_free(struct net_device
*ndev
)
1066 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1069 /* Free Rx skb ringbuffer */
1070 if (mdp
->rx_skbuff
) {
1071 for (i
= 0; i
< mdp
->num_rx_ring
; i
++)
1072 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
1074 kfree(mdp
->rx_skbuff
);
1075 mdp
->rx_skbuff
= NULL
;
1077 /* Free Tx skb ringbuffer */
1078 if (mdp
->tx_skbuff
) {
1079 for (i
= 0; i
< mdp
->num_tx_ring
; i
++)
1080 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
1082 kfree(mdp
->tx_skbuff
);
1083 mdp
->tx_skbuff
= NULL
;
1086 ringsize
= sizeof(struct sh_eth_rxdesc
) * mdp
->num_rx_ring
;
1087 dma_free_coherent(NULL
, ringsize
, mdp
->rx_ring
,
1089 mdp
->rx_ring
= NULL
;
1093 ringsize
= sizeof(struct sh_eth_txdesc
) * mdp
->num_tx_ring
;
1094 dma_free_coherent(NULL
, ringsize
, mdp
->tx_ring
,
1096 mdp
->tx_ring
= NULL
;
1100 /* format skb and descriptor buffer */
1101 static void sh_eth_ring_format(struct net_device
*ndev
)
1103 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1105 struct sk_buff
*skb
;
1106 struct sh_eth_rxdesc
*rxdesc
= NULL
;
1107 struct sh_eth_txdesc
*txdesc
= NULL
;
1108 int rx_ringsize
= sizeof(*rxdesc
) * mdp
->num_rx_ring
;
1109 int tx_ringsize
= sizeof(*txdesc
) * mdp
->num_tx_ring
;
1110 int skbuff_size
= mdp
->rx_buf_sz
+ SH_ETH_RX_ALIGN
+ 32 - 1;
1111 dma_addr_t dma_addr
;
1119 memset(mdp
->rx_ring
, 0, rx_ringsize
);
1121 /* build Rx ring buffer */
1122 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
1124 mdp
->rx_skbuff
[i
] = NULL
;
1125 skb
= netdev_alloc_skb(ndev
, skbuff_size
);
1128 sh_eth_set_receive_align(skb
);
1131 rxdesc
= &mdp
->rx_ring
[i
];
1132 /* The size of the buffer is a multiple of 32 bytes. */
1133 buf_len
= ALIGN(mdp
->rx_buf_sz
, 32);
1134 rxdesc
->len
= cpu_to_le32(buf_len
<< 16);
1135 dma_addr
= dma_map_single(&ndev
->dev
, skb
->data
, buf_len
,
1137 if (dma_mapping_error(&ndev
->dev
, dma_addr
)) {
1141 mdp
->rx_skbuff
[i
] = skb
;
1142 rxdesc
->addr
= cpu_to_le32(dma_addr
);
1143 rxdesc
->status
= cpu_to_le32(RD_RACT
| RD_RFP
);
1145 /* Rx descriptor address set */
1147 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDLAR
);
1148 if (sh_eth_is_gether(mdp
) ||
1149 sh_eth_is_rz_fast_ether(mdp
))
1150 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDFAR
);
1154 mdp
->dirty_rx
= (u32
) (i
- mdp
->num_rx_ring
);
1156 /* Mark the last entry as wrapping the ring. */
1158 rxdesc
->status
|= cpu_to_le32(RD_RDLE
);
1160 memset(mdp
->tx_ring
, 0, tx_ringsize
);
1162 /* build Tx ring buffer */
1163 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
1164 mdp
->tx_skbuff
[i
] = NULL
;
1165 txdesc
= &mdp
->tx_ring
[i
];
1166 txdesc
->status
= cpu_to_le32(TD_TFP
);
1167 txdesc
->len
= cpu_to_le32(0);
1169 /* Tx descriptor address set */
1170 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDLAR
);
1171 if (sh_eth_is_gether(mdp
) ||
1172 sh_eth_is_rz_fast_ether(mdp
))
1173 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDFAR
);
1177 txdesc
->status
|= cpu_to_le32(TD_TDLE
);
1180 /* Get skb and descriptor buffer */
1181 static int sh_eth_ring_init(struct net_device
*ndev
)
1183 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1184 int rx_ringsize
, tx_ringsize
;
1186 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1187 * card needs room to do 8 byte alignment, +2 so we can reserve
1188 * the first 2 bytes, and +16 gets room for the status word from the
1191 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
1192 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
1193 if (mdp
->cd
->rpadir
)
1194 mdp
->rx_buf_sz
+= NET_IP_ALIGN
;
1196 /* Allocate RX and TX skb rings */
1197 mdp
->rx_skbuff
= kcalloc(mdp
->num_rx_ring
, sizeof(*mdp
->rx_skbuff
),
1199 if (!mdp
->rx_skbuff
)
1202 mdp
->tx_skbuff
= kcalloc(mdp
->num_tx_ring
, sizeof(*mdp
->tx_skbuff
),
1204 if (!mdp
->tx_skbuff
)
1207 /* Allocate all Rx descriptors. */
1208 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * mdp
->num_rx_ring
;
1209 mdp
->rx_ring
= dma_alloc_coherent(NULL
, rx_ringsize
, &mdp
->rx_desc_dma
,
1216 /* Allocate all Tx descriptors. */
1217 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * mdp
->num_tx_ring
;
1218 mdp
->tx_ring
= dma_alloc_coherent(NULL
, tx_ringsize
, &mdp
->tx_desc_dma
,
1225 /* Free Rx and Tx skb ring buffer and DMA buffer */
1226 sh_eth_ring_free(ndev
);
1231 static int sh_eth_dev_init(struct net_device
*ndev
, bool start
)
1234 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1237 ret
= sh_eth_reset(ndev
);
1241 if (mdp
->cd
->rmiimode
)
1242 sh_eth_write(ndev
, 0x1, RMIIMODE
);
1244 /* Descriptor format */
1245 sh_eth_ring_format(ndev
);
1246 if (mdp
->cd
->rpadir
)
1247 sh_eth_write(ndev
, mdp
->cd
->rpadir_value
, RPADIR
);
1249 /* all sh_eth int mask */
1250 sh_eth_write(ndev
, 0, EESIPR
);
1252 #if defined(__LITTLE_ENDIAN)
1253 if (mdp
->cd
->hw_swap
)
1254 sh_eth_write(ndev
, EDMR_EL
, EDMR
);
1257 sh_eth_write(ndev
, 0, EDMR
);
1260 sh_eth_write(ndev
, mdp
->cd
->fdr_value
, FDR
);
1261 sh_eth_write(ndev
, 0, TFTR
);
1263 /* Frame recv control (enable multiple-packets per rx irq) */
1264 sh_eth_write(ndev
, RMCR_RNC
, RMCR
);
1266 sh_eth_write(ndev
, mdp
->cd
->trscer_err_mask
, TRSCER
);
1269 sh_eth_write(ndev
, 0x800, BCULR
); /* Burst sycle set */
1271 sh_eth_write(ndev
, mdp
->cd
->fcftr_value
, FCFTR
);
1273 if (!mdp
->cd
->no_trimd
)
1274 sh_eth_write(ndev
, 0, TRIMD
);
1276 /* Recv frame limit set register */
1277 sh_eth_write(ndev
, ndev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
+ ETH_FCS_LEN
,
1280 sh_eth_modify(ndev
, EESR
, 0, 0);
1282 mdp
->irq_enabled
= true;
1283 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1286 /* PAUSE Prohibition */
1287 sh_eth_write(ndev
, ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) |
1288 ECMR_TE
| ECMR_RE
, ECMR
);
1290 if (mdp
->cd
->set_rate
)
1291 mdp
->cd
->set_rate(ndev
);
1293 /* E-MAC Status Register clear */
1294 sh_eth_write(ndev
, mdp
->cd
->ecsr_value
, ECSR
);
1296 /* E-MAC Interrupt Enable register */
1298 sh_eth_write(ndev
, mdp
->cd
->ecsipr_value
, ECSIPR
);
1300 /* Set MAC address */
1301 update_mac_address(ndev
);
1305 sh_eth_write(ndev
, APR_AP
, APR
);
1307 sh_eth_write(ndev
, MPR_MP
, MPR
);
1308 if (mdp
->cd
->tpauser
)
1309 sh_eth_write(ndev
, TPAUSER_UNLIMITED
, TPAUSER
);
1312 /* Setting the Rx mode will start the Rx process. */
1313 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1315 netif_start_queue(ndev
);
1321 static void sh_eth_dev_exit(struct net_device
*ndev
)
1323 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1326 /* Deactivate all TX descriptors, so DMA should stop at next
1327 * packet boundary if it's currently running
1329 for (i
= 0; i
< mdp
->num_tx_ring
; i
++)
1330 mdp
->tx_ring
[i
].status
&= ~cpu_to_le32(TD_TACT
);
1332 /* Disable TX FIFO egress to MAC */
1333 sh_eth_rcv_snd_disable(ndev
);
1335 /* Stop RX DMA at next packet boundary */
1336 sh_eth_write(ndev
, 0, EDRRR
);
1338 /* Aside from TX DMA, we can't tell when the hardware is
1339 * really stopped, so we need to reset to make sure.
1340 * Before doing that, wait for long enough to *probably*
1341 * finish transmitting the last packet and poll stats.
1343 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1344 sh_eth_get_stats(ndev
);
1347 /* Set MAC address again */
1348 update_mac_address(ndev
);
1351 /* free Tx skb function */
1352 static int sh_eth_txfree(struct net_device
*ndev
)
1354 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1355 struct sh_eth_txdesc
*txdesc
;
1359 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
1360 entry
= mdp
->dirty_tx
% mdp
->num_tx_ring
;
1361 txdesc
= &mdp
->tx_ring
[entry
];
1362 if (txdesc
->status
& cpu_to_le32(TD_TACT
))
1364 /* TACT bit must be checked before all the following reads */
1366 netif_info(mdp
, tx_done
, ndev
,
1367 "tx entry %d status 0x%08x\n",
1368 entry
, le32_to_cpu(txdesc
->status
));
1369 /* Free the original skb. */
1370 if (mdp
->tx_skbuff
[entry
]) {
1371 dma_unmap_single(&ndev
->dev
, le32_to_cpu(txdesc
->addr
),
1372 le32_to_cpu(txdesc
->len
) >> 16,
1374 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
1375 mdp
->tx_skbuff
[entry
] = NULL
;
1378 txdesc
->status
= cpu_to_le32(TD_TFP
);
1379 if (entry
>= mdp
->num_tx_ring
- 1)
1380 txdesc
->status
|= cpu_to_le32(TD_TDLE
);
1382 ndev
->stats
.tx_packets
++;
1383 ndev
->stats
.tx_bytes
+= le32_to_cpu(txdesc
->len
) >> 16;
1388 /* Packet receive function */
1389 static int sh_eth_rx(struct net_device
*ndev
, u32 intr_status
, int *quota
)
1391 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1392 struct sh_eth_rxdesc
*rxdesc
;
1394 int entry
= mdp
->cur_rx
% mdp
->num_rx_ring
;
1395 int boguscnt
= (mdp
->dirty_rx
+ mdp
->num_rx_ring
) - mdp
->cur_rx
;
1397 struct sk_buff
*skb
;
1400 int skbuff_size
= mdp
->rx_buf_sz
+ SH_ETH_RX_ALIGN
+ 32 - 1;
1401 dma_addr_t dma_addr
;
1404 boguscnt
= min(boguscnt
, *quota
);
1406 rxdesc
= &mdp
->rx_ring
[entry
];
1407 while (!(rxdesc
->status
& cpu_to_le32(RD_RACT
))) {
1408 /* RACT bit must be checked before all the following reads */
1410 desc_status
= le32_to_cpu(rxdesc
->status
);
1411 pkt_len
= le32_to_cpu(rxdesc
->len
) & RD_RFL
;
1416 netif_info(mdp
, rx_status
, ndev
,
1417 "rx entry %d status 0x%08x len %d\n",
1418 entry
, desc_status
, pkt_len
);
1420 if (!(desc_status
& RDFEND
))
1421 ndev
->stats
.rx_length_errors
++;
1423 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1424 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1425 * bit 0. However, in case of the R8A7740 and R7S72100
1426 * the RFS bits are from bit 25 to bit 16. So, the
1427 * driver needs right shifting by 16.
1429 if (mdp
->cd
->shift_rd0
)
1432 skb
= mdp
->rx_skbuff
[entry
];
1433 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
1434 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
1435 ndev
->stats
.rx_errors
++;
1436 if (desc_status
& RD_RFS1
)
1437 ndev
->stats
.rx_crc_errors
++;
1438 if (desc_status
& RD_RFS2
)
1439 ndev
->stats
.rx_frame_errors
++;
1440 if (desc_status
& RD_RFS3
)
1441 ndev
->stats
.rx_length_errors
++;
1442 if (desc_status
& RD_RFS4
)
1443 ndev
->stats
.rx_length_errors
++;
1444 if (desc_status
& RD_RFS6
)
1445 ndev
->stats
.rx_missed_errors
++;
1446 if (desc_status
& RD_RFS10
)
1447 ndev
->stats
.rx_over_errors
++;
1449 dma_addr
= le32_to_cpu(rxdesc
->addr
);
1450 if (!mdp
->cd
->hw_swap
)
1452 phys_to_virt(ALIGN(dma_addr
, 4)),
1454 mdp
->rx_skbuff
[entry
] = NULL
;
1455 if (mdp
->cd
->rpadir
)
1456 skb_reserve(skb
, NET_IP_ALIGN
);
1457 dma_unmap_single(&ndev
->dev
, dma_addr
,
1458 ALIGN(mdp
->rx_buf_sz
, 32),
1460 skb_put(skb
, pkt_len
);
1461 skb
->protocol
= eth_type_trans(skb
, ndev
);
1462 netif_receive_skb(skb
);
1463 ndev
->stats
.rx_packets
++;
1464 ndev
->stats
.rx_bytes
+= pkt_len
;
1465 if (desc_status
& RD_RFS8
)
1466 ndev
->stats
.multicast
++;
1468 entry
= (++mdp
->cur_rx
) % mdp
->num_rx_ring
;
1469 rxdesc
= &mdp
->rx_ring
[entry
];
1472 /* Refill the Rx ring buffers. */
1473 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
1474 entry
= mdp
->dirty_rx
% mdp
->num_rx_ring
;
1475 rxdesc
= &mdp
->rx_ring
[entry
];
1476 /* The size of the buffer is 32 byte boundary. */
1477 buf_len
= ALIGN(mdp
->rx_buf_sz
, 32);
1478 rxdesc
->len
= cpu_to_le32(buf_len
<< 16);
1480 if (mdp
->rx_skbuff
[entry
] == NULL
) {
1481 skb
= netdev_alloc_skb(ndev
, skbuff_size
);
1483 break; /* Better luck next round. */
1484 sh_eth_set_receive_align(skb
);
1485 dma_addr
= dma_map_single(&ndev
->dev
, skb
->data
,
1486 buf_len
, DMA_FROM_DEVICE
);
1487 if (dma_mapping_error(&ndev
->dev
, dma_addr
)) {
1491 mdp
->rx_skbuff
[entry
] = skb
;
1493 skb_checksum_none_assert(skb
);
1494 rxdesc
->addr
= cpu_to_le32(dma_addr
);
1496 dma_wmb(); /* RACT bit must be set after all the above writes */
1497 if (entry
>= mdp
->num_rx_ring
- 1)
1499 cpu_to_le32(RD_RACT
| RD_RFP
| RD_RDLE
);
1501 rxdesc
->status
|= cpu_to_le32(RD_RACT
| RD_RFP
);
1504 /* Restart Rx engine if stopped. */
1505 /* If we don't need to check status, don't. -KDU */
1506 if (!(sh_eth_read(ndev
, EDRRR
) & EDRRR_R
)) {
1507 /* fix the values for the next receiving if RDE is set */
1508 if (intr_status
& EESR_RDE
&&
1509 mdp
->reg_offset
[RDFAR
] != SH_ETH_OFFSET_INVALID
) {
1510 u32 count
= (sh_eth_read(ndev
, RDFAR
) -
1511 sh_eth_read(ndev
, RDLAR
)) >> 4;
1513 mdp
->cur_rx
= count
;
1514 mdp
->dirty_rx
= count
;
1516 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1519 *quota
-= limit
- boguscnt
- 1;
1524 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
)
1526 /* disable tx and rx */
1527 sh_eth_modify(ndev
, ECMR
, ECMR_RE
| ECMR_TE
, 0);
1530 static void sh_eth_rcv_snd_enable(struct net_device
*ndev
)
1532 /* enable tx and rx */
1533 sh_eth_modify(ndev
, ECMR
, ECMR_RE
| ECMR_TE
, ECMR_RE
| ECMR_TE
);
1536 /* error control function */
1537 static void sh_eth_error(struct net_device
*ndev
, u32 intr_status
)
1539 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1544 if (intr_status
& EESR_ECI
) {
1545 felic_stat
= sh_eth_read(ndev
, ECSR
);
1546 sh_eth_write(ndev
, felic_stat
, ECSR
); /* clear int */
1547 if (felic_stat
& ECSR_ICD
)
1548 ndev
->stats
.tx_carrier_errors
++;
1549 if (felic_stat
& ECSR_LCHNG
) {
1551 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
) {
1554 link_stat
= (sh_eth_read(ndev
, PSR
));
1555 if (mdp
->ether_link_active_low
)
1556 link_stat
= ~link_stat
;
1558 if (!(link_stat
& PHY_ST_LINK
)) {
1559 sh_eth_rcv_snd_disable(ndev
);
1562 sh_eth_modify(ndev
, EESIPR
, DMAC_M_ECI
, 0);
1564 sh_eth_modify(ndev
, ECSR
, 0, 0);
1565 sh_eth_modify(ndev
, EESIPR
, DMAC_M_ECI
,
1567 /* enable tx and rx */
1568 sh_eth_rcv_snd_enable(ndev
);
1574 if (intr_status
& EESR_TWB
) {
1575 /* Unused write back interrupt */
1576 if (intr_status
& EESR_TABT
) { /* Transmit Abort int */
1577 ndev
->stats
.tx_aborted_errors
++;
1578 netif_err(mdp
, tx_err
, ndev
, "Transmit Abort\n");
1582 if (intr_status
& EESR_RABT
) {
1583 /* Receive Abort int */
1584 if (intr_status
& EESR_RFRMER
) {
1585 /* Receive Frame Overflow int */
1586 ndev
->stats
.rx_frame_errors
++;
1590 if (intr_status
& EESR_TDE
) {
1591 /* Transmit Descriptor Empty int */
1592 ndev
->stats
.tx_fifo_errors
++;
1593 netif_err(mdp
, tx_err
, ndev
, "Transmit Descriptor Empty\n");
1596 if (intr_status
& EESR_TFE
) {
1597 /* FIFO under flow */
1598 ndev
->stats
.tx_fifo_errors
++;
1599 netif_err(mdp
, tx_err
, ndev
, "Transmit FIFO Under flow\n");
1602 if (intr_status
& EESR_RDE
) {
1603 /* Receive Descriptor Empty int */
1604 ndev
->stats
.rx_over_errors
++;
1607 if (intr_status
& EESR_RFE
) {
1608 /* Receive FIFO Overflow int */
1609 ndev
->stats
.rx_fifo_errors
++;
1612 if (!mdp
->cd
->no_ade
&& (intr_status
& EESR_ADE
)) {
1614 ndev
->stats
.tx_fifo_errors
++;
1615 netif_err(mdp
, tx_err
, ndev
, "Address Error\n");
1618 mask
= EESR_TWB
| EESR_TABT
| EESR_ADE
| EESR_TDE
| EESR_TFE
;
1619 if (mdp
->cd
->no_ade
)
1621 if (intr_status
& mask
) {
1623 u32 edtrr
= sh_eth_read(ndev
, EDTRR
);
1626 netdev_err(ndev
, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1627 intr_status
, mdp
->cur_tx
, mdp
->dirty_tx
,
1628 (u32
)ndev
->state
, edtrr
);
1629 /* dirty buffer free */
1630 sh_eth_txfree(ndev
);
1633 if (edtrr
^ sh_eth_get_edtrr_trns(mdp
)) {
1635 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1638 netif_wake_queue(ndev
);
1642 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
1644 struct net_device
*ndev
= netdev
;
1645 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1646 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
1647 irqreturn_t ret
= IRQ_NONE
;
1648 u32 intr_status
, intr_enable
;
1650 spin_lock(&mdp
->lock
);
1652 /* Get interrupt status */
1653 intr_status
= sh_eth_read(ndev
, EESR
);
1654 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1655 * enabled since it's the one that comes thru regardless of the mask,
1656 * and we need to fully handle it in sh_eth_error() in order to quench
1657 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1659 intr_enable
= sh_eth_read(ndev
, EESIPR
);
1660 intr_status
&= intr_enable
| DMAC_M_ECI
;
1661 if (intr_status
& (EESR_RX_CHECK
| cd
->tx_check
| cd
->eesr_err_check
))
1666 if (!likely(mdp
->irq_enabled
)) {
1667 sh_eth_write(ndev
, 0, EESIPR
);
1671 if (intr_status
& EESR_RX_CHECK
) {
1672 if (napi_schedule_prep(&mdp
->napi
)) {
1673 /* Mask Rx interrupts */
1674 sh_eth_write(ndev
, intr_enable
& ~EESR_RX_CHECK
,
1676 __napi_schedule(&mdp
->napi
);
1679 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1680 intr_status
, intr_enable
);
1685 if (intr_status
& cd
->tx_check
) {
1686 /* Clear Tx interrupts */
1687 sh_eth_write(ndev
, intr_status
& cd
->tx_check
, EESR
);
1689 sh_eth_txfree(ndev
);
1690 netif_wake_queue(ndev
);
1693 if (intr_status
& cd
->eesr_err_check
) {
1694 /* Clear error interrupts */
1695 sh_eth_write(ndev
, intr_status
& cd
->eesr_err_check
, EESR
);
1697 sh_eth_error(ndev
, intr_status
);
1701 spin_unlock(&mdp
->lock
);
1706 static int sh_eth_poll(struct napi_struct
*napi
, int budget
)
1708 struct sh_eth_private
*mdp
= container_of(napi
, struct sh_eth_private
,
1710 struct net_device
*ndev
= napi
->dev
;
1715 intr_status
= sh_eth_read(ndev
, EESR
);
1716 if (!(intr_status
& EESR_RX_CHECK
))
1718 /* Clear Rx interrupts */
1719 sh_eth_write(ndev
, intr_status
& EESR_RX_CHECK
, EESR
);
1721 if (sh_eth_rx(ndev
, intr_status
, "a
))
1725 napi_complete(napi
);
1727 /* Reenable Rx interrupts */
1728 if (mdp
->irq_enabled
)
1729 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1731 return budget
- quota
;
1734 /* PHY state control function */
1735 static void sh_eth_adjust_link(struct net_device
*ndev
)
1737 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1738 struct phy_device
*phydev
= mdp
->phydev
;
1742 if (phydev
->duplex
!= mdp
->duplex
) {
1744 mdp
->duplex
= phydev
->duplex
;
1745 if (mdp
->cd
->set_duplex
)
1746 mdp
->cd
->set_duplex(ndev
);
1749 if (phydev
->speed
!= mdp
->speed
) {
1751 mdp
->speed
= phydev
->speed
;
1752 if (mdp
->cd
->set_rate
)
1753 mdp
->cd
->set_rate(ndev
);
1756 sh_eth_modify(ndev
, ECMR
, ECMR_TXF
, 0);
1758 mdp
->link
= phydev
->link
;
1759 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1760 sh_eth_rcv_snd_enable(ndev
);
1762 } else if (mdp
->link
) {
1767 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1768 sh_eth_rcv_snd_disable(ndev
);
1771 if (new_state
&& netif_msg_link(mdp
))
1772 phy_print_status(phydev
);
1775 /* PHY init function */
1776 static int sh_eth_phy_init(struct net_device
*ndev
)
1778 struct device_node
*np
= ndev
->dev
.parent
->of_node
;
1779 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1780 struct phy_device
*phydev
= NULL
;
1786 /* Try connect to PHY */
1788 struct device_node
*pn
;
1790 pn
= of_parse_phandle(np
, "phy-handle", 0);
1791 phydev
= of_phy_connect(ndev
, pn
,
1792 sh_eth_adjust_link
, 0,
1793 mdp
->phy_interface
);
1796 phydev
= ERR_PTR(-ENOENT
);
1798 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1800 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
,
1801 mdp
->mii_bus
->id
, mdp
->phy_id
);
1803 phydev
= phy_connect(ndev
, phy_id
, sh_eth_adjust_link
,
1804 mdp
->phy_interface
);
1807 if (IS_ERR(phydev
)) {
1808 netdev_err(ndev
, "failed to connect PHY\n");
1809 return PTR_ERR(phydev
);
1812 phy_attached_info(phydev
);
1814 mdp
->phydev
= phydev
;
1819 /* PHY control start function */
1820 static int sh_eth_phy_start(struct net_device
*ndev
)
1822 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1825 ret
= sh_eth_phy_init(ndev
);
1829 phy_start(mdp
->phydev
);
1834 static int sh_eth_get_settings(struct net_device
*ndev
,
1835 struct ethtool_cmd
*ecmd
)
1837 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1838 unsigned long flags
;
1844 spin_lock_irqsave(&mdp
->lock
, flags
);
1845 ret
= phy_ethtool_gset(mdp
->phydev
, ecmd
);
1846 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1851 static int sh_eth_set_settings(struct net_device
*ndev
,
1852 struct ethtool_cmd
*ecmd
)
1854 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1855 unsigned long flags
;
1861 spin_lock_irqsave(&mdp
->lock
, flags
);
1863 /* disable tx and rx */
1864 sh_eth_rcv_snd_disable(ndev
);
1866 ret
= phy_ethtool_sset(mdp
->phydev
, ecmd
);
1870 if (ecmd
->duplex
== DUPLEX_FULL
)
1875 if (mdp
->cd
->set_duplex
)
1876 mdp
->cd
->set_duplex(ndev
);
1881 /* enable tx and rx */
1882 sh_eth_rcv_snd_enable(ndev
);
1884 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1889 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1890 * version must be bumped as well. Just adding registers up to that
1891 * limit is fine, as long as the existing register indices don't
1894 #define SH_ETH_REG_DUMP_VERSION 1
1895 #define SH_ETH_REG_DUMP_MAX_REGS 256
1897 static size_t __sh_eth_get_regs(struct net_device
*ndev
, u32
*buf
)
1899 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1900 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
1904 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET
> SH_ETH_REG_DUMP_MAX_REGS
);
1906 /* Dump starts with a bitmap that tells ethtool which
1907 * registers are defined for this chip.
1909 len
= DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS
, 32);
1917 /* Add a register to the dump, if it has a defined offset.
1918 * This automatically skips most undefined registers, but for
1919 * some it is also necessary to check a capability flag in
1920 * struct sh_eth_cpu_data.
1922 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1923 #define add_reg_from(reg, read_expr) do { \
1924 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1926 mark_reg_valid(reg); \
1927 *buf++ = read_expr; \
1932 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1933 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2005 add_tsu_reg(TSU_CTRST
);
2006 add_tsu_reg(TSU_FWEN0
);
2007 add_tsu_reg(TSU_FWEN1
);
2008 add_tsu_reg(TSU_FCM
);
2009 add_tsu_reg(TSU_BSYSL0
);
2010 add_tsu_reg(TSU_BSYSL1
);
2011 add_tsu_reg(TSU_PRISL0
);
2012 add_tsu_reg(TSU_PRISL1
);
2013 add_tsu_reg(TSU_FWSL0
);
2014 add_tsu_reg(TSU_FWSL1
);
2015 add_tsu_reg(TSU_FWSLC
);
2016 add_tsu_reg(TSU_QTAG0
);
2017 add_tsu_reg(TSU_QTAG1
);
2018 add_tsu_reg(TSU_QTAGM0
);
2019 add_tsu_reg(TSU_QTAGM1
);
2020 add_tsu_reg(TSU_FWSR
);
2021 add_tsu_reg(TSU_FWINMK
);
2022 add_tsu_reg(TSU_ADQT0
);
2023 add_tsu_reg(TSU_ADQT1
);
2024 add_tsu_reg(TSU_VTAG0
);
2025 add_tsu_reg(TSU_VTAG1
);
2026 add_tsu_reg(TSU_ADSBSY
);
2027 add_tsu_reg(TSU_TEN
);
2028 add_tsu_reg(TSU_POST1
);
2029 add_tsu_reg(TSU_POST2
);
2030 add_tsu_reg(TSU_POST3
);
2031 add_tsu_reg(TSU_POST4
);
2032 if (mdp
->reg_offset
[TSU_ADRH0
] != SH_ETH_OFFSET_INVALID
) {
2033 /* This is the start of a table, not just a single
2039 mark_reg_valid(TSU_ADRH0
);
2040 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
* 2; i
++)
2043 mdp
->reg_offset
[TSU_ADRH0
] +
2046 len
+= SH_ETH_TSU_CAM_ENTRIES
* 2;
2050 #undef mark_reg_valid
2058 static int sh_eth_get_regs_len(struct net_device
*ndev
)
2060 return __sh_eth_get_regs(ndev
, NULL
);
2063 static void sh_eth_get_regs(struct net_device
*ndev
, struct ethtool_regs
*regs
,
2066 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2068 regs
->version
= SH_ETH_REG_DUMP_VERSION
;
2070 pm_runtime_get_sync(&mdp
->pdev
->dev
);
2071 __sh_eth_get_regs(ndev
, buf
);
2072 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2075 static int sh_eth_nway_reset(struct net_device
*ndev
)
2077 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2078 unsigned long flags
;
2084 spin_lock_irqsave(&mdp
->lock
, flags
);
2085 ret
= phy_start_aneg(mdp
->phydev
);
2086 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2091 static u32
sh_eth_get_msglevel(struct net_device
*ndev
)
2093 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2094 return mdp
->msg_enable
;
2097 static void sh_eth_set_msglevel(struct net_device
*ndev
, u32 value
)
2099 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2100 mdp
->msg_enable
= value
;
2103 static const char sh_eth_gstrings_stats
[][ETH_GSTRING_LEN
] = {
2104 "rx_current", "tx_current",
2105 "rx_dirty", "tx_dirty",
2107 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2109 static int sh_eth_get_sset_count(struct net_device
*netdev
, int sset
)
2113 return SH_ETH_STATS_LEN
;
2119 static void sh_eth_get_ethtool_stats(struct net_device
*ndev
,
2120 struct ethtool_stats
*stats
, u64
*data
)
2122 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2125 /* device-specific stats */
2126 data
[i
++] = mdp
->cur_rx
;
2127 data
[i
++] = mdp
->cur_tx
;
2128 data
[i
++] = mdp
->dirty_rx
;
2129 data
[i
++] = mdp
->dirty_tx
;
2132 static void sh_eth_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
2134 switch (stringset
) {
2136 memcpy(data
, *sh_eth_gstrings_stats
,
2137 sizeof(sh_eth_gstrings_stats
));
2142 static void sh_eth_get_ringparam(struct net_device
*ndev
,
2143 struct ethtool_ringparam
*ring
)
2145 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2147 ring
->rx_max_pending
= RX_RING_MAX
;
2148 ring
->tx_max_pending
= TX_RING_MAX
;
2149 ring
->rx_pending
= mdp
->num_rx_ring
;
2150 ring
->tx_pending
= mdp
->num_tx_ring
;
2153 static int sh_eth_set_ringparam(struct net_device
*ndev
,
2154 struct ethtool_ringparam
*ring
)
2156 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2159 if (ring
->tx_pending
> TX_RING_MAX
||
2160 ring
->rx_pending
> RX_RING_MAX
||
2161 ring
->tx_pending
< TX_RING_MIN
||
2162 ring
->rx_pending
< RX_RING_MIN
)
2164 if (ring
->rx_mini_pending
|| ring
->rx_jumbo_pending
)
2167 if (netif_running(ndev
)) {
2168 netif_device_detach(ndev
);
2169 netif_tx_disable(ndev
);
2171 /* Serialise with the interrupt handler and NAPI, then
2172 * disable interrupts. We have to clear the
2173 * irq_enabled flag first to ensure that interrupts
2174 * won't be re-enabled.
2176 mdp
->irq_enabled
= false;
2177 synchronize_irq(ndev
->irq
);
2178 napi_synchronize(&mdp
->napi
);
2179 sh_eth_write(ndev
, 0x0000, EESIPR
);
2181 sh_eth_dev_exit(ndev
);
2183 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2184 sh_eth_ring_free(ndev
);
2187 /* Set new parameters */
2188 mdp
->num_rx_ring
= ring
->rx_pending
;
2189 mdp
->num_tx_ring
= ring
->tx_pending
;
2191 if (netif_running(ndev
)) {
2192 ret
= sh_eth_ring_init(ndev
);
2194 netdev_err(ndev
, "%s: sh_eth_ring_init failed.\n",
2198 ret
= sh_eth_dev_init(ndev
, false);
2200 netdev_err(ndev
, "%s: sh_eth_dev_init failed.\n",
2205 mdp
->irq_enabled
= true;
2206 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
2207 /* Setting the Rx mode will start the Rx process. */
2208 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
2209 netif_device_attach(ndev
);
2215 static const struct ethtool_ops sh_eth_ethtool_ops
= {
2216 .get_settings
= sh_eth_get_settings
,
2217 .set_settings
= sh_eth_set_settings
,
2218 .get_regs_len
= sh_eth_get_regs_len
,
2219 .get_regs
= sh_eth_get_regs
,
2220 .nway_reset
= sh_eth_nway_reset
,
2221 .get_msglevel
= sh_eth_get_msglevel
,
2222 .set_msglevel
= sh_eth_set_msglevel
,
2223 .get_link
= ethtool_op_get_link
,
2224 .get_strings
= sh_eth_get_strings
,
2225 .get_ethtool_stats
= sh_eth_get_ethtool_stats
,
2226 .get_sset_count
= sh_eth_get_sset_count
,
2227 .get_ringparam
= sh_eth_get_ringparam
,
2228 .set_ringparam
= sh_eth_set_ringparam
,
2231 /* network device open function */
2232 static int sh_eth_open(struct net_device
*ndev
)
2235 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2237 pm_runtime_get_sync(&mdp
->pdev
->dev
);
2239 napi_enable(&mdp
->napi
);
2241 ret
= request_irq(ndev
->irq
, sh_eth_interrupt
,
2242 mdp
->cd
->irq_flags
, ndev
->name
, ndev
);
2244 netdev_err(ndev
, "Can not assign IRQ number\n");
2248 /* Descriptor set */
2249 ret
= sh_eth_ring_init(ndev
);
2254 ret
= sh_eth_dev_init(ndev
, true);
2258 /* PHY control start*/
2259 ret
= sh_eth_phy_start(ndev
);
2268 free_irq(ndev
->irq
, ndev
);
2270 napi_disable(&mdp
->napi
);
2271 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2275 /* Timeout function */
2276 static void sh_eth_tx_timeout(struct net_device
*ndev
)
2278 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2279 struct sh_eth_rxdesc
*rxdesc
;
2282 netif_stop_queue(ndev
);
2284 netif_err(mdp
, timer
, ndev
,
2285 "transmit timed out, status %8.8x, resetting...\n",
2286 sh_eth_read(ndev
, EESR
));
2288 /* tx_errors count up */
2289 ndev
->stats
.tx_errors
++;
2291 /* Free all the skbuffs in the Rx queue. */
2292 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
2293 rxdesc
= &mdp
->rx_ring
[i
];
2294 rxdesc
->status
= cpu_to_le32(0);
2295 rxdesc
->addr
= cpu_to_le32(0xBADF00D0);
2296 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
2297 mdp
->rx_skbuff
[i
] = NULL
;
2299 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
2300 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
2301 mdp
->tx_skbuff
[i
] = NULL
;
2305 sh_eth_dev_init(ndev
, true);
2308 /* Packet transmit function */
2309 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
2311 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2312 struct sh_eth_txdesc
*txdesc
;
2313 dma_addr_t dma_addr
;
2315 unsigned long flags
;
2317 spin_lock_irqsave(&mdp
->lock
, flags
);
2318 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (mdp
->num_tx_ring
- 4)) {
2319 if (!sh_eth_txfree(ndev
)) {
2320 netif_warn(mdp
, tx_queued
, ndev
, "TxFD exhausted.\n");
2321 netif_stop_queue(ndev
);
2322 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2323 return NETDEV_TX_BUSY
;
2326 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2328 if (skb_put_padto(skb
, ETH_ZLEN
))
2329 return NETDEV_TX_OK
;
2331 entry
= mdp
->cur_tx
% mdp
->num_tx_ring
;
2332 mdp
->tx_skbuff
[entry
] = skb
;
2333 txdesc
= &mdp
->tx_ring
[entry
];
2335 if (!mdp
->cd
->hw_swap
)
2336 sh_eth_soft_swap(PTR_ALIGN(skb
->data
, 4), skb
->len
+ 2);
2337 dma_addr
= dma_map_single(&ndev
->dev
, skb
->data
, skb
->len
,
2339 if (dma_mapping_error(&ndev
->dev
, dma_addr
)) {
2341 return NETDEV_TX_OK
;
2343 txdesc
->addr
= cpu_to_le32(dma_addr
);
2344 txdesc
->len
= cpu_to_le32(skb
->len
<< 16);
2346 dma_wmb(); /* TACT bit must be set after all the above writes */
2347 if (entry
>= mdp
->num_tx_ring
- 1)
2348 txdesc
->status
|= cpu_to_le32(TD_TACT
| TD_TDLE
);
2350 txdesc
->status
|= cpu_to_le32(TD_TACT
);
2354 if (!(sh_eth_read(ndev
, EDTRR
) & sh_eth_get_edtrr_trns(mdp
)))
2355 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
2357 return NETDEV_TX_OK
;
2360 /* The statistics registers have write-clear behaviour, which means we
2361 * will lose any increment between the read and write. We mitigate
2362 * this by only clearing when we read a non-zero value, so we will
2363 * never falsely report a total of zero.
2366 sh_eth_update_stat(struct net_device
*ndev
, unsigned long *stat
, int reg
)
2368 u32 delta
= sh_eth_read(ndev
, reg
);
2372 sh_eth_write(ndev
, 0, reg
);
2376 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
2378 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2380 if (sh_eth_is_rz_fast_ether(mdp
))
2381 return &ndev
->stats
;
2383 if (!mdp
->is_opened
)
2384 return &ndev
->stats
;
2386 sh_eth_update_stat(ndev
, &ndev
->stats
.tx_dropped
, TROCR
);
2387 sh_eth_update_stat(ndev
, &ndev
->stats
.collisions
, CDCR
);
2388 sh_eth_update_stat(ndev
, &ndev
->stats
.tx_carrier_errors
, LCCR
);
2390 if (sh_eth_is_gether(mdp
)) {
2391 sh_eth_update_stat(ndev
, &ndev
->stats
.tx_carrier_errors
,
2393 sh_eth_update_stat(ndev
, &ndev
->stats
.tx_carrier_errors
,
2396 sh_eth_update_stat(ndev
, &ndev
->stats
.tx_carrier_errors
,
2400 return &ndev
->stats
;
2403 /* device close function */
2404 static int sh_eth_close(struct net_device
*ndev
)
2406 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2408 netif_stop_queue(ndev
);
2410 /* Serialise with the interrupt handler and NAPI, then disable
2411 * interrupts. We have to clear the irq_enabled flag first to
2412 * ensure that interrupts won't be re-enabled.
2414 mdp
->irq_enabled
= false;
2415 synchronize_irq(ndev
->irq
);
2416 napi_disable(&mdp
->napi
);
2417 sh_eth_write(ndev
, 0x0000, EESIPR
);
2419 sh_eth_dev_exit(ndev
);
2421 /* PHY Disconnect */
2423 phy_stop(mdp
->phydev
);
2424 phy_disconnect(mdp
->phydev
);
2428 free_irq(ndev
->irq
, ndev
);
2430 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2431 sh_eth_ring_free(ndev
);
2433 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2440 /* ioctl to device function */
2441 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
, int cmd
)
2443 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2444 struct phy_device
*phydev
= mdp
->phydev
;
2446 if (!netif_running(ndev
))
2452 return phy_mii_ioctl(phydev
, rq
, cmd
);
2455 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2456 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private
*mdp
,
2459 return sh_eth_tsu_get_offset(mdp
, TSU_POST1
) + (entry
/ 8 * 4);
2462 static u32
sh_eth_tsu_get_post_mask(int entry
)
2464 return 0x0f << (28 - ((entry
% 8) * 4));
2467 static u32
sh_eth_tsu_get_post_bit(struct sh_eth_private
*mdp
, int entry
)
2469 return (0x08 >> (mdp
->port
<< 1)) << (28 - ((entry
% 8) * 4));
2472 static void sh_eth_tsu_enable_cam_entry_post(struct net_device
*ndev
,
2475 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2479 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
2480 tmp
= ioread32(reg_offset
);
2481 iowrite32(tmp
| sh_eth_tsu_get_post_bit(mdp
, entry
), reg_offset
);
2484 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device
*ndev
,
2487 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2488 u32 post_mask
, ref_mask
, tmp
;
2491 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
2492 post_mask
= sh_eth_tsu_get_post_mask(entry
);
2493 ref_mask
= sh_eth_tsu_get_post_bit(mdp
, entry
) & ~post_mask
;
2495 tmp
= ioread32(reg_offset
);
2496 iowrite32(tmp
& ~post_mask
, reg_offset
);
2498 /* If other port enables, the function returns "true" */
2499 return tmp
& ref_mask
;
2502 static int sh_eth_tsu_busy(struct net_device
*ndev
)
2504 int timeout
= SH_ETH_TSU_TIMEOUT_MS
* 100;
2505 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2507 while ((sh_eth_tsu_read(mdp
, TSU_ADSBSY
) & TSU_ADSBSY_0
)) {
2511 netdev_err(ndev
, "%s: timeout\n", __func__
);
2519 static int sh_eth_tsu_write_entry(struct net_device
*ndev
, void *reg
,
2524 val
= addr
[0] << 24 | addr
[1] << 16 | addr
[2] << 8 | addr
[3];
2525 iowrite32(val
, reg
);
2526 if (sh_eth_tsu_busy(ndev
) < 0)
2529 val
= addr
[4] << 8 | addr
[5];
2530 iowrite32(val
, reg
+ 4);
2531 if (sh_eth_tsu_busy(ndev
) < 0)
2537 static void sh_eth_tsu_read_entry(void *reg
, u8
*addr
)
2541 val
= ioread32(reg
);
2542 addr
[0] = (val
>> 24) & 0xff;
2543 addr
[1] = (val
>> 16) & 0xff;
2544 addr
[2] = (val
>> 8) & 0xff;
2545 addr
[3] = val
& 0xff;
2546 val
= ioread32(reg
+ 4);
2547 addr
[4] = (val
>> 8) & 0xff;
2548 addr
[5] = val
& 0xff;
2552 static int sh_eth_tsu_find_entry(struct net_device
*ndev
, const u8
*addr
)
2554 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2555 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2557 u8 c_addr
[ETH_ALEN
];
2559 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
2560 sh_eth_tsu_read_entry(reg_offset
, c_addr
);
2561 if (ether_addr_equal(addr
, c_addr
))
2568 static int sh_eth_tsu_find_empty(struct net_device
*ndev
)
2573 memset(blank
, 0, sizeof(blank
));
2574 entry
= sh_eth_tsu_find_entry(ndev
, blank
);
2575 return (entry
< 0) ? -ENOMEM
: entry
;
2578 static int sh_eth_tsu_disable_cam_entry_table(struct net_device
*ndev
,
2581 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2582 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2586 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) &
2587 ~(1 << (31 - entry
)), TSU_TEN
);
2589 memset(blank
, 0, sizeof(blank
));
2590 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ entry
* 8, blank
);
2596 static int sh_eth_tsu_add_entry(struct net_device
*ndev
, const u8
*addr
)
2598 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2599 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2605 i
= sh_eth_tsu_find_entry(ndev
, addr
);
2607 /* No entry found, create one */
2608 i
= sh_eth_tsu_find_empty(ndev
);
2611 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ i
* 8, addr
);
2615 /* Enable the entry */
2616 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) |
2617 (1 << (31 - i
)), TSU_TEN
);
2620 /* Entry found or created, enable POST */
2621 sh_eth_tsu_enable_cam_entry_post(ndev
, i
);
2626 static int sh_eth_tsu_del_entry(struct net_device
*ndev
, const u8
*addr
)
2628 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2634 i
= sh_eth_tsu_find_entry(ndev
, addr
);
2637 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
2640 /* Disable the entry if both ports was disabled */
2641 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
2649 static int sh_eth_tsu_purge_all(struct net_device
*ndev
)
2651 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2657 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++) {
2658 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
2661 /* Disable the entry if both ports was disabled */
2662 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
2670 static void sh_eth_tsu_purge_mcast(struct net_device
*ndev
)
2672 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2674 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2680 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
2681 sh_eth_tsu_read_entry(reg_offset
, addr
);
2682 if (is_multicast_ether_addr(addr
))
2683 sh_eth_tsu_del_entry(ndev
, addr
);
2687 /* Update promiscuous flag and multicast filter */
2688 static void sh_eth_set_rx_mode(struct net_device
*ndev
)
2690 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2693 unsigned long flags
;
2695 spin_lock_irqsave(&mdp
->lock
, flags
);
2696 /* Initial condition is MCT = 1, PRM = 0.
2697 * Depending on ndev->flags, set PRM or clear MCT
2699 ecmr_bits
= sh_eth_read(ndev
, ECMR
) & ~ECMR_PRM
;
2701 ecmr_bits
|= ECMR_MCT
;
2703 if (!(ndev
->flags
& IFF_MULTICAST
)) {
2704 sh_eth_tsu_purge_mcast(ndev
);
2707 if (ndev
->flags
& IFF_ALLMULTI
) {
2708 sh_eth_tsu_purge_mcast(ndev
);
2709 ecmr_bits
&= ~ECMR_MCT
;
2713 if (ndev
->flags
& IFF_PROMISC
) {
2714 sh_eth_tsu_purge_all(ndev
);
2715 ecmr_bits
= (ecmr_bits
& ~ECMR_MCT
) | ECMR_PRM
;
2716 } else if (mdp
->cd
->tsu
) {
2717 struct netdev_hw_addr
*ha
;
2718 netdev_for_each_mc_addr(ha
, ndev
) {
2719 if (mcast_all
&& is_multicast_ether_addr(ha
->addr
))
2722 if (sh_eth_tsu_add_entry(ndev
, ha
->addr
) < 0) {
2724 sh_eth_tsu_purge_mcast(ndev
);
2725 ecmr_bits
&= ~ECMR_MCT
;
2732 /* update the ethernet mode */
2733 sh_eth_write(ndev
, ecmr_bits
, ECMR
);
2735 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2738 static int sh_eth_get_vtag_index(struct sh_eth_private
*mdp
)
2746 static int sh_eth_vlan_rx_add_vid(struct net_device
*ndev
,
2747 __be16 proto
, u16 vid
)
2749 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2750 int vtag_reg_index
= sh_eth_get_vtag_index(mdp
);
2752 if (unlikely(!mdp
->cd
->tsu
))
2755 /* No filtering if vid = 0 */
2759 mdp
->vlan_num_ids
++;
2761 /* The controller has one VLAN tag HW filter. So, if the filter is
2762 * already enabled, the driver disables it and the filte
2764 if (mdp
->vlan_num_ids
> 1) {
2765 /* disable VLAN filter */
2766 sh_eth_tsu_write(mdp
, 0, vtag_reg_index
);
2770 sh_eth_tsu_write(mdp
, TSU_VTAG_ENABLE
| (vid
& TSU_VTAG_VID_MASK
),
2776 static int sh_eth_vlan_rx_kill_vid(struct net_device
*ndev
,
2777 __be16 proto
, u16 vid
)
2779 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2780 int vtag_reg_index
= sh_eth_get_vtag_index(mdp
);
2782 if (unlikely(!mdp
->cd
->tsu
))
2785 /* No filtering if vid = 0 */
2789 mdp
->vlan_num_ids
--;
2790 sh_eth_tsu_write(mdp
, 0, vtag_reg_index
);
2795 /* SuperH's TSU register init function */
2796 static void sh_eth_tsu_init(struct sh_eth_private
*mdp
)
2798 if (sh_eth_is_rz_fast_ether(mdp
)) {
2799 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
2803 sh_eth_tsu_write(mdp
, 0, TSU_FWEN0
); /* Disable forward(0->1) */
2804 sh_eth_tsu_write(mdp
, 0, TSU_FWEN1
); /* Disable forward(1->0) */
2805 sh_eth_tsu_write(mdp
, 0, TSU_FCM
); /* forward fifo 3k-3k */
2806 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL0
);
2807 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL1
);
2808 sh_eth_tsu_write(mdp
, 0, TSU_PRISL0
);
2809 sh_eth_tsu_write(mdp
, 0, TSU_PRISL1
);
2810 sh_eth_tsu_write(mdp
, 0, TSU_FWSL0
);
2811 sh_eth_tsu_write(mdp
, 0, TSU_FWSL1
);
2812 sh_eth_tsu_write(mdp
, TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, TSU_FWSLC
);
2813 if (sh_eth_is_gether(mdp
)) {
2814 sh_eth_tsu_write(mdp
, 0, TSU_QTAG0
); /* Disable QTAG(0->1) */
2815 sh_eth_tsu_write(mdp
, 0, TSU_QTAG1
); /* Disable QTAG(1->0) */
2817 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM0
); /* Disable QTAG(0->1) */
2818 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM1
); /* Disable QTAG(1->0) */
2820 sh_eth_tsu_write(mdp
, 0, TSU_FWSR
); /* all interrupt status clear */
2821 sh_eth_tsu_write(mdp
, 0, TSU_FWINMK
); /* Disable all interrupt */
2822 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
2823 sh_eth_tsu_write(mdp
, 0, TSU_POST1
); /* Disable CAM entry [ 0- 7] */
2824 sh_eth_tsu_write(mdp
, 0, TSU_POST2
); /* Disable CAM entry [ 8-15] */
2825 sh_eth_tsu_write(mdp
, 0, TSU_POST3
); /* Disable CAM entry [16-23] */
2826 sh_eth_tsu_write(mdp
, 0, TSU_POST4
); /* Disable CAM entry [24-31] */
2829 /* MDIO bus release function */
2830 static int sh_mdio_release(struct sh_eth_private
*mdp
)
2832 /* unregister mdio bus */
2833 mdiobus_unregister(mdp
->mii_bus
);
2835 /* free bitbang info */
2836 free_mdio_bitbang(mdp
->mii_bus
);
2841 /* MDIO bus init function */
2842 static int sh_mdio_init(struct sh_eth_private
*mdp
,
2843 struct sh_eth_plat_data
*pd
)
2846 struct bb_info
*bitbang
;
2847 struct platform_device
*pdev
= mdp
->pdev
;
2848 struct device
*dev
= &mdp
->pdev
->dev
;
2850 /* create bit control struct for PHY */
2851 bitbang
= devm_kzalloc(dev
, sizeof(struct bb_info
), GFP_KERNEL
);
2856 bitbang
->addr
= mdp
->addr
+ mdp
->reg_offset
[PIR
];
2857 bitbang
->set_gate
= pd
->set_mdio_gate
;
2858 bitbang
->ctrl
.ops
= &bb_ops
;
2860 /* MII controller setting */
2861 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
2865 /* Hook up MII support for ethtool */
2866 mdp
->mii_bus
->name
= "sh_mii";
2867 mdp
->mii_bus
->parent
= dev
;
2868 snprintf(mdp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
2869 pdev
->name
, pdev
->id
);
2871 /* register MDIO bus */
2873 ret
= of_mdiobus_register(mdp
->mii_bus
, dev
->of_node
);
2875 if (pd
->phy_irq
> 0)
2876 mdp
->mii_bus
->irq
[pd
->phy
] = pd
->phy_irq
;
2878 ret
= mdiobus_register(mdp
->mii_bus
);
2887 free_mdio_bitbang(mdp
->mii_bus
);
2891 static const u16
*sh_eth_get_register_offset(int register_type
)
2893 const u16
*reg_offset
= NULL
;
2895 switch (register_type
) {
2896 case SH_ETH_REG_GIGABIT
:
2897 reg_offset
= sh_eth_offset_gigabit
;
2899 case SH_ETH_REG_FAST_RZ
:
2900 reg_offset
= sh_eth_offset_fast_rz
;
2902 case SH_ETH_REG_FAST_RCAR
:
2903 reg_offset
= sh_eth_offset_fast_rcar
;
2905 case SH_ETH_REG_FAST_SH4
:
2906 reg_offset
= sh_eth_offset_fast_sh4
;
2908 case SH_ETH_REG_FAST_SH3_SH2
:
2909 reg_offset
= sh_eth_offset_fast_sh3_sh2
;
2916 static const struct net_device_ops sh_eth_netdev_ops
= {
2917 .ndo_open
= sh_eth_open
,
2918 .ndo_stop
= sh_eth_close
,
2919 .ndo_start_xmit
= sh_eth_start_xmit
,
2920 .ndo_get_stats
= sh_eth_get_stats
,
2921 .ndo_set_rx_mode
= sh_eth_set_rx_mode
,
2922 .ndo_tx_timeout
= sh_eth_tx_timeout
,
2923 .ndo_do_ioctl
= sh_eth_do_ioctl
,
2924 .ndo_validate_addr
= eth_validate_addr
,
2925 .ndo_set_mac_address
= eth_mac_addr
,
2926 .ndo_change_mtu
= eth_change_mtu
,
2929 static const struct net_device_ops sh_eth_netdev_ops_tsu
= {
2930 .ndo_open
= sh_eth_open
,
2931 .ndo_stop
= sh_eth_close
,
2932 .ndo_start_xmit
= sh_eth_start_xmit
,
2933 .ndo_get_stats
= sh_eth_get_stats
,
2934 .ndo_set_rx_mode
= sh_eth_set_rx_mode
,
2935 .ndo_vlan_rx_add_vid
= sh_eth_vlan_rx_add_vid
,
2936 .ndo_vlan_rx_kill_vid
= sh_eth_vlan_rx_kill_vid
,
2937 .ndo_tx_timeout
= sh_eth_tx_timeout
,
2938 .ndo_do_ioctl
= sh_eth_do_ioctl
,
2939 .ndo_validate_addr
= eth_validate_addr
,
2940 .ndo_set_mac_address
= eth_mac_addr
,
2941 .ndo_change_mtu
= eth_change_mtu
,
2945 static struct sh_eth_plat_data
*sh_eth_parse_dt(struct device
*dev
)
2947 struct device_node
*np
= dev
->of_node
;
2948 struct sh_eth_plat_data
*pdata
;
2949 const char *mac_addr
;
2951 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
2955 pdata
->phy_interface
= of_get_phy_mode(np
);
2957 mac_addr
= of_get_mac_address(np
);
2959 memcpy(pdata
->mac_addr
, mac_addr
, ETH_ALEN
);
2961 pdata
->no_ether_link
=
2962 of_property_read_bool(np
, "renesas,no-ether-link");
2963 pdata
->ether_link_active_low
=
2964 of_property_read_bool(np
, "renesas,ether-link-active-low");
2969 static const struct of_device_id sh_eth_match_table
[] = {
2970 { .compatible
= "renesas,gether-r8a7740", .data
= &r8a7740_data
},
2971 { .compatible
= "renesas,ether-r8a7778", .data
= &r8a777x_data
},
2972 { .compatible
= "renesas,ether-r8a7779", .data
= &r8a777x_data
},
2973 { .compatible
= "renesas,ether-r8a7790", .data
= &r8a779x_data
},
2974 { .compatible
= "renesas,ether-r8a7791", .data
= &r8a779x_data
},
2975 { .compatible
= "renesas,ether-r8a7793", .data
= &r8a779x_data
},
2976 { .compatible
= "renesas,ether-r8a7794", .data
= &r8a779x_data
},
2977 { .compatible
= "renesas,ether-r7s72100", .data
= &r7s72100_data
},
2980 MODULE_DEVICE_TABLE(of
, sh_eth_match_table
);
2982 static inline struct sh_eth_plat_data
*sh_eth_parse_dt(struct device
*dev
)
2988 static int sh_eth_drv_probe(struct platform_device
*pdev
)
2991 struct resource
*res
;
2992 struct net_device
*ndev
= NULL
;
2993 struct sh_eth_private
*mdp
= NULL
;
2994 struct sh_eth_plat_data
*pd
= dev_get_platdata(&pdev
->dev
);
2995 const struct platform_device_id
*id
= platform_get_device_id(pdev
);
2998 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3000 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
3004 pm_runtime_enable(&pdev
->dev
);
3005 pm_runtime_get_sync(&pdev
->dev
);
3012 ret
= platform_get_irq(pdev
, 0);
3017 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
3019 mdp
= netdev_priv(ndev
);
3020 mdp
->num_tx_ring
= TX_RING_SIZE
;
3021 mdp
->num_rx_ring
= RX_RING_SIZE
;
3022 mdp
->addr
= devm_ioremap_resource(&pdev
->dev
, res
);
3023 if (IS_ERR(mdp
->addr
)) {
3024 ret
= PTR_ERR(mdp
->addr
);
3028 ndev
->base_addr
= res
->start
;
3030 spin_lock_init(&mdp
->lock
);
3033 if (pdev
->dev
.of_node
)
3034 pd
= sh_eth_parse_dt(&pdev
->dev
);
3036 dev_err(&pdev
->dev
, "no platform data\n");
3042 mdp
->phy_id
= pd
->phy
;
3043 mdp
->phy_interface
= pd
->phy_interface
;
3044 mdp
->no_ether_link
= pd
->no_ether_link
;
3045 mdp
->ether_link_active_low
= pd
->ether_link_active_low
;
3049 mdp
->cd
= (struct sh_eth_cpu_data
*)id
->driver_data
;
3051 mdp
->cd
= (struct sh_eth_cpu_data
*)of_device_get_match_data(&pdev
->dev
);
3053 mdp
->reg_offset
= sh_eth_get_register_offset(mdp
->cd
->register_type
);
3054 if (!mdp
->reg_offset
) {
3055 dev_err(&pdev
->dev
, "Unknown register type (%d)\n",
3056 mdp
->cd
->register_type
);
3060 sh_eth_set_default_cpu_data(mdp
->cd
);
3064 ndev
->netdev_ops
= &sh_eth_netdev_ops_tsu
;
3066 ndev
->netdev_ops
= &sh_eth_netdev_ops
;
3067 ndev
->ethtool_ops
= &sh_eth_ethtool_ops
;
3068 ndev
->watchdog_timeo
= TX_TIMEOUT
;
3070 /* debug message level */
3071 mdp
->msg_enable
= SH_ETH_DEF_MSG_ENABLE
;
3073 /* read and set MAC address */
3074 read_mac_address(ndev
, pd
->mac_addr
);
3075 if (!is_valid_ether_addr(ndev
->dev_addr
)) {
3076 dev_warn(&pdev
->dev
,
3077 "no valid MAC address supplied, using a random one.\n");
3078 eth_hw_addr_random(ndev
);
3081 /* ioremap the TSU registers */
3083 struct resource
*rtsu
;
3084 rtsu
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
3085 mdp
->tsu_addr
= devm_ioremap_resource(&pdev
->dev
, rtsu
);
3086 if (IS_ERR(mdp
->tsu_addr
)) {
3087 ret
= PTR_ERR(mdp
->tsu_addr
);
3090 mdp
->port
= devno
% 2;
3091 ndev
->features
= NETIF_F_HW_VLAN_CTAG_FILTER
;
3094 /* initialize first or needed device */
3095 if (!devno
|| pd
->needs_init
) {
3096 if (mdp
->cd
->chip_reset
)
3097 mdp
->cd
->chip_reset(ndev
);
3100 /* TSU init (Init only)*/
3101 sh_eth_tsu_init(mdp
);
3105 if (mdp
->cd
->rmiimode
)
3106 sh_eth_write(ndev
, 0x1, RMIIMODE
);
3109 ret
= sh_mdio_init(mdp
, pd
);
3111 dev_err(&ndev
->dev
, "failed to initialise MDIO\n");
3115 netif_napi_add(ndev
, &mdp
->napi
, sh_eth_poll
, 64);
3117 /* network device register */
3118 ret
= register_netdev(ndev
);
3122 /* print device information */
3123 netdev_info(ndev
, "Base address at 0x%x, %pM, IRQ %d.\n",
3124 (u32
)ndev
->base_addr
, ndev
->dev_addr
, ndev
->irq
);
3126 pm_runtime_put(&pdev
->dev
);
3127 platform_set_drvdata(pdev
, ndev
);
3132 netif_napi_del(&mdp
->napi
);
3133 sh_mdio_release(mdp
);
3140 pm_runtime_put(&pdev
->dev
);
3141 pm_runtime_disable(&pdev
->dev
);
3145 static int sh_eth_drv_remove(struct platform_device
*pdev
)
3147 struct net_device
*ndev
= platform_get_drvdata(pdev
);
3148 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
3150 unregister_netdev(ndev
);
3151 netif_napi_del(&mdp
->napi
);
3152 sh_mdio_release(mdp
);
3153 pm_runtime_disable(&pdev
->dev
);
3160 #ifdef CONFIG_PM_SLEEP
3161 static int sh_eth_suspend(struct device
*dev
)
3163 struct net_device
*ndev
= dev_get_drvdata(dev
);
3166 if (netif_running(ndev
)) {
3167 netif_device_detach(ndev
);
3168 ret
= sh_eth_close(ndev
);
3174 static int sh_eth_resume(struct device
*dev
)
3176 struct net_device
*ndev
= dev_get_drvdata(dev
);
3179 if (netif_running(ndev
)) {
3180 ret
= sh_eth_open(ndev
);
3183 netif_device_attach(ndev
);
3190 static int sh_eth_runtime_nop(struct device
*dev
)
3192 /* Runtime PM callback shared between ->runtime_suspend()
3193 * and ->runtime_resume(). Simply returns success.
3195 * This driver re-initializes all registers after
3196 * pm_runtime_get_sync() anyway so there is no need
3197 * to save and restore registers here.
3202 static const struct dev_pm_ops sh_eth_dev_pm_ops
= {
3203 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend
, sh_eth_resume
)
3204 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop
, sh_eth_runtime_nop
, NULL
)
3206 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3208 #define SH_ETH_PM_OPS NULL
3211 static struct platform_device_id sh_eth_id_table
[] = {
3212 { "sh7619-ether", (kernel_ulong_t
)&sh7619_data
},
3213 { "sh771x-ether", (kernel_ulong_t
)&sh771x_data
},
3214 { "sh7724-ether", (kernel_ulong_t
)&sh7724_data
},
3215 { "sh7734-gether", (kernel_ulong_t
)&sh7734_data
},
3216 { "sh7757-ether", (kernel_ulong_t
)&sh7757_data
},
3217 { "sh7757-gether", (kernel_ulong_t
)&sh7757_data_giga
},
3218 { "sh7763-gether", (kernel_ulong_t
)&sh7763_data
},
3221 MODULE_DEVICE_TABLE(platform
, sh_eth_id_table
);
3223 static struct platform_driver sh_eth_driver
= {
3224 .probe
= sh_eth_drv_probe
,
3225 .remove
= sh_eth_drv_remove
,
3226 .id_table
= sh_eth_id_table
,
3229 .pm
= SH_ETH_PM_OPS
,
3230 .of_match_table
= of_match_ptr(sh_eth_match_table
),
3234 module_platform_driver(sh_eth_driver
);
3236 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3237 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3238 MODULE_LICENSE("GPL v2");