2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/spinlock.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/etherdevice.h>
30 #include <linux/delay.h>
31 #include <linux/platform_device.h>
32 #include <linux/mdio-bitbang.h>
33 #include <linux/netdevice.h>
34 #include <linux/phy.h>
35 #include <linux/cache.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/slab.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/sh_eth.h>
45 #define SH_ETH_DEF_MSG_ENABLE \
51 /* There is CPU dependent code */
52 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
53 #define SH_ETH_RESET_DEFAULT 1
54 static void sh_eth_set_duplex(struct net_device
*ndev
)
56 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
58 if (mdp
->duplex
) /* Full */
59 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
61 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
64 static void sh_eth_set_rate(struct net_device
*ndev
)
66 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
70 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_RTM
, ECMR
);
72 case 100:/* 100BASE */
73 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_RTM
, ECMR
);
81 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
82 .set_duplex
= sh_eth_set_duplex
,
83 .set_rate
= sh_eth_set_rate
,
85 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
86 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
87 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x01ff009f,
89 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
90 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
91 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
92 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
99 .rpadir_value
= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
101 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
102 #define SH_ETH_HAS_BOTH_MODULES 1
103 #define SH_ETH_HAS_TSU 1
104 static void sh_eth_set_duplex(struct net_device
*ndev
)
106 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
108 if (mdp
->duplex
) /* Full */
109 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
111 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
114 static void sh_eth_set_rate(struct net_device
*ndev
)
116 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
118 switch (mdp
->speed
) {
119 case 10: /* 10BASE */
120 sh_eth_write(ndev
, 0, RTRATE
);
122 case 100:/* 100BASE */
123 sh_eth_write(ndev
, 1, RTRATE
);
131 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
132 .set_duplex
= sh_eth_set_duplex
,
133 .set_rate
= sh_eth_set_rate
,
135 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
136 .rmcr_value
= 0x00000001,
138 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
139 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
140 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
141 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
149 .rpadir_value
= 2 << 16,
152 #define SH_GIGA_ETH_BASE 0xfee00000
153 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
154 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
155 static void sh_eth_chip_reset_giga(struct net_device
*ndev
)
158 unsigned long mahr
[2], malr
[2];
160 /* save MAHR and MALR */
161 for (i
= 0; i
< 2; i
++) {
162 malr
[i
] = ioread32((void *)GIGA_MALR(i
));
163 mahr
[i
] = ioread32((void *)GIGA_MAHR(i
));
167 iowrite32(ARSTR_ARSTR
, (void *)(SH_GIGA_ETH_BASE
+ 0x1800));
170 /* restore MAHR and MALR */
171 for (i
= 0; i
< 2; i
++) {
172 iowrite32(malr
[i
], (void *)GIGA_MALR(i
));
173 iowrite32(mahr
[i
], (void *)GIGA_MAHR(i
));
177 static int sh_eth_is_gether(struct sh_eth_private
*mdp
);
178 static void sh_eth_reset(struct net_device
*ndev
)
180 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
183 if (sh_eth_is_gether(mdp
)) {
184 sh_eth_write(ndev
, 0x03, EDSR
);
185 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
,
188 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
194 printk(KERN_ERR
"Device reset fail\n");
197 sh_eth_write(ndev
, 0x0, TDLAR
);
198 sh_eth_write(ndev
, 0x0, TDFAR
);
199 sh_eth_write(ndev
, 0x0, TDFXR
);
200 sh_eth_write(ndev
, 0x0, TDFFR
);
201 sh_eth_write(ndev
, 0x0, RDLAR
);
202 sh_eth_write(ndev
, 0x0, RDFAR
);
203 sh_eth_write(ndev
, 0x0, RDFXR
);
204 sh_eth_write(ndev
, 0x0, RDFFR
);
206 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
,
209 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
,
214 static void sh_eth_set_duplex_giga(struct net_device
*ndev
)
216 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
218 if (mdp
->duplex
) /* Full */
219 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
221 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
224 static void sh_eth_set_rate_giga(struct net_device
*ndev
)
226 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
228 switch (mdp
->speed
) {
229 case 10: /* 10BASE */
230 sh_eth_write(ndev
, 0x00000000, GECMR
);
232 case 100:/* 100BASE */
233 sh_eth_write(ndev
, 0x00000010, GECMR
);
235 case 1000: /* 1000BASE */
236 sh_eth_write(ndev
, 0x00000020, GECMR
);
243 /* SH7757(GETHERC) */
244 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga
= {
245 .chip_reset
= sh_eth_chip_reset_giga
,
246 .set_duplex
= sh_eth_set_duplex_giga
,
247 .set_rate
= sh_eth_set_rate_giga
,
249 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
250 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
251 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
253 .tx_check
= EESR_TC1
| EESR_FTC
,
254 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
255 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
257 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
259 .fdr_value
= 0x0000072f,
260 .rmcr_value
= 0x00000001,
268 .rpadir_value
= 2 << 16,
274 static struct sh_eth_cpu_data
*sh_eth_get_cpu_data(struct sh_eth_private
*mdp
)
276 if (sh_eth_is_gether(mdp
))
277 return &sh_eth_my_cpu_data_giga
;
279 return &sh_eth_my_cpu_data
;
282 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
283 #define SH_ETH_HAS_TSU 1
284 static void sh_eth_chip_reset(struct net_device
*ndev
)
286 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
289 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
293 static void sh_eth_reset(struct net_device
*ndev
)
297 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
298 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
, EDMR
);
300 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
306 printk(KERN_ERR
"Device reset fail\n");
309 sh_eth_write(ndev
, 0x0, TDLAR
);
310 sh_eth_write(ndev
, 0x0, TDFAR
);
311 sh_eth_write(ndev
, 0x0, TDFXR
);
312 sh_eth_write(ndev
, 0x0, TDFFR
);
313 sh_eth_write(ndev
, 0x0, RDLAR
);
314 sh_eth_write(ndev
, 0x0, RDFAR
);
315 sh_eth_write(ndev
, 0x0, RDFXR
);
316 sh_eth_write(ndev
, 0x0, RDFFR
);
319 static void sh_eth_set_duplex(struct net_device
*ndev
)
321 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
323 if (mdp
->duplex
) /* Full */
324 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
326 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
329 static void sh_eth_set_rate(struct net_device
*ndev
)
331 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
333 switch (mdp
->speed
) {
334 case 10: /* 10BASE */
335 sh_eth_write(ndev
, GECMR_10
, GECMR
);
337 case 100:/* 100BASE */
338 sh_eth_write(ndev
, GECMR_100
, GECMR
);
340 case 1000: /* 1000BASE */
341 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
349 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
350 .chip_reset
= sh_eth_chip_reset
,
351 .set_duplex
= sh_eth_set_duplex
,
352 .set_rate
= sh_eth_set_rate
,
354 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
355 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
356 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
358 .tx_check
= EESR_TC1
| EESR_FTC
,
359 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
360 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
362 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
375 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
376 #define SH_ETH_RESET_DEFAULT 1
377 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
378 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
385 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
386 #define SH_ETH_RESET_DEFAULT 1
387 #define SH_ETH_HAS_TSU 1
388 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
389 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
394 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data
*cd
)
397 cd
->ecsr_value
= DEFAULT_ECSR_INIT
;
399 if (!cd
->ecsipr_value
)
400 cd
->ecsipr_value
= DEFAULT_ECSIPR_INIT
;
402 if (!cd
->fcftr_value
)
403 cd
->fcftr_value
= DEFAULT_FIFO_F_D_RFF
| \
404 DEFAULT_FIFO_F_D_RFD
;
407 cd
->fdr_value
= DEFAULT_FDR_INIT
;
410 cd
->rmcr_value
= DEFAULT_RMCR_VALUE
;
413 cd
->tx_check
= DEFAULT_TX_CHECK
;
415 if (!cd
->eesr_err_check
)
416 cd
->eesr_err_check
= DEFAULT_EESR_ERR_CHECK
;
418 if (!cd
->tx_error_check
)
419 cd
->tx_error_check
= DEFAULT_TX_ERROR_CHECK
;
422 #if defined(SH_ETH_RESET_DEFAULT)
424 static void sh_eth_reset(struct net_device
*ndev
)
426 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
, EDMR
);
428 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
, EDMR
);
432 #if defined(CONFIG_CPU_SH4)
433 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
437 reserve
= SH4_SKB_RX_ALIGN
- ((u32
)skb
->data
& (SH4_SKB_RX_ALIGN
- 1));
439 skb_reserve(skb
, reserve
);
442 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
444 skb_reserve(skb
, SH2_SH3_SKB_RX_ALIGN
);
449 /* CPU <-> EDMAC endian convert */
450 static inline __u32
cpu_to_edmac(struct sh_eth_private
*mdp
, u32 x
)
452 switch (mdp
->edmac_endian
) {
453 case EDMAC_LITTLE_ENDIAN
:
454 return cpu_to_le32(x
);
455 case EDMAC_BIG_ENDIAN
:
456 return cpu_to_be32(x
);
461 static inline __u32
edmac_to_cpu(struct sh_eth_private
*mdp
, u32 x
)
463 switch (mdp
->edmac_endian
) {
464 case EDMAC_LITTLE_ENDIAN
:
465 return le32_to_cpu(x
);
466 case EDMAC_BIG_ENDIAN
:
467 return be32_to_cpu(x
);
473 * Program the hardware MAC address from dev->dev_addr.
475 static void update_mac_address(struct net_device
*ndev
)
478 (ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
479 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]), MAHR
);
481 (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]), MALR
);
485 * Get MAC address from SuperH MAC address register
487 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
488 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
489 * When you want use this device, you must set MAC address in bootloader.
492 static void read_mac_address(struct net_device
*ndev
, unsigned char *mac
)
494 if (mac
[0] || mac
[1] || mac
[2] || mac
[3] || mac
[4] || mac
[5]) {
495 memcpy(ndev
->dev_addr
, mac
, 6);
497 ndev
->dev_addr
[0] = (sh_eth_read(ndev
, MAHR
) >> 24);
498 ndev
->dev_addr
[1] = (sh_eth_read(ndev
, MAHR
) >> 16) & 0xFF;
499 ndev
->dev_addr
[2] = (sh_eth_read(ndev
, MAHR
) >> 8) & 0xFF;
500 ndev
->dev_addr
[3] = (sh_eth_read(ndev
, MAHR
) & 0xFF);
501 ndev
->dev_addr
[4] = (sh_eth_read(ndev
, MALR
) >> 8) & 0xFF;
502 ndev
->dev_addr
[5] = (sh_eth_read(ndev
, MALR
) & 0xFF);
506 static int sh_eth_is_gether(struct sh_eth_private
*mdp
)
508 if (mdp
->reg_offset
== sh_eth_offset_gigabit
)
514 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private
*mdp
)
516 if (sh_eth_is_gether(mdp
))
517 return EDTRR_TRNS_GETHER
;
519 return EDTRR_TRNS_ETHER
;
523 void (*set_gate
)(void *addr
);
524 struct mdiobb_ctrl ctrl
;
526 u32 mmd_msk
;/* MMD */
533 static void bb_set(void *addr
, u32 msk
)
535 iowrite32(ioread32(addr
) | msk
, addr
);
539 static void bb_clr(void *addr
, u32 msk
)
541 iowrite32((ioread32(addr
) & ~msk
), addr
);
545 static int bb_read(void *addr
, u32 msk
)
547 return (ioread32(addr
) & msk
) != 0;
550 /* Data I/O pin control */
551 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
553 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
555 if (bitbang
->set_gate
)
556 bitbang
->set_gate(bitbang
->addr
);
559 bb_set(bitbang
->addr
, bitbang
->mmd_msk
);
561 bb_clr(bitbang
->addr
, bitbang
->mmd_msk
);
565 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
567 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
569 if (bitbang
->set_gate
)
570 bitbang
->set_gate(bitbang
->addr
);
573 bb_set(bitbang
->addr
, bitbang
->mdo_msk
);
575 bb_clr(bitbang
->addr
, bitbang
->mdo_msk
);
579 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
581 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
583 if (bitbang
->set_gate
)
584 bitbang
->set_gate(bitbang
->addr
);
586 return bb_read(bitbang
->addr
, bitbang
->mdi_msk
);
589 /* MDC pin control */
590 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
592 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
594 if (bitbang
->set_gate
)
595 bitbang
->set_gate(bitbang
->addr
);
598 bb_set(bitbang
->addr
, bitbang
->mdc_msk
);
600 bb_clr(bitbang
->addr
, bitbang
->mdc_msk
);
603 /* mdio bus control struct */
604 static struct mdiobb_ops bb_ops
= {
605 .owner
= THIS_MODULE
,
606 .set_mdc
= sh_mdc_ctrl
,
607 .set_mdio_dir
= sh_mmd_ctrl
,
608 .set_mdio_data
= sh_set_mdio
,
609 .get_mdio_data
= sh_get_mdio
,
612 /* free skb and descriptor buffer */
613 static void sh_eth_ring_free(struct net_device
*ndev
)
615 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
618 /* Free Rx skb ringbuffer */
619 if (mdp
->rx_skbuff
) {
620 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
621 if (mdp
->rx_skbuff
[i
])
622 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
625 kfree(mdp
->rx_skbuff
);
627 /* Free Tx skb ringbuffer */
628 if (mdp
->tx_skbuff
) {
629 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
630 if (mdp
->tx_skbuff
[i
])
631 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
634 kfree(mdp
->tx_skbuff
);
637 /* format skb and descriptor buffer */
638 static void sh_eth_ring_format(struct net_device
*ndev
)
640 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
643 struct sh_eth_rxdesc
*rxdesc
= NULL
;
644 struct sh_eth_txdesc
*txdesc
= NULL
;
645 int rx_ringsize
= sizeof(*rxdesc
) * RX_RING_SIZE
;
646 int tx_ringsize
= sizeof(*txdesc
) * TX_RING_SIZE
;
648 mdp
->cur_rx
= mdp
->cur_tx
= 0;
649 mdp
->dirty_rx
= mdp
->dirty_tx
= 0;
651 memset(mdp
->rx_ring
, 0, rx_ringsize
);
653 /* build Rx ring buffer */
654 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
656 mdp
->rx_skbuff
[i
] = NULL
;
657 skb
= netdev_alloc_skb(ndev
, mdp
->rx_buf_sz
);
658 mdp
->rx_skbuff
[i
] = skb
;
661 dma_map_single(&ndev
->dev
, skb
->data
, mdp
->rx_buf_sz
,
663 sh_eth_set_receive_align(skb
);
666 rxdesc
= &mdp
->rx_ring
[i
];
667 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
668 rxdesc
->status
= cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
670 /* The size of the buffer is 16 byte boundary. */
671 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
672 /* Rx descriptor address set */
674 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDLAR
);
675 if (sh_eth_is_gether(mdp
))
676 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDFAR
);
680 mdp
->dirty_rx
= (u32
) (i
- RX_RING_SIZE
);
682 /* Mark the last entry as wrapping the ring. */
683 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RDEL
);
685 memset(mdp
->tx_ring
, 0, tx_ringsize
);
687 /* build Tx ring buffer */
688 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
689 mdp
->tx_skbuff
[i
] = NULL
;
690 txdesc
= &mdp
->tx_ring
[i
];
691 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
692 txdesc
->buffer_length
= 0;
694 /* Tx descriptor address set */
695 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDLAR
);
696 if (sh_eth_is_gether(mdp
))
697 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDFAR
);
701 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
704 /* Get skb and descriptor buffer */
705 static int sh_eth_ring_init(struct net_device
*ndev
)
707 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
708 int rx_ringsize
, tx_ringsize
, ret
= 0;
711 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
712 * card needs room to do 8 byte alignment, +2 so we can reserve
713 * the first 2 bytes, and +16 gets room for the status word from the
716 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
717 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
719 mdp
->rx_buf_sz
+= NET_IP_ALIGN
;
721 /* Allocate RX and TX skb rings */
722 mdp
->rx_skbuff
= kmalloc(sizeof(*mdp
->rx_skbuff
) * RX_RING_SIZE
,
724 if (!mdp
->rx_skbuff
) {
725 dev_err(&ndev
->dev
, "Cannot allocate Rx skb\n");
730 mdp
->tx_skbuff
= kmalloc(sizeof(*mdp
->tx_skbuff
) * TX_RING_SIZE
,
732 if (!mdp
->tx_skbuff
) {
733 dev_err(&ndev
->dev
, "Cannot allocate Tx skb\n");
738 /* Allocate all Rx descriptors. */
739 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
740 mdp
->rx_ring
= dma_alloc_coherent(NULL
, rx_ringsize
, &mdp
->rx_desc_dma
,
744 dev_err(&ndev
->dev
, "Cannot allocate Rx Ring (size %d bytes)\n",
752 /* Allocate all Tx descriptors. */
753 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
754 mdp
->tx_ring
= dma_alloc_coherent(NULL
, tx_ringsize
, &mdp
->tx_desc_dma
,
757 dev_err(&ndev
->dev
, "Cannot allocate Tx Ring (size %d bytes)\n",
765 /* free DMA buffer */
766 dma_free_coherent(NULL
, rx_ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
769 /* Free Rx and Tx skb ring buffer */
770 sh_eth_ring_free(ndev
);
775 static int sh_eth_dev_init(struct net_device
*ndev
)
778 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
779 u_int32_t rx_int_var
, tx_int_var
;
785 /* Descriptor format */
786 sh_eth_ring_format(ndev
);
788 sh_eth_write(ndev
, mdp
->cd
->rpadir_value
, RPADIR
);
790 /* all sh_eth int mask */
791 sh_eth_write(ndev
, 0, EESIPR
);
793 #if defined(__LITTLE_ENDIAN__)
794 if (mdp
->cd
->hw_swap
)
795 sh_eth_write(ndev
, EDMR_EL
, EDMR
);
798 sh_eth_write(ndev
, 0, EDMR
);
801 sh_eth_write(ndev
, mdp
->cd
->fdr_value
, FDR
);
802 sh_eth_write(ndev
, 0, TFTR
);
804 /* Frame recv control */
805 sh_eth_write(ndev
, mdp
->cd
->rmcr_value
, RMCR
);
807 rx_int_var
= mdp
->rx_int_var
= DESC_I_RINT8
| DESC_I_RINT5
;
808 tx_int_var
= mdp
->tx_int_var
= DESC_I_TINT2
;
809 sh_eth_write(ndev
, rx_int_var
| tx_int_var
, TRSCER
);
812 sh_eth_write(ndev
, 0x800, BCULR
); /* Burst sycle set */
814 sh_eth_write(ndev
, mdp
->cd
->fcftr_value
, FCFTR
);
816 if (!mdp
->cd
->no_trimd
)
817 sh_eth_write(ndev
, 0, TRIMD
);
819 /* Recv frame limit set register */
820 sh_eth_write(ndev
, ndev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
+ ETH_FCS_LEN
,
823 sh_eth_write(ndev
, sh_eth_read(ndev
, EESR
), EESR
);
824 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
826 /* PAUSE Prohibition */
827 val
= (sh_eth_read(ndev
, ECMR
) & ECMR_DM
) |
828 ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) | ECMR_TE
| ECMR_RE
;
830 sh_eth_write(ndev
, val
, ECMR
);
832 if (mdp
->cd
->set_rate
)
833 mdp
->cd
->set_rate(ndev
);
835 /* E-MAC Status Register clear */
836 sh_eth_write(ndev
, mdp
->cd
->ecsr_value
, ECSR
);
838 /* E-MAC Interrupt Enable register */
839 sh_eth_write(ndev
, mdp
->cd
->ecsipr_value
, ECSIPR
);
841 /* Set MAC address */
842 update_mac_address(ndev
);
846 sh_eth_write(ndev
, APR_AP
, APR
);
848 sh_eth_write(ndev
, MPR_MP
, MPR
);
849 if (mdp
->cd
->tpauser
)
850 sh_eth_write(ndev
, TPAUSER_UNLIMITED
, TPAUSER
);
852 /* Setting the Rx mode will start the Rx process. */
853 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
855 netif_start_queue(ndev
);
860 /* free Tx skb function */
861 static int sh_eth_txfree(struct net_device
*ndev
)
863 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
864 struct sh_eth_txdesc
*txdesc
;
868 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
869 entry
= mdp
->dirty_tx
% TX_RING_SIZE
;
870 txdesc
= &mdp
->tx_ring
[entry
];
871 if (txdesc
->status
& cpu_to_edmac(mdp
, TD_TACT
))
873 /* Free the original skb. */
874 if (mdp
->tx_skbuff
[entry
]) {
875 dma_unmap_single(&ndev
->dev
, txdesc
->addr
,
876 txdesc
->buffer_length
, DMA_TO_DEVICE
);
877 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
878 mdp
->tx_skbuff
[entry
] = NULL
;
881 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
882 if (entry
>= TX_RING_SIZE
- 1)
883 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
885 ndev
->stats
.tx_packets
++;
886 ndev
->stats
.tx_bytes
+= txdesc
->buffer_length
;
891 /* Packet receive function */
892 static int sh_eth_rx(struct net_device
*ndev
)
894 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
895 struct sh_eth_rxdesc
*rxdesc
;
897 int entry
= mdp
->cur_rx
% RX_RING_SIZE
;
898 int boguscnt
= (mdp
->dirty_rx
+ RX_RING_SIZE
) - mdp
->cur_rx
;
903 rxdesc
= &mdp
->rx_ring
[entry
];
904 while (!(rxdesc
->status
& cpu_to_edmac(mdp
, RD_RACT
))) {
905 desc_status
= edmac_to_cpu(mdp
, rxdesc
->status
);
906 pkt_len
= rxdesc
->frame_length
;
911 if (!(desc_status
& RDFEND
))
912 ndev
->stats
.rx_length_errors
++;
914 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
915 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
916 ndev
->stats
.rx_errors
++;
917 if (desc_status
& RD_RFS1
)
918 ndev
->stats
.rx_crc_errors
++;
919 if (desc_status
& RD_RFS2
)
920 ndev
->stats
.rx_frame_errors
++;
921 if (desc_status
& RD_RFS3
)
922 ndev
->stats
.rx_length_errors
++;
923 if (desc_status
& RD_RFS4
)
924 ndev
->stats
.rx_length_errors
++;
925 if (desc_status
& RD_RFS6
)
926 ndev
->stats
.rx_missed_errors
++;
927 if (desc_status
& RD_RFS10
)
928 ndev
->stats
.rx_over_errors
++;
930 if (!mdp
->cd
->hw_swap
)
932 phys_to_virt(ALIGN(rxdesc
->addr
, 4)),
934 skb
= mdp
->rx_skbuff
[entry
];
935 mdp
->rx_skbuff
[entry
] = NULL
;
937 skb_reserve(skb
, NET_IP_ALIGN
);
938 skb_put(skb
, pkt_len
);
939 skb
->protocol
= eth_type_trans(skb
, ndev
);
941 ndev
->stats
.rx_packets
++;
942 ndev
->stats
.rx_bytes
+= pkt_len
;
944 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RACT
);
945 entry
= (++mdp
->cur_rx
) % RX_RING_SIZE
;
946 rxdesc
= &mdp
->rx_ring
[entry
];
949 /* Refill the Rx ring buffers. */
950 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
951 entry
= mdp
->dirty_rx
% RX_RING_SIZE
;
952 rxdesc
= &mdp
->rx_ring
[entry
];
953 /* The size of the buffer is 16 byte boundary. */
954 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
956 if (mdp
->rx_skbuff
[entry
] == NULL
) {
957 skb
= netdev_alloc_skb(ndev
, mdp
->rx_buf_sz
);
958 mdp
->rx_skbuff
[entry
] = skb
;
960 break; /* Better luck next round. */
961 dma_map_single(&ndev
->dev
, skb
->data
, mdp
->rx_buf_sz
,
963 sh_eth_set_receive_align(skb
);
965 skb_checksum_none_assert(skb
);
966 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
968 if (entry
>= RX_RING_SIZE
- 1)
970 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
| RD_RDEL
);
973 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
976 /* Restart Rx engine if stopped. */
977 /* If we don't need to check status, don't. -KDU */
978 if (!(sh_eth_read(ndev
, EDRRR
) & EDRRR_R
))
979 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
984 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
)
986 /* disable tx and rx */
987 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) &
988 ~(ECMR_RE
| ECMR_TE
), ECMR
);
991 static void sh_eth_rcv_snd_enable(struct net_device
*ndev
)
993 /* enable tx and rx */
994 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) |
995 (ECMR_RE
| ECMR_TE
), ECMR
);
998 /* error control function */
999 static void sh_eth_error(struct net_device
*ndev
, int intr_status
)
1001 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1006 if (intr_status
& EESR_ECI
) {
1007 felic_stat
= sh_eth_read(ndev
, ECSR
);
1008 sh_eth_write(ndev
, felic_stat
, ECSR
); /* clear int */
1009 if (felic_stat
& ECSR_ICD
)
1010 ndev
->stats
.tx_carrier_errors
++;
1011 if (felic_stat
& ECSR_LCHNG
) {
1013 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
) {
1014 if (mdp
->link
== PHY_DOWN
)
1017 link_stat
= PHY_ST_LINK
;
1019 link_stat
= (sh_eth_read(ndev
, PSR
));
1020 if (mdp
->ether_link_active_low
)
1021 link_stat
= ~link_stat
;
1023 if (!(link_stat
& PHY_ST_LINK
))
1024 sh_eth_rcv_snd_disable(ndev
);
1027 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) &
1028 ~DMAC_M_ECI
, EESIPR
);
1030 sh_eth_write(ndev
, sh_eth_read(ndev
, ECSR
),
1032 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) |
1033 DMAC_M_ECI
, EESIPR
);
1034 /* enable tx and rx */
1035 sh_eth_rcv_snd_enable(ndev
);
1040 if (intr_status
& EESR_TWB
) {
1041 /* Write buck end. unused write back interrupt */
1042 if (intr_status
& EESR_TABT
) /* Transmit Abort int */
1043 ndev
->stats
.tx_aborted_errors
++;
1044 if (netif_msg_tx_err(mdp
))
1045 dev_err(&ndev
->dev
, "Transmit Abort\n");
1048 if (intr_status
& EESR_RABT
) {
1049 /* Receive Abort int */
1050 if (intr_status
& EESR_RFRMER
) {
1051 /* Receive Frame Overflow int */
1052 ndev
->stats
.rx_frame_errors
++;
1053 if (netif_msg_rx_err(mdp
))
1054 dev_err(&ndev
->dev
, "Receive Abort\n");
1058 if (intr_status
& EESR_TDE
) {
1059 /* Transmit Descriptor Empty int */
1060 ndev
->stats
.tx_fifo_errors
++;
1061 if (netif_msg_tx_err(mdp
))
1062 dev_err(&ndev
->dev
, "Transmit Descriptor Empty\n");
1065 if (intr_status
& EESR_TFE
) {
1066 /* FIFO under flow */
1067 ndev
->stats
.tx_fifo_errors
++;
1068 if (netif_msg_tx_err(mdp
))
1069 dev_err(&ndev
->dev
, "Transmit FIFO Under flow\n");
1072 if (intr_status
& EESR_RDE
) {
1073 /* Receive Descriptor Empty int */
1074 ndev
->stats
.rx_over_errors
++;
1076 if (sh_eth_read(ndev
, EDRRR
) ^ EDRRR_R
)
1077 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1078 if (netif_msg_rx_err(mdp
))
1079 dev_err(&ndev
->dev
, "Receive Descriptor Empty\n");
1082 if (intr_status
& EESR_RFE
) {
1083 /* Receive FIFO Overflow int */
1084 ndev
->stats
.rx_fifo_errors
++;
1085 if (netif_msg_rx_err(mdp
))
1086 dev_err(&ndev
->dev
, "Receive FIFO Overflow\n");
1089 if (!mdp
->cd
->no_ade
&& (intr_status
& EESR_ADE
)) {
1091 ndev
->stats
.tx_fifo_errors
++;
1092 if (netif_msg_tx_err(mdp
))
1093 dev_err(&ndev
->dev
, "Address Error\n");
1096 mask
= EESR_TWB
| EESR_TABT
| EESR_ADE
| EESR_TDE
| EESR_TFE
;
1097 if (mdp
->cd
->no_ade
)
1099 if (intr_status
& mask
) {
1101 u32 edtrr
= sh_eth_read(ndev
, EDTRR
);
1103 dev_err(&ndev
->dev
, "TX error. status=%8.8x cur_tx=%8.8x ",
1104 intr_status
, mdp
->cur_tx
);
1105 dev_err(&ndev
->dev
, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1106 mdp
->dirty_tx
, (u32
) ndev
->state
, edtrr
);
1107 /* dirty buffer free */
1108 sh_eth_txfree(ndev
);
1111 if (edtrr
^ sh_eth_get_edtrr_trns(mdp
)) {
1113 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1116 netif_wake_queue(ndev
);
1120 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
1122 struct net_device
*ndev
= netdev
;
1123 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1124 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
1125 irqreturn_t ret
= IRQ_NONE
;
1126 u32 intr_status
= 0;
1128 spin_lock(&mdp
->lock
);
1130 /* Get interrpt stat */
1131 intr_status
= sh_eth_read(ndev
, EESR
);
1132 /* Clear interrupt */
1133 if (intr_status
& (EESR_FRC
| EESR_RMAF
| EESR_RRF
|
1134 EESR_RTLF
| EESR_RTSF
| EESR_PRE
| EESR_CERF
|
1135 cd
->tx_check
| cd
->eesr_err_check
)) {
1136 sh_eth_write(ndev
, intr_status
, EESR
);
1141 if (intr_status
& (EESR_FRC
| /* Frame recv*/
1142 EESR_RMAF
| /* Multi cast address recv*/
1143 EESR_RRF
| /* Bit frame recv */
1144 EESR_RTLF
| /* Long frame recv*/
1145 EESR_RTSF
| /* short frame recv */
1146 EESR_PRE
| /* PHY-LSI recv error */
1147 EESR_CERF
)){ /* recv frame CRC error */
1152 if (intr_status
& cd
->tx_check
) {
1153 sh_eth_txfree(ndev
);
1154 netif_wake_queue(ndev
);
1157 if (intr_status
& cd
->eesr_err_check
)
1158 sh_eth_error(ndev
, intr_status
);
1161 spin_unlock(&mdp
->lock
);
1166 static void sh_eth_timer(unsigned long data
)
1168 struct net_device
*ndev
= (struct net_device
*)data
;
1169 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1171 mod_timer(&mdp
->timer
, jiffies
+ (10 * HZ
));
1174 /* PHY state control function */
1175 static void sh_eth_adjust_link(struct net_device
*ndev
)
1177 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1178 struct phy_device
*phydev
= mdp
->phydev
;
1181 if (phydev
->link
!= PHY_DOWN
) {
1182 if (phydev
->duplex
!= mdp
->duplex
) {
1184 mdp
->duplex
= phydev
->duplex
;
1185 if (mdp
->cd
->set_duplex
)
1186 mdp
->cd
->set_duplex(ndev
);
1189 if (phydev
->speed
!= mdp
->speed
) {
1191 mdp
->speed
= phydev
->speed
;
1192 if (mdp
->cd
->set_rate
)
1193 mdp
->cd
->set_rate(ndev
);
1195 if (mdp
->link
== PHY_DOWN
) {
1197 (sh_eth_read(ndev
, ECMR
) & ~ECMR_TXF
), ECMR
);
1199 mdp
->link
= phydev
->link
;
1201 } else if (mdp
->link
) {
1203 mdp
->link
= PHY_DOWN
;
1208 if (new_state
&& netif_msg_link(mdp
))
1209 phy_print_status(phydev
);
1212 /* PHY init function */
1213 static int sh_eth_phy_init(struct net_device
*ndev
)
1215 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1216 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1217 struct phy_device
*phydev
= NULL
;
1219 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
,
1220 mdp
->mii_bus
->id
, mdp
->phy_id
);
1222 mdp
->link
= PHY_DOWN
;
1226 /* Try connect to PHY */
1227 phydev
= phy_connect(ndev
, phy_id
, sh_eth_adjust_link
,
1228 0, mdp
->phy_interface
);
1229 if (IS_ERR(phydev
)) {
1230 dev_err(&ndev
->dev
, "phy_connect failed\n");
1231 return PTR_ERR(phydev
);
1234 dev_info(&ndev
->dev
, "attached phy %i to driver %s\n",
1235 phydev
->addr
, phydev
->drv
->name
);
1237 mdp
->phydev
= phydev
;
1242 /* PHY control start function */
1243 static int sh_eth_phy_start(struct net_device
*ndev
)
1245 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1248 ret
= sh_eth_phy_init(ndev
);
1252 /* reset phy - this also wakes it from PDOWN */
1253 phy_write(mdp
->phydev
, MII_BMCR
, BMCR_RESET
);
1254 phy_start(mdp
->phydev
);
1259 static int sh_eth_get_settings(struct net_device
*ndev
,
1260 struct ethtool_cmd
*ecmd
)
1262 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1263 unsigned long flags
;
1266 spin_lock_irqsave(&mdp
->lock
, flags
);
1267 ret
= phy_ethtool_gset(mdp
->phydev
, ecmd
);
1268 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1273 static int sh_eth_set_settings(struct net_device
*ndev
,
1274 struct ethtool_cmd
*ecmd
)
1276 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1277 unsigned long flags
;
1280 spin_lock_irqsave(&mdp
->lock
, flags
);
1282 /* disable tx and rx */
1283 sh_eth_rcv_snd_disable(ndev
);
1285 ret
= phy_ethtool_sset(mdp
->phydev
, ecmd
);
1289 if (ecmd
->duplex
== DUPLEX_FULL
)
1294 if (mdp
->cd
->set_duplex
)
1295 mdp
->cd
->set_duplex(ndev
);
1300 /* enable tx and rx */
1301 sh_eth_rcv_snd_enable(ndev
);
1303 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1308 static int sh_eth_nway_reset(struct net_device
*ndev
)
1310 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1311 unsigned long flags
;
1314 spin_lock_irqsave(&mdp
->lock
, flags
);
1315 ret
= phy_start_aneg(mdp
->phydev
);
1316 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1321 static u32
sh_eth_get_msglevel(struct net_device
*ndev
)
1323 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1324 return mdp
->msg_enable
;
1327 static void sh_eth_set_msglevel(struct net_device
*ndev
, u32 value
)
1329 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1330 mdp
->msg_enable
= value
;
1333 static const char sh_eth_gstrings_stats
[][ETH_GSTRING_LEN
] = {
1334 "rx_current", "tx_current",
1335 "rx_dirty", "tx_dirty",
1337 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1339 static int sh_eth_get_sset_count(struct net_device
*netdev
, int sset
)
1343 return SH_ETH_STATS_LEN
;
1349 static void sh_eth_get_ethtool_stats(struct net_device
*ndev
,
1350 struct ethtool_stats
*stats
, u64
*data
)
1352 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1355 /* device-specific stats */
1356 data
[i
++] = mdp
->cur_rx
;
1357 data
[i
++] = mdp
->cur_tx
;
1358 data
[i
++] = mdp
->dirty_rx
;
1359 data
[i
++] = mdp
->dirty_tx
;
1362 static void sh_eth_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1364 switch (stringset
) {
1366 memcpy(data
, *sh_eth_gstrings_stats
,
1367 sizeof(sh_eth_gstrings_stats
));
1372 static const struct ethtool_ops sh_eth_ethtool_ops
= {
1373 .get_settings
= sh_eth_get_settings
,
1374 .set_settings
= sh_eth_set_settings
,
1375 .nway_reset
= sh_eth_nway_reset
,
1376 .get_msglevel
= sh_eth_get_msglevel
,
1377 .set_msglevel
= sh_eth_set_msglevel
,
1378 .get_link
= ethtool_op_get_link
,
1379 .get_strings
= sh_eth_get_strings
,
1380 .get_ethtool_stats
= sh_eth_get_ethtool_stats
,
1381 .get_sset_count
= sh_eth_get_sset_count
,
1384 /* network device open function */
1385 static int sh_eth_open(struct net_device
*ndev
)
1388 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1390 pm_runtime_get_sync(&mdp
->pdev
->dev
);
1392 ret
= request_irq(ndev
->irq
, sh_eth_interrupt
,
1393 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1394 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1395 defined(CONFIG_CPU_SUBTYPE_SH7757)
1402 dev_err(&ndev
->dev
, "Can not assign IRQ number\n");
1406 /* Descriptor set */
1407 ret
= sh_eth_ring_init(ndev
);
1412 ret
= sh_eth_dev_init(ndev
);
1416 /* PHY control start*/
1417 ret
= sh_eth_phy_start(ndev
);
1421 /* Set the timer to check for link beat. */
1422 init_timer(&mdp
->timer
);
1423 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
1424 setup_timer(&mdp
->timer
, sh_eth_timer
, (unsigned long)ndev
);
1429 free_irq(ndev
->irq
, ndev
);
1430 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1434 /* Timeout function */
1435 static void sh_eth_tx_timeout(struct net_device
*ndev
)
1437 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1438 struct sh_eth_rxdesc
*rxdesc
;
1441 netif_stop_queue(ndev
);
1443 if (netif_msg_timer(mdp
))
1444 dev_err(&ndev
->dev
, "%s: transmit timed out, status %8.8x,"
1445 " resetting...\n", ndev
->name
, (int)sh_eth_read(ndev
, EESR
));
1447 /* tx_errors count up */
1448 ndev
->stats
.tx_errors
++;
1451 del_timer_sync(&mdp
->timer
);
1453 /* Free all the skbuffs in the Rx queue. */
1454 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1455 rxdesc
= &mdp
->rx_ring
[i
];
1457 rxdesc
->addr
= 0xBADF00D0;
1458 if (mdp
->rx_skbuff
[i
])
1459 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
1460 mdp
->rx_skbuff
[i
] = NULL
;
1462 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1463 if (mdp
->tx_skbuff
[i
])
1464 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
1465 mdp
->tx_skbuff
[i
] = NULL
;
1469 sh_eth_dev_init(ndev
);
1472 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
1473 add_timer(&mdp
->timer
);
1476 /* Packet transmit function */
1477 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1479 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1480 struct sh_eth_txdesc
*txdesc
;
1482 unsigned long flags
;
1484 spin_lock_irqsave(&mdp
->lock
, flags
);
1485 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (TX_RING_SIZE
- 4)) {
1486 if (!sh_eth_txfree(ndev
)) {
1487 if (netif_msg_tx_queued(mdp
))
1488 dev_warn(&ndev
->dev
, "TxFD exhausted.\n");
1489 netif_stop_queue(ndev
);
1490 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1491 return NETDEV_TX_BUSY
;
1494 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1496 entry
= mdp
->cur_tx
% TX_RING_SIZE
;
1497 mdp
->tx_skbuff
[entry
] = skb
;
1498 txdesc
= &mdp
->tx_ring
[entry
];
1500 if (!mdp
->cd
->hw_swap
)
1501 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc
->addr
, 4)),
1503 txdesc
->addr
= dma_map_single(&ndev
->dev
, skb
->data
, skb
->len
,
1505 if (skb
->len
< ETHERSMALL
)
1506 txdesc
->buffer_length
= ETHERSMALL
;
1508 txdesc
->buffer_length
= skb
->len
;
1510 if (entry
>= TX_RING_SIZE
- 1)
1511 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
| TD_TDLE
);
1513 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
);
1517 if (!(sh_eth_read(ndev
, EDTRR
) & sh_eth_get_edtrr_trns(mdp
)))
1518 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1520 return NETDEV_TX_OK
;
1523 /* device close function */
1524 static int sh_eth_close(struct net_device
*ndev
)
1526 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1529 netif_stop_queue(ndev
);
1531 /* Disable interrupts by clearing the interrupt mask. */
1532 sh_eth_write(ndev
, 0x0000, EESIPR
);
1534 /* Stop the chip's Tx and Rx processes. */
1535 sh_eth_write(ndev
, 0, EDTRR
);
1536 sh_eth_write(ndev
, 0, EDRRR
);
1538 /* PHY Disconnect */
1540 phy_stop(mdp
->phydev
);
1541 phy_disconnect(mdp
->phydev
);
1544 free_irq(ndev
->irq
, ndev
);
1546 del_timer_sync(&mdp
->timer
);
1548 /* Free all the skbuffs in the Rx queue. */
1549 sh_eth_ring_free(ndev
);
1551 /* free DMA buffer */
1552 ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
1553 dma_free_coherent(NULL
, ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
1555 /* free DMA buffer */
1556 ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
1557 dma_free_coherent(NULL
, ringsize
, mdp
->tx_ring
, mdp
->tx_desc_dma
);
1559 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1564 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
1566 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1568 pm_runtime_get_sync(&mdp
->pdev
->dev
);
1570 ndev
->stats
.tx_dropped
+= sh_eth_read(ndev
, TROCR
);
1571 sh_eth_write(ndev
, 0, TROCR
); /* (write clear) */
1572 ndev
->stats
.collisions
+= sh_eth_read(ndev
, CDCR
);
1573 sh_eth_write(ndev
, 0, CDCR
); /* (write clear) */
1574 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, LCCR
);
1575 sh_eth_write(ndev
, 0, LCCR
); /* (write clear) */
1576 if (sh_eth_is_gether(mdp
)) {
1577 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CERCR
);
1578 sh_eth_write(ndev
, 0, CERCR
); /* (write clear) */
1579 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CEECR
);
1580 sh_eth_write(ndev
, 0, CEECR
); /* (write clear) */
1582 ndev
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CNDCR
);
1583 sh_eth_write(ndev
, 0, CNDCR
); /* (write clear) */
1585 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1587 return &ndev
->stats
;
1590 /* ioctl to device function */
1591 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
,
1594 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1595 struct phy_device
*phydev
= mdp
->phydev
;
1597 if (!netif_running(ndev
))
1603 return phy_mii_ioctl(phydev
, rq
, cmd
);
1606 #if defined(SH_ETH_HAS_TSU)
1607 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
1608 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private
*mdp
,
1611 return sh_eth_tsu_get_offset(mdp
, TSU_POST1
) + (entry
/ 8 * 4);
1614 static u32
sh_eth_tsu_get_post_mask(int entry
)
1616 return 0x0f << (28 - ((entry
% 8) * 4));
1619 static u32
sh_eth_tsu_get_post_bit(struct sh_eth_private
*mdp
, int entry
)
1621 return (0x08 >> (mdp
->port
<< 1)) << (28 - ((entry
% 8) * 4));
1624 static void sh_eth_tsu_enable_cam_entry_post(struct net_device
*ndev
,
1627 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1631 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
1632 tmp
= ioread32(reg_offset
);
1633 iowrite32(tmp
| sh_eth_tsu_get_post_bit(mdp
, entry
), reg_offset
);
1636 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device
*ndev
,
1639 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1640 u32 post_mask
, ref_mask
, tmp
;
1643 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
1644 post_mask
= sh_eth_tsu_get_post_mask(entry
);
1645 ref_mask
= sh_eth_tsu_get_post_bit(mdp
, entry
) & ~post_mask
;
1647 tmp
= ioread32(reg_offset
);
1648 iowrite32(tmp
& ~post_mask
, reg_offset
);
1650 /* If other port enables, the function returns "true" */
1651 return tmp
& ref_mask
;
1654 static int sh_eth_tsu_busy(struct net_device
*ndev
)
1656 int timeout
= SH_ETH_TSU_TIMEOUT_MS
* 100;
1657 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1659 while ((sh_eth_tsu_read(mdp
, TSU_ADSBSY
) & TSU_ADSBSY_0
)) {
1663 dev_err(&ndev
->dev
, "%s: timeout\n", __func__
);
1671 static int sh_eth_tsu_write_entry(struct net_device
*ndev
, void *reg
,
1676 val
= addr
[0] << 24 | addr
[1] << 16 | addr
[2] << 8 | addr
[3];
1677 iowrite32(val
, reg
);
1678 if (sh_eth_tsu_busy(ndev
) < 0)
1681 val
= addr
[4] << 8 | addr
[5];
1682 iowrite32(val
, reg
+ 4);
1683 if (sh_eth_tsu_busy(ndev
) < 0)
1689 static void sh_eth_tsu_read_entry(void *reg
, u8
*addr
)
1693 val
= ioread32(reg
);
1694 addr
[0] = (val
>> 24) & 0xff;
1695 addr
[1] = (val
>> 16) & 0xff;
1696 addr
[2] = (val
>> 8) & 0xff;
1697 addr
[3] = val
& 0xff;
1698 val
= ioread32(reg
+ 4);
1699 addr
[4] = (val
>> 8) & 0xff;
1700 addr
[5] = val
& 0xff;
1704 static int sh_eth_tsu_find_entry(struct net_device
*ndev
, const u8
*addr
)
1706 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1707 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
1709 u8 c_addr
[ETH_ALEN
];
1711 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
1712 sh_eth_tsu_read_entry(reg_offset
, c_addr
);
1713 if (memcmp(addr
, c_addr
, ETH_ALEN
) == 0)
1720 static int sh_eth_tsu_find_empty(struct net_device
*ndev
)
1725 memset(blank
, 0, sizeof(blank
));
1726 entry
= sh_eth_tsu_find_entry(ndev
, blank
);
1727 return (entry
< 0) ? -ENOMEM
: entry
;
1730 static int sh_eth_tsu_disable_cam_entry_table(struct net_device
*ndev
,
1733 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1734 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
1738 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) &
1739 ~(1 << (31 - entry
)), TSU_TEN
);
1741 memset(blank
, 0, sizeof(blank
));
1742 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ entry
* 8, blank
);
1748 static int sh_eth_tsu_add_entry(struct net_device
*ndev
, const u8
*addr
)
1750 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1751 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
1757 i
= sh_eth_tsu_find_entry(ndev
, addr
);
1759 /* No entry found, create one */
1760 i
= sh_eth_tsu_find_empty(ndev
);
1763 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ i
* 8, addr
);
1767 /* Enable the entry */
1768 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) |
1769 (1 << (31 - i
)), TSU_TEN
);
1772 /* Entry found or created, enable POST */
1773 sh_eth_tsu_enable_cam_entry_post(ndev
, i
);
1778 static int sh_eth_tsu_del_entry(struct net_device
*ndev
, const u8
*addr
)
1780 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1786 i
= sh_eth_tsu_find_entry(ndev
, addr
);
1789 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
1792 /* Disable the entry if both ports was disabled */
1793 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
1801 static int sh_eth_tsu_purge_all(struct net_device
*ndev
)
1803 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1806 if (unlikely(!mdp
->cd
->tsu
))
1809 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++) {
1810 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
1813 /* Disable the entry if both ports was disabled */
1814 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
1822 static void sh_eth_tsu_purge_mcast(struct net_device
*ndev
)
1824 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1826 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
1829 if (unlikely(!mdp
->cd
->tsu
))
1832 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
1833 sh_eth_tsu_read_entry(reg_offset
, addr
);
1834 if (is_multicast_ether_addr(addr
))
1835 sh_eth_tsu_del_entry(ndev
, addr
);
1839 /* Multicast reception directions set */
1840 static void sh_eth_set_multicast_list(struct net_device
*ndev
)
1842 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1845 unsigned long flags
;
1847 spin_lock_irqsave(&mdp
->lock
, flags
);
1849 * Initial condition is MCT = 1, PRM = 0.
1850 * Depending on ndev->flags, set PRM or clear MCT
1852 ecmr_bits
= (sh_eth_read(ndev
, ECMR
) & ~ECMR_PRM
) | ECMR_MCT
;
1854 if (!(ndev
->flags
& IFF_MULTICAST
)) {
1855 sh_eth_tsu_purge_mcast(ndev
);
1858 if (ndev
->flags
& IFF_ALLMULTI
) {
1859 sh_eth_tsu_purge_mcast(ndev
);
1860 ecmr_bits
&= ~ECMR_MCT
;
1864 if (ndev
->flags
& IFF_PROMISC
) {
1865 sh_eth_tsu_purge_all(ndev
);
1866 ecmr_bits
= (ecmr_bits
& ~ECMR_MCT
) | ECMR_PRM
;
1867 } else if (mdp
->cd
->tsu
) {
1868 struct netdev_hw_addr
*ha
;
1869 netdev_for_each_mc_addr(ha
, ndev
) {
1870 if (mcast_all
&& is_multicast_ether_addr(ha
->addr
))
1873 if (sh_eth_tsu_add_entry(ndev
, ha
->addr
) < 0) {
1875 sh_eth_tsu_purge_mcast(ndev
);
1876 ecmr_bits
&= ~ECMR_MCT
;
1882 /* Normal, unicast/broadcast-only mode. */
1883 ecmr_bits
= (ecmr_bits
& ~ECMR_PRM
) | ECMR_MCT
;
1886 /* update the ethernet mode */
1887 sh_eth_write(ndev
, ecmr_bits
, ECMR
);
1889 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1891 #endif /* SH_ETH_HAS_TSU */
1893 /* SuperH's TSU register init function */
1894 static void sh_eth_tsu_init(struct sh_eth_private
*mdp
)
1896 sh_eth_tsu_write(mdp
, 0, TSU_FWEN0
); /* Disable forward(0->1) */
1897 sh_eth_tsu_write(mdp
, 0, TSU_FWEN1
); /* Disable forward(1->0) */
1898 sh_eth_tsu_write(mdp
, 0, TSU_FCM
); /* forward fifo 3k-3k */
1899 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL0
);
1900 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL1
);
1901 sh_eth_tsu_write(mdp
, 0, TSU_PRISL0
);
1902 sh_eth_tsu_write(mdp
, 0, TSU_PRISL1
);
1903 sh_eth_tsu_write(mdp
, 0, TSU_FWSL0
);
1904 sh_eth_tsu_write(mdp
, 0, TSU_FWSL1
);
1905 sh_eth_tsu_write(mdp
, TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, TSU_FWSLC
);
1906 if (sh_eth_is_gether(mdp
)) {
1907 sh_eth_tsu_write(mdp
, 0, TSU_QTAG0
); /* Disable QTAG(0->1) */
1908 sh_eth_tsu_write(mdp
, 0, TSU_QTAG1
); /* Disable QTAG(1->0) */
1910 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM0
); /* Disable QTAG(0->1) */
1911 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM1
); /* Disable QTAG(1->0) */
1913 sh_eth_tsu_write(mdp
, 0, TSU_FWSR
); /* all interrupt status clear */
1914 sh_eth_tsu_write(mdp
, 0, TSU_FWINMK
); /* Disable all interrupt */
1915 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
1916 sh_eth_tsu_write(mdp
, 0, TSU_POST1
); /* Disable CAM entry [ 0- 7] */
1917 sh_eth_tsu_write(mdp
, 0, TSU_POST2
); /* Disable CAM entry [ 8-15] */
1918 sh_eth_tsu_write(mdp
, 0, TSU_POST3
); /* Disable CAM entry [16-23] */
1919 sh_eth_tsu_write(mdp
, 0, TSU_POST4
); /* Disable CAM entry [24-31] */
1922 /* MDIO bus release function */
1923 static int sh_mdio_release(struct net_device
*ndev
)
1925 struct mii_bus
*bus
= dev_get_drvdata(&ndev
->dev
);
1927 /* unregister mdio bus */
1928 mdiobus_unregister(bus
);
1930 /* remove mdio bus info from net_device */
1931 dev_set_drvdata(&ndev
->dev
, NULL
);
1933 /* free interrupts memory */
1936 /* free bitbang info */
1937 free_mdio_bitbang(bus
);
1942 /* MDIO bus init function */
1943 static int sh_mdio_init(struct net_device
*ndev
, int id
,
1944 struct sh_eth_plat_data
*pd
)
1947 struct bb_info
*bitbang
;
1948 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1950 /* create bit control struct for PHY */
1951 bitbang
= kzalloc(sizeof(struct bb_info
), GFP_KERNEL
);
1958 bitbang
->addr
= mdp
->addr
+ mdp
->reg_offset
[PIR
];
1959 bitbang
->set_gate
= pd
->set_mdio_gate
;
1960 bitbang
->mdi_msk
= 0x08;
1961 bitbang
->mdo_msk
= 0x04;
1962 bitbang
->mmd_msk
= 0x02;/* MMD */
1963 bitbang
->mdc_msk
= 0x01;
1964 bitbang
->ctrl
.ops
= &bb_ops
;
1966 /* MII controller setting */
1967 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
1968 if (!mdp
->mii_bus
) {
1970 goto out_free_bitbang
;
1973 /* Hook up MII support for ethtool */
1974 mdp
->mii_bus
->name
= "sh_mii";
1975 mdp
->mii_bus
->parent
= &ndev
->dev
;
1976 snprintf(mdp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
1977 mdp
->pdev
->name
, id
);
1980 mdp
->mii_bus
->irq
= kmalloc(sizeof(int)*PHY_MAX_ADDR
, GFP_KERNEL
);
1981 if (!mdp
->mii_bus
->irq
) {
1986 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1987 mdp
->mii_bus
->irq
[i
] = PHY_POLL
;
1989 /* regist mdio bus */
1990 ret
= mdiobus_register(mdp
->mii_bus
);
1994 dev_set_drvdata(&ndev
->dev
, mdp
->mii_bus
);
1999 kfree(mdp
->mii_bus
->irq
);
2002 free_mdio_bitbang(mdp
->mii_bus
);
2011 static const u16
*sh_eth_get_register_offset(int register_type
)
2013 const u16
*reg_offset
= NULL
;
2015 switch (register_type
) {
2016 case SH_ETH_REG_GIGABIT
:
2017 reg_offset
= sh_eth_offset_gigabit
;
2019 case SH_ETH_REG_FAST_SH4
:
2020 reg_offset
= sh_eth_offset_fast_sh4
;
2022 case SH_ETH_REG_FAST_SH3_SH2
:
2023 reg_offset
= sh_eth_offset_fast_sh3_sh2
;
2026 printk(KERN_ERR
"Unknown register type (%d)\n", register_type
);
2033 static const struct net_device_ops sh_eth_netdev_ops
= {
2034 .ndo_open
= sh_eth_open
,
2035 .ndo_stop
= sh_eth_close
,
2036 .ndo_start_xmit
= sh_eth_start_xmit
,
2037 .ndo_get_stats
= sh_eth_get_stats
,
2038 #if defined(SH_ETH_HAS_TSU)
2039 .ndo_set_rx_mode
= sh_eth_set_multicast_list
,
2041 .ndo_tx_timeout
= sh_eth_tx_timeout
,
2042 .ndo_do_ioctl
= sh_eth_do_ioctl
,
2043 .ndo_validate_addr
= eth_validate_addr
,
2044 .ndo_set_mac_address
= eth_mac_addr
,
2045 .ndo_change_mtu
= eth_change_mtu
,
2048 static int sh_eth_drv_probe(struct platform_device
*pdev
)
2051 struct resource
*res
;
2052 struct net_device
*ndev
= NULL
;
2053 struct sh_eth_private
*mdp
= NULL
;
2054 struct sh_eth_plat_data
*pd
;
2057 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2058 if (unlikely(res
== NULL
)) {
2059 dev_err(&pdev
->dev
, "invalid resource\n");
2064 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
2070 /* The sh Ether-specific entries in the device structure. */
2071 ndev
->base_addr
= res
->start
;
2077 ret
= platform_get_irq(pdev
, 0);
2084 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2086 /* Fill in the fields of the device structure with ethernet values. */
2089 mdp
= netdev_priv(ndev
);
2090 mdp
->addr
= ioremap(res
->start
, resource_size(res
));
2091 if (mdp
->addr
== NULL
) {
2093 dev_err(&pdev
->dev
, "ioremap failed.\n");
2097 spin_lock_init(&mdp
->lock
);
2099 pm_runtime_enable(&pdev
->dev
);
2100 pm_runtime_resume(&pdev
->dev
);
2102 pd
= (struct sh_eth_plat_data
*)(pdev
->dev
.platform_data
);
2104 mdp
->phy_id
= pd
->phy
;
2105 mdp
->phy_interface
= pd
->phy_interface
;
2107 mdp
->edmac_endian
= pd
->edmac_endian
;
2108 mdp
->no_ether_link
= pd
->no_ether_link
;
2109 mdp
->ether_link_active_low
= pd
->ether_link_active_low
;
2110 mdp
->reg_offset
= sh_eth_get_register_offset(pd
->register_type
);
2113 #if defined(SH_ETH_HAS_BOTH_MODULES)
2114 mdp
->cd
= sh_eth_get_cpu_data(mdp
);
2116 mdp
->cd
= &sh_eth_my_cpu_data
;
2118 sh_eth_set_default_cpu_data(mdp
->cd
);
2121 ndev
->netdev_ops
= &sh_eth_netdev_ops
;
2122 SET_ETHTOOL_OPS(ndev
, &sh_eth_ethtool_ops
);
2123 ndev
->watchdog_timeo
= TX_TIMEOUT
;
2125 /* debug message level */
2126 mdp
->msg_enable
= SH_ETH_DEF_MSG_ENABLE
;
2127 mdp
->post_rx
= POST_RX
>> (devno
<< 1);
2128 mdp
->post_fw
= POST_FW
>> (devno
<< 1);
2130 /* read and set MAC address */
2131 read_mac_address(ndev
, pd
->mac_addr
);
2133 /* ioremap the TSU registers */
2135 struct resource
*rtsu
;
2136 rtsu
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2138 dev_err(&pdev
->dev
, "Not found TSU resource\n");
2141 mdp
->tsu_addr
= ioremap(rtsu
->start
,
2142 resource_size(rtsu
));
2143 mdp
->port
= devno
% 2;
2146 /* initialize first or needed device */
2147 if (!devno
|| pd
->needs_init
) {
2148 if (mdp
->cd
->chip_reset
)
2149 mdp
->cd
->chip_reset(ndev
);
2152 /* TSU init (Init only)*/
2153 sh_eth_tsu_init(mdp
);
2157 /* network device register */
2158 ret
= register_netdev(ndev
);
2163 ret
= sh_mdio_init(ndev
, pdev
->id
, pd
);
2165 goto out_unregister
;
2167 /* print device information */
2168 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2169 (u32
)ndev
->base_addr
, ndev
->dev_addr
, ndev
->irq
);
2171 platform_set_drvdata(pdev
, ndev
);
2176 unregister_netdev(ndev
);
2180 if (mdp
&& mdp
->addr
)
2182 if (mdp
&& mdp
->tsu_addr
)
2183 iounmap(mdp
->tsu_addr
);
2191 static int sh_eth_drv_remove(struct platform_device
*pdev
)
2193 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2194 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2197 iounmap(mdp
->tsu_addr
);
2198 sh_mdio_release(ndev
);
2199 unregister_netdev(ndev
);
2200 pm_runtime_disable(&pdev
->dev
);
2203 platform_set_drvdata(pdev
, NULL
);
2208 static int sh_eth_runtime_nop(struct device
*dev
)
2211 * Runtime PM callback shared between ->runtime_suspend()
2212 * and ->runtime_resume(). Simply returns success.
2214 * This driver re-initializes all registers after
2215 * pm_runtime_get_sync() anyway so there is no need
2216 * to save and restore registers here.
2221 static struct dev_pm_ops sh_eth_dev_pm_ops
= {
2222 .runtime_suspend
= sh_eth_runtime_nop
,
2223 .runtime_resume
= sh_eth_runtime_nop
,
2226 static struct platform_driver sh_eth_driver
= {
2227 .probe
= sh_eth_drv_probe
,
2228 .remove
= sh_eth_drv_remove
,
2231 .pm
= &sh_eth_dev_pm_ops
,
2235 module_platform_driver(sh_eth_driver
);
2237 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2238 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2239 MODULE_LICENSE("GPL v2");