projects / deliverable / linux.git / blob
? search:


cf0bc316cb60a9c56423d720ba36f011c11ee991
[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.c
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2012 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/spinlock.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/etherdevice.h>
30 #include <linux/delay.h>
31 #include <linux/platform_device.h>
32 #include <linux/mdio-bitbang.h>
33 #include <linux/netdevice.h>
34 #include <linux/phy.h>
35 #include <linux/cache.h>
36 #include <linux/io.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/slab.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/clk.h>
42 #include <linux/sh_eth.h>
43
44 #include "sh_eth.h"
45
46 #define SH_ETH_DEF_MSG_ENABLE \
47 (NETIF_MSG_LINK | \
48 NETIF_MSG_TIMER | \
49 NETIF_MSG_RX_ERR| \
50 NETIF_MSG_TX_ERR)
51
52 #if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
53 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
54 defined(CONFIG_ARCH_R8A7740)
55 static void sh_eth_select_mii(struct net_device *ndev)
56 {
57 u32 value = 0x0;
58 struct sh_eth_private *mdp = netdev_priv(ndev);
59
60 switch (mdp->phy_interface) {
61 case PHY_INTERFACE_MODE_GMII:
62 value = 0x2;
63 break;
64 case PHY_INTERFACE_MODE_MII:
65 value = 0x1;
66 break;
67 case PHY_INTERFACE_MODE_RMII:
68 value = 0x0;
69 break;
70 default:
71 pr_warn("PHY interface mode was not setup. Set to MII.\n");
72 value = 0x1;
73 break;
74 }
75
76 sh_eth_write(ndev, value, RMII_MII);
77 }
78 #endif
79
80 /* There is CPU dependent code */
81 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
82 #define SH_ETH_RESET_DEFAULT 1
83 static void sh_eth_set_duplex(struct net_device *ndev)
84 {
85 struct sh_eth_private *mdp = netdev_priv(ndev);
86
87 if (mdp->duplex) /* Full */
88 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
89 else /* Half */
90 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
91 }
92
93 static void sh_eth_set_rate(struct net_device *ndev)
94 {
95 struct sh_eth_private *mdp = netdev_priv(ndev);
96
97 switch (mdp->speed) {
98 case 10: /* 10BASE */
99 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
100 break;
101 case 100:/* 100BASE */
102 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
103 break;
104 default:
105 break;
106 }
107 }
108
109 /* SH7724 */
110 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
111 .set_duplex = sh_eth_set_duplex,
112 .set_rate = sh_eth_set_rate,
113
114 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
115 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
116 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
117
118 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
119 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
120 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
121 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
122
123 .apr = 1,
124 .mpr = 1,
125 .tpauser = 1,
126 .hw_swap = 1,
127 .rpadir = 1,
128 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
129 };
130 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
131 #define SH_ETH_HAS_BOTH_MODULES 1
132 #define SH_ETH_HAS_TSU 1
133 static int sh_eth_check_reset(struct net_device *ndev);
134
135 static void sh_eth_set_duplex(struct net_device *ndev)
136 {
137 struct sh_eth_private *mdp = netdev_priv(ndev);
138
139 if (mdp->duplex) /* Full */
140 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
141 else /* Half */
142 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
143 }
144
145 static void sh_eth_set_rate(struct net_device *ndev)
146 {
147 struct sh_eth_private *mdp = netdev_priv(ndev);
148
149 switch (mdp->speed) {
150 case 10: /* 10BASE */
151 sh_eth_write(ndev, 0, RTRATE);
152 break;
153 case 100:/* 100BASE */
154 sh_eth_write(ndev, 1, RTRATE);
155 break;
156 default:
157 break;
158 }
159 }
160
161 /* SH7757 */
162 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
163 .set_duplex = sh_eth_set_duplex,
164 .set_rate = sh_eth_set_rate,
165
166 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
167 .rmcr_value = 0x00000001,
168
169 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
170 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
171 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
172 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
173
174 .apr = 1,
175 .mpr = 1,
176 .tpauser = 1,
177 .hw_swap = 1,
178 .no_ade = 1,
179 .rpadir = 1,
180 .rpadir_value = 2 << 16,
181 };
182
183 #define SH_GIGA_ETH_BASE 0xfee00000
184 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
185 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
186 static void sh_eth_chip_reset_giga(struct net_device *ndev)
187 {
188 int i;
189 unsigned long mahr[2], malr[2];
190
191 /* save MAHR and MALR */
192 for (i = 0; i < 2; i++) {
193 malr[i] = ioread32((void *)GIGA_MALR(i));
194 mahr[i] = ioread32((void *)GIGA_MAHR(i));
195 }
196
197 /* reset device */
198 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
199 mdelay(1);
200
201 /* restore MAHR and MALR */
202 for (i = 0; i < 2; i++) {
203 iowrite32(malr[i], (void *)GIGA_MALR(i));
204 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
205 }
206 }
207
208 static int sh_eth_is_gether(struct sh_eth_private *mdp);
209 static int sh_eth_reset(struct net_device *ndev)
210 {
211 struct sh_eth_private *mdp = netdev_priv(ndev);
212 int ret = 0;
213
214 if (sh_eth_is_gether(mdp)) {
215 sh_eth_write(ndev, 0x03, EDSR);
216 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
217 EDMR);
218
219 ret = sh_eth_check_reset(ndev);
220 if (ret)
221 goto out;
222
223 /* Table Init */
224 sh_eth_write(ndev, 0x0, TDLAR);
225 sh_eth_write(ndev, 0x0, TDFAR);
226 sh_eth_write(ndev, 0x0, TDFXR);
227 sh_eth_write(ndev, 0x0, TDFFR);
228 sh_eth_write(ndev, 0x0, RDLAR);
229 sh_eth_write(ndev, 0x0, RDFAR);
230 sh_eth_write(ndev, 0x0, RDFXR);
231 sh_eth_write(ndev, 0x0, RDFFR);
232 } else {
233 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
234 EDMR);
235 mdelay(3);
236 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
237 EDMR);
238 }
239
240 out:
241 return ret;
242 }
243
244 static void sh_eth_set_duplex_giga(struct net_device *ndev)
245 {
246 struct sh_eth_private *mdp = netdev_priv(ndev);
247
248 if (mdp->duplex) /* Full */
249 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
250 else /* Half */
251 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
252 }
253
254 static void sh_eth_set_rate_giga(struct net_device *ndev)
255 {
256 struct sh_eth_private *mdp = netdev_priv(ndev);
257
258 switch (mdp->speed) {
259 case 10: /* 10BASE */
260 sh_eth_write(ndev, 0x00000000, GECMR);
261 break;
262 case 100:/* 100BASE */
263 sh_eth_write(ndev, 0x00000010, GECMR);
264 break;
265 case 1000: /* 1000BASE */
266 sh_eth_write(ndev, 0x00000020, GECMR);
267 break;
268 default:
269 break;
270 }
271 }
272
273 /* SH7757(GETHERC) */
274 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
275 .chip_reset = sh_eth_chip_reset_giga,
276 .set_duplex = sh_eth_set_duplex_giga,
277 .set_rate = sh_eth_set_rate_giga,
278
279 .ecsr_value = ECSR_ICD | ECSR_MPD,
280 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
281 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
282
283 .tx_check = EESR_TC1 | EESR_FTC,
284 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
285 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
286 EESR_ECI,
287 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
288 EESR_TFE,
289 .fdr_value = 0x0000072f,
290 .rmcr_value = 0x00000001,
291
292 .apr = 1,
293 .mpr = 1,
294 .tpauser = 1,
295 .bculr = 1,
296 .hw_swap = 1,
297 .rpadir = 1,
298 .rpadir_value = 2 << 16,
299 .no_trimd = 1,
300 .no_ade = 1,
301 .tsu = 1,
302 };
303
304 static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
305 {
306 if (sh_eth_is_gether(mdp))
307 return &sh_eth_my_cpu_data_giga;
308 else
309 return &sh_eth_my_cpu_data;
310 }
311
312 #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
313 #define SH_ETH_HAS_TSU 1
314 static int sh_eth_check_reset(struct net_device *ndev);
315 static void sh_eth_reset_hw_crc(struct net_device *ndev);
316
317 static void sh_eth_chip_reset(struct net_device *ndev)
318 {
319 struct sh_eth_private *mdp = netdev_priv(ndev);
320
321 /* reset device */
322 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
323 mdelay(1);
324 }
325
326 static void sh_eth_set_duplex(struct net_device *ndev)
327 {
328 struct sh_eth_private *mdp = netdev_priv(ndev);
329
330 if (mdp->duplex) /* Full */
331 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
332 else /* Half */
333 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
334 }
335
336 static void sh_eth_set_rate(struct net_device *ndev)
337 {
338 struct sh_eth_private *mdp = netdev_priv(ndev);
339
340 switch (mdp->speed) {
341 case 10: /* 10BASE */
342 sh_eth_write(ndev, GECMR_10, GECMR);
343 break;
344 case 100:/* 100BASE */
345 sh_eth_write(ndev, GECMR_100, GECMR);
346 break;
347 case 1000: /* 1000BASE */
348 sh_eth_write(ndev, GECMR_1000, GECMR);
349 break;
350 default:
351 break;
352 }
353 }
354
355 /* sh7763 */
356 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
357 .chip_reset = sh_eth_chip_reset,
358 .set_duplex = sh_eth_set_duplex,
359 .set_rate = sh_eth_set_rate,
360
361 .ecsr_value = ECSR_ICD | ECSR_MPD,
362 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
363 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
364
365 .tx_check = EESR_TC1 | EESR_FTC,
366 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
367 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
368 EESR_ECI,
369 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
370 EESR_TFE,
371
372 .apr = 1,
373 .mpr = 1,
374 .tpauser = 1,
375 .bculr = 1,
376 .hw_swap = 1,
377 .no_trimd = 1,
378 .no_ade = 1,
379 .tsu = 1,
380 #if defined(CONFIG_CPU_SUBTYPE_SH7734)
381 .hw_crc = 1,
382 .select_mii = 1,
383 #endif
384 };
385
386 static int sh_eth_reset(struct net_device *ndev)
387 {
388 int ret = 0;
389
390 sh_eth_write(ndev, EDSR_ENALL, EDSR);
391 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
392
393 ret = sh_eth_check_reset(ndev);
394 if (ret)
395 goto out;
396
397 /* Table Init */
398 sh_eth_write(ndev, 0x0, TDLAR);
399 sh_eth_write(ndev, 0x0, TDFAR);
400 sh_eth_write(ndev, 0x0, TDFXR);
401 sh_eth_write(ndev, 0x0, TDFFR);
402 sh_eth_write(ndev, 0x0, RDLAR);
403 sh_eth_write(ndev, 0x0, RDFAR);
404 sh_eth_write(ndev, 0x0, RDFXR);
405 sh_eth_write(ndev, 0x0, RDFFR);
406
407 /* Reset HW CRC register */
408 sh_eth_reset_hw_crc(ndev);
409
410 /* Select MII mode */
411 if (sh_eth_my_cpu_data.select_mii)
412 sh_eth_select_mii(ndev);
413 out:
414 return ret;
415 }
416
417 static void sh_eth_reset_hw_crc(struct net_device *ndev)
418 {
419 if (sh_eth_my_cpu_data.hw_crc)
420 sh_eth_write(ndev, 0x0, CSMR);
421 }
422
423 #elif defined(CONFIG_ARCH_R8A7740)
424 #define SH_ETH_HAS_TSU 1
425 static int sh_eth_check_reset(struct net_device *ndev);
426
427 static void sh_eth_chip_reset(struct net_device *ndev)
428 {
429 struct sh_eth_private *mdp = netdev_priv(ndev);
430
431 /* reset device */
432 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
433 mdelay(1);
434
435 sh_eth_select_mii(ndev);
436 }
437
438 static int sh_eth_reset(struct net_device *ndev)
439 {
440 int ret = 0;
441
442 sh_eth_write(ndev, EDSR_ENALL, EDSR);
443 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
444
445 ret = sh_eth_check_reset(ndev);
446 if (ret)
447 goto out;
448
449 /* Table Init */
450 sh_eth_write(ndev, 0x0, TDLAR);
451 sh_eth_write(ndev, 0x0, TDFAR);
452 sh_eth_write(ndev, 0x0, TDFXR);
453 sh_eth_write(ndev, 0x0, TDFFR);
454 sh_eth_write(ndev, 0x0, RDLAR);
455 sh_eth_write(ndev, 0x0, RDFAR);
456 sh_eth_write(ndev, 0x0, RDFXR);
457 sh_eth_write(ndev, 0x0, RDFFR);
458
459 out:
460 return ret;
461 }
462
463 static void sh_eth_set_duplex(struct net_device *ndev)
464 {
465 struct sh_eth_private *mdp = netdev_priv(ndev);
466
467 if (mdp->duplex) /* Full */
468 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
469 else /* Half */
470 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
471 }
472
473 static void sh_eth_set_rate(struct net_device *ndev)
474 {
475 struct sh_eth_private *mdp = netdev_priv(ndev);
476
477 switch (mdp->speed) {
478 case 10: /* 10BASE */
479 sh_eth_write(ndev, GECMR_10, GECMR);
480 break;
481 case 100:/* 100BASE */
482 sh_eth_write(ndev, GECMR_100, GECMR);
483 break;
484 case 1000: /* 1000BASE */
485 sh_eth_write(ndev, GECMR_1000, GECMR);
486 break;
487 default:
488 break;
489 }
490 }
491
492 /* R8A7740 */
493 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
494 .chip_reset = sh_eth_chip_reset,
495 .set_duplex = sh_eth_set_duplex,
496 .set_rate = sh_eth_set_rate,
497
498 .ecsr_value = ECSR_ICD | ECSR_MPD,
499 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
500 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
501
502 .tx_check = EESR_TC1 | EESR_FTC,
503 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
504 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
505 EESR_ECI,
506 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
507 EESR_TFE,
508
509 .apr = 1,
510 .mpr = 1,
511 .tpauser = 1,
512 .bculr = 1,
513 .hw_swap = 1,
514 .no_trimd = 1,
515 .no_ade = 1,
516 .tsu = 1,
517 .select_mii = 1,
518 };
519
520 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
521 #define SH_ETH_RESET_DEFAULT 1
522 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
523 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
524
525 .apr = 1,
526 .mpr = 1,
527 .tpauser = 1,
528 .hw_swap = 1,
529 };
530 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
531 #define SH_ETH_RESET_DEFAULT 1
532 #define SH_ETH_HAS_TSU 1
533 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
534 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
535 .tsu = 1,
536 };
537 #endif
538
539 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
540 {
541 if (!cd->ecsr_value)
542 cd->ecsr_value = DEFAULT_ECSR_INIT;
543
544 if (!cd->ecsipr_value)
545 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
546
547 if (!cd->fcftr_value)
548 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
549 DEFAULT_FIFO_F_D_RFD;
550
551 if (!cd->fdr_value)
552 cd->fdr_value = DEFAULT_FDR_INIT;
553
554 if (!cd->rmcr_value)
555 cd->rmcr_value = DEFAULT_RMCR_VALUE;
556
557 if (!cd->tx_check)
558 cd->tx_check = DEFAULT_TX_CHECK;
559
560 if (!cd->eesr_err_check)
561 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
562
563 if (!cd->tx_error_check)
564 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
565 }
566
567 #if defined(SH_ETH_RESET_DEFAULT)
568 /* Chip Reset */
569 static int sh_eth_reset(struct net_device *ndev)
570 {
571 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
572 mdelay(3);
573 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
574
575 return 0;
576 }
577 #else
578 static int sh_eth_check_reset(struct net_device *ndev)
579 {
580 int ret = 0;
581 int cnt = 100;
582
583 while (cnt > 0) {
584 if (!(sh_eth_read(ndev, EDMR) & 0x3))
585 break;
586 mdelay(1);
587 cnt--;
588 }
589 if (cnt < 0) {
590 printk(KERN_ERR "Device reset fail\n");
591 ret = -ETIMEDOUT;
592 }
593 return ret;
594 }
595 #endif
596
597 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
598 static void sh_eth_set_receive_align(struct sk_buff *skb)
599 {
600 int reserve;
601
602 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
603 if (reserve)
604 skb_reserve(skb, reserve);
605 }
606 #else
607 static void sh_eth_set_receive_align(struct sk_buff *skb)
608 {
609 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
610 }
611 #endif
612
613
614 /* CPU <-> EDMAC endian convert */
615 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
616 {
617 switch (mdp->edmac_endian) {
618 case EDMAC_LITTLE_ENDIAN:
619 return cpu_to_le32(x);
620 case EDMAC_BIG_ENDIAN:
621 return cpu_to_be32(x);
622 }
623 return x;
624 }
625
626 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
627 {
628 switch (mdp->edmac_endian) {
629 case EDMAC_LITTLE_ENDIAN:
630 return le32_to_cpu(x);
631 case EDMAC_BIG_ENDIAN:
632 return be32_to_cpu(x);
633 }
634 return x;
635 }
636
637 /*
638 * Program the hardware MAC address from dev->dev_addr.
639 */
640 static void update_mac_address(struct net_device *ndev)
641 {
642 sh_eth_write(ndev,
643 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
644 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
645 sh_eth_write(ndev,
646 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
647 }
648
649 /*
650 * Get MAC address from SuperH MAC address register
651 *
652 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
653 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
654 * When you want use this device, you must set MAC address in bootloader.
655 *
656 */
657 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
658 {
659 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
660 memcpy(ndev->dev_addr, mac, 6);
661 } else {
662 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
663 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
664 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
665 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
666 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
667 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
668 }
669 }
670
671 static int sh_eth_is_gether(struct sh_eth_private *mdp)
672 {
673 if (mdp->reg_offset == sh_eth_offset_gigabit)
674 return 1;
675 else
676 return 0;
677 }
678
679 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
680 {
681 if (sh_eth_is_gether(mdp))
682 return EDTRR_TRNS_GETHER;
683 else
684 return EDTRR_TRNS_ETHER;
685 }
686
687 struct bb_info {
688 void (*set_gate)(void *addr);
689 struct mdiobb_ctrl ctrl;
690 void *addr;
691 u32 mmd_msk;/* MMD */
692 u32 mdo_msk;
693 u32 mdi_msk;
694 u32 mdc_msk;
695 };
696
697 /* PHY bit set */
698 static void bb_set(void *addr, u32 msk)
699 {
700 iowrite32(ioread32(addr) | msk, addr);
701 }
702
703 /* PHY bit clear */
704 static void bb_clr(void *addr, u32 msk)
705 {
706 iowrite32((ioread32(addr) & ~msk), addr);
707 }
708
709 /* PHY bit read */
710 static int bb_read(void *addr, u32 msk)
711 {
712 return (ioread32(addr) & msk) != 0;
713 }
714
715 /* Data I/O pin control */
716 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
717 {
718 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
719
720 if (bitbang->set_gate)
721 bitbang->set_gate(bitbang->addr);
722
723 if (bit)
724 bb_set(bitbang->addr, bitbang->mmd_msk);
725 else
726 bb_clr(bitbang->addr, bitbang->mmd_msk);
727 }
728
729 /* Set bit data*/
730 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
731 {
732 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
733
734 if (bitbang->set_gate)
735 bitbang->set_gate(bitbang->addr);
736
737 if (bit)
738 bb_set(bitbang->addr, bitbang->mdo_msk);
739 else
740 bb_clr(bitbang->addr, bitbang->mdo_msk);
741 }
742
743 /* Get bit data*/
744 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
745 {
746 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
747
748 if (bitbang->set_gate)
749 bitbang->set_gate(bitbang->addr);
750
751 return bb_read(bitbang->addr, bitbang->mdi_msk);
752 }
753
754 /* MDC pin control */
755 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
756 {
757 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
758
759 if (bitbang->set_gate)
760 bitbang->set_gate(bitbang->addr);
761
762 if (bit)
763 bb_set(bitbang->addr, bitbang->mdc_msk);
764 else
765 bb_clr(bitbang->addr, bitbang->mdc_msk);
766 }
767
768 /* mdio bus control struct */
769 static struct mdiobb_ops bb_ops = {
770 .owner = THIS_MODULE,
771 .set_mdc = sh_mdc_ctrl,
772 .set_mdio_dir = sh_mmd_ctrl,
773 .set_mdio_data = sh_set_mdio,
774 .get_mdio_data = sh_get_mdio,
775 };
776
777 /* free skb and descriptor buffer */
778 static void sh_eth_ring_free(struct net_device *ndev)
779 {
780 struct sh_eth_private *mdp = netdev_priv(ndev);
781 int i;
782
783 /* Free Rx skb ringbuffer */
784 if (mdp->rx_skbuff) {
785 for (i = 0; i < RX_RING_SIZE; i++) {
786 if (mdp->rx_skbuff[i])
787 dev_kfree_skb(mdp->rx_skbuff[i]);
788 }
789 }
790 kfree(mdp->rx_skbuff);
791
792 /* Free Tx skb ringbuffer */
793 if (mdp->tx_skbuff) {
794 for (i = 0; i < TX_RING_SIZE; i++) {
795 if (mdp->tx_skbuff[i])
796 dev_kfree_skb(mdp->tx_skbuff[i]);
797 }
798 }
799 kfree(mdp->tx_skbuff);
800 }
801
802 /* format skb and descriptor buffer */
803 static void sh_eth_ring_format(struct net_device *ndev)
804 {
805 struct sh_eth_private *mdp = netdev_priv(ndev);
806 int i;
807 struct sk_buff *skb;
808 struct sh_eth_rxdesc *rxdesc = NULL;
809 struct sh_eth_txdesc *txdesc = NULL;
810 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
811 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
812
813 mdp->cur_rx = mdp->cur_tx = 0;
814 mdp->dirty_rx = mdp->dirty_tx = 0;
815
816 memset(mdp->rx_ring, 0, rx_ringsize);
817
818 /* build Rx ring buffer */
819 for (i = 0; i < RX_RING_SIZE; i++) {
820 /* skb */
821 mdp->rx_skbuff[i] = NULL;
822 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
823 mdp->rx_skbuff[i] = skb;
824 if (skb == NULL)
825 break;
826 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
827 DMA_FROM_DEVICE);
828 sh_eth_set_receive_align(skb);
829
830 /* RX descriptor */
831 rxdesc = &mdp->rx_ring[i];
832 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
833 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
834
835 /* The size of the buffer is 16 byte boundary. */
836 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
837 /* Rx descriptor address set */
838 if (i == 0) {
839 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
840 if (sh_eth_is_gether(mdp))
841 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
842 }
843 }
844
845 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
846
847 /* Mark the last entry as wrapping the ring. */
848 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
849
850 memset(mdp->tx_ring, 0, tx_ringsize);
851
852 /* build Tx ring buffer */
853 for (i = 0; i < TX_RING_SIZE; i++) {
854 mdp->tx_skbuff[i] = NULL;
855 txdesc = &mdp->tx_ring[i];
856 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
857 txdesc->buffer_length = 0;
858 if (i == 0) {
859 /* Tx descriptor address set */
860 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
861 if (sh_eth_is_gether(mdp))
862 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
863 }
864 }
865
866 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
867 }
868
869 /* Get skb and descriptor buffer */
870 static int sh_eth_ring_init(struct net_device *ndev)
871 {
872 struct sh_eth_private *mdp = netdev_priv(ndev);
873 int rx_ringsize, tx_ringsize, ret = 0;
874
875 /*
876 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
877 * card needs room to do 8 byte alignment, +2 so we can reserve
878 * the first 2 bytes, and +16 gets room for the status word from the
879 * card.
880 */
881 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
882 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
883 if (mdp->cd->rpadir)
884 mdp->rx_buf_sz += NET_IP_ALIGN;
885
886 /* Allocate RX and TX skb rings */
887 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
888 GFP_KERNEL);
889 if (!mdp->rx_skbuff) {
890 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
891 ret = -ENOMEM;
892 return ret;
893 }
894
895 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
896 GFP_KERNEL);
897 if (!mdp->tx_skbuff) {
898 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
899 ret = -ENOMEM;
900 goto skb_ring_free;
901 }
902
903 /* Allocate all Rx descriptors. */
904 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
905 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
906 GFP_KERNEL);
907
908 if (!mdp->rx_ring) {
909 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
910 rx_ringsize);
911 ret = -ENOMEM;
912 goto desc_ring_free;
913 }
914
915 mdp->dirty_rx = 0;
916
917 /* Allocate all Tx descriptors. */
918 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
919 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
920 GFP_KERNEL);
921 if (!mdp->tx_ring) {
922 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
923 tx_ringsize);
924 ret = -ENOMEM;
925 goto desc_ring_free;
926 }
927 return ret;
928
929 desc_ring_free:
930 /* free DMA buffer */
931 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
932
933 skb_ring_free:
934 /* Free Rx and Tx skb ring buffer */
935 sh_eth_ring_free(ndev);
936
937 return ret;
938 }
939
940 static int sh_eth_dev_init(struct net_device *ndev)
941 {
942 int ret = 0;
943 struct sh_eth_private *mdp = netdev_priv(ndev);
944 u_int32_t rx_int_var, tx_int_var;
945 u32 val;
946
947 /* Soft Reset */
948 ret = sh_eth_reset(ndev);
949 if (ret)
950 goto out;
951
952 /* Descriptor format */
953 sh_eth_ring_format(ndev);
954 if (mdp->cd->rpadir)
955 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
956
957 /* all sh_eth int mask */
958 sh_eth_write(ndev, 0, EESIPR);
959
960 #if defined(__LITTLE_ENDIAN)
961 if (mdp->cd->hw_swap)
962 sh_eth_write(ndev, EDMR_EL, EDMR);
963 else
964 #endif
965 sh_eth_write(ndev, 0, EDMR);
966
967 /* FIFO size set */
968 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
969 sh_eth_write(ndev, 0, TFTR);
970
971 /* Frame recv control */
972 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
973
974 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
975 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
976 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
977
978 if (mdp->cd->bculr)
979 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
980
981 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
982
983 if (!mdp->cd->no_trimd)
984 sh_eth_write(ndev, 0, TRIMD);
985
986 /* Recv frame limit set register */
987 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
988 RFLR);
989
990 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
991 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
992
993 /* PAUSE Prohibition */
994 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
995 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
996
997 sh_eth_write(ndev, val, ECMR);
998
999 if (mdp->cd->set_rate)
1000 mdp->cd->set_rate(ndev);
1001
1002 /* E-MAC Status Register clear */
1003 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1004
1005 /* E-MAC Interrupt Enable register */
1006 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1007
1008 /* Set MAC address */
1009 update_mac_address(ndev);
1010
1011 /* mask reset */
1012 if (mdp->cd->apr)
1013 sh_eth_write(ndev, APR_AP, APR);
1014 if (mdp->cd->mpr)
1015 sh_eth_write(ndev, MPR_MP, MPR);
1016 if (mdp->cd->tpauser)
1017 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1018
1019 /* Setting the Rx mode will start the Rx process. */
1020 sh_eth_write(ndev, EDRRR_R, EDRRR);
1021
1022 netif_start_queue(ndev);
1023
1024 out:
1025 return ret;
1026 }
1027
1028 /* free Tx skb function */
1029 static int sh_eth_txfree(struct net_device *ndev)
1030 {
1031 struct sh_eth_private *mdp = netdev_priv(ndev);
1032 struct sh_eth_txdesc *txdesc;
1033 int freeNum = 0;
1034 int entry = 0;
1035
1036 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1037 entry = mdp->dirty_tx % TX_RING_SIZE;
1038 txdesc = &mdp->tx_ring[entry];
1039 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1040 break;
1041 /* Free the original skb. */
1042 if (mdp->tx_skbuff[entry]) {
1043 dma_unmap_single(&ndev->dev, txdesc->addr,
1044 txdesc->buffer_length, DMA_TO_DEVICE);
1045 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1046 mdp->tx_skbuff[entry] = NULL;
1047 freeNum++;
1048 }
1049 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1050 if (entry >= TX_RING_SIZE - 1)
1051 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1052
1053 ndev->stats.tx_packets++;
1054 ndev->stats.tx_bytes += txdesc->buffer_length;
1055 }
1056 return freeNum;
1057 }
1058
1059 /* Packet receive function */
1060 static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
1061 {
1062 struct sh_eth_private *mdp = netdev_priv(ndev);
1063 struct sh_eth_rxdesc *rxdesc;
1064
1065 int entry = mdp->cur_rx % RX_RING_SIZE;
1066 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
1067 struct sk_buff *skb;
1068 u16 pkt_len = 0;
1069 u32 desc_status;
1070
1071 rxdesc = &mdp->rx_ring[entry];
1072 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1073 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1074 pkt_len = rxdesc->frame_length;
1075
1076 #if defined(CONFIG_ARCH_R8A7740)
1077 desc_status >>= 16;
1078 #endif
1079
1080 if (--boguscnt < 0)
1081 break;
1082
1083 if (!(desc_status & RDFEND))
1084 ndev->stats.rx_length_errors++;
1085
1086 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1087 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1088 ndev->stats.rx_errors++;
1089 if (desc_status & RD_RFS1)
1090 ndev->stats.rx_crc_errors++;
1091 if (desc_status & RD_RFS2)
1092 ndev->stats.rx_frame_errors++;
1093 if (desc_status & RD_RFS3)
1094 ndev->stats.rx_length_errors++;
1095 if (desc_status & RD_RFS4)
1096 ndev->stats.rx_length_errors++;
1097 if (desc_status & RD_RFS6)
1098 ndev->stats.rx_missed_errors++;
1099 if (desc_status & RD_RFS10)
1100 ndev->stats.rx_over_errors++;
1101 } else {
1102 if (!mdp->cd->hw_swap)
1103 sh_eth_soft_swap(
1104 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1105 pkt_len + 2);
1106 skb = mdp->rx_skbuff[entry];
1107 mdp->rx_skbuff[entry] = NULL;
1108 if (mdp->cd->rpadir)
1109 skb_reserve(skb, NET_IP_ALIGN);
1110 skb_put(skb, pkt_len);
1111 skb->protocol = eth_type_trans(skb, ndev);
1112 netif_rx(skb);
1113 ndev->stats.rx_packets++;
1114 ndev->stats.rx_bytes += pkt_len;
1115 }
1116 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1117 entry = (++mdp->cur_rx) % RX_RING_SIZE;
1118 rxdesc = &mdp->rx_ring[entry];
1119 }
1120
1121 /* Refill the Rx ring buffers. */
1122 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1123 entry = mdp->dirty_rx % RX_RING_SIZE;
1124 rxdesc = &mdp->rx_ring[entry];
1125 /* The size of the buffer is 16 byte boundary. */
1126 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1127
1128 if (mdp->rx_skbuff[entry] == NULL) {
1129 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1130 mdp->rx_skbuff[entry] = skb;
1131 if (skb == NULL)
1132 break; /* Better luck next round. */
1133 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1134 DMA_FROM_DEVICE);
1135 sh_eth_set_receive_align(skb);
1136
1137 skb_checksum_none_assert(skb);
1138 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1139 }
1140 if (entry >= RX_RING_SIZE - 1)
1141 rxdesc->status |=
1142 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1143 else
1144 rxdesc->status |=
1145 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1146 }
1147
1148 /* Restart Rx engine if stopped. */
1149 /* If we don't need to check status, don't. -KDU */
1150 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1151 /* fix the values for the next receiving if RDE is set */
1152 if (intr_status & EESR_RDE)
1153 mdp->cur_rx = mdp->dirty_rx =
1154 (sh_eth_read(ndev, RDFAR) -
1155 sh_eth_read(ndev, RDLAR)) >> 4;
1156 sh_eth_write(ndev, EDRRR_R, EDRRR);
1157 }
1158
1159 return 0;
1160 }
1161
1162 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1163 {
1164 /* disable tx and rx */
1165 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1166 ~(ECMR_RE | ECMR_TE), ECMR);
1167 }
1168
1169 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1170 {
1171 /* enable tx and rx */
1172 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1173 (ECMR_RE | ECMR_TE), ECMR);
1174 }
1175
1176 /* error control function */
1177 static void sh_eth_error(struct net_device *ndev, int intr_status)
1178 {
1179 struct sh_eth_private *mdp = netdev_priv(ndev);
1180 u32 felic_stat;
1181 u32 link_stat;
1182 u32 mask;
1183
1184 if (intr_status & EESR_ECI) {
1185 felic_stat = sh_eth_read(ndev, ECSR);
1186 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1187 if (felic_stat & ECSR_ICD)
1188 ndev->stats.tx_carrier_errors++;
1189 if (felic_stat & ECSR_LCHNG) {
1190 /* Link Changed */
1191 if (mdp->cd->no_psr || mdp->no_ether_link) {
1192 if (mdp->link == PHY_DOWN)
1193 link_stat = 0;
1194 else
1195 link_stat = PHY_ST_LINK;
1196 } else {
1197 link_stat = (sh_eth_read(ndev, PSR));
1198 if (mdp->ether_link_active_low)
1199 link_stat = ~link_stat;
1200 }
1201 if (!(link_stat & PHY_ST_LINK))
1202 sh_eth_rcv_snd_disable(ndev);
1203 else {
1204 /* Link Up */
1205 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1206 ~DMAC_M_ECI, EESIPR);
1207 /*clear int */
1208 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1209 ECSR);
1210 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1211 DMAC_M_ECI, EESIPR);
1212 /* enable tx and rx */
1213 sh_eth_rcv_snd_enable(ndev);
1214 }
1215 }
1216 }
1217
1218 if (intr_status & EESR_TWB) {
1219 /* Write buck end. unused write back interrupt */
1220 if (intr_status & EESR_TABT) /* Transmit Abort int */
1221 ndev->stats.tx_aborted_errors++;
1222 if (netif_msg_tx_err(mdp))
1223 dev_err(&ndev->dev, "Transmit Abort\n");
1224 }
1225
1226 if (intr_status & EESR_RABT) {
1227 /* Receive Abort int */
1228 if (intr_status & EESR_RFRMER) {
1229 /* Receive Frame Overflow int */
1230 ndev->stats.rx_frame_errors++;
1231 if (netif_msg_rx_err(mdp))
1232 dev_err(&ndev->dev, "Receive Abort\n");
1233 }
1234 }
1235
1236 if (intr_status & EESR_TDE) {
1237 /* Transmit Descriptor Empty int */
1238 ndev->stats.tx_fifo_errors++;
1239 if (netif_msg_tx_err(mdp))
1240 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1241 }
1242
1243 if (intr_status & EESR_TFE) {
1244 /* FIFO under flow */
1245 ndev->stats.tx_fifo_errors++;
1246 if (netif_msg_tx_err(mdp))
1247 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1248 }
1249
1250 if (intr_status & EESR_RDE) {
1251 /* Receive Descriptor Empty int */
1252 ndev->stats.rx_over_errors++;
1253
1254 if (netif_msg_rx_err(mdp))
1255 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1256 }
1257
1258 if (intr_status & EESR_RFE) {
1259 /* Receive FIFO Overflow int */
1260 ndev->stats.rx_fifo_errors++;
1261 if (netif_msg_rx_err(mdp))
1262 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1263 }
1264
1265 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1266 /* Address Error */
1267 ndev->stats.tx_fifo_errors++;
1268 if (netif_msg_tx_err(mdp))
1269 dev_err(&ndev->dev, "Address Error\n");
1270 }
1271
1272 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1273 if (mdp->cd->no_ade)
1274 mask &= ~EESR_ADE;
1275 if (intr_status & mask) {
1276 /* Tx error */
1277 u32 edtrr = sh_eth_read(ndev, EDTRR);
1278 /* dmesg */
1279 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1280 intr_status, mdp->cur_tx);
1281 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1282 mdp->dirty_tx, (u32) ndev->state, edtrr);
1283 /* dirty buffer free */
1284 sh_eth_txfree(ndev);
1285
1286 /* SH7712 BUG */
1287 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1288 /* tx dma start */
1289 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1290 }
1291 /* wakeup */
1292 netif_wake_queue(ndev);
1293 }
1294 }
1295
1296 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1297 {
1298 struct net_device *ndev = netdev;
1299 struct sh_eth_private *mdp = netdev_priv(ndev);
1300 struct sh_eth_cpu_data *cd = mdp->cd;
1301 irqreturn_t ret = IRQ_NONE;
1302 u32 intr_status = 0;
1303
1304 spin_lock(&mdp->lock);
1305
1306 /* Get interrpt stat */
1307 intr_status = sh_eth_read(ndev, EESR);
1308 /* Clear interrupt */
1309 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1310 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1311 cd->tx_check | cd->eesr_err_check)) {
1312 sh_eth_write(ndev, intr_status, EESR);
1313 ret = IRQ_HANDLED;
1314 } else
1315 goto other_irq;
1316
1317 if (intr_status & (EESR_FRC | /* Frame recv*/
1318 EESR_RMAF | /* Multi cast address recv*/
1319 EESR_RRF | /* Bit frame recv */
1320 EESR_RTLF | /* Long frame recv*/
1321 EESR_RTSF | /* short frame recv */
1322 EESR_PRE | /* PHY-LSI recv error */
1323 EESR_CERF)){ /* recv frame CRC error */
1324 sh_eth_rx(ndev, intr_status);
1325 }
1326
1327 /* Tx Check */
1328 if (intr_status & cd->tx_check) {
1329 sh_eth_txfree(ndev);
1330 netif_wake_queue(ndev);
1331 }
1332
1333 if (intr_status & cd->eesr_err_check)
1334 sh_eth_error(ndev, intr_status);
1335
1336 other_irq:
1337 spin_unlock(&mdp->lock);
1338
1339 return ret;
1340 }
1341
1342 /* PHY state control function */
1343 static void sh_eth_adjust_link(struct net_device *ndev)
1344 {
1345 struct sh_eth_private *mdp = netdev_priv(ndev);
1346 struct phy_device *phydev = mdp->phydev;
1347 int new_state = 0;
1348
1349 if (phydev->link != PHY_DOWN) {
1350 if (phydev->duplex != mdp->duplex) {
1351 new_state = 1;
1352 mdp->duplex = phydev->duplex;
1353 if (mdp->cd->set_duplex)
1354 mdp->cd->set_duplex(ndev);
1355 }
1356
1357 if (phydev->speed != mdp->speed) {
1358 new_state = 1;
1359 mdp->speed = phydev->speed;
1360 if (mdp->cd->set_rate)
1361 mdp->cd->set_rate(ndev);
1362 }
1363 if (mdp->link == PHY_DOWN) {
1364 sh_eth_write(ndev,
1365 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1366 new_state = 1;
1367 mdp->link = phydev->link;
1368 }
1369 } else if (mdp->link) {
1370 new_state = 1;
1371 mdp->link = PHY_DOWN;
1372 mdp->speed = 0;
1373 mdp->duplex = -1;
1374 }
1375
1376 if (new_state && netif_msg_link(mdp))
1377 phy_print_status(phydev);
1378 }
1379
1380 /* PHY init function */
1381 static int sh_eth_phy_init(struct net_device *ndev)
1382 {
1383 struct sh_eth_private *mdp = netdev_priv(ndev);
1384 char phy_id[MII_BUS_ID_SIZE + 3];
1385 struct phy_device *phydev = NULL;
1386
1387 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1388 mdp->mii_bus->id , mdp->phy_id);
1389
1390 mdp->link = PHY_DOWN;
1391 mdp->speed = 0;
1392 mdp->duplex = -1;
1393
1394 /* Try connect to PHY */
1395 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1396 0, mdp->phy_interface);
1397 if (IS_ERR(phydev)) {
1398 dev_err(&ndev->dev, "phy_connect failed\n");
1399 return PTR_ERR(phydev);
1400 }
1401
1402 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1403 phydev->addr, phydev->drv->name);
1404
1405 mdp->phydev = phydev;
1406
1407 return 0;
1408 }
1409
1410 /* PHY control start function */
1411 static int sh_eth_phy_start(struct net_device *ndev)
1412 {
1413 struct sh_eth_private *mdp = netdev_priv(ndev);
1414 int ret;
1415
1416 ret = sh_eth_phy_init(ndev);
1417 if (ret)
1418 return ret;
1419
1420 /* reset phy - this also wakes it from PDOWN */
1421 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1422 phy_start(mdp->phydev);
1423
1424 return 0;
1425 }
1426
1427 static int sh_eth_get_settings(struct net_device *ndev,
1428 struct ethtool_cmd *ecmd)
1429 {
1430 struct sh_eth_private *mdp = netdev_priv(ndev);
1431 unsigned long flags;
1432 int ret;
1433
1434 spin_lock_irqsave(&mdp->lock, flags);
1435 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1436 spin_unlock_irqrestore(&mdp->lock, flags);
1437
1438 return ret;
1439 }
1440
1441 static int sh_eth_set_settings(struct net_device *ndev,
1442 struct ethtool_cmd *ecmd)
1443 {
1444 struct sh_eth_private *mdp = netdev_priv(ndev);
1445 unsigned long flags;
1446 int ret;
1447
1448 spin_lock_irqsave(&mdp->lock, flags);
1449
1450 /* disable tx and rx */
1451 sh_eth_rcv_snd_disable(ndev);
1452
1453 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1454 if (ret)
1455 goto error_exit;
1456
1457 if (ecmd->duplex == DUPLEX_FULL)
1458 mdp->duplex = 1;
1459 else
1460 mdp->duplex = 0;
1461
1462 if (mdp->cd->set_duplex)
1463 mdp->cd->set_duplex(ndev);
1464
1465 error_exit:
1466 mdelay(1);
1467
1468 /* enable tx and rx */
1469 sh_eth_rcv_snd_enable(ndev);
1470
1471 spin_unlock_irqrestore(&mdp->lock, flags);
1472
1473 return ret;
1474 }
1475
1476 static int sh_eth_nway_reset(struct net_device *ndev)
1477 {
1478 struct sh_eth_private *mdp = netdev_priv(ndev);
1479 unsigned long flags;
1480 int ret;
1481
1482 spin_lock_irqsave(&mdp->lock, flags);
1483 ret = phy_start_aneg(mdp->phydev);
1484 spin_unlock_irqrestore(&mdp->lock, flags);
1485
1486 return ret;
1487 }
1488
1489 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1490 {
1491 struct sh_eth_private *mdp = netdev_priv(ndev);
1492 return mdp->msg_enable;
1493 }
1494
1495 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1496 {
1497 struct sh_eth_private *mdp = netdev_priv(ndev);
1498 mdp->msg_enable = value;
1499 }
1500
1501 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1502 "rx_current", "tx_current",
1503 "rx_dirty", "tx_dirty",
1504 };
1505 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1506
1507 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1508 {
1509 switch (sset) {
1510 case ETH_SS_STATS:
1511 return SH_ETH_STATS_LEN;
1512 default:
1513 return -EOPNOTSUPP;
1514 }
1515 }
1516
1517 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1518 struct ethtool_stats *stats, u64 *data)
1519 {
1520 struct sh_eth_private *mdp = netdev_priv(ndev);
1521 int i = 0;
1522
1523 /* device-specific stats */
1524 data[i++] = mdp->cur_rx;
1525 data[i++] = mdp->cur_tx;
1526 data[i++] = mdp->dirty_rx;
1527 data[i++] = mdp->dirty_tx;
1528 }
1529
1530 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1531 {
1532 switch (stringset) {
1533 case ETH_SS_STATS:
1534 memcpy(data, *sh_eth_gstrings_stats,
1535 sizeof(sh_eth_gstrings_stats));
1536 break;
1537 }
1538 }
1539
1540 static const struct ethtool_ops sh_eth_ethtool_ops = {
1541 .get_settings = sh_eth_get_settings,
1542 .set_settings = sh_eth_set_settings,
1543 .nway_reset = sh_eth_nway_reset,
1544 .get_msglevel = sh_eth_get_msglevel,
1545 .set_msglevel = sh_eth_set_msglevel,
1546 .get_link = ethtool_op_get_link,
1547 .get_strings = sh_eth_get_strings,
1548 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1549 .get_sset_count = sh_eth_get_sset_count,
1550 };
1551
1552 /* network device open function */
1553 static int sh_eth_open(struct net_device *ndev)
1554 {
1555 int ret = 0;
1556 struct sh_eth_private *mdp = netdev_priv(ndev);
1557
1558 pm_runtime_get_sync(&mdp->pdev->dev);
1559
1560 ret = request_irq(ndev->irq, sh_eth_interrupt,
1561 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1562 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1563 defined(CONFIG_CPU_SUBTYPE_SH7757)
1564 IRQF_SHARED,
1565 #else
1566 0,
1567 #endif
1568 ndev->name, ndev);
1569 if (ret) {
1570 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1571 return ret;
1572 }
1573
1574 /* Descriptor set */
1575 ret = sh_eth_ring_init(ndev);
1576 if (ret)
1577 goto out_free_irq;
1578
1579 /* device init */
1580 ret = sh_eth_dev_init(ndev);
1581 if (ret)
1582 goto out_free_irq;
1583
1584 /* PHY control start*/
1585 ret = sh_eth_phy_start(ndev);
1586 if (ret)
1587 goto out_free_irq;
1588
1589 return ret;
1590
1591 out_free_irq:
1592 free_irq(ndev->irq, ndev);
1593 pm_runtime_put_sync(&mdp->pdev->dev);
1594 return ret;
1595 }
1596
1597 /* Timeout function */
1598 static void sh_eth_tx_timeout(struct net_device *ndev)
1599 {
1600 struct sh_eth_private *mdp = netdev_priv(ndev);
1601 struct sh_eth_rxdesc *rxdesc;
1602 int i;
1603
1604 netif_stop_queue(ndev);
1605
1606 if (netif_msg_timer(mdp))
1607 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1608 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1609
1610 /* tx_errors count up */
1611 ndev->stats.tx_errors++;
1612
1613 /* Free all the skbuffs in the Rx queue. */
1614 for (i = 0; i < RX_RING_SIZE; i++) {
1615 rxdesc = &mdp->rx_ring[i];
1616 rxdesc->status = 0;
1617 rxdesc->addr = 0xBADF00D0;
1618 if (mdp->rx_skbuff[i])
1619 dev_kfree_skb(mdp->rx_skbuff[i]);
1620 mdp->rx_skbuff[i] = NULL;
1621 }
1622 for (i = 0; i < TX_RING_SIZE; i++) {
1623 if (mdp->tx_skbuff[i])
1624 dev_kfree_skb(mdp->tx_skbuff[i]);
1625 mdp->tx_skbuff[i] = NULL;
1626 }
1627
1628 /* device init */
1629 sh_eth_dev_init(ndev);
1630 }
1631
1632 /* Packet transmit function */
1633 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1634 {
1635 struct sh_eth_private *mdp = netdev_priv(ndev);
1636 struct sh_eth_txdesc *txdesc;
1637 u32 entry;
1638 unsigned long flags;
1639
1640 spin_lock_irqsave(&mdp->lock, flags);
1641 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1642 if (!sh_eth_txfree(ndev)) {
1643 if (netif_msg_tx_queued(mdp))
1644 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1645 netif_stop_queue(ndev);
1646 spin_unlock_irqrestore(&mdp->lock, flags);
1647 return NETDEV_TX_BUSY;
1648 }
1649 }
1650 spin_unlock_irqrestore(&mdp->lock, flags);
1651
1652 entry = mdp->cur_tx % TX_RING_SIZE;
1653 mdp->tx_skbuff[entry] = skb;
1654 txdesc = &mdp->tx_ring[entry];
1655 /* soft swap. */
1656 if (!mdp->cd->hw_swap)
1657 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1658 skb->len + 2);
1659 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1660 DMA_TO_DEVICE);
1661 if (skb->len < ETHERSMALL)
1662 txdesc->buffer_length = ETHERSMALL;
1663 else
1664 txdesc->buffer_length = skb->len;
1665
1666 if (entry >= TX_RING_SIZE - 1)
1667 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1668 else
1669 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1670
1671 mdp->cur_tx++;
1672
1673 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1674 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1675
1676 return NETDEV_TX_OK;
1677 }
1678
1679 /* device close function */
1680 static int sh_eth_close(struct net_device *ndev)
1681 {
1682 struct sh_eth_private *mdp = netdev_priv(ndev);
1683 int ringsize;
1684
1685 netif_stop_queue(ndev);
1686
1687 /* Disable interrupts by clearing the interrupt mask. */
1688 sh_eth_write(ndev, 0x0000, EESIPR);
1689
1690 /* Stop the chip's Tx and Rx processes. */
1691 sh_eth_write(ndev, 0, EDTRR);
1692 sh_eth_write(ndev, 0, EDRRR);
1693
1694 /* PHY Disconnect */
1695 if (mdp->phydev) {
1696 phy_stop(mdp->phydev);
1697 phy_disconnect(mdp->phydev);
1698 }
1699
1700 free_irq(ndev->irq, ndev);
1701
1702 /* Free all the skbuffs in the Rx queue. */
1703 sh_eth_ring_free(ndev);
1704
1705 /* free DMA buffer */
1706 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1707 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1708
1709 /* free DMA buffer */
1710 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1711 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1712
1713 pm_runtime_put_sync(&mdp->pdev->dev);
1714
1715 return 0;
1716 }
1717
1718 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1719 {
1720 struct sh_eth_private *mdp = netdev_priv(ndev);
1721
1722 pm_runtime_get_sync(&mdp->pdev->dev);
1723
1724 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1725 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1726 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
1727 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1728 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1729 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
1730 if (sh_eth_is_gether(mdp)) {
1731 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1732 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1733 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1734 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1735 } else {
1736 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1737 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1738 }
1739 pm_runtime_put_sync(&mdp->pdev->dev);
1740
1741 return &ndev->stats;
1742 }
1743
1744 /* ioctl to device function */
1745 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1746 int cmd)
1747 {
1748 struct sh_eth_private *mdp = netdev_priv(ndev);
1749 struct phy_device *phydev = mdp->phydev;
1750
1751 if (!netif_running(ndev))
1752 return -EINVAL;
1753
1754 if (!phydev)
1755 return -ENODEV;
1756
1757 return phy_mii_ioctl(phydev, rq, cmd);
1758 }
1759
1760 #if defined(SH_ETH_HAS_TSU)
1761 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
1762 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
1763 int entry)
1764 {
1765 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
1766 }
1767
1768 static u32 sh_eth_tsu_get_post_mask(int entry)
1769 {
1770 return 0x0f << (28 - ((entry % 8) * 4));
1771 }
1772
1773 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
1774 {
1775 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
1776 }
1777
1778 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
1779 int entry)
1780 {
1781 struct sh_eth_private *mdp = netdev_priv(ndev);
1782 u32 tmp;
1783 void *reg_offset;
1784
1785 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
1786 tmp = ioread32(reg_offset);
1787 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
1788 }
1789
1790 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
1791 int entry)
1792 {
1793 struct sh_eth_private *mdp = netdev_priv(ndev);
1794 u32 post_mask, ref_mask, tmp;
1795 void *reg_offset;
1796
1797 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
1798 post_mask = sh_eth_tsu_get_post_mask(entry);
1799 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
1800
1801 tmp = ioread32(reg_offset);
1802 iowrite32(tmp & ~post_mask, reg_offset);
1803
1804 /* If other port enables, the function returns "true" */
1805 return tmp & ref_mask;
1806 }
1807
1808 static int sh_eth_tsu_busy(struct net_device *ndev)
1809 {
1810 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
1811 struct sh_eth_private *mdp = netdev_priv(ndev);
1812
1813 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
1814 udelay(10);
1815 timeout--;
1816 if (timeout <= 0) {
1817 dev_err(&ndev->dev, "%s: timeout\n", __func__);
1818 return -ETIMEDOUT;
1819 }
1820 }
1821
1822 return 0;
1823 }
1824
1825 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
1826 const u8 *addr)
1827 {
1828 u32 val;
1829
1830 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
1831 iowrite32(val, reg);
1832 if (sh_eth_tsu_busy(ndev) < 0)
1833 return -EBUSY;
1834
1835 val = addr[4] << 8 | addr[5];
1836 iowrite32(val, reg + 4);
1837 if (sh_eth_tsu_busy(ndev) < 0)
1838 return -EBUSY;
1839
1840 return 0;
1841 }
1842
1843 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
1844 {
1845 u32 val;
1846
1847 val = ioread32(reg);
1848 addr[0] = (val >> 24) & 0xff;
1849 addr[1] = (val >> 16) & 0xff;
1850 addr[2] = (val >> 8) & 0xff;
1851 addr[3] = val & 0xff;
1852 val = ioread32(reg + 4);
1853 addr[4] = (val >> 8) & 0xff;
1854 addr[5] = val & 0xff;
1855 }
1856
1857
1858 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
1859 {
1860 struct sh_eth_private *mdp = netdev_priv(ndev);
1861 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1862 int i;
1863 u8 c_addr[ETH_ALEN];
1864
1865 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
1866 sh_eth_tsu_read_entry(reg_offset, c_addr);
1867 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
1868 return i;
1869 }
1870
1871 return -ENOENT;
1872 }
1873
1874 static int sh_eth_tsu_find_empty(struct net_device *ndev)
1875 {
1876 u8 blank[ETH_ALEN];
1877 int entry;
1878
1879 memset(blank, 0, sizeof(blank));
1880 entry = sh_eth_tsu_find_entry(ndev, blank);
1881 return (entry < 0) ? -ENOMEM : entry;
1882 }
1883
1884 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
1885 int entry)
1886 {
1887 struct sh_eth_private *mdp = netdev_priv(ndev);
1888 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1889 int ret;
1890 u8 blank[ETH_ALEN];
1891
1892 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
1893 ~(1 << (31 - entry)), TSU_TEN);
1894
1895 memset(blank, 0, sizeof(blank));
1896 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
1897 if (ret < 0)
1898 return ret;
1899 return 0;
1900 }
1901
1902 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
1903 {
1904 struct sh_eth_private *mdp = netdev_priv(ndev);
1905 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1906 int i, ret;
1907
1908 if (!mdp->cd->tsu)
1909 return 0;
1910
1911 i = sh_eth_tsu_find_entry(ndev, addr);
1912 if (i < 0) {
1913 /* No entry found, create one */
1914 i = sh_eth_tsu_find_empty(ndev);
1915 if (i < 0)
1916 return -ENOMEM;
1917 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
1918 if (ret < 0)
1919 return ret;
1920
1921 /* Enable the entry */
1922 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
1923 (1 << (31 - i)), TSU_TEN);
1924 }
1925
1926 /* Entry found or created, enable POST */
1927 sh_eth_tsu_enable_cam_entry_post(ndev, i);
1928
1929 return 0;
1930 }
1931
1932 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
1933 {
1934 struct sh_eth_private *mdp = netdev_priv(ndev);
1935 int i, ret;
1936
1937 if (!mdp->cd->tsu)
1938 return 0;
1939
1940 i = sh_eth_tsu_find_entry(ndev, addr);
1941 if (i) {
1942 /* Entry found */
1943 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
1944 goto done;
1945
1946 /* Disable the entry if both ports was disabled */
1947 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
1948 if (ret < 0)
1949 return ret;
1950 }
1951 done:
1952 return 0;
1953 }
1954
1955 static int sh_eth_tsu_purge_all(struct net_device *ndev)
1956 {
1957 struct sh_eth_private *mdp = netdev_priv(ndev);
1958 int i, ret;
1959
1960 if (unlikely(!mdp->cd->tsu))
1961 return 0;
1962
1963 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
1964 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
1965 continue;
1966
1967 /* Disable the entry if both ports was disabled */
1968 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
1969 if (ret < 0)
1970 return ret;
1971 }
1972
1973 return 0;
1974 }
1975
1976 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
1977 {
1978 struct sh_eth_private *mdp = netdev_priv(ndev);
1979 u8 addr[ETH_ALEN];
1980 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1981 int i;
1982
1983 if (unlikely(!mdp->cd->tsu))
1984 return;
1985
1986 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
1987 sh_eth_tsu_read_entry(reg_offset, addr);
1988 if (is_multicast_ether_addr(addr))
1989 sh_eth_tsu_del_entry(ndev, addr);
1990 }
1991 }
1992
1993 /* Multicast reception directions set */
1994 static void sh_eth_set_multicast_list(struct net_device *ndev)
1995 {
1996 struct sh_eth_private *mdp = netdev_priv(ndev);
1997 u32 ecmr_bits;
1998 int mcast_all = 0;
1999 unsigned long flags;
2000
2001 spin_lock_irqsave(&mdp->lock, flags);
2002 /*
2003 * Initial condition is MCT = 1, PRM = 0.
2004 * Depending on ndev->flags, set PRM or clear MCT
2005 */
2006 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2007
2008 if (!(ndev->flags & IFF_MULTICAST)) {
2009 sh_eth_tsu_purge_mcast(ndev);
2010 mcast_all = 1;
2011 }
2012 if (ndev->flags & IFF_ALLMULTI) {
2013 sh_eth_tsu_purge_mcast(ndev);
2014 ecmr_bits &= ~ECMR_MCT;
2015 mcast_all = 1;
2016 }
2017
2018 if (ndev->flags & IFF_PROMISC) {
2019 sh_eth_tsu_purge_all(ndev);
2020 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2021 } else if (mdp->cd->tsu) {
2022 struct netdev_hw_addr *ha;
2023 netdev_for_each_mc_addr(ha, ndev) {
2024 if (mcast_all && is_multicast_ether_addr(ha->addr))
2025 continue;
2026
2027 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2028 if (!mcast_all) {
2029 sh_eth_tsu_purge_mcast(ndev);
2030 ecmr_bits &= ~ECMR_MCT;
2031 mcast_all = 1;
2032 }
2033 }
2034 }
2035 } else {
2036 /* Normal, unicast/broadcast-only mode. */
2037 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2038 }
2039
2040 /* update the ethernet mode */
2041 sh_eth_write(ndev, ecmr_bits, ECMR);
2042
2043 spin_unlock_irqrestore(&mdp->lock, flags);
2044 }
2045
2046 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2047 {
2048 if (!mdp->port)
2049 return TSU_VTAG0;
2050 else
2051 return TSU_VTAG1;
2052 }
2053
2054 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
2055 {
2056 struct sh_eth_private *mdp = netdev_priv(ndev);
2057 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2058
2059 if (unlikely(!mdp->cd->tsu))
2060 return -EPERM;
2061
2062 /* No filtering if vid = 0 */
2063 if (!vid)
2064 return 0;
2065
2066 mdp->vlan_num_ids++;
2067
2068 /*
2069 * The controller has one VLAN tag HW filter. So, if the filter is
2070 * already enabled, the driver disables it and the filte
2071 */
2072 if (mdp->vlan_num_ids > 1) {
2073 /* disable VLAN filter */
2074 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2075 return 0;
2076 }
2077
2078 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2079 vtag_reg_index);
2080
2081 return 0;
2082 }
2083
2084 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
2085 {
2086 struct sh_eth_private *mdp = netdev_priv(ndev);
2087 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2088
2089 if (unlikely(!mdp->cd->tsu))
2090 return -EPERM;
2091
2092 /* No filtering if vid = 0 */
2093 if (!vid)
2094 return 0;
2095
2096 mdp->vlan_num_ids--;
2097 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2098
2099 return 0;
2100 }
2101 #endif /* SH_ETH_HAS_TSU */
2102
2103 /* SuperH's TSU register init function */
2104 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2105 {
2106 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2107 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2108 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2109 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2110 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2111 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2112 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2113 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2114 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2115 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2116 if (sh_eth_is_gether(mdp)) {
2117 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2118 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2119 } else {
2120 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2121 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2122 }
2123 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2124 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2125 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2126 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2127 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2128 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2129 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2130 }
2131
2132 /* MDIO bus release function */
2133 static int sh_mdio_release(struct net_device *ndev)
2134 {
2135 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2136
2137 /* unregister mdio bus */
2138 mdiobus_unregister(bus);
2139
2140 /* remove mdio bus info from net_device */
2141 dev_set_drvdata(&ndev->dev, NULL);
2142
2143 /* free interrupts memory */
2144 kfree(bus->irq);
2145
2146 /* free bitbang info */
2147 free_mdio_bitbang(bus);
2148
2149 return 0;
2150 }
2151
2152 /* MDIO bus init function */
2153 static int sh_mdio_init(struct net_device *ndev, int id,
2154 struct sh_eth_plat_data *pd)
2155 {
2156 int ret, i;
2157 struct bb_info *bitbang;
2158 struct sh_eth_private *mdp = netdev_priv(ndev);
2159
2160 /* create bit control struct for PHY */
2161 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
2162 if (!bitbang) {
2163 ret = -ENOMEM;
2164 goto out;
2165 }
2166
2167 /* bitbang init */
2168 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2169 bitbang->set_gate = pd->set_mdio_gate;
2170 bitbang->mdi_msk = 0x08;
2171 bitbang->mdo_msk = 0x04;
2172 bitbang->mmd_msk = 0x02;/* MMD */
2173 bitbang->mdc_msk = 0x01;
2174 bitbang->ctrl.ops = &bb_ops;
2175
2176 /* MII controller setting */
2177 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2178 if (!mdp->mii_bus) {
2179 ret = -ENOMEM;
2180 goto out_free_bitbang;
2181 }
2182
2183 /* Hook up MII support for ethtool */
2184 mdp->mii_bus->name = "sh_mii";
2185 mdp->mii_bus->parent = &ndev->dev;
2186 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2187 mdp->pdev->name, id);
2188
2189 /* PHY IRQ */
2190 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
2191 if (!mdp->mii_bus->irq) {
2192 ret = -ENOMEM;
2193 goto out_free_bus;
2194 }
2195
2196 for (i = 0; i < PHY_MAX_ADDR; i++)
2197 mdp->mii_bus->irq[i] = PHY_POLL;
2198
2199 /* regist mdio bus */
2200 ret = mdiobus_register(mdp->mii_bus);
2201 if (ret)
2202 goto out_free_irq;
2203
2204 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2205
2206 return 0;
2207
2208 out_free_irq:
2209 kfree(mdp->mii_bus->irq);
2210
2211 out_free_bus:
2212 free_mdio_bitbang(mdp->mii_bus);
2213
2214 out_free_bitbang:
2215 kfree(bitbang);
2216
2217 out:
2218 return ret;
2219 }
2220
2221 static const u16 *sh_eth_get_register_offset(int register_type)
2222 {
2223 const u16 *reg_offset = NULL;
2224
2225 switch (register_type) {
2226 case SH_ETH_REG_GIGABIT:
2227 reg_offset = sh_eth_offset_gigabit;
2228 break;
2229 case SH_ETH_REG_FAST_SH4:
2230 reg_offset = sh_eth_offset_fast_sh4;
2231 break;
2232 case SH_ETH_REG_FAST_SH3_SH2:
2233 reg_offset = sh_eth_offset_fast_sh3_sh2;
2234 break;
2235 default:
2236 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
2237 break;
2238 }
2239
2240 return reg_offset;
2241 }
2242
2243 static const struct net_device_ops sh_eth_netdev_ops = {
2244 .ndo_open = sh_eth_open,
2245 .ndo_stop = sh_eth_close,
2246 .ndo_start_xmit = sh_eth_start_xmit,
2247 .ndo_get_stats = sh_eth_get_stats,
2248 #if defined(SH_ETH_HAS_TSU)
2249 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2250 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2251 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2252 #endif
2253 .ndo_tx_timeout = sh_eth_tx_timeout,
2254 .ndo_do_ioctl = sh_eth_do_ioctl,
2255 .ndo_validate_addr = eth_validate_addr,
2256 .ndo_set_mac_address = eth_mac_addr,
2257 .ndo_change_mtu = eth_change_mtu,
2258 };
2259
2260 static int sh_eth_drv_probe(struct platform_device *pdev)
2261 {
2262 int ret, devno = 0;
2263 struct resource *res;
2264 struct net_device *ndev = NULL;
2265 struct sh_eth_private *mdp = NULL;
2266 struct sh_eth_plat_data *pd;
2267
2268 /* get base addr */
2269 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2270 if (unlikely(res == NULL)) {
2271 dev_err(&pdev->dev, "invalid resource\n");
2272 ret = -EINVAL;
2273 goto out;
2274 }
2275
2276 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2277 if (!ndev) {
2278 ret = -ENOMEM;
2279 goto out;
2280 }
2281
2282 /* The sh Ether-specific entries in the device structure. */
2283 ndev->base_addr = res->start;
2284 devno = pdev->id;
2285 if (devno < 0)
2286 devno = 0;
2287
2288 ndev->dma = -1;
2289 ret = platform_get_irq(pdev, 0);
2290 if (ret < 0) {
2291 ret = -ENODEV;
2292 goto out_release;
2293 }
2294 ndev->irq = ret;
2295
2296 SET_NETDEV_DEV(ndev, &pdev->dev);
2297
2298 /* Fill in the fields of the device structure with ethernet values. */
2299 ether_setup(ndev);
2300
2301 mdp = netdev_priv(ndev);
2302 mdp->addr = ioremap(res->start, resource_size(res));
2303 if (mdp->addr == NULL) {
2304 ret = -ENOMEM;
2305 dev_err(&pdev->dev, "ioremap failed.\n");
2306 goto out_release;
2307 }
2308
2309 spin_lock_init(&mdp->lock);
2310 mdp->pdev = pdev;
2311 pm_runtime_enable(&pdev->dev);
2312 pm_runtime_resume(&pdev->dev);
2313
2314 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
2315 /* get PHY ID */
2316 mdp->phy_id = pd->phy;
2317 mdp->phy_interface = pd->phy_interface;
2318 /* EDMAC endian */
2319 mdp->edmac_endian = pd->edmac_endian;
2320 mdp->no_ether_link = pd->no_ether_link;
2321 mdp->ether_link_active_low = pd->ether_link_active_low;
2322 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2323
2324 /* set cpu data */
2325 #if defined(SH_ETH_HAS_BOTH_MODULES)
2326 mdp->cd = sh_eth_get_cpu_data(mdp);
2327 #else
2328 mdp->cd = &sh_eth_my_cpu_data;
2329 #endif
2330 sh_eth_set_default_cpu_data(mdp->cd);
2331
2332 /* set function */
2333 ndev->netdev_ops = &sh_eth_netdev_ops;
2334 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2335 ndev->watchdog_timeo = TX_TIMEOUT;
2336
2337 /* debug message level */
2338 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2339 mdp->post_rx = POST_RX >> (devno << 1);
2340 mdp->post_fw = POST_FW >> (devno << 1);
2341
2342 /* read and set MAC address */
2343 read_mac_address(ndev, pd->mac_addr);
2344
2345 /* ioremap the TSU registers */
2346 if (mdp->cd->tsu) {
2347 struct resource *rtsu;
2348 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2349 if (!rtsu) {
2350 dev_err(&pdev->dev, "Not found TSU resource\n");
2351 goto out_release;
2352 }
2353 mdp->tsu_addr = ioremap(rtsu->start,
2354 resource_size(rtsu));
2355 mdp->port = devno % 2;
2356 ndev->features = NETIF_F_HW_VLAN_FILTER;
2357 }
2358
2359 /* initialize first or needed device */
2360 if (!devno || pd->needs_init) {
2361 if (mdp->cd->chip_reset)
2362 mdp->cd->chip_reset(ndev);
2363
2364 if (mdp->cd->tsu) {
2365 /* TSU init (Init only)*/
2366 sh_eth_tsu_init(mdp);
2367 }
2368 }
2369
2370 /* network device register */
2371 ret = register_netdev(ndev);
2372 if (ret)
2373 goto out_release;
2374
2375 /* mdio bus init */
2376 ret = sh_mdio_init(ndev, pdev->id, pd);
2377 if (ret)
2378 goto out_unregister;
2379
2380 /* print device information */
2381 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2382 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2383
2384 platform_set_drvdata(pdev, ndev);
2385
2386 return ret;
2387
2388 out_unregister:
2389 unregister_netdev(ndev);
2390
2391 out_release:
2392 /* net_dev free */
2393 if (mdp && mdp->addr)
2394 iounmap(mdp->addr);
2395 if (mdp && mdp->tsu_addr)
2396 iounmap(mdp->tsu_addr);
2397 if (ndev)
2398 free_netdev(ndev);
2399
2400 out:
2401 return ret;
2402 }
2403
2404 static int sh_eth_drv_remove(struct platform_device *pdev)
2405 {
2406 struct net_device *ndev = platform_get_drvdata(pdev);
2407 struct sh_eth_private *mdp = netdev_priv(ndev);
2408
2409 if (mdp->cd->tsu)
2410 iounmap(mdp->tsu_addr);
2411 sh_mdio_release(ndev);
2412 unregister_netdev(ndev);
2413 pm_runtime_disable(&pdev->dev);
2414 iounmap(mdp->addr);
2415 free_netdev(ndev);
2416 platform_set_drvdata(pdev, NULL);
2417
2418 return 0;
2419 }
2420
2421 static int sh_eth_runtime_nop(struct device *dev)
2422 {
2423 /*
2424 * Runtime PM callback shared between ->runtime_suspend()
2425 * and ->runtime_resume(). Simply returns success.
2426 *
2427 * This driver re-initializes all registers after
2428 * pm_runtime_get_sync() anyway so there is no need
2429 * to save and restore registers here.
2430 */
2431 return 0;
2432 }
2433
2434 static struct dev_pm_ops sh_eth_dev_pm_ops = {
2435 .runtime_suspend = sh_eth_runtime_nop,
2436 .runtime_resume = sh_eth_runtime_nop,
2437 };
2438
2439 static struct platform_driver sh_eth_driver = {
2440 .probe = sh_eth_drv_probe,
2441 .remove = sh_eth_drv_remove,
2442 .driver = {
2443 .name = CARDNAME,
2444 .pm = &sh_eth_dev_pm_ops,
2445 },
2446 };
2447
2448 module_platform_driver(sh_eth_driver);
2449
2450 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2451 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2452 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.422649 seconds and 4 git commands to generate.