drivers/net/ethernet/renesas/sh_eth.h

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   4  *  Copyright (C) 2008-2012 Renesas Solutions Corp.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  */
  18
  19 #ifndef __SH_ETH_H__
  20 #define __SH_ETH_H__
  21
  22 #define CARDNAME        "sh-eth"
  23 #define TX_TIMEOUT      (5*HZ)
  24 #define TX_RING_SIZE    64      /* Tx ring size */
  25 #define RX_RING_SIZE    64      /* Rx ring size */
  26 #define TX_RING_MIN     64
  27 #define RX_RING_MIN     64
  28 #define TX_RING_MAX     1024
  29 #define RX_RING_MAX     1024
  30 #define PKT_BUF_SZ      1538
  31 #define SH_ETH_TSU_TIMEOUT_MS   500
  32 #define SH_ETH_TSU_CAM_ENTRIES  32
  33
  34 enum {
  35         /* IMPORTANT: To keep ethtool register dump working, add new
  36          * register names immediately before SH_ETH_MAX_REGISTER_OFFSET.
  37          */
  38
  39         /* E-DMAC registers */
  40         EDSR = 0,
  41         EDMR,
  42         EDTRR,
  43         EDRRR,
  44         EESR,
  45         EESIPR,
  46         TDLAR,
  47         TDFAR,
  48         TDFXR,
  49         TDFFR,
  50         RDLAR,
  51         RDFAR,
  52         RDFXR,
  53         RDFFR,
  54         TRSCER,
  55         RMFCR,
  56         TFTR,
  57         FDR,
  58         RMCR,
  59         EDOCR,
  60         TFUCR,
  61         RFOCR,
  62         RMIIMODE,
  63         FCFTR,
  64         RPADIR,
  65         TRIMD,
  66         RBWAR,
  67         TBRAR,
  68
  69         /* Ether registers */
  70         ECMR,
  71         ECSR,
  72         ECSIPR,
  73         PIR,
  74         PSR,
  75         RDMLR,
  76         PIPR,
  77         RFLR,
  78         IPGR,
  79         APR,
  80         MPR,
  81         PFTCR,
  82         PFRCR,
  83         RFCR,
  84         RFCF,
  85         TPAUSER,
  86         TPAUSECR,
  87         BCFR,
  88         BCFRR,
  89         GECMR,
  90         BCULR,
  91         MAHR,
  92         MALR,
  93         TROCR,
  94         CDCR,
  95         LCCR,
  96         CNDCR,
  97         CEFCR,
  98         FRECR,
  99         TSFRCR,
 100         TLFRCR,
 101         CERCR,
 102         CEECR,
 103         MAFCR,
 104         RTRATE,
 105         CSMR,
 106         RMII_MII,
 107
 108         /* TSU Absolute address */
 109         ARSTR,
 110         TSU_CTRST,
 111         TSU_FWEN0,
 112         TSU_FWEN1,
 113         TSU_FCM,
 114         TSU_BSYSL0,
 115         TSU_BSYSL1,
 116         TSU_PRISL0,
 117         TSU_PRISL1,
 118         TSU_FWSL0,
 119         TSU_FWSL1,
 120         TSU_FWSLC,
 121         TSU_QTAG0,
 122         TSU_QTAG1,
 123         TSU_QTAGM0,
 124         TSU_QTAGM1,
 125         TSU_FWSR,
 126         TSU_FWINMK,
 127         TSU_ADQT0,
 128         TSU_ADQT1,
 129         TSU_VTAG0,
 130         TSU_VTAG1,
 131         TSU_ADSBSY,
 132         TSU_TEN,
 133         TSU_POST1,
 134         TSU_POST2,
 135         TSU_POST3,
 136         TSU_POST4,
 137         TSU_ADRH0,
 138         /* TSU_ADR{H,L}{0..31} are assumed to be contiguous */
 139
 140         TXNLCR0,
 141         TXALCR0,
 142         RXNLCR0,
 143         RXALCR0,
 144         FWNLCR0,
 145         FWALCR0,
 146         TXNLCR1,
 147         TXALCR1,
 148         RXNLCR1,
 149         RXALCR1,
 150         FWNLCR1,
 151         FWALCR1,
 152
 153         /* This value must be written at last. */
 154         SH_ETH_MAX_REGISTER_OFFSET,
 155 };
 156
 157 enum {
 158         SH_ETH_REG_GIGABIT,
 159         SH_ETH_REG_FAST_RZ,
 160         SH_ETH_REG_FAST_RCAR,
 161         SH_ETH_REG_FAST_SH4,
 162         SH_ETH_REG_FAST_SH3_SH2
 163 };
 164
 165 /* Driver's parameters */
 166 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 167 #define SH_ETH_RX_ALIGN         32
 168 #else
 169 #define SH_ETH_RX_ALIGN         2
 170 #endif
 171
 172 /* Register's bits
 173  */
 174 /* EDSR : sh7734, sh7757, sh7763, r8a7740, and r7s72100 only */
 175 enum EDSR_BIT {
 176         EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 177 };
 178 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 179
 180 /* GECMR : sh7734, sh7763 and r8a7740 only */
 181 enum GECMR_BIT {
 182         GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
 183 };
 184
 185 /* EDMR */
 186 enum DMAC_M_BIT {
 187         EDMR_EL = 0x40, /* Litte endian */
 188         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 189         EDMR_SRST_GETHER = 0x03,
 190         EDMR_SRST_ETHER = 0x01,
 191 };
 192
 193 /* EDTRR */
 194 enum DMAC_T_BIT {
 195         EDTRR_TRNS_GETHER = 0x03,
 196         EDTRR_TRNS_ETHER = 0x01,
 197 };
 198
 199 /* EDRRR */
 200 enum EDRRR_R_BIT {
 201         EDRRR_R = 0x01,
 202 };
 203
 204 /* TPAUSER */
 205 enum TPAUSER_BIT {
 206         TPAUSER_TPAUSE = 0x0000ffff,
 207         TPAUSER_UNLIMITED = 0,
 208 };
 209
 210 /* BCFR */
 211 enum BCFR_BIT {
 212         BCFR_RPAUSE = 0x0000ffff,
 213         BCFR_UNLIMITED = 0,
 214 };
 215
 216 /* PIR */
 217 enum PIR_BIT {
 218         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 219 };
 220
 221 /* PSR */
 222 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 223
 224 /* EESR */
 225 enum EESR_BIT {
 226         EESR_TWB1       = 0x80000000,
 227         EESR_TWB        = 0x40000000,   /* same as TWB0 */
 228         EESR_TC1        = 0x20000000,
 229         EESR_TUC        = 0x10000000,
 230         EESR_ROC        = 0x08000000,
 231         EESR_TABT       = 0x04000000,
 232         EESR_RABT       = 0x02000000,
 233         EESR_RFRMER     = 0x01000000,   /* same as RFCOF */
 234         EESR_ADE        = 0x00800000,
 235         EESR_ECI        = 0x00400000,
 236         EESR_FTC        = 0x00200000,   /* same as TC or TC0 */
 237         EESR_TDE        = 0x00100000,
 238         EESR_TFE        = 0x00080000,   /* same as TFUF */
 239         EESR_FRC        = 0x00040000,   /* same as FR */
 240         EESR_RDE        = 0x00020000,
 241         EESR_RFE        = 0x00010000,
 242         EESR_CND        = 0x00000800,
 243         EESR_DLC        = 0x00000400,
 244         EESR_CD         = 0x00000200,
 245         EESR_RTO        = 0x00000100,
 246         EESR_RMAF       = 0x00000080,
 247         EESR_CEEF       = 0x00000040,
 248         EESR_CELF       = 0x00000020,
 249         EESR_RRF        = 0x00000010,
 250         EESR_RTLF       = 0x00000008,
 251         EESR_RTSF       = 0x00000004,
 252         EESR_PRE        = 0x00000002,
 253         EESR_CERF       = 0x00000001,
 254 };
 255
 256 #define EESR_RX_CHECK           (EESR_FRC  | /* Frame recv */           \
 257                                  EESR_RMAF | /* Multicast address recv */ \
 258                                  EESR_RRF  | /* Bit frame recv */       \
 259                                  EESR_RTLF | /* Long frame recv */      \
 260                                  EESR_RTSF | /* Short frame recv */     \
 261                                  EESR_PRE  | /* PHY-LSI recv error */   \
 262                                  EESR_CERF)  /* Recv frame CRC error */
 263
 264 #define DEFAULT_TX_CHECK        (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
 265                                  EESR_RTO)
 266 #define DEFAULT_EESR_ERR_CHECK  (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
 267                                  EESR_RDE | EESR_RFRMER | EESR_ADE | \
 268                                  EESR_TFE | EESR_TDE | EESR_ECI)
 269
 270 /* EESIPR */
 271 enum DMAC_IM_BIT {
 272         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 273         DMAC_M_RABT = 0x02000000,
 274         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 275         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 276         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 277         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 278         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 279         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 280         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 281         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 282         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 283         DMAC_M_RINT1 = 0x00000001,
 284 };
 285
 286 /* Receive descriptor bit */
 287 enum RD_STS_BIT {
 288         RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
 289         RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 290         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 291         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 292         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 293         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 294         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 295         RD_RFS1 = 0x00000001,
 296 };
 297 #define RDF1ST  RD_RFP1
 298 #define RDFEND  RD_RFP0
 299 #define RD_RFP  (RD_RFP1|RD_RFP0)
 300
 301 /* FCFTR */
 302 enum FCFTR_BIT {
 303         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 304         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 305         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 306 };
 307 #define DEFAULT_FIFO_F_D_RFF    (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
 308 #define DEFAULT_FIFO_F_D_RFD    (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
 309
 310 /* Transmit descriptor bit */
 311 enum TD_STS_BIT {
 312         TD_TACT = 0x80000000, TD_TDLE = 0x40000000,
 313         TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000,
 314         TD_TFE  = 0x08000000, TD_TWBI = 0x04000000,
 315 };
 316 #define TDF1ST  TD_TFP1
 317 #define TDFEND  TD_TFP0
 318 #define TD_TFP  (TD_TFP1|TD_TFP0)
 319
 320 /* RMCR */
 321 enum RMCR_BIT {
 322         RMCR_RNC = 0x00000001,
 323 };
 324
 325 /* ECMR */
 326 enum FELIC_MODE_BIT {
 327         ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
 328         ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 329         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 330         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 331         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 332         ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
 333         ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
 334 };
 335
 336 /* ECSR */
 337 enum ECSR_STATUS_BIT {
 338         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 339         ECSR_LCHNG = 0x04,
 340         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 341 };
 342
 343 #define DEFAULT_ECSR_INIT       (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
 344                                  ECSR_ICD | ECSIPR_MPDIP)
 345
 346 /* ECSIPR */
 347 enum ECSIPR_STATUS_MASK_BIT {
 348         ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
 349         ECSIPR_LCHNGIP = 0x04,
 350         ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
 351 };
 352
 353 #define DEFAULT_ECSIPR_INIT     (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
 354                                  ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 355
 356 /* APR */
 357 enum APR_BIT {
 358         APR_AP = 0x00000001,
 359 };
 360
 361 /* MPR */
 362 enum MPR_BIT {
 363         MPR_MP = 0x00000001,
 364 };
 365
 366 /* TRSCER */
 367 enum DESC_I_BIT {
 368         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 369         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 370         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 371         DESC_I_RINT1 = 0x0001,
 372 };
 373
 374 #define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2)
 375
 376 /* RPADIR */
 377 enum RPADIR_BIT {
 378         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 379         RPADIR_PADR = 0x0003f,
 380 };
 381
 382 /* FDR */
 383 #define DEFAULT_FDR_INIT        0x00000707
 384
 385 /* ARSTR */
 386 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
 387
 388 /* TSU_FWEN0 */
 389 enum TSU_FWEN0_BIT {
 390         TSU_FWEN0_0 = 0x00000001,
 391 };
 392
 393 /* TSU_ADSBSY */
 394 enum TSU_ADSBSY_BIT {
 395         TSU_ADSBSY_0 = 0x00000001,
 396 };
 397
 398 /* TSU_TEN */
 399 enum TSU_TEN_BIT {
 400         TSU_TEN_0 = 0x80000000,
 401 };
 402
 403 /* TSU_FWSL0 */
 404 enum TSU_FWSL0_BIT {
 405         TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
 406         TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
 407         TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
 408 };
 409
 410 /* TSU_FWSLC */
 411 enum TSU_FWSLC_BIT {
 412         TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
 413         TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
 414         TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
 415         TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
 416         TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
 417 };
 418
 419 /* TSU_VTAGn */
 420 #define TSU_VTAG_ENABLE         0x80000000
 421 #define TSU_VTAG_VID_MASK       0x00000fff
 422
 423 /* The sh ether Tx buffer descriptors.
 424  * This structure should be 20 bytes.
 425  */
 426 struct sh_eth_txdesc {
 427         u32 status;             /* TD0 */
 428 #if defined(__LITTLE_ENDIAN)
 429         u16 pad0;               /* TD1 */
 430         u16 buffer_length;      /* TD1 */
 431 #else
 432         u16 buffer_length;      /* TD1 */
 433         u16 pad0;               /* TD1 */
 434 #endif
 435         u32 addr;               /* TD2 */
 436         u32 pad1;               /* padding data */
 437 } __aligned(2) __packed;
 438
 439 /* The sh ether Rx buffer descriptors.
 440  * This structure should be 20 bytes.
 441  */
 442 struct sh_eth_rxdesc {
 443         u32 status;             /* RD0 */
 444 #if defined(__LITTLE_ENDIAN)
 445         u16 frame_length;       /* RD1 */
 446         u16 buffer_length;      /* RD1 */
 447 #else
 448         u16 buffer_length;      /* RD1 */
 449         u16 frame_length;       /* RD1 */
 450 #endif
 451         u32 addr;               /* RD2 */
 452         u32 pad0;               /* padding data */
 453 } __aligned(2) __packed;
 454
 455 /* This structure is used by each CPU dependency handling. */
 456 struct sh_eth_cpu_data {
 457         /* optional functions */
 458         void (*chip_reset)(struct net_device *ndev);
 459         void (*set_duplex)(struct net_device *ndev);
 460         void (*set_rate)(struct net_device *ndev);
 461
 462         /* mandatory initialize value */
 463         int register_type;
 464         u32 eesipr_value;
 465
 466         /* optional initialize value */
 467         u32 ecsr_value;
 468         u32 ecsipr_value;
 469         u32 fdr_value;
 470         u32 fcftr_value;
 471         u32 rpadir_value;
 472
 473         /* interrupt checking mask */
 474         u32 tx_check;
 475         u32 eesr_err_check;
 476
 477         /* Error mask */
 478         u32 trscer_err_mask;
 479
 480         /* hardware features */
 481         unsigned long irq_flags; /* IRQ configuration flags */
 482         unsigned no_psr:1;      /* EtherC DO NOT have PSR */
 483         unsigned apr:1;         /* EtherC have APR */
 484         unsigned mpr:1;         /* EtherC have MPR */
 485         unsigned tpauser:1;     /* EtherC have TPAUSER */
 486         unsigned bculr:1;       /* EtherC have BCULR */
 487         unsigned tsu:1;         /* EtherC have TSU */
 488         unsigned hw_swap:1;     /* E-DMAC have DE bit in EDMR */
 489         unsigned rpadir:1;      /* E-DMAC have RPADIR */
 490         unsigned no_trimd:1;    /* E-DMAC DO NOT have TRIMD */
 491         unsigned no_ade:1;      /* E-DMAC DO NOT have ADE bit in EESR */
 492         unsigned hw_crc:1;      /* E-DMAC have CSMR */
 493         unsigned select_mii:1;  /* EtherC have RMII_MII (MII select register) */
 494         unsigned shift_rd0:1;   /* shift Rx descriptor word 0 right by 16 */
 495         unsigned rmiimode:1;    /* EtherC has RMIIMODE register */
 496         unsigned rtrate:1;      /* EtherC has RTRATE register */
 497 };
 498
 499 struct sh_eth_private {
 500         struct platform_device *pdev;
 501         struct sh_eth_cpu_data *cd;
 502         const u16 *reg_offset;
 503         void __iomem *addr;
 504         void __iomem *tsu_addr;
 505         u32 num_rx_ring;
 506         u32 num_tx_ring;
 507         dma_addr_t rx_desc_dma;
 508         dma_addr_t tx_desc_dma;
 509         struct sh_eth_rxdesc *rx_ring;
 510         struct sh_eth_txdesc *tx_ring;
 511         struct sk_buff **rx_skbuff;
 512         struct sk_buff **tx_skbuff;
 513         spinlock_t lock;                /* Register access lock */
 514         u32 cur_rx, dirty_rx;           /* Producer/consumer ring indices */
 515         u32 cur_tx, dirty_tx;
 516         u32 rx_buf_sz;                  /* Based on MTU+slack. */
 517         int edmac_endian;
 518         struct napi_struct napi;
 519         bool irq_enabled;
 520         /* MII transceiver section. */
 521         u32 phy_id;                     /* PHY ID */
 522         struct mii_bus *mii_bus;        /* MDIO bus control */
 523         struct phy_device *phydev;      /* PHY device control */
 524         int link;
 525         phy_interface_t phy_interface;
 526         int msg_enable;
 527         int speed;
 528         int duplex;
 529         int port;                       /* for TSU */
 530         int vlan_num_ids;               /* for VLAN tag filter */
 531
 532         unsigned no_ether_link:1;
 533         unsigned ether_link_active_low:1;
 534         unsigned is_opened:1;
 535 };
 536
 537 static inline void sh_eth_soft_swap(char *src, int len)
 538 {
 539 #ifdef __LITTLE_ENDIAN__
 540         u32 *p = (u32 *)src;
 541         u32 *maxp;
 542         maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
 543
 544         for (; p < maxp; p++)
 545                 *p = swab32(*p);
 546 #endif
 547 }
 548
 549 #define SH_ETH_OFFSET_INVALID   ((u16) ~0)
 550
 551 static inline void sh_eth_write(struct net_device *ndev, u32 data,
 552                                 int enum_index)
 553 {
 554         struct sh_eth_private *mdp = netdev_priv(ndev);
 555         u16 offset = mdp->reg_offset[enum_index];
 556
 557         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 558                 return;
 559
 560         iowrite32(data, mdp->addr + offset);
 561 }
 562
 563 static inline u32 sh_eth_read(struct net_device *ndev, int enum_index)
 564 {
 565         struct sh_eth_private *mdp = netdev_priv(ndev);
 566         u16 offset = mdp->reg_offset[enum_index];
 567
 568         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 569                 return ~0U;
 570
 571         return ioread32(mdp->addr + offset);
 572 }
 573
 574 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
 575                                           int enum_index)
 576 {
 577         return mdp->tsu_addr + mdp->reg_offset[enum_index];
 578 }
 579
 580 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
 581                                     int enum_index)
 582 {
 583         iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
 584 }
 585
 586 static inline u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
 587 {
 588         return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
 589 }
 590
 591 #endif  /* #ifndef __SH_ETH_H__ */