drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h

   1 /* 10G controller driver for Samsung SoCs
   2  *
   3  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __SXGBE_COMMON_H__
  14 #define __SXGBE_COMMON_H__
  15
  16 /* forward references */
  17 struct sxgbe_desc_ops;
  18 struct sxgbe_dma_ops;
  19 struct sxgbe_mtl_ops;
  20
  21 #define SXGBE_RESOURCE_NAME     "sam_sxgbeeth"
  22 #define DRV_MODULE_VERSION      "November_2013"
  23
  24 /* MAX HW feature words */
  25 #define SXGBE_HW_WORDS 3
  26
  27 #define SXGBE_RX_COE_NONE       0
  28
  29 /* CSR Frequency Access Defines*/
  30 #define SXGBE_CSR_F_150M        150000000
  31 #define SXGBE_CSR_F_250M        250000000
  32 #define SXGBE_CSR_F_300M        300000000
  33 #define SXGBE_CSR_F_350M        350000000
  34 #define SXGBE_CSR_F_400M        400000000
  35 #define SXGBE_CSR_F_500M        500000000
  36
  37 /* pause time */
  38 #define SXGBE_PAUSE_TIME 0x200
  39
  40 /* tx queues */
  41 #define SXGBE_TX_QUEUES   8
  42 #define SXGBE_RX_QUEUES   16
  43
  44 /* Calculated based how much time does it take to fill 256KB Rx memory
  45  * at 10Gb speed at 156MHz clock rate and considered little less then
  46  * the actual value.
  47  */
  48 #define SXGBE_MAX_DMA_RIWT      0x70
  49 #define SXGBE_MIN_DMA_RIWT      0x01
  50
  51 /* Tx coalesce parameters */
  52 #define SXGBE_COAL_TX_TIMER     40000
  53 #define SXGBE_MAX_COAL_TX_TICK  100000
  54 #define SXGBE_TX_MAX_FRAMES     512
  55 #define SXGBE_TX_FRAMES 128
  56
  57 /* SXGBE TX FIFO is 8K, Rx FIFO is 16K */
  58 #define BUF_SIZE_16KiB 16384
  59 #define BUF_SIZE_8KiB 8192
  60 #define BUF_SIZE_4KiB 4096
  61 #define BUF_SIZE_2KiB 2048
  62
  63 #define SXGBE_DEFAULT_LIT_LS    0x3E8
  64 #define SXGBE_DEFAULT_TWT_LS    0x0
  65
  66 /* Flow Control defines */
  67 #define SXGBE_FLOW_OFF          0
  68 #define SXGBE_FLOW_RX           1
  69 #define SXGBE_FLOW_TX           2
  70 #define SXGBE_FLOW_AUTO         (SXGBE_FLOW_TX | SXGBE_FLOW_RX)
  71
  72 #define SF_DMA_MODE 1           /* DMA STORE-AND-FORWARD Operation Mode */
  73
  74 /* errors */
  75 #define RX_GMII_ERR             0x01
  76 #define RX_WATCHDOG_ERR         0x02
  77 #define RX_CRC_ERR              0x03
  78 #define RX_GAINT_ERR            0x04
  79 #define RX_IP_HDR_ERR           0x05
  80 #define RX_PAYLOAD_ERR          0x06
  81 #define RX_OVERFLOW_ERR         0x07
  82
  83 /* pkt type */
  84 #define RX_LEN_PKT              0x00
  85 #define RX_MACCTL_PKT           0x01
  86 #define RX_DCBCTL_PKT           0x02
  87 #define RX_ARP_PKT              0x03
  88 #define RX_OAM_PKT              0x04
  89 #define RX_UNTAG_PKT            0x05
  90 #define RX_OTHER_PKT            0x07
  91 #define RX_SVLAN_PKT            0x08
  92 #define RX_CVLAN_PKT            0x09
  93 #define RX_DVLAN_OCVLAN_ICVLAN_PKT              0x0A
  94 #define RX_DVLAN_OSVLAN_ISVLAN_PKT              0x0B
  95 #define RX_DVLAN_OSVLAN_ICVLAN_PKT              0x0C
  96 #define RX_DVLAN_OCVLAN_ISVLAN_PKT              0x0D
  97
  98 #define RX_NOT_IP_PKT           0x00
  99 #define RX_IPV4_TCP_PKT         0x01
 100 #define RX_IPV4_UDP_PKT         0x02
 101 #define RX_IPV4_ICMP_PKT        0x03
 102 #define RX_IPV4_UNKNOWN_PKT     0x07
 103 #define RX_IPV6_TCP_PKT         0x09
 104 #define RX_IPV6_UDP_PKT         0x0A
 105 #define RX_IPV6_ICMP_PKT        0x0B
 106 #define RX_IPV6_UNKNOWN_PKT     0x0F
 107
 108 #define RX_NO_PTP               0x00
 109 #define RX_PTP_SYNC             0x01
 110 #define RX_PTP_FOLLOW_UP        0x02
 111 #define RX_PTP_DELAY_REQ        0x03
 112 #define RX_PTP_DELAY_RESP       0x04
 113 #define RX_PTP_PDELAY_REQ       0x05
 114 #define RX_PTP_PDELAY_RESP      0x06
 115 #define RX_PTP_PDELAY_FOLLOW_UP 0x07
 116 #define RX_PTP_ANNOUNCE         0x08
 117 #define RX_PTP_MGMT             0x09
 118 #define RX_PTP_SIGNAL           0x0A
 119 #define RX_PTP_RESV_MSG         0x0F
 120
 121 enum dma_irq_status {
 122         tx_hard_error   = BIT(0),
 123         tx_bump_tc      = BIT(1),
 124         handle_tx       = BIT(2),
 125         rx_hard_error   = BIT(3),
 126         rx_bump_tc      = BIT(4),
 127         handle_rx       = BIT(5),
 128 };
 129
 130 #define NETIF_F_HW_VLAN_ALL     (NETIF_F_HW_VLAN_CTAG_RX |      \
 131                                  NETIF_F_HW_VLAN_STAG_RX |      \
 132                                  NETIF_F_HW_VLAN_CTAG_TX |      \
 133                                  NETIF_F_HW_VLAN_STAG_TX |      \
 134                                  NETIF_F_HW_VLAN_CTAG_FILTER |  \
 135                                  NETIF_F_HW_VLAN_STAG_FILTER)
 136
 137 /* MMC control defines */
 138 #define SXGBE_MMC_CTRL_CNT_FRZ  0x00000008
 139
 140 /* SXGBE HW ADDR regs */
 141 #define SXGBE_ADDR_HIGH(reg)    (((reg > 15) ? 0x00000800 : 0x00000040) + \
 142                                  (reg * 8))
 143 #define SXGBE_ADDR_LOW(reg)     (((reg > 15) ? 0x00000804 : 0x00000044) + \
 144                                  (reg * 8))
 145 #define SXGBE_MAX_PERFECT_ADDRESSES 32 /* Maximum unicast perfect filtering */
 146 #define SXGBE_FRAME_FILTER       0x00000004      /* Frame Filter */
 147
 148 /* SXGBE Frame Filter defines */
 149 #define SXGBE_FRAME_FILTER_PR    0x00000001      /* Promiscuous Mode */
 150 #define SXGBE_FRAME_FILTER_HUC   0x00000002      /* Hash Unicast */
 151 #define SXGBE_FRAME_FILTER_HMC   0x00000004      /* Hash Multicast */
 152 #define SXGBE_FRAME_FILTER_DAIF  0x00000008      /* DA Inverse Filtering */
 153 #define SXGBE_FRAME_FILTER_PM    0x00000010      /* Pass all multicast */
 154 #define SXGBE_FRAME_FILTER_DBF   0x00000020      /* Disable Broadcast frames */
 155 #define SXGBE_FRAME_FILTER_SAIF  0x00000100      /* Inverse Filtering */
 156 #define SXGBE_FRAME_FILTER_SAF   0x00000200      /* Source Address Filter */
 157 #define SXGBE_FRAME_FILTER_HPF   0x00000400      /* Hash or perfect Filter */
 158 #define SXGBE_FRAME_FILTER_RA    0x80000000      /* Receive all mode */
 159
 160 #define SXGBE_HASH_TABLE_SIZE    64
 161 #define SXGBE_HASH_HIGH          0x00000008      /* Multicast Hash Table High */
 162 #define SXGBE_HASH_LOW           0x0000000c      /* Multicast Hash Table Low */
 163
 164 #define SXGBE_HI_REG_AE          0x80000000
 165
 166 /* Minimum and maximum MTU */
 167 #define MIN_MTU         68
 168 #define MAX_MTU         9000
 169
 170 #define SXGBE_FOR_EACH_QUEUE(max_queues, queue_num)                     \
 171         for (queue_num = 0; queue_num < max_queues; queue_num++)
 172
 173 /* sxgbe statistics counters */
 174 struct sxgbe_extra_stats {
 175         /* TX/RX IRQ events */
 176         unsigned long tx_underflow_irq;
 177         unsigned long tx_process_stopped_irq;
 178         unsigned long tx_ctxt_desc_err;
 179         unsigned long tx_threshold;
 180         unsigned long rx_threshold;
 181         unsigned long tx_pkt_n;
 182         unsigned long rx_pkt_n;
 183         unsigned long normal_irq_n;
 184         unsigned long tx_normal_irq_n;
 185         unsigned long rx_normal_irq_n;
 186         unsigned long napi_poll;
 187         unsigned long tx_clean;
 188         unsigned long tx_reset_ic_bit;
 189         unsigned long rx_process_stopped_irq;
 190         unsigned long rx_underflow_irq;
 191
 192         /* Bus access errors */
 193         unsigned long fatal_bus_error_irq;
 194         unsigned long tx_read_transfer_err;
 195         unsigned long tx_write_transfer_err;
 196         unsigned long tx_desc_access_err;
 197         unsigned long tx_buffer_access_err;
 198         unsigned long tx_data_transfer_err;
 199         unsigned long rx_read_transfer_err;
 200         unsigned long rx_write_transfer_err;
 201         unsigned long rx_desc_access_err;
 202         unsigned long rx_buffer_access_err;
 203         unsigned long rx_data_transfer_err;
 204
 205         /* RX specific */
 206         /* L2 error */
 207         unsigned long rx_code_gmii_err;
 208         unsigned long rx_watchdog_err;
 209         unsigned long rx_crc_err;
 210         unsigned long rx_gaint_pkt_err;
 211         unsigned long ip_hdr_err;
 212         unsigned long ip_payload_err;
 213         unsigned long overflow_error;
 214
 215         /* L2 Pkt type */
 216         unsigned long len_pkt;
 217         unsigned long mac_ctl_pkt;
 218         unsigned long dcb_ctl_pkt;
 219         unsigned long arp_pkt;
 220         unsigned long oam_pkt;
 221         unsigned long untag_okt;
 222         unsigned long other_pkt;
 223         unsigned long svlan_tag_pkt;
 224         unsigned long cvlan_tag_pkt;
 225         unsigned long dvlan_ocvlan_icvlan_pkt;
 226         unsigned long dvlan_osvlan_isvlan_pkt;
 227         unsigned long dvlan_osvlan_icvlan_pkt;
 228         unsigned long dvan_ocvlan_icvlan_pkt;
 229
 230         /* L3/L4 Pkt type */
 231         unsigned long not_ip_pkt;
 232         unsigned long ip4_tcp_pkt;
 233         unsigned long ip4_udp_pkt;
 234         unsigned long ip4_icmp_pkt;
 235         unsigned long ip4_unknown_pkt;
 236         unsigned long ip6_tcp_pkt;
 237         unsigned long ip6_udp_pkt;
 238         unsigned long ip6_icmp_pkt;
 239         unsigned long ip6_unknown_pkt;
 240
 241         /* Filter specific */
 242         unsigned long vlan_filter_match;
 243         unsigned long sa_filter_fail;
 244         unsigned long da_filter_fail;
 245         unsigned long hash_filter_pass;
 246         unsigned long l3_filter_match;
 247         unsigned long l4_filter_match;
 248
 249         /* RX context specific */
 250         unsigned long timestamp_dropped;
 251         unsigned long rx_msg_type_no_ptp;
 252         unsigned long rx_ptp_type_sync;
 253         unsigned long rx_ptp_type_follow_up;
 254         unsigned long rx_ptp_type_delay_req;
 255         unsigned long rx_ptp_type_delay_resp;
 256         unsigned long rx_ptp_type_pdelay_req;
 257         unsigned long rx_ptp_type_pdelay_resp;
 258         unsigned long rx_ptp_type_pdelay_follow_up;
 259         unsigned long rx_ptp_announce;
 260         unsigned long rx_ptp_mgmt;
 261         unsigned long rx_ptp_signal;
 262         unsigned long rx_ptp_resv_msg_type;
 263 };
 264
 265 struct mac_link {
 266         int port;
 267         int duplex;
 268         int speed;
 269 };
 270
 271 struct mii_regs {
 272         unsigned int addr;      /* MII Address */
 273         unsigned int data;      /* MII Data */
 274 };
 275
 276 struct sxgbe_core_ops {
 277         /* MAC core initialization */
 278         void (*core_init)(void __iomem *ioaddr);
 279         /* Dump MAC registers */
 280         void (*dump_regs)(void __iomem *ioaddr);
 281         /* Handle extra events on specific interrupts hw dependent */
 282         int (*host_irq_status)(void __iomem *ioaddr,
 283                                struct sxgbe_extra_stats *x);
 284         /* Set power management mode (e.g. magic frame) */
 285         void (*pmt)(void __iomem *ioaddr, unsigned long mode);
 286         /* Set/Get Unicast MAC addresses */
 287         void (*set_umac_addr)(void __iomem *ioaddr, unsigned char *addr,
 288                               unsigned int reg_n);
 289         void (*get_umac_addr)(void __iomem *ioaddr, unsigned char *addr,
 290                               unsigned int reg_n);
 291         void (*enable_rx)(void __iomem *ioaddr, bool enable);
 292         void (*enable_tx)(void __iomem *ioaddr, bool enable);
 293
 294         /* controller version specific operations */
 295         int (*get_controller_version)(void __iomem *ioaddr);
 296
 297         /* If supported then get the optional core features */
 298         unsigned int (*get_hw_feature)(void __iomem *ioaddr,
 299                                        unsigned char feature_index);
 300         /* adjust SXGBE speed */
 301         void (*set_speed)(void __iomem *ioaddr, unsigned char speed);
 302 };
 303
 304 const struct sxgbe_core_ops *sxgbe_get_core_ops(void);
 305
 306 struct sxgbe_ops {
 307         const struct sxgbe_core_ops *mac;
 308         const struct sxgbe_desc_ops *desc;
 309         const struct sxgbe_dma_ops *dma;
 310         const struct sxgbe_mtl_ops *mtl;
 311         struct mii_regs mii;    /* MII register Addresses */
 312         struct mac_link link;
 313         unsigned int ctrl_uid;
 314         unsigned int ctrl_id;
 315 };
 316
 317 /* SXGBE private data structures */
 318 struct sxgbe_tx_queue {
 319         unsigned int irq_no;
 320         struct sxgbe_priv_data *priv_ptr;
 321         struct sxgbe_tx_norm_desc *dma_tx;
 322         dma_addr_t dma_tx_phy;
 323         dma_addr_t *tx_skbuff_dma;
 324         struct sk_buff **tx_skbuff;
 325         struct timer_list txtimer;
 326         spinlock_t tx_lock;     /* lock for tx queues */
 327         unsigned int cur_tx;
 328         unsigned int dirty_tx;
 329         u32 tx_count_frames;
 330         u32 tx_coal_frames;
 331         u32 tx_coal_timer;
 332         int hwts_tx_en;
 333         u8 queue_no;
 334 };
 335
 336 struct sxgbe_rx_queue {
 337         struct sxgbe_priv_data *priv_ptr;
 338         struct sxgbe_rx_norm_desc *dma_rx;
 339         struct sk_buff **rx_skbuff;
 340         unsigned int cur_rx;
 341         unsigned int dirty_rx;
 342         unsigned int irq_no;
 343         u32 rx_riwt;
 344         dma_addr_t *rx_skbuff_dma;
 345         dma_addr_t dma_rx_phy;
 346         u8 queue_no;
 347 };
 348
 349 /* SXGBE HW capabilities */
 350 struct sxgbe_hw_features {
 351         /****** CAP [0] *******/
 352         unsigned int pmt_remote_wake_up;
 353         unsigned int pmt_magic_frame;
 354         /* IEEE 1588-2008 */
 355         unsigned int atime_stamp;
 356
 357         unsigned int tx_csum_offload;
 358         unsigned int rx_csum_offload;
 359         unsigned int multi_macaddr;
 360         unsigned int tstamp_srcselect;
 361         unsigned int sa_vlan_insert;
 362
 363         /****** CAP [1] *******/
 364         unsigned int rxfifo_size;
 365         unsigned int txfifo_size;
 366         unsigned int atstmap_hword;
 367         unsigned int dcb_enable;
 368         unsigned int splithead_enable;
 369         unsigned int tcpseg_offload;
 370         unsigned int debug_mem;
 371         unsigned int rss_enable;
 372         unsigned int hash_tsize;
 373         unsigned int l3l4_filer_size;
 374
 375         /* This value is in bytes and
 376          * as mentioned in HW features
 377          * of SXGBE data book
 378          */
 379         unsigned int rx_mtl_qsize;
 380         unsigned int tx_mtl_qsize;
 381
 382         /****** CAP [2] *******/
 383         /* TX and RX number of channels */
 384         unsigned int rx_mtl_queues;
 385         unsigned int tx_mtl_queues;
 386         unsigned int rx_dma_channels;
 387         unsigned int tx_dma_channels;
 388         unsigned int pps_output_count;
 389         unsigned int aux_input_count;
 390 };
 391
 392 struct sxgbe_priv_data {
 393         /* DMA descriptos */
 394         struct sxgbe_tx_queue *txq[SXGBE_TX_QUEUES];
 395         struct sxgbe_rx_queue *rxq[SXGBE_RX_QUEUES];
 396         u8 cur_rx_qnum;
 397
 398         unsigned int dma_tx_size;
 399         unsigned int dma_rx_size;
 400         unsigned int dma_buf_sz;
 401         u32 rx_riwt;
 402
 403         struct napi_struct napi;
 404
 405         void __iomem *ioaddr;
 406         struct net_device *dev;
 407         struct device *device;
 408         struct sxgbe_ops *hw;   /* sxgbe specific ops */
 409         int no_csum_insertion;
 410         int irq;
 411         spinlock_t stats_lock;  /* lock for tx/rx statatics */
 412
 413         struct phy_device *phydev;
 414         int oldlink;
 415         int speed;
 416         int oldduplex;
 417         struct mii_bus *mii;
 418         int mii_irq[PHY_MAX_ADDR];
 419         u8 rx_pause;
 420         u8 tx_pause;
 421
 422         struct sxgbe_extra_stats xstats;
 423         struct sxgbe_plat_data *plat;
 424         struct sxgbe_hw_features hw_cap;
 425
 426         u32 msg_enable;
 427
 428         struct clk *sxgbe_clk;
 429         int clk_csr;
 430         unsigned int mode;
 431         unsigned int default_addend;
 432
 433         /* advanced time stamp support */
 434         u32 adv_ts;
 435         int use_riwt;
 436
 437         /* tc control */
 438         int tx_tc;
 439         int rx_tc;
 440 };
 441
 442 /* Function prototypes */
 443 struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
 444                                         struct sxgbe_plat_data *plat_dat,
 445                                         void __iomem *addr);
 446 int sxgbe_drv_remove(struct net_device *ndev);
 447 void sxgbe_set_ethtool_ops(struct net_device *netdev);
 448 int sxgbe_mdio_unregister(struct net_device *ndev);
 449 int sxgbe_mdio_register(struct net_device *ndev);
 450 int sxgbe_register_platform(void);
 451 void sxgbe_unregister_platform(void);
 452
 453 #ifdef CONFIG_PM
 454 int sxgbe_suspend(struct net_device *ndev);
 455 int sxgbe_resume(struct net_device *ndev);
 456 int sxgbe_freeze(struct net_device *ndev);
 457 int sxgbe_restore(struct net_device *ndev);
 458 #endif /* CONFIG_PM */
 459
 460 const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void);
 461
 462 #endif /* __SXGBE_COMMON_H__ */