1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include "net_driver.h"
11 #include "ef10_regs.h"
14 #include "mcdi_pcol.h"
16 #include "workarounds.h"
19 #include <linux/jhash.h>
20 #include <linux/wait.h>
21 #include <linux/workqueue.h>
23 /* Hardware control for EF10 architecture including 'Huntington'. */
25 #define EFX_EF10_DRVGEN_EV 7
31 /* The reserved RSS context value */
32 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The filter table(s) are managed by firmware and we have write-only
35 * access. When removing filters we must identify them to the
36 * firmware by a 64-bit handle, but this is too wide for Linux kernel
37 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
38 * be able to tell in advance whether a requested insertion will
39 * replace an existing filter. Therefore we maintain a software hash
40 * table, which should be at least as large as the hardware hash
43 * Huntington has a single 8K filter table shared between all filter
44 * types and both ports.
46 #define HUNT_FILTER_TBL_ROWS 8192
48 struct efx_ef10_filter_table
{
49 /* The RX match field masks supported by this fw & hw, in order of priority */
50 enum efx_filter_match_flags rx_match_flags
[
51 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM
];
52 unsigned int rx_match_count
;
55 unsigned long spec
; /* pointer to spec plus flag bits */
56 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
57 * used to mark and sweep MAC filters for the device address lists.
59 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
60 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
61 #define EFX_EF10_FILTER_FLAGS 3UL
62 u64 handle
; /* firmware handle */
64 wait_queue_head_t waitq
;
65 /* Shadow of net_device address lists, guarded by mac_lock */
66 #define EFX_EF10_FILTER_DEV_UC_MAX 32
67 #define EFX_EF10_FILTER_DEV_MC_MAX 256
71 } dev_uc_list
[EFX_EF10_FILTER_DEV_UC_MAX
],
72 dev_mc_list
[EFX_EF10_FILTER_DEV_MC_MAX
];
73 int dev_uc_count
; /* negative for PROMISC */
74 int dev_mc_count
; /* negative for PROMISC/ALLMULTI */
77 /* An arbitrary search limit for the software hash table */
78 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
80 static void efx_ef10_rx_push_rss_config(struct efx_nic
*efx
);
81 static void efx_ef10_rx_free_indir_table(struct efx_nic
*efx
);
82 static void efx_ef10_filter_table_remove(struct efx_nic
*efx
);
84 static int efx_ef10_get_warm_boot_count(struct efx_nic
*efx
)
88 efx_readd(efx
, ®
, ER_DZ_BIU_MC_SFT_STATUS
);
89 return EFX_DWORD_FIELD(reg
, EFX_WORD_1
) == 0xb007 ?
90 EFX_DWORD_FIELD(reg
, EFX_WORD_0
) : -EIO
;
93 static unsigned int efx_ef10_mem_map_size(struct efx_nic
*efx
)
95 return resource_size(&efx
->pci_dev
->resource
[EFX_MEM_BAR
]);
98 static int efx_ef10_init_datapath_caps(struct efx_nic
*efx
)
100 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_CAPABILITIES_OUT_LEN
);
101 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
105 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN
!= 0);
107 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_CAPABILITIES
, NULL
, 0,
108 outbuf
, sizeof(outbuf
), &outlen
);
111 if (outlen
< sizeof(outbuf
)) {
112 netif_err(efx
, drv
, efx
->net_dev
,
113 "unable to read datapath firmware capabilities\n");
117 nic_data
->datapath_caps
=
118 MCDI_DWORD(outbuf
, GET_CAPABILITIES_OUT_FLAGS1
);
120 if (!(nic_data
->datapath_caps
&
121 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN
))) {
122 netif_err(efx
, drv
, efx
->net_dev
,
123 "current firmware does not support TSO\n");
127 if (!(nic_data
->datapath_caps
&
128 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN
))) {
129 netif_err(efx
, probe
, efx
->net_dev
,
130 "current firmware does not support an RX prefix\n");
137 static int efx_ef10_get_sysclk_freq(struct efx_nic
*efx
)
139 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_CLOCK_OUT_LEN
);
142 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_CLOCK
, NULL
, 0,
143 outbuf
, sizeof(outbuf
), NULL
);
146 rc
= MCDI_DWORD(outbuf
, GET_CLOCK_OUT_SYS_FREQ
);
147 return rc
> 0 ? rc
: -ERANGE
;
150 static int efx_ef10_get_mac_address(struct efx_nic
*efx
, u8
*mac_address
)
152 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN
);
156 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN
!= 0);
158 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_MAC_ADDRESSES
, NULL
, 0,
159 outbuf
, sizeof(outbuf
), &outlen
);
162 if (outlen
< MC_CMD_GET_MAC_ADDRESSES_OUT_LEN
)
165 ether_addr_copy(mac_address
,
166 MCDI_PTR(outbuf
, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE
));
170 static int efx_ef10_probe(struct efx_nic
*efx
)
172 struct efx_ef10_nic_data
*nic_data
;
175 /* We can have one VI for each 8K region. However, until we
176 * use TX option descriptors we need two TX queues per channel.
181 resource_size(&efx
->pci_dev
->resource
[EFX_MEM_BAR
]) /
182 (EFX_VI_PAGE_SIZE
* EFX_TXQ_TYPES
));
183 BUG_ON(efx
->max_channels
== 0);
185 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
188 efx
->nic_data
= nic_data
;
190 rc
= efx_nic_alloc_buffer(efx
, &nic_data
->mcdi_buf
,
191 8 + MCDI_CTL_SDU_LEN_MAX_V2
, GFP_KERNEL
);
195 /* Get the MC's warm boot count. In case it's rebooting right
196 * now, be prepared to retry.
200 rc
= efx_ef10_get_warm_boot_count(efx
);
207 nic_data
->warm_boot_count
= rc
;
209 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
211 /* In case we're recovering from a crash (kexec), we want to
212 * cancel any outstanding request by the previous user of this
213 * function. We send a special message using the least
214 * significant bits of the 'high' (doorbell) register.
216 _efx_writed(efx
, cpu_to_le32(1), ER_DZ_MC_DB_HWRD
);
218 rc
= efx_mcdi_init(efx
);
222 /* Reset (most) configuration for this function */
223 rc
= efx_mcdi_reset(efx
, RESET_TYPE_ALL
);
227 /* Enable event logging */
228 rc
= efx_mcdi_log_ctrl(efx
, true, false, 0);
232 rc
= efx_ef10_init_datapath_caps(efx
);
236 efx
->rx_packet_len_offset
=
237 ES_DZ_RX_PREFIX_PKTLEN_OFST
- ES_DZ_RX_PREFIX_SIZE
;
239 rc
= efx_mcdi_port_get_number(efx
);
244 rc
= efx_ef10_get_mac_address(efx
, efx
->net_dev
->perm_addr
);
248 rc
= efx_ef10_get_sysclk_freq(efx
);
251 efx
->timer_quantum_ns
= 1536000 / rc
; /* 1536 cycles */
253 /* Check whether firmware supports bug 35388 workaround */
254 rc
= efx_mcdi_set_workaround(efx
, MC_CMD_WORKAROUND_BUG35388
, true);
256 nic_data
->workaround_35388
= true;
257 else if (rc
!= -ENOSYS
&& rc
!= -ENOENT
)
259 netif_dbg(efx
, probe
, efx
->net_dev
,
260 "workaround for bug 35388 is %sabled\n",
261 nic_data
->workaround_35388
? "en" : "dis");
263 rc
= efx_mcdi_mon_probe(efx
);
267 efx_ptp_probe(efx
, NULL
);
274 efx_nic_free_buffer(efx
, &nic_data
->mcdi_buf
);
277 efx
->nic_data
= NULL
;
281 static int efx_ef10_free_vis(struct efx_nic
*efx
)
283 MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf
, 0);
285 int rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FREE_VIS
, NULL
, 0,
286 outbuf
, sizeof(outbuf
), &outlen
);
288 /* -EALREADY means nothing to free, so ignore */
292 efx_mcdi_display_error(efx
, MC_CMD_FREE_VIS
, 0, outbuf
, outlen
,
299 static void efx_ef10_free_piobufs(struct efx_nic
*efx
)
301 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
302 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FREE_PIOBUF_IN_LEN
);
306 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN
!= 0);
308 for (i
= 0; i
< nic_data
->n_piobufs
; i
++) {
309 MCDI_SET_DWORD(inbuf
, FREE_PIOBUF_IN_PIOBUF_HANDLE
,
310 nic_data
->piobuf_handle
[i
]);
311 rc
= efx_mcdi_rpc(efx
, MC_CMD_FREE_PIOBUF
, inbuf
, sizeof(inbuf
),
316 nic_data
->n_piobufs
= 0;
319 static int efx_ef10_alloc_piobufs(struct efx_nic
*efx
, unsigned int n
)
321 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
322 MCDI_DECLARE_BUF(outbuf
, MC_CMD_ALLOC_PIOBUF_OUT_LEN
);
327 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN
!= 0);
329 for (i
= 0; i
< n
; i
++) {
330 rc
= efx_mcdi_rpc(efx
, MC_CMD_ALLOC_PIOBUF
, NULL
, 0,
331 outbuf
, sizeof(outbuf
), &outlen
);
334 if (outlen
< MC_CMD_ALLOC_PIOBUF_OUT_LEN
) {
338 nic_data
->piobuf_handle
[i
] =
339 MCDI_DWORD(outbuf
, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE
);
340 netif_dbg(efx
, probe
, efx
->net_dev
,
341 "allocated PIO buffer %u handle %x\n", i
,
342 nic_data
->piobuf_handle
[i
]);
345 nic_data
->n_piobufs
= i
;
347 efx_ef10_free_piobufs(efx
);
351 static int efx_ef10_link_piobufs(struct efx_nic
*efx
)
353 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
354 MCDI_DECLARE_BUF(inbuf
,
355 max(MC_CMD_LINK_PIOBUF_IN_LEN
,
356 MC_CMD_UNLINK_PIOBUF_IN_LEN
));
357 struct efx_channel
*channel
;
358 struct efx_tx_queue
*tx_queue
;
359 unsigned int offset
, index
;
362 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN
!= 0);
363 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN
!= 0);
365 /* Link a buffer to each VI in the write-combining mapping */
366 for (index
= 0; index
< nic_data
->n_piobufs
; ++index
) {
367 MCDI_SET_DWORD(inbuf
, LINK_PIOBUF_IN_PIOBUF_HANDLE
,
368 nic_data
->piobuf_handle
[index
]);
369 MCDI_SET_DWORD(inbuf
, LINK_PIOBUF_IN_TXQ_INSTANCE
,
370 nic_data
->pio_write_vi_base
+ index
);
371 rc
= efx_mcdi_rpc(efx
, MC_CMD_LINK_PIOBUF
,
372 inbuf
, MC_CMD_LINK_PIOBUF_IN_LEN
,
375 netif_err(efx
, drv
, efx
->net_dev
,
376 "failed to link VI %u to PIO buffer %u (%d)\n",
377 nic_data
->pio_write_vi_base
+ index
, index
,
381 netif_dbg(efx
, probe
, efx
->net_dev
,
382 "linked VI %u to PIO buffer %u\n",
383 nic_data
->pio_write_vi_base
+ index
, index
);
386 /* Link a buffer to each TX queue */
387 efx_for_each_channel(channel
, efx
) {
388 efx_for_each_channel_tx_queue(tx_queue
, channel
) {
389 /* We assign the PIO buffers to queues in
390 * reverse order to allow for the following
393 offset
= ((efx
->tx_channel_offset
+ efx
->n_tx_channels
-
394 tx_queue
->channel
->channel
- 1) *
396 index
= offset
/ ER_DZ_TX_PIOBUF_SIZE
;
397 offset
= offset
% ER_DZ_TX_PIOBUF_SIZE
;
399 /* When the host page size is 4K, the first
400 * host page in the WC mapping may be within
401 * the same VI page as the last TX queue. We
402 * can only link one buffer to each VI.
404 if (tx_queue
->queue
== nic_data
->pio_write_vi_base
) {
408 MCDI_SET_DWORD(inbuf
,
409 LINK_PIOBUF_IN_PIOBUF_HANDLE
,
410 nic_data
->piobuf_handle
[index
]);
411 MCDI_SET_DWORD(inbuf
,
412 LINK_PIOBUF_IN_TXQ_INSTANCE
,
414 rc
= efx_mcdi_rpc(efx
, MC_CMD_LINK_PIOBUF
,
415 inbuf
, MC_CMD_LINK_PIOBUF_IN_LEN
,
420 /* This is non-fatal; the TX path just
421 * won't use PIO for this queue
423 netif_err(efx
, drv
, efx
->net_dev
,
424 "failed to link VI %u to PIO buffer %u (%d)\n",
425 tx_queue
->queue
, index
, rc
);
426 tx_queue
->piobuf
= NULL
;
429 nic_data
->pio_write_base
+
430 index
* EFX_VI_PAGE_SIZE
+ offset
;
431 tx_queue
->piobuf_offset
= offset
;
432 netif_dbg(efx
, probe
, efx
->net_dev
,
433 "linked VI %u to PIO buffer %u offset %x addr %p\n",
434 tx_queue
->queue
, index
,
435 tx_queue
->piobuf_offset
,
445 MCDI_SET_DWORD(inbuf
, UNLINK_PIOBUF_IN_TXQ_INSTANCE
,
446 nic_data
->pio_write_vi_base
+ index
);
447 efx_mcdi_rpc(efx
, MC_CMD_UNLINK_PIOBUF
,
448 inbuf
, MC_CMD_UNLINK_PIOBUF_IN_LEN
,
454 #else /* !EFX_USE_PIO */
456 static int efx_ef10_alloc_piobufs(struct efx_nic
*efx
, unsigned int n
)
458 return n
== 0 ? 0 : -ENOBUFS
;
461 static int efx_ef10_link_piobufs(struct efx_nic
*efx
)
466 static void efx_ef10_free_piobufs(struct efx_nic
*efx
)
470 #endif /* EFX_USE_PIO */
472 static void efx_ef10_remove(struct efx_nic
*efx
)
474 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
479 efx_mcdi_mon_remove(efx
);
481 efx_ef10_rx_free_indir_table(efx
);
483 if (nic_data
->wc_membase
)
484 iounmap(nic_data
->wc_membase
);
486 rc
= efx_ef10_free_vis(efx
);
489 if (!nic_data
->must_restore_piobufs
)
490 efx_ef10_free_piobufs(efx
);
493 efx_nic_free_buffer(efx
, &nic_data
->mcdi_buf
);
497 static int efx_ef10_alloc_vis(struct efx_nic
*efx
,
498 unsigned int min_vis
, unsigned int max_vis
)
500 MCDI_DECLARE_BUF(inbuf
, MC_CMD_ALLOC_VIS_IN_LEN
);
501 MCDI_DECLARE_BUF(outbuf
, MC_CMD_ALLOC_VIS_OUT_LEN
);
502 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
506 MCDI_SET_DWORD(inbuf
, ALLOC_VIS_IN_MIN_VI_COUNT
, min_vis
);
507 MCDI_SET_DWORD(inbuf
, ALLOC_VIS_IN_MAX_VI_COUNT
, max_vis
);
508 rc
= efx_mcdi_rpc(efx
, MC_CMD_ALLOC_VIS
, inbuf
, sizeof(inbuf
),
509 outbuf
, sizeof(outbuf
), &outlen
);
513 if (outlen
< MC_CMD_ALLOC_VIS_OUT_LEN
)
516 netif_dbg(efx
, drv
, efx
->net_dev
, "base VI is A0x%03x\n",
517 MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_BASE
));
519 nic_data
->vi_base
= MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_BASE
);
520 nic_data
->n_allocated_vis
= MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_COUNT
);
524 /* Note that the failure path of this function does not free
525 * resources, as this will be done by efx_ef10_remove().
527 static int efx_ef10_dimension_resources(struct efx_nic
*efx
)
529 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
530 unsigned int uc_mem_map_size
, wc_mem_map_size
;
531 unsigned int min_vis
, pio_write_vi_base
, max_vis
;
532 void __iomem
*membase
;
535 min_vis
= max(efx
->n_channels
, efx
->n_tx_channels
* EFX_TXQ_TYPES
);
538 /* Try to allocate PIO buffers if wanted and if the full
539 * number of PIO buffers would be sufficient to allocate one
540 * copy-buffer per TX channel. Failure is non-fatal, as there
541 * are only a small number of PIO buffers shared between all
542 * functions of the controller.
544 if (efx_piobuf_size
!= 0 &&
545 ER_DZ_TX_PIOBUF_SIZE
/ efx_piobuf_size
* EF10_TX_PIOBUF_COUNT
>=
546 efx
->n_tx_channels
) {
547 unsigned int n_piobufs
=
548 DIV_ROUND_UP(efx
->n_tx_channels
,
549 ER_DZ_TX_PIOBUF_SIZE
/ efx_piobuf_size
);
551 rc
= efx_ef10_alloc_piobufs(efx
, n_piobufs
);
553 netif_err(efx
, probe
, efx
->net_dev
,
554 "failed to allocate PIO buffers (%d)\n", rc
);
556 netif_dbg(efx
, probe
, efx
->net_dev
,
557 "allocated %u PIO buffers\n", n_piobufs
);
560 nic_data
->n_piobufs
= 0;
563 /* PIO buffers should be mapped with write-combining enabled,
564 * and we want to make single UC and WC mappings rather than
565 * several of each (in fact that's the only option if host
566 * page size is >4K). So we may allocate some extra VIs just
567 * for writing PIO buffers through.
569 * The UC mapping contains (min_vis - 1) complete VIs and the
570 * first half of the next VI. Then the WC mapping begins with
571 * the second half of this last VI.
573 uc_mem_map_size
= PAGE_ALIGN((min_vis
- 1) * EFX_VI_PAGE_SIZE
+
575 if (nic_data
->n_piobufs
) {
576 /* pio_write_vi_base rounds down to give the number of complete
577 * VIs inside the UC mapping.
579 pio_write_vi_base
= uc_mem_map_size
/ EFX_VI_PAGE_SIZE
;
580 wc_mem_map_size
= (PAGE_ALIGN((pio_write_vi_base
+
581 nic_data
->n_piobufs
) *
584 max_vis
= pio_write_vi_base
+ nic_data
->n_piobufs
;
586 pio_write_vi_base
= 0;
591 /* In case the last attached driver failed to free VIs, do it now */
592 rc
= efx_ef10_free_vis(efx
);
596 rc
= efx_ef10_alloc_vis(efx
, min_vis
, max_vis
);
600 /* If we didn't get enough VIs to map all the PIO buffers, free the
603 if (nic_data
->n_piobufs
&&
604 nic_data
->n_allocated_vis
<
605 pio_write_vi_base
+ nic_data
->n_piobufs
) {
606 netif_dbg(efx
, probe
, efx
->net_dev
,
607 "%u VIs are not sufficient to map %u PIO buffers\n",
608 nic_data
->n_allocated_vis
, nic_data
->n_piobufs
);
609 efx_ef10_free_piobufs(efx
);
612 /* Shrink the original UC mapping of the memory BAR */
613 membase
= ioremap_nocache(efx
->membase_phys
, uc_mem_map_size
);
615 netif_err(efx
, probe
, efx
->net_dev
,
616 "could not shrink memory BAR to %x\n",
620 iounmap(efx
->membase
);
621 efx
->membase
= membase
;
623 /* Set up the WC mapping if needed */
624 if (wc_mem_map_size
) {
625 nic_data
->wc_membase
= ioremap_wc(efx
->membase_phys
+
628 if (!nic_data
->wc_membase
) {
629 netif_err(efx
, probe
, efx
->net_dev
,
630 "could not allocate WC mapping of size %x\n",
634 nic_data
->pio_write_vi_base
= pio_write_vi_base
;
635 nic_data
->pio_write_base
=
636 nic_data
->wc_membase
+
637 (pio_write_vi_base
* EFX_VI_PAGE_SIZE
+ ER_DZ_TX_PIOBUF
-
640 rc
= efx_ef10_link_piobufs(efx
);
642 efx_ef10_free_piobufs(efx
);
645 netif_dbg(efx
, probe
, efx
->net_dev
,
646 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
647 &efx
->membase_phys
, efx
->membase
, uc_mem_map_size
,
648 nic_data
->wc_membase
, wc_mem_map_size
);
653 static int efx_ef10_init_nic(struct efx_nic
*efx
)
655 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
658 if (nic_data
->must_check_datapath_caps
) {
659 rc
= efx_ef10_init_datapath_caps(efx
);
662 nic_data
->must_check_datapath_caps
= false;
665 if (nic_data
->must_realloc_vis
) {
666 /* We cannot let the number of VIs change now */
667 rc
= efx_ef10_alloc_vis(efx
, nic_data
->n_allocated_vis
,
668 nic_data
->n_allocated_vis
);
671 nic_data
->must_realloc_vis
= false;
674 if (nic_data
->must_restore_piobufs
&& nic_data
->n_piobufs
) {
675 rc
= efx_ef10_alloc_piobufs(efx
, nic_data
->n_piobufs
);
677 rc
= efx_ef10_link_piobufs(efx
);
679 efx_ef10_free_piobufs(efx
);
682 /* Log an error on failure, but this is non-fatal */
684 netif_err(efx
, drv
, efx
->net_dev
,
685 "failed to restore PIO buffers (%d)\n", rc
);
686 nic_data
->must_restore_piobufs
= false;
689 efx_ef10_rx_push_rss_config(efx
);
693 static void efx_ef10_reset_mc_allocations(struct efx_nic
*efx
)
695 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
697 /* All our allocations have been reset */
698 nic_data
->must_realloc_vis
= true;
699 nic_data
->must_restore_filters
= true;
700 nic_data
->must_restore_piobufs
= true;
701 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
704 static int efx_ef10_map_reset_flags(u32
*flags
)
707 EF10_RESET_PORT
= ((ETH_RESET_MAC
| ETH_RESET_PHY
) <<
708 ETH_RESET_SHARED_SHIFT
),
709 EF10_RESET_MC
= ((ETH_RESET_DMA
| ETH_RESET_FILTER
|
710 ETH_RESET_OFFLOAD
| ETH_RESET_MAC
|
711 ETH_RESET_PHY
| ETH_RESET_MGMT
) <<
712 ETH_RESET_SHARED_SHIFT
)
715 /* We assume for now that our PCI function is permitted to
719 if ((*flags
& EF10_RESET_MC
) == EF10_RESET_MC
) {
720 *flags
&= ~EF10_RESET_MC
;
721 return RESET_TYPE_WORLD
;
724 if ((*flags
& EF10_RESET_PORT
) == EF10_RESET_PORT
) {
725 *flags
&= ~EF10_RESET_PORT
;
726 return RESET_TYPE_ALL
;
729 /* no invisible reset implemented */
734 static int efx_ef10_reset(struct efx_nic
*efx
, enum reset_type reset_type
)
736 int rc
= efx_mcdi_reset(efx
, reset_type
);
738 /* If it was a port reset, trigger reallocation of MC resources.
739 * Note that on an MC reset nothing needs to be done now because we'll
740 * detect the MC reset later and handle it then.
741 * For an FLR, we never get an MC reset event, but the MC has reset all
742 * resources assigned to us, so we have to trigger reallocation now.
744 if ((reset_type
== RESET_TYPE_ALL
||
745 reset_type
== RESET_TYPE_MCDI_TIMEOUT
) && !rc
)
746 efx_ef10_reset_mc_allocations(efx
);
750 #define EF10_DMA_STAT(ext_name, mcdi_name) \
751 [EF10_STAT_ ## ext_name] = \
752 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
753 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
754 [EF10_STAT_ ## int_name] = \
755 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
756 #define EF10_OTHER_STAT(ext_name) \
757 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
758 #define GENERIC_SW_STAT(ext_name) \
759 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
761 static const struct efx_hw_stat_desc efx_ef10_stat_desc
[EF10_STAT_COUNT
] = {
762 EF10_DMA_STAT(tx_bytes
, TX_BYTES
),
763 EF10_DMA_STAT(tx_packets
, TX_PKTS
),
764 EF10_DMA_STAT(tx_pause
, TX_PAUSE_PKTS
),
765 EF10_DMA_STAT(tx_control
, TX_CONTROL_PKTS
),
766 EF10_DMA_STAT(tx_unicast
, TX_UNICAST_PKTS
),
767 EF10_DMA_STAT(tx_multicast
, TX_MULTICAST_PKTS
),
768 EF10_DMA_STAT(tx_broadcast
, TX_BROADCAST_PKTS
),
769 EF10_DMA_STAT(tx_lt64
, TX_LT64_PKTS
),
770 EF10_DMA_STAT(tx_64
, TX_64_PKTS
),
771 EF10_DMA_STAT(tx_65_to_127
, TX_65_TO_127_PKTS
),
772 EF10_DMA_STAT(tx_128_to_255
, TX_128_TO_255_PKTS
),
773 EF10_DMA_STAT(tx_256_to_511
, TX_256_TO_511_PKTS
),
774 EF10_DMA_STAT(tx_512_to_1023
, TX_512_TO_1023_PKTS
),
775 EF10_DMA_STAT(tx_1024_to_15xx
, TX_1024_TO_15XX_PKTS
),
776 EF10_DMA_STAT(tx_15xx_to_jumbo
, TX_15XX_TO_JUMBO_PKTS
),
777 EF10_DMA_STAT(rx_bytes
, RX_BYTES
),
778 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes
, RX_BAD_BYTES
),
779 EF10_OTHER_STAT(rx_good_bytes
),
780 EF10_OTHER_STAT(rx_bad_bytes
),
781 EF10_DMA_STAT(rx_packets
, RX_PKTS
),
782 EF10_DMA_STAT(rx_good
, RX_GOOD_PKTS
),
783 EF10_DMA_STAT(rx_bad
, RX_BAD_FCS_PKTS
),
784 EF10_DMA_STAT(rx_pause
, RX_PAUSE_PKTS
),
785 EF10_DMA_STAT(rx_control
, RX_CONTROL_PKTS
),
786 EF10_DMA_STAT(rx_unicast
, RX_UNICAST_PKTS
),
787 EF10_DMA_STAT(rx_multicast
, RX_MULTICAST_PKTS
),
788 EF10_DMA_STAT(rx_broadcast
, RX_BROADCAST_PKTS
),
789 EF10_DMA_STAT(rx_lt64
, RX_UNDERSIZE_PKTS
),
790 EF10_DMA_STAT(rx_64
, RX_64_PKTS
),
791 EF10_DMA_STAT(rx_65_to_127
, RX_65_TO_127_PKTS
),
792 EF10_DMA_STAT(rx_128_to_255
, RX_128_TO_255_PKTS
),
793 EF10_DMA_STAT(rx_256_to_511
, RX_256_TO_511_PKTS
),
794 EF10_DMA_STAT(rx_512_to_1023
, RX_512_TO_1023_PKTS
),
795 EF10_DMA_STAT(rx_1024_to_15xx
, RX_1024_TO_15XX_PKTS
),
796 EF10_DMA_STAT(rx_15xx_to_jumbo
, RX_15XX_TO_JUMBO_PKTS
),
797 EF10_DMA_STAT(rx_gtjumbo
, RX_GTJUMBO_PKTS
),
798 EF10_DMA_STAT(rx_bad_gtjumbo
, RX_JABBER_PKTS
),
799 EF10_DMA_STAT(rx_overflow
, RX_OVERFLOW_PKTS
),
800 EF10_DMA_STAT(rx_align_error
, RX_ALIGN_ERROR_PKTS
),
801 EF10_DMA_STAT(rx_length_error
, RX_LENGTH_ERROR_PKTS
),
802 EF10_DMA_STAT(rx_nodesc_drops
, RX_NODESC_DROPS
),
803 GENERIC_SW_STAT(rx_nodesc_trunc
),
804 GENERIC_SW_STAT(rx_noskb_drops
),
805 EF10_DMA_STAT(rx_pm_trunc_bb_overflow
, PM_TRUNC_BB_OVERFLOW
),
806 EF10_DMA_STAT(rx_pm_discard_bb_overflow
, PM_DISCARD_BB_OVERFLOW
),
807 EF10_DMA_STAT(rx_pm_trunc_vfifo_full
, PM_TRUNC_VFIFO_FULL
),
808 EF10_DMA_STAT(rx_pm_discard_vfifo_full
, PM_DISCARD_VFIFO_FULL
),
809 EF10_DMA_STAT(rx_pm_trunc_qbb
, PM_TRUNC_QBB
),
810 EF10_DMA_STAT(rx_pm_discard_qbb
, PM_DISCARD_QBB
),
811 EF10_DMA_STAT(rx_pm_discard_mapping
, PM_DISCARD_MAPPING
),
812 EF10_DMA_STAT(rx_dp_q_disabled_packets
, RXDP_Q_DISABLED_PKTS
),
813 EF10_DMA_STAT(rx_dp_di_dropped_packets
, RXDP_DI_DROPPED_PKTS
),
814 EF10_DMA_STAT(rx_dp_streaming_packets
, RXDP_STREAMING_PKTS
),
815 EF10_DMA_STAT(rx_dp_hlb_fetch
, RXDP_EMERGENCY_FETCH_CONDITIONS
),
816 EF10_DMA_STAT(rx_dp_hlb_wait
, RXDP_EMERGENCY_WAIT_CONDITIONS
),
819 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \
820 (1ULL << EF10_STAT_tx_packets) | \
821 (1ULL << EF10_STAT_tx_pause) | \
822 (1ULL << EF10_STAT_tx_unicast) | \
823 (1ULL << EF10_STAT_tx_multicast) | \
824 (1ULL << EF10_STAT_tx_broadcast) | \
825 (1ULL << EF10_STAT_rx_bytes) | \
826 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
827 (1ULL << EF10_STAT_rx_good_bytes) | \
828 (1ULL << EF10_STAT_rx_bad_bytes) | \
829 (1ULL << EF10_STAT_rx_packets) | \
830 (1ULL << EF10_STAT_rx_good) | \
831 (1ULL << EF10_STAT_rx_bad) | \
832 (1ULL << EF10_STAT_rx_pause) | \
833 (1ULL << EF10_STAT_rx_control) | \
834 (1ULL << EF10_STAT_rx_unicast) | \
835 (1ULL << EF10_STAT_rx_multicast) | \
836 (1ULL << EF10_STAT_rx_broadcast) | \
837 (1ULL << EF10_STAT_rx_lt64) | \
838 (1ULL << EF10_STAT_rx_64) | \
839 (1ULL << EF10_STAT_rx_65_to_127) | \
840 (1ULL << EF10_STAT_rx_128_to_255) | \
841 (1ULL << EF10_STAT_rx_256_to_511) | \
842 (1ULL << EF10_STAT_rx_512_to_1023) | \
843 (1ULL << EF10_STAT_rx_1024_to_15xx) | \
844 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \
845 (1ULL << EF10_STAT_rx_gtjumbo) | \
846 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \
847 (1ULL << EF10_STAT_rx_overflow) | \
848 (1ULL << EF10_STAT_rx_nodesc_drops) | \
849 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
850 (1ULL << GENERIC_STAT_rx_noskb_drops))
852 /* These statistics are only provided by the 10G MAC. For a 10G/40G
853 * switchable port we do not expose these because they might not
854 * include all the packets they should.
856 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \
857 (1ULL << EF10_STAT_tx_lt64) | \
858 (1ULL << EF10_STAT_tx_64) | \
859 (1ULL << EF10_STAT_tx_65_to_127) | \
860 (1ULL << EF10_STAT_tx_128_to_255) | \
861 (1ULL << EF10_STAT_tx_256_to_511) | \
862 (1ULL << EF10_STAT_tx_512_to_1023) | \
863 (1ULL << EF10_STAT_tx_1024_to_15xx) | \
864 (1ULL << EF10_STAT_tx_15xx_to_jumbo))
866 /* These statistics are only provided by the 40G MAC. For a 10G/40G
867 * switchable port we do expose these because the errors will otherwise
870 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \
871 (1ULL << EF10_STAT_rx_length_error))
873 /* These statistics are only provided if the firmware supports the
874 * capability PM_AND_RXDP_COUNTERS.
876 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
877 (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \
878 (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \
879 (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \
880 (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \
881 (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \
882 (1ULL << EF10_STAT_rx_pm_discard_qbb) | \
883 (1ULL << EF10_STAT_rx_pm_discard_mapping) | \
884 (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \
885 (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \
886 (1ULL << EF10_STAT_rx_dp_streaming_packets) | \
887 (1ULL << EF10_STAT_rx_dp_hlb_fetch) | \
888 (1ULL << EF10_STAT_rx_dp_hlb_wait))
890 static u64
efx_ef10_raw_stat_mask(struct efx_nic
*efx
)
892 u64 raw_mask
= HUNT_COMMON_STAT_MASK
;
893 u32 port_caps
= efx_mcdi_phy_get_caps(efx
);
894 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
896 if (port_caps
& (1 << MC_CMD_PHY_CAP_40000FDX_LBN
))
897 raw_mask
|= HUNT_40G_EXTRA_STAT_MASK
;
899 raw_mask
|= HUNT_10G_ONLY_STAT_MASK
;
901 if (nic_data
->datapath_caps
&
902 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN
))
903 raw_mask
|= HUNT_PM_AND_RXDP_STAT_MASK
;
908 static void efx_ef10_get_stat_mask(struct efx_nic
*efx
, unsigned long *mask
)
910 u64 raw_mask
= efx_ef10_raw_stat_mask(efx
);
912 #if BITS_PER_LONG == 64
915 mask
[0] = raw_mask
& 0xffffffff;
916 mask
[1] = raw_mask
>> 32;
920 static size_t efx_ef10_describe_stats(struct efx_nic
*efx
, u8
*names
)
922 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
924 efx_ef10_get_stat_mask(efx
, mask
);
925 return efx_nic_describe_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
,
929 static int efx_ef10_try_update_nic_stats(struct efx_nic
*efx
)
931 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
932 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
933 __le64 generation_start
, generation_end
;
934 u64
*stats
= nic_data
->stats
;
937 efx_ef10_get_stat_mask(efx
, mask
);
939 dma_stats
= efx
->stats_buffer
.addr
;
940 nic_data
= efx
->nic_data
;
942 generation_end
= dma_stats
[MC_CMD_MAC_GENERATION_END
];
943 if (generation_end
== EFX_MC_STATS_GENERATION_INVALID
)
946 efx_nic_update_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
, mask
,
947 stats
, efx
->stats_buffer
.addr
, false);
949 generation_start
= dma_stats
[MC_CMD_MAC_GENERATION_START
];
950 if (generation_end
!= generation_start
)
953 /* Update derived statistics */
954 efx_nic_fix_nodesc_drop_stat(efx
, &stats
[EF10_STAT_rx_nodesc_drops
]);
955 stats
[EF10_STAT_rx_good_bytes
] =
956 stats
[EF10_STAT_rx_bytes
] -
957 stats
[EF10_STAT_rx_bytes_minus_good_bytes
];
958 efx_update_diff_stat(&stats
[EF10_STAT_rx_bad_bytes
],
959 stats
[EF10_STAT_rx_bytes_minus_good_bytes
]);
960 efx_update_sw_stats(efx
, stats
);
965 static size_t efx_ef10_update_stats(struct efx_nic
*efx
, u64
*full_stats
,
966 struct rtnl_link_stats64
*core_stats
)
968 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
969 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
970 u64
*stats
= nic_data
->stats
;
971 size_t stats_count
= 0, index
;
974 efx_ef10_get_stat_mask(efx
, mask
);
976 /* If we're unlucky enough to read statistics during the DMA, wait
977 * up to 10ms for it to finish (typically takes <500us)
979 for (retry
= 0; retry
< 100; ++retry
) {
980 if (efx_ef10_try_update_nic_stats(efx
) == 0)
986 for_each_set_bit(index
, mask
, EF10_STAT_COUNT
) {
987 if (efx_ef10_stat_desc
[index
].name
) {
988 *full_stats
++ = stats
[index
];
995 core_stats
->rx_packets
= stats
[EF10_STAT_rx_packets
];
996 core_stats
->tx_packets
= stats
[EF10_STAT_tx_packets
];
997 core_stats
->rx_bytes
= stats
[EF10_STAT_rx_bytes
];
998 core_stats
->tx_bytes
= stats
[EF10_STAT_tx_bytes
];
999 core_stats
->rx_dropped
= stats
[EF10_STAT_rx_nodesc_drops
] +
1000 stats
[GENERIC_STAT_rx_nodesc_trunc
] +
1001 stats
[GENERIC_STAT_rx_noskb_drops
];
1002 core_stats
->multicast
= stats
[EF10_STAT_rx_multicast
];
1003 core_stats
->rx_length_errors
=
1004 stats
[EF10_STAT_rx_gtjumbo
] +
1005 stats
[EF10_STAT_rx_length_error
];
1006 core_stats
->rx_crc_errors
= stats
[EF10_STAT_rx_bad
];
1007 core_stats
->rx_frame_errors
= stats
[EF10_STAT_rx_align_error
];
1008 core_stats
->rx_fifo_errors
= stats
[EF10_STAT_rx_overflow
];
1009 core_stats
->rx_errors
= (core_stats
->rx_length_errors
+
1010 core_stats
->rx_crc_errors
+
1011 core_stats
->rx_frame_errors
);
1017 static void efx_ef10_push_irq_moderation(struct efx_channel
*channel
)
1019 struct efx_nic
*efx
= channel
->efx
;
1020 unsigned int mode
, value
;
1021 efx_dword_t timer_cmd
;
1023 if (channel
->irq_moderation
) {
1025 value
= channel
->irq_moderation
- 1;
1031 if (EFX_EF10_WORKAROUND_35388(efx
)) {
1032 EFX_POPULATE_DWORD_3(timer_cmd
, ERF_DD_EVQ_IND_TIMER_FLAGS
,
1033 EFE_DD_EVQ_IND_TIMER_FLAGS
,
1034 ERF_DD_EVQ_IND_TIMER_MODE
, mode
,
1035 ERF_DD_EVQ_IND_TIMER_VAL
, value
);
1036 efx_writed_page(efx
, &timer_cmd
, ER_DD_EVQ_INDIRECT
,
1039 EFX_POPULATE_DWORD_2(timer_cmd
, ERF_DZ_TC_TIMER_MODE
, mode
,
1040 ERF_DZ_TC_TIMER_VAL
, value
);
1041 efx_writed_page(efx
, &timer_cmd
, ER_DZ_EVQ_TMR
,
1046 static void efx_ef10_get_wol(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
)
1050 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
1053 static int efx_ef10_set_wol(struct efx_nic
*efx
, u32 type
)
1060 static void efx_ef10_mcdi_request(struct efx_nic
*efx
,
1061 const efx_dword_t
*hdr
, size_t hdr_len
,
1062 const efx_dword_t
*sdu
, size_t sdu_len
)
1064 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1065 u8
*pdu
= nic_data
->mcdi_buf
.addr
;
1067 memcpy(pdu
, hdr
, hdr_len
);
1068 memcpy(pdu
+ hdr_len
, sdu
, sdu_len
);
1071 /* The hardware provides 'low' and 'high' (doorbell) registers
1072 * for passing the 64-bit address of an MCDI request to
1073 * firmware. However the dwords are swapped by firmware. The
1074 * least significant bits of the doorbell are then 0 for all
1075 * MCDI requests due to alignment.
1077 _efx_writed(efx
, cpu_to_le32((u64
)nic_data
->mcdi_buf
.dma_addr
>> 32),
1079 _efx_writed(efx
, cpu_to_le32((u32
)nic_data
->mcdi_buf
.dma_addr
),
1083 static bool efx_ef10_mcdi_poll_response(struct efx_nic
*efx
)
1085 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1086 const efx_dword_t hdr
= *(const efx_dword_t
*)nic_data
->mcdi_buf
.addr
;
1089 return EFX_DWORD_FIELD(hdr
, MCDI_HEADER_RESPONSE
);
1093 efx_ef10_mcdi_read_response(struct efx_nic
*efx
, efx_dword_t
*outbuf
,
1094 size_t offset
, size_t outlen
)
1096 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1097 const u8
*pdu
= nic_data
->mcdi_buf
.addr
;
1099 memcpy(outbuf
, pdu
+ offset
, outlen
);
1102 static int efx_ef10_mcdi_poll_reboot(struct efx_nic
*efx
)
1104 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1107 rc
= efx_ef10_get_warm_boot_count(efx
);
1109 /* The firmware is presumably in the process of
1110 * rebooting. However, we are supposed to report each
1111 * reboot just once, so we must only do that once we
1112 * can read and store the updated warm boot count.
1117 if (rc
== nic_data
->warm_boot_count
)
1120 nic_data
->warm_boot_count
= rc
;
1122 /* All our allocations have been reset */
1123 efx_ef10_reset_mc_allocations(efx
);
1125 /* The datapath firmware might have been changed */
1126 nic_data
->must_check_datapath_caps
= true;
1128 /* MAC statistics have been cleared on the NIC; clear the local
1129 * statistic that we update with efx_update_diff_stat().
1131 nic_data
->stats
[EF10_STAT_rx_bad_bytes
] = 0;
1136 /* Handle an MSI interrupt
1138 * Handle an MSI hardware interrupt. This routine schedules event
1139 * queue processing. No interrupt acknowledgement cycle is necessary.
1140 * Also, we never need to check that the interrupt is for us, since
1141 * MSI interrupts cannot be shared.
1143 static irqreturn_t
efx_ef10_msi_interrupt(int irq
, void *dev_id
)
1145 struct efx_msi_context
*context
= dev_id
;
1146 struct efx_nic
*efx
= context
->efx
;
1148 netif_vdbg(efx
, intr
, efx
->net_dev
,
1149 "IRQ %d on CPU %d\n", irq
, raw_smp_processor_id());
1151 if (likely(ACCESS_ONCE(efx
->irq_soft_enabled
))) {
1152 /* Note test interrupts */
1153 if (context
->index
== efx
->irq_level
)
1154 efx
->last_irq_cpu
= raw_smp_processor_id();
1156 /* Schedule processing of the channel */
1157 efx_schedule_channel_irq(efx
->channel
[context
->index
]);
1163 static irqreturn_t
efx_ef10_legacy_interrupt(int irq
, void *dev_id
)
1165 struct efx_nic
*efx
= dev_id
;
1166 bool soft_enabled
= ACCESS_ONCE(efx
->irq_soft_enabled
);
1167 struct efx_channel
*channel
;
1171 /* Read the ISR which also ACKs the interrupts */
1172 efx_readd(efx
, ®
, ER_DZ_BIU_INT_ISR
);
1173 queues
= EFX_DWORD_FIELD(reg
, ERF_DZ_ISR_REG
);
1178 if (likely(soft_enabled
)) {
1179 /* Note test interrupts */
1180 if (queues
& (1U << efx
->irq_level
))
1181 efx
->last_irq_cpu
= raw_smp_processor_id();
1183 efx_for_each_channel(channel
, efx
) {
1185 efx_schedule_channel_irq(channel
);
1190 netif_vdbg(efx
, intr
, efx
->net_dev
,
1191 "IRQ %d on CPU %d status " EFX_DWORD_FMT
"\n",
1192 irq
, raw_smp_processor_id(), EFX_DWORD_VAL(reg
));
1197 static void efx_ef10_irq_test_generate(struct efx_nic
*efx
)
1199 MCDI_DECLARE_BUF(inbuf
, MC_CMD_TRIGGER_INTERRUPT_IN_LEN
);
1201 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN
!= 0);
1203 MCDI_SET_DWORD(inbuf
, TRIGGER_INTERRUPT_IN_INTR_LEVEL
, efx
->irq_level
);
1204 (void) efx_mcdi_rpc(efx
, MC_CMD_TRIGGER_INTERRUPT
,
1205 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
1208 static int efx_ef10_tx_probe(struct efx_tx_queue
*tx_queue
)
1210 return efx_nic_alloc_buffer(tx_queue
->efx
, &tx_queue
->txd
.buf
,
1211 (tx_queue
->ptr_mask
+ 1) *
1212 sizeof(efx_qword_t
),
1216 /* This writes to the TX_DESC_WPTR and also pushes data */
1217 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue
*tx_queue
,
1218 const efx_qword_t
*txd
)
1220 unsigned int write_ptr
;
1223 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
1224 EFX_POPULATE_OWORD_1(reg
, ERF_DZ_TX_DESC_WPTR
, write_ptr
);
1225 reg
.qword
[0] = *txd
;
1226 efx_writeo_page(tx_queue
->efx
, ®
,
1227 ER_DZ_TX_DESC_UPD
, tx_queue
->queue
);
1230 static void efx_ef10_tx_init(struct efx_tx_queue
*tx_queue
)
1232 MCDI_DECLARE_BUF(inbuf
, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE
* 8 /
1234 MCDI_DECLARE_BUF(outbuf
, MC_CMD_INIT_TXQ_OUT_LEN
);
1235 bool csum_offload
= tx_queue
->queue
& EFX_TXQ_TYPE_OFFLOAD
;
1236 size_t entries
= tx_queue
->txd
.buf
.len
/ EFX_BUF_SIZE
;
1237 struct efx_channel
*channel
= tx_queue
->channel
;
1238 struct efx_nic
*efx
= tx_queue
->efx
;
1239 size_t inlen
, outlen
;
1240 dma_addr_t dma_addr
;
1245 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_SIZE
, tx_queue
->ptr_mask
+ 1);
1246 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_TARGET_EVQ
, channel
->channel
);
1247 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_LABEL
, tx_queue
->queue
);
1248 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_INSTANCE
, tx_queue
->queue
);
1249 MCDI_POPULATE_DWORD_2(inbuf
, INIT_TXQ_IN_FLAGS
,
1250 INIT_TXQ_IN_FLAG_IP_CSUM_DIS
, !csum_offload
,
1251 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS
, !csum_offload
);
1252 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_OWNER_ID
, 0);
1253 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_PORT_ID
, EVB_PORT_ID_ASSIGNED
);
1255 dma_addr
= tx_queue
->txd
.buf
.dma_addr
;
1257 netif_dbg(efx
, hw
, efx
->net_dev
, "pushing TXQ %d. %zu entries (%llx)\n",
1258 tx_queue
->queue
, entries
, (u64
)dma_addr
);
1260 for (i
= 0; i
< entries
; ++i
) {
1261 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_TXQ_IN_DMA_ADDR
, i
, dma_addr
);
1262 dma_addr
+= EFX_BUF_SIZE
;
1265 inlen
= MC_CMD_INIT_TXQ_IN_LEN(entries
);
1267 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_TXQ
, inbuf
, inlen
,
1268 outbuf
, sizeof(outbuf
), &outlen
);
1272 /* A previous user of this TX queue might have set us up the
1273 * bomb by writing a descriptor to the TX push collector but
1274 * not the doorbell. (Each collector belongs to a port, not a
1275 * queue or function, so cannot easily be reset.) We must
1276 * attempt to push a no-op descriptor in its place.
1278 tx_queue
->buffer
[0].flags
= EFX_TX_BUF_OPTION
;
1279 tx_queue
->insert_count
= 1;
1280 txd
= efx_tx_desc(tx_queue
, 0);
1281 EFX_POPULATE_QWORD_4(*txd
,
1282 ESF_DZ_TX_DESC_IS_OPT
, true,
1283 ESF_DZ_TX_OPTION_TYPE
,
1284 ESE_DZ_TX_OPTION_DESC_CRC_CSUM
,
1285 ESF_DZ_TX_OPTION_UDP_TCP_CSUM
, csum_offload
,
1286 ESF_DZ_TX_OPTION_IP_CSUM
, csum_offload
);
1287 tx_queue
->write_count
= 1;
1289 efx_ef10_push_tx_desc(tx_queue
, txd
);
1294 netdev_WARN(efx
->net_dev
, "failed to initialise TXQ %d\n",
1298 static void efx_ef10_tx_fini(struct efx_tx_queue
*tx_queue
)
1300 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_TXQ_IN_LEN
);
1301 MCDI_DECLARE_BUF(outbuf
, MC_CMD_FINI_TXQ_OUT_LEN
);
1302 struct efx_nic
*efx
= tx_queue
->efx
;
1306 MCDI_SET_DWORD(inbuf
, FINI_TXQ_IN_INSTANCE
,
1309 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_TXQ
, inbuf
, sizeof(inbuf
),
1310 outbuf
, sizeof(outbuf
), &outlen
);
1312 if (rc
&& rc
!= -EALREADY
)
1318 efx_mcdi_display_error(efx
, MC_CMD_FINI_TXQ
, MC_CMD_FINI_TXQ_IN_LEN
,
1319 outbuf
, outlen
, rc
);
1322 static void efx_ef10_tx_remove(struct efx_tx_queue
*tx_queue
)
1324 efx_nic_free_buffer(tx_queue
->efx
, &tx_queue
->txd
.buf
);
1327 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1328 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue
*tx_queue
)
1330 unsigned int write_ptr
;
1333 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
1334 EFX_POPULATE_DWORD_1(reg
, ERF_DZ_TX_DESC_WPTR_DWORD
, write_ptr
);
1335 efx_writed_page(tx_queue
->efx
, ®
,
1336 ER_DZ_TX_DESC_UPD_DWORD
, tx_queue
->queue
);
1339 static void efx_ef10_tx_write(struct efx_tx_queue
*tx_queue
)
1341 unsigned int old_write_count
= tx_queue
->write_count
;
1342 struct efx_tx_buffer
*buffer
;
1343 unsigned int write_ptr
;
1346 BUG_ON(tx_queue
->write_count
== tx_queue
->insert_count
);
1349 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
1350 buffer
= &tx_queue
->buffer
[write_ptr
];
1351 txd
= efx_tx_desc(tx_queue
, write_ptr
);
1352 ++tx_queue
->write_count
;
1354 /* Create TX descriptor ring entry */
1355 if (buffer
->flags
& EFX_TX_BUF_OPTION
) {
1356 *txd
= buffer
->option
;
1358 BUILD_BUG_ON(EFX_TX_BUF_CONT
!= 1);
1359 EFX_POPULATE_QWORD_3(
1362 buffer
->flags
& EFX_TX_BUF_CONT
,
1363 ESF_DZ_TX_KER_BYTE_CNT
, buffer
->len
,
1364 ESF_DZ_TX_KER_BUF_ADDR
, buffer
->dma_addr
);
1366 } while (tx_queue
->write_count
!= tx_queue
->insert_count
);
1368 wmb(); /* Ensure descriptors are written before they are fetched */
1370 if (efx_nic_may_push_tx_desc(tx_queue
, old_write_count
)) {
1371 txd
= efx_tx_desc(tx_queue
,
1372 old_write_count
& tx_queue
->ptr_mask
);
1373 efx_ef10_push_tx_desc(tx_queue
, txd
);
1376 efx_ef10_notify_tx_desc(tx_queue
);
1380 static int efx_ef10_alloc_rss_context(struct efx_nic
*efx
, u32
*context
)
1382 MCDI_DECLARE_BUF(inbuf
, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN
);
1383 MCDI_DECLARE_BUF(outbuf
, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN
);
1387 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID
,
1388 EVB_PORT_ID_ASSIGNED
);
1389 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_TYPE
,
1390 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE
);
1391 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES
,
1394 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_ALLOC
, inbuf
, sizeof(inbuf
),
1395 outbuf
, sizeof(outbuf
), &outlen
);
1399 if (outlen
< MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN
)
1402 *context
= MCDI_DWORD(outbuf
, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID
);
1407 static void efx_ef10_free_rss_context(struct efx_nic
*efx
, u32 context
)
1409 MCDI_DECLARE_BUF(inbuf
, MC_CMD_RSS_CONTEXT_FREE_IN_LEN
);
1412 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID
,
1415 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_FREE
, inbuf
, sizeof(inbuf
),
1420 static int efx_ef10_populate_rss_table(struct efx_nic
*efx
, u32 context
)
1422 MCDI_DECLARE_BUF(tablebuf
, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN
);
1423 MCDI_DECLARE_BUF(keybuf
, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN
);
1426 MCDI_SET_DWORD(tablebuf
, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID
,
1428 BUILD_BUG_ON(ARRAY_SIZE(efx
->rx_indir_table
) !=
1429 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN
);
1431 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_indir_table
); ++i
)
1433 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE
)[i
] =
1434 (u8
) efx
->rx_indir_table
[i
];
1436 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_SET_TABLE
, tablebuf
,
1437 sizeof(tablebuf
), NULL
, 0, NULL
);
1441 MCDI_SET_DWORD(keybuf
, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID
,
1443 BUILD_BUG_ON(ARRAY_SIZE(efx
->rx_hash_key
) !=
1444 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN
);
1445 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_hash_key
); ++i
)
1446 MCDI_PTR(keybuf
, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY
)[i
] =
1447 efx
->rx_hash_key
[i
];
1449 return efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_SET_KEY
, keybuf
,
1450 sizeof(keybuf
), NULL
, 0, NULL
);
1453 static void efx_ef10_rx_free_indir_table(struct efx_nic
*efx
)
1455 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1457 if (nic_data
->rx_rss_context
!= EFX_EF10_RSS_CONTEXT_INVALID
)
1458 efx_ef10_free_rss_context(efx
, nic_data
->rx_rss_context
);
1459 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
1462 static void efx_ef10_rx_push_rss_config(struct efx_nic
*efx
)
1464 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1467 netif_dbg(efx
, drv
, efx
->net_dev
, "pushing RSS config\n");
1469 if (nic_data
->rx_rss_context
== EFX_EF10_RSS_CONTEXT_INVALID
) {
1470 rc
= efx_ef10_alloc_rss_context(efx
, &nic_data
->rx_rss_context
);
1475 rc
= efx_ef10_populate_rss_table(efx
, nic_data
->rx_rss_context
);
1482 netif_err(efx
, hw
, efx
->net_dev
, "%s: failed rc=%d\n", __func__
, rc
);
1485 static int efx_ef10_rx_probe(struct efx_rx_queue
*rx_queue
)
1487 return efx_nic_alloc_buffer(rx_queue
->efx
, &rx_queue
->rxd
.buf
,
1488 (rx_queue
->ptr_mask
+ 1) *
1489 sizeof(efx_qword_t
),
1493 static void efx_ef10_rx_init(struct efx_rx_queue
*rx_queue
)
1495 MCDI_DECLARE_BUF(inbuf
,
1496 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE
* 8 /
1498 MCDI_DECLARE_BUF(outbuf
, MC_CMD_INIT_RXQ_OUT_LEN
);
1499 struct efx_channel
*channel
= efx_rx_queue_channel(rx_queue
);
1500 size_t entries
= rx_queue
->rxd
.buf
.len
/ EFX_BUF_SIZE
;
1501 struct efx_nic
*efx
= rx_queue
->efx
;
1502 size_t inlen
, outlen
;
1503 dma_addr_t dma_addr
;
1507 rx_queue
->scatter_n
= 0;
1508 rx_queue
->scatter_len
= 0;
1510 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_SIZE
, rx_queue
->ptr_mask
+ 1);
1511 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_TARGET_EVQ
, channel
->channel
);
1512 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_LABEL
, efx_rx_queue_index(rx_queue
));
1513 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_INSTANCE
,
1514 efx_rx_queue_index(rx_queue
));
1515 MCDI_POPULATE_DWORD_2(inbuf
, INIT_RXQ_IN_FLAGS
,
1516 INIT_RXQ_IN_FLAG_PREFIX
, 1,
1517 INIT_RXQ_IN_FLAG_TIMESTAMP
, 1);
1518 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_OWNER_ID
, 0);
1519 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_PORT_ID
, EVB_PORT_ID_ASSIGNED
);
1521 dma_addr
= rx_queue
->rxd
.buf
.dma_addr
;
1523 netif_dbg(efx
, hw
, efx
->net_dev
, "pushing RXQ %d. %zu entries (%llx)\n",
1524 efx_rx_queue_index(rx_queue
), entries
, (u64
)dma_addr
);
1526 for (i
= 0; i
< entries
; ++i
) {
1527 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_RXQ_IN_DMA_ADDR
, i
, dma_addr
);
1528 dma_addr
+= EFX_BUF_SIZE
;
1531 inlen
= MC_CMD_INIT_RXQ_IN_LEN(entries
);
1533 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_RXQ
, inbuf
, inlen
,
1534 outbuf
, sizeof(outbuf
), &outlen
);
1536 netdev_WARN(efx
->net_dev
, "failed to initialise RXQ %d\n",
1537 efx_rx_queue_index(rx_queue
));
1540 static void efx_ef10_rx_fini(struct efx_rx_queue
*rx_queue
)
1542 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_RXQ_IN_LEN
);
1543 MCDI_DECLARE_BUF(outbuf
, MC_CMD_FINI_RXQ_OUT_LEN
);
1544 struct efx_nic
*efx
= rx_queue
->efx
;
1548 MCDI_SET_DWORD(inbuf
, FINI_RXQ_IN_INSTANCE
,
1549 efx_rx_queue_index(rx_queue
));
1551 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_RXQ
, inbuf
, sizeof(inbuf
),
1552 outbuf
, sizeof(outbuf
), &outlen
);
1554 if (rc
&& rc
!= -EALREADY
)
1560 efx_mcdi_display_error(efx
, MC_CMD_FINI_RXQ
, MC_CMD_FINI_RXQ_IN_LEN
,
1561 outbuf
, outlen
, rc
);
1564 static void efx_ef10_rx_remove(struct efx_rx_queue
*rx_queue
)
1566 efx_nic_free_buffer(rx_queue
->efx
, &rx_queue
->rxd
.buf
);
1569 /* This creates an entry in the RX descriptor queue */
1571 efx_ef10_build_rx_desc(struct efx_rx_queue
*rx_queue
, unsigned int index
)
1573 struct efx_rx_buffer
*rx_buf
;
1576 rxd
= efx_rx_desc(rx_queue
, index
);
1577 rx_buf
= efx_rx_buffer(rx_queue
, index
);
1578 EFX_POPULATE_QWORD_2(*rxd
,
1579 ESF_DZ_RX_KER_BYTE_CNT
, rx_buf
->len
,
1580 ESF_DZ_RX_KER_BUF_ADDR
, rx_buf
->dma_addr
);
1583 static void efx_ef10_rx_write(struct efx_rx_queue
*rx_queue
)
1585 struct efx_nic
*efx
= rx_queue
->efx
;
1586 unsigned int write_count
;
1589 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1590 write_count
= rx_queue
->added_count
& ~7;
1591 if (rx_queue
->notified_count
== write_count
)
1595 efx_ef10_build_rx_desc(
1597 rx_queue
->notified_count
& rx_queue
->ptr_mask
);
1598 while (++rx_queue
->notified_count
!= write_count
);
1601 EFX_POPULATE_DWORD_1(reg
, ERF_DZ_RX_DESC_WPTR
,
1602 write_count
& rx_queue
->ptr_mask
);
1603 efx_writed_page(efx
, ®
, ER_DZ_RX_DESC_UPD
,
1604 efx_rx_queue_index(rx_queue
));
1607 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete
;
1609 static void efx_ef10_rx_defer_refill(struct efx_rx_queue
*rx_queue
)
1611 struct efx_channel
*channel
= efx_rx_queue_channel(rx_queue
);
1612 MCDI_DECLARE_BUF(inbuf
, MC_CMD_DRIVER_EVENT_IN_LEN
);
1615 EFX_POPULATE_QWORD_2(event
,
1616 ESF_DZ_EV_CODE
, EFX_EF10_DRVGEN_EV
,
1617 ESF_DZ_EV_DATA
, EFX_EF10_REFILL
);
1619 MCDI_SET_DWORD(inbuf
, DRIVER_EVENT_IN_EVQ
, channel
->channel
);
1621 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1622 * already swapped the data to little-endian order.
1624 memcpy(MCDI_PTR(inbuf
, DRIVER_EVENT_IN_DATA
), &event
.u64
[0],
1625 sizeof(efx_qword_t
));
1627 efx_mcdi_rpc_async(channel
->efx
, MC_CMD_DRIVER_EVENT
,
1628 inbuf
, sizeof(inbuf
), 0,
1629 efx_ef10_rx_defer_refill_complete
, 0);
1633 efx_ef10_rx_defer_refill_complete(struct efx_nic
*efx
, unsigned long cookie
,
1634 int rc
, efx_dword_t
*outbuf
,
1635 size_t outlen_actual
)
1640 static int efx_ef10_ev_probe(struct efx_channel
*channel
)
1642 return efx_nic_alloc_buffer(channel
->efx
, &channel
->eventq
.buf
,
1643 (channel
->eventq_mask
+ 1) *
1644 sizeof(efx_qword_t
),
1648 static int efx_ef10_ev_init(struct efx_channel
*channel
)
1650 MCDI_DECLARE_BUF(inbuf
,
1651 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE
* 8 /
1653 MCDI_DECLARE_BUF(outbuf
, MC_CMD_INIT_EVQ_OUT_LEN
);
1654 size_t entries
= channel
->eventq
.buf
.len
/ EFX_BUF_SIZE
;
1655 struct efx_nic
*efx
= channel
->efx
;
1656 struct efx_ef10_nic_data
*nic_data
;
1657 bool supports_rx_merge
;
1658 size_t inlen
, outlen
;
1659 dma_addr_t dma_addr
;
1663 nic_data
= efx
->nic_data
;
1665 !!(nic_data
->datapath_caps
&
1666 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN
);
1668 /* Fill event queue with all ones (i.e. empty events) */
1669 memset(channel
->eventq
.buf
.addr
, 0xff, channel
->eventq
.buf
.len
);
1671 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_SIZE
, channel
->eventq_mask
+ 1);
1672 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_INSTANCE
, channel
->channel
);
1673 /* INIT_EVQ expects index in vector table, not absolute */
1674 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_IRQ_NUM
, channel
->channel
);
1675 MCDI_POPULATE_DWORD_4(inbuf
, INIT_EVQ_IN_FLAGS
,
1676 INIT_EVQ_IN_FLAG_INTERRUPTING
, 1,
1677 INIT_EVQ_IN_FLAG_RX_MERGE
, 1,
1678 INIT_EVQ_IN_FLAG_TX_MERGE
, 1,
1679 INIT_EVQ_IN_FLAG_CUT_THRU
, !supports_rx_merge
);
1680 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_MODE
,
1681 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS
);
1682 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_LOAD
, 0);
1683 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_RELOAD
, 0);
1684 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_COUNT_MODE
,
1685 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS
);
1686 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_COUNT_THRSHLD
, 0);
1688 dma_addr
= channel
->eventq
.buf
.dma_addr
;
1689 for (i
= 0; i
< entries
; ++i
) {
1690 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_EVQ_IN_DMA_ADDR
, i
, dma_addr
);
1691 dma_addr
+= EFX_BUF_SIZE
;
1694 inlen
= MC_CMD_INIT_EVQ_IN_LEN(entries
);
1696 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_EVQ
, inbuf
, inlen
,
1697 outbuf
, sizeof(outbuf
), &outlen
);
1698 /* IRQ return is ignored */
1702 static void efx_ef10_ev_fini(struct efx_channel
*channel
)
1704 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_EVQ_IN_LEN
);
1705 MCDI_DECLARE_BUF(outbuf
, MC_CMD_FINI_EVQ_OUT_LEN
);
1706 struct efx_nic
*efx
= channel
->efx
;
1710 MCDI_SET_DWORD(inbuf
, FINI_EVQ_IN_INSTANCE
, channel
->channel
);
1712 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_EVQ
, inbuf
, sizeof(inbuf
),
1713 outbuf
, sizeof(outbuf
), &outlen
);
1715 if (rc
&& rc
!= -EALREADY
)
1721 efx_mcdi_display_error(efx
, MC_CMD_FINI_EVQ
, MC_CMD_FINI_EVQ_IN_LEN
,
1722 outbuf
, outlen
, rc
);
1725 static void efx_ef10_ev_remove(struct efx_channel
*channel
)
1727 efx_nic_free_buffer(channel
->efx
, &channel
->eventq
.buf
);
1730 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue
*rx_queue
,
1731 unsigned int rx_queue_label
)
1733 struct efx_nic
*efx
= rx_queue
->efx
;
1735 netif_info(efx
, hw
, efx
->net_dev
,
1736 "rx event arrived on queue %d labeled as queue %u\n",
1737 efx_rx_queue_index(rx_queue
), rx_queue_label
);
1739 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
1743 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue
*rx_queue
,
1744 unsigned int actual
, unsigned int expected
)
1746 unsigned int dropped
= (actual
- expected
) & rx_queue
->ptr_mask
;
1747 struct efx_nic
*efx
= rx_queue
->efx
;
1749 netif_info(efx
, hw
, efx
->net_dev
,
1750 "dropped %d events (index=%d expected=%d)\n",
1751 dropped
, actual
, expected
);
1753 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
1756 /* partially received RX was aborted. clean up. */
1757 static void efx_ef10_handle_rx_abort(struct efx_rx_queue
*rx_queue
)
1759 unsigned int rx_desc_ptr
;
1761 netif_dbg(rx_queue
->efx
, hw
, rx_queue
->efx
->net_dev
,
1762 "scattered RX aborted (dropping %u buffers)\n",
1763 rx_queue
->scatter_n
);
1765 rx_desc_ptr
= rx_queue
->removed_count
& rx_queue
->ptr_mask
;
1767 efx_rx_packet(rx_queue
, rx_desc_ptr
, rx_queue
->scatter_n
,
1768 0, EFX_RX_PKT_DISCARD
);
1770 rx_queue
->removed_count
+= rx_queue
->scatter_n
;
1771 rx_queue
->scatter_n
= 0;
1772 rx_queue
->scatter_len
= 0;
1773 ++efx_rx_queue_channel(rx_queue
)->n_rx_nodesc_trunc
;
1776 static int efx_ef10_handle_rx_event(struct efx_channel
*channel
,
1777 const efx_qword_t
*event
)
1779 unsigned int rx_bytes
, next_ptr_lbits
, rx_queue_label
, rx_l4_class
;
1780 unsigned int n_descs
, n_packets
, i
;
1781 struct efx_nic
*efx
= channel
->efx
;
1782 struct efx_rx_queue
*rx_queue
;
1786 if (unlikely(ACCESS_ONCE(efx
->reset_pending
)))
1789 /* Basic packet information */
1790 rx_bytes
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_BYTES
);
1791 next_ptr_lbits
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_DSC_PTR_LBITS
);
1792 rx_queue_label
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_QLABEL
);
1793 rx_l4_class
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_L4_CLASS
);
1794 rx_cont
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_CONT
);
1796 if (EFX_QWORD_FIELD(*event
, ESF_DZ_RX_DROP_EVENT
))
1797 netdev_WARN(efx
->net_dev
, "saw RX_DROP_EVENT: event="
1799 EFX_QWORD_VAL(*event
));
1801 rx_queue
= efx_channel_get_rx_queue(channel
);
1803 if (unlikely(rx_queue_label
!= efx_rx_queue_index(rx_queue
)))
1804 efx_ef10_handle_rx_wrong_queue(rx_queue
, rx_queue_label
);
1806 n_descs
= ((next_ptr_lbits
- rx_queue
->removed_count
) &
1807 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH
) - 1));
1809 if (n_descs
!= rx_queue
->scatter_n
+ 1) {
1810 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1812 /* detect rx abort */
1813 if (unlikely(n_descs
== rx_queue
->scatter_n
)) {
1814 if (rx_queue
->scatter_n
== 0 || rx_bytes
!= 0)
1815 netdev_WARN(efx
->net_dev
,
1816 "invalid RX abort: scatter_n=%u event="
1818 rx_queue
->scatter_n
,
1819 EFX_QWORD_VAL(*event
));
1820 efx_ef10_handle_rx_abort(rx_queue
);
1824 /* Check that RX completion merging is valid, i.e.
1825 * the current firmware supports it and this is a
1826 * non-scattered packet.
1828 if (!(nic_data
->datapath_caps
&
1829 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN
)) ||
1830 rx_queue
->scatter_n
!= 0 || rx_cont
) {
1831 efx_ef10_handle_rx_bad_lbits(
1832 rx_queue
, next_ptr_lbits
,
1833 (rx_queue
->removed_count
+
1834 rx_queue
->scatter_n
+ 1) &
1835 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH
) - 1));
1839 /* Merged completion for multiple non-scattered packets */
1840 rx_queue
->scatter_n
= 1;
1841 rx_queue
->scatter_len
= 0;
1842 n_packets
= n_descs
;
1843 ++channel
->n_rx_merge_events
;
1844 channel
->n_rx_merge_packets
+= n_packets
;
1845 flags
|= EFX_RX_PKT_PREFIX_LEN
;
1847 ++rx_queue
->scatter_n
;
1848 rx_queue
->scatter_len
+= rx_bytes
;
1854 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_RX_ECRC_ERR
)))
1855 flags
|= EFX_RX_PKT_DISCARD
;
1857 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_RX_IPCKSUM_ERR
))) {
1858 channel
->n_rx_ip_hdr_chksum_err
+= n_packets
;
1859 } else if (unlikely(EFX_QWORD_FIELD(*event
,
1860 ESF_DZ_RX_TCPUDP_CKSUM_ERR
))) {
1861 channel
->n_rx_tcp_udp_chksum_err
+= n_packets
;
1862 } else if (rx_l4_class
== ESE_DZ_L4_CLASS_TCP
||
1863 rx_l4_class
== ESE_DZ_L4_CLASS_UDP
) {
1864 flags
|= EFX_RX_PKT_CSUMMED
;
1867 if (rx_l4_class
== ESE_DZ_L4_CLASS_TCP
)
1868 flags
|= EFX_RX_PKT_TCP
;
1870 channel
->irq_mod_score
+= 2 * n_packets
;
1872 /* Handle received packet(s) */
1873 for (i
= 0; i
< n_packets
; i
++) {
1874 efx_rx_packet(rx_queue
,
1875 rx_queue
->removed_count
& rx_queue
->ptr_mask
,
1876 rx_queue
->scatter_n
, rx_queue
->scatter_len
,
1878 rx_queue
->removed_count
+= rx_queue
->scatter_n
;
1881 rx_queue
->scatter_n
= 0;
1882 rx_queue
->scatter_len
= 0;
1888 efx_ef10_handle_tx_event(struct efx_channel
*channel
, efx_qword_t
*event
)
1890 struct efx_nic
*efx
= channel
->efx
;
1891 struct efx_tx_queue
*tx_queue
;
1892 unsigned int tx_ev_desc_ptr
;
1893 unsigned int tx_ev_q_label
;
1896 if (unlikely(ACCESS_ONCE(efx
->reset_pending
)))
1899 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_TX_DROP_EVENT
)))
1902 /* Transmit completion */
1903 tx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, ESF_DZ_TX_DESCR_INDX
);
1904 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, ESF_DZ_TX_QLABEL
);
1905 tx_queue
= efx_channel_get_tx_queue(channel
,
1906 tx_ev_q_label
% EFX_TXQ_TYPES
);
1907 tx_descs
= ((tx_ev_desc_ptr
+ 1 - tx_queue
->read_count
) &
1908 tx_queue
->ptr_mask
);
1909 efx_xmit_done(tx_queue
, tx_ev_desc_ptr
& tx_queue
->ptr_mask
);
1915 efx_ef10_handle_driver_event(struct efx_channel
*channel
, efx_qword_t
*event
)
1917 struct efx_nic
*efx
= channel
->efx
;
1920 subcode
= EFX_QWORD_FIELD(*event
, ESF_DZ_DRV_SUB_CODE
);
1923 case ESE_DZ_DRV_TIMER_EV
:
1924 case ESE_DZ_DRV_WAKE_UP_EV
:
1926 case ESE_DZ_DRV_START_UP_EV
:
1927 /* event queue init complete. ok. */
1930 netif_err(efx
, hw
, efx
->net_dev
,
1931 "channel %d unknown driver event type %d"
1932 " (data " EFX_QWORD_FMT
")\n",
1933 channel
->channel
, subcode
,
1934 EFX_QWORD_VAL(*event
));
1939 static void efx_ef10_handle_driver_generated_event(struct efx_channel
*channel
,
1942 struct efx_nic
*efx
= channel
->efx
;
1945 subcode
= EFX_QWORD_FIELD(*event
, EFX_DWORD_0
);
1949 channel
->event_test_cpu
= raw_smp_processor_id();
1951 case EFX_EF10_REFILL
:
1952 /* The queue must be empty, so we won't receive any rx
1953 * events, so efx_process_channel() won't refill the
1954 * queue. Refill it here
1956 efx_fast_push_rx_descriptors(&channel
->rx_queue
, true);
1959 netif_err(efx
, hw
, efx
->net_dev
,
1960 "channel %d unknown driver event type %u"
1961 " (data " EFX_QWORD_FMT
")\n",
1962 channel
->channel
, (unsigned) subcode
,
1963 EFX_QWORD_VAL(*event
));
1967 static int efx_ef10_ev_process(struct efx_channel
*channel
, int quota
)
1969 struct efx_nic
*efx
= channel
->efx
;
1970 efx_qword_t event
, *p_event
;
1971 unsigned int read_ptr
;
1979 read_ptr
= channel
->eventq_read_ptr
;
1982 p_event
= efx_event(channel
, read_ptr
);
1985 if (!efx_event_present(&event
))
1988 EFX_SET_QWORD(*p_event
);
1992 ev_code
= EFX_QWORD_FIELD(event
, ESF_DZ_EV_CODE
);
1994 netif_vdbg(efx
, drv
, efx
->net_dev
,
1995 "processing event on %d " EFX_QWORD_FMT
"\n",
1996 channel
->channel
, EFX_QWORD_VAL(event
));
1999 case ESE_DZ_EV_CODE_MCDI_EV
:
2000 efx_mcdi_process_event(channel
, &event
);
2002 case ESE_DZ_EV_CODE_RX_EV
:
2003 spent
+= efx_ef10_handle_rx_event(channel
, &event
);
2004 if (spent
>= quota
) {
2005 /* XXX can we split a merged event to
2006 * avoid going over-quota?
2012 case ESE_DZ_EV_CODE_TX_EV
:
2013 tx_descs
+= efx_ef10_handle_tx_event(channel
, &event
);
2014 if (tx_descs
> efx
->txq_entries
) {
2017 } else if (++spent
== quota
) {
2021 case ESE_DZ_EV_CODE_DRIVER_EV
:
2022 efx_ef10_handle_driver_event(channel
, &event
);
2023 if (++spent
== quota
)
2026 case EFX_EF10_DRVGEN_EV
:
2027 efx_ef10_handle_driver_generated_event(channel
, &event
);
2030 netif_err(efx
, hw
, efx
->net_dev
,
2031 "channel %d unknown event type %d"
2032 " (data " EFX_QWORD_FMT
")\n",
2033 channel
->channel
, ev_code
,
2034 EFX_QWORD_VAL(event
));
2039 channel
->eventq_read_ptr
= read_ptr
;
2043 static void efx_ef10_ev_read_ack(struct efx_channel
*channel
)
2045 struct efx_nic
*efx
= channel
->efx
;
2048 if (EFX_EF10_WORKAROUND_35388(efx
)) {
2049 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE
<
2050 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH
));
2051 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE
>
2052 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH
));
2054 EFX_POPULATE_DWORD_2(rptr
, ERF_DD_EVQ_IND_RPTR_FLAGS
,
2055 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH
,
2056 ERF_DD_EVQ_IND_RPTR
,
2057 (channel
->eventq_read_ptr
&
2058 channel
->eventq_mask
) >>
2059 ERF_DD_EVQ_IND_RPTR_WIDTH
);
2060 efx_writed_page(efx
, &rptr
, ER_DD_EVQ_INDIRECT
,
2062 EFX_POPULATE_DWORD_2(rptr
, ERF_DD_EVQ_IND_RPTR_FLAGS
,
2063 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW
,
2064 ERF_DD_EVQ_IND_RPTR
,
2065 channel
->eventq_read_ptr
&
2066 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH
) - 1));
2067 efx_writed_page(efx
, &rptr
, ER_DD_EVQ_INDIRECT
,
2070 EFX_POPULATE_DWORD_1(rptr
, ERF_DZ_EVQ_RPTR
,
2071 channel
->eventq_read_ptr
&
2072 channel
->eventq_mask
);
2073 efx_writed_page(efx
, &rptr
, ER_DZ_EVQ_RPTR
, channel
->channel
);
2077 static void efx_ef10_ev_test_generate(struct efx_channel
*channel
)
2079 MCDI_DECLARE_BUF(inbuf
, MC_CMD_DRIVER_EVENT_IN_LEN
);
2080 struct efx_nic
*efx
= channel
->efx
;
2084 EFX_POPULATE_QWORD_2(event
,
2085 ESF_DZ_EV_CODE
, EFX_EF10_DRVGEN_EV
,
2086 ESF_DZ_EV_DATA
, EFX_EF10_TEST
);
2088 MCDI_SET_DWORD(inbuf
, DRIVER_EVENT_IN_EVQ
, channel
->channel
);
2090 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2091 * already swapped the data to little-endian order.
2093 memcpy(MCDI_PTR(inbuf
, DRIVER_EVENT_IN_DATA
), &event
.u64
[0],
2094 sizeof(efx_qword_t
));
2096 rc
= efx_mcdi_rpc(efx
, MC_CMD_DRIVER_EVENT
, inbuf
, sizeof(inbuf
),
2105 netif_err(efx
, hw
, efx
->net_dev
, "%s: failed rc=%d\n", __func__
, rc
);
2108 void efx_ef10_handle_drain_event(struct efx_nic
*efx
)
2110 if (atomic_dec_and_test(&efx
->active_queues
))
2111 wake_up(&efx
->flush_wq
);
2113 WARN_ON(atomic_read(&efx
->active_queues
) < 0);
2116 static int efx_ef10_fini_dmaq(struct efx_nic
*efx
)
2118 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2119 struct efx_channel
*channel
;
2120 struct efx_tx_queue
*tx_queue
;
2121 struct efx_rx_queue
*rx_queue
;
2124 /* If the MC has just rebooted, the TX/RX queues will have already been
2125 * torn down, but efx->active_queues needs to be set to zero.
2127 if (nic_data
->must_realloc_vis
) {
2128 atomic_set(&efx
->active_queues
, 0);
2132 /* Do not attempt to write to the NIC during EEH recovery */
2133 if (efx
->state
!= STATE_RECOVERY
) {
2134 efx_for_each_channel(channel
, efx
) {
2135 efx_for_each_channel_rx_queue(rx_queue
, channel
)
2136 efx_ef10_rx_fini(rx_queue
);
2137 efx_for_each_channel_tx_queue(tx_queue
, channel
)
2138 efx_ef10_tx_fini(tx_queue
);
2141 wait_event_timeout(efx
->flush_wq
,
2142 atomic_read(&efx
->active_queues
) == 0,
2143 msecs_to_jiffies(EFX_MAX_FLUSH_TIME
));
2144 pending
= atomic_read(&efx
->active_queues
);
2146 netif_err(efx
, hw
, efx
->net_dev
, "failed to flush %d queues\n",
2155 static void efx_ef10_prepare_flr(struct efx_nic
*efx
)
2157 atomic_set(&efx
->active_queues
, 0);
2160 static bool efx_ef10_filter_equal(const struct efx_filter_spec
*left
,
2161 const struct efx_filter_spec
*right
)
2163 if ((left
->match_flags
^ right
->match_flags
) |
2164 ((left
->flags
^ right
->flags
) &
2165 (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_TX
)))
2168 return memcmp(&left
->outer_vid
, &right
->outer_vid
,
2169 sizeof(struct efx_filter_spec
) -
2170 offsetof(struct efx_filter_spec
, outer_vid
)) == 0;
2173 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec
*spec
)
2175 BUILD_BUG_ON(offsetof(struct efx_filter_spec
, outer_vid
) & 3);
2176 return jhash2((const u32
*)&spec
->outer_vid
,
2177 (sizeof(struct efx_filter_spec
) -
2178 offsetof(struct efx_filter_spec
, outer_vid
)) / 4,
2180 /* XXX should we randomise the initval? */
2183 /* Decide whether a filter should be exclusive or else should allow
2184 * delivery to additional recipients. Currently we decide that
2185 * filters for specific local unicast MAC and IP addresses are
2188 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec
*spec
)
2190 if (spec
->match_flags
& EFX_FILTER_MATCH_LOC_MAC
&&
2191 !is_multicast_ether_addr(spec
->loc_mac
))
2194 if ((spec
->match_flags
&
2195 (EFX_FILTER_MATCH_ETHER_TYPE
| EFX_FILTER_MATCH_LOC_HOST
)) ==
2196 (EFX_FILTER_MATCH_ETHER_TYPE
| EFX_FILTER_MATCH_LOC_HOST
)) {
2197 if (spec
->ether_type
== htons(ETH_P_IP
) &&
2198 !ipv4_is_multicast(spec
->loc_host
[0]))
2200 if (spec
->ether_type
== htons(ETH_P_IPV6
) &&
2201 ((const u8
*)spec
->loc_host
)[0] != 0xff)
2208 static struct efx_filter_spec
*
2209 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table
*table
,
2210 unsigned int filter_idx
)
2212 return (struct efx_filter_spec
*)(table
->entry
[filter_idx
].spec
&
2213 ~EFX_EF10_FILTER_FLAGS
);
2217 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table
*table
,
2218 unsigned int filter_idx
)
2220 return table
->entry
[filter_idx
].spec
& EFX_EF10_FILTER_FLAGS
;
2224 efx_ef10_filter_set_entry(struct efx_ef10_filter_table
*table
,
2225 unsigned int filter_idx
,
2226 const struct efx_filter_spec
*spec
,
2229 table
->entry
[filter_idx
].spec
= (unsigned long)spec
| flags
;
2232 static void efx_ef10_filter_push_prep(struct efx_nic
*efx
,
2233 const struct efx_filter_spec
*spec
,
2234 efx_dword_t
*inbuf
, u64 handle
,
2237 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2239 memset(inbuf
, 0, MC_CMD_FILTER_OP_IN_LEN
);
2242 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
2243 MC_CMD_FILTER_OP_IN_OP_REPLACE
);
2244 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
, handle
);
2246 u32 match_fields
= 0;
2248 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
2249 efx_ef10_filter_is_exclusive(spec
) ?
2250 MC_CMD_FILTER_OP_IN_OP_INSERT
:
2251 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE
);
2253 /* Convert match flags and values. Unlike almost
2254 * everything else in MCDI, these fields are in
2255 * network byte order.
2257 if (spec
->match_flags
& EFX_FILTER_MATCH_LOC_MAC_IG
)
2259 is_multicast_ether_addr(spec
->loc_mac
) ?
2260 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN
:
2261 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN
;
2262 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2263 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2265 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2266 mcdi_field ## _LBN; \
2268 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2269 sizeof(spec->gen_field)); \
2270 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2271 &spec->gen_field, sizeof(spec->gen_field)); \
2273 COPY_FIELD(REM_HOST
, rem_host
, SRC_IP
);
2274 COPY_FIELD(LOC_HOST
, loc_host
, DST_IP
);
2275 COPY_FIELD(REM_MAC
, rem_mac
, SRC_MAC
);
2276 COPY_FIELD(REM_PORT
, rem_port
, SRC_PORT
);
2277 COPY_FIELD(LOC_MAC
, loc_mac
, DST_MAC
);
2278 COPY_FIELD(LOC_PORT
, loc_port
, DST_PORT
);
2279 COPY_FIELD(ETHER_TYPE
, ether_type
, ETHER_TYPE
);
2280 COPY_FIELD(INNER_VID
, inner_vid
, INNER_VLAN
);
2281 COPY_FIELD(OUTER_VID
, outer_vid
, OUTER_VLAN
);
2282 COPY_FIELD(IP_PROTO
, ip_proto
, IP_PROTO
);
2284 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_MATCH_FIELDS
,
2288 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_PORT_ID
, EVB_PORT_ID_ASSIGNED
);
2289 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_DEST
,
2290 spec
->dmaq_id
== EFX_FILTER_RX_DMAQ_ID_DROP
?
2291 MC_CMD_FILTER_OP_IN_RX_DEST_DROP
:
2292 MC_CMD_FILTER_OP_IN_RX_DEST_HOST
);
2293 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_TX_DEST
,
2294 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT
);
2295 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_QUEUE
,
2296 spec
->dmaq_id
== EFX_FILTER_RX_DMAQ_ID_DROP
?
2298 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_MODE
,
2299 (spec
->flags
& EFX_FILTER_FLAG_RX_RSS
) ?
2300 MC_CMD_FILTER_OP_IN_RX_MODE_RSS
:
2301 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE
);
2302 if (spec
->flags
& EFX_FILTER_FLAG_RX_RSS
)
2303 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_CONTEXT
,
2304 spec
->rss_context
!=
2305 EFX_FILTER_RSS_CONTEXT_DEFAULT
?
2306 spec
->rss_context
: nic_data
->rx_rss_context
);
2309 static int efx_ef10_filter_push(struct efx_nic
*efx
,
2310 const struct efx_filter_spec
*spec
,
2311 u64
*handle
, bool replacing
)
2313 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
2314 MCDI_DECLARE_BUF(outbuf
, MC_CMD_FILTER_OP_OUT_LEN
);
2317 efx_ef10_filter_push_prep(efx
, spec
, inbuf
, *handle
, replacing
);
2318 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
2319 outbuf
, sizeof(outbuf
), NULL
);
2321 *handle
= MCDI_QWORD(outbuf
, FILTER_OP_OUT_HANDLE
);
2323 rc
= -EBUSY
; /* to match efx_farch_filter_insert() */
2327 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table
*table
,
2328 enum efx_filter_match_flags match_flags
)
2330 unsigned int match_pri
;
2333 match_pri
< table
->rx_match_count
;
2335 if (table
->rx_match_flags
[match_pri
] == match_flags
)
2338 return -EPROTONOSUPPORT
;
2341 static s32
efx_ef10_filter_insert(struct efx_nic
*efx
,
2342 struct efx_filter_spec
*spec
,
2345 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2346 DECLARE_BITMAP(mc_rem_map
, EFX_EF10_FILTER_SEARCH_LIMIT
);
2347 struct efx_filter_spec
*saved_spec
;
2348 unsigned int match_pri
, hash
;
2349 unsigned int priv_flags
;
2350 bool replacing
= false;
2356 /* For now, only support RX filters */
2357 if ((spec
->flags
& (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_TX
)) !=
2361 rc
= efx_ef10_filter_rx_match_pri(table
, spec
->match_flags
);
2366 hash
= efx_ef10_filter_hash(spec
);
2367 is_mc_recip
= efx_filter_is_mc_recipient(spec
);
2369 bitmap_zero(mc_rem_map
, EFX_EF10_FILTER_SEARCH_LIMIT
);
2371 /* Find any existing filters with the same match tuple or
2372 * else a free slot to insert at. If any of them are busy,
2373 * we have to wait and retry.
2376 unsigned int depth
= 1;
2379 spin_lock_bh(&efx
->filter_lock
);
2382 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
2383 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
2388 } else if (efx_ef10_filter_equal(spec
, saved_spec
)) {
2389 if (table
->entry
[i
].spec
&
2390 EFX_EF10_FILTER_FLAG_BUSY
)
2392 if (spec
->priority
< saved_spec
->priority
&&
2393 spec
->priority
!= EFX_FILTER_PRI_AUTO
) {
2398 /* This is the only one */
2399 if (spec
->priority
==
2400 saved_spec
->priority
&&
2407 } else if (spec
->priority
>
2408 saved_spec
->priority
||
2410 saved_spec
->priority
&&
2415 __set_bit(depth
, mc_rem_map
);
2419 /* Once we reach the maximum search depth, use
2420 * the first suitable slot or return -EBUSY if
2423 if (depth
== EFX_EF10_FILTER_SEARCH_LIMIT
) {
2424 if (ins_index
< 0) {
2434 prepare_to_wait(&table
->waitq
, &wait
, TASK_UNINTERRUPTIBLE
);
2435 spin_unlock_bh(&efx
->filter_lock
);
2440 /* Create a software table entry if necessary, and mark it
2441 * busy. We might yet fail to insert, but any attempt to
2442 * insert a conflicting filter while we're waiting for the
2443 * firmware must find the busy entry.
2445 saved_spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
2447 if (spec
->priority
== EFX_FILTER_PRI_AUTO
&&
2448 saved_spec
->priority
>= EFX_FILTER_PRI_AUTO
) {
2449 /* Just make sure it won't be removed */
2450 if (saved_spec
->priority
> EFX_FILTER_PRI_AUTO
)
2451 saved_spec
->flags
|= EFX_FILTER_FLAG_RX_OVER_AUTO
;
2452 table
->entry
[ins_index
].spec
&=
2453 ~EFX_EF10_FILTER_FLAG_AUTO_OLD
;
2458 priv_flags
= efx_ef10_filter_entry_flags(table
, ins_index
);
2460 saved_spec
= kmalloc(sizeof(*spec
), GFP_ATOMIC
);
2465 *saved_spec
= *spec
;
2468 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
,
2469 priv_flags
| EFX_EF10_FILTER_FLAG_BUSY
);
2471 /* Mark lower-priority multicast recipients busy prior to removal */
2473 unsigned int depth
, i
;
2475 for (depth
= 0; depth
< EFX_EF10_FILTER_SEARCH_LIMIT
; depth
++) {
2476 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
2477 if (test_bit(depth
, mc_rem_map
))
2478 table
->entry
[i
].spec
|=
2479 EFX_EF10_FILTER_FLAG_BUSY
;
2483 spin_unlock_bh(&efx
->filter_lock
);
2485 rc
= efx_ef10_filter_push(efx
, spec
, &table
->entry
[ins_index
].handle
,
2488 /* Finalise the software table entry */
2489 spin_lock_bh(&efx
->filter_lock
);
2492 /* Update the fields that may differ */
2493 if (saved_spec
->priority
== EFX_FILTER_PRI_AUTO
)
2494 saved_spec
->flags
|=
2495 EFX_FILTER_FLAG_RX_OVER_AUTO
;
2496 saved_spec
->priority
= spec
->priority
;
2497 saved_spec
->flags
&= EFX_FILTER_FLAG_RX_OVER_AUTO
;
2498 saved_spec
->flags
|= spec
->flags
;
2499 saved_spec
->rss_context
= spec
->rss_context
;
2500 saved_spec
->dmaq_id
= spec
->dmaq_id
;
2502 } else if (!replacing
) {
2506 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
, priv_flags
);
2508 /* Remove and finalise entries for lower-priority multicast
2512 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
2513 unsigned int depth
, i
;
2515 memset(inbuf
, 0, sizeof(inbuf
));
2517 for (depth
= 0; depth
< EFX_EF10_FILTER_SEARCH_LIMIT
; depth
++) {
2518 if (!test_bit(depth
, mc_rem_map
))
2521 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
2522 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
2523 priv_flags
= efx_ef10_filter_entry_flags(table
, i
);
2526 spin_unlock_bh(&efx
->filter_lock
);
2527 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
2528 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
2529 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
2530 table
->entry
[i
].handle
);
2531 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
,
2532 inbuf
, sizeof(inbuf
),
2534 spin_lock_bh(&efx
->filter_lock
);
2542 priv_flags
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
2544 efx_ef10_filter_set_entry(table
, i
, saved_spec
,
2549 /* If successful, return the inserted filter ID */
2551 rc
= match_pri
* HUNT_FILTER_TBL_ROWS
+ ins_index
;
2553 wake_up_all(&table
->waitq
);
2555 spin_unlock_bh(&efx
->filter_lock
);
2556 finish_wait(&table
->waitq
, &wait
);
2560 static void efx_ef10_filter_update_rx_scatter(struct efx_nic
*efx
)
2562 /* no need to do anything here on EF10 */
2566 * If !by_index, remove by ID
2567 * If by_index, remove by index
2568 * Filter ID may come from userland and must be range-checked.
2570 static int efx_ef10_filter_remove_internal(struct efx_nic
*efx
,
2571 unsigned int priority_mask
,
2572 u32 filter_id
, bool by_index
)
2574 unsigned int filter_idx
= filter_id
% HUNT_FILTER_TBL_ROWS
;
2575 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2576 MCDI_DECLARE_BUF(inbuf
,
2577 MC_CMD_FILTER_OP_IN_HANDLE_OFST
+
2578 MC_CMD_FILTER_OP_IN_HANDLE_LEN
);
2579 struct efx_filter_spec
*spec
;
2583 /* Find the software table entry and mark it busy. Don't
2584 * remove it yet; any attempt to update while we're waiting
2585 * for the firmware must find the busy entry.
2588 spin_lock_bh(&efx
->filter_lock
);
2589 if (!(table
->entry
[filter_idx
].spec
&
2590 EFX_EF10_FILTER_FLAG_BUSY
))
2592 prepare_to_wait(&table
->waitq
, &wait
, TASK_UNINTERRUPTIBLE
);
2593 spin_unlock_bh(&efx
->filter_lock
);
2597 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
2600 efx_ef10_filter_rx_match_pri(table
, spec
->match_flags
) !=
2601 filter_id
/ HUNT_FILTER_TBL_ROWS
)) {
2606 if (spec
->flags
& EFX_FILTER_FLAG_RX_OVER_AUTO
&&
2607 priority_mask
== (1U << EFX_FILTER_PRI_AUTO
)) {
2608 /* Just remove flags */
2609 spec
->flags
&= ~EFX_FILTER_FLAG_RX_OVER_AUTO
;
2610 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_AUTO_OLD
;
2615 if (!(priority_mask
& (1U << spec
->priority
))) {
2620 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
2621 spin_unlock_bh(&efx
->filter_lock
);
2623 if (spec
->flags
& EFX_FILTER_FLAG_RX_OVER_AUTO
) {
2624 /* Reset to an automatic filter */
2626 struct efx_filter_spec new_spec
= *spec
;
2628 new_spec
.priority
= EFX_FILTER_PRI_AUTO
;
2629 new_spec
.flags
= (EFX_FILTER_FLAG_RX
|
2630 EFX_FILTER_FLAG_RX_RSS
);
2631 new_spec
.dmaq_id
= 0;
2632 new_spec
.rss_context
= EFX_FILTER_RSS_CONTEXT_DEFAULT
;
2633 rc
= efx_ef10_filter_push(efx
, &new_spec
,
2634 &table
->entry
[filter_idx
].handle
,
2637 spin_lock_bh(&efx
->filter_lock
);
2641 /* Really remove the filter */
2643 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
2644 efx_ef10_filter_is_exclusive(spec
) ?
2645 MC_CMD_FILTER_OP_IN_OP_REMOVE
:
2646 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
2647 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
2648 table
->entry
[filter_idx
].handle
);
2649 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
,
2650 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
2652 spin_lock_bh(&efx
->filter_lock
);
2655 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
2659 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
2660 wake_up_all(&table
->waitq
);
2662 spin_unlock_bh(&efx
->filter_lock
);
2663 finish_wait(&table
->waitq
, &wait
);
2667 static int efx_ef10_filter_remove_safe(struct efx_nic
*efx
,
2668 enum efx_filter_priority priority
,
2671 return efx_ef10_filter_remove_internal(efx
, 1U << priority
,
2675 static int efx_ef10_filter_get_safe(struct efx_nic
*efx
,
2676 enum efx_filter_priority priority
,
2677 u32 filter_id
, struct efx_filter_spec
*spec
)
2679 unsigned int filter_idx
= filter_id
% HUNT_FILTER_TBL_ROWS
;
2680 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2681 const struct efx_filter_spec
*saved_spec
;
2684 spin_lock_bh(&efx
->filter_lock
);
2685 saved_spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
2686 if (saved_spec
&& saved_spec
->priority
== priority
&&
2687 efx_ef10_filter_rx_match_pri(table
, saved_spec
->match_flags
) ==
2688 filter_id
/ HUNT_FILTER_TBL_ROWS
) {
2689 *spec
= *saved_spec
;
2694 spin_unlock_bh(&efx
->filter_lock
);
2698 static int efx_ef10_filter_clear_rx(struct efx_nic
*efx
,
2699 enum efx_filter_priority priority
)
2701 unsigned int priority_mask
;
2705 priority_mask
= (((1U << (priority
+ 1)) - 1) &
2706 ~(1U << EFX_FILTER_PRI_AUTO
));
2708 for (i
= 0; i
< HUNT_FILTER_TBL_ROWS
; i
++) {
2709 rc
= efx_ef10_filter_remove_internal(efx
, priority_mask
,
2711 if (rc
&& rc
!= -ENOENT
)
2718 static u32
efx_ef10_filter_count_rx_used(struct efx_nic
*efx
,
2719 enum efx_filter_priority priority
)
2721 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2722 unsigned int filter_idx
;
2725 spin_lock_bh(&efx
->filter_lock
);
2726 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
2727 if (table
->entry
[filter_idx
].spec
&&
2728 efx_ef10_filter_entry_spec(table
, filter_idx
)->priority
==
2732 spin_unlock_bh(&efx
->filter_lock
);
2736 static u32
efx_ef10_filter_get_rx_id_limit(struct efx_nic
*efx
)
2738 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2740 return table
->rx_match_count
* HUNT_FILTER_TBL_ROWS
;
2743 static s32
efx_ef10_filter_get_rx_ids(struct efx_nic
*efx
,
2744 enum efx_filter_priority priority
,
2747 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2748 struct efx_filter_spec
*spec
;
2749 unsigned int filter_idx
;
2752 spin_lock_bh(&efx
->filter_lock
);
2753 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
2754 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
2755 if (spec
&& spec
->priority
== priority
) {
2756 if (count
== size
) {
2760 buf
[count
++] = (efx_ef10_filter_rx_match_pri(
2761 table
, spec
->match_flags
) *
2762 HUNT_FILTER_TBL_ROWS
+
2766 spin_unlock_bh(&efx
->filter_lock
);
2770 #ifdef CONFIG_RFS_ACCEL
2772 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete
;
2774 static s32
efx_ef10_filter_rfs_insert(struct efx_nic
*efx
,
2775 struct efx_filter_spec
*spec
)
2777 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2778 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
2779 struct efx_filter_spec
*saved_spec
;
2780 unsigned int hash
, i
, depth
= 1;
2781 bool replacing
= false;
2786 /* Must be an RX filter without RSS and not for a multicast
2787 * destination address (RFS only works for connected sockets).
2788 * These restrictions allow us to pass only a tiny amount of
2789 * data through to the completion function.
2791 EFX_WARN_ON_PARANOID(spec
->flags
!=
2792 (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_RX_SCATTER
));
2793 EFX_WARN_ON_PARANOID(spec
->priority
!= EFX_FILTER_PRI_HINT
);
2794 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec
));
2796 hash
= efx_ef10_filter_hash(spec
);
2798 spin_lock_bh(&efx
->filter_lock
);
2800 /* Find any existing filter with the same match tuple or else
2801 * a free slot to insert at. If an existing filter is busy,
2802 * we have to give up.
2805 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
2806 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
2811 } else if (efx_ef10_filter_equal(spec
, saved_spec
)) {
2812 if (table
->entry
[i
].spec
& EFX_EF10_FILTER_FLAG_BUSY
) {
2816 if (spec
->priority
< saved_spec
->priority
) {
2824 /* Once we reach the maximum search depth, use the
2825 * first suitable slot or return -EBUSY if there was
2828 if (depth
== EFX_EF10_FILTER_SEARCH_LIMIT
) {
2829 if (ins_index
< 0) {
2839 /* Create a software table entry if necessary, and mark it
2840 * busy. We might yet fail to insert, but any attempt to
2841 * insert a conflicting filter while we're waiting for the
2842 * firmware must find the busy entry.
2844 saved_spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
2848 saved_spec
= kmalloc(sizeof(*spec
), GFP_ATOMIC
);
2853 *saved_spec
= *spec
;
2855 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
,
2856 EFX_EF10_FILTER_FLAG_BUSY
);
2858 spin_unlock_bh(&efx
->filter_lock
);
2860 /* Pack up the variables needed on completion */
2861 cookie
= replacing
<< 31 | ins_index
<< 16 | spec
->dmaq_id
;
2863 efx_ef10_filter_push_prep(efx
, spec
, inbuf
,
2864 table
->entry
[ins_index
].handle
, replacing
);
2865 efx_mcdi_rpc_async(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
2866 MC_CMD_FILTER_OP_OUT_LEN
,
2867 efx_ef10_filter_rfs_insert_complete
, cookie
);
2872 spin_unlock_bh(&efx
->filter_lock
);
2877 efx_ef10_filter_rfs_insert_complete(struct efx_nic
*efx
, unsigned long cookie
,
2878 int rc
, efx_dword_t
*outbuf
,
2879 size_t outlen_actual
)
2881 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2882 unsigned int ins_index
, dmaq_id
;
2883 struct efx_filter_spec
*spec
;
2886 /* Unpack the cookie */
2887 replacing
= cookie
>> 31;
2888 ins_index
= (cookie
>> 16) & (HUNT_FILTER_TBL_ROWS
- 1);
2889 dmaq_id
= cookie
& 0xffff;
2891 spin_lock_bh(&efx
->filter_lock
);
2892 spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
2894 table
->entry
[ins_index
].handle
=
2895 MCDI_QWORD(outbuf
, FILTER_OP_OUT_HANDLE
);
2897 spec
->dmaq_id
= dmaq_id
;
2898 } else if (!replacing
) {
2902 efx_ef10_filter_set_entry(table
, ins_index
, spec
, 0);
2903 spin_unlock_bh(&efx
->filter_lock
);
2905 wake_up_all(&table
->waitq
);
2909 efx_ef10_filter_rfs_expire_complete(struct efx_nic
*efx
,
2910 unsigned long filter_idx
,
2911 int rc
, efx_dword_t
*outbuf
,
2912 size_t outlen_actual
);
2914 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic
*efx
, u32 flow_id
,
2915 unsigned int filter_idx
)
2917 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2918 struct efx_filter_spec
*spec
=
2919 efx_ef10_filter_entry_spec(table
, filter_idx
);
2920 MCDI_DECLARE_BUF(inbuf
,
2921 MC_CMD_FILTER_OP_IN_HANDLE_OFST
+
2922 MC_CMD_FILTER_OP_IN_HANDLE_LEN
);
2925 (table
->entry
[filter_idx
].spec
& EFX_EF10_FILTER_FLAG_BUSY
) ||
2926 spec
->priority
!= EFX_FILTER_PRI_HINT
||
2927 !rps_may_expire_flow(efx
->net_dev
, spec
->dmaq_id
,
2928 flow_id
, filter_idx
))
2931 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
2932 MC_CMD_FILTER_OP_IN_OP_REMOVE
);
2933 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
2934 table
->entry
[filter_idx
].handle
);
2935 if (efx_mcdi_rpc_async(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
), 0,
2936 efx_ef10_filter_rfs_expire_complete
, filter_idx
))
2939 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
2944 efx_ef10_filter_rfs_expire_complete(struct efx_nic
*efx
,
2945 unsigned long filter_idx
,
2946 int rc
, efx_dword_t
*outbuf
,
2947 size_t outlen_actual
)
2949 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2950 struct efx_filter_spec
*spec
=
2951 efx_ef10_filter_entry_spec(table
, filter_idx
);
2953 spin_lock_bh(&efx
->filter_lock
);
2956 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
2958 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
2959 wake_up_all(&table
->waitq
);
2960 spin_unlock_bh(&efx
->filter_lock
);
2963 #endif /* CONFIG_RFS_ACCEL */
2965 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags
)
2967 int match_flags
= 0;
2969 #define MAP_FLAG(gen_flag, mcdi_field) { \
2970 u32 old_mcdi_flags = mcdi_flags; \
2971 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2972 mcdi_field ## _LBN); \
2973 if (mcdi_flags != old_mcdi_flags) \
2974 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
2976 MAP_FLAG(LOC_MAC_IG
, UNKNOWN_UCAST_DST
);
2977 MAP_FLAG(LOC_MAC_IG
, UNKNOWN_MCAST_DST
);
2978 MAP_FLAG(REM_HOST
, SRC_IP
);
2979 MAP_FLAG(LOC_HOST
, DST_IP
);
2980 MAP_FLAG(REM_MAC
, SRC_MAC
);
2981 MAP_FLAG(REM_PORT
, SRC_PORT
);
2982 MAP_FLAG(LOC_MAC
, DST_MAC
);
2983 MAP_FLAG(LOC_PORT
, DST_PORT
);
2984 MAP_FLAG(ETHER_TYPE
, ETHER_TYPE
);
2985 MAP_FLAG(INNER_VID
, INNER_VLAN
);
2986 MAP_FLAG(OUTER_VID
, OUTER_VLAN
);
2987 MAP_FLAG(IP_PROTO
, IP_PROTO
);
2990 /* Did we map them all? */
2997 static int efx_ef10_filter_table_probe(struct efx_nic
*efx
)
2999 MCDI_DECLARE_BUF(inbuf
, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN
);
3000 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX
);
3001 unsigned int pd_match_pri
, pd_match_count
;
3002 struct efx_ef10_filter_table
*table
;
3006 table
= kzalloc(sizeof(*table
), GFP_KERNEL
);
3010 /* Find out which RX filter types are supported, and their priorities */
3011 MCDI_SET_DWORD(inbuf
, GET_PARSER_DISP_INFO_IN_OP
,
3012 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES
);
3013 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_PARSER_DISP_INFO
,
3014 inbuf
, sizeof(inbuf
), outbuf
, sizeof(outbuf
),
3018 pd_match_count
= MCDI_VAR_ARRAY_LEN(
3019 outlen
, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES
);
3020 table
->rx_match_count
= 0;
3022 for (pd_match_pri
= 0; pd_match_pri
< pd_match_count
; pd_match_pri
++) {
3026 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES
,
3028 rc
= efx_ef10_filter_match_flags_from_mcdi(mcdi_flags
);
3030 netif_dbg(efx
, probe
, efx
->net_dev
,
3031 "%s: fw flags %#x pri %u not supported in driver\n",
3032 __func__
, mcdi_flags
, pd_match_pri
);
3034 netif_dbg(efx
, probe
, efx
->net_dev
,
3035 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3036 __func__
, mcdi_flags
, pd_match_pri
,
3037 rc
, table
->rx_match_count
);
3038 table
->rx_match_flags
[table
->rx_match_count
++] = rc
;
3042 table
->entry
= vzalloc(HUNT_FILTER_TBL_ROWS
* sizeof(*table
->entry
));
3043 if (!table
->entry
) {
3048 efx
->filter_state
= table
;
3049 init_waitqueue_head(&table
->waitq
);
3057 static void efx_ef10_filter_table_restore(struct efx_nic
*efx
)
3059 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3060 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
3061 struct efx_filter_spec
*spec
;
3062 unsigned int filter_idx
;
3063 bool failed
= false;
3066 if (!nic_data
->must_restore_filters
)
3069 spin_lock_bh(&efx
->filter_lock
);
3071 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3072 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3076 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
3077 spin_unlock_bh(&efx
->filter_lock
);
3079 rc
= efx_ef10_filter_push(efx
, spec
,
3080 &table
->entry
[filter_idx
].handle
,
3085 spin_lock_bh(&efx
->filter_lock
);
3088 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
3090 table
->entry
[filter_idx
].spec
&=
3091 ~EFX_EF10_FILTER_FLAG_BUSY
;
3095 spin_unlock_bh(&efx
->filter_lock
);
3098 netif_err(efx
, hw
, efx
->net_dev
,
3099 "unable to restore all filters\n");
3101 nic_data
->must_restore_filters
= false;
3104 static void efx_ef10_filter_table_remove(struct efx_nic
*efx
)
3106 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3107 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3108 struct efx_filter_spec
*spec
;
3109 unsigned int filter_idx
;
3112 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3113 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3117 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3118 efx_ef10_filter_is_exclusive(spec
) ?
3119 MC_CMD_FILTER_OP_IN_OP_REMOVE
:
3120 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
3121 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3122 table
->entry
[filter_idx
].handle
);
3123 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
3126 netdev_WARN(efx
->net_dev
,
3127 "filter_idx=%#x handle=%#llx\n",
3129 table
->entry
[filter_idx
].handle
);
3133 vfree(table
->entry
);
3137 static void efx_ef10_filter_sync_rx_mode(struct efx_nic
*efx
)
3139 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3140 struct net_device
*net_dev
= efx
->net_dev
;
3141 struct efx_filter_spec spec
;
3142 bool remove_failed
= false;
3143 struct netdev_hw_addr
*uc
;
3144 struct netdev_hw_addr
*mc
;
3145 unsigned int filter_idx
;
3148 if (!efx_dev_registered(efx
))
3151 /* Mark old filters that may need to be removed */
3152 spin_lock_bh(&efx
->filter_lock
);
3153 n
= table
->dev_uc_count
< 0 ? 1 : table
->dev_uc_count
;
3154 for (i
= 0; i
< n
; i
++) {
3155 filter_idx
= table
->dev_uc_list
[i
].id
% HUNT_FILTER_TBL_ROWS
;
3156 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_AUTO_OLD
;
3158 n
= table
->dev_mc_count
< 0 ? 1 : table
->dev_mc_count
;
3159 for (i
= 0; i
< n
; i
++) {
3160 filter_idx
= table
->dev_mc_list
[i
].id
% HUNT_FILTER_TBL_ROWS
;
3161 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_AUTO_OLD
;
3163 spin_unlock_bh(&efx
->filter_lock
);
3165 /* Copy/convert the address lists; add the primary station
3166 * address and broadcast address
3168 netif_addr_lock_bh(net_dev
);
3169 if (net_dev
->flags
& IFF_PROMISC
||
3170 netdev_uc_count(net_dev
) >= EFX_EF10_FILTER_DEV_UC_MAX
) {
3171 table
->dev_uc_count
= -1;
3173 table
->dev_uc_count
= 1 + netdev_uc_count(net_dev
);
3174 ether_addr_copy(table
->dev_uc_list
[0].addr
, net_dev
->dev_addr
);
3176 netdev_for_each_uc_addr(uc
, net_dev
) {
3177 ether_addr_copy(table
->dev_uc_list
[i
].addr
, uc
->addr
);
3181 if (net_dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
) ||
3182 netdev_mc_count(net_dev
) >= EFX_EF10_FILTER_DEV_MC_MAX
) {
3183 table
->dev_mc_count
= -1;
3185 table
->dev_mc_count
= 1 + netdev_mc_count(net_dev
);
3186 eth_broadcast_addr(table
->dev_mc_list
[0].addr
);
3188 netdev_for_each_mc_addr(mc
, net_dev
) {
3189 ether_addr_copy(table
->dev_mc_list
[i
].addr
, mc
->addr
);
3193 netif_addr_unlock_bh(net_dev
);
3195 /* Insert/renew unicast filters */
3196 if (table
->dev_uc_count
>= 0) {
3197 for (i
= 0; i
< table
->dev_uc_count
; i
++) {
3198 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
3199 EFX_FILTER_FLAG_RX_RSS
,
3201 efx_filter_set_eth_local(&spec
, EFX_FILTER_VID_UNSPEC
,
3202 table
->dev_uc_list
[i
].addr
);
3203 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
3205 /* Fall back to unicast-promisc */
3207 efx_ef10_filter_remove_safe(
3208 efx
, EFX_FILTER_PRI_AUTO
,
3209 table
->dev_uc_list
[i
].id
);
3210 table
->dev_uc_count
= -1;
3213 table
->dev_uc_list
[i
].id
= rc
;
3216 if (table
->dev_uc_count
< 0) {
3217 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
3218 EFX_FILTER_FLAG_RX_RSS
,
3220 efx_filter_set_uc_def(&spec
);
3221 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
3224 table
->dev_uc_count
= 0;
3226 table
->dev_uc_list
[0].id
= rc
;
3230 /* Insert/renew multicast filters */
3231 if (table
->dev_mc_count
>= 0) {
3232 for (i
= 0; i
< table
->dev_mc_count
; i
++) {
3233 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
3234 EFX_FILTER_FLAG_RX_RSS
,
3236 efx_filter_set_eth_local(&spec
, EFX_FILTER_VID_UNSPEC
,
3237 table
->dev_mc_list
[i
].addr
);
3238 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
3240 /* Fall back to multicast-promisc */
3242 efx_ef10_filter_remove_safe(
3243 efx
, EFX_FILTER_PRI_AUTO
,
3244 table
->dev_mc_list
[i
].id
);
3245 table
->dev_mc_count
= -1;
3248 table
->dev_mc_list
[i
].id
= rc
;
3251 if (table
->dev_mc_count
< 0) {
3252 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
3253 EFX_FILTER_FLAG_RX_RSS
,
3255 efx_filter_set_mc_def(&spec
);
3256 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
3259 table
->dev_mc_count
= 0;
3261 table
->dev_mc_list
[0].id
= rc
;
3265 /* Remove filters that weren't renewed. Since nothing else
3266 * changes the AUTO_OLD flag or removes these filters, we
3267 * don't need to hold the filter_lock while scanning for
3270 for (i
= 0; i
< HUNT_FILTER_TBL_ROWS
; i
++) {
3271 if (ACCESS_ONCE(table
->entry
[i
].spec
) &
3272 EFX_EF10_FILTER_FLAG_AUTO_OLD
) {
3273 if (efx_ef10_filter_remove_internal(
3274 efx
, 1U << EFX_FILTER_PRI_AUTO
,
3276 remove_failed
= true;
3279 WARN_ON(remove_failed
);
3282 static int efx_ef10_mac_reconfigure(struct efx_nic
*efx
)
3284 efx_ef10_filter_sync_rx_mode(efx
);
3286 return efx_mcdi_set_mac(efx
);
3289 static int efx_ef10_start_bist(struct efx_nic
*efx
, u32 bist_type
)
3291 MCDI_DECLARE_BUF(inbuf
, MC_CMD_START_BIST_IN_LEN
);
3293 MCDI_SET_DWORD(inbuf
, START_BIST_IN_TYPE
, bist_type
);
3294 return efx_mcdi_rpc(efx
, MC_CMD_START_BIST
, inbuf
, sizeof(inbuf
),
3298 /* MC BISTs follow a different poll mechanism to phy BISTs.
3299 * The BIST is done in the poll handler on the MC, and the MCDI command
3300 * will block until the BIST is done.
3302 static int efx_ef10_poll_bist(struct efx_nic
*efx
)
3305 MCDI_DECLARE_BUF(outbuf
, MC_CMD_POLL_BIST_OUT_LEN
);
3309 rc
= efx_mcdi_rpc(efx
, MC_CMD_POLL_BIST
, NULL
, 0,
3310 outbuf
, sizeof(outbuf
), &outlen
);
3314 if (outlen
< MC_CMD_POLL_BIST_OUT_LEN
)
3317 result
= MCDI_DWORD(outbuf
, POLL_BIST_OUT_RESULT
);
3319 case MC_CMD_POLL_BIST_PASSED
:
3320 netif_dbg(efx
, hw
, efx
->net_dev
, "BIST passed.\n");
3322 case MC_CMD_POLL_BIST_TIMEOUT
:
3323 netif_err(efx
, hw
, efx
->net_dev
, "BIST timed out\n");
3325 case MC_CMD_POLL_BIST_FAILED
:
3326 netif_err(efx
, hw
, efx
->net_dev
, "BIST failed.\n");
3329 netif_err(efx
, hw
, efx
->net_dev
,
3330 "BIST returned unknown result %u", result
);
3335 static int efx_ef10_run_bist(struct efx_nic
*efx
, u32 bist_type
)
3339 netif_dbg(efx
, drv
, efx
->net_dev
, "starting BIST type %u\n", bist_type
);
3341 rc
= efx_ef10_start_bist(efx
, bist_type
);
3345 return efx_ef10_poll_bist(efx
);
3349 efx_ef10_test_chip(struct efx_nic
*efx
, struct efx_self_tests
*tests
)
3353 efx_reset_down(efx
, RESET_TYPE_WORLD
);
3355 rc
= efx_mcdi_rpc(efx
, MC_CMD_ENABLE_OFFLINE_BIST
,
3356 NULL
, 0, NULL
, 0, NULL
);
3360 tests
->memory
= efx_ef10_run_bist(efx
, MC_CMD_MC_MEM_BIST
) ? -1 : 1;
3361 tests
->registers
= efx_ef10_run_bist(efx
, MC_CMD_REG_BIST
) ? -1 : 1;
3363 rc
= efx_mcdi_reset(efx
, RESET_TYPE_WORLD
);
3366 rc2
= efx_reset_up(efx
, RESET_TYPE_WORLD
, rc
== 0);
3367 return rc
? rc
: rc2
;
3370 #ifdef CONFIG_SFC_MTD
3372 struct efx_ef10_nvram_type_info
{
3373 u16 type
, type_mask
;
3378 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types
[] = {
3379 { NVRAM_PARTITION_TYPE_MC_FIRMWARE
, 0, 0, "sfc_mcfw" },
3380 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP
, 0, 0, "sfc_mcfw_backup" },
3381 { NVRAM_PARTITION_TYPE_EXPANSION_ROM
, 0, 0, "sfc_exp_rom" },
3382 { NVRAM_PARTITION_TYPE_STATIC_CONFIG
, 0, 0, "sfc_static_cfg" },
3383 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG
, 0, 0, "sfc_dynamic_cfg" },
3384 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0
, 0, 0, "sfc_exp_rom_cfg" },
3385 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1
, 0, 1, "sfc_exp_rom_cfg" },
3386 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2
, 0, 2, "sfc_exp_rom_cfg" },
3387 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3
, 0, 3, "sfc_exp_rom_cfg" },
3388 { NVRAM_PARTITION_TYPE_LICENSE
, 0, 0, "sfc_license" },
3389 { NVRAM_PARTITION_TYPE_PHY_MIN
, 0xff, 0, "sfc_phy_fw" },
3392 static int efx_ef10_mtd_probe_partition(struct efx_nic
*efx
,
3393 struct efx_mcdi_mtd_partition
*part
,
3396 MCDI_DECLARE_BUF(inbuf
, MC_CMD_NVRAM_METADATA_IN_LEN
);
3397 MCDI_DECLARE_BUF(outbuf
, MC_CMD_NVRAM_METADATA_OUT_LENMAX
);
3398 const struct efx_ef10_nvram_type_info
*info
;
3399 size_t size
, erase_size
, outlen
;
3403 for (info
= efx_ef10_nvram_types
; ; info
++) {
3405 efx_ef10_nvram_types
+ ARRAY_SIZE(efx_ef10_nvram_types
))
3407 if ((type
& ~info
->type_mask
) == info
->type
)
3410 if (info
->port
!= efx_port_num(efx
))
3413 rc
= efx_mcdi_nvram_info(efx
, type
, &size
, &erase_size
, &protected);
3417 return -ENODEV
; /* hide it */
3419 part
->nvram_type
= type
;
3421 MCDI_SET_DWORD(inbuf
, NVRAM_METADATA_IN_TYPE
, type
);
3422 rc
= efx_mcdi_rpc(efx
, MC_CMD_NVRAM_METADATA
, inbuf
, sizeof(inbuf
),
3423 outbuf
, sizeof(outbuf
), &outlen
);
3426 if (outlen
< MC_CMD_NVRAM_METADATA_OUT_LENMIN
)
3428 if (MCDI_DWORD(outbuf
, NVRAM_METADATA_OUT_FLAGS
) &
3429 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN
))
3430 part
->fw_subtype
= MCDI_DWORD(outbuf
,
3431 NVRAM_METADATA_OUT_SUBTYPE
);
3433 part
->common
.dev_type_name
= "EF10 NVRAM manager";
3434 part
->common
.type_name
= info
->name
;
3436 part
->common
.mtd
.type
= MTD_NORFLASH
;
3437 part
->common
.mtd
.flags
= MTD_CAP_NORFLASH
;
3438 part
->common
.mtd
.size
= size
;
3439 part
->common
.mtd
.erasesize
= erase_size
;
3444 static int efx_ef10_mtd_probe(struct efx_nic
*efx
)
3446 MCDI_DECLARE_BUF(outbuf
, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX
);
3447 struct efx_mcdi_mtd_partition
*parts
;
3448 size_t outlen
, n_parts_total
, i
, n_parts
;
3454 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN
!= 0);
3455 rc
= efx_mcdi_rpc(efx
, MC_CMD_NVRAM_PARTITIONS
, NULL
, 0,
3456 outbuf
, sizeof(outbuf
), &outlen
);
3459 if (outlen
< MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN
)
3462 n_parts_total
= MCDI_DWORD(outbuf
, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS
);
3464 MCDI_VAR_ARRAY_LEN(outlen
, NVRAM_PARTITIONS_OUT_TYPE_ID
))
3467 parts
= kcalloc(n_parts_total
, sizeof(*parts
), GFP_KERNEL
);
3472 for (i
= 0; i
< n_parts_total
; i
++) {
3473 type
= MCDI_ARRAY_DWORD(outbuf
, NVRAM_PARTITIONS_OUT_TYPE_ID
,
3475 rc
= efx_ef10_mtd_probe_partition(efx
, &parts
[n_parts
], type
);
3478 else if (rc
!= -ENODEV
)
3482 rc
= efx_mtd_add(efx
, &parts
[0].common
, n_parts
, sizeof(*parts
));
3489 #endif /* CONFIG_SFC_MTD */
3491 static void efx_ef10_ptp_write_host_time(struct efx_nic
*efx
, u32 host_time
)
3493 _efx_writed(efx
, cpu_to_le32(host_time
), ER_DZ_MC_DB_LWRD
);
3496 static int efx_ef10_rx_enable_timestamping(struct efx_channel
*channel
,
3499 MCDI_DECLARE_BUF(inbuf
, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN
);
3502 if (channel
->sync_events_state
== SYNC_EVENTS_REQUESTED
||
3503 channel
->sync_events_state
== SYNC_EVENTS_VALID
||
3504 (temp
&& channel
->sync_events_state
== SYNC_EVENTS_DISABLED
))
3506 channel
->sync_events_state
= SYNC_EVENTS_REQUESTED
;
3508 MCDI_SET_DWORD(inbuf
, PTP_IN_OP
, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE
);
3509 MCDI_SET_DWORD(inbuf
, PTP_IN_PERIPH_ID
, 0);
3510 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE
,
3513 rc
= efx_mcdi_rpc(channel
->efx
, MC_CMD_PTP
,
3514 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
3517 channel
->sync_events_state
= temp
? SYNC_EVENTS_QUIESCENT
:
3518 SYNC_EVENTS_DISABLED
;
3523 static int efx_ef10_rx_disable_timestamping(struct efx_channel
*channel
,
3526 MCDI_DECLARE_BUF(inbuf
, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN
);
3529 if (channel
->sync_events_state
== SYNC_EVENTS_DISABLED
||
3530 (temp
&& channel
->sync_events_state
== SYNC_EVENTS_QUIESCENT
))
3532 if (channel
->sync_events_state
== SYNC_EVENTS_QUIESCENT
) {
3533 channel
->sync_events_state
= SYNC_EVENTS_DISABLED
;
3536 channel
->sync_events_state
= temp
? SYNC_EVENTS_QUIESCENT
:
3537 SYNC_EVENTS_DISABLED
;
3539 MCDI_SET_DWORD(inbuf
, PTP_IN_OP
, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE
);
3540 MCDI_SET_DWORD(inbuf
, PTP_IN_PERIPH_ID
, 0);
3541 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL
,
3542 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE
);
3543 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE
,
3546 rc
= efx_mcdi_rpc(channel
->efx
, MC_CMD_PTP
,
3547 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
3552 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic
*efx
, bool en
,
3555 int (*set
)(struct efx_channel
*channel
, bool temp
);
3556 struct efx_channel
*channel
;
3559 efx_ef10_rx_enable_timestamping
:
3560 efx_ef10_rx_disable_timestamping
;
3562 efx_for_each_channel(channel
, efx
) {
3563 int rc
= set(channel
, temp
);
3564 if (en
&& rc
!= 0) {
3565 efx_ef10_ptp_set_ts_sync_events(efx
, false, temp
);
3573 static int efx_ef10_ptp_set_ts_config(struct efx_nic
*efx
,
3574 struct hwtstamp_config
*init
)
3578 switch (init
->rx_filter
) {
3579 case HWTSTAMP_FILTER_NONE
:
3580 efx_ef10_ptp_set_ts_sync_events(efx
, false, false);
3581 /* if TX timestamping is still requested then leave PTP on */
3582 return efx_ptp_change_mode(efx
,
3583 init
->tx_type
!= HWTSTAMP_TX_OFF
, 0);
3584 case HWTSTAMP_FILTER_ALL
:
3585 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
3586 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
3587 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
3588 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
3589 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
3590 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
3591 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
3592 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
3593 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
3594 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
3595 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
3596 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
3597 init
->rx_filter
= HWTSTAMP_FILTER_ALL
;
3598 rc
= efx_ptp_change_mode(efx
, true, 0);
3600 rc
= efx_ef10_ptp_set_ts_sync_events(efx
, true, false);
3602 efx_ptp_change_mode(efx
, false, 0);
3609 const struct efx_nic_type efx_hunt_a0_nic_type
= {
3610 .mem_map_size
= efx_ef10_mem_map_size
,
3611 .probe
= efx_ef10_probe
,
3612 .remove
= efx_ef10_remove
,
3613 .dimension_resources
= efx_ef10_dimension_resources
,
3614 .init
= efx_ef10_init_nic
,
3615 .fini
= efx_port_dummy_op_void
,
3616 .map_reset_reason
= efx_mcdi_map_reset_reason
,
3617 .map_reset_flags
= efx_ef10_map_reset_flags
,
3618 .reset
= efx_ef10_reset
,
3619 .probe_port
= efx_mcdi_port_probe
,
3620 .remove_port
= efx_mcdi_port_remove
,
3621 .fini_dmaq
= efx_ef10_fini_dmaq
,
3622 .prepare_flr
= efx_ef10_prepare_flr
,
3623 .finish_flr
= efx_port_dummy_op_void
,
3624 .describe_stats
= efx_ef10_describe_stats
,
3625 .update_stats
= efx_ef10_update_stats
,
3626 .start_stats
= efx_mcdi_mac_start_stats
,
3627 .pull_stats
= efx_mcdi_mac_pull_stats
,
3628 .stop_stats
= efx_mcdi_mac_stop_stats
,
3629 .set_id_led
= efx_mcdi_set_id_led
,
3630 .push_irq_moderation
= efx_ef10_push_irq_moderation
,
3631 .reconfigure_mac
= efx_ef10_mac_reconfigure
,
3632 .check_mac_fault
= efx_mcdi_mac_check_fault
,
3633 .reconfigure_port
= efx_mcdi_port_reconfigure
,
3634 .get_wol
= efx_ef10_get_wol
,
3635 .set_wol
= efx_ef10_set_wol
,
3636 .resume_wol
= efx_port_dummy_op_void
,
3637 .test_chip
= efx_ef10_test_chip
,
3638 .test_nvram
= efx_mcdi_nvram_test_all
,
3639 .mcdi_request
= efx_ef10_mcdi_request
,
3640 .mcdi_poll_response
= efx_ef10_mcdi_poll_response
,
3641 .mcdi_read_response
= efx_ef10_mcdi_read_response
,
3642 .mcdi_poll_reboot
= efx_ef10_mcdi_poll_reboot
,
3643 .irq_enable_master
= efx_port_dummy_op_void
,
3644 .irq_test_generate
= efx_ef10_irq_test_generate
,
3645 .irq_disable_non_ev
= efx_port_dummy_op_void
,
3646 .irq_handle_msi
= efx_ef10_msi_interrupt
,
3647 .irq_handle_legacy
= efx_ef10_legacy_interrupt
,
3648 .tx_probe
= efx_ef10_tx_probe
,
3649 .tx_init
= efx_ef10_tx_init
,
3650 .tx_remove
= efx_ef10_tx_remove
,
3651 .tx_write
= efx_ef10_tx_write
,
3652 .rx_push_rss_config
= efx_ef10_rx_push_rss_config
,
3653 .rx_probe
= efx_ef10_rx_probe
,
3654 .rx_init
= efx_ef10_rx_init
,
3655 .rx_remove
= efx_ef10_rx_remove
,
3656 .rx_write
= efx_ef10_rx_write
,
3657 .rx_defer_refill
= efx_ef10_rx_defer_refill
,
3658 .ev_probe
= efx_ef10_ev_probe
,
3659 .ev_init
= efx_ef10_ev_init
,
3660 .ev_fini
= efx_ef10_ev_fini
,
3661 .ev_remove
= efx_ef10_ev_remove
,
3662 .ev_process
= efx_ef10_ev_process
,
3663 .ev_read_ack
= efx_ef10_ev_read_ack
,
3664 .ev_test_generate
= efx_ef10_ev_test_generate
,
3665 .filter_table_probe
= efx_ef10_filter_table_probe
,
3666 .filter_table_restore
= efx_ef10_filter_table_restore
,
3667 .filter_table_remove
= efx_ef10_filter_table_remove
,
3668 .filter_update_rx_scatter
= efx_ef10_filter_update_rx_scatter
,
3669 .filter_insert
= efx_ef10_filter_insert
,
3670 .filter_remove_safe
= efx_ef10_filter_remove_safe
,
3671 .filter_get_safe
= efx_ef10_filter_get_safe
,
3672 .filter_clear_rx
= efx_ef10_filter_clear_rx
,
3673 .filter_count_rx_used
= efx_ef10_filter_count_rx_used
,
3674 .filter_get_rx_id_limit
= efx_ef10_filter_get_rx_id_limit
,
3675 .filter_get_rx_ids
= efx_ef10_filter_get_rx_ids
,
3676 #ifdef CONFIG_RFS_ACCEL
3677 .filter_rfs_insert
= efx_ef10_filter_rfs_insert
,
3678 .filter_rfs_expire_one
= efx_ef10_filter_rfs_expire_one
,
3680 #ifdef CONFIG_SFC_MTD
3681 .mtd_probe
= efx_ef10_mtd_probe
,
3682 .mtd_rename
= efx_mcdi_mtd_rename
,
3683 .mtd_read
= efx_mcdi_mtd_read
,
3684 .mtd_erase
= efx_mcdi_mtd_erase
,
3685 .mtd_write
= efx_mcdi_mtd_write
,
3686 .mtd_sync
= efx_mcdi_mtd_sync
,
3688 .ptp_write_host_time
= efx_ef10_ptp_write_host_time
,
3689 .ptp_set_ts_sync_events
= efx_ef10_ptp_set_ts_sync_events
,
3690 .ptp_set_ts_config
= efx_ef10_ptp_set_ts_config
,
3692 .revision
= EFX_REV_HUNT_A0
,
3693 .max_dma_mask
= DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH
),
3694 .rx_prefix_size
= ES_DZ_RX_PREFIX_SIZE
,
3695 .rx_hash_offset
= ES_DZ_RX_PREFIX_HASH_OFST
,
3696 .rx_ts_offset
= ES_DZ_RX_PREFIX_TSTAMP_OFST
,
3697 .can_rx_scatter
= true,
3698 .always_rx_scatter
= true,
3699 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
3700 .timer_period_max
= 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH
,
3701 .offload_features
= (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3702 NETIF_F_RXHASH
| NETIF_F_NTUPLE
),
3704 .max_rx_ip_filters
= HUNT_FILTER_TBL_ROWS
,
3705 .hwtstamp_filters
= 1 << HWTSTAMP_FILTER_NONE
|
3706 1 << HWTSTAMP_FILTER_ALL
,