1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include "net_driver.h"
11 #include "ef10_regs.h"
14 #include "mcdi_pcol.h"
16 #include "workarounds.h"
18 #include "ef10_sriov.h"
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
24 /* Hardware control for EF10 architecture including 'Huntington'. */
26 #define EFX_EF10_DRVGEN_EV 7
32 /* The reserved RSS context value */
33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The maximum size of a shared RSS context */
35 /* TODO: this should really be from the mcdi protocol export */
36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
38 /* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
50 #define HUNT_FILTER_TBL_ROWS 8192
52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
53 struct efx_ef10_dev_addr
{
58 struct efx_ef10_filter_table
{
59 /* The RX match field masks supported by this fw & hw, in order of priority */
60 enum efx_filter_match_flags rx_match_flags
[
61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM
];
62 unsigned int rx_match_count
;
65 unsigned long spec
; /* pointer to spec plus flag bits */
66 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
67 * used to mark and sweep MAC filters for the device address lists.
69 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
70 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
71 #define EFX_EF10_FILTER_FLAGS 3UL
72 u64 handle
; /* firmware handle */
74 wait_queue_head_t waitq
;
75 /* Shadow of net_device address lists, guarded by mac_lock */
76 #define EFX_EF10_FILTER_DEV_UC_MAX 32
77 #define EFX_EF10_FILTER_DEV_MC_MAX 256
78 struct efx_ef10_dev_addr dev_uc_list
[EFX_EF10_FILTER_DEV_UC_MAX
];
79 struct efx_ef10_dev_addr dev_mc_list
[EFX_EF10_FILTER_DEV_MC_MAX
];
82 /* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */
88 /* An arbitrary search limit for the software hash table */
89 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
91 static void efx_ef10_rx_free_indir_table(struct efx_nic
*efx
);
92 static void efx_ef10_filter_table_remove(struct efx_nic
*efx
);
94 static int efx_ef10_get_warm_boot_count(struct efx_nic
*efx
)
98 efx_readd(efx
, ®
, ER_DZ_BIU_MC_SFT_STATUS
);
99 return EFX_DWORD_FIELD(reg
, EFX_WORD_1
) == 0xb007 ?
100 EFX_DWORD_FIELD(reg
, EFX_WORD_0
) : -EIO
;
103 static unsigned int efx_ef10_mem_map_size(struct efx_nic
*efx
)
107 bar
= efx
->type
->mem_bar
;
108 return resource_size(&efx
->pci_dev
->resource
[bar
]);
111 static bool efx_ef10_is_vf(struct efx_nic
*efx
)
113 return efx
->type
->is_vf
;
116 static int efx_ef10_get_pf_index(struct efx_nic
*efx
)
118 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_FUNCTION_INFO_OUT_LEN
);
119 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
123 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_FUNCTION_INFO
, NULL
, 0, outbuf
,
124 sizeof(outbuf
), &outlen
);
127 if (outlen
< sizeof(outbuf
))
130 nic_data
->pf_index
= MCDI_DWORD(outbuf
, GET_FUNCTION_INFO_OUT_PF
);
134 #ifdef CONFIG_SFC_SRIOV
135 static int efx_ef10_get_vf_index(struct efx_nic
*efx
)
137 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_FUNCTION_INFO_OUT_LEN
);
138 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
142 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_FUNCTION_INFO
, NULL
, 0, outbuf
,
143 sizeof(outbuf
), &outlen
);
146 if (outlen
< sizeof(outbuf
))
149 nic_data
->vf_index
= MCDI_DWORD(outbuf
, GET_FUNCTION_INFO_OUT_VF
);
154 static int efx_ef10_init_datapath_caps(struct efx_nic
*efx
)
156 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_CAPABILITIES_OUT_LEN
);
157 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN
!= 0);
163 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_CAPABILITIES
, NULL
, 0,
164 outbuf
, sizeof(outbuf
), &outlen
);
167 if (outlen
< sizeof(outbuf
)) {
168 netif_err(efx
, drv
, efx
->net_dev
,
169 "unable to read datapath firmware capabilities\n");
173 nic_data
->datapath_caps
=
174 MCDI_DWORD(outbuf
, GET_CAPABILITIES_OUT_FLAGS1
);
176 /* record the DPCPU firmware IDs to determine VEB vswitching support.
178 nic_data
->rx_dpcpu_fw_id
=
179 MCDI_WORD(outbuf
, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID
);
180 nic_data
->tx_dpcpu_fw_id
=
181 MCDI_WORD(outbuf
, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID
);
183 if (!(nic_data
->datapath_caps
&
184 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN
))) {
185 netif_err(efx
, drv
, efx
->net_dev
,
186 "current firmware does not support TSO\n");
190 if (!(nic_data
->datapath_caps
&
191 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN
))) {
192 netif_err(efx
, probe
, efx
->net_dev
,
193 "current firmware does not support an RX prefix\n");
200 static int efx_ef10_get_sysclk_freq(struct efx_nic
*efx
)
202 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_CLOCK_OUT_LEN
);
205 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_CLOCK
, NULL
, 0,
206 outbuf
, sizeof(outbuf
), NULL
);
209 rc
= MCDI_DWORD(outbuf
, GET_CLOCK_OUT_SYS_FREQ
);
210 return rc
> 0 ? rc
: -ERANGE
;
213 static int efx_ef10_get_mac_address_pf(struct efx_nic
*efx
, u8
*mac_address
)
215 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN
);
219 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN
!= 0);
221 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_MAC_ADDRESSES
, NULL
, 0,
222 outbuf
, sizeof(outbuf
), &outlen
);
225 if (outlen
< MC_CMD_GET_MAC_ADDRESSES_OUT_LEN
)
228 ether_addr_copy(mac_address
,
229 MCDI_PTR(outbuf
, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE
));
233 static int efx_ef10_get_mac_address_vf(struct efx_nic
*efx
, u8
*mac_address
)
235 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN
);
236 MCDI_DECLARE_BUF(outbuf
, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX
);
240 MCDI_SET_DWORD(inbuf
, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID
,
241 EVB_PORT_ID_ASSIGNED
);
242 rc
= efx_mcdi_rpc(efx
, MC_CMD_VPORT_GET_MAC_ADDRESSES
, inbuf
,
243 sizeof(inbuf
), outbuf
, sizeof(outbuf
), &outlen
);
247 if (outlen
< MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN
)
250 num_addrs
= MCDI_DWORD(outbuf
,
251 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT
);
253 WARN_ON(num_addrs
!= 1);
255 ether_addr_copy(mac_address
,
256 MCDI_PTR(outbuf
, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR
));
261 static ssize_t
efx_ef10_show_link_control_flag(struct device
*dev
,
262 struct device_attribute
*attr
,
265 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
267 return sprintf(buf
, "%d\n",
268 ((efx
->mcdi
->fn_flags
) &
269 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL
))
273 static ssize_t
efx_ef10_show_primary_flag(struct device
*dev
,
274 struct device_attribute
*attr
,
277 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
279 return sprintf(buf
, "%d\n",
280 ((efx
->mcdi
->fn_flags
) &
281 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY
))
285 static DEVICE_ATTR(link_control_flag
, 0444, efx_ef10_show_link_control_flag
,
287 static DEVICE_ATTR(primary_flag
, 0444, efx_ef10_show_primary_flag
, NULL
);
289 static int efx_ef10_probe(struct efx_nic
*efx
)
291 struct efx_ef10_nic_data
*nic_data
;
292 struct net_device
*net_dev
= efx
->net_dev
;
295 /* We can have one VI for each 8K region. However, until we
296 * use TX option descriptors we need two TX queues per channel.
301 efx_ef10_mem_map_size(efx
) /
302 (EFX_VI_PAGE_SIZE
* EFX_TXQ_TYPES
));
303 if (WARN_ON(efx
->max_channels
== 0))
306 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
309 efx
->nic_data
= nic_data
;
311 /* we assume later that we can copy from this buffer in dwords */
312 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2
% 4);
314 rc
= efx_nic_alloc_buffer(efx
, &nic_data
->mcdi_buf
,
315 8 + MCDI_CTL_SDU_LEN_MAX_V2
, GFP_KERNEL
);
319 /* Get the MC's warm boot count. In case it's rebooting right
320 * now, be prepared to retry.
324 rc
= efx_ef10_get_warm_boot_count(efx
);
331 nic_data
->warm_boot_count
= rc
;
333 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
335 nic_data
->vport_id
= EVB_PORT_ID_ASSIGNED
;
337 /* In case we're recovering from a crash (kexec), we want to
338 * cancel any outstanding request by the previous user of this
339 * function. We send a special message using the least
340 * significant bits of the 'high' (doorbell) register.
342 _efx_writed(efx
, cpu_to_le32(1), ER_DZ_MC_DB_HWRD
);
344 rc
= efx_mcdi_init(efx
);
348 /* Reset (most) configuration for this function */
349 rc
= efx_mcdi_reset(efx
, RESET_TYPE_ALL
);
353 /* Enable event logging */
354 rc
= efx_mcdi_log_ctrl(efx
, true, false, 0);
358 rc
= device_create_file(&efx
->pci_dev
->dev
,
359 &dev_attr_link_control_flag
);
363 rc
= device_create_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
367 rc
= efx_ef10_get_pf_index(efx
);
371 rc
= efx_ef10_init_datapath_caps(efx
);
375 efx
->rx_packet_len_offset
=
376 ES_DZ_RX_PREFIX_PKTLEN_OFST
- ES_DZ_RX_PREFIX_SIZE
;
378 rc
= efx_mcdi_port_get_number(efx
);
382 net_dev
->dev_port
= rc
;
384 rc
= efx
->type
->get_mac_address(efx
, efx
->net_dev
->perm_addr
);
388 rc
= efx_ef10_get_sysclk_freq(efx
);
391 efx
->timer_quantum_ns
= 1536000 / rc
; /* 1536 cycles */
393 /* Check whether firmware supports bug 35388 workaround.
394 * First try to enable it, then if we get EPERM, just
395 * ask if it's already enabled
397 rc
= efx_mcdi_set_workaround(efx
, MC_CMD_WORKAROUND_BUG35388
, true, NULL
);
399 nic_data
->workaround_35388
= true;
400 } else if (rc
== -EPERM
) {
401 unsigned int enabled
;
403 rc
= efx_mcdi_get_workarounds(efx
, NULL
, &enabled
);
406 nic_data
->workaround_35388
= enabled
&
407 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388
;
408 } else if (rc
!= -ENOSYS
&& rc
!= -ENOENT
) {
411 netif_dbg(efx
, probe
, efx
->net_dev
,
412 "workaround for bug 35388 is %sabled\n",
413 nic_data
->workaround_35388
? "en" : "dis");
415 rc
= efx_mcdi_mon_probe(efx
);
416 if (rc
&& rc
!= -EPERM
)
419 efx_ptp_probe(efx
, NULL
);
421 #ifdef CONFIG_SFC_SRIOV
422 if ((efx
->pci_dev
->physfn
) && (!efx
->pci_dev
->is_physfn
)) {
423 struct pci_dev
*pci_dev_pf
= efx
->pci_dev
->physfn
;
424 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
426 efx_pf
->type
->get_mac_address(efx_pf
, nic_data
->port_id
);
429 ether_addr_copy(nic_data
->port_id
, efx
->net_dev
->perm_addr
);
434 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
436 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_link_control_flag
);
440 efx_nic_free_buffer(efx
, &nic_data
->mcdi_buf
);
443 efx
->nic_data
= NULL
;
447 static int efx_ef10_free_vis(struct efx_nic
*efx
)
449 MCDI_DECLARE_BUF_ERR(outbuf
);
451 int rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FREE_VIS
, NULL
, 0,
452 outbuf
, sizeof(outbuf
), &outlen
);
454 /* -EALREADY means nothing to free, so ignore */
458 efx_mcdi_display_error(efx
, MC_CMD_FREE_VIS
, 0, outbuf
, outlen
,
465 static void efx_ef10_free_piobufs(struct efx_nic
*efx
)
467 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
468 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FREE_PIOBUF_IN_LEN
);
472 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN
!= 0);
474 for (i
= 0; i
< nic_data
->n_piobufs
; i
++) {
475 MCDI_SET_DWORD(inbuf
, FREE_PIOBUF_IN_PIOBUF_HANDLE
,
476 nic_data
->piobuf_handle
[i
]);
477 rc
= efx_mcdi_rpc(efx
, MC_CMD_FREE_PIOBUF
, inbuf
, sizeof(inbuf
),
482 nic_data
->n_piobufs
= 0;
485 static int efx_ef10_alloc_piobufs(struct efx_nic
*efx
, unsigned int n
)
487 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
488 MCDI_DECLARE_BUF(outbuf
, MC_CMD_ALLOC_PIOBUF_OUT_LEN
);
493 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN
!= 0);
495 for (i
= 0; i
< n
; i
++) {
496 rc
= efx_mcdi_rpc(efx
, MC_CMD_ALLOC_PIOBUF
, NULL
, 0,
497 outbuf
, sizeof(outbuf
), &outlen
);
500 if (outlen
< MC_CMD_ALLOC_PIOBUF_OUT_LEN
) {
504 nic_data
->piobuf_handle
[i
] =
505 MCDI_DWORD(outbuf
, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE
);
506 netif_dbg(efx
, probe
, efx
->net_dev
,
507 "allocated PIO buffer %u handle %x\n", i
,
508 nic_data
->piobuf_handle
[i
]);
511 nic_data
->n_piobufs
= i
;
513 efx_ef10_free_piobufs(efx
);
517 static int efx_ef10_link_piobufs(struct efx_nic
*efx
)
519 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
520 _MCDI_DECLARE_BUF(inbuf
,
521 max(MC_CMD_LINK_PIOBUF_IN_LEN
,
522 MC_CMD_UNLINK_PIOBUF_IN_LEN
));
523 struct efx_channel
*channel
;
524 struct efx_tx_queue
*tx_queue
;
525 unsigned int offset
, index
;
528 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN
!= 0);
529 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN
!= 0);
531 memset(inbuf
, 0, sizeof(inbuf
));
533 /* Link a buffer to each VI in the write-combining mapping */
534 for (index
= 0; index
< nic_data
->n_piobufs
; ++index
) {
535 MCDI_SET_DWORD(inbuf
, LINK_PIOBUF_IN_PIOBUF_HANDLE
,
536 nic_data
->piobuf_handle
[index
]);
537 MCDI_SET_DWORD(inbuf
, LINK_PIOBUF_IN_TXQ_INSTANCE
,
538 nic_data
->pio_write_vi_base
+ index
);
539 rc
= efx_mcdi_rpc(efx
, MC_CMD_LINK_PIOBUF
,
540 inbuf
, MC_CMD_LINK_PIOBUF_IN_LEN
,
543 netif_err(efx
, drv
, efx
->net_dev
,
544 "failed to link VI %u to PIO buffer %u (%d)\n",
545 nic_data
->pio_write_vi_base
+ index
, index
,
549 netif_dbg(efx
, probe
, efx
->net_dev
,
550 "linked VI %u to PIO buffer %u\n",
551 nic_data
->pio_write_vi_base
+ index
, index
);
554 /* Link a buffer to each TX queue */
555 efx_for_each_channel(channel
, efx
) {
556 efx_for_each_channel_tx_queue(tx_queue
, channel
) {
557 /* We assign the PIO buffers to queues in
558 * reverse order to allow for the following
561 offset
= ((efx
->tx_channel_offset
+ efx
->n_tx_channels
-
562 tx_queue
->channel
->channel
- 1) *
564 index
= offset
/ ER_DZ_TX_PIOBUF_SIZE
;
565 offset
= offset
% ER_DZ_TX_PIOBUF_SIZE
;
567 /* When the host page size is 4K, the first
568 * host page in the WC mapping may be within
569 * the same VI page as the last TX queue. We
570 * can only link one buffer to each VI.
572 if (tx_queue
->queue
== nic_data
->pio_write_vi_base
) {
576 MCDI_SET_DWORD(inbuf
,
577 LINK_PIOBUF_IN_PIOBUF_HANDLE
,
578 nic_data
->piobuf_handle
[index
]);
579 MCDI_SET_DWORD(inbuf
,
580 LINK_PIOBUF_IN_TXQ_INSTANCE
,
582 rc
= efx_mcdi_rpc(efx
, MC_CMD_LINK_PIOBUF
,
583 inbuf
, MC_CMD_LINK_PIOBUF_IN_LEN
,
588 /* This is non-fatal; the TX path just
589 * won't use PIO for this queue
591 netif_err(efx
, drv
, efx
->net_dev
,
592 "failed to link VI %u to PIO buffer %u (%d)\n",
593 tx_queue
->queue
, index
, rc
);
594 tx_queue
->piobuf
= NULL
;
597 nic_data
->pio_write_base
+
598 index
* EFX_VI_PAGE_SIZE
+ offset
;
599 tx_queue
->piobuf_offset
= offset
;
600 netif_dbg(efx
, probe
, efx
->net_dev
,
601 "linked VI %u to PIO buffer %u offset %x addr %p\n",
602 tx_queue
->queue
, index
,
603 tx_queue
->piobuf_offset
,
613 MCDI_SET_DWORD(inbuf
, UNLINK_PIOBUF_IN_TXQ_INSTANCE
,
614 nic_data
->pio_write_vi_base
+ index
);
615 efx_mcdi_rpc(efx
, MC_CMD_UNLINK_PIOBUF
,
616 inbuf
, MC_CMD_UNLINK_PIOBUF_IN_LEN
,
622 #else /* !EFX_USE_PIO */
624 static int efx_ef10_alloc_piobufs(struct efx_nic
*efx
, unsigned int n
)
626 return n
== 0 ? 0 : -ENOBUFS
;
629 static int efx_ef10_link_piobufs(struct efx_nic
*efx
)
634 static void efx_ef10_free_piobufs(struct efx_nic
*efx
)
638 #endif /* EFX_USE_PIO */
640 static void efx_ef10_remove(struct efx_nic
*efx
)
642 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
645 #ifdef CONFIG_SFC_SRIOV
646 struct efx_ef10_nic_data
*nic_data_pf
;
647 struct pci_dev
*pci_dev_pf
;
648 struct efx_nic
*efx_pf
;
651 if (efx
->pci_dev
->is_virtfn
) {
652 pci_dev_pf
= efx
->pci_dev
->physfn
;
654 efx_pf
= pci_get_drvdata(pci_dev_pf
);
655 nic_data_pf
= efx_pf
->nic_data
;
656 vf
= nic_data_pf
->vf
+ nic_data
->vf_index
;
659 netif_info(efx
, drv
, efx
->net_dev
,
660 "Could not get the PF id from VF\n");
666 efx_mcdi_mon_remove(efx
);
668 efx_ef10_rx_free_indir_table(efx
);
670 if (nic_data
->wc_membase
)
671 iounmap(nic_data
->wc_membase
);
673 rc
= efx_ef10_free_vis(efx
);
676 if (!nic_data
->must_restore_piobufs
)
677 efx_ef10_free_piobufs(efx
);
679 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
680 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_link_control_flag
);
683 efx_nic_free_buffer(efx
, &nic_data
->mcdi_buf
);
687 static int efx_ef10_probe_pf(struct efx_nic
*efx
)
689 return efx_ef10_probe(efx
);
692 int efx_ef10_vadaptor_alloc(struct efx_nic
*efx
, unsigned int port_id
)
694 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_ALLOC_IN_LEN
);
696 MCDI_SET_DWORD(inbuf
, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID
, port_id
);
697 return efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_ALLOC
, inbuf
, sizeof(inbuf
),
701 int efx_ef10_vadaptor_free(struct efx_nic
*efx
, unsigned int port_id
)
703 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_FREE_IN_LEN
);
705 MCDI_SET_DWORD(inbuf
, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID
, port_id
);
706 return efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_FREE
, inbuf
, sizeof(inbuf
),
710 int efx_ef10_vport_add_mac(struct efx_nic
*efx
,
711 unsigned int port_id
, u8
*mac
)
713 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN
);
715 MCDI_SET_DWORD(inbuf
, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID
, port_id
);
716 ether_addr_copy(MCDI_PTR(inbuf
, VPORT_ADD_MAC_ADDRESS_IN_MACADDR
), mac
);
718 return efx_mcdi_rpc(efx
, MC_CMD_VPORT_ADD_MAC_ADDRESS
, inbuf
,
719 sizeof(inbuf
), NULL
, 0, NULL
);
722 int efx_ef10_vport_del_mac(struct efx_nic
*efx
,
723 unsigned int port_id
, u8
*mac
)
725 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN
);
727 MCDI_SET_DWORD(inbuf
, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID
, port_id
);
728 ether_addr_copy(MCDI_PTR(inbuf
, VPORT_DEL_MAC_ADDRESS_IN_MACADDR
), mac
);
730 return efx_mcdi_rpc(efx
, MC_CMD_VPORT_DEL_MAC_ADDRESS
, inbuf
,
731 sizeof(inbuf
), NULL
, 0, NULL
);
734 #ifdef CONFIG_SFC_SRIOV
735 static int efx_ef10_probe_vf(struct efx_nic
*efx
)
738 struct pci_dev
*pci_dev_pf
;
740 /* If the parent PF has no VF data structure, it doesn't know about this
741 * VF so fail probe. The VF needs to be re-created. This can happen
742 * if the PF driver is unloaded while the VF is assigned to a guest.
744 pci_dev_pf
= efx
->pci_dev
->physfn
;
746 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
747 struct efx_ef10_nic_data
*nic_data_pf
= efx_pf
->nic_data
;
749 if (!nic_data_pf
->vf
) {
750 netif_info(efx
, drv
, efx
->net_dev
,
751 "The VF cannot link to its parent PF; "
752 "please destroy and re-create the VF\n");
757 rc
= efx_ef10_probe(efx
);
761 rc
= efx_ef10_get_vf_index(efx
);
765 if (efx
->pci_dev
->is_virtfn
) {
766 if (efx
->pci_dev
->physfn
) {
767 struct efx_nic
*efx_pf
=
768 pci_get_drvdata(efx
->pci_dev
->physfn
);
769 struct efx_ef10_nic_data
*nic_data_p
= efx_pf
->nic_data
;
770 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
772 nic_data_p
->vf
[nic_data
->vf_index
].efx
= efx
;
773 nic_data_p
->vf
[nic_data
->vf_index
].pci_dev
=
776 netif_info(efx
, drv
, efx
->net_dev
,
777 "Could not get the PF id from VF\n");
783 efx_ef10_remove(efx
);
787 static int efx_ef10_probe_vf(struct efx_nic
*efx
__attribute__ ((unused
)))
793 static int efx_ef10_alloc_vis(struct efx_nic
*efx
,
794 unsigned int min_vis
, unsigned int max_vis
)
796 MCDI_DECLARE_BUF(inbuf
, MC_CMD_ALLOC_VIS_IN_LEN
);
797 MCDI_DECLARE_BUF(outbuf
, MC_CMD_ALLOC_VIS_OUT_LEN
);
798 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
802 MCDI_SET_DWORD(inbuf
, ALLOC_VIS_IN_MIN_VI_COUNT
, min_vis
);
803 MCDI_SET_DWORD(inbuf
, ALLOC_VIS_IN_MAX_VI_COUNT
, max_vis
);
804 rc
= efx_mcdi_rpc(efx
, MC_CMD_ALLOC_VIS
, inbuf
, sizeof(inbuf
),
805 outbuf
, sizeof(outbuf
), &outlen
);
809 if (outlen
< MC_CMD_ALLOC_VIS_OUT_LEN
)
812 netif_dbg(efx
, drv
, efx
->net_dev
, "base VI is A0x%03x\n",
813 MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_BASE
));
815 nic_data
->vi_base
= MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_BASE
);
816 nic_data
->n_allocated_vis
= MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_COUNT
);
820 /* Note that the failure path of this function does not free
821 * resources, as this will be done by efx_ef10_remove().
823 static int efx_ef10_dimension_resources(struct efx_nic
*efx
)
825 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
826 unsigned int uc_mem_map_size
, wc_mem_map_size
;
827 unsigned int min_vis
, pio_write_vi_base
, max_vis
;
828 void __iomem
*membase
;
831 min_vis
= max(efx
->n_channels
, efx
->n_tx_channels
* EFX_TXQ_TYPES
);
834 /* Try to allocate PIO buffers if wanted and if the full
835 * number of PIO buffers would be sufficient to allocate one
836 * copy-buffer per TX channel. Failure is non-fatal, as there
837 * are only a small number of PIO buffers shared between all
838 * functions of the controller.
840 if (efx_piobuf_size
!= 0 &&
841 ER_DZ_TX_PIOBUF_SIZE
/ efx_piobuf_size
* EF10_TX_PIOBUF_COUNT
>=
842 efx
->n_tx_channels
) {
843 unsigned int n_piobufs
=
844 DIV_ROUND_UP(efx
->n_tx_channels
,
845 ER_DZ_TX_PIOBUF_SIZE
/ efx_piobuf_size
);
847 rc
= efx_ef10_alloc_piobufs(efx
, n_piobufs
);
849 netif_err(efx
, probe
, efx
->net_dev
,
850 "failed to allocate PIO buffers (%d)\n", rc
);
852 netif_dbg(efx
, probe
, efx
->net_dev
,
853 "allocated %u PIO buffers\n", n_piobufs
);
856 nic_data
->n_piobufs
= 0;
859 /* PIO buffers should be mapped with write-combining enabled,
860 * and we want to make single UC and WC mappings rather than
861 * several of each (in fact that's the only option if host
862 * page size is >4K). So we may allocate some extra VIs just
863 * for writing PIO buffers through.
865 * The UC mapping contains (min_vis - 1) complete VIs and the
866 * first half of the next VI. Then the WC mapping begins with
867 * the second half of this last VI.
869 uc_mem_map_size
= PAGE_ALIGN((min_vis
- 1) * EFX_VI_PAGE_SIZE
+
871 if (nic_data
->n_piobufs
) {
872 /* pio_write_vi_base rounds down to give the number of complete
873 * VIs inside the UC mapping.
875 pio_write_vi_base
= uc_mem_map_size
/ EFX_VI_PAGE_SIZE
;
876 wc_mem_map_size
= (PAGE_ALIGN((pio_write_vi_base
+
877 nic_data
->n_piobufs
) *
880 max_vis
= pio_write_vi_base
+ nic_data
->n_piobufs
;
882 pio_write_vi_base
= 0;
887 /* In case the last attached driver failed to free VIs, do it now */
888 rc
= efx_ef10_free_vis(efx
);
892 rc
= efx_ef10_alloc_vis(efx
, min_vis
, max_vis
);
896 /* If we didn't get enough VIs to map all the PIO buffers, free the
899 if (nic_data
->n_piobufs
&&
900 nic_data
->n_allocated_vis
<
901 pio_write_vi_base
+ nic_data
->n_piobufs
) {
902 netif_dbg(efx
, probe
, efx
->net_dev
,
903 "%u VIs are not sufficient to map %u PIO buffers\n",
904 nic_data
->n_allocated_vis
, nic_data
->n_piobufs
);
905 efx_ef10_free_piobufs(efx
);
908 /* Shrink the original UC mapping of the memory BAR */
909 membase
= ioremap_nocache(efx
->membase_phys
, uc_mem_map_size
);
911 netif_err(efx
, probe
, efx
->net_dev
,
912 "could not shrink memory BAR to %x\n",
916 iounmap(efx
->membase
);
917 efx
->membase
= membase
;
919 /* Set up the WC mapping if needed */
920 if (wc_mem_map_size
) {
921 nic_data
->wc_membase
= ioremap_wc(efx
->membase_phys
+
924 if (!nic_data
->wc_membase
) {
925 netif_err(efx
, probe
, efx
->net_dev
,
926 "could not allocate WC mapping of size %x\n",
930 nic_data
->pio_write_vi_base
= pio_write_vi_base
;
931 nic_data
->pio_write_base
=
932 nic_data
->wc_membase
+
933 (pio_write_vi_base
* EFX_VI_PAGE_SIZE
+ ER_DZ_TX_PIOBUF
-
936 rc
= efx_ef10_link_piobufs(efx
);
938 efx_ef10_free_piobufs(efx
);
941 netif_dbg(efx
, probe
, efx
->net_dev
,
942 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
943 &efx
->membase_phys
, efx
->membase
, uc_mem_map_size
,
944 nic_data
->wc_membase
, wc_mem_map_size
);
949 static int efx_ef10_init_nic(struct efx_nic
*efx
)
951 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
954 if (nic_data
->must_check_datapath_caps
) {
955 rc
= efx_ef10_init_datapath_caps(efx
);
958 nic_data
->must_check_datapath_caps
= false;
961 if (nic_data
->must_realloc_vis
) {
962 /* We cannot let the number of VIs change now */
963 rc
= efx_ef10_alloc_vis(efx
, nic_data
->n_allocated_vis
,
964 nic_data
->n_allocated_vis
);
967 nic_data
->must_realloc_vis
= false;
970 if (nic_data
->must_restore_piobufs
&& nic_data
->n_piobufs
) {
971 rc
= efx_ef10_alloc_piobufs(efx
, nic_data
->n_piobufs
);
973 rc
= efx_ef10_link_piobufs(efx
);
975 efx_ef10_free_piobufs(efx
);
978 /* Log an error on failure, but this is non-fatal */
980 netif_err(efx
, drv
, efx
->net_dev
,
981 "failed to restore PIO buffers (%d)\n", rc
);
982 nic_data
->must_restore_piobufs
= false;
985 /* don't fail init if RSS setup doesn't work */
986 efx
->type
->rx_push_rss_config(efx
, false, efx
->rx_indir_table
);
991 static void efx_ef10_reset_mc_allocations(struct efx_nic
*efx
)
993 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
995 /* All our allocations have been reset */
996 nic_data
->must_realloc_vis
= true;
997 nic_data
->must_restore_filters
= true;
998 nic_data
->must_restore_piobufs
= true;
999 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
1002 static enum reset_type
efx_ef10_map_reset_reason(enum reset_type reason
)
1004 if (reason
== RESET_TYPE_MC_FAILURE
)
1005 return RESET_TYPE_DATAPATH
;
1007 return efx_mcdi_map_reset_reason(reason
);
1010 static int efx_ef10_map_reset_flags(u32
*flags
)
1013 EF10_RESET_PORT
= ((ETH_RESET_MAC
| ETH_RESET_PHY
) <<
1014 ETH_RESET_SHARED_SHIFT
),
1015 EF10_RESET_MC
= ((ETH_RESET_DMA
| ETH_RESET_FILTER
|
1016 ETH_RESET_OFFLOAD
| ETH_RESET_MAC
|
1017 ETH_RESET_PHY
| ETH_RESET_MGMT
) <<
1018 ETH_RESET_SHARED_SHIFT
)
1021 /* We assume for now that our PCI function is permitted to
1025 if ((*flags
& EF10_RESET_MC
) == EF10_RESET_MC
) {
1026 *flags
&= ~EF10_RESET_MC
;
1027 return RESET_TYPE_WORLD
;
1030 if ((*flags
& EF10_RESET_PORT
) == EF10_RESET_PORT
) {
1031 *flags
&= ~EF10_RESET_PORT
;
1032 return RESET_TYPE_ALL
;
1035 /* no invisible reset implemented */
1040 static int efx_ef10_reset(struct efx_nic
*efx
, enum reset_type reset_type
)
1042 int rc
= efx_mcdi_reset(efx
, reset_type
);
1044 /* If it was a port reset, trigger reallocation of MC resources.
1045 * Note that on an MC reset nothing needs to be done now because we'll
1046 * detect the MC reset later and handle it then.
1047 * For an FLR, we never get an MC reset event, but the MC has reset all
1048 * resources assigned to us, so we have to trigger reallocation now.
1050 if ((reset_type
== RESET_TYPE_ALL
||
1051 reset_type
== RESET_TYPE_MCDI_TIMEOUT
) && !rc
)
1052 efx_ef10_reset_mc_allocations(efx
);
1056 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1057 [EF10_STAT_ ## ext_name] = \
1058 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1059 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1060 [EF10_STAT_ ## int_name] = \
1061 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1062 #define EF10_OTHER_STAT(ext_name) \
1063 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1064 #define GENERIC_SW_STAT(ext_name) \
1065 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1067 static const struct efx_hw_stat_desc efx_ef10_stat_desc
[EF10_STAT_COUNT
] = {
1068 EF10_DMA_STAT(port_tx_bytes
, TX_BYTES
),
1069 EF10_DMA_STAT(port_tx_packets
, TX_PKTS
),
1070 EF10_DMA_STAT(port_tx_pause
, TX_PAUSE_PKTS
),
1071 EF10_DMA_STAT(port_tx_control
, TX_CONTROL_PKTS
),
1072 EF10_DMA_STAT(port_tx_unicast
, TX_UNICAST_PKTS
),
1073 EF10_DMA_STAT(port_tx_multicast
, TX_MULTICAST_PKTS
),
1074 EF10_DMA_STAT(port_tx_broadcast
, TX_BROADCAST_PKTS
),
1075 EF10_DMA_STAT(port_tx_lt64
, TX_LT64_PKTS
),
1076 EF10_DMA_STAT(port_tx_64
, TX_64_PKTS
),
1077 EF10_DMA_STAT(port_tx_65_to_127
, TX_65_TO_127_PKTS
),
1078 EF10_DMA_STAT(port_tx_128_to_255
, TX_128_TO_255_PKTS
),
1079 EF10_DMA_STAT(port_tx_256_to_511
, TX_256_TO_511_PKTS
),
1080 EF10_DMA_STAT(port_tx_512_to_1023
, TX_512_TO_1023_PKTS
),
1081 EF10_DMA_STAT(port_tx_1024_to_15xx
, TX_1024_TO_15XX_PKTS
),
1082 EF10_DMA_STAT(port_tx_15xx_to_jumbo
, TX_15XX_TO_JUMBO_PKTS
),
1083 EF10_DMA_STAT(port_rx_bytes
, RX_BYTES
),
1084 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes
, RX_BAD_BYTES
),
1085 EF10_OTHER_STAT(port_rx_good_bytes
),
1086 EF10_OTHER_STAT(port_rx_bad_bytes
),
1087 EF10_DMA_STAT(port_rx_packets
, RX_PKTS
),
1088 EF10_DMA_STAT(port_rx_good
, RX_GOOD_PKTS
),
1089 EF10_DMA_STAT(port_rx_bad
, RX_BAD_FCS_PKTS
),
1090 EF10_DMA_STAT(port_rx_pause
, RX_PAUSE_PKTS
),
1091 EF10_DMA_STAT(port_rx_control
, RX_CONTROL_PKTS
),
1092 EF10_DMA_STAT(port_rx_unicast
, RX_UNICAST_PKTS
),
1093 EF10_DMA_STAT(port_rx_multicast
, RX_MULTICAST_PKTS
),
1094 EF10_DMA_STAT(port_rx_broadcast
, RX_BROADCAST_PKTS
),
1095 EF10_DMA_STAT(port_rx_lt64
, RX_UNDERSIZE_PKTS
),
1096 EF10_DMA_STAT(port_rx_64
, RX_64_PKTS
),
1097 EF10_DMA_STAT(port_rx_65_to_127
, RX_65_TO_127_PKTS
),
1098 EF10_DMA_STAT(port_rx_128_to_255
, RX_128_TO_255_PKTS
),
1099 EF10_DMA_STAT(port_rx_256_to_511
, RX_256_TO_511_PKTS
),
1100 EF10_DMA_STAT(port_rx_512_to_1023
, RX_512_TO_1023_PKTS
),
1101 EF10_DMA_STAT(port_rx_1024_to_15xx
, RX_1024_TO_15XX_PKTS
),
1102 EF10_DMA_STAT(port_rx_15xx_to_jumbo
, RX_15XX_TO_JUMBO_PKTS
),
1103 EF10_DMA_STAT(port_rx_gtjumbo
, RX_GTJUMBO_PKTS
),
1104 EF10_DMA_STAT(port_rx_bad_gtjumbo
, RX_JABBER_PKTS
),
1105 EF10_DMA_STAT(port_rx_overflow
, RX_OVERFLOW_PKTS
),
1106 EF10_DMA_STAT(port_rx_align_error
, RX_ALIGN_ERROR_PKTS
),
1107 EF10_DMA_STAT(port_rx_length_error
, RX_LENGTH_ERROR_PKTS
),
1108 EF10_DMA_STAT(port_rx_nodesc_drops
, RX_NODESC_DROPS
),
1109 GENERIC_SW_STAT(rx_nodesc_trunc
),
1110 GENERIC_SW_STAT(rx_noskb_drops
),
1111 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow
, PM_TRUNC_BB_OVERFLOW
),
1112 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow
, PM_DISCARD_BB_OVERFLOW
),
1113 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full
, PM_TRUNC_VFIFO_FULL
),
1114 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full
, PM_DISCARD_VFIFO_FULL
),
1115 EF10_DMA_STAT(port_rx_pm_trunc_qbb
, PM_TRUNC_QBB
),
1116 EF10_DMA_STAT(port_rx_pm_discard_qbb
, PM_DISCARD_QBB
),
1117 EF10_DMA_STAT(port_rx_pm_discard_mapping
, PM_DISCARD_MAPPING
),
1118 EF10_DMA_STAT(port_rx_dp_q_disabled_packets
, RXDP_Q_DISABLED_PKTS
),
1119 EF10_DMA_STAT(port_rx_dp_di_dropped_packets
, RXDP_DI_DROPPED_PKTS
),
1120 EF10_DMA_STAT(port_rx_dp_streaming_packets
, RXDP_STREAMING_PKTS
),
1121 EF10_DMA_STAT(port_rx_dp_hlb_fetch
, RXDP_HLB_FETCH_CONDITIONS
),
1122 EF10_DMA_STAT(port_rx_dp_hlb_wait
, RXDP_HLB_WAIT_CONDITIONS
),
1123 EF10_DMA_STAT(rx_unicast
, VADAPTER_RX_UNICAST_PACKETS
),
1124 EF10_DMA_STAT(rx_unicast_bytes
, VADAPTER_RX_UNICAST_BYTES
),
1125 EF10_DMA_STAT(rx_multicast
, VADAPTER_RX_MULTICAST_PACKETS
),
1126 EF10_DMA_STAT(rx_multicast_bytes
, VADAPTER_RX_MULTICAST_BYTES
),
1127 EF10_DMA_STAT(rx_broadcast
, VADAPTER_RX_BROADCAST_PACKETS
),
1128 EF10_DMA_STAT(rx_broadcast_bytes
, VADAPTER_RX_BROADCAST_BYTES
),
1129 EF10_DMA_STAT(rx_bad
, VADAPTER_RX_BAD_PACKETS
),
1130 EF10_DMA_STAT(rx_bad_bytes
, VADAPTER_RX_BAD_BYTES
),
1131 EF10_DMA_STAT(rx_overflow
, VADAPTER_RX_OVERFLOW
),
1132 EF10_DMA_STAT(tx_unicast
, VADAPTER_TX_UNICAST_PACKETS
),
1133 EF10_DMA_STAT(tx_unicast_bytes
, VADAPTER_TX_UNICAST_BYTES
),
1134 EF10_DMA_STAT(tx_multicast
, VADAPTER_TX_MULTICAST_PACKETS
),
1135 EF10_DMA_STAT(tx_multicast_bytes
, VADAPTER_TX_MULTICAST_BYTES
),
1136 EF10_DMA_STAT(tx_broadcast
, VADAPTER_TX_BROADCAST_PACKETS
),
1137 EF10_DMA_STAT(tx_broadcast_bytes
, VADAPTER_TX_BROADCAST_BYTES
),
1138 EF10_DMA_STAT(tx_bad
, VADAPTER_TX_BAD_PACKETS
),
1139 EF10_DMA_STAT(tx_bad_bytes
, VADAPTER_TX_BAD_BYTES
),
1140 EF10_DMA_STAT(tx_overflow
, VADAPTER_TX_OVERFLOW
),
1143 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1144 (1ULL << EF10_STAT_port_tx_packets) | \
1145 (1ULL << EF10_STAT_port_tx_pause) | \
1146 (1ULL << EF10_STAT_port_tx_unicast) | \
1147 (1ULL << EF10_STAT_port_tx_multicast) | \
1148 (1ULL << EF10_STAT_port_tx_broadcast) | \
1149 (1ULL << EF10_STAT_port_rx_bytes) | \
1151 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1152 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1153 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1154 (1ULL << EF10_STAT_port_rx_packets) | \
1155 (1ULL << EF10_STAT_port_rx_good) | \
1156 (1ULL << EF10_STAT_port_rx_bad) | \
1157 (1ULL << EF10_STAT_port_rx_pause) | \
1158 (1ULL << EF10_STAT_port_rx_control) | \
1159 (1ULL << EF10_STAT_port_rx_unicast) | \
1160 (1ULL << EF10_STAT_port_rx_multicast) | \
1161 (1ULL << EF10_STAT_port_rx_broadcast) | \
1162 (1ULL << EF10_STAT_port_rx_lt64) | \
1163 (1ULL << EF10_STAT_port_rx_64) | \
1164 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1165 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1166 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1167 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1168 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1169 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1170 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1171 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1172 (1ULL << EF10_STAT_port_rx_overflow) | \
1173 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1174 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1175 (1ULL << GENERIC_STAT_rx_noskb_drops))
1177 /* These statistics are only provided by the 10G MAC. For a 10G/40G
1178 * switchable port we do not expose these because they might not
1179 * include all the packets they should.
1181 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1182 (1ULL << EF10_STAT_port_tx_lt64) | \
1183 (1ULL << EF10_STAT_port_tx_64) | \
1184 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1185 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1186 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1187 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1188 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1189 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1191 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1192 * switchable port we do expose these because the errors will otherwise
1195 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1196 (1ULL << EF10_STAT_port_rx_length_error))
1198 /* These statistics are only provided if the firmware supports the
1199 * capability PM_AND_RXDP_COUNTERS.
1201 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1202 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1203 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1204 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1205 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1206 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1207 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1208 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1209 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1210 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1211 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1212 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1213 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1215 static u64
efx_ef10_raw_stat_mask(struct efx_nic
*efx
)
1217 u64 raw_mask
= HUNT_COMMON_STAT_MASK
;
1218 u32 port_caps
= efx_mcdi_phy_get_caps(efx
);
1219 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1221 if (!(efx
->mcdi
->fn_flags
&
1222 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL
))
1225 if (port_caps
& (1 << MC_CMD_PHY_CAP_40000FDX_LBN
))
1226 raw_mask
|= HUNT_40G_EXTRA_STAT_MASK
;
1228 raw_mask
|= HUNT_10G_ONLY_STAT_MASK
;
1230 if (nic_data
->datapath_caps
&
1231 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN
))
1232 raw_mask
|= HUNT_PM_AND_RXDP_STAT_MASK
;
1237 static void efx_ef10_get_stat_mask(struct efx_nic
*efx
, unsigned long *mask
)
1239 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1242 raw_mask
[0] = efx_ef10_raw_stat_mask(efx
);
1244 /* Only show vadaptor stats when EVB capability is present */
1245 if (nic_data
->datapath_caps
&
1246 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN
)) {
1247 raw_mask
[0] |= ~((1ULL << EF10_STAT_rx_unicast
) - 1);
1248 raw_mask
[1] = (1ULL << (EF10_STAT_COUNT
- 63)) - 1;
1253 #if BITS_PER_LONG == 64
1254 mask
[0] = raw_mask
[0];
1255 mask
[1] = raw_mask
[1];
1257 mask
[0] = raw_mask
[0] & 0xffffffff;
1258 mask
[1] = raw_mask
[0] >> 32;
1259 mask
[2] = raw_mask
[1] & 0xffffffff;
1260 mask
[3] = raw_mask
[1] >> 32;
1264 static size_t efx_ef10_describe_stats(struct efx_nic
*efx
, u8
*names
)
1266 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1268 efx_ef10_get_stat_mask(efx
, mask
);
1269 return efx_nic_describe_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
,
1273 static size_t efx_ef10_update_stats_common(struct efx_nic
*efx
, u64
*full_stats
,
1274 struct rtnl_link_stats64
*core_stats
)
1276 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1277 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1278 u64
*stats
= nic_data
->stats
;
1279 size_t stats_count
= 0, index
;
1281 efx_ef10_get_stat_mask(efx
, mask
);
1284 for_each_set_bit(index
, mask
, EF10_STAT_COUNT
) {
1285 if (efx_ef10_stat_desc
[index
].name
) {
1286 *full_stats
++ = stats
[index
];
1293 core_stats
->rx_packets
= stats
[EF10_STAT_rx_unicast
] +
1294 stats
[EF10_STAT_rx_multicast
] +
1295 stats
[EF10_STAT_rx_broadcast
];
1296 core_stats
->tx_packets
= stats
[EF10_STAT_tx_unicast
] +
1297 stats
[EF10_STAT_tx_multicast
] +
1298 stats
[EF10_STAT_tx_broadcast
];
1299 core_stats
->rx_bytes
= stats
[EF10_STAT_rx_unicast_bytes
] +
1300 stats
[EF10_STAT_rx_multicast_bytes
] +
1301 stats
[EF10_STAT_rx_broadcast_bytes
];
1302 core_stats
->tx_bytes
= stats
[EF10_STAT_tx_unicast_bytes
] +
1303 stats
[EF10_STAT_tx_multicast_bytes
] +
1304 stats
[EF10_STAT_tx_broadcast_bytes
];
1305 core_stats
->rx_dropped
= stats
[GENERIC_STAT_rx_nodesc_trunc
] +
1306 stats
[GENERIC_STAT_rx_noskb_drops
];
1307 core_stats
->multicast
= stats
[EF10_STAT_rx_multicast
];
1308 core_stats
->rx_crc_errors
= stats
[EF10_STAT_rx_bad
];
1309 core_stats
->rx_fifo_errors
= stats
[EF10_STAT_rx_overflow
];
1310 core_stats
->rx_errors
= core_stats
->rx_crc_errors
;
1311 core_stats
->tx_errors
= stats
[EF10_STAT_tx_bad
];
1317 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic
*efx
)
1319 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1320 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1321 __le64 generation_start
, generation_end
;
1322 u64
*stats
= nic_data
->stats
;
1325 efx_ef10_get_stat_mask(efx
, mask
);
1327 dma_stats
= efx
->stats_buffer
.addr
;
1328 nic_data
= efx
->nic_data
;
1330 generation_end
= dma_stats
[MC_CMD_MAC_GENERATION_END
];
1331 if (generation_end
== EFX_MC_STATS_GENERATION_INVALID
)
1334 efx_nic_update_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
, mask
,
1335 stats
, efx
->stats_buffer
.addr
, false);
1337 generation_start
= dma_stats
[MC_CMD_MAC_GENERATION_START
];
1338 if (generation_end
!= generation_start
)
1341 /* Update derived statistics */
1342 efx_nic_fix_nodesc_drop_stat(efx
,
1343 &stats
[EF10_STAT_port_rx_nodesc_drops
]);
1344 stats
[EF10_STAT_port_rx_good_bytes
] =
1345 stats
[EF10_STAT_port_rx_bytes
] -
1346 stats
[EF10_STAT_port_rx_bytes_minus_good_bytes
];
1347 efx_update_diff_stat(&stats
[EF10_STAT_port_rx_bad_bytes
],
1348 stats
[EF10_STAT_port_rx_bytes_minus_good_bytes
]);
1349 efx_update_sw_stats(efx
, stats
);
1354 static size_t efx_ef10_update_stats_pf(struct efx_nic
*efx
, u64
*full_stats
,
1355 struct rtnl_link_stats64
*core_stats
)
1359 /* If we're unlucky enough to read statistics during the DMA, wait
1360 * up to 10ms for it to finish (typically takes <500us)
1362 for (retry
= 0; retry
< 100; ++retry
) {
1363 if (efx_ef10_try_update_nic_stats_pf(efx
) == 0)
1368 return efx_ef10_update_stats_common(efx
, full_stats
, core_stats
);
1371 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic
*efx
)
1373 MCDI_DECLARE_BUF(inbuf
, MC_CMD_MAC_STATS_IN_LEN
);
1374 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1375 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1376 __le64 generation_start
, generation_end
;
1377 u64
*stats
= nic_data
->stats
;
1378 u32 dma_len
= MC_CMD_MAC_NSTATS
* sizeof(u64
);
1379 struct efx_buffer stats_buf
;
1383 spin_unlock_bh(&efx
->stats_lock
);
1385 if (in_interrupt()) {
1386 /* If in atomic context, cannot update stats. Just update the
1387 * software stats and return so the caller can continue.
1389 spin_lock_bh(&efx
->stats_lock
);
1390 efx_update_sw_stats(efx
, stats
);
1394 efx_ef10_get_stat_mask(efx
, mask
);
1396 rc
= efx_nic_alloc_buffer(efx
, &stats_buf
, dma_len
, GFP_ATOMIC
);
1398 spin_lock_bh(&efx
->stats_lock
);
1402 dma_stats
= stats_buf
.addr
;
1403 dma_stats
[MC_CMD_MAC_GENERATION_END
] = EFX_MC_STATS_GENERATION_INVALID
;
1405 MCDI_SET_QWORD(inbuf
, MAC_STATS_IN_DMA_ADDR
, stats_buf
.dma_addr
);
1406 MCDI_POPULATE_DWORD_1(inbuf
, MAC_STATS_IN_CMD
,
1407 MAC_STATS_IN_DMA
, 1);
1408 MCDI_SET_DWORD(inbuf
, MAC_STATS_IN_DMA_LEN
, dma_len
);
1409 MCDI_SET_DWORD(inbuf
, MAC_STATS_IN_PORT_ID
, EVB_PORT_ID_ASSIGNED
);
1411 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_MAC_STATS
, inbuf
, sizeof(inbuf
),
1413 spin_lock_bh(&efx
->stats_lock
);
1415 /* Expect ENOENT if DMA queues have not been set up */
1416 if (rc
!= -ENOENT
|| atomic_read(&efx
->active_queues
))
1417 efx_mcdi_display_error(efx
, MC_CMD_MAC_STATS
,
1418 sizeof(inbuf
), NULL
, 0, rc
);
1422 generation_end
= dma_stats
[MC_CMD_MAC_GENERATION_END
];
1423 if (generation_end
== EFX_MC_STATS_GENERATION_INVALID
) {
1428 efx_nic_update_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
, mask
,
1429 stats
, stats_buf
.addr
, false);
1431 generation_start
= dma_stats
[MC_CMD_MAC_GENERATION_START
];
1432 if (generation_end
!= generation_start
) {
1437 efx_update_sw_stats(efx
, stats
);
1439 efx_nic_free_buffer(efx
, &stats_buf
);
1443 static size_t efx_ef10_update_stats_vf(struct efx_nic
*efx
, u64
*full_stats
,
1444 struct rtnl_link_stats64
*core_stats
)
1446 if (efx_ef10_try_update_nic_stats_vf(efx
))
1449 return efx_ef10_update_stats_common(efx
, full_stats
, core_stats
);
1452 static void efx_ef10_push_irq_moderation(struct efx_channel
*channel
)
1454 struct efx_nic
*efx
= channel
->efx
;
1455 unsigned int mode
, value
;
1456 efx_dword_t timer_cmd
;
1458 if (channel
->irq_moderation
) {
1460 value
= channel
->irq_moderation
- 1;
1466 if (EFX_EF10_WORKAROUND_35388(efx
)) {
1467 EFX_POPULATE_DWORD_3(timer_cmd
, ERF_DD_EVQ_IND_TIMER_FLAGS
,
1468 EFE_DD_EVQ_IND_TIMER_FLAGS
,
1469 ERF_DD_EVQ_IND_TIMER_MODE
, mode
,
1470 ERF_DD_EVQ_IND_TIMER_VAL
, value
);
1471 efx_writed_page(efx
, &timer_cmd
, ER_DD_EVQ_INDIRECT
,
1474 EFX_POPULATE_DWORD_2(timer_cmd
, ERF_DZ_TC_TIMER_MODE
, mode
,
1475 ERF_DZ_TC_TIMER_VAL
, value
);
1476 efx_writed_page(efx
, &timer_cmd
, ER_DZ_EVQ_TMR
,
1481 static void efx_ef10_get_wol_vf(struct efx_nic
*efx
,
1482 struct ethtool_wolinfo
*wol
) {}
1484 static int efx_ef10_set_wol_vf(struct efx_nic
*efx
, u32 type
)
1489 static void efx_ef10_get_wol(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
)
1493 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
1496 static int efx_ef10_set_wol(struct efx_nic
*efx
, u32 type
)
1503 static void efx_ef10_mcdi_request(struct efx_nic
*efx
,
1504 const efx_dword_t
*hdr
, size_t hdr_len
,
1505 const efx_dword_t
*sdu
, size_t sdu_len
)
1507 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1508 u8
*pdu
= nic_data
->mcdi_buf
.addr
;
1510 memcpy(pdu
, hdr
, hdr_len
);
1511 memcpy(pdu
+ hdr_len
, sdu
, sdu_len
);
1514 /* The hardware provides 'low' and 'high' (doorbell) registers
1515 * for passing the 64-bit address of an MCDI request to
1516 * firmware. However the dwords are swapped by firmware. The
1517 * least significant bits of the doorbell are then 0 for all
1518 * MCDI requests due to alignment.
1520 _efx_writed(efx
, cpu_to_le32((u64
)nic_data
->mcdi_buf
.dma_addr
>> 32),
1522 _efx_writed(efx
, cpu_to_le32((u32
)nic_data
->mcdi_buf
.dma_addr
),
1526 static bool efx_ef10_mcdi_poll_response(struct efx_nic
*efx
)
1528 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1529 const efx_dword_t hdr
= *(const efx_dword_t
*)nic_data
->mcdi_buf
.addr
;
1532 return EFX_DWORD_FIELD(hdr
, MCDI_HEADER_RESPONSE
);
1536 efx_ef10_mcdi_read_response(struct efx_nic
*efx
, efx_dword_t
*outbuf
,
1537 size_t offset
, size_t outlen
)
1539 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1540 const u8
*pdu
= nic_data
->mcdi_buf
.addr
;
1542 memcpy(outbuf
, pdu
+ offset
, outlen
);
1545 static int efx_ef10_mcdi_poll_reboot(struct efx_nic
*efx
)
1547 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1550 rc
= efx_ef10_get_warm_boot_count(efx
);
1552 /* The firmware is presumably in the process of
1553 * rebooting. However, we are supposed to report each
1554 * reboot just once, so we must only do that once we
1555 * can read and store the updated warm boot count.
1560 if (rc
== nic_data
->warm_boot_count
)
1563 nic_data
->warm_boot_count
= rc
;
1565 /* All our allocations have been reset */
1566 efx_ef10_reset_mc_allocations(efx
);
1568 /* Driver-created vswitches and vports must be re-created */
1569 nic_data
->must_probe_vswitching
= true;
1570 nic_data
->vport_id
= EVB_PORT_ID_ASSIGNED
;
1572 /* The datapath firmware might have been changed */
1573 nic_data
->must_check_datapath_caps
= true;
1575 /* MAC statistics have been cleared on the NIC; clear the local
1576 * statistic that we update with efx_update_diff_stat().
1578 nic_data
->stats
[EF10_STAT_port_rx_bad_bytes
] = 0;
1583 /* Handle an MSI interrupt
1585 * Handle an MSI hardware interrupt. This routine schedules event
1586 * queue processing. No interrupt acknowledgement cycle is necessary.
1587 * Also, we never need to check that the interrupt is for us, since
1588 * MSI interrupts cannot be shared.
1590 static irqreturn_t
efx_ef10_msi_interrupt(int irq
, void *dev_id
)
1592 struct efx_msi_context
*context
= dev_id
;
1593 struct efx_nic
*efx
= context
->efx
;
1595 netif_vdbg(efx
, intr
, efx
->net_dev
,
1596 "IRQ %d on CPU %d\n", irq
, raw_smp_processor_id());
1598 if (likely(ACCESS_ONCE(efx
->irq_soft_enabled
))) {
1599 /* Note test interrupts */
1600 if (context
->index
== efx
->irq_level
)
1601 efx
->last_irq_cpu
= raw_smp_processor_id();
1603 /* Schedule processing of the channel */
1604 efx_schedule_channel_irq(efx
->channel
[context
->index
]);
1610 static irqreturn_t
efx_ef10_legacy_interrupt(int irq
, void *dev_id
)
1612 struct efx_nic
*efx
= dev_id
;
1613 bool soft_enabled
= ACCESS_ONCE(efx
->irq_soft_enabled
);
1614 struct efx_channel
*channel
;
1618 /* Read the ISR which also ACKs the interrupts */
1619 efx_readd(efx
, ®
, ER_DZ_BIU_INT_ISR
);
1620 queues
= EFX_DWORD_FIELD(reg
, ERF_DZ_ISR_REG
);
1625 if (likely(soft_enabled
)) {
1626 /* Note test interrupts */
1627 if (queues
& (1U << efx
->irq_level
))
1628 efx
->last_irq_cpu
= raw_smp_processor_id();
1630 efx_for_each_channel(channel
, efx
) {
1632 efx_schedule_channel_irq(channel
);
1637 netif_vdbg(efx
, intr
, efx
->net_dev
,
1638 "IRQ %d on CPU %d status " EFX_DWORD_FMT
"\n",
1639 irq
, raw_smp_processor_id(), EFX_DWORD_VAL(reg
));
1644 static void efx_ef10_irq_test_generate(struct efx_nic
*efx
)
1646 MCDI_DECLARE_BUF(inbuf
, MC_CMD_TRIGGER_INTERRUPT_IN_LEN
);
1648 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN
!= 0);
1650 MCDI_SET_DWORD(inbuf
, TRIGGER_INTERRUPT_IN_INTR_LEVEL
, efx
->irq_level
);
1651 (void) efx_mcdi_rpc(efx
, MC_CMD_TRIGGER_INTERRUPT
,
1652 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
1655 static int efx_ef10_tx_probe(struct efx_tx_queue
*tx_queue
)
1657 return efx_nic_alloc_buffer(tx_queue
->efx
, &tx_queue
->txd
.buf
,
1658 (tx_queue
->ptr_mask
+ 1) *
1659 sizeof(efx_qword_t
),
1663 /* This writes to the TX_DESC_WPTR and also pushes data */
1664 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue
*tx_queue
,
1665 const efx_qword_t
*txd
)
1667 unsigned int write_ptr
;
1670 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
1671 EFX_POPULATE_OWORD_1(reg
, ERF_DZ_TX_DESC_WPTR
, write_ptr
);
1672 reg
.qword
[0] = *txd
;
1673 efx_writeo_page(tx_queue
->efx
, ®
,
1674 ER_DZ_TX_DESC_UPD
, tx_queue
->queue
);
1677 static void efx_ef10_tx_init(struct efx_tx_queue
*tx_queue
)
1679 MCDI_DECLARE_BUF(inbuf
, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE
* 8 /
1681 bool csum_offload
= tx_queue
->queue
& EFX_TXQ_TYPE_OFFLOAD
;
1682 size_t entries
= tx_queue
->txd
.buf
.len
/ EFX_BUF_SIZE
;
1683 struct efx_channel
*channel
= tx_queue
->channel
;
1684 struct efx_nic
*efx
= tx_queue
->efx
;
1685 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1687 dma_addr_t dma_addr
;
1691 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN
!= 0);
1693 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_SIZE
, tx_queue
->ptr_mask
+ 1);
1694 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_TARGET_EVQ
, channel
->channel
);
1695 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_LABEL
, tx_queue
->queue
);
1696 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_INSTANCE
, tx_queue
->queue
);
1697 MCDI_POPULATE_DWORD_2(inbuf
, INIT_TXQ_IN_FLAGS
,
1698 INIT_TXQ_IN_FLAG_IP_CSUM_DIS
, !csum_offload
,
1699 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS
, !csum_offload
);
1700 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_OWNER_ID
, 0);
1701 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_PORT_ID
, nic_data
->vport_id
);
1703 dma_addr
= tx_queue
->txd
.buf
.dma_addr
;
1705 netif_dbg(efx
, hw
, efx
->net_dev
, "pushing TXQ %d. %zu entries (%llx)\n",
1706 tx_queue
->queue
, entries
, (u64
)dma_addr
);
1708 for (i
= 0; i
< entries
; ++i
) {
1709 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_TXQ_IN_DMA_ADDR
, i
, dma_addr
);
1710 dma_addr
+= EFX_BUF_SIZE
;
1713 inlen
= MC_CMD_INIT_TXQ_IN_LEN(entries
);
1715 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_TXQ
, inbuf
, inlen
,
1720 /* A previous user of this TX queue might have set us up the
1721 * bomb by writing a descriptor to the TX push collector but
1722 * not the doorbell. (Each collector belongs to a port, not a
1723 * queue or function, so cannot easily be reset.) We must
1724 * attempt to push a no-op descriptor in its place.
1726 tx_queue
->buffer
[0].flags
= EFX_TX_BUF_OPTION
;
1727 tx_queue
->insert_count
= 1;
1728 txd
= efx_tx_desc(tx_queue
, 0);
1729 EFX_POPULATE_QWORD_4(*txd
,
1730 ESF_DZ_TX_DESC_IS_OPT
, true,
1731 ESF_DZ_TX_OPTION_TYPE
,
1732 ESE_DZ_TX_OPTION_DESC_CRC_CSUM
,
1733 ESF_DZ_TX_OPTION_UDP_TCP_CSUM
, csum_offload
,
1734 ESF_DZ_TX_OPTION_IP_CSUM
, csum_offload
);
1735 tx_queue
->write_count
= 1;
1737 efx_ef10_push_tx_desc(tx_queue
, txd
);
1742 netdev_WARN(efx
->net_dev
, "failed to initialise TXQ %d\n",
1746 static void efx_ef10_tx_fini(struct efx_tx_queue
*tx_queue
)
1748 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_TXQ_IN_LEN
);
1749 MCDI_DECLARE_BUF_ERR(outbuf
);
1750 struct efx_nic
*efx
= tx_queue
->efx
;
1754 MCDI_SET_DWORD(inbuf
, FINI_TXQ_IN_INSTANCE
,
1757 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_TXQ
, inbuf
, sizeof(inbuf
),
1758 outbuf
, sizeof(outbuf
), &outlen
);
1760 if (rc
&& rc
!= -EALREADY
)
1766 efx_mcdi_display_error(efx
, MC_CMD_FINI_TXQ
, MC_CMD_FINI_TXQ_IN_LEN
,
1767 outbuf
, outlen
, rc
);
1770 static void efx_ef10_tx_remove(struct efx_tx_queue
*tx_queue
)
1772 efx_nic_free_buffer(tx_queue
->efx
, &tx_queue
->txd
.buf
);
1775 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1776 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue
*tx_queue
)
1778 unsigned int write_ptr
;
1781 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
1782 EFX_POPULATE_DWORD_1(reg
, ERF_DZ_TX_DESC_WPTR_DWORD
, write_ptr
);
1783 efx_writed_page(tx_queue
->efx
, ®
,
1784 ER_DZ_TX_DESC_UPD_DWORD
, tx_queue
->queue
);
1787 static void efx_ef10_tx_write(struct efx_tx_queue
*tx_queue
)
1789 unsigned int old_write_count
= tx_queue
->write_count
;
1790 struct efx_tx_buffer
*buffer
;
1791 unsigned int write_ptr
;
1794 BUG_ON(tx_queue
->write_count
== tx_queue
->insert_count
);
1797 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
1798 buffer
= &tx_queue
->buffer
[write_ptr
];
1799 txd
= efx_tx_desc(tx_queue
, write_ptr
);
1800 ++tx_queue
->write_count
;
1802 /* Create TX descriptor ring entry */
1803 if (buffer
->flags
& EFX_TX_BUF_OPTION
) {
1804 *txd
= buffer
->option
;
1806 BUILD_BUG_ON(EFX_TX_BUF_CONT
!= 1);
1807 EFX_POPULATE_QWORD_3(
1810 buffer
->flags
& EFX_TX_BUF_CONT
,
1811 ESF_DZ_TX_KER_BYTE_CNT
, buffer
->len
,
1812 ESF_DZ_TX_KER_BUF_ADDR
, buffer
->dma_addr
);
1814 } while (tx_queue
->write_count
!= tx_queue
->insert_count
);
1816 wmb(); /* Ensure descriptors are written before they are fetched */
1818 if (efx_nic_may_push_tx_desc(tx_queue
, old_write_count
)) {
1819 txd
= efx_tx_desc(tx_queue
,
1820 old_write_count
& tx_queue
->ptr_mask
);
1821 efx_ef10_push_tx_desc(tx_queue
, txd
);
1824 efx_ef10_notify_tx_desc(tx_queue
);
1828 static int efx_ef10_alloc_rss_context(struct efx_nic
*efx
, u32
*context
,
1829 bool exclusive
, unsigned *context_size
)
1831 MCDI_DECLARE_BUF(inbuf
, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN
);
1832 MCDI_DECLARE_BUF(outbuf
, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN
);
1833 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1836 u32 alloc_type
= exclusive
?
1837 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE
:
1838 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED
;
1839 unsigned rss_spread
= exclusive
?
1841 min(rounddown_pow_of_two(efx
->rss_spread
),
1842 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE
);
1844 if (!exclusive
&& rss_spread
== 1) {
1845 *context
= EFX_EF10_RSS_CONTEXT_INVALID
;
1851 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID
,
1852 nic_data
->vport_id
);
1853 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_TYPE
, alloc_type
);
1854 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES
, rss_spread
);
1856 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_ALLOC
, inbuf
, sizeof(inbuf
),
1857 outbuf
, sizeof(outbuf
), &outlen
);
1861 if (outlen
< MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN
)
1864 *context
= MCDI_DWORD(outbuf
, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID
);
1867 *context_size
= rss_spread
;
1872 static void efx_ef10_free_rss_context(struct efx_nic
*efx
, u32 context
)
1874 MCDI_DECLARE_BUF(inbuf
, MC_CMD_RSS_CONTEXT_FREE_IN_LEN
);
1877 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID
,
1880 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_FREE
, inbuf
, sizeof(inbuf
),
1885 static int efx_ef10_populate_rss_table(struct efx_nic
*efx
, u32 context
,
1886 const u32
*rx_indir_table
)
1888 MCDI_DECLARE_BUF(tablebuf
, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN
);
1889 MCDI_DECLARE_BUF(keybuf
, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN
);
1892 MCDI_SET_DWORD(tablebuf
, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID
,
1894 BUILD_BUG_ON(ARRAY_SIZE(efx
->rx_indir_table
) !=
1895 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN
);
1897 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_indir_table
); ++i
)
1899 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE
)[i
] =
1900 (u8
) rx_indir_table
[i
];
1902 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_SET_TABLE
, tablebuf
,
1903 sizeof(tablebuf
), NULL
, 0, NULL
);
1907 MCDI_SET_DWORD(keybuf
, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID
,
1909 BUILD_BUG_ON(ARRAY_SIZE(efx
->rx_hash_key
) !=
1910 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN
);
1911 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_hash_key
); ++i
)
1912 MCDI_PTR(keybuf
, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY
)[i
] =
1913 efx
->rx_hash_key
[i
];
1915 return efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_SET_KEY
, keybuf
,
1916 sizeof(keybuf
), NULL
, 0, NULL
);
1919 static void efx_ef10_rx_free_indir_table(struct efx_nic
*efx
)
1921 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1923 if (nic_data
->rx_rss_context
!= EFX_EF10_RSS_CONTEXT_INVALID
)
1924 efx_ef10_free_rss_context(efx
, nic_data
->rx_rss_context
);
1925 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
1928 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic
*efx
,
1929 unsigned *context_size
)
1931 u32 new_rx_rss_context
;
1932 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1933 int rc
= efx_ef10_alloc_rss_context(efx
, &new_rx_rss_context
,
1934 false, context_size
);
1939 nic_data
->rx_rss_context
= new_rx_rss_context
;
1940 nic_data
->rx_rss_context_exclusive
= false;
1941 efx_set_default_rx_indir_table(efx
);
1945 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic
*efx
,
1946 const u32
*rx_indir_table
)
1948 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1950 u32 new_rx_rss_context
;
1952 if (nic_data
->rx_rss_context
== EFX_EF10_RSS_CONTEXT_INVALID
||
1953 !nic_data
->rx_rss_context_exclusive
) {
1954 rc
= efx_ef10_alloc_rss_context(efx
, &new_rx_rss_context
,
1956 if (rc
== -EOPNOTSUPP
)
1961 new_rx_rss_context
= nic_data
->rx_rss_context
;
1964 rc
= efx_ef10_populate_rss_table(efx
, new_rx_rss_context
,
1969 if (nic_data
->rx_rss_context
!= new_rx_rss_context
)
1970 efx_ef10_rx_free_indir_table(efx
);
1971 nic_data
->rx_rss_context
= new_rx_rss_context
;
1972 nic_data
->rx_rss_context_exclusive
= true;
1973 if (rx_indir_table
!= efx
->rx_indir_table
)
1974 memcpy(efx
->rx_indir_table
, rx_indir_table
,
1975 sizeof(efx
->rx_indir_table
));
1979 if (new_rx_rss_context
!= nic_data
->rx_rss_context
)
1980 efx_ef10_free_rss_context(efx
, new_rx_rss_context
);
1982 netif_err(efx
, hw
, efx
->net_dev
, "%s: failed rc=%d\n", __func__
, rc
);
1986 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic
*efx
, bool user
,
1987 const u32
*rx_indir_table
)
1991 if (efx
->rss_spread
== 1)
1994 rc
= efx_ef10_rx_push_exclusive_rss_config(efx
, rx_indir_table
);
1996 if (rc
== -ENOBUFS
&& !user
) {
1997 unsigned context_size
;
1998 bool mismatch
= false;
2001 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_indir_table
) && !mismatch
;
2003 mismatch
= rx_indir_table
[i
] !=
2004 ethtool_rxfh_indir_default(i
, efx
->rss_spread
);
2006 rc
= efx_ef10_rx_push_shared_rss_config(efx
, &context_size
);
2008 if (context_size
!= efx
->rss_spread
)
2009 netif_warn(efx
, probe
, efx
->net_dev
,
2010 "Could not allocate an exclusive RSS"
2011 " context; allocated a shared one of"
2013 " Wanted %u, got %u.\n",
2014 efx
->rss_spread
, context_size
);
2016 netif_warn(efx
, probe
, efx
->net_dev
,
2017 "Could not allocate an exclusive RSS"
2018 " context; allocated a shared one but"
2019 " could not apply custom"
2022 netif_info(efx
, probe
, efx
->net_dev
,
2023 "Could not allocate an exclusive RSS"
2024 " context; allocated a shared one.\n");
2030 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic
*efx
, bool user
,
2031 const u32
*rx_indir_table
2032 __attribute__ ((unused
)))
2034 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2038 if (nic_data
->rx_rss_context
!= EFX_EF10_RSS_CONTEXT_INVALID
)
2040 return efx_ef10_rx_push_shared_rss_config(efx
, NULL
);
2043 static int efx_ef10_rx_probe(struct efx_rx_queue
*rx_queue
)
2045 return efx_nic_alloc_buffer(rx_queue
->efx
, &rx_queue
->rxd
.buf
,
2046 (rx_queue
->ptr_mask
+ 1) *
2047 sizeof(efx_qword_t
),
2051 static void efx_ef10_rx_init(struct efx_rx_queue
*rx_queue
)
2053 MCDI_DECLARE_BUF(inbuf
,
2054 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE
* 8 /
2056 struct efx_channel
*channel
= efx_rx_queue_channel(rx_queue
);
2057 size_t entries
= rx_queue
->rxd
.buf
.len
/ EFX_BUF_SIZE
;
2058 struct efx_nic
*efx
= rx_queue
->efx
;
2059 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2061 dma_addr_t dma_addr
;
2064 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN
!= 0);
2066 rx_queue
->scatter_n
= 0;
2067 rx_queue
->scatter_len
= 0;
2069 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_SIZE
, rx_queue
->ptr_mask
+ 1);
2070 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_TARGET_EVQ
, channel
->channel
);
2071 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_LABEL
, efx_rx_queue_index(rx_queue
));
2072 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_INSTANCE
,
2073 efx_rx_queue_index(rx_queue
));
2074 MCDI_POPULATE_DWORD_2(inbuf
, INIT_RXQ_IN_FLAGS
,
2075 INIT_RXQ_IN_FLAG_PREFIX
, 1,
2076 INIT_RXQ_IN_FLAG_TIMESTAMP
, 1);
2077 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_OWNER_ID
, 0);
2078 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_PORT_ID
, nic_data
->vport_id
);
2080 dma_addr
= rx_queue
->rxd
.buf
.dma_addr
;
2082 netif_dbg(efx
, hw
, efx
->net_dev
, "pushing RXQ %d. %zu entries (%llx)\n",
2083 efx_rx_queue_index(rx_queue
), entries
, (u64
)dma_addr
);
2085 for (i
= 0; i
< entries
; ++i
) {
2086 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_RXQ_IN_DMA_ADDR
, i
, dma_addr
);
2087 dma_addr
+= EFX_BUF_SIZE
;
2090 inlen
= MC_CMD_INIT_RXQ_IN_LEN(entries
);
2092 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_RXQ
, inbuf
, inlen
,
2095 netdev_WARN(efx
->net_dev
, "failed to initialise RXQ %d\n",
2096 efx_rx_queue_index(rx_queue
));
2099 static void efx_ef10_rx_fini(struct efx_rx_queue
*rx_queue
)
2101 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_RXQ_IN_LEN
);
2102 MCDI_DECLARE_BUF_ERR(outbuf
);
2103 struct efx_nic
*efx
= rx_queue
->efx
;
2107 MCDI_SET_DWORD(inbuf
, FINI_RXQ_IN_INSTANCE
,
2108 efx_rx_queue_index(rx_queue
));
2110 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_RXQ
, inbuf
, sizeof(inbuf
),
2111 outbuf
, sizeof(outbuf
), &outlen
);
2113 if (rc
&& rc
!= -EALREADY
)
2119 efx_mcdi_display_error(efx
, MC_CMD_FINI_RXQ
, MC_CMD_FINI_RXQ_IN_LEN
,
2120 outbuf
, outlen
, rc
);
2123 static void efx_ef10_rx_remove(struct efx_rx_queue
*rx_queue
)
2125 efx_nic_free_buffer(rx_queue
->efx
, &rx_queue
->rxd
.buf
);
2128 /* This creates an entry in the RX descriptor queue */
2130 efx_ef10_build_rx_desc(struct efx_rx_queue
*rx_queue
, unsigned int index
)
2132 struct efx_rx_buffer
*rx_buf
;
2135 rxd
= efx_rx_desc(rx_queue
, index
);
2136 rx_buf
= efx_rx_buffer(rx_queue
, index
);
2137 EFX_POPULATE_QWORD_2(*rxd
,
2138 ESF_DZ_RX_KER_BYTE_CNT
, rx_buf
->len
,
2139 ESF_DZ_RX_KER_BUF_ADDR
, rx_buf
->dma_addr
);
2142 static void efx_ef10_rx_write(struct efx_rx_queue
*rx_queue
)
2144 struct efx_nic
*efx
= rx_queue
->efx
;
2145 unsigned int write_count
;
2148 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2149 write_count
= rx_queue
->added_count
& ~7;
2150 if (rx_queue
->notified_count
== write_count
)
2154 efx_ef10_build_rx_desc(
2156 rx_queue
->notified_count
& rx_queue
->ptr_mask
);
2157 while (++rx_queue
->notified_count
!= write_count
);
2160 EFX_POPULATE_DWORD_1(reg
, ERF_DZ_RX_DESC_WPTR
,
2161 write_count
& rx_queue
->ptr_mask
);
2162 efx_writed_page(efx
, ®
, ER_DZ_RX_DESC_UPD
,
2163 efx_rx_queue_index(rx_queue
));
2166 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete
;
2168 static void efx_ef10_rx_defer_refill(struct efx_rx_queue
*rx_queue
)
2170 struct efx_channel
*channel
= efx_rx_queue_channel(rx_queue
);
2171 MCDI_DECLARE_BUF(inbuf
, MC_CMD_DRIVER_EVENT_IN_LEN
);
2174 EFX_POPULATE_QWORD_2(event
,
2175 ESF_DZ_EV_CODE
, EFX_EF10_DRVGEN_EV
,
2176 ESF_DZ_EV_DATA
, EFX_EF10_REFILL
);
2178 MCDI_SET_DWORD(inbuf
, DRIVER_EVENT_IN_EVQ
, channel
->channel
);
2180 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2181 * already swapped the data to little-endian order.
2183 memcpy(MCDI_PTR(inbuf
, DRIVER_EVENT_IN_DATA
), &event
.u64
[0],
2184 sizeof(efx_qword_t
));
2186 efx_mcdi_rpc_async(channel
->efx
, MC_CMD_DRIVER_EVENT
,
2187 inbuf
, sizeof(inbuf
), 0,
2188 efx_ef10_rx_defer_refill_complete
, 0);
2192 efx_ef10_rx_defer_refill_complete(struct efx_nic
*efx
, unsigned long cookie
,
2193 int rc
, efx_dword_t
*outbuf
,
2194 size_t outlen_actual
)
2199 static int efx_ef10_ev_probe(struct efx_channel
*channel
)
2201 return efx_nic_alloc_buffer(channel
->efx
, &channel
->eventq
.buf
,
2202 (channel
->eventq_mask
+ 1) *
2203 sizeof(efx_qword_t
),
2207 static void efx_ef10_ev_fini(struct efx_channel
*channel
)
2209 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_EVQ_IN_LEN
);
2210 MCDI_DECLARE_BUF_ERR(outbuf
);
2211 struct efx_nic
*efx
= channel
->efx
;
2215 MCDI_SET_DWORD(inbuf
, FINI_EVQ_IN_INSTANCE
, channel
->channel
);
2217 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_EVQ
, inbuf
, sizeof(inbuf
),
2218 outbuf
, sizeof(outbuf
), &outlen
);
2220 if (rc
&& rc
!= -EALREADY
)
2226 efx_mcdi_display_error(efx
, MC_CMD_FINI_EVQ
, MC_CMD_FINI_EVQ_IN_LEN
,
2227 outbuf
, outlen
, rc
);
2230 static int efx_ef10_ev_init(struct efx_channel
*channel
)
2232 MCDI_DECLARE_BUF(inbuf
,
2233 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE
* 8 /
2235 MCDI_DECLARE_BUF(outbuf
, MC_CMD_INIT_EVQ_OUT_LEN
);
2236 size_t entries
= channel
->eventq
.buf
.len
/ EFX_BUF_SIZE
;
2237 struct efx_nic
*efx
= channel
->efx
;
2238 struct efx_ef10_nic_data
*nic_data
;
2239 bool supports_rx_merge
;
2240 size_t inlen
, outlen
;
2241 unsigned int enabled
, implemented
;
2242 dma_addr_t dma_addr
;
2246 nic_data
= efx
->nic_data
;
2248 !!(nic_data
->datapath_caps
&
2249 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN
);
2251 /* Fill event queue with all ones (i.e. empty events) */
2252 memset(channel
->eventq
.buf
.addr
, 0xff, channel
->eventq
.buf
.len
);
2254 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_SIZE
, channel
->eventq_mask
+ 1);
2255 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_INSTANCE
, channel
->channel
);
2256 /* INIT_EVQ expects index in vector table, not absolute */
2257 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_IRQ_NUM
, channel
->channel
);
2258 MCDI_POPULATE_DWORD_4(inbuf
, INIT_EVQ_IN_FLAGS
,
2259 INIT_EVQ_IN_FLAG_INTERRUPTING
, 1,
2260 INIT_EVQ_IN_FLAG_RX_MERGE
, 1,
2261 INIT_EVQ_IN_FLAG_TX_MERGE
, 1,
2262 INIT_EVQ_IN_FLAG_CUT_THRU
, !supports_rx_merge
);
2263 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_MODE
,
2264 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS
);
2265 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_LOAD
, 0);
2266 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_RELOAD
, 0);
2267 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_COUNT_MODE
,
2268 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS
);
2269 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_COUNT_THRSHLD
, 0);
2271 dma_addr
= channel
->eventq
.buf
.dma_addr
;
2272 for (i
= 0; i
< entries
; ++i
) {
2273 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_EVQ_IN_DMA_ADDR
, i
, dma_addr
);
2274 dma_addr
+= EFX_BUF_SIZE
;
2277 inlen
= MC_CMD_INIT_EVQ_IN_LEN(entries
);
2279 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_EVQ
, inbuf
, inlen
,
2280 outbuf
, sizeof(outbuf
), &outlen
);
2281 /* IRQ return is ignored */
2282 if (channel
->channel
|| rc
)
2285 /* Successfully created event queue on channel 0 */
2286 rc
= efx_mcdi_get_workarounds(efx
, &implemented
, &enabled
);
2287 if (rc
== -ENOSYS
) {
2288 /* GET_WORKAROUNDS was implemented before the bug26807
2289 * workaround, thus the latter must be unavailable in this fw
2291 nic_data
->workaround_26807
= false;
2296 nic_data
->workaround_26807
=
2297 !!(enabled
& MC_CMD_GET_WORKAROUNDS_OUT_BUG26807
);
2299 if (implemented
& MC_CMD_GET_WORKAROUNDS_OUT_BUG26807
&&
2300 !nic_data
->workaround_26807
) {
2303 rc
= efx_mcdi_set_workaround(efx
,
2304 MC_CMD_WORKAROUND_BUG26807
,
2309 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN
) {
2310 netif_info(efx
, drv
, efx
->net_dev
,
2311 "other functions on NIC have been reset\n");
2312 /* MC's boot count has incremented */
2313 ++nic_data
->warm_boot_count
;
2315 nic_data
->workaround_26807
= true;
2316 } else if (rc
== -EPERM
) {
2326 efx_ef10_ev_fini(channel
);
2330 static void efx_ef10_ev_remove(struct efx_channel
*channel
)
2332 efx_nic_free_buffer(channel
->efx
, &channel
->eventq
.buf
);
2335 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue
*rx_queue
,
2336 unsigned int rx_queue_label
)
2338 struct efx_nic
*efx
= rx_queue
->efx
;
2340 netif_info(efx
, hw
, efx
->net_dev
,
2341 "rx event arrived on queue %d labeled as queue %u\n",
2342 efx_rx_queue_index(rx_queue
), rx_queue_label
);
2344 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
2348 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue
*rx_queue
,
2349 unsigned int actual
, unsigned int expected
)
2351 unsigned int dropped
= (actual
- expected
) & rx_queue
->ptr_mask
;
2352 struct efx_nic
*efx
= rx_queue
->efx
;
2354 netif_info(efx
, hw
, efx
->net_dev
,
2355 "dropped %d events (index=%d expected=%d)\n",
2356 dropped
, actual
, expected
);
2358 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
2361 /* partially received RX was aborted. clean up. */
2362 static void efx_ef10_handle_rx_abort(struct efx_rx_queue
*rx_queue
)
2364 unsigned int rx_desc_ptr
;
2366 netif_dbg(rx_queue
->efx
, hw
, rx_queue
->efx
->net_dev
,
2367 "scattered RX aborted (dropping %u buffers)\n",
2368 rx_queue
->scatter_n
);
2370 rx_desc_ptr
= rx_queue
->removed_count
& rx_queue
->ptr_mask
;
2372 efx_rx_packet(rx_queue
, rx_desc_ptr
, rx_queue
->scatter_n
,
2373 0, EFX_RX_PKT_DISCARD
);
2375 rx_queue
->removed_count
+= rx_queue
->scatter_n
;
2376 rx_queue
->scatter_n
= 0;
2377 rx_queue
->scatter_len
= 0;
2378 ++efx_rx_queue_channel(rx_queue
)->n_rx_nodesc_trunc
;
2381 static int efx_ef10_handle_rx_event(struct efx_channel
*channel
,
2382 const efx_qword_t
*event
)
2384 unsigned int rx_bytes
, next_ptr_lbits
, rx_queue_label
, rx_l4_class
;
2385 unsigned int n_descs
, n_packets
, i
;
2386 struct efx_nic
*efx
= channel
->efx
;
2387 struct efx_rx_queue
*rx_queue
;
2391 if (unlikely(ACCESS_ONCE(efx
->reset_pending
)))
2394 /* Basic packet information */
2395 rx_bytes
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_BYTES
);
2396 next_ptr_lbits
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_DSC_PTR_LBITS
);
2397 rx_queue_label
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_QLABEL
);
2398 rx_l4_class
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_L4_CLASS
);
2399 rx_cont
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_CONT
);
2401 if (EFX_QWORD_FIELD(*event
, ESF_DZ_RX_DROP_EVENT
))
2402 netdev_WARN(efx
->net_dev
, "saw RX_DROP_EVENT: event="
2404 EFX_QWORD_VAL(*event
));
2406 rx_queue
= efx_channel_get_rx_queue(channel
);
2408 if (unlikely(rx_queue_label
!= efx_rx_queue_index(rx_queue
)))
2409 efx_ef10_handle_rx_wrong_queue(rx_queue
, rx_queue_label
);
2411 n_descs
= ((next_ptr_lbits
- rx_queue
->removed_count
) &
2412 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH
) - 1));
2414 if (n_descs
!= rx_queue
->scatter_n
+ 1) {
2415 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2417 /* detect rx abort */
2418 if (unlikely(n_descs
== rx_queue
->scatter_n
)) {
2419 if (rx_queue
->scatter_n
== 0 || rx_bytes
!= 0)
2420 netdev_WARN(efx
->net_dev
,
2421 "invalid RX abort: scatter_n=%u event="
2423 rx_queue
->scatter_n
,
2424 EFX_QWORD_VAL(*event
));
2425 efx_ef10_handle_rx_abort(rx_queue
);
2429 /* Check that RX completion merging is valid, i.e.
2430 * the current firmware supports it and this is a
2431 * non-scattered packet.
2433 if (!(nic_data
->datapath_caps
&
2434 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN
)) ||
2435 rx_queue
->scatter_n
!= 0 || rx_cont
) {
2436 efx_ef10_handle_rx_bad_lbits(
2437 rx_queue
, next_ptr_lbits
,
2438 (rx_queue
->removed_count
+
2439 rx_queue
->scatter_n
+ 1) &
2440 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH
) - 1));
2444 /* Merged completion for multiple non-scattered packets */
2445 rx_queue
->scatter_n
= 1;
2446 rx_queue
->scatter_len
= 0;
2447 n_packets
= n_descs
;
2448 ++channel
->n_rx_merge_events
;
2449 channel
->n_rx_merge_packets
+= n_packets
;
2450 flags
|= EFX_RX_PKT_PREFIX_LEN
;
2452 ++rx_queue
->scatter_n
;
2453 rx_queue
->scatter_len
+= rx_bytes
;
2459 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_RX_ECRC_ERR
)))
2460 flags
|= EFX_RX_PKT_DISCARD
;
2462 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_RX_IPCKSUM_ERR
))) {
2463 channel
->n_rx_ip_hdr_chksum_err
+= n_packets
;
2464 } else if (unlikely(EFX_QWORD_FIELD(*event
,
2465 ESF_DZ_RX_TCPUDP_CKSUM_ERR
))) {
2466 channel
->n_rx_tcp_udp_chksum_err
+= n_packets
;
2467 } else if (rx_l4_class
== ESE_DZ_L4_CLASS_TCP
||
2468 rx_l4_class
== ESE_DZ_L4_CLASS_UDP
) {
2469 flags
|= EFX_RX_PKT_CSUMMED
;
2472 if (rx_l4_class
== ESE_DZ_L4_CLASS_TCP
)
2473 flags
|= EFX_RX_PKT_TCP
;
2475 channel
->irq_mod_score
+= 2 * n_packets
;
2477 /* Handle received packet(s) */
2478 for (i
= 0; i
< n_packets
; i
++) {
2479 efx_rx_packet(rx_queue
,
2480 rx_queue
->removed_count
& rx_queue
->ptr_mask
,
2481 rx_queue
->scatter_n
, rx_queue
->scatter_len
,
2483 rx_queue
->removed_count
+= rx_queue
->scatter_n
;
2486 rx_queue
->scatter_n
= 0;
2487 rx_queue
->scatter_len
= 0;
2493 efx_ef10_handle_tx_event(struct efx_channel
*channel
, efx_qword_t
*event
)
2495 struct efx_nic
*efx
= channel
->efx
;
2496 struct efx_tx_queue
*tx_queue
;
2497 unsigned int tx_ev_desc_ptr
;
2498 unsigned int tx_ev_q_label
;
2501 if (unlikely(ACCESS_ONCE(efx
->reset_pending
)))
2504 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_TX_DROP_EVENT
)))
2507 /* Transmit completion */
2508 tx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, ESF_DZ_TX_DESCR_INDX
);
2509 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, ESF_DZ_TX_QLABEL
);
2510 tx_queue
= efx_channel_get_tx_queue(channel
,
2511 tx_ev_q_label
% EFX_TXQ_TYPES
);
2512 tx_descs
= ((tx_ev_desc_ptr
+ 1 - tx_queue
->read_count
) &
2513 tx_queue
->ptr_mask
);
2514 efx_xmit_done(tx_queue
, tx_ev_desc_ptr
& tx_queue
->ptr_mask
);
2520 efx_ef10_handle_driver_event(struct efx_channel
*channel
, efx_qword_t
*event
)
2522 struct efx_nic
*efx
= channel
->efx
;
2525 subcode
= EFX_QWORD_FIELD(*event
, ESF_DZ_DRV_SUB_CODE
);
2528 case ESE_DZ_DRV_TIMER_EV
:
2529 case ESE_DZ_DRV_WAKE_UP_EV
:
2531 case ESE_DZ_DRV_START_UP_EV
:
2532 /* event queue init complete. ok. */
2535 netif_err(efx
, hw
, efx
->net_dev
,
2536 "channel %d unknown driver event type %d"
2537 " (data " EFX_QWORD_FMT
")\n",
2538 channel
->channel
, subcode
,
2539 EFX_QWORD_VAL(*event
));
2544 static void efx_ef10_handle_driver_generated_event(struct efx_channel
*channel
,
2547 struct efx_nic
*efx
= channel
->efx
;
2550 subcode
= EFX_QWORD_FIELD(*event
, EFX_DWORD_0
);
2554 channel
->event_test_cpu
= raw_smp_processor_id();
2556 case EFX_EF10_REFILL
:
2557 /* The queue must be empty, so we won't receive any rx
2558 * events, so efx_process_channel() won't refill the
2559 * queue. Refill it here
2561 efx_fast_push_rx_descriptors(&channel
->rx_queue
, true);
2564 netif_err(efx
, hw
, efx
->net_dev
,
2565 "channel %d unknown driver event type %u"
2566 " (data " EFX_QWORD_FMT
")\n",
2567 channel
->channel
, (unsigned) subcode
,
2568 EFX_QWORD_VAL(*event
));
2572 static int efx_ef10_ev_process(struct efx_channel
*channel
, int quota
)
2574 struct efx_nic
*efx
= channel
->efx
;
2575 efx_qword_t event
, *p_event
;
2576 unsigned int read_ptr
;
2584 read_ptr
= channel
->eventq_read_ptr
;
2587 p_event
= efx_event(channel
, read_ptr
);
2590 if (!efx_event_present(&event
))
2593 EFX_SET_QWORD(*p_event
);
2597 ev_code
= EFX_QWORD_FIELD(event
, ESF_DZ_EV_CODE
);
2599 netif_vdbg(efx
, drv
, efx
->net_dev
,
2600 "processing event on %d " EFX_QWORD_FMT
"\n",
2601 channel
->channel
, EFX_QWORD_VAL(event
));
2604 case ESE_DZ_EV_CODE_MCDI_EV
:
2605 efx_mcdi_process_event(channel
, &event
);
2607 case ESE_DZ_EV_CODE_RX_EV
:
2608 spent
+= efx_ef10_handle_rx_event(channel
, &event
);
2609 if (spent
>= quota
) {
2610 /* XXX can we split a merged event to
2611 * avoid going over-quota?
2617 case ESE_DZ_EV_CODE_TX_EV
:
2618 tx_descs
+= efx_ef10_handle_tx_event(channel
, &event
);
2619 if (tx_descs
> efx
->txq_entries
) {
2622 } else if (++spent
== quota
) {
2626 case ESE_DZ_EV_CODE_DRIVER_EV
:
2627 efx_ef10_handle_driver_event(channel
, &event
);
2628 if (++spent
== quota
)
2631 case EFX_EF10_DRVGEN_EV
:
2632 efx_ef10_handle_driver_generated_event(channel
, &event
);
2635 netif_err(efx
, hw
, efx
->net_dev
,
2636 "channel %d unknown event type %d"
2637 " (data " EFX_QWORD_FMT
")\n",
2638 channel
->channel
, ev_code
,
2639 EFX_QWORD_VAL(event
));
2644 channel
->eventq_read_ptr
= read_ptr
;
2648 static void efx_ef10_ev_read_ack(struct efx_channel
*channel
)
2650 struct efx_nic
*efx
= channel
->efx
;
2653 if (EFX_EF10_WORKAROUND_35388(efx
)) {
2654 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE
<
2655 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH
));
2656 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE
>
2657 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH
));
2659 EFX_POPULATE_DWORD_2(rptr
, ERF_DD_EVQ_IND_RPTR_FLAGS
,
2660 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH
,
2661 ERF_DD_EVQ_IND_RPTR
,
2662 (channel
->eventq_read_ptr
&
2663 channel
->eventq_mask
) >>
2664 ERF_DD_EVQ_IND_RPTR_WIDTH
);
2665 efx_writed_page(efx
, &rptr
, ER_DD_EVQ_INDIRECT
,
2667 EFX_POPULATE_DWORD_2(rptr
, ERF_DD_EVQ_IND_RPTR_FLAGS
,
2668 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW
,
2669 ERF_DD_EVQ_IND_RPTR
,
2670 channel
->eventq_read_ptr
&
2671 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH
) - 1));
2672 efx_writed_page(efx
, &rptr
, ER_DD_EVQ_INDIRECT
,
2675 EFX_POPULATE_DWORD_1(rptr
, ERF_DZ_EVQ_RPTR
,
2676 channel
->eventq_read_ptr
&
2677 channel
->eventq_mask
);
2678 efx_writed_page(efx
, &rptr
, ER_DZ_EVQ_RPTR
, channel
->channel
);
2682 static void efx_ef10_ev_test_generate(struct efx_channel
*channel
)
2684 MCDI_DECLARE_BUF(inbuf
, MC_CMD_DRIVER_EVENT_IN_LEN
);
2685 struct efx_nic
*efx
= channel
->efx
;
2689 EFX_POPULATE_QWORD_2(event
,
2690 ESF_DZ_EV_CODE
, EFX_EF10_DRVGEN_EV
,
2691 ESF_DZ_EV_DATA
, EFX_EF10_TEST
);
2693 MCDI_SET_DWORD(inbuf
, DRIVER_EVENT_IN_EVQ
, channel
->channel
);
2695 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2696 * already swapped the data to little-endian order.
2698 memcpy(MCDI_PTR(inbuf
, DRIVER_EVENT_IN_DATA
), &event
.u64
[0],
2699 sizeof(efx_qword_t
));
2701 rc
= efx_mcdi_rpc(efx
, MC_CMD_DRIVER_EVENT
, inbuf
, sizeof(inbuf
),
2710 netif_err(efx
, hw
, efx
->net_dev
, "%s: failed rc=%d\n", __func__
, rc
);
2713 void efx_ef10_handle_drain_event(struct efx_nic
*efx
)
2715 if (atomic_dec_and_test(&efx
->active_queues
))
2716 wake_up(&efx
->flush_wq
);
2718 WARN_ON(atomic_read(&efx
->active_queues
) < 0);
2721 static int efx_ef10_fini_dmaq(struct efx_nic
*efx
)
2723 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2724 struct efx_channel
*channel
;
2725 struct efx_tx_queue
*tx_queue
;
2726 struct efx_rx_queue
*rx_queue
;
2729 /* If the MC has just rebooted, the TX/RX queues will have already been
2730 * torn down, but efx->active_queues needs to be set to zero.
2732 if (nic_data
->must_realloc_vis
) {
2733 atomic_set(&efx
->active_queues
, 0);
2737 /* Do not attempt to write to the NIC during EEH recovery */
2738 if (efx
->state
!= STATE_RECOVERY
) {
2739 efx_for_each_channel(channel
, efx
) {
2740 efx_for_each_channel_rx_queue(rx_queue
, channel
)
2741 efx_ef10_rx_fini(rx_queue
);
2742 efx_for_each_channel_tx_queue(tx_queue
, channel
)
2743 efx_ef10_tx_fini(tx_queue
);
2746 wait_event_timeout(efx
->flush_wq
,
2747 atomic_read(&efx
->active_queues
) == 0,
2748 msecs_to_jiffies(EFX_MAX_FLUSH_TIME
));
2749 pending
= atomic_read(&efx
->active_queues
);
2751 netif_err(efx
, hw
, efx
->net_dev
, "failed to flush %d queues\n",
2760 static void efx_ef10_prepare_flr(struct efx_nic
*efx
)
2762 atomic_set(&efx
->active_queues
, 0);
2765 static bool efx_ef10_filter_equal(const struct efx_filter_spec
*left
,
2766 const struct efx_filter_spec
*right
)
2768 if ((left
->match_flags
^ right
->match_flags
) |
2769 ((left
->flags
^ right
->flags
) &
2770 (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_TX
)))
2773 return memcmp(&left
->outer_vid
, &right
->outer_vid
,
2774 sizeof(struct efx_filter_spec
) -
2775 offsetof(struct efx_filter_spec
, outer_vid
)) == 0;
2778 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec
*spec
)
2780 BUILD_BUG_ON(offsetof(struct efx_filter_spec
, outer_vid
) & 3);
2781 return jhash2((const u32
*)&spec
->outer_vid
,
2782 (sizeof(struct efx_filter_spec
) -
2783 offsetof(struct efx_filter_spec
, outer_vid
)) / 4,
2785 /* XXX should we randomise the initval? */
2788 /* Decide whether a filter should be exclusive or else should allow
2789 * delivery to additional recipients. Currently we decide that
2790 * filters for specific local unicast MAC and IP addresses are
2793 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec
*spec
)
2795 if (spec
->match_flags
& EFX_FILTER_MATCH_LOC_MAC
&&
2796 !is_multicast_ether_addr(spec
->loc_mac
))
2799 if ((spec
->match_flags
&
2800 (EFX_FILTER_MATCH_ETHER_TYPE
| EFX_FILTER_MATCH_LOC_HOST
)) ==
2801 (EFX_FILTER_MATCH_ETHER_TYPE
| EFX_FILTER_MATCH_LOC_HOST
)) {
2802 if (spec
->ether_type
== htons(ETH_P_IP
) &&
2803 !ipv4_is_multicast(spec
->loc_host
[0]))
2805 if (spec
->ether_type
== htons(ETH_P_IPV6
) &&
2806 ((const u8
*)spec
->loc_host
)[0] != 0xff)
2813 static struct efx_filter_spec
*
2814 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table
*table
,
2815 unsigned int filter_idx
)
2817 return (struct efx_filter_spec
*)(table
->entry
[filter_idx
].spec
&
2818 ~EFX_EF10_FILTER_FLAGS
);
2822 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table
*table
,
2823 unsigned int filter_idx
)
2825 return table
->entry
[filter_idx
].spec
& EFX_EF10_FILTER_FLAGS
;
2829 efx_ef10_filter_set_entry(struct efx_ef10_filter_table
*table
,
2830 unsigned int filter_idx
,
2831 const struct efx_filter_spec
*spec
,
2834 table
->entry
[filter_idx
].spec
= (unsigned long)spec
| flags
;
2837 static void efx_ef10_filter_push_prep(struct efx_nic
*efx
,
2838 const struct efx_filter_spec
*spec
,
2839 efx_dword_t
*inbuf
, u64 handle
,
2842 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2844 memset(inbuf
, 0, MC_CMD_FILTER_OP_IN_LEN
);
2847 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
2848 MC_CMD_FILTER_OP_IN_OP_REPLACE
);
2849 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
, handle
);
2851 u32 match_fields
= 0;
2853 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
2854 efx_ef10_filter_is_exclusive(spec
) ?
2855 MC_CMD_FILTER_OP_IN_OP_INSERT
:
2856 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE
);
2858 /* Convert match flags and values. Unlike almost
2859 * everything else in MCDI, these fields are in
2860 * network byte order.
2862 if (spec
->match_flags
& EFX_FILTER_MATCH_LOC_MAC_IG
)
2864 is_multicast_ether_addr(spec
->loc_mac
) ?
2865 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN
:
2866 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN
;
2867 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2868 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2870 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2871 mcdi_field ## _LBN; \
2873 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2874 sizeof(spec->gen_field)); \
2875 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2876 &spec->gen_field, sizeof(spec->gen_field)); \
2878 COPY_FIELD(REM_HOST
, rem_host
, SRC_IP
);
2879 COPY_FIELD(LOC_HOST
, loc_host
, DST_IP
);
2880 COPY_FIELD(REM_MAC
, rem_mac
, SRC_MAC
);
2881 COPY_FIELD(REM_PORT
, rem_port
, SRC_PORT
);
2882 COPY_FIELD(LOC_MAC
, loc_mac
, DST_MAC
);
2883 COPY_FIELD(LOC_PORT
, loc_port
, DST_PORT
);
2884 COPY_FIELD(ETHER_TYPE
, ether_type
, ETHER_TYPE
);
2885 COPY_FIELD(INNER_VID
, inner_vid
, INNER_VLAN
);
2886 COPY_FIELD(OUTER_VID
, outer_vid
, OUTER_VLAN
);
2887 COPY_FIELD(IP_PROTO
, ip_proto
, IP_PROTO
);
2889 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_MATCH_FIELDS
,
2893 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_PORT_ID
, nic_data
->vport_id
);
2894 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_DEST
,
2895 spec
->dmaq_id
== EFX_FILTER_RX_DMAQ_ID_DROP
?
2896 MC_CMD_FILTER_OP_IN_RX_DEST_DROP
:
2897 MC_CMD_FILTER_OP_IN_RX_DEST_HOST
);
2898 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_TX_DOMAIN
, 0);
2899 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_TX_DEST
,
2900 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT
);
2901 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_QUEUE
,
2902 spec
->dmaq_id
== EFX_FILTER_RX_DMAQ_ID_DROP
?
2904 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_MODE
,
2905 (spec
->flags
& EFX_FILTER_FLAG_RX_RSS
) ?
2906 MC_CMD_FILTER_OP_IN_RX_MODE_RSS
:
2907 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE
);
2908 if (spec
->flags
& EFX_FILTER_FLAG_RX_RSS
)
2909 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_CONTEXT
,
2910 spec
->rss_context
!=
2911 EFX_FILTER_RSS_CONTEXT_DEFAULT
?
2912 spec
->rss_context
: nic_data
->rx_rss_context
);
2915 static int efx_ef10_filter_push(struct efx_nic
*efx
,
2916 const struct efx_filter_spec
*spec
,
2917 u64
*handle
, bool replacing
)
2919 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
2920 MCDI_DECLARE_BUF(outbuf
, MC_CMD_FILTER_OP_OUT_LEN
);
2923 efx_ef10_filter_push_prep(efx
, spec
, inbuf
, *handle
, replacing
);
2924 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
2925 outbuf
, sizeof(outbuf
), NULL
);
2927 *handle
= MCDI_QWORD(outbuf
, FILTER_OP_OUT_HANDLE
);
2929 rc
= -EBUSY
; /* to match efx_farch_filter_insert() */
2933 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table
*table
,
2934 enum efx_filter_match_flags match_flags
)
2936 unsigned int match_pri
;
2939 match_pri
< table
->rx_match_count
;
2941 if (table
->rx_match_flags
[match_pri
] == match_flags
)
2944 return -EPROTONOSUPPORT
;
2947 static s32
efx_ef10_filter_insert(struct efx_nic
*efx
,
2948 struct efx_filter_spec
*spec
,
2951 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
2952 DECLARE_BITMAP(mc_rem_map
, EFX_EF10_FILTER_SEARCH_LIMIT
);
2953 struct efx_filter_spec
*saved_spec
;
2954 unsigned int match_pri
, hash
;
2955 unsigned int priv_flags
;
2956 bool replacing
= false;
2962 /* For now, only support RX filters */
2963 if ((spec
->flags
& (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_TX
)) !=
2967 rc
= efx_ef10_filter_rx_match_pri(table
, spec
->match_flags
);
2972 hash
= efx_ef10_filter_hash(spec
);
2973 is_mc_recip
= efx_filter_is_mc_recipient(spec
);
2975 bitmap_zero(mc_rem_map
, EFX_EF10_FILTER_SEARCH_LIMIT
);
2977 /* Find any existing filters with the same match tuple or
2978 * else a free slot to insert at. If any of them are busy,
2979 * we have to wait and retry.
2982 unsigned int depth
= 1;
2985 spin_lock_bh(&efx
->filter_lock
);
2988 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
2989 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
2994 } else if (efx_ef10_filter_equal(spec
, saved_spec
)) {
2995 if (table
->entry
[i
].spec
&
2996 EFX_EF10_FILTER_FLAG_BUSY
)
2998 if (spec
->priority
< saved_spec
->priority
&&
2999 spec
->priority
!= EFX_FILTER_PRI_AUTO
) {
3004 /* This is the only one */
3005 if (spec
->priority
==
3006 saved_spec
->priority
&&
3013 } else if (spec
->priority
>
3014 saved_spec
->priority
||
3016 saved_spec
->priority
&&
3021 __set_bit(depth
, mc_rem_map
);
3025 /* Once we reach the maximum search depth, use
3026 * the first suitable slot or return -EBUSY if
3029 if (depth
== EFX_EF10_FILTER_SEARCH_LIMIT
) {
3030 if (ins_index
< 0) {
3040 prepare_to_wait(&table
->waitq
, &wait
, TASK_UNINTERRUPTIBLE
);
3041 spin_unlock_bh(&efx
->filter_lock
);
3046 /* Create a software table entry if necessary, and mark it
3047 * busy. We might yet fail to insert, but any attempt to
3048 * insert a conflicting filter while we're waiting for the
3049 * firmware must find the busy entry.
3051 saved_spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3053 if (spec
->priority
== EFX_FILTER_PRI_AUTO
&&
3054 saved_spec
->priority
>= EFX_FILTER_PRI_AUTO
) {
3055 /* Just make sure it won't be removed */
3056 if (saved_spec
->priority
> EFX_FILTER_PRI_AUTO
)
3057 saved_spec
->flags
|= EFX_FILTER_FLAG_RX_OVER_AUTO
;
3058 table
->entry
[ins_index
].spec
&=
3059 ~EFX_EF10_FILTER_FLAG_AUTO_OLD
;
3064 priv_flags
= efx_ef10_filter_entry_flags(table
, ins_index
);
3066 saved_spec
= kmalloc(sizeof(*spec
), GFP_ATOMIC
);
3071 *saved_spec
= *spec
;
3074 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
,
3075 priv_flags
| EFX_EF10_FILTER_FLAG_BUSY
);
3077 /* Mark lower-priority multicast recipients busy prior to removal */
3079 unsigned int depth
, i
;
3081 for (depth
= 0; depth
< EFX_EF10_FILTER_SEARCH_LIMIT
; depth
++) {
3082 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3083 if (test_bit(depth
, mc_rem_map
))
3084 table
->entry
[i
].spec
|=
3085 EFX_EF10_FILTER_FLAG_BUSY
;
3089 spin_unlock_bh(&efx
->filter_lock
);
3091 rc
= efx_ef10_filter_push(efx
, spec
, &table
->entry
[ins_index
].handle
,
3094 /* Finalise the software table entry */
3095 spin_lock_bh(&efx
->filter_lock
);
3098 /* Update the fields that may differ */
3099 if (saved_spec
->priority
== EFX_FILTER_PRI_AUTO
)
3100 saved_spec
->flags
|=
3101 EFX_FILTER_FLAG_RX_OVER_AUTO
;
3102 saved_spec
->priority
= spec
->priority
;
3103 saved_spec
->flags
&= EFX_FILTER_FLAG_RX_OVER_AUTO
;
3104 saved_spec
->flags
|= spec
->flags
;
3105 saved_spec
->rss_context
= spec
->rss_context
;
3106 saved_spec
->dmaq_id
= spec
->dmaq_id
;
3108 } else if (!replacing
) {
3112 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
, priv_flags
);
3114 /* Remove and finalise entries for lower-priority multicast
3118 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3119 unsigned int depth
, i
;
3121 memset(inbuf
, 0, sizeof(inbuf
));
3123 for (depth
= 0; depth
< EFX_EF10_FILTER_SEARCH_LIMIT
; depth
++) {
3124 if (!test_bit(depth
, mc_rem_map
))
3127 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3128 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3129 priv_flags
= efx_ef10_filter_entry_flags(table
, i
);
3132 spin_unlock_bh(&efx
->filter_lock
);
3133 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3134 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
3135 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3136 table
->entry
[i
].handle
);
3137 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
,
3138 inbuf
, sizeof(inbuf
),
3140 spin_lock_bh(&efx
->filter_lock
);
3148 priv_flags
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3150 efx_ef10_filter_set_entry(table
, i
, saved_spec
,
3155 /* If successful, return the inserted filter ID */
3157 rc
= match_pri
* HUNT_FILTER_TBL_ROWS
+ ins_index
;
3159 wake_up_all(&table
->waitq
);
3161 spin_unlock_bh(&efx
->filter_lock
);
3162 finish_wait(&table
->waitq
, &wait
);
3166 static void efx_ef10_filter_update_rx_scatter(struct efx_nic
*efx
)
3168 /* no need to do anything here on EF10 */
3172 * If !by_index, remove by ID
3173 * If by_index, remove by index
3174 * Filter ID may come from userland and must be range-checked.
3176 static int efx_ef10_filter_remove_internal(struct efx_nic
*efx
,
3177 unsigned int priority_mask
,
3178 u32 filter_id
, bool by_index
)
3180 unsigned int filter_idx
= filter_id
% HUNT_FILTER_TBL_ROWS
;
3181 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3182 MCDI_DECLARE_BUF(inbuf
,
3183 MC_CMD_FILTER_OP_IN_HANDLE_OFST
+
3184 MC_CMD_FILTER_OP_IN_HANDLE_LEN
);
3185 struct efx_filter_spec
*spec
;
3189 /* Find the software table entry and mark it busy. Don't
3190 * remove it yet; any attempt to update while we're waiting
3191 * for the firmware must find the busy entry.
3194 spin_lock_bh(&efx
->filter_lock
);
3195 if (!(table
->entry
[filter_idx
].spec
&
3196 EFX_EF10_FILTER_FLAG_BUSY
))
3198 prepare_to_wait(&table
->waitq
, &wait
, TASK_UNINTERRUPTIBLE
);
3199 spin_unlock_bh(&efx
->filter_lock
);
3203 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3206 efx_ef10_filter_rx_match_pri(table
, spec
->match_flags
) !=
3207 filter_id
/ HUNT_FILTER_TBL_ROWS
)) {
3212 if (spec
->flags
& EFX_FILTER_FLAG_RX_OVER_AUTO
&&
3213 priority_mask
== (1U << EFX_FILTER_PRI_AUTO
)) {
3214 /* Just remove flags */
3215 spec
->flags
&= ~EFX_FILTER_FLAG_RX_OVER_AUTO
;
3216 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_AUTO_OLD
;
3221 if (!(priority_mask
& (1U << spec
->priority
))) {
3226 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
3227 spin_unlock_bh(&efx
->filter_lock
);
3229 if (spec
->flags
& EFX_FILTER_FLAG_RX_OVER_AUTO
) {
3230 /* Reset to an automatic filter */
3232 struct efx_filter_spec new_spec
= *spec
;
3234 new_spec
.priority
= EFX_FILTER_PRI_AUTO
;
3235 new_spec
.flags
= (EFX_FILTER_FLAG_RX
|
3236 EFX_FILTER_FLAG_RX_RSS
);
3237 new_spec
.dmaq_id
= 0;
3238 new_spec
.rss_context
= EFX_FILTER_RSS_CONTEXT_DEFAULT
;
3239 rc
= efx_ef10_filter_push(efx
, &new_spec
,
3240 &table
->entry
[filter_idx
].handle
,
3243 spin_lock_bh(&efx
->filter_lock
);
3247 /* Really remove the filter */
3249 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3250 efx_ef10_filter_is_exclusive(spec
) ?
3251 MC_CMD_FILTER_OP_IN_OP_REMOVE
:
3252 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
3253 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3254 table
->entry
[filter_idx
].handle
);
3255 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
,
3256 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
3258 spin_lock_bh(&efx
->filter_lock
);
3261 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
3265 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3266 wake_up_all(&table
->waitq
);
3268 spin_unlock_bh(&efx
->filter_lock
);
3269 finish_wait(&table
->waitq
, &wait
);
3273 static int efx_ef10_filter_remove_safe(struct efx_nic
*efx
,
3274 enum efx_filter_priority priority
,
3277 return efx_ef10_filter_remove_internal(efx
, 1U << priority
,
3281 static u32
efx_ef10_filter_get_unsafe_id(struct efx_nic
*efx
, u32 filter_id
)
3283 return filter_id
% HUNT_FILTER_TBL_ROWS
;
3286 static int efx_ef10_filter_remove_unsafe(struct efx_nic
*efx
,
3287 enum efx_filter_priority priority
,
3290 return efx_ef10_filter_remove_internal(efx
, 1U << priority
,
3294 static int efx_ef10_filter_get_safe(struct efx_nic
*efx
,
3295 enum efx_filter_priority priority
,
3296 u32 filter_id
, struct efx_filter_spec
*spec
)
3298 unsigned int filter_idx
= filter_id
% HUNT_FILTER_TBL_ROWS
;
3299 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3300 const struct efx_filter_spec
*saved_spec
;
3303 spin_lock_bh(&efx
->filter_lock
);
3304 saved_spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3305 if (saved_spec
&& saved_spec
->priority
== priority
&&
3306 efx_ef10_filter_rx_match_pri(table
, saved_spec
->match_flags
) ==
3307 filter_id
/ HUNT_FILTER_TBL_ROWS
) {
3308 *spec
= *saved_spec
;
3313 spin_unlock_bh(&efx
->filter_lock
);
3317 static int efx_ef10_filter_clear_rx(struct efx_nic
*efx
,
3318 enum efx_filter_priority priority
)
3320 unsigned int priority_mask
;
3324 priority_mask
= (((1U << (priority
+ 1)) - 1) &
3325 ~(1U << EFX_FILTER_PRI_AUTO
));
3327 for (i
= 0; i
< HUNT_FILTER_TBL_ROWS
; i
++) {
3328 rc
= efx_ef10_filter_remove_internal(efx
, priority_mask
,
3330 if (rc
&& rc
!= -ENOENT
)
3337 static u32
efx_ef10_filter_count_rx_used(struct efx_nic
*efx
,
3338 enum efx_filter_priority priority
)
3340 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3341 unsigned int filter_idx
;
3344 spin_lock_bh(&efx
->filter_lock
);
3345 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3346 if (table
->entry
[filter_idx
].spec
&&
3347 efx_ef10_filter_entry_spec(table
, filter_idx
)->priority
==
3351 spin_unlock_bh(&efx
->filter_lock
);
3355 static u32
efx_ef10_filter_get_rx_id_limit(struct efx_nic
*efx
)
3357 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3359 return table
->rx_match_count
* HUNT_FILTER_TBL_ROWS
;
3362 static s32
efx_ef10_filter_get_rx_ids(struct efx_nic
*efx
,
3363 enum efx_filter_priority priority
,
3366 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3367 struct efx_filter_spec
*spec
;
3368 unsigned int filter_idx
;
3371 spin_lock_bh(&efx
->filter_lock
);
3372 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3373 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3374 if (spec
&& spec
->priority
== priority
) {
3375 if (count
== size
) {
3379 buf
[count
++] = (efx_ef10_filter_rx_match_pri(
3380 table
, spec
->match_flags
) *
3381 HUNT_FILTER_TBL_ROWS
+
3385 spin_unlock_bh(&efx
->filter_lock
);
3389 #ifdef CONFIG_RFS_ACCEL
3391 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete
;
3393 static s32
efx_ef10_filter_rfs_insert(struct efx_nic
*efx
,
3394 struct efx_filter_spec
*spec
)
3396 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3397 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3398 struct efx_filter_spec
*saved_spec
;
3399 unsigned int hash
, i
, depth
= 1;
3400 bool replacing
= false;
3405 /* Must be an RX filter without RSS and not for a multicast
3406 * destination address (RFS only works for connected sockets).
3407 * These restrictions allow us to pass only a tiny amount of
3408 * data through to the completion function.
3410 EFX_WARN_ON_PARANOID(spec
->flags
!=
3411 (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_RX_SCATTER
));
3412 EFX_WARN_ON_PARANOID(spec
->priority
!= EFX_FILTER_PRI_HINT
);
3413 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec
));
3415 hash
= efx_ef10_filter_hash(spec
);
3417 spin_lock_bh(&efx
->filter_lock
);
3419 /* Find any existing filter with the same match tuple or else
3420 * a free slot to insert at. If an existing filter is busy,
3421 * we have to give up.
3424 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3425 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3430 } else if (efx_ef10_filter_equal(spec
, saved_spec
)) {
3431 if (table
->entry
[i
].spec
& EFX_EF10_FILTER_FLAG_BUSY
) {
3435 if (spec
->priority
< saved_spec
->priority
) {
3443 /* Once we reach the maximum search depth, use the
3444 * first suitable slot or return -EBUSY if there was
3447 if (depth
== EFX_EF10_FILTER_SEARCH_LIMIT
) {
3448 if (ins_index
< 0) {
3458 /* Create a software table entry if necessary, and mark it
3459 * busy. We might yet fail to insert, but any attempt to
3460 * insert a conflicting filter while we're waiting for the
3461 * firmware must find the busy entry.
3463 saved_spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3467 saved_spec
= kmalloc(sizeof(*spec
), GFP_ATOMIC
);
3472 *saved_spec
= *spec
;
3474 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
,
3475 EFX_EF10_FILTER_FLAG_BUSY
);
3477 spin_unlock_bh(&efx
->filter_lock
);
3479 /* Pack up the variables needed on completion */
3480 cookie
= replacing
<< 31 | ins_index
<< 16 | spec
->dmaq_id
;
3482 efx_ef10_filter_push_prep(efx
, spec
, inbuf
,
3483 table
->entry
[ins_index
].handle
, replacing
);
3484 efx_mcdi_rpc_async(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
3485 MC_CMD_FILTER_OP_OUT_LEN
,
3486 efx_ef10_filter_rfs_insert_complete
, cookie
);
3491 spin_unlock_bh(&efx
->filter_lock
);
3496 efx_ef10_filter_rfs_insert_complete(struct efx_nic
*efx
, unsigned long cookie
,
3497 int rc
, efx_dword_t
*outbuf
,
3498 size_t outlen_actual
)
3500 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3501 unsigned int ins_index
, dmaq_id
;
3502 struct efx_filter_spec
*spec
;
3505 /* Unpack the cookie */
3506 replacing
= cookie
>> 31;
3507 ins_index
= (cookie
>> 16) & (HUNT_FILTER_TBL_ROWS
- 1);
3508 dmaq_id
= cookie
& 0xffff;
3510 spin_lock_bh(&efx
->filter_lock
);
3511 spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3513 table
->entry
[ins_index
].handle
=
3514 MCDI_QWORD(outbuf
, FILTER_OP_OUT_HANDLE
);
3516 spec
->dmaq_id
= dmaq_id
;
3517 } else if (!replacing
) {
3521 efx_ef10_filter_set_entry(table
, ins_index
, spec
, 0);
3522 spin_unlock_bh(&efx
->filter_lock
);
3524 wake_up_all(&table
->waitq
);
3528 efx_ef10_filter_rfs_expire_complete(struct efx_nic
*efx
,
3529 unsigned long filter_idx
,
3530 int rc
, efx_dword_t
*outbuf
,
3531 size_t outlen_actual
);
3533 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic
*efx
, u32 flow_id
,
3534 unsigned int filter_idx
)
3536 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3537 struct efx_filter_spec
*spec
=
3538 efx_ef10_filter_entry_spec(table
, filter_idx
);
3539 MCDI_DECLARE_BUF(inbuf
,
3540 MC_CMD_FILTER_OP_IN_HANDLE_OFST
+
3541 MC_CMD_FILTER_OP_IN_HANDLE_LEN
);
3544 (table
->entry
[filter_idx
].spec
& EFX_EF10_FILTER_FLAG_BUSY
) ||
3545 spec
->priority
!= EFX_FILTER_PRI_HINT
||
3546 !rps_may_expire_flow(efx
->net_dev
, spec
->dmaq_id
,
3547 flow_id
, filter_idx
))
3550 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3551 MC_CMD_FILTER_OP_IN_OP_REMOVE
);
3552 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3553 table
->entry
[filter_idx
].handle
);
3554 if (efx_mcdi_rpc_async(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
), 0,
3555 efx_ef10_filter_rfs_expire_complete
, filter_idx
))
3558 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
3563 efx_ef10_filter_rfs_expire_complete(struct efx_nic
*efx
,
3564 unsigned long filter_idx
,
3565 int rc
, efx_dword_t
*outbuf
,
3566 size_t outlen_actual
)
3568 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3569 struct efx_filter_spec
*spec
=
3570 efx_ef10_filter_entry_spec(table
, filter_idx
);
3572 spin_lock_bh(&efx
->filter_lock
);
3575 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
3577 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3578 wake_up_all(&table
->waitq
);
3579 spin_unlock_bh(&efx
->filter_lock
);
3582 #endif /* CONFIG_RFS_ACCEL */
3584 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags
)
3586 int match_flags
= 0;
3588 #define MAP_FLAG(gen_flag, mcdi_field) { \
3589 u32 old_mcdi_flags = mcdi_flags; \
3590 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3591 mcdi_field ## _LBN); \
3592 if (mcdi_flags != old_mcdi_flags) \
3593 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3595 MAP_FLAG(LOC_MAC_IG
, UNKNOWN_UCAST_DST
);
3596 MAP_FLAG(LOC_MAC_IG
, UNKNOWN_MCAST_DST
);
3597 MAP_FLAG(REM_HOST
, SRC_IP
);
3598 MAP_FLAG(LOC_HOST
, DST_IP
);
3599 MAP_FLAG(REM_MAC
, SRC_MAC
);
3600 MAP_FLAG(REM_PORT
, SRC_PORT
);
3601 MAP_FLAG(LOC_MAC
, DST_MAC
);
3602 MAP_FLAG(LOC_PORT
, DST_PORT
);
3603 MAP_FLAG(ETHER_TYPE
, ETHER_TYPE
);
3604 MAP_FLAG(INNER_VID
, INNER_VLAN
);
3605 MAP_FLAG(OUTER_VID
, OUTER_VLAN
);
3606 MAP_FLAG(IP_PROTO
, IP_PROTO
);
3609 /* Did we map them all? */
3616 static int efx_ef10_filter_table_probe(struct efx_nic
*efx
)
3618 MCDI_DECLARE_BUF(inbuf
, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN
);
3619 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX
);
3620 unsigned int pd_match_pri
, pd_match_count
;
3621 struct efx_ef10_filter_table
*table
;
3625 table
= kzalloc(sizeof(*table
), GFP_KERNEL
);
3629 /* Find out which RX filter types are supported, and their priorities */
3630 MCDI_SET_DWORD(inbuf
, GET_PARSER_DISP_INFO_IN_OP
,
3631 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES
);
3632 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_PARSER_DISP_INFO
,
3633 inbuf
, sizeof(inbuf
), outbuf
, sizeof(outbuf
),
3637 pd_match_count
= MCDI_VAR_ARRAY_LEN(
3638 outlen
, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES
);
3639 table
->rx_match_count
= 0;
3641 for (pd_match_pri
= 0; pd_match_pri
< pd_match_count
; pd_match_pri
++) {
3645 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES
,
3647 rc
= efx_ef10_filter_match_flags_from_mcdi(mcdi_flags
);
3649 netif_dbg(efx
, probe
, efx
->net_dev
,
3650 "%s: fw flags %#x pri %u not supported in driver\n",
3651 __func__
, mcdi_flags
, pd_match_pri
);
3653 netif_dbg(efx
, probe
, efx
->net_dev
,
3654 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3655 __func__
, mcdi_flags
, pd_match_pri
,
3656 rc
, table
->rx_match_count
);
3657 table
->rx_match_flags
[table
->rx_match_count
++] = rc
;
3661 table
->entry
= vzalloc(HUNT_FILTER_TBL_ROWS
* sizeof(*table
->entry
));
3662 if (!table
->entry
) {
3667 table
->ucdef_id
= EFX_EF10_FILTER_ID_INVALID
;
3668 table
->bcast_id
= EFX_EF10_FILTER_ID_INVALID
;
3669 table
->mcdef_id
= EFX_EF10_FILTER_ID_INVALID
;
3671 efx
->filter_state
= table
;
3672 init_waitqueue_head(&table
->waitq
);
3680 /* Caller must hold efx->filter_sem for read if race against
3681 * efx_ef10_filter_table_remove() is possible
3683 static void efx_ef10_filter_table_restore(struct efx_nic
*efx
)
3685 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3686 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
3687 struct efx_filter_spec
*spec
;
3688 unsigned int filter_idx
;
3689 bool failed
= false;
3692 WARN_ON(!rwsem_is_locked(&efx
->filter_sem
));
3694 if (!nic_data
->must_restore_filters
)
3700 spin_lock_bh(&efx
->filter_lock
);
3702 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3703 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3707 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
3708 spin_unlock_bh(&efx
->filter_lock
);
3710 rc
= efx_ef10_filter_push(efx
, spec
,
3711 &table
->entry
[filter_idx
].handle
,
3716 spin_lock_bh(&efx
->filter_lock
);
3719 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
3721 table
->entry
[filter_idx
].spec
&=
3722 ~EFX_EF10_FILTER_FLAG_BUSY
;
3726 spin_unlock_bh(&efx
->filter_lock
);
3729 netif_err(efx
, hw
, efx
->net_dev
,
3730 "unable to restore all filters\n");
3732 nic_data
->must_restore_filters
= false;
3735 /* Caller must hold efx->filter_sem for write */
3736 static void efx_ef10_filter_table_remove(struct efx_nic
*efx
)
3738 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3739 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3740 struct efx_filter_spec
*spec
;
3741 unsigned int filter_idx
;
3744 efx
->filter_state
= NULL
;
3748 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3749 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3753 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3754 efx_ef10_filter_is_exclusive(spec
) ?
3755 MC_CMD_FILTER_OP_IN_OP_REMOVE
:
3756 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
3757 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3758 table
->entry
[filter_idx
].handle
);
3759 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
3762 netdev_WARN(efx
->net_dev
,
3763 "filter_idx=%#x handle=%#llx\n",
3765 table
->entry
[filter_idx
].handle
);
3769 vfree(table
->entry
);
3773 #define EFX_EF10_FILTER_DO_MARK_OLD(id) \
3774 if (id != EFX_EF10_FILTER_ID_INVALID) { \
3775 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \
3776 WARN_ON(!table->entry[filter_idx].spec); \
3777 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; \
3779 static void efx_ef10_filter_mark_old(struct efx_nic
*efx
)
3781 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3782 unsigned int filter_idx
, i
;
3787 /* Mark old filters that may need to be removed */
3788 spin_lock_bh(&efx
->filter_lock
);
3789 for (i
= 0; i
< table
->dev_uc_count
; i
++)
3790 EFX_EF10_FILTER_DO_MARK_OLD(table
->dev_uc_list
[i
].id
);
3791 for (i
= 0; i
< table
->dev_mc_count
; i
++)
3792 EFX_EF10_FILTER_DO_MARK_OLD(table
->dev_mc_list
[i
].id
);
3793 EFX_EF10_FILTER_DO_MARK_OLD(table
->ucdef_id
);
3794 EFX_EF10_FILTER_DO_MARK_OLD(table
->bcast_id
);
3795 EFX_EF10_FILTER_DO_MARK_OLD(table
->mcdef_id
);
3796 spin_unlock_bh(&efx
->filter_lock
);
3798 #undef EFX_EF10_FILTER_DO_MARK_OLD
3800 static void efx_ef10_filter_uc_addr_list(struct efx_nic
*efx
, bool *promisc
)
3802 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3803 struct net_device
*net_dev
= efx
->net_dev
;
3804 struct netdev_hw_addr
*uc
;
3808 table
->ucdef_id
= EFX_EF10_FILTER_ID_INVALID
;
3809 addr_count
= netdev_uc_count(net_dev
);
3810 if (net_dev
->flags
& IFF_PROMISC
)
3812 table
->dev_uc_count
= 1 + addr_count
;
3813 ether_addr_copy(table
->dev_uc_list
[0].addr
, net_dev
->dev_addr
);
3815 netdev_for_each_uc_addr(uc
, net_dev
) {
3816 if (i
>= EFX_EF10_FILTER_DEV_UC_MAX
) {
3820 ether_addr_copy(table
->dev_uc_list
[i
].addr
, uc
->addr
);
3821 table
->dev_uc_list
[i
].id
= EFX_EF10_FILTER_ID_INVALID
;
3826 static void efx_ef10_filter_mc_addr_list(struct efx_nic
*efx
, bool *promisc
)
3828 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3829 struct net_device
*net_dev
= efx
->net_dev
;
3830 struct netdev_hw_addr
*mc
;
3831 unsigned int i
, addr_count
;
3833 table
->mcdef_id
= EFX_EF10_FILTER_ID_INVALID
;
3834 table
->bcast_id
= EFX_EF10_FILTER_ID_INVALID
;
3835 if (net_dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))
3838 addr_count
= netdev_mc_count(net_dev
);
3840 netdev_for_each_mc_addr(mc
, net_dev
) {
3841 if (i
>= EFX_EF10_FILTER_DEV_MC_MAX
) {
3845 ether_addr_copy(table
->dev_mc_list
[i
].addr
, mc
->addr
);
3846 table
->dev_mc_list
[i
].id
= EFX_EF10_FILTER_ID_INVALID
;
3850 table
->dev_mc_count
= i
;
3853 static int efx_ef10_filter_insert_addr_list(struct efx_nic
*efx
,
3854 bool multicast
, bool rollback
)
3856 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3857 struct efx_ef10_dev_addr
*addr_list
;
3858 struct efx_filter_spec spec
;
3865 addr_list
= table
->dev_mc_list
;
3866 addr_count
= table
->dev_mc_count
;
3868 addr_list
= table
->dev_uc_list
;
3869 addr_count
= table
->dev_uc_count
;
3872 /* Insert/renew filters */
3873 for (i
= 0; i
< addr_count
; i
++) {
3874 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
3875 EFX_FILTER_FLAG_RX_RSS
,
3877 efx_filter_set_eth_local(&spec
, EFX_FILTER_VID_UNSPEC
,
3879 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
3882 netif_info(efx
, drv
, efx
->net_dev
,
3883 "efx_ef10_filter_insert failed rc=%d\n",
3885 /* Fall back to promiscuous */
3886 for (j
= 0; j
< i
; j
++) {
3887 if (addr_list
[j
].id
== EFX_EF10_FILTER_ID_INVALID
)
3889 efx_ef10_filter_remove_unsafe(
3890 efx
, EFX_FILTER_PRI_AUTO
,
3892 addr_list
[j
].id
= EFX_EF10_FILTER_ID_INVALID
;
3896 /* mark as not inserted, and carry on */
3897 rc
= EFX_EF10_FILTER_ID_INVALID
;
3900 addr_list
[i
].id
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
3903 if (multicast
&& rollback
) {
3904 /* Also need an Ethernet broadcast filter */
3905 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
3906 EFX_FILTER_FLAG_RX_RSS
,
3908 eth_broadcast_addr(baddr
);
3909 efx_filter_set_eth_local(&spec
, EFX_FILTER_VID_UNSPEC
, baddr
);
3910 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
3912 netif_warn(efx
, drv
, efx
->net_dev
,
3913 "Broadcast filter insert failed rc=%d\n", rc
);
3914 /* Fall back to promiscuous */
3915 for (j
= 0; j
< i
; j
++) {
3916 if (addr_list
[j
].id
== EFX_EF10_FILTER_ID_INVALID
)
3918 efx_ef10_filter_remove_unsafe(
3919 efx
, EFX_FILTER_PRI_AUTO
,
3921 addr_list
[j
].id
= EFX_EF10_FILTER_ID_INVALID
;
3925 table
->bcast_id
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
3932 static int efx_ef10_filter_insert_def(struct efx_nic
*efx
, bool multicast
,
3935 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3936 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
3937 struct efx_filter_spec spec
;
3941 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
3942 EFX_FILTER_FLAG_RX_RSS
,
3946 efx_filter_set_mc_def(&spec
);
3948 efx_filter_set_uc_def(&spec
);
3950 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
3952 netif_warn(efx
, drv
, efx
->net_dev
,
3953 "%scast mismatch filter insert failed rc=%d\n",
3954 multicast
? "Multi" : "Uni", rc
);
3955 } else if (multicast
) {
3956 table
->mcdef_id
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
3957 if (!nic_data
->workaround_26807
) {
3958 /* Also need an Ethernet broadcast filter */
3959 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
3960 EFX_FILTER_FLAG_RX_RSS
,
3962 eth_broadcast_addr(baddr
);
3963 efx_filter_set_eth_local(&spec
, EFX_FILTER_VID_UNSPEC
,
3965 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
3967 netif_warn(efx
, drv
, efx
->net_dev
,
3968 "Broadcast filter insert failed rc=%d\n",
3971 /* Roll back the mc_def filter */
3972 efx_ef10_filter_remove_unsafe(
3973 efx
, EFX_FILTER_PRI_AUTO
,
3975 table
->mcdef_id
= EFX_EF10_FILTER_ID_INVALID
;
3979 table
->bcast_id
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
3984 table
->ucdef_id
= rc
;
3990 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
3991 * flag or removes these filters, we don't need to hold the filter_lock while
3992 * scanning for these filters.
3994 static void efx_ef10_filter_remove_old(struct efx_nic
*efx
)
3996 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3997 bool remove_failed
= false;
4000 for (i
= 0; i
< HUNT_FILTER_TBL_ROWS
; i
++) {
4001 if (ACCESS_ONCE(table
->entry
[i
].spec
) &
4002 EFX_EF10_FILTER_FLAG_AUTO_OLD
) {
4003 if (efx_ef10_filter_remove_internal(
4004 efx
, 1U << EFX_FILTER_PRI_AUTO
,
4006 remove_failed
= true;
4009 WARN_ON(remove_failed
);
4012 static int efx_ef10_vport_set_mac_address(struct efx_nic
*efx
)
4014 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4015 u8 mac_old
[ETH_ALEN
];
4018 /* Only reconfigure a PF-created vport */
4019 if (is_zero_ether_addr(nic_data
->vport_mac
))
4022 efx_device_detach_sync(efx
);
4023 efx_net_stop(efx
->net_dev
);
4024 down_write(&efx
->filter_sem
);
4025 efx_ef10_filter_table_remove(efx
);
4026 up_write(&efx
->filter_sem
);
4028 rc
= efx_ef10_vadaptor_free(efx
, nic_data
->vport_id
);
4030 goto restore_filters
;
4032 ether_addr_copy(mac_old
, nic_data
->vport_mac
);
4033 rc
= efx_ef10_vport_del_mac(efx
, nic_data
->vport_id
,
4034 nic_data
->vport_mac
);
4036 goto restore_vadaptor
;
4038 rc
= efx_ef10_vport_add_mac(efx
, nic_data
->vport_id
,
4039 efx
->net_dev
->dev_addr
);
4041 ether_addr_copy(nic_data
->vport_mac
, efx
->net_dev
->dev_addr
);
4043 rc2
= efx_ef10_vport_add_mac(efx
, nic_data
->vport_id
, mac_old
);
4045 /* Failed to add original MAC, so clear vport_mac */
4046 eth_zero_addr(nic_data
->vport_mac
);
4052 rc2
= efx_ef10_vadaptor_alloc(efx
, nic_data
->vport_id
);
4056 down_write(&efx
->filter_sem
);
4057 rc2
= efx_ef10_filter_table_probe(efx
);
4058 up_write(&efx
->filter_sem
);
4062 rc2
= efx_net_open(efx
->net_dev
);
4066 netif_device_attach(efx
->net_dev
);
4071 netif_err(efx
, drv
, efx
->net_dev
,
4072 "Failed to restore when changing MAC address - scheduling reset\n");
4073 efx_schedule_reset(efx
, RESET_TYPE_DATAPATH
);
4075 return rc
? rc
: rc2
;
4078 /* Caller must hold efx->filter_sem for read if race against
4079 * efx_ef10_filter_table_remove() is possible
4081 static void efx_ef10_filter_sync_rx_mode(struct efx_nic
*efx
)
4083 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4084 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4085 struct net_device
*net_dev
= efx
->net_dev
;
4086 bool uc_promisc
= false, mc_promisc
= false;
4088 if (!efx_dev_registered(efx
))
4094 efx_ef10_filter_mark_old(efx
);
4096 /* Copy/convert the address lists; add the primary station
4097 * address and broadcast address
4099 netif_addr_lock_bh(net_dev
);
4100 efx_ef10_filter_uc_addr_list(efx
, &uc_promisc
);
4101 efx_ef10_filter_mc_addr_list(efx
, &mc_promisc
);
4102 netif_addr_unlock_bh(net_dev
);
4104 /* Insert/renew unicast filters */
4106 efx_ef10_filter_insert_def(efx
, false, false);
4107 efx_ef10_filter_insert_addr_list(efx
, false, false);
4109 /* If any of the filters failed to insert, fall back to
4110 * promiscuous mode - add in the uc_def filter. But keep
4111 * our individual unicast filters.
4113 if (efx_ef10_filter_insert_addr_list(efx
, false, false))
4114 efx_ef10_filter_insert_def(efx
, false, false);
4117 /* Insert/renew multicast filters */
4118 /* If changing promiscuous state with cascaded multicast filters, remove
4119 * old filters first, so that packets are dropped rather than duplicated
4121 if (nic_data
->workaround_26807
&& efx
->mc_promisc
!= mc_promisc
)
4122 efx_ef10_filter_remove_old(efx
);
4124 if (nic_data
->workaround_26807
) {
4125 /* If we failed to insert promiscuous filters, rollback
4126 * and fall back to individual multicast filters
4128 if (efx_ef10_filter_insert_def(efx
, true, true)) {
4129 /* Changing promisc state, so remove old filters */
4130 efx_ef10_filter_remove_old(efx
);
4131 efx_ef10_filter_insert_addr_list(efx
, true, false);
4134 /* If we failed to insert promiscuous filters, don't
4135 * rollback. Regardless, also insert the mc_list
4137 efx_ef10_filter_insert_def(efx
, true, false);
4138 efx_ef10_filter_insert_addr_list(efx
, true, false);
4141 /* If any filters failed to insert, rollback and fall back to
4142 * promiscuous mode - mc_def filter and maybe broadcast. If
4143 * that fails, roll back again and insert as many of our
4144 * individual multicast filters as we can.
4146 if (efx_ef10_filter_insert_addr_list(efx
, true, true)) {
4147 /* Changing promisc state, so remove old filters */
4148 if (nic_data
->workaround_26807
)
4149 efx_ef10_filter_remove_old(efx
);
4150 if (efx_ef10_filter_insert_def(efx
, true, true))
4151 efx_ef10_filter_insert_addr_list(efx
, true, false);
4155 efx_ef10_filter_remove_old(efx
);
4156 efx
->mc_promisc
= mc_promisc
;
4159 static int efx_ef10_set_mac_address(struct efx_nic
*efx
)
4161 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_SET_MAC_IN_LEN
);
4162 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4163 bool was_enabled
= efx
->port_enabled
;
4166 efx_device_detach_sync(efx
);
4167 efx_net_stop(efx
->net_dev
);
4168 down_write(&efx
->filter_sem
);
4169 efx_ef10_filter_table_remove(efx
);
4171 ether_addr_copy(MCDI_PTR(inbuf
, VADAPTOR_SET_MAC_IN_MACADDR
),
4172 efx
->net_dev
->dev_addr
);
4173 MCDI_SET_DWORD(inbuf
, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID
,
4174 nic_data
->vport_id
);
4175 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_VADAPTOR_SET_MAC
, inbuf
,
4176 sizeof(inbuf
), NULL
, 0, NULL
);
4178 efx_ef10_filter_table_probe(efx
);
4179 up_write(&efx
->filter_sem
);
4181 efx_net_open(efx
->net_dev
);
4182 netif_device_attach(efx
->net_dev
);
4184 #ifdef CONFIG_SFC_SRIOV
4185 if (efx
->pci_dev
->is_virtfn
&& efx
->pci_dev
->physfn
) {
4186 struct pci_dev
*pci_dev_pf
= efx
->pci_dev
->physfn
;
4189 struct efx_nic
*efx_pf
;
4191 /* Switch to PF and change MAC address on vport */
4192 efx_pf
= pci_get_drvdata(pci_dev_pf
);
4194 rc
= efx_ef10_sriov_set_vf_mac(efx_pf
,
4196 efx
->net_dev
->dev_addr
);
4198 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
4199 struct efx_ef10_nic_data
*nic_data
= efx_pf
->nic_data
;
4202 /* MAC address successfully changed by VF (with MAC
4203 * spoofing) so update the parent PF if possible.
4205 for (i
= 0; i
< efx_pf
->vf_count
; ++i
) {
4206 struct ef10_vf
*vf
= nic_data
->vf
+ i
;
4208 if (vf
->efx
== efx
) {
4209 ether_addr_copy(vf
->mac
,
4210 efx
->net_dev
->dev_addr
);
4218 netif_err(efx
, drv
, efx
->net_dev
,
4219 "Cannot change MAC address; use sfboot to enable"
4220 " mac-spoofing on this interface\n");
4221 } else if (rc
== -ENOSYS
&& !efx_ef10_is_vf(efx
)) {
4222 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4223 * fall-back to the method of changing the MAC address on the
4224 * vport. This only applies to PFs because such versions of
4225 * MCFW do not support VFs.
4227 rc
= efx_ef10_vport_set_mac_address(efx
);
4229 efx_mcdi_display_error(efx
, MC_CMD_VADAPTOR_SET_MAC
,
4230 sizeof(inbuf
), NULL
, 0, rc
);
4236 static int efx_ef10_mac_reconfigure(struct efx_nic
*efx
)
4238 efx_ef10_filter_sync_rx_mode(efx
);
4240 return efx_mcdi_set_mac(efx
);
4243 static int efx_ef10_mac_reconfigure_vf(struct efx_nic
*efx
)
4245 efx_ef10_filter_sync_rx_mode(efx
);
4250 static int efx_ef10_start_bist(struct efx_nic
*efx
, u32 bist_type
)
4252 MCDI_DECLARE_BUF(inbuf
, MC_CMD_START_BIST_IN_LEN
);
4254 MCDI_SET_DWORD(inbuf
, START_BIST_IN_TYPE
, bist_type
);
4255 return efx_mcdi_rpc(efx
, MC_CMD_START_BIST
, inbuf
, sizeof(inbuf
),
4259 /* MC BISTs follow a different poll mechanism to phy BISTs.
4260 * The BIST is done in the poll handler on the MC, and the MCDI command
4261 * will block until the BIST is done.
4263 static int efx_ef10_poll_bist(struct efx_nic
*efx
)
4266 MCDI_DECLARE_BUF(outbuf
, MC_CMD_POLL_BIST_OUT_LEN
);
4270 rc
= efx_mcdi_rpc(efx
, MC_CMD_POLL_BIST
, NULL
, 0,
4271 outbuf
, sizeof(outbuf
), &outlen
);
4275 if (outlen
< MC_CMD_POLL_BIST_OUT_LEN
)
4278 result
= MCDI_DWORD(outbuf
, POLL_BIST_OUT_RESULT
);
4280 case MC_CMD_POLL_BIST_PASSED
:
4281 netif_dbg(efx
, hw
, efx
->net_dev
, "BIST passed.\n");
4283 case MC_CMD_POLL_BIST_TIMEOUT
:
4284 netif_err(efx
, hw
, efx
->net_dev
, "BIST timed out\n");
4286 case MC_CMD_POLL_BIST_FAILED
:
4287 netif_err(efx
, hw
, efx
->net_dev
, "BIST failed.\n");
4290 netif_err(efx
, hw
, efx
->net_dev
,
4291 "BIST returned unknown result %u", result
);
4296 static int efx_ef10_run_bist(struct efx_nic
*efx
, u32 bist_type
)
4300 netif_dbg(efx
, drv
, efx
->net_dev
, "starting BIST type %u\n", bist_type
);
4302 rc
= efx_ef10_start_bist(efx
, bist_type
);
4306 return efx_ef10_poll_bist(efx
);
4310 efx_ef10_test_chip(struct efx_nic
*efx
, struct efx_self_tests
*tests
)
4314 efx_reset_down(efx
, RESET_TYPE_WORLD
);
4316 rc
= efx_mcdi_rpc(efx
, MC_CMD_ENABLE_OFFLINE_BIST
,
4317 NULL
, 0, NULL
, 0, NULL
);
4321 tests
->memory
= efx_ef10_run_bist(efx
, MC_CMD_MC_MEM_BIST
) ? -1 : 1;
4322 tests
->registers
= efx_ef10_run_bist(efx
, MC_CMD_REG_BIST
) ? -1 : 1;
4324 rc
= efx_mcdi_reset(efx
, RESET_TYPE_WORLD
);
4327 rc2
= efx_reset_up(efx
, RESET_TYPE_WORLD
, rc
== 0);
4328 return rc
? rc
: rc2
;
4331 #ifdef CONFIG_SFC_MTD
4333 struct efx_ef10_nvram_type_info
{
4334 u16 type
, type_mask
;
4339 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types
[] = {
4340 { NVRAM_PARTITION_TYPE_MC_FIRMWARE
, 0, 0, "sfc_mcfw" },
4341 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP
, 0, 0, "sfc_mcfw_backup" },
4342 { NVRAM_PARTITION_TYPE_EXPANSION_ROM
, 0, 0, "sfc_exp_rom" },
4343 { NVRAM_PARTITION_TYPE_STATIC_CONFIG
, 0, 0, "sfc_static_cfg" },
4344 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG
, 0, 0, "sfc_dynamic_cfg" },
4345 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0
, 0, 0, "sfc_exp_rom_cfg" },
4346 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1
, 0, 1, "sfc_exp_rom_cfg" },
4347 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2
, 0, 2, "sfc_exp_rom_cfg" },
4348 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3
, 0, 3, "sfc_exp_rom_cfg" },
4349 { NVRAM_PARTITION_TYPE_LICENSE
, 0, 0, "sfc_license" },
4350 { NVRAM_PARTITION_TYPE_PHY_MIN
, 0xff, 0, "sfc_phy_fw" },
4353 static int efx_ef10_mtd_probe_partition(struct efx_nic
*efx
,
4354 struct efx_mcdi_mtd_partition
*part
,
4357 MCDI_DECLARE_BUF(inbuf
, MC_CMD_NVRAM_METADATA_IN_LEN
);
4358 MCDI_DECLARE_BUF(outbuf
, MC_CMD_NVRAM_METADATA_OUT_LENMAX
);
4359 const struct efx_ef10_nvram_type_info
*info
;
4360 size_t size
, erase_size
, outlen
;
4364 for (info
= efx_ef10_nvram_types
; ; info
++) {
4366 efx_ef10_nvram_types
+ ARRAY_SIZE(efx_ef10_nvram_types
))
4368 if ((type
& ~info
->type_mask
) == info
->type
)
4371 if (info
->port
!= efx_port_num(efx
))
4374 rc
= efx_mcdi_nvram_info(efx
, type
, &size
, &erase_size
, &protected);
4378 return -ENODEV
; /* hide it */
4380 part
->nvram_type
= type
;
4382 MCDI_SET_DWORD(inbuf
, NVRAM_METADATA_IN_TYPE
, type
);
4383 rc
= efx_mcdi_rpc(efx
, MC_CMD_NVRAM_METADATA
, inbuf
, sizeof(inbuf
),
4384 outbuf
, sizeof(outbuf
), &outlen
);
4387 if (outlen
< MC_CMD_NVRAM_METADATA_OUT_LENMIN
)
4389 if (MCDI_DWORD(outbuf
, NVRAM_METADATA_OUT_FLAGS
) &
4390 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN
))
4391 part
->fw_subtype
= MCDI_DWORD(outbuf
,
4392 NVRAM_METADATA_OUT_SUBTYPE
);
4394 part
->common
.dev_type_name
= "EF10 NVRAM manager";
4395 part
->common
.type_name
= info
->name
;
4397 part
->common
.mtd
.type
= MTD_NORFLASH
;
4398 part
->common
.mtd
.flags
= MTD_CAP_NORFLASH
;
4399 part
->common
.mtd
.size
= size
;
4400 part
->common
.mtd
.erasesize
= erase_size
;
4405 static int efx_ef10_mtd_probe(struct efx_nic
*efx
)
4407 MCDI_DECLARE_BUF(outbuf
, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX
);
4408 struct efx_mcdi_mtd_partition
*parts
;
4409 size_t outlen
, n_parts_total
, i
, n_parts
;
4415 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN
!= 0);
4416 rc
= efx_mcdi_rpc(efx
, MC_CMD_NVRAM_PARTITIONS
, NULL
, 0,
4417 outbuf
, sizeof(outbuf
), &outlen
);
4420 if (outlen
< MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN
)
4423 n_parts_total
= MCDI_DWORD(outbuf
, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS
);
4425 MCDI_VAR_ARRAY_LEN(outlen
, NVRAM_PARTITIONS_OUT_TYPE_ID
))
4428 parts
= kcalloc(n_parts_total
, sizeof(*parts
), GFP_KERNEL
);
4433 for (i
= 0; i
< n_parts_total
; i
++) {
4434 type
= MCDI_ARRAY_DWORD(outbuf
, NVRAM_PARTITIONS_OUT_TYPE_ID
,
4436 rc
= efx_ef10_mtd_probe_partition(efx
, &parts
[n_parts
], type
);
4439 else if (rc
!= -ENODEV
)
4443 rc
= efx_mtd_add(efx
, &parts
[0].common
, n_parts
, sizeof(*parts
));
4450 #endif /* CONFIG_SFC_MTD */
4452 static void efx_ef10_ptp_write_host_time(struct efx_nic
*efx
, u32 host_time
)
4454 _efx_writed(efx
, cpu_to_le32(host_time
), ER_DZ_MC_DB_LWRD
);
4457 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic
*efx
,
4460 static int efx_ef10_rx_enable_timestamping(struct efx_channel
*channel
,
4463 MCDI_DECLARE_BUF(inbuf
, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN
);
4466 if (channel
->sync_events_state
== SYNC_EVENTS_REQUESTED
||
4467 channel
->sync_events_state
== SYNC_EVENTS_VALID
||
4468 (temp
&& channel
->sync_events_state
== SYNC_EVENTS_DISABLED
))
4470 channel
->sync_events_state
= SYNC_EVENTS_REQUESTED
;
4472 MCDI_SET_DWORD(inbuf
, PTP_IN_OP
, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE
);
4473 MCDI_SET_DWORD(inbuf
, PTP_IN_PERIPH_ID
, 0);
4474 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE
,
4477 rc
= efx_mcdi_rpc(channel
->efx
, MC_CMD_PTP
,
4478 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
4481 channel
->sync_events_state
= temp
? SYNC_EVENTS_QUIESCENT
:
4482 SYNC_EVENTS_DISABLED
;
4487 static int efx_ef10_rx_disable_timestamping(struct efx_channel
*channel
,
4490 MCDI_DECLARE_BUF(inbuf
, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN
);
4493 if (channel
->sync_events_state
== SYNC_EVENTS_DISABLED
||
4494 (temp
&& channel
->sync_events_state
== SYNC_EVENTS_QUIESCENT
))
4496 if (channel
->sync_events_state
== SYNC_EVENTS_QUIESCENT
) {
4497 channel
->sync_events_state
= SYNC_EVENTS_DISABLED
;
4500 channel
->sync_events_state
= temp
? SYNC_EVENTS_QUIESCENT
:
4501 SYNC_EVENTS_DISABLED
;
4503 MCDI_SET_DWORD(inbuf
, PTP_IN_OP
, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE
);
4504 MCDI_SET_DWORD(inbuf
, PTP_IN_PERIPH_ID
, 0);
4505 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL
,
4506 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE
);
4507 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE
,
4510 rc
= efx_mcdi_rpc(channel
->efx
, MC_CMD_PTP
,
4511 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
4516 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic
*efx
, bool en
,
4519 int (*set
)(struct efx_channel
*channel
, bool temp
);
4520 struct efx_channel
*channel
;
4523 efx_ef10_rx_enable_timestamping
:
4524 efx_ef10_rx_disable_timestamping
;
4526 efx_for_each_channel(channel
, efx
) {
4527 int rc
= set(channel
, temp
);
4528 if (en
&& rc
!= 0) {
4529 efx_ef10_ptp_set_ts_sync_events(efx
, false, temp
);
4537 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic
*efx
,
4538 struct hwtstamp_config
*init
)
4543 static int efx_ef10_ptp_set_ts_config(struct efx_nic
*efx
,
4544 struct hwtstamp_config
*init
)
4548 switch (init
->rx_filter
) {
4549 case HWTSTAMP_FILTER_NONE
:
4550 efx_ef10_ptp_set_ts_sync_events(efx
, false, false);
4551 /* if TX timestamping is still requested then leave PTP on */
4552 return efx_ptp_change_mode(efx
,
4553 init
->tx_type
!= HWTSTAMP_TX_OFF
, 0);
4554 case HWTSTAMP_FILTER_ALL
:
4555 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
4556 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
4557 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
4558 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
4559 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
4560 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
4561 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
4562 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
4563 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
4564 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
4565 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
4566 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
4567 init
->rx_filter
= HWTSTAMP_FILTER_ALL
;
4568 rc
= efx_ptp_change_mode(efx
, true, 0);
4570 rc
= efx_ef10_ptp_set_ts_sync_events(efx
, true, false);
4572 efx_ptp_change_mode(efx
, false, 0);
4579 const struct efx_nic_type efx_hunt_a0_vf_nic_type
= {
4581 .mem_bar
= EFX_MEM_VF_BAR
,
4582 .mem_map_size
= efx_ef10_mem_map_size
,
4583 .probe
= efx_ef10_probe_vf
,
4584 .remove
= efx_ef10_remove
,
4585 .dimension_resources
= efx_ef10_dimension_resources
,
4586 .init
= efx_ef10_init_nic
,
4587 .fini
= efx_port_dummy_op_void
,
4588 .map_reset_reason
= efx_ef10_map_reset_reason
,
4589 .map_reset_flags
= efx_ef10_map_reset_flags
,
4590 .reset
= efx_ef10_reset
,
4591 .probe_port
= efx_mcdi_port_probe
,
4592 .remove_port
= efx_mcdi_port_remove
,
4593 .fini_dmaq
= efx_ef10_fini_dmaq
,
4594 .prepare_flr
= efx_ef10_prepare_flr
,
4595 .finish_flr
= efx_port_dummy_op_void
,
4596 .describe_stats
= efx_ef10_describe_stats
,
4597 .update_stats
= efx_ef10_update_stats_vf
,
4598 .start_stats
= efx_port_dummy_op_void
,
4599 .pull_stats
= efx_port_dummy_op_void
,
4600 .stop_stats
= efx_port_dummy_op_void
,
4601 .set_id_led
= efx_mcdi_set_id_led
,
4602 .push_irq_moderation
= efx_ef10_push_irq_moderation
,
4603 .reconfigure_mac
= efx_ef10_mac_reconfigure_vf
,
4604 .check_mac_fault
= efx_mcdi_mac_check_fault
,
4605 .reconfigure_port
= efx_mcdi_port_reconfigure
,
4606 .get_wol
= efx_ef10_get_wol_vf
,
4607 .set_wol
= efx_ef10_set_wol_vf
,
4608 .resume_wol
= efx_port_dummy_op_void
,
4609 .mcdi_request
= efx_ef10_mcdi_request
,
4610 .mcdi_poll_response
= efx_ef10_mcdi_poll_response
,
4611 .mcdi_read_response
= efx_ef10_mcdi_read_response
,
4612 .mcdi_poll_reboot
= efx_ef10_mcdi_poll_reboot
,
4613 .irq_enable_master
= efx_port_dummy_op_void
,
4614 .irq_test_generate
= efx_ef10_irq_test_generate
,
4615 .irq_disable_non_ev
= efx_port_dummy_op_void
,
4616 .irq_handle_msi
= efx_ef10_msi_interrupt
,
4617 .irq_handle_legacy
= efx_ef10_legacy_interrupt
,
4618 .tx_probe
= efx_ef10_tx_probe
,
4619 .tx_init
= efx_ef10_tx_init
,
4620 .tx_remove
= efx_ef10_tx_remove
,
4621 .tx_write
= efx_ef10_tx_write
,
4622 .rx_push_rss_config
= efx_ef10_vf_rx_push_rss_config
,
4623 .rx_probe
= efx_ef10_rx_probe
,
4624 .rx_init
= efx_ef10_rx_init
,
4625 .rx_remove
= efx_ef10_rx_remove
,
4626 .rx_write
= efx_ef10_rx_write
,
4627 .rx_defer_refill
= efx_ef10_rx_defer_refill
,
4628 .ev_probe
= efx_ef10_ev_probe
,
4629 .ev_init
= efx_ef10_ev_init
,
4630 .ev_fini
= efx_ef10_ev_fini
,
4631 .ev_remove
= efx_ef10_ev_remove
,
4632 .ev_process
= efx_ef10_ev_process
,
4633 .ev_read_ack
= efx_ef10_ev_read_ack
,
4634 .ev_test_generate
= efx_ef10_ev_test_generate
,
4635 .filter_table_probe
= efx_ef10_filter_table_probe
,
4636 .filter_table_restore
= efx_ef10_filter_table_restore
,
4637 .filter_table_remove
= efx_ef10_filter_table_remove
,
4638 .filter_update_rx_scatter
= efx_ef10_filter_update_rx_scatter
,
4639 .filter_insert
= efx_ef10_filter_insert
,
4640 .filter_remove_safe
= efx_ef10_filter_remove_safe
,
4641 .filter_get_safe
= efx_ef10_filter_get_safe
,
4642 .filter_clear_rx
= efx_ef10_filter_clear_rx
,
4643 .filter_count_rx_used
= efx_ef10_filter_count_rx_used
,
4644 .filter_get_rx_id_limit
= efx_ef10_filter_get_rx_id_limit
,
4645 .filter_get_rx_ids
= efx_ef10_filter_get_rx_ids
,
4646 #ifdef CONFIG_RFS_ACCEL
4647 .filter_rfs_insert
= efx_ef10_filter_rfs_insert
,
4648 .filter_rfs_expire_one
= efx_ef10_filter_rfs_expire_one
,
4650 #ifdef CONFIG_SFC_MTD
4651 .mtd_probe
= efx_port_dummy_op_int
,
4653 .ptp_write_host_time
= efx_ef10_ptp_write_host_time_vf
,
4654 .ptp_set_ts_config
= efx_ef10_ptp_set_ts_config_vf
,
4655 #ifdef CONFIG_SFC_SRIOV
4656 .vswitching_probe
= efx_ef10_vswitching_probe_vf
,
4657 .vswitching_restore
= efx_ef10_vswitching_restore_vf
,
4658 .vswitching_remove
= efx_ef10_vswitching_remove_vf
,
4659 .sriov_get_phys_port_id
= efx_ef10_sriov_get_phys_port_id
,
4661 .get_mac_address
= efx_ef10_get_mac_address_vf
,
4662 .set_mac_address
= efx_ef10_set_mac_address
,
4664 .revision
= EFX_REV_HUNT_A0
,
4665 .max_dma_mask
= DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH
),
4666 .rx_prefix_size
= ES_DZ_RX_PREFIX_SIZE
,
4667 .rx_hash_offset
= ES_DZ_RX_PREFIX_HASH_OFST
,
4668 .rx_ts_offset
= ES_DZ_RX_PREFIX_TSTAMP_OFST
,
4669 .can_rx_scatter
= true,
4670 .always_rx_scatter
= true,
4671 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
4672 .timer_period_max
= 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH
,
4673 .offload_features
= (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
4674 NETIF_F_RXHASH
| NETIF_F_NTUPLE
),
4676 .max_rx_ip_filters
= HUNT_FILTER_TBL_ROWS
,
4677 .hwtstamp_filters
= 1 << HWTSTAMP_FILTER_NONE
|
4678 1 << HWTSTAMP_FILTER_ALL
,
4681 const struct efx_nic_type efx_hunt_a0_nic_type
= {
4683 .mem_bar
= EFX_MEM_BAR
,
4684 .mem_map_size
= efx_ef10_mem_map_size
,
4685 .probe
= efx_ef10_probe_pf
,
4686 .remove
= efx_ef10_remove
,
4687 .dimension_resources
= efx_ef10_dimension_resources
,
4688 .init
= efx_ef10_init_nic
,
4689 .fini
= efx_port_dummy_op_void
,
4690 .map_reset_reason
= efx_ef10_map_reset_reason
,
4691 .map_reset_flags
= efx_ef10_map_reset_flags
,
4692 .reset
= efx_ef10_reset
,
4693 .probe_port
= efx_mcdi_port_probe
,
4694 .remove_port
= efx_mcdi_port_remove
,
4695 .fini_dmaq
= efx_ef10_fini_dmaq
,
4696 .prepare_flr
= efx_ef10_prepare_flr
,
4697 .finish_flr
= efx_port_dummy_op_void
,
4698 .describe_stats
= efx_ef10_describe_stats
,
4699 .update_stats
= efx_ef10_update_stats_pf
,
4700 .start_stats
= efx_mcdi_mac_start_stats
,
4701 .pull_stats
= efx_mcdi_mac_pull_stats
,
4702 .stop_stats
= efx_mcdi_mac_stop_stats
,
4703 .set_id_led
= efx_mcdi_set_id_led
,
4704 .push_irq_moderation
= efx_ef10_push_irq_moderation
,
4705 .reconfigure_mac
= efx_ef10_mac_reconfigure
,
4706 .check_mac_fault
= efx_mcdi_mac_check_fault
,
4707 .reconfigure_port
= efx_mcdi_port_reconfigure
,
4708 .get_wol
= efx_ef10_get_wol
,
4709 .set_wol
= efx_ef10_set_wol
,
4710 .resume_wol
= efx_port_dummy_op_void
,
4711 .test_chip
= efx_ef10_test_chip
,
4712 .test_nvram
= efx_mcdi_nvram_test_all
,
4713 .mcdi_request
= efx_ef10_mcdi_request
,
4714 .mcdi_poll_response
= efx_ef10_mcdi_poll_response
,
4715 .mcdi_read_response
= efx_ef10_mcdi_read_response
,
4716 .mcdi_poll_reboot
= efx_ef10_mcdi_poll_reboot
,
4717 .irq_enable_master
= efx_port_dummy_op_void
,
4718 .irq_test_generate
= efx_ef10_irq_test_generate
,
4719 .irq_disable_non_ev
= efx_port_dummy_op_void
,
4720 .irq_handle_msi
= efx_ef10_msi_interrupt
,
4721 .irq_handle_legacy
= efx_ef10_legacy_interrupt
,
4722 .tx_probe
= efx_ef10_tx_probe
,
4723 .tx_init
= efx_ef10_tx_init
,
4724 .tx_remove
= efx_ef10_tx_remove
,
4725 .tx_write
= efx_ef10_tx_write
,
4726 .rx_push_rss_config
= efx_ef10_pf_rx_push_rss_config
,
4727 .rx_probe
= efx_ef10_rx_probe
,
4728 .rx_init
= efx_ef10_rx_init
,
4729 .rx_remove
= efx_ef10_rx_remove
,
4730 .rx_write
= efx_ef10_rx_write
,
4731 .rx_defer_refill
= efx_ef10_rx_defer_refill
,
4732 .ev_probe
= efx_ef10_ev_probe
,
4733 .ev_init
= efx_ef10_ev_init
,
4734 .ev_fini
= efx_ef10_ev_fini
,
4735 .ev_remove
= efx_ef10_ev_remove
,
4736 .ev_process
= efx_ef10_ev_process
,
4737 .ev_read_ack
= efx_ef10_ev_read_ack
,
4738 .ev_test_generate
= efx_ef10_ev_test_generate
,
4739 .filter_table_probe
= efx_ef10_filter_table_probe
,
4740 .filter_table_restore
= efx_ef10_filter_table_restore
,
4741 .filter_table_remove
= efx_ef10_filter_table_remove
,
4742 .filter_update_rx_scatter
= efx_ef10_filter_update_rx_scatter
,
4743 .filter_insert
= efx_ef10_filter_insert
,
4744 .filter_remove_safe
= efx_ef10_filter_remove_safe
,
4745 .filter_get_safe
= efx_ef10_filter_get_safe
,
4746 .filter_clear_rx
= efx_ef10_filter_clear_rx
,
4747 .filter_count_rx_used
= efx_ef10_filter_count_rx_used
,
4748 .filter_get_rx_id_limit
= efx_ef10_filter_get_rx_id_limit
,
4749 .filter_get_rx_ids
= efx_ef10_filter_get_rx_ids
,
4750 #ifdef CONFIG_RFS_ACCEL
4751 .filter_rfs_insert
= efx_ef10_filter_rfs_insert
,
4752 .filter_rfs_expire_one
= efx_ef10_filter_rfs_expire_one
,
4754 #ifdef CONFIG_SFC_MTD
4755 .mtd_probe
= efx_ef10_mtd_probe
,
4756 .mtd_rename
= efx_mcdi_mtd_rename
,
4757 .mtd_read
= efx_mcdi_mtd_read
,
4758 .mtd_erase
= efx_mcdi_mtd_erase
,
4759 .mtd_write
= efx_mcdi_mtd_write
,
4760 .mtd_sync
= efx_mcdi_mtd_sync
,
4762 .ptp_write_host_time
= efx_ef10_ptp_write_host_time
,
4763 .ptp_set_ts_sync_events
= efx_ef10_ptp_set_ts_sync_events
,
4764 .ptp_set_ts_config
= efx_ef10_ptp_set_ts_config
,
4765 #ifdef CONFIG_SFC_SRIOV
4766 .sriov_configure
= efx_ef10_sriov_configure
,
4767 .sriov_init
= efx_ef10_sriov_init
,
4768 .sriov_fini
= efx_ef10_sriov_fini
,
4769 .sriov_wanted
= efx_ef10_sriov_wanted
,
4770 .sriov_reset
= efx_ef10_sriov_reset
,
4771 .sriov_flr
= efx_ef10_sriov_flr
,
4772 .sriov_set_vf_mac
= efx_ef10_sriov_set_vf_mac
,
4773 .sriov_set_vf_vlan
= efx_ef10_sriov_set_vf_vlan
,
4774 .sriov_set_vf_spoofchk
= efx_ef10_sriov_set_vf_spoofchk
,
4775 .sriov_get_vf_config
= efx_ef10_sriov_get_vf_config
,
4776 .sriov_set_vf_link_state
= efx_ef10_sriov_set_vf_link_state
,
4777 .vswitching_probe
= efx_ef10_vswitching_probe_pf
,
4778 .vswitching_restore
= efx_ef10_vswitching_restore_pf
,
4779 .vswitching_remove
= efx_ef10_vswitching_remove_pf
,
4781 .get_mac_address
= efx_ef10_get_mac_address_pf
,
4782 .set_mac_address
= efx_ef10_set_mac_address
,
4784 .revision
= EFX_REV_HUNT_A0
,
4785 .max_dma_mask
= DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH
),
4786 .rx_prefix_size
= ES_DZ_RX_PREFIX_SIZE
,
4787 .rx_hash_offset
= ES_DZ_RX_PREFIX_HASH_OFST
,
4788 .rx_ts_offset
= ES_DZ_RX_PREFIX_TSTAMP_OFST
,
4789 .can_rx_scatter
= true,
4790 .always_rx_scatter
= true,
4791 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
4792 .timer_period_max
= 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH
,
4793 .offload_features
= (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
4794 NETIF_F_RXHASH
| NETIF_F_NTUPLE
),
4796 .max_rx_ip_filters
= HUNT_FILTER_TBL_ROWS
,
4797 .hwtstamp_filters
= 1 << HWTSTAMP_FILTER_NONE
|
4798 1 << HWTSTAMP_FILTER_ALL
,