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sfc: Implement ndo_vlan_rx_{add, kill}_vid() callbacks
[deliverable/linux.git] / drivers / net / ethernet / sfc / ef10.c
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10 #include "net_driver.h"
11 #include "ef10_regs.h"
12 #include "io.h"
13 #include "mcdi.h"
14 #include "mcdi_pcol.h"
15 #include "nic.h"
16 #include "workarounds.h"
17 #include "selftest.h"
18 #include "ef10_sriov.h"
19 #include <linux/in.h>
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
23
24 /* Hardware control for EF10 architecture including 'Huntington'. */
25
26 #define EFX_EF10_DRVGEN_EV 7
27 enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30 };
31
32 /* The reserved RSS context value */
33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The maximum size of a shared RSS context */
35 /* TODO: this should really be from the mcdi protocol export */
36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
37
38 /* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50 #define HUNT_FILTER_TBL_ROWS 8192
51
52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
53
54 #define EFX_EF10_FILTER_DEV_UC_MAX 32
55 #define EFX_EF10_FILTER_DEV_MC_MAX 256
56
57 /* VLAN list entry */
58 struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61 };
62
63 /* Per-VLAN filters information */
64 struct efx_ef10_filter_vlan {
65 struct list_head list;
66 u16 vid;
67 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
68 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
69 u16 ucdef;
70 u16 bcast;
71 u16 mcdef;
72 };
73
74 struct efx_ef10_dev_addr {
75 u8 addr[ETH_ALEN];
76 };
77
78 struct efx_ef10_filter_table {
79 /* The RX match field masks supported by this fw & hw, in order of priority */
80 enum efx_filter_match_flags rx_match_flags[
81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
82 unsigned int rx_match_count;
83
84 struct {
85 unsigned long spec; /* pointer to spec plus flag bits */
86 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
87 * used to mark and sweep MAC filters for the device address lists.
88 */
89 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
90 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
91 #define EFX_EF10_FILTER_FLAGS 3UL
92 u64 handle; /* firmware handle */
93 } *entry;
94 wait_queue_head_t waitq;
95 /* Shadow of net_device address lists, guarded by mac_lock */
96 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
97 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
98 int dev_uc_count;
99 int dev_mc_count;
100 bool uc_promisc;
101 bool mc_promisc;
102 /* Whether in multicast promiscuous mode when last changed */
103 bool mc_promisc_last;
104 bool vlan_filter;
105 struct list_head vlan_list;
106 };
107
108 /* An arbitrary search limit for the software hash table */
109 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
110
111 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
112 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
113 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
114 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
115 struct efx_ef10_filter_vlan *vlan);
116 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
117
118 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
119 {
120 efx_dword_t reg;
121
122 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
123 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
124 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
125 }
126
127 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
128 {
129 int bar;
130
131 bar = efx->type->mem_bar;
132 return resource_size(&efx->pci_dev->resource[bar]);
133 }
134
135 static bool efx_ef10_is_vf(struct efx_nic *efx)
136 {
137 return efx->type->is_vf;
138 }
139
140 static int efx_ef10_get_pf_index(struct efx_nic *efx)
141 {
142 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
143 struct efx_ef10_nic_data *nic_data = efx->nic_data;
144 size_t outlen;
145 int rc;
146
147 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
148 sizeof(outbuf), &outlen);
149 if (rc)
150 return rc;
151 if (outlen < sizeof(outbuf))
152 return -EIO;
153
154 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
155 return 0;
156 }
157
158 #ifdef CONFIG_SFC_SRIOV
159 static int efx_ef10_get_vf_index(struct efx_nic *efx)
160 {
161 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
162 struct efx_ef10_nic_data *nic_data = efx->nic_data;
163 size_t outlen;
164 int rc;
165
166 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
167 sizeof(outbuf), &outlen);
168 if (rc)
169 return rc;
170 if (outlen < sizeof(outbuf))
171 return -EIO;
172
173 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
174 return 0;
175 }
176 #endif
177
178 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
179 {
180 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
181 struct efx_ef10_nic_data *nic_data = efx->nic_data;
182 size_t outlen;
183 int rc;
184
185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
186
187 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
188 outbuf, sizeof(outbuf), &outlen);
189 if (rc)
190 return rc;
191 if (outlen < sizeof(outbuf)) {
192 netif_err(efx, drv, efx->net_dev,
193 "unable to read datapath firmware capabilities\n");
194 return -EIO;
195 }
196
197 nic_data->datapath_caps =
198 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
199
200 /* record the DPCPU firmware IDs to determine VEB vswitching support.
201 */
202 nic_data->rx_dpcpu_fw_id =
203 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
204 nic_data->tx_dpcpu_fw_id =
205 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
206
207 if (!(nic_data->datapath_caps &
208 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
209 netif_err(efx, probe, efx->net_dev,
210 "current firmware does not support an RX prefix\n");
211 return -ENODEV;
212 }
213
214 return 0;
215 }
216
217 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
218 {
219 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
220 int rc;
221
222 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
223 outbuf, sizeof(outbuf), NULL);
224 if (rc)
225 return rc;
226 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
227 return rc > 0 ? rc : -ERANGE;
228 }
229
230 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
231 {
232 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
233 size_t outlen;
234 int rc;
235
236 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
237
238 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
239 outbuf, sizeof(outbuf), &outlen);
240 if (rc)
241 return rc;
242 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
243 return -EIO;
244
245 ether_addr_copy(mac_address,
246 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
247 return 0;
248 }
249
250 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
251 {
252 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
253 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
254 size_t outlen;
255 int num_addrs, rc;
256
257 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
258 EVB_PORT_ID_ASSIGNED);
259 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
260 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
261
262 if (rc)
263 return rc;
264 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
265 return -EIO;
266
267 num_addrs = MCDI_DWORD(outbuf,
268 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
269
270 WARN_ON(num_addrs != 1);
271
272 ether_addr_copy(mac_address,
273 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
274
275 return 0;
276 }
277
278 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
279 struct device_attribute *attr,
280 char *buf)
281 {
282 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
283
284 return sprintf(buf, "%d\n",
285 ((efx->mcdi->fn_flags) &
286 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
287 ? 1 : 0);
288 }
289
290 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
291 struct device_attribute *attr,
292 char *buf)
293 {
294 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
295
296 return sprintf(buf, "%d\n",
297 ((efx->mcdi->fn_flags) &
298 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
299 ? 1 : 0);
300 }
301
302 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
303 {
304 struct efx_ef10_nic_data *nic_data = efx->nic_data;
305 struct efx_ef10_vlan *vlan;
306
307 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
308
309 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
310 if (vlan->vid == vid)
311 return vlan;
312 }
313
314 return NULL;
315 }
316
317 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
318 {
319 struct efx_ef10_nic_data *nic_data = efx->nic_data;
320 struct efx_ef10_vlan *vlan;
321 int rc;
322
323 mutex_lock(&nic_data->vlan_lock);
324
325 vlan = efx_ef10_find_vlan(efx, vid);
326 if (vlan) {
327 /* We add VID 0 on init. 8021q adds it on module init
328 * for all interfaces with VLAN filtring feature.
329 */
330 if (vid == 0)
331 goto done_unlock;
332 netif_warn(efx, drv, efx->net_dev,
333 "VLAN %u already added\n", vid);
334 rc = -EALREADY;
335 goto fail_exist;
336 }
337
338 rc = -ENOMEM;
339 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
340 if (!vlan)
341 goto fail_alloc;
342
343 vlan->vid = vid;
344
345 list_add_tail(&vlan->list, &nic_data->vlan_list);
346
347 if (efx->filter_state) {
348 mutex_lock(&efx->mac_lock);
349 down_write(&efx->filter_sem);
350 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
351 up_write(&efx->filter_sem);
352 mutex_unlock(&efx->mac_lock);
353 if (rc)
354 goto fail_filter_add_vlan;
355 }
356
357 done_unlock:
358 mutex_unlock(&nic_data->vlan_lock);
359 return 0;
360
361 fail_filter_add_vlan:
362 list_del(&vlan->list);
363 kfree(vlan);
364 fail_alloc:
365 fail_exist:
366 mutex_unlock(&nic_data->vlan_lock);
367 return rc;
368 }
369
370 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
371 struct efx_ef10_vlan *vlan)
372 {
373 struct efx_ef10_nic_data *nic_data = efx->nic_data;
374
375 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
376
377 if (efx->filter_state) {
378 down_write(&efx->filter_sem);
379 efx_ef10_filter_del_vlan(efx, vlan->vid);
380 up_write(&efx->filter_sem);
381 }
382
383 list_del(&vlan->list);
384 kfree(vlan);
385 }
386
387 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
388 {
389 struct efx_ef10_nic_data *nic_data = efx->nic_data;
390 struct efx_ef10_vlan *vlan;
391 int rc = 0;
392
393 /* 8021q removes VID 0 on module unload for all interfaces
394 * with VLAN filtering feature. We need to keep it to receive
395 * untagged traffic.
396 */
397 if (vid == 0)
398 return 0;
399
400 mutex_lock(&nic_data->vlan_lock);
401
402 vlan = efx_ef10_find_vlan(efx, vid);
403 if (!vlan) {
404 netif_err(efx, drv, efx->net_dev,
405 "VLAN %u to be deleted not found\n", vid);
406 rc = -ENOENT;
407 } else {
408 efx_ef10_del_vlan_internal(efx, vlan);
409 }
410
411 mutex_unlock(&nic_data->vlan_lock);
412
413 return rc;
414 }
415
416 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
417 {
418 struct efx_ef10_nic_data *nic_data = efx->nic_data;
419 struct efx_ef10_vlan *vlan, *next_vlan;
420
421 mutex_lock(&nic_data->vlan_lock);
422 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
423 efx_ef10_del_vlan_internal(efx, vlan);
424 mutex_unlock(&nic_data->vlan_lock);
425 }
426
427 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
428 NULL);
429 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
430
431 static int efx_ef10_probe(struct efx_nic *efx)
432 {
433 struct efx_ef10_nic_data *nic_data;
434 struct net_device *net_dev = efx->net_dev;
435 int i, rc;
436
437 /* We can have one VI for each 8K region. However, until we
438 * use TX option descriptors we need two TX queues per channel.
439 */
440 efx->max_channels = min_t(unsigned int,
441 EFX_MAX_CHANNELS,
442 efx_ef10_mem_map_size(efx) /
443 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
444 efx->max_tx_channels = efx->max_channels;
445 if (WARN_ON(efx->max_channels == 0))
446 return -EIO;
447
448 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
449 if (!nic_data)
450 return -ENOMEM;
451 efx->nic_data = nic_data;
452
453 /* we assume later that we can copy from this buffer in dwords */
454 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
455
456 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
457 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
458 if (rc)
459 goto fail1;
460
461 /* Get the MC's warm boot count. In case it's rebooting right
462 * now, be prepared to retry.
463 */
464 i = 0;
465 for (;;) {
466 rc = efx_ef10_get_warm_boot_count(efx);
467 if (rc >= 0)
468 break;
469 if (++i == 5)
470 goto fail2;
471 ssleep(1);
472 }
473 nic_data->warm_boot_count = rc;
474
475 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
476
477 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
478
479 /* In case we're recovering from a crash (kexec), we want to
480 * cancel any outstanding request by the previous user of this
481 * function. We send a special message using the least
482 * significant bits of the 'high' (doorbell) register.
483 */
484 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
485
486 rc = efx_mcdi_init(efx);
487 if (rc)
488 goto fail2;
489
490 /* Reset (most) configuration for this function */
491 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
492 if (rc)
493 goto fail3;
494
495 /* Enable event logging */
496 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
497 if (rc)
498 goto fail3;
499
500 rc = device_create_file(&efx->pci_dev->dev,
501 &dev_attr_link_control_flag);
502 if (rc)
503 goto fail3;
504
505 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
506 if (rc)
507 goto fail4;
508
509 rc = efx_ef10_get_pf_index(efx);
510 if (rc)
511 goto fail5;
512
513 rc = efx_ef10_init_datapath_caps(efx);
514 if (rc < 0)
515 goto fail5;
516
517 efx->rx_packet_len_offset =
518 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
519
520 rc = efx_mcdi_port_get_number(efx);
521 if (rc < 0)
522 goto fail5;
523 efx->port_num = rc;
524 net_dev->dev_port = rc;
525
526 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
527 if (rc)
528 goto fail5;
529
530 rc = efx_ef10_get_sysclk_freq(efx);
531 if (rc < 0)
532 goto fail5;
533 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
534
535 /* Check whether firmware supports bug 35388 workaround.
536 * First try to enable it, then if we get EPERM, just
537 * ask if it's already enabled
538 */
539 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
540 if (rc == 0) {
541 nic_data->workaround_35388 = true;
542 } else if (rc == -EPERM) {
543 unsigned int enabled;
544
545 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
546 if (rc)
547 goto fail3;
548 nic_data->workaround_35388 = enabled &
549 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
550 } else if (rc != -ENOSYS && rc != -ENOENT) {
551 goto fail5;
552 }
553 netif_dbg(efx, probe, efx->net_dev,
554 "workaround for bug 35388 is %sabled\n",
555 nic_data->workaround_35388 ? "en" : "dis");
556
557 rc = efx_mcdi_mon_probe(efx);
558 if (rc && rc != -EPERM)
559 goto fail5;
560
561 efx_ptp_probe(efx, NULL);
562
563 #ifdef CONFIG_SFC_SRIOV
564 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
565 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
566 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
567
568 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
569 } else
570 #endif
571 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
572
573 INIT_LIST_HEAD(&nic_data->vlan_list);
574 mutex_init(&nic_data->vlan_lock);
575
576 /* Add unspecified VID to support VLAN filtering being disabled */
577 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
578 if (rc)
579 goto fail_add_vid_unspec;
580
581 /* If VLAN filtering is enabled, we need VID 0 to get untagged
582 * traffic. It is added automatically if 8021q module is loaded,
583 * but we can't rely on it since module may be not loaded.
584 */
585 rc = efx_ef10_add_vlan(efx, 0);
586 if (rc)
587 goto fail_add_vid_0;
588
589 return 0;
590
591 fail_add_vid_0:
592 efx_ef10_cleanup_vlans(efx);
593 fail_add_vid_unspec:
594 mutex_destroy(&nic_data->vlan_lock);
595 efx_ptp_remove(efx);
596 efx_mcdi_mon_remove(efx);
597 fail5:
598 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
599 fail4:
600 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
601 fail3:
602 efx_mcdi_fini(efx);
603 fail2:
604 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
605 fail1:
606 kfree(nic_data);
607 efx->nic_data = NULL;
608 return rc;
609 }
610
611 static int efx_ef10_free_vis(struct efx_nic *efx)
612 {
613 MCDI_DECLARE_BUF_ERR(outbuf);
614 size_t outlen;
615 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
616 outbuf, sizeof(outbuf), &outlen);
617
618 /* -EALREADY means nothing to free, so ignore */
619 if (rc == -EALREADY)
620 rc = 0;
621 if (rc)
622 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
623 rc);
624 return rc;
625 }
626
627 #ifdef EFX_USE_PIO
628
629 static void efx_ef10_free_piobufs(struct efx_nic *efx)
630 {
631 struct efx_ef10_nic_data *nic_data = efx->nic_data;
632 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
633 unsigned int i;
634 int rc;
635
636 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
637
638 for (i = 0; i < nic_data->n_piobufs; i++) {
639 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
640 nic_data->piobuf_handle[i]);
641 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
642 NULL, 0, NULL);
643 WARN_ON(rc);
644 }
645
646 nic_data->n_piobufs = 0;
647 }
648
649 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
650 {
651 struct efx_ef10_nic_data *nic_data = efx->nic_data;
652 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
653 unsigned int i;
654 size_t outlen;
655 int rc = 0;
656
657 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
658
659 for (i = 0; i < n; i++) {
660 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
661 outbuf, sizeof(outbuf), &outlen);
662 if (rc) {
663 /* Don't display the MC error if we didn't have space
664 * for a VF.
665 */
666 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
667 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
668 0, outbuf, outlen, rc);
669 break;
670 }
671 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
672 rc = -EIO;
673 break;
674 }
675 nic_data->piobuf_handle[i] =
676 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
677 netif_dbg(efx, probe, efx->net_dev,
678 "allocated PIO buffer %u handle %x\n", i,
679 nic_data->piobuf_handle[i]);
680 }
681
682 nic_data->n_piobufs = i;
683 if (rc)
684 efx_ef10_free_piobufs(efx);
685 return rc;
686 }
687
688 static int efx_ef10_link_piobufs(struct efx_nic *efx)
689 {
690 struct efx_ef10_nic_data *nic_data = efx->nic_data;
691 _MCDI_DECLARE_BUF(inbuf,
692 max(MC_CMD_LINK_PIOBUF_IN_LEN,
693 MC_CMD_UNLINK_PIOBUF_IN_LEN));
694 struct efx_channel *channel;
695 struct efx_tx_queue *tx_queue;
696 unsigned int offset, index;
697 int rc;
698
699 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
700 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
701
702 memset(inbuf, 0, sizeof(inbuf));
703
704 /* Link a buffer to each VI in the write-combining mapping */
705 for (index = 0; index < nic_data->n_piobufs; ++index) {
706 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
707 nic_data->piobuf_handle[index]);
708 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
709 nic_data->pio_write_vi_base + index);
710 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
711 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
712 NULL, 0, NULL);
713 if (rc) {
714 netif_err(efx, drv, efx->net_dev,
715 "failed to link VI %u to PIO buffer %u (%d)\n",
716 nic_data->pio_write_vi_base + index, index,
717 rc);
718 goto fail;
719 }
720 netif_dbg(efx, probe, efx->net_dev,
721 "linked VI %u to PIO buffer %u\n",
722 nic_data->pio_write_vi_base + index, index);
723 }
724
725 /* Link a buffer to each TX queue */
726 efx_for_each_channel(channel, efx) {
727 efx_for_each_channel_tx_queue(tx_queue, channel) {
728 /* We assign the PIO buffers to queues in
729 * reverse order to allow for the following
730 * special case.
731 */
732 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
733 tx_queue->channel->channel - 1) *
734 efx_piobuf_size);
735 index = offset / ER_DZ_TX_PIOBUF_SIZE;
736 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
737
738 /* When the host page size is 4K, the first
739 * host page in the WC mapping may be within
740 * the same VI page as the last TX queue. We
741 * can only link one buffer to each VI.
742 */
743 if (tx_queue->queue == nic_data->pio_write_vi_base) {
744 BUG_ON(index != 0);
745 rc = 0;
746 } else {
747 MCDI_SET_DWORD(inbuf,
748 LINK_PIOBUF_IN_PIOBUF_HANDLE,
749 nic_data->piobuf_handle[index]);
750 MCDI_SET_DWORD(inbuf,
751 LINK_PIOBUF_IN_TXQ_INSTANCE,
752 tx_queue->queue);
753 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
754 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
755 NULL, 0, NULL);
756 }
757
758 if (rc) {
759 /* This is non-fatal; the TX path just
760 * won't use PIO for this queue
761 */
762 netif_err(efx, drv, efx->net_dev,
763 "failed to link VI %u to PIO buffer %u (%d)\n",
764 tx_queue->queue, index, rc);
765 tx_queue->piobuf = NULL;
766 } else {
767 tx_queue->piobuf =
768 nic_data->pio_write_base +
769 index * EFX_VI_PAGE_SIZE + offset;
770 tx_queue->piobuf_offset = offset;
771 netif_dbg(efx, probe, efx->net_dev,
772 "linked VI %u to PIO buffer %u offset %x addr %p\n",
773 tx_queue->queue, index,
774 tx_queue->piobuf_offset,
775 tx_queue->piobuf);
776 }
777 }
778 }
779
780 return 0;
781
782 fail:
783 while (index--) {
784 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
785 nic_data->pio_write_vi_base + index);
786 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
787 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
788 NULL, 0, NULL);
789 }
790 return rc;
791 }
792
793 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
794 {
795 struct efx_channel *channel;
796 struct efx_tx_queue *tx_queue;
797
798 /* All our existing PIO buffers went away */
799 efx_for_each_channel(channel, efx)
800 efx_for_each_channel_tx_queue(tx_queue, channel)
801 tx_queue->piobuf = NULL;
802 }
803
804 #else /* !EFX_USE_PIO */
805
806 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
807 {
808 return n == 0 ? 0 : -ENOBUFS;
809 }
810
811 static int efx_ef10_link_piobufs(struct efx_nic *efx)
812 {
813 return 0;
814 }
815
816 static void efx_ef10_free_piobufs(struct efx_nic *efx)
817 {
818 }
819
820 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
821 {
822 }
823
824 #endif /* EFX_USE_PIO */
825
826 static void efx_ef10_remove(struct efx_nic *efx)
827 {
828 struct efx_ef10_nic_data *nic_data = efx->nic_data;
829 int rc;
830
831 #ifdef CONFIG_SFC_SRIOV
832 struct efx_ef10_nic_data *nic_data_pf;
833 struct pci_dev *pci_dev_pf;
834 struct efx_nic *efx_pf;
835 struct ef10_vf *vf;
836
837 if (efx->pci_dev->is_virtfn) {
838 pci_dev_pf = efx->pci_dev->physfn;
839 if (pci_dev_pf) {
840 efx_pf = pci_get_drvdata(pci_dev_pf);
841 nic_data_pf = efx_pf->nic_data;
842 vf = nic_data_pf->vf + nic_data->vf_index;
843 vf->efx = NULL;
844 } else
845 netif_info(efx, drv, efx->net_dev,
846 "Could not get the PF id from VF\n");
847 }
848 #endif
849
850 efx_ef10_cleanup_vlans(efx);
851 mutex_destroy(&nic_data->vlan_lock);
852
853 efx_ptp_remove(efx);
854
855 efx_mcdi_mon_remove(efx);
856
857 efx_ef10_rx_free_indir_table(efx);
858
859 if (nic_data->wc_membase)
860 iounmap(nic_data->wc_membase);
861
862 rc = efx_ef10_free_vis(efx);
863 WARN_ON(rc != 0);
864
865 if (!nic_data->must_restore_piobufs)
866 efx_ef10_free_piobufs(efx);
867
868 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
869 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
870
871 efx_mcdi_fini(efx);
872 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
873 kfree(nic_data);
874 }
875
876 static int efx_ef10_probe_pf(struct efx_nic *efx)
877 {
878 return efx_ef10_probe(efx);
879 }
880
881 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
882 {
883 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
884
885 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
886 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
887 NULL, 0, NULL);
888 }
889
890 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
891 {
892 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
893
894 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
895 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
896 NULL, 0, NULL);
897 }
898
899 int efx_ef10_vport_add_mac(struct efx_nic *efx,
900 unsigned int port_id, u8 *mac)
901 {
902 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
903
904 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
905 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
906
907 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
908 sizeof(inbuf), NULL, 0, NULL);
909 }
910
911 int efx_ef10_vport_del_mac(struct efx_nic *efx,
912 unsigned int port_id, u8 *mac)
913 {
914 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
915
916 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
917 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
918
919 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
920 sizeof(inbuf), NULL, 0, NULL);
921 }
922
923 #ifdef CONFIG_SFC_SRIOV
924 static int efx_ef10_probe_vf(struct efx_nic *efx)
925 {
926 int rc;
927 struct pci_dev *pci_dev_pf;
928
929 /* If the parent PF has no VF data structure, it doesn't know about this
930 * VF so fail probe. The VF needs to be re-created. This can happen
931 * if the PF driver is unloaded while the VF is assigned to a guest.
932 */
933 pci_dev_pf = efx->pci_dev->physfn;
934 if (pci_dev_pf) {
935 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
936 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
937
938 if (!nic_data_pf->vf) {
939 netif_info(efx, drv, efx->net_dev,
940 "The VF cannot link to its parent PF; "
941 "please destroy and re-create the VF\n");
942 return -EBUSY;
943 }
944 }
945
946 rc = efx_ef10_probe(efx);
947 if (rc)
948 return rc;
949
950 rc = efx_ef10_get_vf_index(efx);
951 if (rc)
952 goto fail;
953
954 if (efx->pci_dev->is_virtfn) {
955 if (efx->pci_dev->physfn) {
956 struct efx_nic *efx_pf =
957 pci_get_drvdata(efx->pci_dev->physfn);
958 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
959 struct efx_ef10_nic_data *nic_data = efx->nic_data;
960
961 nic_data_p->vf[nic_data->vf_index].efx = efx;
962 nic_data_p->vf[nic_data->vf_index].pci_dev =
963 efx->pci_dev;
964 } else
965 netif_info(efx, drv, efx->net_dev,
966 "Could not get the PF id from VF\n");
967 }
968
969 return 0;
970
971 fail:
972 efx_ef10_remove(efx);
973 return rc;
974 }
975 #else
976 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
977 {
978 return 0;
979 }
980 #endif
981
982 static int efx_ef10_alloc_vis(struct efx_nic *efx,
983 unsigned int min_vis, unsigned int max_vis)
984 {
985 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
986 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
987 struct efx_ef10_nic_data *nic_data = efx->nic_data;
988 size_t outlen;
989 int rc;
990
991 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
992 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
993 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
994 outbuf, sizeof(outbuf), &outlen);
995 if (rc != 0)
996 return rc;
997
998 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
999 return -EIO;
1000
1001 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1002 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1003
1004 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1005 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1006 return 0;
1007 }
1008
1009 /* Note that the failure path of this function does not free
1010 * resources, as this will be done by efx_ef10_remove().
1011 */
1012 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1013 {
1014 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1015 unsigned int uc_mem_map_size, wc_mem_map_size;
1016 unsigned int min_vis = max(EFX_TXQ_TYPES,
1017 efx_separate_tx_channels ? 2 : 1);
1018 unsigned int channel_vis, pio_write_vi_base, max_vis;
1019 void __iomem *membase;
1020 int rc;
1021
1022 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1023
1024 #ifdef EFX_USE_PIO
1025 /* Try to allocate PIO buffers if wanted and if the full
1026 * number of PIO buffers would be sufficient to allocate one
1027 * copy-buffer per TX channel. Failure is non-fatal, as there
1028 * are only a small number of PIO buffers shared between all
1029 * functions of the controller.
1030 */
1031 if (efx_piobuf_size != 0 &&
1032 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1033 efx->n_tx_channels) {
1034 unsigned int n_piobufs =
1035 DIV_ROUND_UP(efx->n_tx_channels,
1036 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
1037
1038 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1039 if (rc)
1040 netif_err(efx, probe, efx->net_dev,
1041 "failed to allocate PIO buffers (%d)\n", rc);
1042 else
1043 netif_dbg(efx, probe, efx->net_dev,
1044 "allocated %u PIO buffers\n", n_piobufs);
1045 }
1046 #else
1047 nic_data->n_piobufs = 0;
1048 #endif
1049
1050 /* PIO buffers should be mapped with write-combining enabled,
1051 * and we want to make single UC and WC mappings rather than
1052 * several of each (in fact that's the only option if host
1053 * page size is >4K). So we may allocate some extra VIs just
1054 * for writing PIO buffers through.
1055 *
1056 * The UC mapping contains (channel_vis - 1) complete VIs and the
1057 * first half of the next VI. Then the WC mapping begins with
1058 * the second half of this last VI.
1059 */
1060 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
1061 ER_DZ_TX_PIOBUF);
1062 if (nic_data->n_piobufs) {
1063 /* pio_write_vi_base rounds down to give the number of complete
1064 * VIs inside the UC mapping.
1065 */
1066 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1067 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1068 nic_data->n_piobufs) *
1069 EFX_VI_PAGE_SIZE) -
1070 uc_mem_map_size);
1071 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1072 } else {
1073 pio_write_vi_base = 0;
1074 wc_mem_map_size = 0;
1075 max_vis = channel_vis;
1076 }
1077
1078 /* In case the last attached driver failed to free VIs, do it now */
1079 rc = efx_ef10_free_vis(efx);
1080 if (rc != 0)
1081 return rc;
1082
1083 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1084 if (rc != 0)
1085 return rc;
1086
1087 if (nic_data->n_allocated_vis < channel_vis) {
1088 netif_info(efx, drv, efx->net_dev,
1089 "Could not allocate enough VIs to satisfy RSS"
1090 " requirements. Performance may not be optimal.\n");
1091 /* We didn't get the VIs to populate our channels.
1092 * We could keep what we got but then we'd have more
1093 * interrupts than we need.
1094 * Instead calculate new max_channels and restart
1095 */
1096 efx->max_channels = nic_data->n_allocated_vis;
1097 efx->max_tx_channels =
1098 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1099
1100 efx_ef10_free_vis(efx);
1101 return -EAGAIN;
1102 }
1103
1104 /* If we didn't get enough VIs to map all the PIO buffers, free the
1105 * PIO buffers
1106 */
1107 if (nic_data->n_piobufs &&
1108 nic_data->n_allocated_vis <
1109 pio_write_vi_base + nic_data->n_piobufs) {
1110 netif_dbg(efx, probe, efx->net_dev,
1111 "%u VIs are not sufficient to map %u PIO buffers\n",
1112 nic_data->n_allocated_vis, nic_data->n_piobufs);
1113 efx_ef10_free_piobufs(efx);
1114 }
1115
1116 /* Shrink the original UC mapping of the memory BAR */
1117 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1118 if (!membase) {
1119 netif_err(efx, probe, efx->net_dev,
1120 "could not shrink memory BAR to %x\n",
1121 uc_mem_map_size);
1122 return -ENOMEM;
1123 }
1124 iounmap(efx->membase);
1125 efx->membase = membase;
1126
1127 /* Set up the WC mapping if needed */
1128 if (wc_mem_map_size) {
1129 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1130 uc_mem_map_size,
1131 wc_mem_map_size);
1132 if (!nic_data->wc_membase) {
1133 netif_err(efx, probe, efx->net_dev,
1134 "could not allocate WC mapping of size %x\n",
1135 wc_mem_map_size);
1136 return -ENOMEM;
1137 }
1138 nic_data->pio_write_vi_base = pio_write_vi_base;
1139 nic_data->pio_write_base =
1140 nic_data->wc_membase +
1141 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1142 uc_mem_map_size);
1143
1144 rc = efx_ef10_link_piobufs(efx);
1145 if (rc)
1146 efx_ef10_free_piobufs(efx);
1147 }
1148
1149 netif_dbg(efx, probe, efx->net_dev,
1150 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1151 &efx->membase_phys, efx->membase, uc_mem_map_size,
1152 nic_data->wc_membase, wc_mem_map_size);
1153
1154 return 0;
1155 }
1156
1157 static int efx_ef10_init_nic(struct efx_nic *efx)
1158 {
1159 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1160 int rc;
1161
1162 if (nic_data->must_check_datapath_caps) {
1163 rc = efx_ef10_init_datapath_caps(efx);
1164 if (rc)
1165 return rc;
1166 nic_data->must_check_datapath_caps = false;
1167 }
1168
1169 if (nic_data->must_realloc_vis) {
1170 /* We cannot let the number of VIs change now */
1171 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1172 nic_data->n_allocated_vis);
1173 if (rc)
1174 return rc;
1175 nic_data->must_realloc_vis = false;
1176 }
1177
1178 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1179 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1180 if (rc == 0) {
1181 rc = efx_ef10_link_piobufs(efx);
1182 if (rc)
1183 efx_ef10_free_piobufs(efx);
1184 }
1185
1186 /* Log an error on failure, but this is non-fatal */
1187 if (rc)
1188 netif_err(efx, drv, efx->net_dev,
1189 "failed to restore PIO buffers (%d)\n", rc);
1190 nic_data->must_restore_piobufs = false;
1191 }
1192
1193 /* don't fail init if RSS setup doesn't work */
1194 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1195
1196 return 0;
1197 }
1198
1199 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1200 {
1201 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1202 #ifdef CONFIG_SFC_SRIOV
1203 unsigned int i;
1204 #endif
1205
1206 /* All our allocations have been reset */
1207 nic_data->must_realloc_vis = true;
1208 nic_data->must_restore_filters = true;
1209 nic_data->must_restore_piobufs = true;
1210 efx_ef10_forget_old_piobufs(efx);
1211 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1212
1213 /* Driver-created vswitches and vports must be re-created */
1214 nic_data->must_probe_vswitching = true;
1215 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1216 #ifdef CONFIG_SFC_SRIOV
1217 if (nic_data->vf)
1218 for (i = 0; i < efx->vf_count; i++)
1219 nic_data->vf[i].vport_id = 0;
1220 #endif
1221 }
1222
1223 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1224 {
1225 if (reason == RESET_TYPE_MC_FAILURE)
1226 return RESET_TYPE_DATAPATH;
1227
1228 return efx_mcdi_map_reset_reason(reason);
1229 }
1230
1231 static int efx_ef10_map_reset_flags(u32 *flags)
1232 {
1233 enum {
1234 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1235 ETH_RESET_SHARED_SHIFT),
1236 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1237 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1238 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1239 ETH_RESET_SHARED_SHIFT)
1240 };
1241
1242 /* We assume for now that our PCI function is permitted to
1243 * reset everything.
1244 */
1245
1246 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1247 *flags &= ~EF10_RESET_MC;
1248 return RESET_TYPE_WORLD;
1249 }
1250
1251 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1252 *flags &= ~EF10_RESET_PORT;
1253 return RESET_TYPE_ALL;
1254 }
1255
1256 /* no invisible reset implemented */
1257
1258 return -EINVAL;
1259 }
1260
1261 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1262 {
1263 int rc = efx_mcdi_reset(efx, reset_type);
1264
1265 /* Unprivileged functions return -EPERM, but need to return success
1266 * here so that the datapath is brought back up.
1267 */
1268 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1269 rc = 0;
1270
1271 /* If it was a port reset, trigger reallocation of MC resources.
1272 * Note that on an MC reset nothing needs to be done now because we'll
1273 * detect the MC reset later and handle it then.
1274 * For an FLR, we never get an MC reset event, but the MC has reset all
1275 * resources assigned to us, so we have to trigger reallocation now.
1276 */
1277 if ((reset_type == RESET_TYPE_ALL ||
1278 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1279 efx_ef10_reset_mc_allocations(efx);
1280 return rc;
1281 }
1282
1283 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1284 [EF10_STAT_ ## ext_name] = \
1285 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1286 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1287 [EF10_STAT_ ## int_name] = \
1288 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1289 #define EF10_OTHER_STAT(ext_name) \
1290 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1291 #define GENERIC_SW_STAT(ext_name) \
1292 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1293
1294 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1295 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1296 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1297 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1298 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1299 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1300 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1301 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1302 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1303 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1304 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1305 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1306 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1307 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1308 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1309 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1310 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1311 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1312 EF10_OTHER_STAT(port_rx_good_bytes),
1313 EF10_OTHER_STAT(port_rx_bad_bytes),
1314 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1315 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1316 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1317 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1318 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1319 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1320 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1321 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1322 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1323 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1324 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1325 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1326 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1327 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1328 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1329 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1330 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1331 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1332 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1333 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1334 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1335 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1336 GENERIC_SW_STAT(rx_nodesc_trunc),
1337 GENERIC_SW_STAT(rx_noskb_drops),
1338 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1339 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1340 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1341 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1342 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1343 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1344 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1345 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1346 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1347 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1348 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1349 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1350 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1351 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1352 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1353 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1354 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1355 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1356 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1357 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1358 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1359 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1360 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1361 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1362 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1363 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1364 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1365 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1366 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1367 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1368 };
1369
1370 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1371 (1ULL << EF10_STAT_port_tx_packets) | \
1372 (1ULL << EF10_STAT_port_tx_pause) | \
1373 (1ULL << EF10_STAT_port_tx_unicast) | \
1374 (1ULL << EF10_STAT_port_tx_multicast) | \
1375 (1ULL << EF10_STAT_port_tx_broadcast) | \
1376 (1ULL << EF10_STAT_port_rx_bytes) | \
1377 (1ULL << \
1378 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1379 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1380 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1381 (1ULL << EF10_STAT_port_rx_packets) | \
1382 (1ULL << EF10_STAT_port_rx_good) | \
1383 (1ULL << EF10_STAT_port_rx_bad) | \
1384 (1ULL << EF10_STAT_port_rx_pause) | \
1385 (1ULL << EF10_STAT_port_rx_control) | \
1386 (1ULL << EF10_STAT_port_rx_unicast) | \
1387 (1ULL << EF10_STAT_port_rx_multicast) | \
1388 (1ULL << EF10_STAT_port_rx_broadcast) | \
1389 (1ULL << EF10_STAT_port_rx_lt64) | \
1390 (1ULL << EF10_STAT_port_rx_64) | \
1391 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1392 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1393 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1394 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1395 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1396 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1397 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1398 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1399 (1ULL << EF10_STAT_port_rx_overflow) | \
1400 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1401 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1402 (1ULL << GENERIC_STAT_rx_noskb_drops))
1403
1404 /* These statistics are only provided by the 10G MAC. For a 10G/40G
1405 * switchable port we do not expose these because they might not
1406 * include all the packets they should.
1407 */
1408 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1409 (1ULL << EF10_STAT_port_tx_lt64) | \
1410 (1ULL << EF10_STAT_port_tx_64) | \
1411 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1412 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1413 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1414 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1415 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1416 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1417
1418 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1419 * switchable port we do expose these because the errors will otherwise
1420 * be silent.
1421 */
1422 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1423 (1ULL << EF10_STAT_port_rx_length_error))
1424
1425 /* These statistics are only provided if the firmware supports the
1426 * capability PM_AND_RXDP_COUNTERS.
1427 */
1428 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1429 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1430 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1431 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1432 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1433 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1434 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1435 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1436 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1437 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1438 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1439 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1440 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1441
1442 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1443 {
1444 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1445 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1446 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1447
1448 if (!(efx->mcdi->fn_flags &
1449 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1450 return 0;
1451
1452 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
1453 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1454 else
1455 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1456
1457 if (nic_data->datapath_caps &
1458 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1459 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1460
1461 return raw_mask;
1462 }
1463
1464 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1465 {
1466 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1467 u64 raw_mask[2];
1468
1469 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1470
1471 /* Only show vadaptor stats when EVB capability is present */
1472 if (nic_data->datapath_caps &
1473 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1474 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1475 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1476 } else {
1477 raw_mask[1] = 0;
1478 }
1479
1480 #if BITS_PER_LONG == 64
1481 mask[0] = raw_mask[0];
1482 mask[1] = raw_mask[1];
1483 #else
1484 mask[0] = raw_mask[0] & 0xffffffff;
1485 mask[1] = raw_mask[0] >> 32;
1486 mask[2] = raw_mask[1] & 0xffffffff;
1487 mask[3] = raw_mask[1] >> 32;
1488 #endif
1489 }
1490
1491 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1492 {
1493 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1494
1495 efx_ef10_get_stat_mask(efx, mask);
1496 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1497 mask, names);
1498 }
1499
1500 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1501 struct rtnl_link_stats64 *core_stats)
1502 {
1503 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1504 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1505 u64 *stats = nic_data->stats;
1506 size_t stats_count = 0, index;
1507
1508 efx_ef10_get_stat_mask(efx, mask);
1509
1510 if (full_stats) {
1511 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1512 if (efx_ef10_stat_desc[index].name) {
1513 *full_stats++ = stats[index];
1514 ++stats_count;
1515 }
1516 }
1517 }
1518
1519 if (!core_stats)
1520 return stats_count;
1521
1522 if (nic_data->datapath_caps &
1523 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1524 /* Use vadaptor stats. */
1525 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1526 stats[EF10_STAT_rx_multicast] +
1527 stats[EF10_STAT_rx_broadcast];
1528 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1529 stats[EF10_STAT_tx_multicast] +
1530 stats[EF10_STAT_tx_broadcast];
1531 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1532 stats[EF10_STAT_rx_multicast_bytes] +
1533 stats[EF10_STAT_rx_broadcast_bytes];
1534 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1535 stats[EF10_STAT_tx_multicast_bytes] +
1536 stats[EF10_STAT_tx_broadcast_bytes];
1537 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1538 stats[GENERIC_STAT_rx_noskb_drops];
1539 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1540 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1541 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1542 core_stats->rx_errors = core_stats->rx_crc_errors;
1543 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1544 } else {
1545 /* Use port stats. */
1546 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1547 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1548 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1549 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1550 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1551 stats[GENERIC_STAT_rx_nodesc_trunc] +
1552 stats[GENERIC_STAT_rx_noskb_drops];
1553 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1554 core_stats->rx_length_errors =
1555 stats[EF10_STAT_port_rx_gtjumbo] +
1556 stats[EF10_STAT_port_rx_length_error];
1557 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1558 core_stats->rx_frame_errors =
1559 stats[EF10_STAT_port_rx_align_error];
1560 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1561 core_stats->rx_errors = (core_stats->rx_length_errors +
1562 core_stats->rx_crc_errors +
1563 core_stats->rx_frame_errors);
1564 }
1565
1566 return stats_count;
1567 }
1568
1569 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1570 {
1571 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1572 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1573 __le64 generation_start, generation_end;
1574 u64 *stats = nic_data->stats;
1575 __le64 *dma_stats;
1576
1577 efx_ef10_get_stat_mask(efx, mask);
1578
1579 dma_stats = efx->stats_buffer.addr;
1580 nic_data = efx->nic_data;
1581
1582 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1583 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1584 return 0;
1585 rmb();
1586 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1587 stats, efx->stats_buffer.addr, false);
1588 rmb();
1589 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1590 if (generation_end != generation_start)
1591 return -EAGAIN;
1592
1593 /* Update derived statistics */
1594 efx_nic_fix_nodesc_drop_stat(efx,
1595 &stats[EF10_STAT_port_rx_nodesc_drops]);
1596 stats[EF10_STAT_port_rx_good_bytes] =
1597 stats[EF10_STAT_port_rx_bytes] -
1598 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1599 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1600 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1601 efx_update_sw_stats(efx, stats);
1602 return 0;
1603 }
1604
1605
1606 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1607 struct rtnl_link_stats64 *core_stats)
1608 {
1609 int retry;
1610
1611 /* If we're unlucky enough to read statistics during the DMA, wait
1612 * up to 10ms for it to finish (typically takes <500us)
1613 */
1614 for (retry = 0; retry < 100; ++retry) {
1615 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1616 break;
1617 udelay(100);
1618 }
1619
1620 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1621 }
1622
1623 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1624 {
1625 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1626 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1627 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1628 __le64 generation_start, generation_end;
1629 u64 *stats = nic_data->stats;
1630 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1631 struct efx_buffer stats_buf;
1632 __le64 *dma_stats;
1633 int rc;
1634
1635 spin_unlock_bh(&efx->stats_lock);
1636
1637 if (in_interrupt()) {
1638 /* If in atomic context, cannot update stats. Just update the
1639 * software stats and return so the caller can continue.
1640 */
1641 spin_lock_bh(&efx->stats_lock);
1642 efx_update_sw_stats(efx, stats);
1643 return 0;
1644 }
1645
1646 efx_ef10_get_stat_mask(efx, mask);
1647
1648 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1649 if (rc) {
1650 spin_lock_bh(&efx->stats_lock);
1651 return rc;
1652 }
1653
1654 dma_stats = stats_buf.addr;
1655 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1656
1657 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1658 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1659 MAC_STATS_IN_DMA, 1);
1660 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1661 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1662
1663 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1664 NULL, 0, NULL);
1665 spin_lock_bh(&efx->stats_lock);
1666 if (rc) {
1667 /* Expect ENOENT if DMA queues have not been set up */
1668 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1669 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1670 sizeof(inbuf), NULL, 0, rc);
1671 goto out;
1672 }
1673
1674 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1675 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1676 WARN_ON_ONCE(1);
1677 goto out;
1678 }
1679 rmb();
1680 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1681 stats, stats_buf.addr, false);
1682 rmb();
1683 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1684 if (generation_end != generation_start) {
1685 rc = -EAGAIN;
1686 goto out;
1687 }
1688
1689 efx_update_sw_stats(efx, stats);
1690 out:
1691 efx_nic_free_buffer(efx, &stats_buf);
1692 return rc;
1693 }
1694
1695 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1696 struct rtnl_link_stats64 *core_stats)
1697 {
1698 if (efx_ef10_try_update_nic_stats_vf(efx))
1699 return 0;
1700
1701 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1702 }
1703
1704 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1705 {
1706 struct efx_nic *efx = channel->efx;
1707 unsigned int mode, value;
1708 efx_dword_t timer_cmd;
1709
1710 if (channel->irq_moderation) {
1711 mode = 3;
1712 value = channel->irq_moderation - 1;
1713 } else {
1714 mode = 0;
1715 value = 0;
1716 }
1717
1718 if (EFX_EF10_WORKAROUND_35388(efx)) {
1719 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1720 EFE_DD_EVQ_IND_TIMER_FLAGS,
1721 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1722 ERF_DD_EVQ_IND_TIMER_VAL, value);
1723 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1724 channel->channel);
1725 } else {
1726 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1727 ERF_DZ_TC_TIMER_VAL, value);
1728 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1729 channel->channel);
1730 }
1731 }
1732
1733 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1734 struct ethtool_wolinfo *wol) {}
1735
1736 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1737 {
1738 return -EOPNOTSUPP;
1739 }
1740
1741 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1742 {
1743 wol->supported = 0;
1744 wol->wolopts = 0;
1745 memset(&wol->sopass, 0, sizeof(wol->sopass));
1746 }
1747
1748 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1749 {
1750 if (type != 0)
1751 return -EINVAL;
1752 return 0;
1753 }
1754
1755 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1756 const efx_dword_t *hdr, size_t hdr_len,
1757 const efx_dword_t *sdu, size_t sdu_len)
1758 {
1759 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1760 u8 *pdu = nic_data->mcdi_buf.addr;
1761
1762 memcpy(pdu, hdr, hdr_len);
1763 memcpy(pdu + hdr_len, sdu, sdu_len);
1764 wmb();
1765
1766 /* The hardware provides 'low' and 'high' (doorbell) registers
1767 * for passing the 64-bit address of an MCDI request to
1768 * firmware. However the dwords are swapped by firmware. The
1769 * least significant bits of the doorbell are then 0 for all
1770 * MCDI requests due to alignment.
1771 */
1772 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1773 ER_DZ_MC_DB_LWRD);
1774 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1775 ER_DZ_MC_DB_HWRD);
1776 }
1777
1778 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1779 {
1780 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1781 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1782
1783 rmb();
1784 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1785 }
1786
1787 static void
1788 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1789 size_t offset, size_t outlen)
1790 {
1791 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1792 const u8 *pdu = nic_data->mcdi_buf.addr;
1793
1794 memcpy(outbuf, pdu + offset, outlen);
1795 }
1796
1797 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1798 {
1799 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1800
1801 /* All our allocations have been reset */
1802 efx_ef10_reset_mc_allocations(efx);
1803
1804 /* The datapath firmware might have been changed */
1805 nic_data->must_check_datapath_caps = true;
1806
1807 /* MAC statistics have been cleared on the NIC; clear the local
1808 * statistic that we update with efx_update_diff_stat().
1809 */
1810 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1811 }
1812
1813 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1814 {
1815 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1816 int rc;
1817
1818 rc = efx_ef10_get_warm_boot_count(efx);
1819 if (rc < 0) {
1820 /* The firmware is presumably in the process of
1821 * rebooting. However, we are supposed to report each
1822 * reboot just once, so we must only do that once we
1823 * can read and store the updated warm boot count.
1824 */
1825 return 0;
1826 }
1827
1828 if (rc == nic_data->warm_boot_count)
1829 return 0;
1830
1831 nic_data->warm_boot_count = rc;
1832 efx_ef10_mcdi_reboot_detected(efx);
1833
1834 return -EIO;
1835 }
1836
1837 /* Handle an MSI interrupt
1838 *
1839 * Handle an MSI hardware interrupt. This routine schedules event
1840 * queue processing. No interrupt acknowledgement cycle is necessary.
1841 * Also, we never need to check that the interrupt is for us, since
1842 * MSI interrupts cannot be shared.
1843 */
1844 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1845 {
1846 struct efx_msi_context *context = dev_id;
1847 struct efx_nic *efx = context->efx;
1848
1849 netif_vdbg(efx, intr, efx->net_dev,
1850 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1851
1852 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1853 /* Note test interrupts */
1854 if (context->index == efx->irq_level)
1855 efx->last_irq_cpu = raw_smp_processor_id();
1856
1857 /* Schedule processing of the channel */
1858 efx_schedule_channel_irq(efx->channel[context->index]);
1859 }
1860
1861 return IRQ_HANDLED;
1862 }
1863
1864 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1865 {
1866 struct efx_nic *efx = dev_id;
1867 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1868 struct efx_channel *channel;
1869 efx_dword_t reg;
1870 u32 queues;
1871
1872 /* Read the ISR which also ACKs the interrupts */
1873 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1874 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1875
1876 if (queues == 0)
1877 return IRQ_NONE;
1878
1879 if (likely(soft_enabled)) {
1880 /* Note test interrupts */
1881 if (queues & (1U << efx->irq_level))
1882 efx->last_irq_cpu = raw_smp_processor_id();
1883
1884 efx_for_each_channel(channel, efx) {
1885 if (queues & 1)
1886 efx_schedule_channel_irq(channel);
1887 queues >>= 1;
1888 }
1889 }
1890
1891 netif_vdbg(efx, intr, efx->net_dev,
1892 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1893 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1894
1895 return IRQ_HANDLED;
1896 }
1897
1898 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1899 {
1900 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1901
1902 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1903
1904 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1905 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1906 inbuf, sizeof(inbuf), NULL, 0, NULL);
1907 }
1908
1909 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1910 {
1911 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1912 (tx_queue->ptr_mask + 1) *
1913 sizeof(efx_qword_t),
1914 GFP_KERNEL);
1915 }
1916
1917 /* This writes to the TX_DESC_WPTR and also pushes data */
1918 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1919 const efx_qword_t *txd)
1920 {
1921 unsigned int write_ptr;
1922 efx_oword_t reg;
1923
1924 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1925 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1926 reg.qword[0] = *txd;
1927 efx_writeo_page(tx_queue->efx, &reg,
1928 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1929 }
1930
1931 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1932 {
1933 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1934 EFX_BUF_SIZE));
1935 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1936 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1937 struct efx_channel *channel = tx_queue->channel;
1938 struct efx_nic *efx = tx_queue->efx;
1939 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1940 size_t inlen;
1941 dma_addr_t dma_addr;
1942 efx_qword_t *txd;
1943 int rc;
1944 int i;
1945 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
1946
1947 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1948 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1949 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1950 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1951 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1952 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1953 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1954 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1955 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
1956
1957 dma_addr = tx_queue->txd.buf.dma_addr;
1958
1959 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1960 tx_queue->queue, entries, (u64)dma_addr);
1961
1962 for (i = 0; i < entries; ++i) {
1963 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1964 dma_addr += EFX_BUF_SIZE;
1965 }
1966
1967 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1968
1969 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1970 NULL, 0, NULL);
1971 if (rc)
1972 goto fail;
1973
1974 /* A previous user of this TX queue might have set us up the
1975 * bomb by writing a descriptor to the TX push collector but
1976 * not the doorbell. (Each collector belongs to a port, not a
1977 * queue or function, so cannot easily be reset.) We must
1978 * attempt to push a no-op descriptor in its place.
1979 */
1980 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1981 tx_queue->insert_count = 1;
1982 txd = efx_tx_desc(tx_queue, 0);
1983 EFX_POPULATE_QWORD_4(*txd,
1984 ESF_DZ_TX_DESC_IS_OPT, true,
1985 ESF_DZ_TX_OPTION_TYPE,
1986 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1987 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1988 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1989 tx_queue->write_count = 1;
1990
1991 if (nic_data->datapath_caps &
1992 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
1993 tx_queue->tso_version = 1;
1994 }
1995
1996 wmb();
1997 efx_ef10_push_tx_desc(tx_queue, txd);
1998
1999 return;
2000
2001 fail:
2002 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2003 tx_queue->queue);
2004 }
2005
2006 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2007 {
2008 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2009 MCDI_DECLARE_BUF_ERR(outbuf);
2010 struct efx_nic *efx = tx_queue->efx;
2011 size_t outlen;
2012 int rc;
2013
2014 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2015 tx_queue->queue);
2016
2017 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2018 outbuf, sizeof(outbuf), &outlen);
2019
2020 if (rc && rc != -EALREADY)
2021 goto fail;
2022
2023 return;
2024
2025 fail:
2026 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2027 outbuf, outlen, rc);
2028 }
2029
2030 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2031 {
2032 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2033 }
2034
2035 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2036 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2037 {
2038 unsigned int write_ptr;
2039 efx_dword_t reg;
2040
2041 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2042 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2043 efx_writed_page(tx_queue->efx, &reg,
2044 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2045 }
2046
2047 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2048 {
2049 unsigned int old_write_count = tx_queue->write_count;
2050 struct efx_tx_buffer *buffer;
2051 unsigned int write_ptr;
2052 efx_qword_t *txd;
2053
2054 tx_queue->xmit_more_available = false;
2055 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2056 return;
2057
2058 do {
2059 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2060 buffer = &tx_queue->buffer[write_ptr];
2061 txd = efx_tx_desc(tx_queue, write_ptr);
2062 ++tx_queue->write_count;
2063
2064 /* Create TX descriptor ring entry */
2065 if (buffer->flags & EFX_TX_BUF_OPTION) {
2066 *txd = buffer->option;
2067 } else {
2068 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2069 EFX_POPULATE_QWORD_3(
2070 *txd,
2071 ESF_DZ_TX_KER_CONT,
2072 buffer->flags & EFX_TX_BUF_CONT,
2073 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2074 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2075 }
2076 } while (tx_queue->write_count != tx_queue->insert_count);
2077
2078 wmb(); /* Ensure descriptors are written before they are fetched */
2079
2080 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2081 txd = efx_tx_desc(tx_queue,
2082 old_write_count & tx_queue->ptr_mask);
2083 efx_ef10_push_tx_desc(tx_queue, txd);
2084 ++tx_queue->pushes;
2085 } else {
2086 efx_ef10_notify_tx_desc(tx_queue);
2087 }
2088 }
2089
2090 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2091 bool exclusive, unsigned *context_size)
2092 {
2093 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2094 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2095 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2096 size_t outlen;
2097 int rc;
2098 u32 alloc_type = exclusive ?
2099 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2100 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2101 unsigned rss_spread = exclusive ?
2102 efx->rss_spread :
2103 min(rounddown_pow_of_two(efx->rss_spread),
2104 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2105
2106 if (!exclusive && rss_spread == 1) {
2107 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2108 if (context_size)
2109 *context_size = 1;
2110 return 0;
2111 }
2112
2113 if (nic_data->datapath_caps &
2114 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2115 return -EOPNOTSUPP;
2116
2117 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2118 nic_data->vport_id);
2119 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2120 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2121
2122 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2123 outbuf, sizeof(outbuf), &outlen);
2124 if (rc != 0)
2125 return rc;
2126
2127 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2128 return -EIO;
2129
2130 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2131
2132 if (context_size)
2133 *context_size = rss_spread;
2134
2135 return 0;
2136 }
2137
2138 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2139 {
2140 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2141 int rc;
2142
2143 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2144 context);
2145
2146 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2147 NULL, 0, NULL);
2148 WARN_ON(rc != 0);
2149 }
2150
2151 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2152 const u32 *rx_indir_table)
2153 {
2154 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2155 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2156 int i, rc;
2157
2158 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2159 context);
2160 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2161 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2162
2163 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2164 MCDI_PTR(tablebuf,
2165 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2166 (u8) rx_indir_table[i];
2167
2168 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2169 sizeof(tablebuf), NULL, 0, NULL);
2170 if (rc != 0)
2171 return rc;
2172
2173 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2174 context);
2175 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2176 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2177 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2178 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
2179 efx->rx_hash_key[i];
2180
2181 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2182 sizeof(keybuf), NULL, 0, NULL);
2183 }
2184
2185 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2186 {
2187 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2188
2189 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2190 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2191 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2192 }
2193
2194 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2195 unsigned *context_size)
2196 {
2197 u32 new_rx_rss_context;
2198 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2199 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2200 false, context_size);
2201
2202 if (rc != 0)
2203 return rc;
2204
2205 nic_data->rx_rss_context = new_rx_rss_context;
2206 nic_data->rx_rss_context_exclusive = false;
2207 efx_set_default_rx_indir_table(efx);
2208 return 0;
2209 }
2210
2211 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2212 const u32 *rx_indir_table)
2213 {
2214 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2215 int rc;
2216 u32 new_rx_rss_context;
2217
2218 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2219 !nic_data->rx_rss_context_exclusive) {
2220 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2221 true, NULL);
2222 if (rc == -EOPNOTSUPP)
2223 return rc;
2224 else if (rc != 0)
2225 goto fail1;
2226 } else {
2227 new_rx_rss_context = nic_data->rx_rss_context;
2228 }
2229
2230 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2231 rx_indir_table);
2232 if (rc != 0)
2233 goto fail2;
2234
2235 if (nic_data->rx_rss_context != new_rx_rss_context)
2236 efx_ef10_rx_free_indir_table(efx);
2237 nic_data->rx_rss_context = new_rx_rss_context;
2238 nic_data->rx_rss_context_exclusive = true;
2239 if (rx_indir_table != efx->rx_indir_table)
2240 memcpy(efx->rx_indir_table, rx_indir_table,
2241 sizeof(efx->rx_indir_table));
2242 return 0;
2243
2244 fail2:
2245 if (new_rx_rss_context != nic_data->rx_rss_context)
2246 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2247 fail1:
2248 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2249 return rc;
2250 }
2251
2252 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2253 const u32 *rx_indir_table)
2254 {
2255 int rc;
2256
2257 if (efx->rss_spread == 1)
2258 return 0;
2259
2260 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2261
2262 if (rc == -ENOBUFS && !user) {
2263 unsigned context_size;
2264 bool mismatch = false;
2265 size_t i;
2266
2267 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2268 i++)
2269 mismatch = rx_indir_table[i] !=
2270 ethtool_rxfh_indir_default(i, efx->rss_spread);
2271
2272 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2273 if (rc == 0) {
2274 if (context_size != efx->rss_spread)
2275 netif_warn(efx, probe, efx->net_dev,
2276 "Could not allocate an exclusive RSS"
2277 " context; allocated a shared one of"
2278 " different size."
2279 " Wanted %u, got %u.\n",
2280 efx->rss_spread, context_size);
2281 else if (mismatch)
2282 netif_warn(efx, probe, efx->net_dev,
2283 "Could not allocate an exclusive RSS"
2284 " context; allocated a shared one but"
2285 " could not apply custom"
2286 " indirection.\n");
2287 else
2288 netif_info(efx, probe, efx->net_dev,
2289 "Could not allocate an exclusive RSS"
2290 " context; allocated a shared one.\n");
2291 }
2292 }
2293 return rc;
2294 }
2295
2296 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2297 const u32 *rx_indir_table
2298 __attribute__ ((unused)))
2299 {
2300 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2301
2302 if (user)
2303 return -EOPNOTSUPP;
2304 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2305 return 0;
2306 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2307 }
2308
2309 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2310 {
2311 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2312 (rx_queue->ptr_mask + 1) *
2313 sizeof(efx_qword_t),
2314 GFP_KERNEL);
2315 }
2316
2317 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2318 {
2319 MCDI_DECLARE_BUF(inbuf,
2320 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2321 EFX_BUF_SIZE));
2322 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2323 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2324 struct efx_nic *efx = rx_queue->efx;
2325 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2326 size_t inlen;
2327 dma_addr_t dma_addr;
2328 int rc;
2329 int i;
2330 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2331
2332 rx_queue->scatter_n = 0;
2333 rx_queue->scatter_len = 0;
2334
2335 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2336 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2337 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2338 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2339 efx_rx_queue_index(rx_queue));
2340 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2341 INIT_RXQ_IN_FLAG_PREFIX, 1,
2342 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2343 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2344 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2345
2346 dma_addr = rx_queue->rxd.buf.dma_addr;
2347
2348 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2349 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2350
2351 for (i = 0; i < entries; ++i) {
2352 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2353 dma_addr += EFX_BUF_SIZE;
2354 }
2355
2356 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2357
2358 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2359 NULL, 0, NULL);
2360 if (rc)
2361 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2362 efx_rx_queue_index(rx_queue));
2363 }
2364
2365 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2366 {
2367 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2368 MCDI_DECLARE_BUF_ERR(outbuf);
2369 struct efx_nic *efx = rx_queue->efx;
2370 size_t outlen;
2371 int rc;
2372
2373 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2374 efx_rx_queue_index(rx_queue));
2375
2376 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2377 outbuf, sizeof(outbuf), &outlen);
2378
2379 if (rc && rc != -EALREADY)
2380 goto fail;
2381
2382 return;
2383
2384 fail:
2385 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2386 outbuf, outlen, rc);
2387 }
2388
2389 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2390 {
2391 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2392 }
2393
2394 /* This creates an entry in the RX descriptor queue */
2395 static inline void
2396 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2397 {
2398 struct efx_rx_buffer *rx_buf;
2399 efx_qword_t *rxd;
2400
2401 rxd = efx_rx_desc(rx_queue, index);
2402 rx_buf = efx_rx_buffer(rx_queue, index);
2403 EFX_POPULATE_QWORD_2(*rxd,
2404 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2405 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2406 }
2407
2408 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2409 {
2410 struct efx_nic *efx = rx_queue->efx;
2411 unsigned int write_count;
2412 efx_dword_t reg;
2413
2414 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2415 write_count = rx_queue->added_count & ~7;
2416 if (rx_queue->notified_count == write_count)
2417 return;
2418
2419 do
2420 efx_ef10_build_rx_desc(
2421 rx_queue,
2422 rx_queue->notified_count & rx_queue->ptr_mask);
2423 while (++rx_queue->notified_count != write_count);
2424
2425 wmb();
2426 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2427 write_count & rx_queue->ptr_mask);
2428 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2429 efx_rx_queue_index(rx_queue));
2430 }
2431
2432 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2433
2434 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2435 {
2436 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2437 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2438 efx_qword_t event;
2439
2440 EFX_POPULATE_QWORD_2(event,
2441 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2442 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2443
2444 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2445
2446 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2447 * already swapped the data to little-endian order.
2448 */
2449 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2450 sizeof(efx_qword_t));
2451
2452 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2453 inbuf, sizeof(inbuf), 0,
2454 efx_ef10_rx_defer_refill_complete, 0);
2455 }
2456
2457 static void
2458 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2459 int rc, efx_dword_t *outbuf,
2460 size_t outlen_actual)
2461 {
2462 /* nothing to do */
2463 }
2464
2465 static int efx_ef10_ev_probe(struct efx_channel *channel)
2466 {
2467 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2468 (channel->eventq_mask + 1) *
2469 sizeof(efx_qword_t),
2470 GFP_KERNEL);
2471 }
2472
2473 static void efx_ef10_ev_fini(struct efx_channel *channel)
2474 {
2475 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2476 MCDI_DECLARE_BUF_ERR(outbuf);
2477 struct efx_nic *efx = channel->efx;
2478 size_t outlen;
2479 int rc;
2480
2481 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2482
2483 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2484 outbuf, sizeof(outbuf), &outlen);
2485
2486 if (rc && rc != -EALREADY)
2487 goto fail;
2488
2489 return;
2490
2491 fail:
2492 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2493 outbuf, outlen, rc);
2494 }
2495
2496 static int efx_ef10_ev_init(struct efx_channel *channel)
2497 {
2498 MCDI_DECLARE_BUF(inbuf,
2499 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2500 EFX_BUF_SIZE));
2501 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2502 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2503 struct efx_nic *efx = channel->efx;
2504 struct efx_ef10_nic_data *nic_data;
2505 bool supports_rx_merge;
2506 size_t inlen, outlen;
2507 unsigned int enabled, implemented;
2508 dma_addr_t dma_addr;
2509 int rc;
2510 int i;
2511
2512 nic_data = efx->nic_data;
2513 supports_rx_merge =
2514 !!(nic_data->datapath_caps &
2515 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2516
2517 /* Fill event queue with all ones (i.e. empty events) */
2518 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2519
2520 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2521 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2522 /* INIT_EVQ expects index in vector table, not absolute */
2523 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2524 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2525 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2526 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2527 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2528 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2529 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2530 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2531 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2532 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2533 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2534 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2535 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2536
2537 dma_addr = channel->eventq.buf.dma_addr;
2538 for (i = 0; i < entries; ++i) {
2539 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2540 dma_addr += EFX_BUF_SIZE;
2541 }
2542
2543 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2544
2545 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2546 outbuf, sizeof(outbuf), &outlen);
2547 /* IRQ return is ignored */
2548 if (channel->channel || rc)
2549 return rc;
2550
2551 /* Successfully created event queue on channel 0 */
2552 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2553 if (rc == -ENOSYS) {
2554 /* GET_WORKAROUNDS was implemented before the bug26807
2555 * workaround, thus the latter must be unavailable in this fw
2556 */
2557 nic_data->workaround_26807 = false;
2558 rc = 0;
2559 } else if (rc) {
2560 goto fail;
2561 } else {
2562 nic_data->workaround_26807 =
2563 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2564
2565 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2566 !nic_data->workaround_26807) {
2567 unsigned int flags;
2568
2569 rc = efx_mcdi_set_workaround(efx,
2570 MC_CMD_WORKAROUND_BUG26807,
2571 true, &flags);
2572
2573 if (!rc) {
2574 if (flags &
2575 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2576 netif_info(efx, drv, efx->net_dev,
2577 "other functions on NIC have been reset\n");
2578
2579 /* With MCFW v4.6.x and earlier, the
2580 * boot count will have incremented,
2581 * so re-read the warm_boot_count
2582 * value now to ensure this function
2583 * doesn't think it has changed next
2584 * time it checks.
2585 */
2586 rc = efx_ef10_get_warm_boot_count(efx);
2587 if (rc >= 0) {
2588 nic_data->warm_boot_count = rc;
2589 rc = 0;
2590 }
2591 }
2592 nic_data->workaround_26807 = true;
2593 } else if (rc == -EPERM) {
2594 rc = 0;
2595 }
2596 }
2597 }
2598
2599 if (!rc)
2600 return 0;
2601
2602 fail:
2603 efx_ef10_ev_fini(channel);
2604 return rc;
2605 }
2606
2607 static void efx_ef10_ev_remove(struct efx_channel *channel)
2608 {
2609 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2610 }
2611
2612 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2613 unsigned int rx_queue_label)
2614 {
2615 struct efx_nic *efx = rx_queue->efx;
2616
2617 netif_info(efx, hw, efx->net_dev,
2618 "rx event arrived on queue %d labeled as queue %u\n",
2619 efx_rx_queue_index(rx_queue), rx_queue_label);
2620
2621 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2622 }
2623
2624 static void
2625 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2626 unsigned int actual, unsigned int expected)
2627 {
2628 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2629 struct efx_nic *efx = rx_queue->efx;
2630
2631 netif_info(efx, hw, efx->net_dev,
2632 "dropped %d events (index=%d expected=%d)\n",
2633 dropped, actual, expected);
2634
2635 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2636 }
2637
2638 /* partially received RX was aborted. clean up. */
2639 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2640 {
2641 unsigned int rx_desc_ptr;
2642
2643 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2644 "scattered RX aborted (dropping %u buffers)\n",
2645 rx_queue->scatter_n);
2646
2647 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2648
2649 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2650 0, EFX_RX_PKT_DISCARD);
2651
2652 rx_queue->removed_count += rx_queue->scatter_n;
2653 rx_queue->scatter_n = 0;
2654 rx_queue->scatter_len = 0;
2655 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2656 }
2657
2658 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2659 const efx_qword_t *event)
2660 {
2661 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2662 unsigned int n_descs, n_packets, i;
2663 struct efx_nic *efx = channel->efx;
2664 struct efx_rx_queue *rx_queue;
2665 bool rx_cont;
2666 u16 flags = 0;
2667
2668 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2669 return 0;
2670
2671 /* Basic packet information */
2672 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2673 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2674 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2675 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2676 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2677
2678 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2679 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2680 EFX_QWORD_FMT "\n",
2681 EFX_QWORD_VAL(*event));
2682
2683 rx_queue = efx_channel_get_rx_queue(channel);
2684
2685 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2686 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2687
2688 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2689 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2690
2691 if (n_descs != rx_queue->scatter_n + 1) {
2692 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2693
2694 /* detect rx abort */
2695 if (unlikely(n_descs == rx_queue->scatter_n)) {
2696 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2697 netdev_WARN(efx->net_dev,
2698 "invalid RX abort: scatter_n=%u event="
2699 EFX_QWORD_FMT "\n",
2700 rx_queue->scatter_n,
2701 EFX_QWORD_VAL(*event));
2702 efx_ef10_handle_rx_abort(rx_queue);
2703 return 0;
2704 }
2705
2706 /* Check that RX completion merging is valid, i.e.
2707 * the current firmware supports it and this is a
2708 * non-scattered packet.
2709 */
2710 if (!(nic_data->datapath_caps &
2711 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2712 rx_queue->scatter_n != 0 || rx_cont) {
2713 efx_ef10_handle_rx_bad_lbits(
2714 rx_queue, next_ptr_lbits,
2715 (rx_queue->removed_count +
2716 rx_queue->scatter_n + 1) &
2717 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2718 return 0;
2719 }
2720
2721 /* Merged completion for multiple non-scattered packets */
2722 rx_queue->scatter_n = 1;
2723 rx_queue->scatter_len = 0;
2724 n_packets = n_descs;
2725 ++channel->n_rx_merge_events;
2726 channel->n_rx_merge_packets += n_packets;
2727 flags |= EFX_RX_PKT_PREFIX_LEN;
2728 } else {
2729 ++rx_queue->scatter_n;
2730 rx_queue->scatter_len += rx_bytes;
2731 if (rx_cont)
2732 return 0;
2733 n_packets = 1;
2734 }
2735
2736 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2737 flags |= EFX_RX_PKT_DISCARD;
2738
2739 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2740 channel->n_rx_ip_hdr_chksum_err += n_packets;
2741 } else if (unlikely(EFX_QWORD_FIELD(*event,
2742 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2743 channel->n_rx_tcp_udp_chksum_err += n_packets;
2744 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2745 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2746 flags |= EFX_RX_PKT_CSUMMED;
2747 }
2748
2749 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2750 flags |= EFX_RX_PKT_TCP;
2751
2752 channel->irq_mod_score += 2 * n_packets;
2753
2754 /* Handle received packet(s) */
2755 for (i = 0; i < n_packets; i++) {
2756 efx_rx_packet(rx_queue,
2757 rx_queue->removed_count & rx_queue->ptr_mask,
2758 rx_queue->scatter_n, rx_queue->scatter_len,
2759 flags);
2760 rx_queue->removed_count += rx_queue->scatter_n;
2761 }
2762
2763 rx_queue->scatter_n = 0;
2764 rx_queue->scatter_len = 0;
2765
2766 return n_packets;
2767 }
2768
2769 static int
2770 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2771 {
2772 struct efx_nic *efx = channel->efx;
2773 struct efx_tx_queue *tx_queue;
2774 unsigned int tx_ev_desc_ptr;
2775 unsigned int tx_ev_q_label;
2776 int tx_descs = 0;
2777
2778 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2779 return 0;
2780
2781 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2782 return 0;
2783
2784 /* Transmit completion */
2785 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2786 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2787 tx_queue = efx_channel_get_tx_queue(channel,
2788 tx_ev_q_label % EFX_TXQ_TYPES);
2789 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2790 tx_queue->ptr_mask);
2791 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2792
2793 return tx_descs;
2794 }
2795
2796 static void
2797 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2798 {
2799 struct efx_nic *efx = channel->efx;
2800 int subcode;
2801
2802 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2803
2804 switch (subcode) {
2805 case ESE_DZ_DRV_TIMER_EV:
2806 case ESE_DZ_DRV_WAKE_UP_EV:
2807 break;
2808 case ESE_DZ_DRV_START_UP_EV:
2809 /* event queue init complete. ok. */
2810 break;
2811 default:
2812 netif_err(efx, hw, efx->net_dev,
2813 "channel %d unknown driver event type %d"
2814 " (data " EFX_QWORD_FMT ")\n",
2815 channel->channel, subcode,
2816 EFX_QWORD_VAL(*event));
2817
2818 }
2819 }
2820
2821 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2822 efx_qword_t *event)
2823 {
2824 struct efx_nic *efx = channel->efx;
2825 u32 subcode;
2826
2827 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2828
2829 switch (subcode) {
2830 case EFX_EF10_TEST:
2831 channel->event_test_cpu = raw_smp_processor_id();
2832 break;
2833 case EFX_EF10_REFILL:
2834 /* The queue must be empty, so we won't receive any rx
2835 * events, so efx_process_channel() won't refill the
2836 * queue. Refill it here
2837 */
2838 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
2839 break;
2840 default:
2841 netif_err(efx, hw, efx->net_dev,
2842 "channel %d unknown driver event type %u"
2843 " (data " EFX_QWORD_FMT ")\n",
2844 channel->channel, (unsigned) subcode,
2845 EFX_QWORD_VAL(*event));
2846 }
2847 }
2848
2849 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2850 {
2851 struct efx_nic *efx = channel->efx;
2852 efx_qword_t event, *p_event;
2853 unsigned int read_ptr;
2854 int ev_code;
2855 int tx_descs = 0;
2856 int spent = 0;
2857
2858 if (quota <= 0)
2859 return spent;
2860
2861 read_ptr = channel->eventq_read_ptr;
2862
2863 for (;;) {
2864 p_event = efx_event(channel, read_ptr);
2865 event = *p_event;
2866
2867 if (!efx_event_present(&event))
2868 break;
2869
2870 EFX_SET_QWORD(*p_event);
2871
2872 ++read_ptr;
2873
2874 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2875
2876 netif_vdbg(efx, drv, efx->net_dev,
2877 "processing event on %d " EFX_QWORD_FMT "\n",
2878 channel->channel, EFX_QWORD_VAL(event));
2879
2880 switch (ev_code) {
2881 case ESE_DZ_EV_CODE_MCDI_EV:
2882 efx_mcdi_process_event(channel, &event);
2883 break;
2884 case ESE_DZ_EV_CODE_RX_EV:
2885 spent += efx_ef10_handle_rx_event(channel, &event);
2886 if (spent >= quota) {
2887 /* XXX can we split a merged event to
2888 * avoid going over-quota?
2889 */
2890 spent = quota;
2891 goto out;
2892 }
2893 break;
2894 case ESE_DZ_EV_CODE_TX_EV:
2895 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2896 if (tx_descs > efx->txq_entries) {
2897 spent = quota;
2898 goto out;
2899 } else if (++spent == quota) {
2900 goto out;
2901 }
2902 break;
2903 case ESE_DZ_EV_CODE_DRIVER_EV:
2904 efx_ef10_handle_driver_event(channel, &event);
2905 if (++spent == quota)
2906 goto out;
2907 break;
2908 case EFX_EF10_DRVGEN_EV:
2909 efx_ef10_handle_driver_generated_event(channel, &event);
2910 break;
2911 default:
2912 netif_err(efx, hw, efx->net_dev,
2913 "channel %d unknown event type %d"
2914 " (data " EFX_QWORD_FMT ")\n",
2915 channel->channel, ev_code,
2916 EFX_QWORD_VAL(event));
2917 }
2918 }
2919
2920 out:
2921 channel->eventq_read_ptr = read_ptr;
2922 return spent;
2923 }
2924
2925 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2926 {
2927 struct efx_nic *efx = channel->efx;
2928 efx_dword_t rptr;
2929
2930 if (EFX_EF10_WORKAROUND_35388(efx)) {
2931 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2932 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2933 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2934 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2935
2936 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2937 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2938 ERF_DD_EVQ_IND_RPTR,
2939 (channel->eventq_read_ptr &
2940 channel->eventq_mask) >>
2941 ERF_DD_EVQ_IND_RPTR_WIDTH);
2942 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2943 channel->channel);
2944 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2945 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2946 ERF_DD_EVQ_IND_RPTR,
2947 channel->eventq_read_ptr &
2948 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2949 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2950 channel->channel);
2951 } else {
2952 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2953 channel->eventq_read_ptr &
2954 channel->eventq_mask);
2955 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2956 }
2957 }
2958
2959 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2960 {
2961 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2962 struct efx_nic *efx = channel->efx;
2963 efx_qword_t event;
2964 int rc;
2965
2966 EFX_POPULATE_QWORD_2(event,
2967 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2968 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2969
2970 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2971
2972 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2973 * already swapped the data to little-endian order.
2974 */
2975 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2976 sizeof(efx_qword_t));
2977
2978 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2979 NULL, 0, NULL);
2980 if (rc != 0)
2981 goto fail;
2982
2983 return;
2984
2985 fail:
2986 WARN_ON(true);
2987 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2988 }
2989
2990 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2991 {
2992 if (atomic_dec_and_test(&efx->active_queues))
2993 wake_up(&efx->flush_wq);
2994
2995 WARN_ON(atomic_read(&efx->active_queues) < 0);
2996 }
2997
2998 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2999 {
3000 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3001 struct efx_channel *channel;
3002 struct efx_tx_queue *tx_queue;
3003 struct efx_rx_queue *rx_queue;
3004 int pending;
3005
3006 /* If the MC has just rebooted, the TX/RX queues will have already been
3007 * torn down, but efx->active_queues needs to be set to zero.
3008 */
3009 if (nic_data->must_realloc_vis) {
3010 atomic_set(&efx->active_queues, 0);
3011 return 0;
3012 }
3013
3014 /* Do not attempt to write to the NIC during EEH recovery */
3015 if (efx->state != STATE_RECOVERY) {
3016 efx_for_each_channel(channel, efx) {
3017 efx_for_each_channel_rx_queue(rx_queue, channel)
3018 efx_ef10_rx_fini(rx_queue);
3019 efx_for_each_channel_tx_queue(tx_queue, channel)
3020 efx_ef10_tx_fini(tx_queue);
3021 }
3022
3023 wait_event_timeout(efx->flush_wq,
3024 atomic_read(&efx->active_queues) == 0,
3025 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3026 pending = atomic_read(&efx->active_queues);
3027 if (pending) {
3028 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3029 pending);
3030 return -ETIMEDOUT;
3031 }
3032 }
3033
3034 return 0;
3035 }
3036
3037 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3038 {
3039 atomic_set(&efx->active_queues, 0);
3040 }
3041
3042 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3043 const struct efx_filter_spec *right)
3044 {
3045 if ((left->match_flags ^ right->match_flags) |
3046 ((left->flags ^ right->flags) &
3047 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3048 return false;
3049
3050 return memcmp(&left->outer_vid, &right->outer_vid,
3051 sizeof(struct efx_filter_spec) -
3052 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3053 }
3054
3055 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3056 {
3057 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3058 return jhash2((const u32 *)&spec->outer_vid,
3059 (sizeof(struct efx_filter_spec) -
3060 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3061 0);
3062 /* XXX should we randomise the initval? */
3063 }
3064
3065 /* Decide whether a filter should be exclusive or else should allow
3066 * delivery to additional recipients. Currently we decide that
3067 * filters for specific local unicast MAC and IP addresses are
3068 * exclusive.
3069 */
3070 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3071 {
3072 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3073 !is_multicast_ether_addr(spec->loc_mac))
3074 return true;
3075
3076 if ((spec->match_flags &
3077 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3078 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3079 if (spec->ether_type == htons(ETH_P_IP) &&
3080 !ipv4_is_multicast(spec->loc_host[0]))
3081 return true;
3082 if (spec->ether_type == htons(ETH_P_IPV6) &&
3083 ((const u8 *)spec->loc_host)[0] != 0xff)
3084 return true;
3085 }
3086
3087 return false;
3088 }
3089
3090 static struct efx_filter_spec *
3091 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3092 unsigned int filter_idx)
3093 {
3094 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3095 ~EFX_EF10_FILTER_FLAGS);
3096 }
3097
3098 static unsigned int
3099 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3100 unsigned int filter_idx)
3101 {
3102 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3103 }
3104
3105 static void
3106 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3107 unsigned int filter_idx,
3108 const struct efx_filter_spec *spec,
3109 unsigned int flags)
3110 {
3111 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3112 }
3113
3114 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3115 const struct efx_filter_spec *spec,
3116 efx_dword_t *inbuf, u64 handle,
3117 bool replacing)
3118 {
3119 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3120 u32 flags = spec->flags;
3121
3122 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
3123
3124 /* Remove RSS flag if we don't have an RSS context. */
3125 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3126 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3127 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3128 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3129
3130 if (replacing) {
3131 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3132 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3133 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3134 } else {
3135 u32 match_fields = 0;
3136
3137 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3138 efx_ef10_filter_is_exclusive(spec) ?
3139 MC_CMD_FILTER_OP_IN_OP_INSERT :
3140 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3141
3142 /* Convert match flags and values. Unlike almost
3143 * everything else in MCDI, these fields are in
3144 * network byte order.
3145 */
3146 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3147 match_fields |=
3148 is_multicast_ether_addr(spec->loc_mac) ?
3149 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
3150 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3151 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3152 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3153 match_fields |= \
3154 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3155 mcdi_field ## _LBN; \
3156 BUILD_BUG_ON( \
3157 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3158 sizeof(spec->gen_field)); \
3159 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3160 &spec->gen_field, sizeof(spec->gen_field)); \
3161 }
3162 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3163 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3164 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3165 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3166 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3167 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3168 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3169 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3170 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3171 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3172 #undef COPY_FIELD
3173 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3174 match_fields);
3175 }
3176
3177 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
3178 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3179 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3180 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3181 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
3182 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
3183 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3184 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
3185 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3186 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3187 0 : spec->dmaq_id);
3188 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
3189 (flags & EFX_FILTER_FLAG_RX_RSS) ?
3190 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3191 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3192 if (flags & EFX_FILTER_FLAG_RX_RSS)
3193 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3194 spec->rss_context !=
3195 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3196 spec->rss_context : nic_data->rx_rss_context);
3197 }
3198
3199 static int efx_ef10_filter_push(struct efx_nic *efx,
3200 const struct efx_filter_spec *spec,
3201 u64 *handle, bool replacing)
3202 {
3203 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3204 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3205 int rc;
3206
3207 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3208 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3209 outbuf, sizeof(outbuf), NULL);
3210 if (rc == 0)
3211 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3212 if (rc == -ENOSPC)
3213 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3214 return rc;
3215 }
3216
3217 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
3218 enum efx_filter_match_flags match_flags)
3219 {
3220 unsigned int match_pri;
3221
3222 for (match_pri = 0;
3223 match_pri < table->rx_match_count;
3224 match_pri++)
3225 if (table->rx_match_flags[match_pri] == match_flags)
3226 return match_pri;
3227
3228 return -EPROTONOSUPPORT;
3229 }
3230
3231 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3232 struct efx_filter_spec *spec,
3233 bool replace_equal)
3234 {
3235 struct efx_ef10_filter_table *table = efx->filter_state;
3236 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3237 struct efx_filter_spec *saved_spec;
3238 unsigned int match_pri, hash;
3239 unsigned int priv_flags;
3240 bool replacing = false;
3241 int ins_index = -1;
3242 DEFINE_WAIT(wait);
3243 bool is_mc_recip;
3244 s32 rc;
3245
3246 /* For now, only support RX filters */
3247 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3248 EFX_FILTER_FLAG_RX)
3249 return -EINVAL;
3250
3251 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
3252 if (rc < 0)
3253 return rc;
3254 match_pri = rc;
3255
3256 hash = efx_ef10_filter_hash(spec);
3257 is_mc_recip = efx_filter_is_mc_recipient(spec);
3258 if (is_mc_recip)
3259 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3260
3261 /* Find any existing filters with the same match tuple or
3262 * else a free slot to insert at. If any of them are busy,
3263 * we have to wait and retry.
3264 */
3265 for (;;) {
3266 unsigned int depth = 1;
3267 unsigned int i;
3268
3269 spin_lock_bh(&efx->filter_lock);
3270
3271 for (;;) {
3272 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3273 saved_spec = efx_ef10_filter_entry_spec(table, i);
3274
3275 if (!saved_spec) {
3276 if (ins_index < 0)
3277 ins_index = i;
3278 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3279 if (table->entry[i].spec &
3280 EFX_EF10_FILTER_FLAG_BUSY)
3281 break;
3282 if (spec->priority < saved_spec->priority &&
3283 spec->priority != EFX_FILTER_PRI_AUTO) {
3284 rc = -EPERM;
3285 goto out_unlock;
3286 }
3287 if (!is_mc_recip) {
3288 /* This is the only one */
3289 if (spec->priority ==
3290 saved_spec->priority &&
3291 !replace_equal) {
3292 rc = -EEXIST;
3293 goto out_unlock;
3294 }
3295 ins_index = i;
3296 goto found;
3297 } else if (spec->priority >
3298 saved_spec->priority ||
3299 (spec->priority ==
3300 saved_spec->priority &&
3301 replace_equal)) {
3302 if (ins_index < 0)
3303 ins_index = i;
3304 else
3305 __set_bit(depth, mc_rem_map);
3306 }
3307 }
3308
3309 /* Once we reach the maximum search depth, use
3310 * the first suitable slot or return -EBUSY if
3311 * there was none
3312 */
3313 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3314 if (ins_index < 0) {
3315 rc = -EBUSY;
3316 goto out_unlock;
3317 }
3318 goto found;
3319 }
3320
3321 ++depth;
3322 }
3323
3324 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3325 spin_unlock_bh(&efx->filter_lock);
3326 schedule();
3327 }
3328
3329 found:
3330 /* Create a software table entry if necessary, and mark it
3331 * busy. We might yet fail to insert, but any attempt to
3332 * insert a conflicting filter while we're waiting for the
3333 * firmware must find the busy entry.
3334 */
3335 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3336 if (saved_spec) {
3337 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3338 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3339 /* Just make sure it won't be removed */
3340 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3341 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3342 table->entry[ins_index].spec &=
3343 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3344 rc = ins_index;
3345 goto out_unlock;
3346 }
3347 replacing = true;
3348 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3349 } else {
3350 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3351 if (!saved_spec) {
3352 rc = -ENOMEM;
3353 goto out_unlock;
3354 }
3355 *saved_spec = *spec;
3356 priv_flags = 0;
3357 }
3358 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3359 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3360
3361 /* Mark lower-priority multicast recipients busy prior to removal */
3362 if (is_mc_recip) {
3363 unsigned int depth, i;
3364
3365 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3366 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3367 if (test_bit(depth, mc_rem_map))
3368 table->entry[i].spec |=
3369 EFX_EF10_FILTER_FLAG_BUSY;
3370 }
3371 }
3372
3373 spin_unlock_bh(&efx->filter_lock);
3374
3375 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3376 replacing);
3377
3378 /* Finalise the software table entry */
3379 spin_lock_bh(&efx->filter_lock);
3380 if (rc == 0) {
3381 if (replacing) {
3382 /* Update the fields that may differ */
3383 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3384 saved_spec->flags |=
3385 EFX_FILTER_FLAG_RX_OVER_AUTO;
3386 saved_spec->priority = spec->priority;
3387 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3388 saved_spec->flags |= spec->flags;
3389 saved_spec->rss_context = spec->rss_context;
3390 saved_spec->dmaq_id = spec->dmaq_id;
3391 }
3392 } else if (!replacing) {
3393 kfree(saved_spec);
3394 saved_spec = NULL;
3395 }
3396 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3397
3398 /* Remove and finalise entries for lower-priority multicast
3399 * recipients
3400 */
3401 if (is_mc_recip) {
3402 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3403 unsigned int depth, i;
3404
3405 memset(inbuf, 0, sizeof(inbuf));
3406
3407 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3408 if (!test_bit(depth, mc_rem_map))
3409 continue;
3410
3411 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3412 saved_spec = efx_ef10_filter_entry_spec(table, i);
3413 priv_flags = efx_ef10_filter_entry_flags(table, i);
3414
3415 if (rc == 0) {
3416 spin_unlock_bh(&efx->filter_lock);
3417 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3418 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3419 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3420 table->entry[i].handle);
3421 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3422 inbuf, sizeof(inbuf),
3423 NULL, 0, NULL);
3424 spin_lock_bh(&efx->filter_lock);
3425 }
3426
3427 if (rc == 0) {
3428 kfree(saved_spec);
3429 saved_spec = NULL;
3430 priv_flags = 0;
3431 } else {
3432 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3433 }
3434 efx_ef10_filter_set_entry(table, i, saved_spec,
3435 priv_flags);
3436 }
3437 }
3438
3439 /* If successful, return the inserted filter ID */
3440 if (rc == 0)
3441 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3442
3443 wake_up_all(&table->waitq);
3444 out_unlock:
3445 spin_unlock_bh(&efx->filter_lock);
3446 finish_wait(&table->waitq, &wait);
3447 return rc;
3448 }
3449
3450 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3451 {
3452 /* no need to do anything here on EF10 */
3453 }
3454
3455 /* Remove a filter.
3456 * If !by_index, remove by ID
3457 * If by_index, remove by index
3458 * Filter ID may come from userland and must be range-checked.
3459 */
3460 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3461 unsigned int priority_mask,
3462 u32 filter_id, bool by_index)
3463 {
3464 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3465 struct efx_ef10_filter_table *table = efx->filter_state;
3466 MCDI_DECLARE_BUF(inbuf,
3467 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3468 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3469 struct efx_filter_spec *spec;
3470 DEFINE_WAIT(wait);
3471 int rc;
3472
3473 /* Find the software table entry and mark it busy. Don't
3474 * remove it yet; any attempt to update while we're waiting
3475 * for the firmware must find the busy entry.
3476 */
3477 for (;;) {
3478 spin_lock_bh(&efx->filter_lock);
3479 if (!(table->entry[filter_idx].spec &
3480 EFX_EF10_FILTER_FLAG_BUSY))
3481 break;
3482 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3483 spin_unlock_bh(&efx->filter_lock);
3484 schedule();
3485 }
3486
3487 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3488 if (!spec ||
3489 (!by_index &&
3490 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3491 filter_id / HUNT_FILTER_TBL_ROWS)) {
3492 rc = -ENOENT;
3493 goto out_unlock;
3494 }
3495
3496 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3497 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3498 /* Just remove flags */
3499 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3500 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3501 rc = 0;
3502 goto out_unlock;
3503 }
3504
3505 if (!(priority_mask & (1U << spec->priority))) {
3506 rc = -ENOENT;
3507 goto out_unlock;
3508 }
3509
3510 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3511 spin_unlock_bh(&efx->filter_lock);
3512
3513 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3514 /* Reset to an automatic filter */
3515
3516 struct efx_filter_spec new_spec = *spec;
3517
3518 new_spec.priority = EFX_FILTER_PRI_AUTO;
3519 new_spec.flags = (EFX_FILTER_FLAG_RX |
3520 (efx_rss_enabled(efx) ?
3521 EFX_FILTER_FLAG_RX_RSS : 0));
3522 new_spec.dmaq_id = 0;
3523 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3524 rc = efx_ef10_filter_push(efx, &new_spec,
3525 &table->entry[filter_idx].handle,
3526 true);
3527
3528 spin_lock_bh(&efx->filter_lock);
3529 if (rc == 0)
3530 *spec = new_spec;
3531 } else {
3532 /* Really remove the filter */
3533
3534 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3535 efx_ef10_filter_is_exclusive(spec) ?
3536 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3537 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3538 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3539 table->entry[filter_idx].handle);
3540 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3541 inbuf, sizeof(inbuf), NULL, 0, NULL);
3542
3543 spin_lock_bh(&efx->filter_lock);
3544 if (rc == 0) {
3545 kfree(spec);
3546 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3547 }
3548 }
3549
3550 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3551 wake_up_all(&table->waitq);
3552 out_unlock:
3553 spin_unlock_bh(&efx->filter_lock);
3554 finish_wait(&table->waitq, &wait);
3555 return rc;
3556 }
3557
3558 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3559 enum efx_filter_priority priority,
3560 u32 filter_id)
3561 {
3562 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3563 filter_id, false);
3564 }
3565
3566 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3567 {
3568 return filter_id % HUNT_FILTER_TBL_ROWS;
3569 }
3570
3571 static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3572 enum efx_filter_priority priority,
3573 u32 filter_id)
3574 {
3575 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3576 filter_id, true);
3577 }
3578
3579 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3580 enum efx_filter_priority priority,
3581 u32 filter_id, struct efx_filter_spec *spec)
3582 {
3583 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3584 struct efx_ef10_filter_table *table = efx->filter_state;
3585 const struct efx_filter_spec *saved_spec;
3586 int rc;
3587
3588 spin_lock_bh(&efx->filter_lock);
3589 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3590 if (saved_spec && saved_spec->priority == priority &&
3591 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3592 filter_id / HUNT_FILTER_TBL_ROWS) {
3593 *spec = *saved_spec;
3594 rc = 0;
3595 } else {
3596 rc = -ENOENT;
3597 }
3598 spin_unlock_bh(&efx->filter_lock);
3599 return rc;
3600 }
3601
3602 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3603 enum efx_filter_priority priority)
3604 {
3605 unsigned int priority_mask;
3606 unsigned int i;
3607 int rc;
3608
3609 priority_mask = (((1U << (priority + 1)) - 1) &
3610 ~(1U << EFX_FILTER_PRI_AUTO));
3611
3612 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3613 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3614 i, true);
3615 if (rc && rc != -ENOENT)
3616 return rc;
3617 }
3618
3619 return 0;
3620 }
3621
3622 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3623 enum efx_filter_priority priority)
3624 {
3625 struct efx_ef10_filter_table *table = efx->filter_state;
3626 unsigned int filter_idx;
3627 s32 count = 0;
3628
3629 spin_lock_bh(&efx->filter_lock);
3630 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3631 if (table->entry[filter_idx].spec &&
3632 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3633 priority)
3634 ++count;
3635 }
3636 spin_unlock_bh(&efx->filter_lock);
3637 return count;
3638 }
3639
3640 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3641 {
3642 struct efx_ef10_filter_table *table = efx->filter_state;
3643
3644 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3645 }
3646
3647 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3648 enum efx_filter_priority priority,
3649 u32 *buf, u32 size)
3650 {
3651 struct efx_ef10_filter_table *table = efx->filter_state;
3652 struct efx_filter_spec *spec;
3653 unsigned int filter_idx;
3654 s32 count = 0;
3655
3656 spin_lock_bh(&efx->filter_lock);
3657 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3658 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3659 if (spec && spec->priority == priority) {
3660 if (count == size) {
3661 count = -EMSGSIZE;
3662 break;
3663 }
3664 buf[count++] = (efx_ef10_filter_rx_match_pri(
3665 table, spec->match_flags) *
3666 HUNT_FILTER_TBL_ROWS +
3667 filter_idx);
3668 }
3669 }
3670 spin_unlock_bh(&efx->filter_lock);
3671 return count;
3672 }
3673
3674 #ifdef CONFIG_RFS_ACCEL
3675
3676 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3677
3678 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3679 struct efx_filter_spec *spec)
3680 {
3681 struct efx_ef10_filter_table *table = efx->filter_state;
3682 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3683 struct efx_filter_spec *saved_spec;
3684 unsigned int hash, i, depth = 1;
3685 bool replacing = false;
3686 int ins_index = -1;
3687 u64 cookie;
3688 s32 rc;
3689
3690 /* Must be an RX filter without RSS and not for a multicast
3691 * destination address (RFS only works for connected sockets).
3692 * These restrictions allow us to pass only a tiny amount of
3693 * data through to the completion function.
3694 */
3695 EFX_WARN_ON_PARANOID(spec->flags !=
3696 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3697 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3698 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3699
3700 hash = efx_ef10_filter_hash(spec);
3701
3702 spin_lock_bh(&efx->filter_lock);
3703
3704 /* Find any existing filter with the same match tuple or else
3705 * a free slot to insert at. If an existing filter is busy,
3706 * we have to give up.
3707 */
3708 for (;;) {
3709 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3710 saved_spec = efx_ef10_filter_entry_spec(table, i);
3711
3712 if (!saved_spec) {
3713 if (ins_index < 0)
3714 ins_index = i;
3715 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3716 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3717 rc = -EBUSY;
3718 goto fail_unlock;
3719 }
3720 if (spec->priority < saved_spec->priority) {
3721 rc = -EPERM;
3722 goto fail_unlock;
3723 }
3724 ins_index = i;
3725 break;
3726 }
3727
3728 /* Once we reach the maximum search depth, use the
3729 * first suitable slot or return -EBUSY if there was
3730 * none
3731 */
3732 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3733 if (ins_index < 0) {
3734 rc = -EBUSY;
3735 goto fail_unlock;
3736 }
3737 break;
3738 }
3739
3740 ++depth;
3741 }
3742
3743 /* Create a software table entry if necessary, and mark it
3744 * busy. We might yet fail to insert, but any attempt to
3745 * insert a conflicting filter while we're waiting for the
3746 * firmware must find the busy entry.
3747 */
3748 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3749 if (saved_spec) {
3750 replacing = true;
3751 } else {
3752 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3753 if (!saved_spec) {
3754 rc = -ENOMEM;
3755 goto fail_unlock;
3756 }
3757 *saved_spec = *spec;
3758 }
3759 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3760 EFX_EF10_FILTER_FLAG_BUSY);
3761
3762 spin_unlock_bh(&efx->filter_lock);
3763
3764 /* Pack up the variables needed on completion */
3765 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3766
3767 efx_ef10_filter_push_prep(efx, spec, inbuf,
3768 table->entry[ins_index].handle, replacing);
3769 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3770 MC_CMD_FILTER_OP_OUT_LEN,
3771 efx_ef10_filter_rfs_insert_complete, cookie);
3772
3773 return ins_index;
3774
3775 fail_unlock:
3776 spin_unlock_bh(&efx->filter_lock);
3777 return rc;
3778 }
3779
3780 static void
3781 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3782 int rc, efx_dword_t *outbuf,
3783 size_t outlen_actual)
3784 {
3785 struct efx_ef10_filter_table *table = efx->filter_state;
3786 unsigned int ins_index, dmaq_id;
3787 struct efx_filter_spec *spec;
3788 bool replacing;
3789
3790 /* Unpack the cookie */
3791 replacing = cookie >> 31;
3792 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3793 dmaq_id = cookie & 0xffff;
3794
3795 spin_lock_bh(&efx->filter_lock);
3796 spec = efx_ef10_filter_entry_spec(table, ins_index);
3797 if (rc == 0) {
3798 table->entry[ins_index].handle =
3799 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3800 if (replacing)
3801 spec->dmaq_id = dmaq_id;
3802 } else if (!replacing) {
3803 kfree(spec);
3804 spec = NULL;
3805 }
3806 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3807 spin_unlock_bh(&efx->filter_lock);
3808
3809 wake_up_all(&table->waitq);
3810 }
3811
3812 static void
3813 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3814 unsigned long filter_idx,
3815 int rc, efx_dword_t *outbuf,
3816 size_t outlen_actual);
3817
3818 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3819 unsigned int filter_idx)
3820 {
3821 struct efx_ef10_filter_table *table = efx->filter_state;
3822 struct efx_filter_spec *spec =
3823 efx_ef10_filter_entry_spec(table, filter_idx);
3824 MCDI_DECLARE_BUF(inbuf,
3825 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3826 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3827
3828 if (!spec ||
3829 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3830 spec->priority != EFX_FILTER_PRI_HINT ||
3831 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3832 flow_id, filter_idx))
3833 return false;
3834
3835 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3836 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3837 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3838 table->entry[filter_idx].handle);
3839 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3840 efx_ef10_filter_rfs_expire_complete, filter_idx))
3841 return false;
3842
3843 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3844 return true;
3845 }
3846
3847 static void
3848 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3849 unsigned long filter_idx,
3850 int rc, efx_dword_t *outbuf,
3851 size_t outlen_actual)
3852 {
3853 struct efx_ef10_filter_table *table = efx->filter_state;
3854 struct efx_filter_spec *spec =
3855 efx_ef10_filter_entry_spec(table, filter_idx);
3856
3857 spin_lock_bh(&efx->filter_lock);
3858 if (rc == 0) {
3859 kfree(spec);
3860 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3861 }
3862 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3863 wake_up_all(&table->waitq);
3864 spin_unlock_bh(&efx->filter_lock);
3865 }
3866
3867 #endif /* CONFIG_RFS_ACCEL */
3868
3869 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3870 {
3871 int match_flags = 0;
3872
3873 #define MAP_FLAG(gen_flag, mcdi_field) { \
3874 u32 old_mcdi_flags = mcdi_flags; \
3875 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3876 mcdi_field ## _LBN); \
3877 if (mcdi_flags != old_mcdi_flags) \
3878 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3879 }
3880 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3881 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3882 MAP_FLAG(REM_HOST, SRC_IP);
3883 MAP_FLAG(LOC_HOST, DST_IP);
3884 MAP_FLAG(REM_MAC, SRC_MAC);
3885 MAP_FLAG(REM_PORT, SRC_PORT);
3886 MAP_FLAG(LOC_MAC, DST_MAC);
3887 MAP_FLAG(LOC_PORT, DST_PORT);
3888 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3889 MAP_FLAG(INNER_VID, INNER_VLAN);
3890 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3891 MAP_FLAG(IP_PROTO, IP_PROTO);
3892 #undef MAP_FLAG
3893
3894 /* Did we map them all? */
3895 if (mcdi_flags)
3896 return -EINVAL;
3897
3898 return match_flags;
3899 }
3900
3901 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
3902 {
3903 struct efx_ef10_filter_table *table = efx->filter_state;
3904 struct efx_ef10_filter_vlan *vlan, *next_vlan;
3905
3906 /* See comment in efx_ef10_filter_table_remove() */
3907 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
3908 return;
3909
3910 if (!table)
3911 return;
3912
3913 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
3914 efx_ef10_filter_del_vlan_internal(efx, vlan);
3915 }
3916
3917 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3918 {
3919 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3920 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3921 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3922 unsigned int pd_match_pri, pd_match_count;
3923 struct efx_ef10_filter_table *table;
3924 struct efx_ef10_vlan *vlan;
3925 size_t outlen;
3926 int rc;
3927
3928 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
3929 return -EINVAL;
3930
3931 if (efx->filter_state) /* already probed */
3932 return 0;
3933
3934 table = kzalloc(sizeof(*table), GFP_KERNEL);
3935 if (!table)
3936 return -ENOMEM;
3937
3938 /* Find out which RX filter types are supported, and their priorities */
3939 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3940 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3941 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3942 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3943 &outlen);
3944 if (rc)
3945 goto fail;
3946 pd_match_count = MCDI_VAR_ARRAY_LEN(
3947 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3948 table->rx_match_count = 0;
3949
3950 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3951 u32 mcdi_flags =
3952 MCDI_ARRAY_DWORD(
3953 outbuf,
3954 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3955 pd_match_pri);
3956 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3957 if (rc < 0) {
3958 netif_dbg(efx, probe, efx->net_dev,
3959 "%s: fw flags %#x pri %u not supported in driver\n",
3960 __func__, mcdi_flags, pd_match_pri);
3961 } else {
3962 netif_dbg(efx, probe, efx->net_dev,
3963 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3964 __func__, mcdi_flags, pd_match_pri,
3965 rc, table->rx_match_count);
3966 table->rx_match_flags[table->rx_match_count++] = rc;
3967 }
3968 }
3969
3970 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3971 if (!table->entry) {
3972 rc = -ENOMEM;
3973 goto fail;
3974 }
3975
3976 table->mc_promisc_last = false;
3977 table->vlan_filter =
3978 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
3979 INIT_LIST_HEAD(&table->vlan_list);
3980
3981 efx->filter_state = table;
3982 init_waitqueue_head(&table->waitq);
3983
3984 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
3985 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
3986 if (rc)
3987 goto fail_add_vlan;
3988 }
3989
3990 return 0;
3991
3992 fail_add_vlan:
3993 efx_ef10_filter_cleanup_vlans(efx);
3994 efx->filter_state = NULL;
3995 fail:
3996 kfree(table);
3997 return rc;
3998 }
3999
4000 /* Caller must hold efx->filter_sem for read if race against
4001 * efx_ef10_filter_table_remove() is possible
4002 */
4003 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4004 {
4005 struct efx_ef10_filter_table *table = efx->filter_state;
4006 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4007 struct efx_filter_spec *spec;
4008 unsigned int filter_idx;
4009 bool failed = false;
4010 int rc;
4011
4012 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4013
4014 if (!nic_data->must_restore_filters)
4015 return;
4016
4017 if (!table)
4018 return;
4019
4020 spin_lock_bh(&efx->filter_lock);
4021
4022 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4023 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4024 if (!spec)
4025 continue;
4026
4027 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4028 spin_unlock_bh(&efx->filter_lock);
4029
4030 rc = efx_ef10_filter_push(efx, spec,
4031 &table->entry[filter_idx].handle,
4032 false);
4033 if (rc)
4034 failed = true;
4035
4036 spin_lock_bh(&efx->filter_lock);
4037 if (rc) {
4038 kfree(spec);
4039 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4040 } else {
4041 table->entry[filter_idx].spec &=
4042 ~EFX_EF10_FILTER_FLAG_BUSY;
4043 }
4044 }
4045
4046 spin_unlock_bh(&efx->filter_lock);
4047
4048 if (failed)
4049 netif_err(efx, hw, efx->net_dev,
4050 "unable to restore all filters\n");
4051 else
4052 nic_data->must_restore_filters = false;
4053 }
4054
4055 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4056 {
4057 struct efx_ef10_filter_table *table = efx->filter_state;
4058 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4059 struct efx_filter_spec *spec;
4060 unsigned int filter_idx;
4061 int rc;
4062
4063 efx_ef10_filter_cleanup_vlans(efx);
4064 efx->filter_state = NULL;
4065 /* If we were called without locking, then it's not safe to free
4066 * the table as others might be using it. So we just WARN, leak
4067 * the memory, and potentially get an inconsistent filter table
4068 * state.
4069 * This should never actually happen.
4070 */
4071 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4072 return;
4073
4074 if (!table)
4075 return;
4076
4077 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4078 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4079 if (!spec)
4080 continue;
4081
4082 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4083 efx_ef10_filter_is_exclusive(spec) ?
4084 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4085 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4086 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4087 table->entry[filter_idx].handle);
4088 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4089 sizeof(inbuf), NULL, 0, NULL);
4090 if (rc)
4091 netif_info(efx, drv, efx->net_dev,
4092 "%s: filter %04x remove failed\n",
4093 __func__, filter_idx);
4094 kfree(spec);
4095 }
4096
4097 vfree(table->entry);
4098 kfree(table);
4099 }
4100
4101 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4102 {
4103 struct efx_ef10_filter_table *table = efx->filter_state;
4104 unsigned int filter_idx;
4105
4106 if (*id != EFX_EF10_FILTER_ID_INVALID) {
4107 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4108 if (!table->entry[filter_idx].spec)
4109 netif_dbg(efx, drv, efx->net_dev,
4110 "marked null spec old %04x:%04x\n", *id,
4111 filter_idx);
4112 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4113 *id = EFX_EF10_FILTER_ID_INVALID;
4114 }
4115 }
4116
4117 /* Mark old per-VLAN filters that may need to be removed */
4118 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4119 struct efx_ef10_filter_vlan *vlan)
4120 {
4121 struct efx_ef10_filter_table *table = efx->filter_state;
4122 unsigned int i;
4123
4124 for (i = 0; i < table->dev_uc_count; i++)
4125 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
4126 for (i = 0; i < table->dev_mc_count; i++)
4127 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
4128 efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
4129 efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
4130 efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
4131 }
4132
4133 /* Mark old filters that may need to be removed.
4134 * Caller must hold efx->filter_sem for read if race against
4135 * efx_ef10_filter_table_remove() is possible
4136 */
4137 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4138 {
4139 struct efx_ef10_filter_table *table = efx->filter_state;
4140 struct efx_ef10_filter_vlan *vlan;
4141
4142 spin_lock_bh(&efx->filter_lock);
4143 list_for_each_entry(vlan, &table->vlan_list, list)
4144 _efx_ef10_filter_vlan_mark_old(efx, vlan);
4145 spin_unlock_bh(&efx->filter_lock);
4146 }
4147
4148 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
4149 {
4150 struct efx_ef10_filter_table *table = efx->filter_state;
4151 struct net_device *net_dev = efx->net_dev;
4152 struct netdev_hw_addr *uc;
4153 int addr_count;
4154 unsigned int i;
4155
4156 addr_count = netdev_uc_count(net_dev);
4157 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
4158 table->dev_uc_count = 1 + addr_count;
4159 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4160 i = 1;
4161 netdev_for_each_uc_addr(uc, net_dev) {
4162 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
4163 table->uc_promisc = true;
4164 break;
4165 }
4166 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4167 i++;
4168 }
4169 }
4170
4171 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
4172 {
4173 struct efx_ef10_filter_table *table = efx->filter_state;
4174 struct net_device *net_dev = efx->net_dev;
4175 struct netdev_hw_addr *mc;
4176 unsigned int i, addr_count;
4177
4178 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
4179
4180 addr_count = netdev_mc_count(net_dev);
4181 i = 0;
4182 netdev_for_each_mc_addr(mc, net_dev) {
4183 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
4184 table->mc_promisc = true;
4185 break;
4186 }
4187 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4188 i++;
4189 }
4190
4191 table->dev_mc_count = i;
4192 }
4193
4194 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
4195 struct efx_ef10_filter_vlan *vlan,
4196 bool multicast, bool rollback)
4197 {
4198 struct efx_ef10_filter_table *table = efx->filter_state;
4199 struct efx_ef10_dev_addr *addr_list;
4200 enum efx_filter_flags filter_flags;
4201 struct efx_filter_spec spec;
4202 u8 baddr[ETH_ALEN];
4203 unsigned int i, j;
4204 int addr_count;
4205 u16 *ids;
4206 int rc;
4207
4208 if (multicast) {
4209 addr_list = table->dev_mc_list;
4210 addr_count = table->dev_mc_count;
4211 ids = vlan->mc;
4212 } else {
4213 addr_list = table->dev_uc_list;
4214 addr_count = table->dev_uc_count;
4215 ids = vlan->uc;
4216 }
4217
4218 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4219
4220 /* Insert/renew filters */
4221 for (i = 0; i < addr_count; i++) {
4222 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4223 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
4224 rc = efx_ef10_filter_insert(efx, &spec, true);
4225 if (rc < 0) {
4226 if (rollback) {
4227 netif_info(efx, drv, efx->net_dev,
4228 "efx_ef10_filter_insert failed rc=%d\n",
4229 rc);
4230 /* Fall back to promiscuous */
4231 for (j = 0; j < i; j++) {
4232 if (ids[j] == EFX_EF10_FILTER_ID_INVALID)
4233 continue;
4234 efx_ef10_filter_remove_unsafe(
4235 efx, EFX_FILTER_PRI_AUTO,
4236 ids[j]);
4237 ids[j] = EFX_EF10_FILTER_ID_INVALID;
4238 }
4239 return rc;
4240 } else {
4241 /* mark as not inserted, and carry on */
4242 rc = EFX_EF10_FILTER_ID_INVALID;
4243 }
4244 }
4245 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
4246 }
4247
4248 if (multicast && rollback) {
4249 /* Also need an Ethernet broadcast filter */
4250 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4251 eth_broadcast_addr(baddr);
4252 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4253 rc = efx_ef10_filter_insert(efx, &spec, true);
4254 if (rc < 0) {
4255 netif_warn(efx, drv, efx->net_dev,
4256 "Broadcast filter insert failed rc=%d\n", rc);
4257 /* Fall back to promiscuous */
4258 for (j = 0; j < i; j++) {
4259 if (ids[j] == EFX_EF10_FILTER_ID_INVALID)
4260 continue;
4261 efx_ef10_filter_remove_unsafe(
4262 efx, EFX_FILTER_PRI_AUTO,
4263 ids[j]);
4264 ids[j] = EFX_EF10_FILTER_ID_INVALID;
4265 }
4266 return rc;
4267 } else {
4268 EFX_WARN_ON_PARANOID(vlan->bcast !=
4269 EFX_EF10_FILTER_ID_INVALID);
4270 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4271 }
4272 }
4273
4274 return 0;
4275 }
4276
4277 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
4278 struct efx_ef10_filter_vlan *vlan,
4279 bool multicast, bool rollback)
4280 {
4281 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4282 enum efx_filter_flags filter_flags;
4283 struct efx_filter_spec spec;
4284 u8 baddr[ETH_ALEN];
4285 int rc;
4286
4287 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4288
4289 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4290
4291 if (multicast)
4292 efx_filter_set_mc_def(&spec);
4293 else
4294 efx_filter_set_uc_def(&spec);
4295
4296 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
4297 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
4298
4299 rc = efx_ef10_filter_insert(efx, &spec, true);
4300 if (rc < 0) {
4301 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4302 efx->net_dev,
4303 "%scast mismatch filter insert failed rc=%d\n",
4304 multicast ? "Multi" : "Uni", rc);
4305 } else if (multicast) {
4306 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
4307 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
4308 if (!nic_data->workaround_26807) {
4309 /* Also need an Ethernet broadcast filter */
4310 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4311 filter_flags, 0);
4312 eth_broadcast_addr(baddr);
4313 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4314 rc = efx_ef10_filter_insert(efx, &spec, true);
4315 if (rc < 0) {
4316 netif_warn(efx, drv, efx->net_dev,
4317 "Broadcast filter insert failed rc=%d\n",
4318 rc);
4319 if (rollback) {
4320 /* Roll back the mc_def filter */
4321 efx_ef10_filter_remove_unsafe(
4322 efx, EFX_FILTER_PRI_AUTO,
4323 vlan->mcdef);
4324 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4325 return rc;
4326 }
4327 } else {
4328 EFX_WARN_ON_PARANOID(vlan->bcast !=
4329 EFX_EF10_FILTER_ID_INVALID);
4330 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4331 }
4332 }
4333 rc = 0;
4334 } else {
4335 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
4336 vlan->ucdef = rc;
4337 rc = 0;
4338 }
4339 return rc;
4340 }
4341
4342 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4343 * flag or removes these filters, we don't need to hold the filter_lock while
4344 * scanning for these filters.
4345 */
4346 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4347 {
4348 struct efx_ef10_filter_table *table = efx->filter_state;
4349 int remove_failed = 0;
4350 int remove_noent = 0;
4351 int rc;
4352 int i;
4353
4354 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4355 if (ACCESS_ONCE(table->entry[i].spec) &
4356 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4357 rc = efx_ef10_filter_remove_internal(efx,
4358 1U << EFX_FILTER_PRI_AUTO, i, true);
4359 if (rc == -ENOENT)
4360 remove_noent++;
4361 else if (rc)
4362 remove_failed++;
4363 }
4364 }
4365
4366 if (remove_failed)
4367 netif_info(efx, drv, efx->net_dev,
4368 "%s: failed to remove %d filters\n",
4369 __func__, remove_failed);
4370 if (remove_noent)
4371 netif_info(efx, drv, efx->net_dev,
4372 "%s: failed to remove %d non-existent filters\n",
4373 __func__, remove_noent);
4374 }
4375
4376 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4377 {
4378 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4379 u8 mac_old[ETH_ALEN];
4380 int rc, rc2;
4381
4382 /* Only reconfigure a PF-created vport */
4383 if (is_zero_ether_addr(nic_data->vport_mac))
4384 return 0;
4385
4386 efx_device_detach_sync(efx);
4387 efx_net_stop(efx->net_dev);
4388 down_write(&efx->filter_sem);
4389 efx_ef10_filter_table_remove(efx);
4390 up_write(&efx->filter_sem);
4391
4392 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4393 if (rc)
4394 goto restore_filters;
4395
4396 ether_addr_copy(mac_old, nic_data->vport_mac);
4397 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4398 nic_data->vport_mac);
4399 if (rc)
4400 goto restore_vadaptor;
4401
4402 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4403 efx->net_dev->dev_addr);
4404 if (!rc) {
4405 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4406 } else {
4407 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4408 if (rc2) {
4409 /* Failed to add original MAC, so clear vport_mac */
4410 eth_zero_addr(nic_data->vport_mac);
4411 goto reset_nic;
4412 }
4413 }
4414
4415 restore_vadaptor:
4416 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4417 if (rc2)
4418 goto reset_nic;
4419 restore_filters:
4420 down_write(&efx->filter_sem);
4421 rc2 = efx_ef10_filter_table_probe(efx);
4422 up_write(&efx->filter_sem);
4423 if (rc2)
4424 goto reset_nic;
4425
4426 rc2 = efx_net_open(efx->net_dev);
4427 if (rc2)
4428 goto reset_nic;
4429
4430 netif_device_attach(efx->net_dev);
4431
4432 return rc;
4433
4434 reset_nic:
4435 netif_err(efx, drv, efx->net_dev,
4436 "Failed to restore when changing MAC address - scheduling reset\n");
4437 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4438
4439 return rc ? rc : rc2;
4440 }
4441
4442 /* Caller must hold efx->filter_sem for read if race against
4443 * efx_ef10_filter_table_remove() is possible
4444 */
4445 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
4446 struct efx_ef10_filter_vlan *vlan)
4447 {
4448 struct efx_ef10_filter_table *table = efx->filter_state;
4449 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4450
4451 /* Do not install unspecified VID if VLAN filtering is enabled.
4452 * Do not install all specified VIDs if VLAN filtering is disabled.
4453 */
4454 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
4455 return;
4456
4457 /* Insert/renew unicast filters */
4458 if (table->uc_promisc) {
4459 efx_ef10_filter_insert_def(efx, vlan, false, false);
4460 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
4461 } else {
4462 /* If any of the filters failed to insert, fall back to
4463 * promiscuous mode - add in the uc_def filter. But keep
4464 * our individual unicast filters.
4465 */
4466 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
4467 efx_ef10_filter_insert_def(efx, vlan, false, false);
4468 }
4469
4470 /* Insert/renew multicast filters */
4471 /* If changing promiscuous state with cascaded multicast filters, remove
4472 * old filters first, so that packets are dropped rather than duplicated
4473 */
4474 if (nic_data->workaround_26807 &&
4475 table->mc_promisc_last != table->mc_promisc)
4476 efx_ef10_filter_remove_old(efx);
4477 if (table->mc_promisc) {
4478 if (nic_data->workaround_26807) {
4479 /* If we failed to insert promiscuous filters, rollback
4480 * and fall back to individual multicast filters
4481 */
4482 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
4483 /* Changing promisc state, so remove old filters */
4484 efx_ef10_filter_remove_old(efx);
4485 efx_ef10_filter_insert_addr_list(efx, vlan,
4486 true, false);
4487 }
4488 } else {
4489 /* If we failed to insert promiscuous filters, don't
4490 * rollback. Regardless, also insert the mc_list
4491 */
4492 efx_ef10_filter_insert_def(efx, vlan, true, false);
4493 efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
4494 }
4495 } else {
4496 /* If any filters failed to insert, rollback and fall back to
4497 * promiscuous mode - mc_def filter and maybe broadcast. If
4498 * that fails, roll back again and insert as many of our
4499 * individual multicast filters as we can.
4500 */
4501 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
4502 /* Changing promisc state, so remove old filters */
4503 if (nic_data->workaround_26807)
4504 efx_ef10_filter_remove_old(efx);
4505 if (efx_ef10_filter_insert_def(efx, vlan, true, true))
4506 efx_ef10_filter_insert_addr_list(efx, vlan,
4507 true, false);
4508 }
4509 }
4510 }
4511
4512 /* Caller must hold efx->filter_sem for read if race against
4513 * efx_ef10_filter_table_remove() is possible
4514 */
4515 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4516 {
4517 struct efx_ef10_filter_table *table = efx->filter_state;
4518 struct net_device *net_dev = efx->net_dev;
4519 struct efx_ef10_filter_vlan *vlan;
4520 bool vlan_filter;
4521
4522 if (!efx_dev_registered(efx))
4523 return;
4524
4525 if (!table)
4526 return;
4527
4528 efx_ef10_filter_mark_old(efx);
4529
4530 /* Copy/convert the address lists; add the primary station
4531 * address and broadcast address
4532 */
4533 netif_addr_lock_bh(net_dev);
4534 efx_ef10_filter_uc_addr_list(efx);
4535 efx_ef10_filter_mc_addr_list(efx);
4536 netif_addr_unlock_bh(net_dev);
4537
4538 /* If VLAN filtering changes, all old filters are finally removed.
4539 * Do it in advance to avoid conflicts for unicast untagged and
4540 * VLAN 0 tagged filters.
4541 */
4542 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4543 if (table->vlan_filter != vlan_filter) {
4544 table->vlan_filter = vlan_filter;
4545 efx_ef10_filter_remove_old(efx);
4546 }
4547
4548 list_for_each_entry(vlan, &table->vlan_list, list)
4549 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4550
4551 efx_ef10_filter_remove_old(efx);
4552 table->mc_promisc_last = table->mc_promisc;
4553 }
4554
4555 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
4556 {
4557 struct efx_ef10_filter_table *table = efx->filter_state;
4558 struct efx_ef10_filter_vlan *vlan;
4559
4560 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4561
4562 list_for_each_entry(vlan, &table->vlan_list, list) {
4563 if (vlan->vid == vid)
4564 return vlan;
4565 }
4566
4567 return NULL;
4568 }
4569
4570 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
4571 {
4572 struct efx_ef10_filter_table *table = efx->filter_state;
4573 struct efx_ef10_filter_vlan *vlan;
4574 unsigned int i;
4575
4576 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4577 return -EINVAL;
4578
4579 vlan = efx_ef10_filter_find_vlan(efx, vid);
4580 if (WARN_ON(vlan)) {
4581 netif_err(efx, drv, efx->net_dev,
4582 "VLAN %u already added\n", vid);
4583 return -EALREADY;
4584 }
4585
4586 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
4587 if (!vlan)
4588 return -ENOMEM;
4589
4590 vlan->vid = vid;
4591
4592 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4593 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
4594 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4595 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
4596 vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
4597 vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
4598 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4599
4600 list_add_tail(&vlan->list, &table->vlan_list);
4601
4602 if (efx_dev_registered(efx))
4603 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4604
4605 return 0;
4606 }
4607
4608 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
4609 struct efx_ef10_filter_vlan *vlan)
4610 {
4611 unsigned int i;
4612
4613 /* See comment in efx_ef10_filter_table_remove() */
4614 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4615 return;
4616
4617 list_del(&vlan->list);
4618
4619 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++) {
4620 if (vlan->uc[i] != EFX_EF10_FILTER_ID_INVALID)
4621 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4622 vlan->uc[i]);
4623 }
4624 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++) {
4625 if (vlan->mc[i] != EFX_EF10_FILTER_ID_INVALID)
4626 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4627 vlan->mc[i]);
4628 }
4629 if (vlan->ucdef != EFX_EF10_FILTER_ID_INVALID)
4630 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4631 vlan->ucdef);
4632 if (vlan->bcast != EFX_EF10_FILTER_ID_INVALID)
4633 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4634 vlan->bcast);
4635 if (vlan->mcdef != EFX_EF10_FILTER_ID_INVALID)
4636 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4637 vlan->mcdef);
4638
4639 kfree(vlan);
4640 }
4641
4642 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
4643 {
4644 struct efx_ef10_filter_vlan *vlan;
4645
4646 /* See comment in efx_ef10_filter_table_remove() */
4647 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4648 return;
4649
4650 vlan = efx_ef10_filter_find_vlan(efx, vid);
4651 if (!vlan) {
4652 netif_err(efx, drv, efx->net_dev,
4653 "VLAN %u not found in filter state\n", vid);
4654 return;
4655 }
4656
4657 efx_ef10_filter_del_vlan_internal(efx, vlan);
4658 }
4659
4660 static int efx_ef10_set_mac_address(struct efx_nic *efx)
4661 {
4662 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4663 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4664 bool was_enabled = efx->port_enabled;
4665 int rc;
4666
4667 efx_device_detach_sync(efx);
4668 efx_net_stop(efx->net_dev);
4669 down_write(&efx->filter_sem);
4670 efx_ef10_filter_table_remove(efx);
4671
4672 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4673 efx->net_dev->dev_addr);
4674 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4675 nic_data->vport_id);
4676 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4677 sizeof(inbuf), NULL, 0, NULL);
4678
4679 efx_ef10_filter_table_probe(efx);
4680 up_write(&efx->filter_sem);
4681 if (was_enabled)
4682 efx_net_open(efx->net_dev);
4683 netif_device_attach(efx->net_dev);
4684
4685 #ifdef CONFIG_SFC_SRIOV
4686 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
4687 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4688
4689 if (rc == -EPERM) {
4690 struct efx_nic *efx_pf;
4691
4692 /* Switch to PF and change MAC address on vport */
4693 efx_pf = pci_get_drvdata(pci_dev_pf);
4694
4695 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4696 nic_data->vf_index,
4697 efx->net_dev->dev_addr);
4698 } else if (!rc) {
4699 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4700 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4701 unsigned int i;
4702
4703 /* MAC address successfully changed by VF (with MAC
4704 * spoofing) so update the parent PF if possible.
4705 */
4706 for (i = 0; i < efx_pf->vf_count; ++i) {
4707 struct ef10_vf *vf = nic_data->vf + i;
4708
4709 if (vf->efx == efx) {
4710 ether_addr_copy(vf->mac,
4711 efx->net_dev->dev_addr);
4712 return 0;
4713 }
4714 }
4715 }
4716 } else
4717 #endif
4718 if (rc == -EPERM) {
4719 netif_err(efx, drv, efx->net_dev,
4720 "Cannot change MAC address; use sfboot to enable"
4721 " mac-spoofing on this interface\n");
4722 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4723 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4724 * fall-back to the method of changing the MAC address on the
4725 * vport. This only applies to PFs because such versions of
4726 * MCFW do not support VFs.
4727 */
4728 rc = efx_ef10_vport_set_mac_address(efx);
4729 } else {
4730 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4731 sizeof(inbuf), NULL, 0, rc);
4732 }
4733
4734 return rc;
4735 }
4736
4737 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4738 {
4739 efx_ef10_filter_sync_rx_mode(efx);
4740
4741 return efx_mcdi_set_mac(efx);
4742 }
4743
4744 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4745 {
4746 efx_ef10_filter_sync_rx_mode(efx);
4747
4748 return 0;
4749 }
4750
4751 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4752 {
4753 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4754
4755 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4756 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4757 NULL, 0, NULL);
4758 }
4759
4760 /* MC BISTs follow a different poll mechanism to phy BISTs.
4761 * The BIST is done in the poll handler on the MC, and the MCDI command
4762 * will block until the BIST is done.
4763 */
4764 static int efx_ef10_poll_bist(struct efx_nic *efx)
4765 {
4766 int rc;
4767 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4768 size_t outlen;
4769 u32 result;
4770
4771 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4772 outbuf, sizeof(outbuf), &outlen);
4773 if (rc != 0)
4774 return rc;
4775
4776 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4777 return -EIO;
4778
4779 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4780 switch (result) {
4781 case MC_CMD_POLL_BIST_PASSED:
4782 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4783 return 0;
4784 case MC_CMD_POLL_BIST_TIMEOUT:
4785 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4786 return -EIO;
4787 case MC_CMD_POLL_BIST_FAILED:
4788 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4789 return -EIO;
4790 default:
4791 netif_err(efx, hw, efx->net_dev,
4792 "BIST returned unknown result %u", result);
4793 return -EIO;
4794 }
4795 }
4796
4797 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4798 {
4799 int rc;
4800
4801 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4802
4803 rc = efx_ef10_start_bist(efx, bist_type);
4804 if (rc != 0)
4805 return rc;
4806
4807 return efx_ef10_poll_bist(efx);
4808 }
4809
4810 static int
4811 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4812 {
4813 int rc, rc2;
4814
4815 efx_reset_down(efx, RESET_TYPE_WORLD);
4816
4817 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4818 NULL, 0, NULL, 0, NULL);
4819 if (rc != 0)
4820 goto out;
4821
4822 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4823 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4824
4825 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4826
4827 out:
4828 if (rc == -EPERM)
4829 rc = 0;
4830 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4831 return rc ? rc : rc2;
4832 }
4833
4834 #ifdef CONFIG_SFC_MTD
4835
4836 struct efx_ef10_nvram_type_info {
4837 u16 type, type_mask;
4838 u8 port;
4839 const char *name;
4840 };
4841
4842 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4843 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
4844 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
4845 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
4846 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
4847 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
4848 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
4849 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
4850 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
4851 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
4852 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
4853 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
4854 };
4855
4856 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4857 struct efx_mcdi_mtd_partition *part,
4858 unsigned int type)
4859 {
4860 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4861 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4862 const struct efx_ef10_nvram_type_info *info;
4863 size_t size, erase_size, outlen;
4864 bool protected;
4865 int rc;
4866
4867 for (info = efx_ef10_nvram_types; ; info++) {
4868 if (info ==
4869 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4870 return -ENODEV;
4871 if ((type & ~info->type_mask) == info->type)
4872 break;
4873 }
4874 if (info->port != efx_port_num(efx))
4875 return -ENODEV;
4876
4877 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4878 if (rc)
4879 return rc;
4880 if (protected)
4881 return -ENODEV; /* hide it */
4882
4883 part->nvram_type = type;
4884
4885 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4886 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4887 outbuf, sizeof(outbuf), &outlen);
4888 if (rc)
4889 return rc;
4890 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4891 return -EIO;
4892 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4893 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4894 part->fw_subtype = MCDI_DWORD(outbuf,
4895 NVRAM_METADATA_OUT_SUBTYPE);
4896
4897 part->common.dev_type_name = "EF10 NVRAM manager";
4898 part->common.type_name = info->name;
4899
4900 part->common.mtd.type = MTD_NORFLASH;
4901 part->common.mtd.flags = MTD_CAP_NORFLASH;
4902 part->common.mtd.size = size;
4903 part->common.mtd.erasesize = erase_size;
4904
4905 return 0;
4906 }
4907
4908 static int efx_ef10_mtd_probe(struct efx_nic *efx)
4909 {
4910 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4911 struct efx_mcdi_mtd_partition *parts;
4912 size_t outlen, n_parts_total, i, n_parts;
4913 unsigned int type;
4914 int rc;
4915
4916 ASSERT_RTNL();
4917
4918 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4919 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4920 outbuf, sizeof(outbuf), &outlen);
4921 if (rc)
4922 return rc;
4923 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4924 return -EIO;
4925
4926 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4927 if (n_parts_total >
4928 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4929 return -EIO;
4930
4931 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4932 if (!parts)
4933 return -ENOMEM;
4934
4935 n_parts = 0;
4936 for (i = 0; i < n_parts_total; i++) {
4937 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4938 i);
4939 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4940 if (rc == 0)
4941 n_parts++;
4942 else if (rc != -ENODEV)
4943 goto fail;
4944 }
4945
4946 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4947 fail:
4948 if (rc)
4949 kfree(parts);
4950 return rc;
4951 }
4952
4953 #endif /* CONFIG_SFC_MTD */
4954
4955 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4956 {
4957 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4958 }
4959
4960 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4961 u32 host_time) {}
4962
4963 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4964 bool temp)
4965 {
4966 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4967 int rc;
4968
4969 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4970 channel->sync_events_state == SYNC_EVENTS_VALID ||
4971 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4972 return 0;
4973 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4974
4975 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4976 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4977 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4978 channel->channel);
4979
4980 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4981 inbuf, sizeof(inbuf), NULL, 0, NULL);
4982
4983 if (rc != 0)
4984 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4985 SYNC_EVENTS_DISABLED;
4986
4987 return rc;
4988 }
4989
4990 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4991 bool temp)
4992 {
4993 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4994 int rc;
4995
4996 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4997 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4998 return 0;
4999 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5000 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5001 return 0;
5002 }
5003 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5004 SYNC_EVENTS_DISABLED;
5005
5006 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5007 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5008 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5009 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5010 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5011 channel->channel);
5012
5013 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5014 inbuf, sizeof(inbuf), NULL, 0, NULL);
5015
5016 return rc;
5017 }
5018
5019 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5020 bool temp)
5021 {
5022 int (*set)(struct efx_channel *channel, bool temp);
5023 struct efx_channel *channel;
5024
5025 set = en ?
5026 efx_ef10_rx_enable_timestamping :
5027 efx_ef10_rx_disable_timestamping;
5028
5029 efx_for_each_channel(channel, efx) {
5030 int rc = set(channel, temp);
5031 if (en && rc != 0) {
5032 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5033 return rc;
5034 }
5035 }
5036
5037 return 0;
5038 }
5039
5040 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5041 struct hwtstamp_config *init)
5042 {
5043 return -EOPNOTSUPP;
5044 }
5045
5046 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5047 struct hwtstamp_config *init)
5048 {
5049 int rc;
5050
5051 switch (init->rx_filter) {
5052 case HWTSTAMP_FILTER_NONE:
5053 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5054 /* if TX timestamping is still requested then leave PTP on */
5055 return efx_ptp_change_mode(efx,
5056 init->tx_type != HWTSTAMP_TX_OFF, 0);
5057 case HWTSTAMP_FILTER_ALL:
5058 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5059 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5060 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5061 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5062 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5063 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5064 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5065 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5066 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5067 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5068 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5069 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5070 init->rx_filter = HWTSTAMP_FILTER_ALL;
5071 rc = efx_ptp_change_mode(efx, true, 0);
5072 if (!rc)
5073 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5074 if (rc)
5075 efx_ptp_change_mode(efx, false, 0);
5076 return rc;
5077 default:
5078 return -ERANGE;
5079 }
5080 }
5081
5082 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5083 {
5084 if (proto != htons(ETH_P_8021Q))
5085 return -EINVAL;
5086
5087 return efx_ef10_add_vlan(efx, vid);
5088 }
5089
5090 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5091 {
5092 if (proto != htons(ETH_P_8021Q))
5093 return -EINVAL;
5094
5095 return efx_ef10_del_vlan(efx, vid);
5096 }
5097
5098 #define EF10_OFFLOAD_FEATURES \
5099 (NETIF_F_IP_CSUM | \
5100 NETIF_F_HW_VLAN_CTAG_FILTER | \
5101 NETIF_F_IPV6_CSUM | \
5102 NETIF_F_RXHASH | \
5103 NETIF_F_NTUPLE)
5104
5105 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
5106 .is_vf = true,
5107 .mem_bar = EFX_MEM_VF_BAR,
5108 .mem_map_size = efx_ef10_mem_map_size,
5109 .probe = efx_ef10_probe_vf,
5110 .remove = efx_ef10_remove,
5111 .dimension_resources = efx_ef10_dimension_resources,
5112 .init = efx_ef10_init_nic,
5113 .fini = efx_port_dummy_op_void,
5114 .map_reset_reason = efx_ef10_map_reset_reason,
5115 .map_reset_flags = efx_ef10_map_reset_flags,
5116 .reset = efx_ef10_reset,
5117 .probe_port = efx_mcdi_port_probe,
5118 .remove_port = efx_mcdi_port_remove,
5119 .fini_dmaq = efx_ef10_fini_dmaq,
5120 .prepare_flr = efx_ef10_prepare_flr,
5121 .finish_flr = efx_port_dummy_op_void,
5122 .describe_stats = efx_ef10_describe_stats,
5123 .update_stats = efx_ef10_update_stats_vf,
5124 .start_stats = efx_port_dummy_op_void,
5125 .pull_stats = efx_port_dummy_op_void,
5126 .stop_stats = efx_port_dummy_op_void,
5127 .set_id_led = efx_mcdi_set_id_led,
5128 .push_irq_moderation = efx_ef10_push_irq_moderation,
5129 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
5130 .check_mac_fault = efx_mcdi_mac_check_fault,
5131 .reconfigure_port = efx_mcdi_port_reconfigure,
5132 .get_wol = efx_ef10_get_wol_vf,
5133 .set_wol = efx_ef10_set_wol_vf,
5134 .resume_wol = efx_port_dummy_op_void,
5135 .mcdi_request = efx_ef10_mcdi_request,
5136 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5137 .mcdi_read_response = efx_ef10_mcdi_read_response,
5138 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5139 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5140 .irq_enable_master = efx_port_dummy_op_void,
5141 .irq_test_generate = efx_ef10_irq_test_generate,
5142 .irq_disable_non_ev = efx_port_dummy_op_void,
5143 .irq_handle_msi = efx_ef10_msi_interrupt,
5144 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5145 .tx_probe = efx_ef10_tx_probe,
5146 .tx_init = efx_ef10_tx_init,
5147 .tx_remove = efx_ef10_tx_remove,
5148 .tx_write = efx_ef10_tx_write,
5149 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
5150 .rx_probe = efx_ef10_rx_probe,
5151 .rx_init = efx_ef10_rx_init,
5152 .rx_remove = efx_ef10_rx_remove,
5153 .rx_write = efx_ef10_rx_write,
5154 .rx_defer_refill = efx_ef10_rx_defer_refill,
5155 .ev_probe = efx_ef10_ev_probe,
5156 .ev_init = efx_ef10_ev_init,
5157 .ev_fini = efx_ef10_ev_fini,
5158 .ev_remove = efx_ef10_ev_remove,
5159 .ev_process = efx_ef10_ev_process,
5160 .ev_read_ack = efx_ef10_ev_read_ack,
5161 .ev_test_generate = efx_ef10_ev_test_generate,
5162 .filter_table_probe = efx_ef10_filter_table_probe,
5163 .filter_table_restore = efx_ef10_filter_table_restore,
5164 .filter_table_remove = efx_ef10_filter_table_remove,
5165 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5166 .filter_insert = efx_ef10_filter_insert,
5167 .filter_remove_safe = efx_ef10_filter_remove_safe,
5168 .filter_get_safe = efx_ef10_filter_get_safe,
5169 .filter_clear_rx = efx_ef10_filter_clear_rx,
5170 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5171 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5172 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5173 #ifdef CONFIG_RFS_ACCEL
5174 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5175 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5176 #endif
5177 #ifdef CONFIG_SFC_MTD
5178 .mtd_probe = efx_port_dummy_op_int,
5179 #endif
5180 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
5181 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
5182 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5183 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5184 #ifdef CONFIG_SFC_SRIOV
5185 .vswitching_probe = efx_ef10_vswitching_probe_vf,
5186 .vswitching_restore = efx_ef10_vswitching_restore_vf,
5187 .vswitching_remove = efx_ef10_vswitching_remove_vf,
5188 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
5189 #endif
5190 .get_mac_address = efx_ef10_get_mac_address_vf,
5191 .set_mac_address = efx_ef10_set_mac_address,
5192
5193 .revision = EFX_REV_HUNT_A0,
5194 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5195 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5196 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5197 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5198 .can_rx_scatter = true,
5199 .always_rx_scatter = true,
5200 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5201 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5202 .offload_features = EF10_OFFLOAD_FEATURES,
5203 .mcdi_max_ver = 2,
5204 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5205 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5206 1 << HWTSTAMP_FILTER_ALL,
5207 };
5208
5209 const struct efx_nic_type efx_hunt_a0_nic_type = {
5210 .is_vf = false,
5211 .mem_bar = EFX_MEM_BAR,
5212 .mem_map_size = efx_ef10_mem_map_size,
5213 .probe = efx_ef10_probe_pf,
5214 .remove = efx_ef10_remove,
5215 .dimension_resources = efx_ef10_dimension_resources,
5216 .init = efx_ef10_init_nic,
5217 .fini = efx_port_dummy_op_void,
5218 .map_reset_reason = efx_ef10_map_reset_reason,
5219 .map_reset_flags = efx_ef10_map_reset_flags,
5220 .reset = efx_ef10_reset,
5221 .probe_port = efx_mcdi_port_probe,
5222 .remove_port = efx_mcdi_port_remove,
5223 .fini_dmaq = efx_ef10_fini_dmaq,
5224 .prepare_flr = efx_ef10_prepare_flr,
5225 .finish_flr = efx_port_dummy_op_void,
5226 .describe_stats = efx_ef10_describe_stats,
5227 .update_stats = efx_ef10_update_stats_pf,
5228 .start_stats = efx_mcdi_mac_start_stats,
5229 .pull_stats = efx_mcdi_mac_pull_stats,
5230 .stop_stats = efx_mcdi_mac_stop_stats,
5231 .set_id_led = efx_mcdi_set_id_led,
5232 .push_irq_moderation = efx_ef10_push_irq_moderation,
5233 .reconfigure_mac = efx_ef10_mac_reconfigure,
5234 .check_mac_fault = efx_mcdi_mac_check_fault,
5235 .reconfigure_port = efx_mcdi_port_reconfigure,
5236 .get_wol = efx_ef10_get_wol,
5237 .set_wol = efx_ef10_set_wol,
5238 .resume_wol = efx_port_dummy_op_void,
5239 .test_chip = efx_ef10_test_chip,
5240 .test_nvram = efx_mcdi_nvram_test_all,
5241 .mcdi_request = efx_ef10_mcdi_request,
5242 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5243 .mcdi_read_response = efx_ef10_mcdi_read_response,
5244 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5245 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5246 .irq_enable_master = efx_port_dummy_op_void,
5247 .irq_test_generate = efx_ef10_irq_test_generate,
5248 .irq_disable_non_ev = efx_port_dummy_op_void,
5249 .irq_handle_msi = efx_ef10_msi_interrupt,
5250 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5251 .tx_probe = efx_ef10_tx_probe,
5252 .tx_init = efx_ef10_tx_init,
5253 .tx_remove = efx_ef10_tx_remove,
5254 .tx_write = efx_ef10_tx_write,
5255 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
5256 .rx_probe = efx_ef10_rx_probe,
5257 .rx_init = efx_ef10_rx_init,
5258 .rx_remove = efx_ef10_rx_remove,
5259 .rx_write = efx_ef10_rx_write,
5260 .rx_defer_refill = efx_ef10_rx_defer_refill,
5261 .ev_probe = efx_ef10_ev_probe,
5262 .ev_init = efx_ef10_ev_init,
5263 .ev_fini = efx_ef10_ev_fini,
5264 .ev_remove = efx_ef10_ev_remove,
5265 .ev_process = efx_ef10_ev_process,
5266 .ev_read_ack = efx_ef10_ev_read_ack,
5267 .ev_test_generate = efx_ef10_ev_test_generate,
5268 .filter_table_probe = efx_ef10_filter_table_probe,
5269 .filter_table_restore = efx_ef10_filter_table_restore,
5270 .filter_table_remove = efx_ef10_filter_table_remove,
5271 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5272 .filter_insert = efx_ef10_filter_insert,
5273 .filter_remove_safe = efx_ef10_filter_remove_safe,
5274 .filter_get_safe = efx_ef10_filter_get_safe,
5275 .filter_clear_rx = efx_ef10_filter_clear_rx,
5276 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5277 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5278 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5279 #ifdef CONFIG_RFS_ACCEL
5280 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5281 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5282 #endif
5283 #ifdef CONFIG_SFC_MTD
5284 .mtd_probe = efx_ef10_mtd_probe,
5285 .mtd_rename = efx_mcdi_mtd_rename,
5286 .mtd_read = efx_mcdi_mtd_read,
5287 .mtd_erase = efx_mcdi_mtd_erase,
5288 .mtd_write = efx_mcdi_mtd_write,
5289 .mtd_sync = efx_mcdi_mtd_sync,
5290 #endif
5291 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
5292 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
5293 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
5294 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5295 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5296 #ifdef CONFIG_SFC_SRIOV
5297 .sriov_configure = efx_ef10_sriov_configure,
5298 .sriov_init = efx_ef10_sriov_init,
5299 .sriov_fini = efx_ef10_sriov_fini,
5300 .sriov_wanted = efx_ef10_sriov_wanted,
5301 .sriov_reset = efx_ef10_sriov_reset,
5302 .sriov_flr = efx_ef10_sriov_flr,
5303 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
5304 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
5305 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
5306 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
5307 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
5308 .vswitching_probe = efx_ef10_vswitching_probe_pf,
5309 .vswitching_restore = efx_ef10_vswitching_restore_pf,
5310 .vswitching_remove = efx_ef10_vswitching_remove_pf,
5311 #endif
5312 .get_mac_address = efx_ef10_get_mac_address_pf,
5313 .set_mac_address = efx_ef10_set_mac_address,
5314
5315 .revision = EFX_REV_HUNT_A0,
5316 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5317 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5318 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5319 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5320 .can_rx_scatter = true,
5321 .always_rx_scatter = true,
5322 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5323 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5324 .offload_features = EF10_OFFLOAD_FEATURES,
5325 .mcdi_max_ver = 2,
5326 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5327 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5328 1 << HWTSTAMP_FILTER_ALL,
5329 };
Linux kernel - Deliverables
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