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Merge tag 'rxrpc-devel-20140304' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / net / ethernet / sfc / efx.c
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/delay.h>
16 #include <linux/notifier.h>
17 #include <linux/ip.h>
18 #include <linux/tcp.h>
19 #include <linux/in.h>
20 #include <linux/ethtool.h>
21 #include <linux/topology.h>
22 #include <linux/gfp.h>
23 #include <linux/aer.h>
24 #include <linux/interrupt.h>
25 #include "net_driver.h"
26 #include "efx.h"
27 #include "nic.h"
28 #include "selftest.h"
29
30 #include "mcdi.h"
31 #include "workarounds.h"
32
33 /**************************************************************************
34 *
35 * Type name strings
36 *
37 **************************************************************************
38 */
39
40 /* Loopback mode names (see LOOPBACK_MODE()) */
41 const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
42 const char *const efx_loopback_mode_names[] = {
43 [LOOPBACK_NONE] = "NONE",
44 [LOOPBACK_DATA] = "DATAPATH",
45 [LOOPBACK_GMAC] = "GMAC",
46 [LOOPBACK_XGMII] = "XGMII",
47 [LOOPBACK_XGXS] = "XGXS",
48 [LOOPBACK_XAUI] = "XAUI",
49 [LOOPBACK_GMII] = "GMII",
50 [LOOPBACK_SGMII] = "SGMII",
51 [LOOPBACK_XGBR] = "XGBR",
52 [LOOPBACK_XFI] = "XFI",
53 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
54 [LOOPBACK_GMII_FAR] = "GMII_FAR",
55 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
56 [LOOPBACK_XFI_FAR] = "XFI_FAR",
57 [LOOPBACK_GPHY] = "GPHY",
58 [LOOPBACK_PHYXS] = "PHYXS",
59 [LOOPBACK_PCS] = "PCS",
60 [LOOPBACK_PMAPMD] = "PMA/PMD",
61 [LOOPBACK_XPORT] = "XPORT",
62 [LOOPBACK_XGMII_WS] = "XGMII_WS",
63 [LOOPBACK_XAUI_WS] = "XAUI_WS",
64 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
65 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
66 [LOOPBACK_GMII_WS] = "GMII_WS",
67 [LOOPBACK_XFI_WS] = "XFI_WS",
68 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
69 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
70 };
71
72 const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
73 const char *const efx_reset_type_names[] = {
74 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
75 [RESET_TYPE_ALL] = "ALL",
76 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
77 [RESET_TYPE_WORLD] = "WORLD",
78 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
79 [RESET_TYPE_DISABLE] = "DISABLE",
80 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
81 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
82 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
83 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
84 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
85 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
86 [RESET_TYPE_MC_BIST] = "MC_BIST",
87 };
88
89 /* Reset workqueue. If any NIC has a hardware failure then a reset will be
90 * queued onto this work queue. This is not a per-nic work queue, because
91 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
92 */
93 static struct workqueue_struct *reset_workqueue;
94
95 /* How often and how many times to poll for a reset while waiting for a
96 * BIST that another function started to complete.
97 */
98 #define BIST_WAIT_DELAY_MS 100
99 #define BIST_WAIT_DELAY_COUNT 100
100
101 /**************************************************************************
102 *
103 * Configurable values
104 *
105 *************************************************************************/
106
107 /*
108 * Use separate channels for TX and RX events
109 *
110 * Set this to 1 to use separate channels for TX and RX. It allows us
111 * to control interrupt affinity separately for TX and RX.
112 *
113 * This is only used in MSI-X interrupt mode
114 */
115 static bool separate_tx_channels;
116 module_param(separate_tx_channels, bool, 0444);
117 MODULE_PARM_DESC(separate_tx_channels,
118 "Use separate channels for TX and RX");
119
120 /* This is the weight assigned to each of the (per-channel) virtual
121 * NAPI devices.
122 */
123 static int napi_weight = 64;
124
125 /* This is the time (in jiffies) between invocations of the hardware
126 * monitor.
127 * On Falcon-based NICs, this will:
128 * - Check the on-board hardware monitor;
129 * - Poll the link state and reconfigure the hardware as necessary.
130 * On Siena-based NICs for power systems with EEH support, this will give EEH a
131 * chance to start.
132 */
133 static unsigned int efx_monitor_interval = 1 * HZ;
134
135 /* Initial interrupt moderation settings. They can be modified after
136 * module load with ethtool.
137 *
138 * The default for RX should strike a balance between increasing the
139 * round-trip latency and reducing overhead.
140 */
141 static unsigned int rx_irq_mod_usec = 60;
142
143 /* Initial interrupt moderation settings. They can be modified after
144 * module load with ethtool.
145 *
146 * This default is chosen to ensure that a 10G link does not go idle
147 * while a TX queue is stopped after it has become full. A queue is
148 * restarted when it drops below half full. The time this takes (assuming
149 * worst case 3 descriptors per packet and 1024 descriptors) is
150 * 512 / 3 * 1.2 = 205 usec.
151 */
152 static unsigned int tx_irq_mod_usec = 150;
153
154 /* This is the first interrupt mode to try out of:
155 * 0 => MSI-X
156 * 1 => MSI
157 * 2 => legacy
158 */
159 static unsigned int interrupt_mode;
160
161 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
162 * i.e. the number of CPUs among which we may distribute simultaneous
163 * interrupt handling.
164 *
165 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
166 * The default (0) means to assign an interrupt to each core.
167 */
168 static unsigned int rss_cpus;
169 module_param(rss_cpus, uint, 0444);
170 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
171
172 static bool phy_flash_cfg;
173 module_param(phy_flash_cfg, bool, 0644);
174 MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
175
176 static unsigned irq_adapt_low_thresh = 8000;
177 module_param(irq_adapt_low_thresh, uint, 0644);
178 MODULE_PARM_DESC(irq_adapt_low_thresh,
179 "Threshold score for reducing IRQ moderation");
180
181 static unsigned irq_adapt_high_thresh = 16000;
182 module_param(irq_adapt_high_thresh, uint, 0644);
183 MODULE_PARM_DESC(irq_adapt_high_thresh,
184 "Threshold score for increasing IRQ moderation");
185
186 static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
187 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
188 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
189 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
190 module_param(debug, uint, 0);
191 MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
192
193 /**************************************************************************
194 *
195 * Utility functions and prototypes
196 *
197 *************************************************************************/
198
199 static int efx_soft_enable_interrupts(struct efx_nic *efx);
200 static void efx_soft_disable_interrupts(struct efx_nic *efx);
201 static void efx_remove_channel(struct efx_channel *channel);
202 static void efx_remove_channels(struct efx_nic *efx);
203 static const struct efx_channel_type efx_default_channel_type;
204 static void efx_remove_port(struct efx_nic *efx);
205 static void efx_init_napi_channel(struct efx_channel *channel);
206 static void efx_fini_napi(struct efx_nic *efx);
207 static void efx_fini_napi_channel(struct efx_channel *channel);
208 static void efx_fini_struct(struct efx_nic *efx);
209 static void efx_start_all(struct efx_nic *efx);
210 static void efx_stop_all(struct efx_nic *efx);
211
212 #define EFX_ASSERT_RESET_SERIALISED(efx) \
213 do { \
214 if ((efx->state == STATE_READY) || \
215 (efx->state == STATE_RECOVERY) || \
216 (efx->state == STATE_DISABLED)) \
217 ASSERT_RTNL(); \
218 } while (0)
219
220 static int efx_check_disabled(struct efx_nic *efx)
221 {
222 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
223 netif_err(efx, drv, efx->net_dev,
224 "device is disabled due to earlier errors\n");
225 return -EIO;
226 }
227 return 0;
228 }
229
230 /**************************************************************************
231 *
232 * Event queue processing
233 *
234 *************************************************************************/
235
236 /* Process channel's event queue
237 *
238 * This function is responsible for processing the event queue of a
239 * single channel. The caller must guarantee that this function will
240 * never be concurrently called more than once on the same channel,
241 * though different channels may be being processed concurrently.
242 */
243 static int efx_process_channel(struct efx_channel *channel, int budget)
244 {
245 int spent;
246
247 if (unlikely(!channel->enabled))
248 return 0;
249
250 spent = efx_nic_process_eventq(channel, budget);
251 if (spent && efx_channel_has_rx_queue(channel)) {
252 struct efx_rx_queue *rx_queue =
253 efx_channel_get_rx_queue(channel);
254
255 efx_rx_flush_packet(channel);
256 efx_fast_push_rx_descriptors(rx_queue, true);
257 }
258
259 return spent;
260 }
261
262 /* NAPI poll handler
263 *
264 * NAPI guarantees serialisation of polls of the same device, which
265 * provides the guarantee required by efx_process_channel().
266 */
267 static int efx_poll(struct napi_struct *napi, int budget)
268 {
269 struct efx_channel *channel =
270 container_of(napi, struct efx_channel, napi_str);
271 struct efx_nic *efx = channel->efx;
272 int spent;
273
274 netif_vdbg(efx, intr, efx->net_dev,
275 "channel %d NAPI poll executing on CPU %d\n",
276 channel->channel, raw_smp_processor_id());
277
278 spent = efx_process_channel(channel, budget);
279
280 if (spent < budget) {
281 if (efx_channel_has_rx_queue(channel) &&
282 efx->irq_rx_adaptive &&
283 unlikely(++channel->irq_count == 1000)) {
284 if (unlikely(channel->irq_mod_score <
285 irq_adapt_low_thresh)) {
286 if (channel->irq_moderation > 1) {
287 channel->irq_moderation -= 1;
288 efx->type->push_irq_moderation(channel);
289 }
290 } else if (unlikely(channel->irq_mod_score >
291 irq_adapt_high_thresh)) {
292 if (channel->irq_moderation <
293 efx->irq_rx_moderation) {
294 channel->irq_moderation += 1;
295 efx->type->push_irq_moderation(channel);
296 }
297 }
298 channel->irq_count = 0;
299 channel->irq_mod_score = 0;
300 }
301
302 efx_filter_rfs_expire(channel);
303
304 /* There is no race here; although napi_disable() will
305 * only wait for napi_complete(), this isn't a problem
306 * since efx_nic_eventq_read_ack() will have no effect if
307 * interrupts have already been disabled.
308 */
309 napi_complete(napi);
310 efx_nic_eventq_read_ack(channel);
311 }
312
313 return spent;
314 }
315
316 /* Create event queue
317 * Event queue memory allocations are done only once. If the channel
318 * is reset, the memory buffer will be reused; this guards against
319 * errors during channel reset and also simplifies interrupt handling.
320 */
321 static int efx_probe_eventq(struct efx_channel *channel)
322 {
323 struct efx_nic *efx = channel->efx;
324 unsigned long entries;
325
326 netif_dbg(efx, probe, efx->net_dev,
327 "chan %d create event queue\n", channel->channel);
328
329 /* Build an event queue with room for one event per tx and rx buffer,
330 * plus some extra for link state events and MCDI completions. */
331 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
332 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
333 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
334
335 return efx_nic_probe_eventq(channel);
336 }
337
338 /* Prepare channel's event queue */
339 static int efx_init_eventq(struct efx_channel *channel)
340 {
341 struct efx_nic *efx = channel->efx;
342 int rc;
343
344 EFX_WARN_ON_PARANOID(channel->eventq_init);
345
346 netif_dbg(efx, drv, efx->net_dev,
347 "chan %d init event queue\n", channel->channel);
348
349 rc = efx_nic_init_eventq(channel);
350 if (rc == 0) {
351 efx->type->push_irq_moderation(channel);
352 channel->eventq_read_ptr = 0;
353 channel->eventq_init = true;
354 }
355 return rc;
356 }
357
358 /* Enable event queue processing and NAPI */
359 static void efx_start_eventq(struct efx_channel *channel)
360 {
361 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
362 "chan %d start event queue\n", channel->channel);
363
364 /* Make sure the NAPI handler sees the enabled flag set */
365 channel->enabled = true;
366 smp_wmb();
367
368 napi_enable(&channel->napi_str);
369 efx_nic_eventq_read_ack(channel);
370 }
371
372 /* Disable event queue processing and NAPI */
373 static void efx_stop_eventq(struct efx_channel *channel)
374 {
375 if (!channel->enabled)
376 return;
377
378 napi_disable(&channel->napi_str);
379 channel->enabled = false;
380 }
381
382 static void efx_fini_eventq(struct efx_channel *channel)
383 {
384 if (!channel->eventq_init)
385 return;
386
387 netif_dbg(channel->efx, drv, channel->efx->net_dev,
388 "chan %d fini event queue\n", channel->channel);
389
390 efx_nic_fini_eventq(channel);
391 channel->eventq_init = false;
392 }
393
394 static void efx_remove_eventq(struct efx_channel *channel)
395 {
396 netif_dbg(channel->efx, drv, channel->efx->net_dev,
397 "chan %d remove event queue\n", channel->channel);
398
399 efx_nic_remove_eventq(channel);
400 }
401
402 /**************************************************************************
403 *
404 * Channel handling
405 *
406 *************************************************************************/
407
408 /* Allocate and initialise a channel structure. */
409 static struct efx_channel *
410 efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
411 {
412 struct efx_channel *channel;
413 struct efx_rx_queue *rx_queue;
414 struct efx_tx_queue *tx_queue;
415 int j;
416
417 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
418 if (!channel)
419 return NULL;
420
421 channel->efx = efx;
422 channel->channel = i;
423 channel->type = &efx_default_channel_type;
424
425 for (j = 0; j < EFX_TXQ_TYPES; j++) {
426 tx_queue = &channel->tx_queue[j];
427 tx_queue->efx = efx;
428 tx_queue->queue = i * EFX_TXQ_TYPES + j;
429 tx_queue->channel = channel;
430 }
431
432 rx_queue = &channel->rx_queue;
433 rx_queue->efx = efx;
434 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
435 (unsigned long)rx_queue);
436
437 return channel;
438 }
439
440 /* Allocate and initialise a channel structure, copying parameters
441 * (but not resources) from an old channel structure.
442 */
443 static struct efx_channel *
444 efx_copy_channel(const struct efx_channel *old_channel)
445 {
446 struct efx_channel *channel;
447 struct efx_rx_queue *rx_queue;
448 struct efx_tx_queue *tx_queue;
449 int j;
450
451 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
452 if (!channel)
453 return NULL;
454
455 *channel = *old_channel;
456
457 channel->napi_dev = NULL;
458 memset(&channel->eventq, 0, sizeof(channel->eventq));
459
460 for (j = 0; j < EFX_TXQ_TYPES; j++) {
461 tx_queue = &channel->tx_queue[j];
462 if (tx_queue->channel)
463 tx_queue->channel = channel;
464 tx_queue->buffer = NULL;
465 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
466 }
467
468 rx_queue = &channel->rx_queue;
469 rx_queue->buffer = NULL;
470 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
471 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
472 (unsigned long)rx_queue);
473
474 return channel;
475 }
476
477 static int efx_probe_channel(struct efx_channel *channel)
478 {
479 struct efx_tx_queue *tx_queue;
480 struct efx_rx_queue *rx_queue;
481 int rc;
482
483 netif_dbg(channel->efx, probe, channel->efx->net_dev,
484 "creating channel %d\n", channel->channel);
485
486 rc = channel->type->pre_probe(channel);
487 if (rc)
488 goto fail;
489
490 rc = efx_probe_eventq(channel);
491 if (rc)
492 goto fail;
493
494 efx_for_each_channel_tx_queue(tx_queue, channel) {
495 rc = efx_probe_tx_queue(tx_queue);
496 if (rc)
497 goto fail;
498 }
499
500 efx_for_each_channel_rx_queue(rx_queue, channel) {
501 rc = efx_probe_rx_queue(rx_queue);
502 if (rc)
503 goto fail;
504 }
505
506 return 0;
507
508 fail:
509 efx_remove_channel(channel);
510 return rc;
511 }
512
513 static void
514 efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
515 {
516 struct efx_nic *efx = channel->efx;
517 const char *type;
518 int number;
519
520 number = channel->channel;
521 if (efx->tx_channel_offset == 0) {
522 type = "";
523 } else if (channel->channel < efx->tx_channel_offset) {
524 type = "-rx";
525 } else {
526 type = "-tx";
527 number -= efx->tx_channel_offset;
528 }
529 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
530 }
531
532 static void efx_set_channel_names(struct efx_nic *efx)
533 {
534 struct efx_channel *channel;
535
536 efx_for_each_channel(channel, efx)
537 channel->type->get_name(channel,
538 efx->msi_context[channel->channel].name,
539 sizeof(efx->msi_context[0].name));
540 }
541
542 static int efx_probe_channels(struct efx_nic *efx)
543 {
544 struct efx_channel *channel;
545 int rc;
546
547 /* Restart special buffer allocation */
548 efx->next_buffer_table = 0;
549
550 /* Probe channels in reverse, so that any 'extra' channels
551 * use the start of the buffer table. This allows the traffic
552 * channels to be resized without moving them or wasting the
553 * entries before them.
554 */
555 efx_for_each_channel_rev(channel, efx) {
556 rc = efx_probe_channel(channel);
557 if (rc) {
558 netif_err(efx, probe, efx->net_dev,
559 "failed to create channel %d\n",
560 channel->channel);
561 goto fail;
562 }
563 }
564 efx_set_channel_names(efx);
565
566 return 0;
567
568 fail:
569 efx_remove_channels(efx);
570 return rc;
571 }
572
573 /* Channels are shutdown and reinitialised whilst the NIC is running
574 * to propagate configuration changes (mtu, checksum offload), or
575 * to clear hardware error conditions
576 */
577 static void efx_start_datapath(struct efx_nic *efx)
578 {
579 bool old_rx_scatter = efx->rx_scatter;
580 struct efx_tx_queue *tx_queue;
581 struct efx_rx_queue *rx_queue;
582 struct efx_channel *channel;
583 size_t rx_buf_len;
584
585 /* Calculate the rx buffer allocation parameters required to
586 * support the current MTU, including padding for header
587 * alignment and overruns.
588 */
589 efx->rx_dma_len = (efx->rx_prefix_size +
590 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
591 efx->type->rx_buffer_padding);
592 rx_buf_len = (sizeof(struct efx_rx_page_state) +
593 efx->rx_ip_align + efx->rx_dma_len);
594 if (rx_buf_len <= PAGE_SIZE) {
595 efx->rx_scatter = efx->type->always_rx_scatter;
596 efx->rx_buffer_order = 0;
597 } else if (efx->type->can_rx_scatter) {
598 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
599 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
600 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
601 EFX_RX_BUF_ALIGNMENT) >
602 PAGE_SIZE);
603 efx->rx_scatter = true;
604 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
605 efx->rx_buffer_order = 0;
606 } else {
607 efx->rx_scatter = false;
608 efx->rx_buffer_order = get_order(rx_buf_len);
609 }
610
611 efx_rx_config_page_split(efx);
612 if (efx->rx_buffer_order)
613 netif_dbg(efx, drv, efx->net_dev,
614 "RX buf len=%u; page order=%u batch=%u\n",
615 efx->rx_dma_len, efx->rx_buffer_order,
616 efx->rx_pages_per_batch);
617 else
618 netif_dbg(efx, drv, efx->net_dev,
619 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
620 efx->rx_dma_len, efx->rx_page_buf_step,
621 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
622
623 /* RX filters may also have scatter-enabled flags */
624 if (efx->rx_scatter != old_rx_scatter)
625 efx->type->filter_update_rx_scatter(efx);
626
627 /* We must keep at least one descriptor in a TX ring empty.
628 * We could avoid this when the queue size does not exactly
629 * match the hardware ring size, but it's not that important.
630 * Therefore we stop the queue when one more skb might fill
631 * the ring completely. We wake it when half way back to
632 * empty.
633 */
634 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
635 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
636
637 /* Initialise the channels */
638 efx_for_each_channel(channel, efx) {
639 efx_for_each_channel_tx_queue(tx_queue, channel) {
640 efx_init_tx_queue(tx_queue);
641 atomic_inc(&efx->active_queues);
642 }
643
644 efx_for_each_channel_rx_queue(rx_queue, channel) {
645 efx_init_rx_queue(rx_queue);
646 atomic_inc(&efx->active_queues);
647 efx_stop_eventq(channel);
648 efx_fast_push_rx_descriptors(rx_queue, false);
649 efx_start_eventq(channel);
650 }
651
652 WARN_ON(channel->rx_pkt_n_frags);
653 }
654
655 efx_ptp_start_datapath(efx);
656
657 if (netif_device_present(efx->net_dev))
658 netif_tx_wake_all_queues(efx->net_dev);
659 }
660
661 static void efx_stop_datapath(struct efx_nic *efx)
662 {
663 struct efx_channel *channel;
664 struct efx_tx_queue *tx_queue;
665 struct efx_rx_queue *rx_queue;
666 int rc;
667
668 EFX_ASSERT_RESET_SERIALISED(efx);
669 BUG_ON(efx->port_enabled);
670
671 efx_ptp_stop_datapath(efx);
672
673 /* Stop RX refill */
674 efx_for_each_channel(channel, efx) {
675 efx_for_each_channel_rx_queue(rx_queue, channel)
676 rx_queue->refill_enabled = false;
677 }
678
679 efx_for_each_channel(channel, efx) {
680 /* RX packet processing is pipelined, so wait for the
681 * NAPI handler to complete. At least event queue 0
682 * might be kept active by non-data events, so don't
683 * use napi_synchronize() but actually disable NAPI
684 * temporarily.
685 */
686 if (efx_channel_has_rx_queue(channel)) {
687 efx_stop_eventq(channel);
688 efx_start_eventq(channel);
689 }
690 }
691
692 rc = efx->type->fini_dmaq(efx);
693 if (rc && EFX_WORKAROUND_7803(efx)) {
694 /* Schedule a reset to recover from the flush failure. The
695 * descriptor caches reference memory we're about to free,
696 * but falcon_reconfigure_mac_wrapper() won't reconnect
697 * the MACs because of the pending reset.
698 */
699 netif_err(efx, drv, efx->net_dev,
700 "Resetting to recover from flush failure\n");
701 efx_schedule_reset(efx, RESET_TYPE_ALL);
702 } else if (rc) {
703 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
704 } else {
705 netif_dbg(efx, drv, efx->net_dev,
706 "successfully flushed all queues\n");
707 }
708
709 efx_for_each_channel(channel, efx) {
710 efx_for_each_channel_rx_queue(rx_queue, channel)
711 efx_fini_rx_queue(rx_queue);
712 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
713 efx_fini_tx_queue(tx_queue);
714 }
715 }
716
717 static void efx_remove_channel(struct efx_channel *channel)
718 {
719 struct efx_tx_queue *tx_queue;
720 struct efx_rx_queue *rx_queue;
721
722 netif_dbg(channel->efx, drv, channel->efx->net_dev,
723 "destroy chan %d\n", channel->channel);
724
725 efx_for_each_channel_rx_queue(rx_queue, channel)
726 efx_remove_rx_queue(rx_queue);
727 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
728 efx_remove_tx_queue(tx_queue);
729 efx_remove_eventq(channel);
730 channel->type->post_remove(channel);
731 }
732
733 static void efx_remove_channels(struct efx_nic *efx)
734 {
735 struct efx_channel *channel;
736
737 efx_for_each_channel(channel, efx)
738 efx_remove_channel(channel);
739 }
740
741 int
742 efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
743 {
744 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
745 u32 old_rxq_entries, old_txq_entries;
746 unsigned i, next_buffer_table = 0;
747 int rc, rc2;
748
749 rc = efx_check_disabled(efx);
750 if (rc)
751 return rc;
752
753 /* Not all channels should be reallocated. We must avoid
754 * reallocating their buffer table entries.
755 */
756 efx_for_each_channel(channel, efx) {
757 struct efx_rx_queue *rx_queue;
758 struct efx_tx_queue *tx_queue;
759
760 if (channel->type->copy)
761 continue;
762 next_buffer_table = max(next_buffer_table,
763 channel->eventq.index +
764 channel->eventq.entries);
765 efx_for_each_channel_rx_queue(rx_queue, channel)
766 next_buffer_table = max(next_buffer_table,
767 rx_queue->rxd.index +
768 rx_queue->rxd.entries);
769 efx_for_each_channel_tx_queue(tx_queue, channel)
770 next_buffer_table = max(next_buffer_table,
771 tx_queue->txd.index +
772 tx_queue->txd.entries);
773 }
774
775 efx_device_detach_sync(efx);
776 efx_stop_all(efx);
777 efx_soft_disable_interrupts(efx);
778
779 /* Clone channels (where possible) */
780 memset(other_channel, 0, sizeof(other_channel));
781 for (i = 0; i < efx->n_channels; i++) {
782 channel = efx->channel[i];
783 if (channel->type->copy)
784 channel = channel->type->copy(channel);
785 if (!channel) {
786 rc = -ENOMEM;
787 goto out;
788 }
789 other_channel[i] = channel;
790 }
791
792 /* Swap entry counts and channel pointers */
793 old_rxq_entries = efx->rxq_entries;
794 old_txq_entries = efx->txq_entries;
795 efx->rxq_entries = rxq_entries;
796 efx->txq_entries = txq_entries;
797 for (i = 0; i < efx->n_channels; i++) {
798 channel = efx->channel[i];
799 efx->channel[i] = other_channel[i];
800 other_channel[i] = channel;
801 }
802
803 /* Restart buffer table allocation */
804 efx->next_buffer_table = next_buffer_table;
805
806 for (i = 0; i < efx->n_channels; i++) {
807 channel = efx->channel[i];
808 if (!channel->type->copy)
809 continue;
810 rc = efx_probe_channel(channel);
811 if (rc)
812 goto rollback;
813 efx_init_napi_channel(efx->channel[i]);
814 }
815
816 out:
817 /* Destroy unused channel structures */
818 for (i = 0; i < efx->n_channels; i++) {
819 channel = other_channel[i];
820 if (channel && channel->type->copy) {
821 efx_fini_napi_channel(channel);
822 efx_remove_channel(channel);
823 kfree(channel);
824 }
825 }
826
827 rc2 = efx_soft_enable_interrupts(efx);
828 if (rc2) {
829 rc = rc ? rc : rc2;
830 netif_err(efx, drv, efx->net_dev,
831 "unable to restart interrupts on channel reallocation\n");
832 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
833 } else {
834 efx_start_all(efx);
835 netif_device_attach(efx->net_dev);
836 }
837 return rc;
838
839 rollback:
840 /* Swap back */
841 efx->rxq_entries = old_rxq_entries;
842 efx->txq_entries = old_txq_entries;
843 for (i = 0; i < efx->n_channels; i++) {
844 channel = efx->channel[i];
845 efx->channel[i] = other_channel[i];
846 other_channel[i] = channel;
847 }
848 goto out;
849 }
850
851 void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
852 {
853 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
854 }
855
856 static const struct efx_channel_type efx_default_channel_type = {
857 .pre_probe = efx_channel_dummy_op_int,
858 .post_remove = efx_channel_dummy_op_void,
859 .get_name = efx_get_channel_name,
860 .copy = efx_copy_channel,
861 .keep_eventq = false,
862 };
863
864 int efx_channel_dummy_op_int(struct efx_channel *channel)
865 {
866 return 0;
867 }
868
869 void efx_channel_dummy_op_void(struct efx_channel *channel)
870 {
871 }
872
873 /**************************************************************************
874 *
875 * Port handling
876 *
877 **************************************************************************/
878
879 /* This ensures that the kernel is kept informed (via
880 * netif_carrier_on/off) of the link status, and also maintains the
881 * link status's stop on the port's TX queue.
882 */
883 void efx_link_status_changed(struct efx_nic *efx)
884 {
885 struct efx_link_state *link_state = &efx->link_state;
886
887 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
888 * that no events are triggered between unregister_netdev() and the
889 * driver unloading. A more general condition is that NETDEV_CHANGE
890 * can only be generated between NETDEV_UP and NETDEV_DOWN */
891 if (!netif_running(efx->net_dev))
892 return;
893
894 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
895 efx->n_link_state_changes++;
896
897 if (link_state->up)
898 netif_carrier_on(efx->net_dev);
899 else
900 netif_carrier_off(efx->net_dev);
901 }
902
903 /* Status message for kernel log */
904 if (link_state->up)
905 netif_info(efx, link, efx->net_dev,
906 "link up at %uMbps %s-duplex (MTU %d)\n",
907 link_state->speed, link_state->fd ? "full" : "half",
908 efx->net_dev->mtu);
909 else
910 netif_info(efx, link, efx->net_dev, "link down\n");
911 }
912
913 void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
914 {
915 efx->link_advertising = advertising;
916 if (advertising) {
917 if (advertising & ADVERTISED_Pause)
918 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
919 else
920 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
921 if (advertising & ADVERTISED_Asym_Pause)
922 efx->wanted_fc ^= EFX_FC_TX;
923 }
924 }
925
926 void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
927 {
928 efx->wanted_fc = wanted_fc;
929 if (efx->link_advertising) {
930 if (wanted_fc & EFX_FC_RX)
931 efx->link_advertising |= (ADVERTISED_Pause |
932 ADVERTISED_Asym_Pause);
933 else
934 efx->link_advertising &= ~(ADVERTISED_Pause |
935 ADVERTISED_Asym_Pause);
936 if (wanted_fc & EFX_FC_TX)
937 efx->link_advertising ^= ADVERTISED_Asym_Pause;
938 }
939 }
940
941 static void efx_fini_port(struct efx_nic *efx);
942
943 /* Push loopback/power/transmit disable settings to the PHY, and reconfigure
944 * the MAC appropriately. All other PHY configuration changes are pushed
945 * through phy_op->set_settings(), and pushed asynchronously to the MAC
946 * through efx_monitor().
947 *
948 * Callers must hold the mac_lock
949 */
950 int __efx_reconfigure_port(struct efx_nic *efx)
951 {
952 enum efx_phy_mode phy_mode;
953 int rc;
954
955 WARN_ON(!mutex_is_locked(&efx->mac_lock));
956
957 /* Disable PHY transmit in mac level loopbacks */
958 phy_mode = efx->phy_mode;
959 if (LOOPBACK_INTERNAL(efx))
960 efx->phy_mode |= PHY_MODE_TX_DISABLED;
961 else
962 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
963
964 rc = efx->type->reconfigure_port(efx);
965
966 if (rc)
967 efx->phy_mode = phy_mode;
968
969 return rc;
970 }
971
972 /* Reinitialise the MAC to pick up new PHY settings, even if the port is
973 * disabled. */
974 int efx_reconfigure_port(struct efx_nic *efx)
975 {
976 int rc;
977
978 EFX_ASSERT_RESET_SERIALISED(efx);
979
980 mutex_lock(&efx->mac_lock);
981 rc = __efx_reconfigure_port(efx);
982 mutex_unlock(&efx->mac_lock);
983
984 return rc;
985 }
986
987 /* Asynchronous work item for changing MAC promiscuity and multicast
988 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
989 * MAC directly. */
990 static void efx_mac_work(struct work_struct *data)
991 {
992 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
993
994 mutex_lock(&efx->mac_lock);
995 if (efx->port_enabled)
996 efx->type->reconfigure_mac(efx);
997 mutex_unlock(&efx->mac_lock);
998 }
999
1000 static int efx_probe_port(struct efx_nic *efx)
1001 {
1002 int rc;
1003
1004 netif_dbg(efx, probe, efx->net_dev, "create port\n");
1005
1006 if (phy_flash_cfg)
1007 efx->phy_mode = PHY_MODE_SPECIAL;
1008
1009 /* Connect up MAC/PHY operations table */
1010 rc = efx->type->probe_port(efx);
1011 if (rc)
1012 return rc;
1013
1014 /* Initialise MAC address to permanent address */
1015 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN);
1016
1017 return 0;
1018 }
1019
1020 static int efx_init_port(struct efx_nic *efx)
1021 {
1022 int rc;
1023
1024 netif_dbg(efx, drv, efx->net_dev, "init port\n");
1025
1026 mutex_lock(&efx->mac_lock);
1027
1028 rc = efx->phy_op->init(efx);
1029 if (rc)
1030 goto fail1;
1031
1032 efx->port_initialized = true;
1033
1034 /* Reconfigure the MAC before creating dma queues (required for
1035 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
1036 efx->type->reconfigure_mac(efx);
1037
1038 /* Ensure the PHY advertises the correct flow control settings */
1039 rc = efx->phy_op->reconfigure(efx);
1040 if (rc)
1041 goto fail2;
1042
1043 mutex_unlock(&efx->mac_lock);
1044 return 0;
1045
1046 fail2:
1047 efx->phy_op->fini(efx);
1048 fail1:
1049 mutex_unlock(&efx->mac_lock);
1050 return rc;
1051 }
1052
1053 static void efx_start_port(struct efx_nic *efx)
1054 {
1055 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
1056 BUG_ON(efx->port_enabled);
1057
1058 mutex_lock(&efx->mac_lock);
1059 efx->port_enabled = true;
1060
1061 /* Ensure MAC ingress/egress is enabled */
1062 efx->type->reconfigure_mac(efx);
1063
1064 mutex_unlock(&efx->mac_lock);
1065 }
1066
1067 /* Cancel work for MAC reconfiguration, periodic hardware monitoring
1068 * and the async self-test, wait for them to finish and prevent them
1069 * being scheduled again. This doesn't cover online resets, which
1070 * should only be cancelled when removing the device.
1071 */
1072 static void efx_stop_port(struct efx_nic *efx)
1073 {
1074 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
1075
1076 EFX_ASSERT_RESET_SERIALISED(efx);
1077
1078 mutex_lock(&efx->mac_lock);
1079 efx->port_enabled = false;
1080 mutex_unlock(&efx->mac_lock);
1081
1082 /* Serialise against efx_set_multicast_list() */
1083 netif_addr_lock_bh(efx->net_dev);
1084 netif_addr_unlock_bh(efx->net_dev);
1085
1086 cancel_delayed_work_sync(&efx->monitor_work);
1087 efx_selftest_async_cancel(efx);
1088 cancel_work_sync(&efx->mac_work);
1089 }
1090
1091 static void efx_fini_port(struct efx_nic *efx)
1092 {
1093 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
1094
1095 if (!efx->port_initialized)
1096 return;
1097
1098 efx->phy_op->fini(efx);
1099 efx->port_initialized = false;
1100
1101 efx->link_state.up = false;
1102 efx_link_status_changed(efx);
1103 }
1104
1105 static void efx_remove_port(struct efx_nic *efx)
1106 {
1107 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
1108
1109 efx->type->remove_port(efx);
1110 }
1111
1112 /**************************************************************************
1113 *
1114 * NIC handling
1115 *
1116 **************************************************************************/
1117
1118 static LIST_HEAD(efx_primary_list);
1119 static LIST_HEAD(efx_unassociated_list);
1120
1121 static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right)
1122 {
1123 return left->type == right->type &&
1124 left->vpd_sn && right->vpd_sn &&
1125 !strcmp(left->vpd_sn, right->vpd_sn);
1126 }
1127
1128 static void efx_associate(struct efx_nic *efx)
1129 {
1130 struct efx_nic *other, *next;
1131
1132 if (efx->primary == efx) {
1133 /* Adding primary function; look for secondaries */
1134
1135 netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n");
1136 list_add_tail(&efx->node, &efx_primary_list);
1137
1138 list_for_each_entry_safe(other, next, &efx_unassociated_list,
1139 node) {
1140 if (efx_same_controller(efx, other)) {
1141 list_del(&other->node);
1142 netif_dbg(other, probe, other->net_dev,
1143 "moving to secondary list of %s %s\n",
1144 pci_name(efx->pci_dev),
1145 efx->net_dev->name);
1146 list_add_tail(&other->node,
1147 &efx->secondary_list);
1148 other->primary = efx;
1149 }
1150 }
1151 } else {
1152 /* Adding secondary function; look for primary */
1153
1154 list_for_each_entry(other, &efx_primary_list, node) {
1155 if (efx_same_controller(efx, other)) {
1156 netif_dbg(efx, probe, efx->net_dev,
1157 "adding to secondary list of %s %s\n",
1158 pci_name(other->pci_dev),
1159 other->net_dev->name);
1160 list_add_tail(&efx->node,
1161 &other->secondary_list);
1162 efx->primary = other;
1163 return;
1164 }
1165 }
1166
1167 netif_dbg(efx, probe, efx->net_dev,
1168 "adding to unassociated list\n");
1169 list_add_tail(&efx->node, &efx_unassociated_list);
1170 }
1171 }
1172
1173 static void efx_dissociate(struct efx_nic *efx)
1174 {
1175 struct efx_nic *other, *next;
1176
1177 list_del(&efx->node);
1178 efx->primary = NULL;
1179
1180 list_for_each_entry_safe(other, next, &efx->secondary_list, node) {
1181 list_del(&other->node);
1182 netif_dbg(other, probe, other->net_dev,
1183 "moving to unassociated list\n");
1184 list_add_tail(&other->node, &efx_unassociated_list);
1185 other->primary = NULL;
1186 }
1187 }
1188
1189 /* This configures the PCI device to enable I/O and DMA. */
1190 static int efx_init_io(struct efx_nic *efx)
1191 {
1192 struct pci_dev *pci_dev = efx->pci_dev;
1193 dma_addr_t dma_mask = efx->type->max_dma_mask;
1194 unsigned int mem_map_size = efx->type->mem_map_size(efx);
1195 int rc;
1196
1197 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
1198
1199 rc = pci_enable_device(pci_dev);
1200 if (rc) {
1201 netif_err(efx, probe, efx->net_dev,
1202 "failed to enable PCI device\n");
1203 goto fail1;
1204 }
1205
1206 pci_set_master(pci_dev);
1207
1208 /* Set the PCI DMA mask. Try all possibilities from our
1209 * genuine mask down to 32 bits, because some architectures
1210 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1211 * masks event though they reject 46 bit masks.
1212 */
1213 while (dma_mask > 0x7fffffffUL) {
1214 if (dma_supported(&pci_dev->dev, dma_mask)) {
1215 rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask);
1216 if (rc == 0)
1217 break;
1218 }
1219 dma_mask >>= 1;
1220 }
1221 if (rc) {
1222 netif_err(efx, probe, efx->net_dev,
1223 "could not find a suitable DMA mask\n");
1224 goto fail2;
1225 }
1226 netif_dbg(efx, probe, efx->net_dev,
1227 "using DMA mask %llx\n", (unsigned long long) dma_mask);
1228
1229 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1230 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
1231 if (rc) {
1232 netif_err(efx, probe, efx->net_dev,
1233 "request for memory BAR failed\n");
1234 rc = -EIO;
1235 goto fail3;
1236 }
1237 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
1238 if (!efx->membase) {
1239 netif_err(efx, probe, efx->net_dev,
1240 "could not map memory BAR at %llx+%x\n",
1241 (unsigned long long)efx->membase_phys, mem_map_size);
1242 rc = -ENOMEM;
1243 goto fail4;
1244 }
1245 netif_dbg(efx, probe, efx->net_dev,
1246 "memory BAR at %llx+%x (virtual %p)\n",
1247 (unsigned long long)efx->membase_phys, mem_map_size,
1248 efx->membase);
1249
1250 return 0;
1251
1252 fail4:
1253 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
1254 fail3:
1255 efx->membase_phys = 0;
1256 fail2:
1257 pci_disable_device(efx->pci_dev);
1258 fail1:
1259 return rc;
1260 }
1261
1262 static void efx_fini_io(struct efx_nic *efx)
1263 {
1264 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
1265
1266 if (efx->membase) {
1267 iounmap(efx->membase);
1268 efx->membase = NULL;
1269 }
1270
1271 if (efx->membase_phys) {
1272 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
1273 efx->membase_phys = 0;
1274 }
1275
1276 pci_disable_device(efx->pci_dev);
1277 }
1278
1279 static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
1280 {
1281 cpumask_var_t thread_mask;
1282 unsigned int count;
1283 int cpu;
1284
1285 if (rss_cpus) {
1286 count = rss_cpus;
1287 } else {
1288 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1289 netif_warn(efx, probe, efx->net_dev,
1290 "RSS disabled due to allocation failure\n");
1291 return 1;
1292 }
1293
1294 count = 0;
1295 for_each_online_cpu(cpu) {
1296 if (!cpumask_test_cpu(cpu, thread_mask)) {
1297 ++count;
1298 cpumask_or(thread_mask, thread_mask,
1299 topology_thread_cpumask(cpu));
1300 }
1301 }
1302
1303 free_cpumask_var(thread_mask);
1304 }
1305
1306 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1307 * table entries that are inaccessible to VFs
1308 */
1309 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1310 count > efx_vf_size(efx)) {
1311 netif_warn(efx, probe, efx->net_dev,
1312 "Reducing number of RSS channels from %u to %u for "
1313 "VF support. Increase vf-msix-limit to use more "
1314 "channels on the PF.\n",
1315 count, efx_vf_size(efx));
1316 count = efx_vf_size(efx);
1317 }
1318
1319 return count;
1320 }
1321
1322 /* Probe the number and type of interrupts we are able to obtain, and
1323 * the resulting numbers of channels and RX queues.
1324 */
1325 static int efx_probe_interrupts(struct efx_nic *efx)
1326 {
1327 unsigned int extra_channels = 0;
1328 unsigned int i, j;
1329 int rc;
1330
1331 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1332 if (efx->extra_channel_type[i])
1333 ++extra_channels;
1334
1335 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
1336 struct msix_entry xentries[EFX_MAX_CHANNELS];
1337 unsigned int n_channels;
1338
1339 n_channels = efx_wanted_parallelism(efx);
1340 if (separate_tx_channels)
1341 n_channels *= 2;
1342 n_channels += extra_channels;
1343 n_channels = min(n_channels, efx->max_channels);
1344
1345 for (i = 0; i < n_channels; i++)
1346 xentries[i].entry = i;
1347 rc = pci_enable_msix_range(efx->pci_dev,
1348 xentries, 1, n_channels);
1349 if (rc < 0) {
1350 /* Fall back to single channel MSI */
1351 efx->interrupt_mode = EFX_INT_MODE_MSI;
1352 netif_err(efx, drv, efx->net_dev,
1353 "could not enable MSI-X\n");
1354 } else if (rc < n_channels) {
1355 netif_err(efx, drv, efx->net_dev,
1356 "WARNING: Insufficient MSI-X vectors"
1357 " available (%d < %u).\n", rc, n_channels);
1358 netif_err(efx, drv, efx->net_dev,
1359 "WARNING: Performance may be reduced.\n");
1360 n_channels = rc;
1361 }
1362
1363 if (rc > 0) {
1364 efx->n_channels = n_channels;
1365 if (n_channels > extra_channels)
1366 n_channels -= extra_channels;
1367 if (separate_tx_channels) {
1368 efx->n_tx_channels = max(n_channels / 2, 1U);
1369 efx->n_rx_channels = max(n_channels -
1370 efx->n_tx_channels,
1371 1U);
1372 } else {
1373 efx->n_tx_channels = n_channels;
1374 efx->n_rx_channels = n_channels;
1375 }
1376 for (i = 0; i < efx->n_channels; i++)
1377 efx_get_channel(efx, i)->irq =
1378 xentries[i].vector;
1379 }
1380 }
1381
1382 /* Try single interrupt MSI */
1383 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
1384 efx->n_channels = 1;
1385 efx->n_rx_channels = 1;
1386 efx->n_tx_channels = 1;
1387 rc = pci_enable_msi(efx->pci_dev);
1388 if (rc == 0) {
1389 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
1390 } else {
1391 netif_err(efx, drv, efx->net_dev,
1392 "could not enable MSI\n");
1393 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1394 }
1395 }
1396
1397 /* Assume legacy interrupts */
1398 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
1399 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
1400 efx->n_rx_channels = 1;
1401 efx->n_tx_channels = 1;
1402 efx->legacy_irq = efx->pci_dev->irq;
1403 }
1404
1405 /* Assign extra channels if possible */
1406 j = efx->n_channels;
1407 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1408 if (!efx->extra_channel_type[i])
1409 continue;
1410 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1411 efx->n_channels <= extra_channels) {
1412 efx->extra_channel_type[i]->handle_no_channel(efx);
1413 } else {
1414 --j;
1415 efx_get_channel(efx, j)->type =
1416 efx->extra_channel_type[i];
1417 }
1418 }
1419
1420 /* RSS might be usable on VFs even if it is disabled on the PF */
1421 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ?
1422 efx->n_rx_channels : efx_vf_size(efx));
1423
1424 return 0;
1425 }
1426
1427 static int efx_soft_enable_interrupts(struct efx_nic *efx)
1428 {
1429 struct efx_channel *channel, *end_channel;
1430 int rc;
1431
1432 BUG_ON(efx->state == STATE_DISABLED);
1433
1434 efx->irq_soft_enabled = true;
1435 smp_wmb();
1436
1437 efx_for_each_channel(channel, efx) {
1438 if (!channel->type->keep_eventq) {
1439 rc = efx_init_eventq(channel);
1440 if (rc)
1441 goto fail;
1442 }
1443 efx_start_eventq(channel);
1444 }
1445
1446 efx_mcdi_mode_event(efx);
1447
1448 return 0;
1449 fail:
1450 end_channel = channel;
1451 efx_for_each_channel(channel, efx) {
1452 if (channel == end_channel)
1453 break;
1454 efx_stop_eventq(channel);
1455 if (!channel->type->keep_eventq)
1456 efx_fini_eventq(channel);
1457 }
1458
1459 return rc;
1460 }
1461
1462 static void efx_soft_disable_interrupts(struct efx_nic *efx)
1463 {
1464 struct efx_channel *channel;
1465
1466 if (efx->state == STATE_DISABLED)
1467 return;
1468
1469 efx_mcdi_mode_poll(efx);
1470
1471 efx->irq_soft_enabled = false;
1472 smp_wmb();
1473
1474 if (efx->legacy_irq)
1475 synchronize_irq(efx->legacy_irq);
1476
1477 efx_for_each_channel(channel, efx) {
1478 if (channel->irq)
1479 synchronize_irq(channel->irq);
1480
1481 efx_stop_eventq(channel);
1482 if (!channel->type->keep_eventq)
1483 efx_fini_eventq(channel);
1484 }
1485
1486 /* Flush the asynchronous MCDI request queue */
1487 efx_mcdi_flush_async(efx);
1488 }
1489
1490 static int efx_enable_interrupts(struct efx_nic *efx)
1491 {
1492 struct efx_channel *channel, *end_channel;
1493 int rc;
1494
1495 BUG_ON(efx->state == STATE_DISABLED);
1496
1497 if (efx->eeh_disabled_legacy_irq) {
1498 enable_irq(efx->legacy_irq);
1499 efx->eeh_disabled_legacy_irq = false;
1500 }
1501
1502 efx->type->irq_enable_master(efx);
1503
1504 efx_for_each_channel(channel, efx) {
1505 if (channel->type->keep_eventq) {
1506 rc = efx_init_eventq(channel);
1507 if (rc)
1508 goto fail;
1509 }
1510 }
1511
1512 rc = efx_soft_enable_interrupts(efx);
1513 if (rc)
1514 goto fail;
1515
1516 return 0;
1517
1518 fail:
1519 end_channel = channel;
1520 efx_for_each_channel(channel, efx) {
1521 if (channel == end_channel)
1522 break;
1523 if (channel->type->keep_eventq)
1524 efx_fini_eventq(channel);
1525 }
1526
1527 efx->type->irq_disable_non_ev(efx);
1528
1529 return rc;
1530 }
1531
1532 static void efx_disable_interrupts(struct efx_nic *efx)
1533 {
1534 struct efx_channel *channel;
1535
1536 efx_soft_disable_interrupts(efx);
1537
1538 efx_for_each_channel(channel, efx) {
1539 if (channel->type->keep_eventq)
1540 efx_fini_eventq(channel);
1541 }
1542
1543 efx->type->irq_disable_non_ev(efx);
1544 }
1545
1546 static void efx_remove_interrupts(struct efx_nic *efx)
1547 {
1548 struct efx_channel *channel;
1549
1550 /* Remove MSI/MSI-X interrupts */
1551 efx_for_each_channel(channel, efx)
1552 channel->irq = 0;
1553 pci_disable_msi(efx->pci_dev);
1554 pci_disable_msix(efx->pci_dev);
1555
1556 /* Remove legacy interrupt */
1557 efx->legacy_irq = 0;
1558 }
1559
1560 static void efx_set_channels(struct efx_nic *efx)
1561 {
1562 struct efx_channel *channel;
1563 struct efx_tx_queue *tx_queue;
1564
1565 efx->tx_channel_offset =
1566 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
1567
1568 /* We need to mark which channels really have RX and TX
1569 * queues, and adjust the TX queue numbers if we have separate
1570 * RX-only and TX-only channels.
1571 */
1572 efx_for_each_channel(channel, efx) {
1573 if (channel->channel < efx->n_rx_channels)
1574 channel->rx_queue.core_index = channel->channel;
1575 else
1576 channel->rx_queue.core_index = -1;
1577
1578 efx_for_each_channel_tx_queue(tx_queue, channel)
1579 tx_queue->queue -= (efx->tx_channel_offset *
1580 EFX_TXQ_TYPES);
1581 }
1582 }
1583
1584 static int efx_probe_nic(struct efx_nic *efx)
1585 {
1586 size_t i;
1587 int rc;
1588
1589 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
1590
1591 /* Carry out hardware-type specific initialisation */
1592 rc = efx->type->probe(efx);
1593 if (rc)
1594 return rc;
1595
1596 /* Determine the number of channels and queues by trying to hook
1597 * in MSI-X interrupts. */
1598 rc = efx_probe_interrupts(efx);
1599 if (rc)
1600 goto fail1;
1601
1602 rc = efx->type->dimension_resources(efx);
1603 if (rc)
1604 goto fail2;
1605
1606 if (efx->n_channels > 1)
1607 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
1608 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
1609 efx->rx_indir_table[i] =
1610 ethtool_rxfh_indir_default(i, efx->rss_spread);
1611
1612 efx_set_channels(efx);
1613 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1614 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
1615
1616 /* Initialise the interrupt moderation settings */
1617 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1618 true);
1619
1620 return 0;
1621
1622 fail2:
1623 efx_remove_interrupts(efx);
1624 fail1:
1625 efx->type->remove(efx);
1626 return rc;
1627 }
1628
1629 static void efx_remove_nic(struct efx_nic *efx)
1630 {
1631 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
1632
1633 efx_remove_interrupts(efx);
1634 efx->type->remove(efx);
1635 }
1636
1637 static int efx_probe_filters(struct efx_nic *efx)
1638 {
1639 int rc;
1640
1641 spin_lock_init(&efx->filter_lock);
1642
1643 rc = efx->type->filter_table_probe(efx);
1644 if (rc)
1645 return rc;
1646
1647 #ifdef CONFIG_RFS_ACCEL
1648 if (efx->type->offload_features & NETIF_F_NTUPLE) {
1649 efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters,
1650 sizeof(*efx->rps_flow_id),
1651 GFP_KERNEL);
1652 if (!efx->rps_flow_id) {
1653 efx->type->filter_table_remove(efx);
1654 return -ENOMEM;
1655 }
1656 }
1657 #endif
1658
1659 return 0;
1660 }
1661
1662 static void efx_remove_filters(struct efx_nic *efx)
1663 {
1664 #ifdef CONFIG_RFS_ACCEL
1665 kfree(efx->rps_flow_id);
1666 #endif
1667 efx->type->filter_table_remove(efx);
1668 }
1669
1670 static void efx_restore_filters(struct efx_nic *efx)
1671 {
1672 efx->type->filter_table_restore(efx);
1673 }
1674
1675 /**************************************************************************
1676 *
1677 * NIC startup/shutdown
1678 *
1679 *************************************************************************/
1680
1681 static int efx_probe_all(struct efx_nic *efx)
1682 {
1683 int rc;
1684
1685 rc = efx_probe_nic(efx);
1686 if (rc) {
1687 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
1688 goto fail1;
1689 }
1690
1691 rc = efx_probe_port(efx);
1692 if (rc) {
1693 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
1694 goto fail2;
1695 }
1696
1697 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1698 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1699 rc = -EINVAL;
1700 goto fail3;
1701 }
1702 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
1703
1704 rc = efx_probe_filters(efx);
1705 if (rc) {
1706 netif_err(efx, probe, efx->net_dev,
1707 "failed to create filter tables\n");
1708 goto fail3;
1709 }
1710
1711 rc = efx_probe_channels(efx);
1712 if (rc)
1713 goto fail4;
1714
1715 return 0;
1716
1717 fail4:
1718 efx_remove_filters(efx);
1719 fail3:
1720 efx_remove_port(efx);
1721 fail2:
1722 efx_remove_nic(efx);
1723 fail1:
1724 return rc;
1725 }
1726
1727 /* If the interface is supposed to be running but is not, start
1728 * the hardware and software data path, regular activity for the port
1729 * (MAC statistics, link polling, etc.) and schedule the port to be
1730 * reconfigured. Interrupts must already be enabled. This function
1731 * is safe to call multiple times, so long as the NIC is not disabled.
1732 * Requires the RTNL lock.
1733 */
1734 static void efx_start_all(struct efx_nic *efx)
1735 {
1736 EFX_ASSERT_RESET_SERIALISED(efx);
1737 BUG_ON(efx->state == STATE_DISABLED);
1738
1739 /* Check that it is appropriate to restart the interface. All
1740 * of these flags are safe to read under just the rtnl lock */
1741 if (efx->port_enabled || !netif_running(efx->net_dev))
1742 return;
1743
1744 efx_start_port(efx);
1745 efx_start_datapath(efx);
1746
1747 /* Start the hardware monitor if there is one */
1748 if (efx->type->monitor != NULL)
1749 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1750 efx_monitor_interval);
1751
1752 /* If link state detection is normally event-driven, we have
1753 * to poll now because we could have missed a change
1754 */
1755 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1756 mutex_lock(&efx->mac_lock);
1757 if (efx->phy_op->poll(efx))
1758 efx_link_status_changed(efx);
1759 mutex_unlock(&efx->mac_lock);
1760 }
1761
1762 efx->type->start_stats(efx);
1763 efx->type->pull_stats(efx);
1764 spin_lock_bh(&efx->stats_lock);
1765 efx->type->update_stats(efx, NULL, NULL);
1766 spin_unlock_bh(&efx->stats_lock);
1767 }
1768
1769 /* Quiesce the hardware and software data path, and regular activity
1770 * for the port without bringing the link down. Safe to call multiple
1771 * times with the NIC in almost any state, but interrupts should be
1772 * enabled. Requires the RTNL lock.
1773 */
1774 static void efx_stop_all(struct efx_nic *efx)
1775 {
1776 EFX_ASSERT_RESET_SERIALISED(efx);
1777
1778 /* port_enabled can be read safely under the rtnl lock */
1779 if (!efx->port_enabled)
1780 return;
1781
1782 /* update stats before we go down so we can accurately count
1783 * rx_nodesc_drops
1784 */
1785 efx->type->pull_stats(efx);
1786 spin_lock_bh(&efx->stats_lock);
1787 efx->type->update_stats(efx, NULL, NULL);
1788 spin_unlock_bh(&efx->stats_lock);
1789 efx->type->stop_stats(efx);
1790 efx_stop_port(efx);
1791
1792 /* Stop the kernel transmit interface. This is only valid if
1793 * the device is stopped or detached; otherwise the watchdog
1794 * may fire immediately.
1795 */
1796 WARN_ON(netif_running(efx->net_dev) &&
1797 netif_device_present(efx->net_dev));
1798 netif_tx_disable(efx->net_dev);
1799
1800 efx_stop_datapath(efx);
1801 }
1802
1803 static void efx_remove_all(struct efx_nic *efx)
1804 {
1805 efx_remove_channels(efx);
1806 efx_remove_filters(efx);
1807 efx_remove_port(efx);
1808 efx_remove_nic(efx);
1809 }
1810
1811 /**************************************************************************
1812 *
1813 * Interrupt moderation
1814 *
1815 **************************************************************************/
1816
1817 static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
1818 {
1819 if (usecs == 0)
1820 return 0;
1821 if (usecs * 1000 < quantum_ns)
1822 return 1; /* never round down to 0 */
1823 return usecs * 1000 / quantum_ns;
1824 }
1825
1826 /* Set interrupt moderation parameters */
1827 int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1828 unsigned int rx_usecs, bool rx_adaptive,
1829 bool rx_may_override_tx)
1830 {
1831 struct efx_channel *channel;
1832 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1833 efx->timer_quantum_ns,
1834 1000);
1835 unsigned int tx_ticks;
1836 unsigned int rx_ticks;
1837
1838 EFX_ASSERT_RESET_SERIALISED(efx);
1839
1840 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
1841 return -EINVAL;
1842
1843 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1844 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1845
1846 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1847 !rx_may_override_tx) {
1848 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1849 "RX and TX IRQ moderation must be equal\n");
1850 return -EINVAL;
1851 }
1852
1853 efx->irq_rx_adaptive = rx_adaptive;
1854 efx->irq_rx_moderation = rx_ticks;
1855 efx_for_each_channel(channel, efx) {
1856 if (efx_channel_has_rx_queue(channel))
1857 channel->irq_moderation = rx_ticks;
1858 else if (efx_channel_has_tx_queues(channel))
1859 channel->irq_moderation = tx_ticks;
1860 }
1861
1862 return 0;
1863 }
1864
1865 void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
1866 unsigned int *rx_usecs, bool *rx_adaptive)
1867 {
1868 /* We must round up when converting ticks to microseconds
1869 * because we round down when converting the other way.
1870 */
1871
1872 *rx_adaptive = efx->irq_rx_adaptive;
1873 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
1874 efx->timer_quantum_ns,
1875 1000);
1876
1877 /* If channels are shared between RX and TX, so is IRQ
1878 * moderation. Otherwise, IRQ moderation is the same for all
1879 * TX channels and is not adaptive.
1880 */
1881 if (efx->tx_channel_offset == 0)
1882 *tx_usecs = *rx_usecs;
1883 else
1884 *tx_usecs = DIV_ROUND_UP(
1885 efx->channel[efx->tx_channel_offset]->irq_moderation *
1886 efx->timer_quantum_ns,
1887 1000);
1888 }
1889
1890 /**************************************************************************
1891 *
1892 * Hardware monitor
1893 *
1894 **************************************************************************/
1895
1896 /* Run periodically off the general workqueue */
1897 static void efx_monitor(struct work_struct *data)
1898 {
1899 struct efx_nic *efx = container_of(data, struct efx_nic,
1900 monitor_work.work);
1901
1902 netif_vdbg(efx, timer, efx->net_dev,
1903 "hardware monitor executing on CPU %d\n",
1904 raw_smp_processor_id());
1905 BUG_ON(efx->type->monitor == NULL);
1906
1907 /* If the mac_lock is already held then it is likely a port
1908 * reconfiguration is already in place, which will likely do
1909 * most of the work of monitor() anyway. */
1910 if (mutex_trylock(&efx->mac_lock)) {
1911 if (efx->port_enabled)
1912 efx->type->monitor(efx);
1913 mutex_unlock(&efx->mac_lock);
1914 }
1915
1916 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1917 efx_monitor_interval);
1918 }
1919
1920 /**************************************************************************
1921 *
1922 * ioctls
1923 *
1924 *************************************************************************/
1925
1926 /* Net device ioctl
1927 * Context: process, rtnl_lock() held.
1928 */
1929 static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1930 {
1931 struct efx_nic *efx = netdev_priv(net_dev);
1932 struct mii_ioctl_data *data = if_mii(ifr);
1933
1934 if (cmd == SIOCSHWTSTAMP)
1935 return efx_ptp_set_ts_config(efx, ifr);
1936 if (cmd == SIOCGHWTSTAMP)
1937 return efx_ptp_get_ts_config(efx, ifr);
1938
1939 /* Convert phy_id from older PRTAD/DEVAD format */
1940 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1941 (data->phy_id & 0xfc00) == 0x0400)
1942 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1943
1944 return mdio_mii_ioctl(&efx->mdio, data, cmd);
1945 }
1946
1947 /**************************************************************************
1948 *
1949 * NAPI interface
1950 *
1951 **************************************************************************/
1952
1953 static void efx_init_napi_channel(struct efx_channel *channel)
1954 {
1955 struct efx_nic *efx = channel->efx;
1956
1957 channel->napi_dev = efx->net_dev;
1958 netif_napi_add(channel->napi_dev, &channel->napi_str,
1959 efx_poll, napi_weight);
1960 }
1961
1962 static void efx_init_napi(struct efx_nic *efx)
1963 {
1964 struct efx_channel *channel;
1965
1966 efx_for_each_channel(channel, efx)
1967 efx_init_napi_channel(channel);
1968 }
1969
1970 static void efx_fini_napi_channel(struct efx_channel *channel)
1971 {
1972 if (channel->napi_dev)
1973 netif_napi_del(&channel->napi_str);
1974 channel->napi_dev = NULL;
1975 }
1976
1977 static void efx_fini_napi(struct efx_nic *efx)
1978 {
1979 struct efx_channel *channel;
1980
1981 efx_for_each_channel(channel, efx)
1982 efx_fini_napi_channel(channel);
1983 }
1984
1985 /**************************************************************************
1986 *
1987 * Kernel netpoll interface
1988 *
1989 *************************************************************************/
1990
1991 #ifdef CONFIG_NET_POLL_CONTROLLER
1992
1993 /* Although in the common case interrupts will be disabled, this is not
1994 * guaranteed. However, all our work happens inside the NAPI callback,
1995 * so no locking is required.
1996 */
1997 static void efx_netpoll(struct net_device *net_dev)
1998 {
1999 struct efx_nic *efx = netdev_priv(net_dev);
2000 struct efx_channel *channel;
2001
2002 efx_for_each_channel(channel, efx)
2003 efx_schedule_channel(channel);
2004 }
2005
2006 #endif
2007
2008 /**************************************************************************
2009 *
2010 * Kernel net device interface
2011 *
2012 *************************************************************************/
2013
2014 /* Context: process, rtnl_lock() held. */
2015 static int efx_net_open(struct net_device *net_dev)
2016 {
2017 struct efx_nic *efx = netdev_priv(net_dev);
2018 int rc;
2019
2020 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
2021 raw_smp_processor_id());
2022
2023 rc = efx_check_disabled(efx);
2024 if (rc)
2025 return rc;
2026 if (efx->phy_mode & PHY_MODE_SPECIAL)
2027 return -EBUSY;
2028 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
2029 return -EIO;
2030
2031 /* Notify the kernel of the link state polled during driver load,
2032 * before the monitor starts running */
2033 efx_link_status_changed(efx);
2034
2035 efx_start_all(efx);
2036 efx_selftest_async_start(efx);
2037 return 0;
2038 }
2039
2040 /* Context: process, rtnl_lock() held.
2041 * Note that the kernel will ignore our return code; this method
2042 * should really be a void.
2043 */
2044 static int efx_net_stop(struct net_device *net_dev)
2045 {
2046 struct efx_nic *efx = netdev_priv(net_dev);
2047
2048 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
2049 raw_smp_processor_id());
2050
2051 /* Stop the device and flush all the channels */
2052 efx_stop_all(efx);
2053
2054 return 0;
2055 }
2056
2057 /* Context: process, dev_base_lock or RTNL held, non-blocking. */
2058 static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
2059 struct rtnl_link_stats64 *stats)
2060 {
2061 struct efx_nic *efx = netdev_priv(net_dev);
2062
2063 spin_lock_bh(&efx->stats_lock);
2064 efx->type->update_stats(efx, NULL, stats);
2065 spin_unlock_bh(&efx->stats_lock);
2066
2067 return stats;
2068 }
2069
2070 /* Context: netif_tx_lock held, BHs disabled. */
2071 static void efx_watchdog(struct net_device *net_dev)
2072 {
2073 struct efx_nic *efx = netdev_priv(net_dev);
2074
2075 netif_err(efx, tx_err, efx->net_dev,
2076 "TX stuck with port_enabled=%d: resetting channels\n",
2077 efx->port_enabled);
2078
2079 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
2080 }
2081
2082
2083 /* Context: process, rtnl_lock() held. */
2084 static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
2085 {
2086 struct efx_nic *efx = netdev_priv(net_dev);
2087 int rc;
2088
2089 rc = efx_check_disabled(efx);
2090 if (rc)
2091 return rc;
2092 if (new_mtu > EFX_MAX_MTU)
2093 return -EINVAL;
2094
2095 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
2096
2097 efx_device_detach_sync(efx);
2098 efx_stop_all(efx);
2099
2100 mutex_lock(&efx->mac_lock);
2101 net_dev->mtu = new_mtu;
2102 efx->type->reconfigure_mac(efx);
2103 mutex_unlock(&efx->mac_lock);
2104
2105 efx_start_all(efx);
2106 netif_device_attach(efx->net_dev);
2107 return 0;
2108 }
2109
2110 static int efx_set_mac_address(struct net_device *net_dev, void *data)
2111 {
2112 struct efx_nic *efx = netdev_priv(net_dev);
2113 struct sockaddr *addr = data;
2114 u8 *new_addr = addr->sa_data;
2115
2116 if (!is_valid_ether_addr(new_addr)) {
2117 netif_err(efx, drv, efx->net_dev,
2118 "invalid ethernet MAC address requested: %pM\n",
2119 new_addr);
2120 return -EADDRNOTAVAIL;
2121 }
2122
2123 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
2124 efx_sriov_mac_address_changed(efx);
2125
2126 /* Reconfigure the MAC */
2127 mutex_lock(&efx->mac_lock);
2128 efx->type->reconfigure_mac(efx);
2129 mutex_unlock(&efx->mac_lock);
2130
2131 return 0;
2132 }
2133
2134 /* Context: netif_addr_lock held, BHs disabled. */
2135 static void efx_set_rx_mode(struct net_device *net_dev)
2136 {
2137 struct efx_nic *efx = netdev_priv(net_dev);
2138
2139 if (efx->port_enabled)
2140 queue_work(efx->workqueue, &efx->mac_work);
2141 /* Otherwise efx_start_port() will do this */
2142 }
2143
2144 static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
2145 {
2146 struct efx_nic *efx = netdev_priv(net_dev);
2147
2148 /* If disabling RX n-tuple filtering, clear existing filters */
2149 if (net_dev->features & ~data & NETIF_F_NTUPLE)
2150 return efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2151
2152 return 0;
2153 }
2154
2155 static const struct net_device_ops efx_farch_netdev_ops = {
2156 .ndo_open = efx_net_open,
2157 .ndo_stop = efx_net_stop,
2158 .ndo_get_stats64 = efx_net_stats,
2159 .ndo_tx_timeout = efx_watchdog,
2160 .ndo_start_xmit = efx_hard_start_xmit,
2161 .ndo_validate_addr = eth_validate_addr,
2162 .ndo_do_ioctl = efx_ioctl,
2163 .ndo_change_mtu = efx_change_mtu,
2164 .ndo_set_mac_address = efx_set_mac_address,
2165 .ndo_set_rx_mode = efx_set_rx_mode,
2166 .ndo_set_features = efx_set_features,
2167 #ifdef CONFIG_SFC_SRIOV
2168 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2169 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2170 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2171 .ndo_get_vf_config = efx_sriov_get_vf_config,
2172 #endif
2173 #ifdef CONFIG_NET_POLL_CONTROLLER
2174 .ndo_poll_controller = efx_netpoll,
2175 #endif
2176 .ndo_setup_tc = efx_setup_tc,
2177 #ifdef CONFIG_RFS_ACCEL
2178 .ndo_rx_flow_steer = efx_filter_rfs,
2179 #endif
2180 };
2181
2182 static const struct net_device_ops efx_ef10_netdev_ops = {
2183 .ndo_open = efx_net_open,
2184 .ndo_stop = efx_net_stop,
2185 .ndo_get_stats64 = efx_net_stats,
2186 .ndo_tx_timeout = efx_watchdog,
2187 .ndo_start_xmit = efx_hard_start_xmit,
2188 .ndo_validate_addr = eth_validate_addr,
2189 .ndo_do_ioctl = efx_ioctl,
2190 .ndo_change_mtu = efx_change_mtu,
2191 .ndo_set_mac_address = efx_set_mac_address,
2192 .ndo_set_rx_mode = efx_set_rx_mode,
2193 .ndo_set_features = efx_set_features,
2194 #ifdef CONFIG_NET_POLL_CONTROLLER
2195 .ndo_poll_controller = efx_netpoll,
2196 #endif
2197 #ifdef CONFIG_RFS_ACCEL
2198 .ndo_rx_flow_steer = efx_filter_rfs,
2199 #endif
2200 };
2201
2202 static void efx_update_name(struct efx_nic *efx)
2203 {
2204 strcpy(efx->name, efx->net_dev->name);
2205 efx_mtd_rename(efx);
2206 efx_set_channel_names(efx);
2207 }
2208
2209 static int efx_netdev_event(struct notifier_block *this,
2210 unsigned long event, void *ptr)
2211 {
2212 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
2213
2214 if ((net_dev->netdev_ops == &efx_farch_netdev_ops ||
2215 net_dev->netdev_ops == &efx_ef10_netdev_ops) &&
2216 event == NETDEV_CHANGENAME)
2217 efx_update_name(netdev_priv(net_dev));
2218
2219 return NOTIFY_DONE;
2220 }
2221
2222 static struct notifier_block efx_netdev_notifier = {
2223 .notifier_call = efx_netdev_event,
2224 };
2225
2226 static ssize_t
2227 show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2228 {
2229 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2230 return sprintf(buf, "%d\n", efx->phy_type);
2231 }
2232 static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
2233
2234 static int efx_register_netdev(struct efx_nic *efx)
2235 {
2236 struct net_device *net_dev = efx->net_dev;
2237 struct efx_channel *channel;
2238 int rc;
2239
2240 net_dev->watchdog_timeo = 5 * HZ;
2241 net_dev->irq = efx->pci_dev->irq;
2242 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) {
2243 net_dev->netdev_ops = &efx_ef10_netdev_ops;
2244 net_dev->priv_flags |= IFF_UNICAST_FLT;
2245 } else {
2246 net_dev->netdev_ops = &efx_farch_netdev_ops;
2247 }
2248 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
2249 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
2250
2251 rtnl_lock();
2252
2253 /* Enable resets to be scheduled and check whether any were
2254 * already requested. If so, the NIC is probably hosed so we
2255 * abort.
2256 */
2257 efx->state = STATE_READY;
2258 smp_mb(); /* ensure we change state before checking reset_pending */
2259 if (efx->reset_pending) {
2260 netif_err(efx, probe, efx->net_dev,
2261 "aborting probe due to scheduled reset\n");
2262 rc = -EIO;
2263 goto fail_locked;
2264 }
2265
2266 rc = dev_alloc_name(net_dev, net_dev->name);
2267 if (rc < 0)
2268 goto fail_locked;
2269 efx_update_name(efx);
2270
2271 /* Always start with carrier off; PHY events will detect the link */
2272 netif_carrier_off(net_dev);
2273
2274 rc = register_netdevice(net_dev);
2275 if (rc)
2276 goto fail_locked;
2277
2278 efx_for_each_channel(channel, efx) {
2279 struct efx_tx_queue *tx_queue;
2280 efx_for_each_channel_tx_queue(tx_queue, channel)
2281 efx_init_tx_queue_core_txq(tx_queue);
2282 }
2283
2284 efx_associate(efx);
2285
2286 rtnl_unlock();
2287
2288 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2289 if (rc) {
2290 netif_err(efx, drv, efx->net_dev,
2291 "failed to init net dev attributes\n");
2292 goto fail_registered;
2293 }
2294
2295 return 0;
2296
2297 fail_registered:
2298 rtnl_lock();
2299 efx_dissociate(efx);
2300 unregister_netdevice(net_dev);
2301 fail_locked:
2302 efx->state = STATE_UNINIT;
2303 rtnl_unlock();
2304 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
2305 return rc;
2306 }
2307
2308 static void efx_unregister_netdev(struct efx_nic *efx)
2309 {
2310 if (!efx->net_dev)
2311 return;
2312
2313 BUG_ON(netdev_priv(efx->net_dev) != efx);
2314
2315 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2316 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2317
2318 rtnl_lock();
2319 unregister_netdevice(efx->net_dev);
2320 efx->state = STATE_UNINIT;
2321 rtnl_unlock();
2322 }
2323
2324 /**************************************************************************
2325 *
2326 * Device reset and suspend
2327 *
2328 **************************************************************************/
2329
2330 /* Tears down the entire software state and most of the hardware state
2331 * before reset. */
2332 void efx_reset_down(struct efx_nic *efx, enum reset_type method)
2333 {
2334 EFX_ASSERT_RESET_SERIALISED(efx);
2335
2336 efx_stop_all(efx);
2337 efx_disable_interrupts(efx);
2338
2339 mutex_lock(&efx->mac_lock);
2340 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2341 efx->phy_op->fini(efx);
2342 efx->type->fini(efx);
2343 }
2344
2345 /* This function will always ensure that the locks acquired in
2346 * efx_reset_down() are released. A failure return code indicates
2347 * that we were unable to reinitialise the hardware, and the
2348 * driver should be disabled. If ok is false, then the rx and tx
2349 * engines are not restarted, pending a RESET_DISABLE. */
2350 int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
2351 {
2352 int rc;
2353
2354 EFX_ASSERT_RESET_SERIALISED(efx);
2355
2356 rc = efx->type->init(efx);
2357 if (rc) {
2358 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
2359 goto fail;
2360 }
2361
2362 if (!ok)
2363 goto fail;
2364
2365 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
2366 rc = efx->phy_op->init(efx);
2367 if (rc)
2368 goto fail;
2369 if (efx->phy_op->reconfigure(efx))
2370 netif_err(efx, drv, efx->net_dev,
2371 "could not restore PHY settings\n");
2372 }
2373
2374 rc = efx_enable_interrupts(efx);
2375 if (rc)
2376 goto fail;
2377 efx_restore_filters(efx);
2378 efx_sriov_reset(efx);
2379
2380 mutex_unlock(&efx->mac_lock);
2381
2382 efx_start_all(efx);
2383
2384 return 0;
2385
2386 fail:
2387 efx->port_initialized = false;
2388
2389 mutex_unlock(&efx->mac_lock);
2390
2391 return rc;
2392 }
2393
2394 /* Reset the NIC using the specified method. Note that the reset may
2395 * fail, in which case the card will be left in an unusable state.
2396 *
2397 * Caller must hold the rtnl_lock.
2398 */
2399 int efx_reset(struct efx_nic *efx, enum reset_type method)
2400 {
2401 int rc, rc2;
2402 bool disabled;
2403
2404 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2405 RESET_TYPE(method));
2406
2407 efx_device_detach_sync(efx);
2408 efx_reset_down(efx, method);
2409
2410 rc = efx->type->reset(efx, method);
2411 if (rc) {
2412 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
2413 goto out;
2414 }
2415
2416 /* Clear flags for the scopes we covered. We assume the NIC and
2417 * driver are now quiescent so that there is no race here.
2418 */
2419 efx->reset_pending &= -(1 << (method + 1));
2420
2421 /* Reinitialise bus-mastering, which may have been turned off before
2422 * the reset was scheduled. This is still appropriate, even in the
2423 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2424 * can respond to requests. */
2425 pci_set_master(efx->pci_dev);
2426
2427 out:
2428 /* Leave device stopped if necessary */
2429 disabled = rc ||
2430 method == RESET_TYPE_DISABLE ||
2431 method == RESET_TYPE_RECOVER_OR_DISABLE;
2432 rc2 = efx_reset_up(efx, method, !disabled);
2433 if (rc2) {
2434 disabled = true;
2435 if (!rc)
2436 rc = rc2;
2437 }
2438
2439 if (disabled) {
2440 dev_close(efx->net_dev);
2441 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
2442 efx->state = STATE_DISABLED;
2443 } else {
2444 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
2445 netif_device_attach(efx->net_dev);
2446 }
2447 return rc;
2448 }
2449
2450 /* Try recovery mechanisms.
2451 * For now only EEH is supported.
2452 * Returns 0 if the recovery mechanisms are unsuccessful.
2453 * Returns a non-zero value otherwise.
2454 */
2455 int efx_try_recovery(struct efx_nic *efx)
2456 {
2457 #ifdef CONFIG_EEH
2458 /* A PCI error can occur and not be seen by EEH because nothing
2459 * happens on the PCI bus. In this case the driver may fail and
2460 * schedule a 'recover or reset', leading to this recovery handler.
2461 * Manually call the eeh failure check function.
2462 */
2463 struct eeh_dev *eehdev =
2464 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
2465
2466 if (eeh_dev_check_failure(eehdev)) {
2467 /* The EEH mechanisms will handle the error and reset the
2468 * device if necessary.
2469 */
2470 return 1;
2471 }
2472 #endif
2473 return 0;
2474 }
2475
2476 static void efx_wait_for_bist_end(struct efx_nic *efx)
2477 {
2478 int i;
2479
2480 for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) {
2481 if (efx_mcdi_poll_reboot(efx))
2482 goto out;
2483 msleep(BIST_WAIT_DELAY_MS);
2484 }
2485
2486 netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n");
2487 out:
2488 /* Either way unset the BIST flag. If we found no reboot we probably
2489 * won't recover, but we should try.
2490 */
2491 efx->mc_bist_for_other_fn = false;
2492 }
2493
2494 /* The worker thread exists so that code that cannot sleep can
2495 * schedule a reset for later.
2496 */
2497 static void efx_reset_work(struct work_struct *data)
2498 {
2499 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
2500 unsigned long pending;
2501 enum reset_type method;
2502
2503 pending = ACCESS_ONCE(efx->reset_pending);
2504 method = fls(pending) - 1;
2505
2506 if (method == RESET_TYPE_MC_BIST)
2507 efx_wait_for_bist_end(efx);
2508
2509 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2510 method == RESET_TYPE_RECOVER_OR_ALL) &&
2511 efx_try_recovery(efx))
2512 return;
2513
2514 if (!pending)
2515 return;
2516
2517 rtnl_lock();
2518
2519 /* We checked the state in efx_schedule_reset() but it may
2520 * have changed by now. Now that we have the RTNL lock,
2521 * it cannot change again.
2522 */
2523 if (efx->state == STATE_READY)
2524 (void)efx_reset(efx, method);
2525
2526 rtnl_unlock();
2527 }
2528
2529 void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2530 {
2531 enum reset_type method;
2532
2533 if (efx->state == STATE_RECOVERY) {
2534 netif_dbg(efx, drv, efx->net_dev,
2535 "recovering: skip scheduling %s reset\n",
2536 RESET_TYPE(type));
2537 return;
2538 }
2539
2540 switch (type) {
2541 case RESET_TYPE_INVISIBLE:
2542 case RESET_TYPE_ALL:
2543 case RESET_TYPE_RECOVER_OR_ALL:
2544 case RESET_TYPE_WORLD:
2545 case RESET_TYPE_DISABLE:
2546 case RESET_TYPE_RECOVER_OR_DISABLE:
2547 case RESET_TYPE_MC_BIST:
2548 method = type;
2549 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2550 RESET_TYPE(method));
2551 break;
2552 default:
2553 method = efx->type->map_reset_reason(type);
2554 netif_dbg(efx, drv, efx->net_dev,
2555 "scheduling %s reset for %s\n",
2556 RESET_TYPE(method), RESET_TYPE(type));
2557 break;
2558 }
2559
2560 set_bit(method, &efx->reset_pending);
2561 smp_mb(); /* ensure we change reset_pending before checking state */
2562
2563 /* If we're not READY then just leave the flags set as the cue
2564 * to abort probing or reschedule the reset later.
2565 */
2566 if (ACCESS_ONCE(efx->state) != STATE_READY)
2567 return;
2568
2569 /* efx_process_channel() will no longer read events once a
2570 * reset is scheduled. So switch back to poll'd MCDI completions. */
2571 efx_mcdi_mode_poll(efx);
2572
2573 queue_work(reset_workqueue, &efx->reset_work);
2574 }
2575
2576 /**************************************************************************
2577 *
2578 * List of NICs we support
2579 *
2580 **************************************************************************/
2581
2582 /* PCI device ID table */
2583 static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
2584 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2585 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
2586 .driver_data = (unsigned long) &falcon_a1_nic_type},
2587 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2588 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
2589 .driver_data = (unsigned long) &falcon_b0_nic_type},
2590 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
2591 .driver_data = (unsigned long) &siena_a0_nic_type},
2592 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
2593 .driver_data = (unsigned long) &siena_a0_nic_type},
2594 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */
2595 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
2596 {0} /* end of list */
2597 };
2598
2599 /**************************************************************************
2600 *
2601 * Dummy PHY/MAC operations
2602 *
2603 * Can be used for some unimplemented operations
2604 * Needed so all function pointers are valid and do not have to be tested
2605 * before use
2606 *
2607 **************************************************************************/
2608 int efx_port_dummy_op_int(struct efx_nic *efx)
2609 {
2610 return 0;
2611 }
2612 void efx_port_dummy_op_void(struct efx_nic *efx) {}
2613
2614 static bool efx_port_dummy_op_poll(struct efx_nic *efx)
2615 {
2616 return false;
2617 }
2618
2619 static const struct efx_phy_operations efx_dummy_phy_operations = {
2620 .init = efx_port_dummy_op_int,
2621 .reconfigure = efx_port_dummy_op_int,
2622 .poll = efx_port_dummy_op_poll,
2623 .fini = efx_port_dummy_op_void,
2624 };
2625
2626 /**************************************************************************
2627 *
2628 * Data housekeeping
2629 *
2630 **************************************************************************/
2631
2632 /* This zeroes out and then fills in the invariants in a struct
2633 * efx_nic (including all sub-structures).
2634 */
2635 static int efx_init_struct(struct efx_nic *efx,
2636 struct pci_dev *pci_dev, struct net_device *net_dev)
2637 {
2638 int i;
2639
2640 /* Initialise common structures */
2641 INIT_LIST_HEAD(&efx->node);
2642 INIT_LIST_HEAD(&efx->secondary_list);
2643 spin_lock_init(&efx->biu_lock);
2644 #ifdef CONFIG_SFC_MTD
2645 INIT_LIST_HEAD(&efx->mtd_list);
2646 #endif
2647 INIT_WORK(&efx->reset_work, efx_reset_work);
2648 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
2649 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
2650 efx->pci_dev = pci_dev;
2651 efx->msg_enable = debug;
2652 efx->state = STATE_UNINIT;
2653 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
2654
2655 efx->net_dev = net_dev;
2656 efx->rx_prefix_size = efx->type->rx_prefix_size;
2657 efx->rx_ip_align =
2658 NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0;
2659 efx->rx_packet_hash_offset =
2660 efx->type->rx_hash_offset - efx->type->rx_prefix_size;
2661 efx->rx_packet_ts_offset =
2662 efx->type->rx_ts_offset - efx->type->rx_prefix_size;
2663 spin_lock_init(&efx->stats_lock);
2664 mutex_init(&efx->mac_lock);
2665 efx->phy_op = &efx_dummy_phy_operations;
2666 efx->mdio.dev = net_dev;
2667 INIT_WORK(&efx->mac_work, efx_mac_work);
2668 init_waitqueue_head(&efx->flush_wq);
2669
2670 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
2671 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2672 if (!efx->channel[i])
2673 goto fail;
2674 efx->msi_context[i].efx = efx;
2675 efx->msi_context[i].index = i;
2676 }
2677
2678 /* Higher numbered interrupt modes are less capable! */
2679 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2680 interrupt_mode);
2681
2682 /* Would be good to use the net_dev name, but we're too early */
2683 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2684 pci_name(pci_dev));
2685 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
2686 if (!efx->workqueue)
2687 goto fail;
2688
2689 return 0;
2690
2691 fail:
2692 efx_fini_struct(efx);
2693 return -ENOMEM;
2694 }
2695
2696 static void efx_fini_struct(struct efx_nic *efx)
2697 {
2698 int i;
2699
2700 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2701 kfree(efx->channel[i]);
2702
2703 kfree(efx->vpd_sn);
2704
2705 if (efx->workqueue) {
2706 destroy_workqueue(efx->workqueue);
2707 efx->workqueue = NULL;
2708 }
2709 }
2710
2711 /**************************************************************************
2712 *
2713 * PCI interface
2714 *
2715 **************************************************************************/
2716
2717 /* Main body of final NIC shutdown code
2718 * This is called only at module unload (or hotplug removal).
2719 */
2720 static void efx_pci_remove_main(struct efx_nic *efx)
2721 {
2722 /* Flush reset_work. It can no longer be scheduled since we
2723 * are not READY.
2724 */
2725 BUG_ON(efx->state == STATE_READY);
2726 cancel_work_sync(&efx->reset_work);
2727
2728 efx_disable_interrupts(efx);
2729 efx_nic_fini_interrupt(efx);
2730 efx_fini_port(efx);
2731 efx->type->fini(efx);
2732 efx_fini_napi(efx);
2733 efx_remove_all(efx);
2734 }
2735
2736 /* Final NIC shutdown
2737 * This is called only at module unload (or hotplug removal).
2738 */
2739 static void efx_pci_remove(struct pci_dev *pci_dev)
2740 {
2741 struct efx_nic *efx;
2742
2743 efx = pci_get_drvdata(pci_dev);
2744 if (!efx)
2745 return;
2746
2747 /* Mark the NIC as fini, then stop the interface */
2748 rtnl_lock();
2749 efx_dissociate(efx);
2750 dev_close(efx->net_dev);
2751 efx_disable_interrupts(efx);
2752 rtnl_unlock();
2753
2754 efx_sriov_fini(efx);
2755 efx_unregister_netdev(efx);
2756
2757 efx_mtd_remove(efx);
2758
2759 efx_pci_remove_main(efx);
2760
2761 efx_fini_io(efx);
2762 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
2763
2764 efx_fini_struct(efx);
2765 free_netdev(efx->net_dev);
2766
2767 pci_disable_pcie_error_reporting(pci_dev);
2768 };
2769
2770 /* NIC VPD information
2771 * Called during probe to display the part number of the
2772 * installed NIC. VPD is potentially very large but this should
2773 * always appear within the first 512 bytes.
2774 */
2775 #define SFC_VPD_LEN 512
2776 static void efx_probe_vpd_strings(struct efx_nic *efx)
2777 {
2778 struct pci_dev *dev = efx->pci_dev;
2779 char vpd_data[SFC_VPD_LEN];
2780 ssize_t vpd_size;
2781 int ro_start, ro_size, i, j;
2782
2783 /* Get the vpd data from the device */
2784 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
2785 if (vpd_size <= 0) {
2786 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
2787 return;
2788 }
2789
2790 /* Get the Read only section */
2791 ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
2792 if (ro_start < 0) {
2793 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
2794 return;
2795 }
2796
2797 ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]);
2798 j = ro_size;
2799 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
2800 if (i + j > vpd_size)
2801 j = vpd_size - i;
2802
2803 /* Get the Part number */
2804 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
2805 if (i < 0) {
2806 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
2807 return;
2808 }
2809
2810 j = pci_vpd_info_field_size(&vpd_data[i]);
2811 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2812 if (i + j > vpd_size) {
2813 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
2814 return;
2815 }
2816
2817 netif_info(efx, drv, efx->net_dev,
2818 "Part Number : %.*s\n", j, &vpd_data[i]);
2819
2820 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
2821 j = ro_size;
2822 i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN");
2823 if (i < 0) {
2824 netif_err(efx, drv, efx->net_dev, "Serial number not found\n");
2825 return;
2826 }
2827
2828 j = pci_vpd_info_field_size(&vpd_data[i]);
2829 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2830 if (i + j > vpd_size) {
2831 netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n");
2832 return;
2833 }
2834
2835 efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL);
2836 if (!efx->vpd_sn)
2837 return;
2838
2839 snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]);
2840 }
2841
2842
2843 /* Main body of NIC initialisation
2844 * This is called at module load (or hotplug insertion, theoretically).
2845 */
2846 static int efx_pci_probe_main(struct efx_nic *efx)
2847 {
2848 int rc;
2849
2850 /* Do start-of-day initialisation */
2851 rc = efx_probe_all(efx);
2852 if (rc)
2853 goto fail1;
2854
2855 efx_init_napi(efx);
2856
2857 rc = efx->type->init(efx);
2858 if (rc) {
2859 netif_err(efx, probe, efx->net_dev,
2860 "failed to initialise NIC\n");
2861 goto fail3;
2862 }
2863
2864 rc = efx_init_port(efx);
2865 if (rc) {
2866 netif_err(efx, probe, efx->net_dev,
2867 "failed to initialise port\n");
2868 goto fail4;
2869 }
2870
2871 rc = efx_nic_init_interrupt(efx);
2872 if (rc)
2873 goto fail5;
2874 rc = efx_enable_interrupts(efx);
2875 if (rc)
2876 goto fail6;
2877
2878 return 0;
2879
2880 fail6:
2881 efx_nic_fini_interrupt(efx);
2882 fail5:
2883 efx_fini_port(efx);
2884 fail4:
2885 efx->type->fini(efx);
2886 fail3:
2887 efx_fini_napi(efx);
2888 efx_remove_all(efx);
2889 fail1:
2890 return rc;
2891 }
2892
2893 /* NIC initialisation
2894 *
2895 * This is called at module load (or hotplug insertion,
2896 * theoretically). It sets up PCI mappings, resets the NIC,
2897 * sets up and registers the network devices with the kernel and hooks
2898 * the interrupt service routine. It does not prepare the device for
2899 * transmission; this is left to the first time one of the network
2900 * interfaces is brought up (i.e. efx_net_open).
2901 */
2902 static int efx_pci_probe(struct pci_dev *pci_dev,
2903 const struct pci_device_id *entry)
2904 {
2905 struct net_device *net_dev;
2906 struct efx_nic *efx;
2907 int rc;
2908
2909 /* Allocate and initialise a struct net_device and struct efx_nic */
2910 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2911 EFX_MAX_RX_QUEUES);
2912 if (!net_dev)
2913 return -ENOMEM;
2914 efx = netdev_priv(net_dev);
2915 efx->type = (const struct efx_nic_type *) entry->driver_data;
2916 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
2917 NETIF_F_HIGHDMA | NETIF_F_TSO |
2918 NETIF_F_RXCSUM);
2919 if (efx->type->offload_features & NETIF_F_V6_CSUM)
2920 net_dev->features |= NETIF_F_TSO6;
2921 /* Mask for features that also apply to VLAN devices */
2922 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
2923 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2924 NETIF_F_RXCSUM);
2925 /* All offloads can be toggled */
2926 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
2927 pci_set_drvdata(pci_dev, efx);
2928 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
2929 rc = efx_init_struct(efx, pci_dev, net_dev);
2930 if (rc)
2931 goto fail1;
2932
2933 netif_info(efx, probe, efx->net_dev,
2934 "Solarflare NIC detected\n");
2935
2936 efx_probe_vpd_strings(efx);
2937
2938 /* Set up basic I/O (BAR mappings etc) */
2939 rc = efx_init_io(efx);
2940 if (rc)
2941 goto fail2;
2942
2943 rc = efx_pci_probe_main(efx);
2944 if (rc)
2945 goto fail3;
2946
2947 rc = efx_register_netdev(efx);
2948 if (rc)
2949 goto fail4;
2950
2951 rc = efx_sriov_init(efx);
2952 if (rc)
2953 netif_err(efx, probe, efx->net_dev,
2954 "SR-IOV can't be enabled rc %d\n", rc);
2955
2956 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
2957
2958 /* Try to create MTDs, but allow this to fail */
2959 rtnl_lock();
2960 rc = efx_mtd_probe(efx);
2961 rtnl_unlock();
2962 if (rc)
2963 netif_warn(efx, probe, efx->net_dev,
2964 "failed to create MTDs (%d)\n", rc);
2965
2966 rc = pci_enable_pcie_error_reporting(pci_dev);
2967 if (rc && rc != -EINVAL)
2968 netif_warn(efx, probe, efx->net_dev,
2969 "pci_enable_pcie_error_reporting failed (%d)\n", rc);
2970
2971 return 0;
2972
2973 fail4:
2974 efx_pci_remove_main(efx);
2975 fail3:
2976 efx_fini_io(efx);
2977 fail2:
2978 efx_fini_struct(efx);
2979 fail1:
2980 WARN_ON(rc > 0);
2981 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
2982 free_netdev(net_dev);
2983 return rc;
2984 }
2985
2986 static int efx_pm_freeze(struct device *dev)
2987 {
2988 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2989
2990 rtnl_lock();
2991
2992 if (efx->state != STATE_DISABLED) {
2993 efx->state = STATE_UNINIT;
2994
2995 efx_device_detach_sync(efx);
2996
2997 efx_stop_all(efx);
2998 efx_disable_interrupts(efx);
2999 }
3000
3001 rtnl_unlock();
3002
3003 return 0;
3004 }
3005
3006 static int efx_pm_thaw(struct device *dev)
3007 {
3008 int rc;
3009 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
3010
3011 rtnl_lock();
3012
3013 if (efx->state != STATE_DISABLED) {
3014 rc = efx_enable_interrupts(efx);
3015 if (rc)
3016 goto fail;
3017
3018 mutex_lock(&efx->mac_lock);
3019 efx->phy_op->reconfigure(efx);
3020 mutex_unlock(&efx->mac_lock);
3021
3022 efx_start_all(efx);
3023
3024 netif_device_attach(efx->net_dev);
3025
3026 efx->state = STATE_READY;
3027
3028 efx->type->resume_wol(efx);
3029 }
3030
3031 rtnl_unlock();
3032
3033 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
3034 queue_work(reset_workqueue, &efx->reset_work);
3035
3036 return 0;
3037
3038 fail:
3039 rtnl_unlock();
3040
3041 return rc;
3042 }
3043
3044 static int efx_pm_poweroff(struct device *dev)
3045 {
3046 struct pci_dev *pci_dev = to_pci_dev(dev);
3047 struct efx_nic *efx = pci_get_drvdata(pci_dev);
3048
3049 efx->type->fini(efx);
3050
3051 efx->reset_pending = 0;
3052
3053 pci_save_state(pci_dev);
3054 return pci_set_power_state(pci_dev, PCI_D3hot);
3055 }
3056
3057 /* Used for both resume and restore */
3058 static int efx_pm_resume(struct device *dev)
3059 {
3060 struct pci_dev *pci_dev = to_pci_dev(dev);
3061 struct efx_nic *efx = pci_get_drvdata(pci_dev);
3062 int rc;
3063
3064 rc = pci_set_power_state(pci_dev, PCI_D0);
3065 if (rc)
3066 return rc;
3067 pci_restore_state(pci_dev);
3068 rc = pci_enable_device(pci_dev);
3069 if (rc)
3070 return rc;
3071 pci_set_master(efx->pci_dev);
3072 rc = efx->type->reset(efx, RESET_TYPE_ALL);
3073 if (rc)
3074 return rc;
3075 rc = efx->type->init(efx);
3076 if (rc)
3077 return rc;
3078 rc = efx_pm_thaw(dev);
3079 return rc;
3080 }
3081
3082 static int efx_pm_suspend(struct device *dev)
3083 {
3084 int rc;
3085
3086 efx_pm_freeze(dev);
3087 rc = efx_pm_poweroff(dev);
3088 if (rc)
3089 efx_pm_resume(dev);
3090 return rc;
3091 }
3092
3093 static const struct dev_pm_ops efx_pm_ops = {
3094 .suspend = efx_pm_suspend,
3095 .resume = efx_pm_resume,
3096 .freeze = efx_pm_freeze,
3097 .thaw = efx_pm_thaw,
3098 .poweroff = efx_pm_poweroff,
3099 .restore = efx_pm_resume,
3100 };
3101
3102 /* A PCI error affecting this device was detected.
3103 * At this point MMIO and DMA may be disabled.
3104 * Stop the software path and request a slot reset.
3105 */
3106 static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
3107 enum pci_channel_state state)
3108 {
3109 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3110 struct efx_nic *efx = pci_get_drvdata(pdev);
3111
3112 if (state == pci_channel_io_perm_failure)
3113 return PCI_ERS_RESULT_DISCONNECT;
3114
3115 rtnl_lock();
3116
3117 if (efx->state != STATE_DISABLED) {
3118 efx->state = STATE_RECOVERY;
3119 efx->reset_pending = 0;
3120
3121 efx_device_detach_sync(efx);
3122
3123 efx_stop_all(efx);
3124 efx_disable_interrupts(efx);
3125
3126 status = PCI_ERS_RESULT_NEED_RESET;
3127 } else {
3128 /* If the interface is disabled we don't want to do anything
3129 * with it.
3130 */
3131 status = PCI_ERS_RESULT_RECOVERED;
3132 }
3133
3134 rtnl_unlock();
3135
3136 pci_disable_device(pdev);
3137
3138 return status;
3139 }
3140
3141 /* Fake a successfull reset, which will be performed later in efx_io_resume. */
3142 static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
3143 {
3144 struct efx_nic *efx = pci_get_drvdata(pdev);
3145 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3146 int rc;
3147
3148 if (pci_enable_device(pdev)) {
3149 netif_err(efx, hw, efx->net_dev,
3150 "Cannot re-enable PCI device after reset.\n");
3151 status = PCI_ERS_RESULT_DISCONNECT;
3152 }
3153
3154 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
3155 if (rc) {
3156 netif_err(efx, hw, efx->net_dev,
3157 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
3158 /* Non-fatal error. Continue. */
3159 }
3160
3161 return status;
3162 }
3163
3164 /* Perform the actual reset and resume I/O operations. */
3165 static void efx_io_resume(struct pci_dev *pdev)
3166 {
3167 struct efx_nic *efx = pci_get_drvdata(pdev);
3168 int rc;
3169
3170 rtnl_lock();
3171
3172 if (efx->state == STATE_DISABLED)
3173 goto out;
3174
3175 rc = efx_reset(efx, RESET_TYPE_ALL);
3176 if (rc) {
3177 netif_err(efx, hw, efx->net_dev,
3178 "efx_reset failed after PCI error (%d)\n", rc);
3179 } else {
3180 efx->state = STATE_READY;
3181 netif_dbg(efx, hw, efx->net_dev,
3182 "Done resetting and resuming IO after PCI error.\n");
3183 }
3184
3185 out:
3186 rtnl_unlock();
3187 }
3188
3189 /* For simplicity and reliability, we always require a slot reset and try to
3190 * reset the hardware when a pci error affecting the device is detected.
3191 * We leave both the link_reset and mmio_enabled callback unimplemented:
3192 * with our request for slot reset the mmio_enabled callback will never be
3193 * called, and the link_reset callback is not used by AER or EEH mechanisms.
3194 */
3195 static struct pci_error_handlers efx_err_handlers = {
3196 .error_detected = efx_io_error_detected,
3197 .slot_reset = efx_io_slot_reset,
3198 .resume = efx_io_resume,
3199 };
3200
3201 static struct pci_driver efx_pci_driver = {
3202 .name = KBUILD_MODNAME,
3203 .id_table = efx_pci_table,
3204 .probe = efx_pci_probe,
3205 .remove = efx_pci_remove,
3206 .driver.pm = &efx_pm_ops,
3207 .err_handler = &efx_err_handlers,
3208 };
3209
3210 /**************************************************************************
3211 *
3212 * Kernel module interface
3213 *
3214 *************************************************************************/
3215
3216 module_param(interrupt_mode, uint, 0444);
3217 MODULE_PARM_DESC(interrupt_mode,
3218 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
3219
3220 static int __init efx_init_module(void)
3221 {
3222 int rc;
3223
3224 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
3225
3226 rc = register_netdevice_notifier(&efx_netdev_notifier);
3227 if (rc)
3228 goto err_notifier;
3229
3230 rc = efx_init_sriov();
3231 if (rc)
3232 goto err_sriov;
3233
3234 reset_workqueue = create_singlethread_workqueue("sfc_reset");
3235 if (!reset_workqueue) {
3236 rc = -ENOMEM;
3237 goto err_reset;
3238 }
3239
3240 rc = pci_register_driver(&efx_pci_driver);
3241 if (rc < 0)
3242 goto err_pci;
3243
3244 return 0;
3245
3246 err_pci:
3247 destroy_workqueue(reset_workqueue);
3248 err_reset:
3249 efx_fini_sriov();
3250 err_sriov:
3251 unregister_netdevice_notifier(&efx_netdev_notifier);
3252 err_notifier:
3253 return rc;
3254 }
3255
3256 static void __exit efx_exit_module(void)
3257 {
3258 printk(KERN_INFO "Solarflare NET driver unloading\n");
3259
3260 pci_unregister_driver(&efx_pci_driver);
3261 destroy_workqueue(reset_workqueue);
3262 efx_fini_sriov();
3263 unregister_netdevice_notifier(&efx_netdev_notifier);
3264
3265 }
3266
3267 module_init(efx_init_module);
3268 module_exit(efx_exit_module);
3269
3270 MODULE_AUTHOR("Solarflare Communications and "
3271 "Michael Brown <mbrown@fensystems.co.uk>");
3272 MODULE_DESCRIPTION("Solarflare network driver");
3273 MODULE_LICENSE("GPL");
3274 MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux kernel - Deliverables
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