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sfc: Prepare for RX scatter on EF10
[deliverable/linux.git] / drivers / net / ethernet / sfc / falcon.c
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include <linux/slab.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "nic.h"
23 #include "farch_regs.h"
24 #include "io.h"
25 #include "phy.h"
26 #include "workarounds.h"
27 #include "selftest.h"
28 #include "mdio_10g.h"
29
30 /* Hardware control for SFC4000 (aka Falcon). */
31
32 /**************************************************************************
33 *
34 * NIC stats
35 *
36 **************************************************************************
37 */
38
39 #define FALCON_MAC_STATS_SIZE 0x100
40
41 #define XgRxOctets_offset 0x0
42 #define XgRxOctets_WIDTH 48
43 #define XgRxOctetsOK_offset 0x8
44 #define XgRxOctetsOK_WIDTH 48
45 #define XgRxPkts_offset 0x10
46 #define XgRxPkts_WIDTH 32
47 #define XgRxPktsOK_offset 0x14
48 #define XgRxPktsOK_WIDTH 32
49 #define XgRxBroadcastPkts_offset 0x18
50 #define XgRxBroadcastPkts_WIDTH 32
51 #define XgRxMulticastPkts_offset 0x1C
52 #define XgRxMulticastPkts_WIDTH 32
53 #define XgRxUnicastPkts_offset 0x20
54 #define XgRxUnicastPkts_WIDTH 32
55 #define XgRxUndersizePkts_offset 0x24
56 #define XgRxUndersizePkts_WIDTH 32
57 #define XgRxOversizePkts_offset 0x28
58 #define XgRxOversizePkts_WIDTH 32
59 #define XgRxJabberPkts_offset 0x2C
60 #define XgRxJabberPkts_WIDTH 32
61 #define XgRxUndersizeFCSerrorPkts_offset 0x30
62 #define XgRxUndersizeFCSerrorPkts_WIDTH 32
63 #define XgRxDropEvents_offset 0x34
64 #define XgRxDropEvents_WIDTH 32
65 #define XgRxFCSerrorPkts_offset 0x38
66 #define XgRxFCSerrorPkts_WIDTH 32
67 #define XgRxAlignError_offset 0x3C
68 #define XgRxAlignError_WIDTH 32
69 #define XgRxSymbolError_offset 0x40
70 #define XgRxSymbolError_WIDTH 32
71 #define XgRxInternalMACError_offset 0x44
72 #define XgRxInternalMACError_WIDTH 32
73 #define XgRxControlPkts_offset 0x48
74 #define XgRxControlPkts_WIDTH 32
75 #define XgRxPausePkts_offset 0x4C
76 #define XgRxPausePkts_WIDTH 32
77 #define XgRxPkts64Octets_offset 0x50
78 #define XgRxPkts64Octets_WIDTH 32
79 #define XgRxPkts65to127Octets_offset 0x54
80 #define XgRxPkts65to127Octets_WIDTH 32
81 #define XgRxPkts128to255Octets_offset 0x58
82 #define XgRxPkts128to255Octets_WIDTH 32
83 #define XgRxPkts256to511Octets_offset 0x5C
84 #define XgRxPkts256to511Octets_WIDTH 32
85 #define XgRxPkts512to1023Octets_offset 0x60
86 #define XgRxPkts512to1023Octets_WIDTH 32
87 #define XgRxPkts1024to15xxOctets_offset 0x64
88 #define XgRxPkts1024to15xxOctets_WIDTH 32
89 #define XgRxPkts15xxtoMaxOctets_offset 0x68
90 #define XgRxPkts15xxtoMaxOctets_WIDTH 32
91 #define XgRxLengthError_offset 0x6C
92 #define XgRxLengthError_WIDTH 32
93 #define XgTxPkts_offset 0x80
94 #define XgTxPkts_WIDTH 32
95 #define XgTxOctets_offset 0x88
96 #define XgTxOctets_WIDTH 48
97 #define XgTxMulticastPkts_offset 0x90
98 #define XgTxMulticastPkts_WIDTH 32
99 #define XgTxBroadcastPkts_offset 0x94
100 #define XgTxBroadcastPkts_WIDTH 32
101 #define XgTxUnicastPkts_offset 0x98
102 #define XgTxUnicastPkts_WIDTH 32
103 #define XgTxControlPkts_offset 0x9C
104 #define XgTxControlPkts_WIDTH 32
105 #define XgTxPausePkts_offset 0xA0
106 #define XgTxPausePkts_WIDTH 32
107 #define XgTxPkts64Octets_offset 0xA4
108 #define XgTxPkts64Octets_WIDTH 32
109 #define XgTxPkts65to127Octets_offset 0xA8
110 #define XgTxPkts65to127Octets_WIDTH 32
111 #define XgTxPkts128to255Octets_offset 0xAC
112 #define XgTxPkts128to255Octets_WIDTH 32
113 #define XgTxPkts256to511Octets_offset 0xB0
114 #define XgTxPkts256to511Octets_WIDTH 32
115 #define XgTxPkts512to1023Octets_offset 0xB4
116 #define XgTxPkts512to1023Octets_WIDTH 32
117 #define XgTxPkts1024to15xxOctets_offset 0xB8
118 #define XgTxPkts1024to15xxOctets_WIDTH 32
119 #define XgTxPkts1519toMaxOctets_offset 0xBC
120 #define XgTxPkts1519toMaxOctets_WIDTH 32
121 #define XgTxUndersizePkts_offset 0xC0
122 #define XgTxUndersizePkts_WIDTH 32
123 #define XgTxOversizePkts_offset 0xC4
124 #define XgTxOversizePkts_WIDTH 32
125 #define XgTxNonTcpUdpPkt_offset 0xC8
126 #define XgTxNonTcpUdpPkt_WIDTH 16
127 #define XgTxMacSrcErrPkt_offset 0xCC
128 #define XgTxMacSrcErrPkt_WIDTH 16
129 #define XgTxIpSrcErrPkt_offset 0xD0
130 #define XgTxIpSrcErrPkt_WIDTH 16
131 #define XgDmaDone_offset 0xD4
132 #define XgDmaDone_WIDTH 32
133
134 #define FALCON_XMAC_STATS_DMA_FLAG(efx) \
135 (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset))
136
137 #define FALCON_DMA_STAT(ext_name, hw_name) \
138 [FALCON_STAT_ ## ext_name] = \
139 { #ext_name, \
140 /* 48-bit stats are zero-padded to 64 on DMA */ \
141 hw_name ## _ ## WIDTH == 48 ? 64 : hw_name ## _ ## WIDTH, \
142 hw_name ## _ ## offset }
143 #define FALCON_OTHER_STAT(ext_name) \
144 [FALCON_STAT_ ## ext_name] = { #ext_name, 0, 0 }
145
146 static const struct efx_hw_stat_desc falcon_stat_desc[FALCON_STAT_COUNT] = {
147 FALCON_DMA_STAT(tx_bytes, XgTxOctets),
148 FALCON_DMA_STAT(tx_packets, XgTxPkts),
149 FALCON_DMA_STAT(tx_pause, XgTxPausePkts),
150 FALCON_DMA_STAT(tx_control, XgTxControlPkts),
151 FALCON_DMA_STAT(tx_unicast, XgTxUnicastPkts),
152 FALCON_DMA_STAT(tx_multicast, XgTxMulticastPkts),
153 FALCON_DMA_STAT(tx_broadcast, XgTxBroadcastPkts),
154 FALCON_DMA_STAT(tx_lt64, XgTxUndersizePkts),
155 FALCON_DMA_STAT(tx_64, XgTxPkts64Octets),
156 FALCON_DMA_STAT(tx_65_to_127, XgTxPkts65to127Octets),
157 FALCON_DMA_STAT(tx_128_to_255, XgTxPkts128to255Octets),
158 FALCON_DMA_STAT(tx_256_to_511, XgTxPkts256to511Octets),
159 FALCON_DMA_STAT(tx_512_to_1023, XgTxPkts512to1023Octets),
160 FALCON_DMA_STAT(tx_1024_to_15xx, XgTxPkts1024to15xxOctets),
161 FALCON_DMA_STAT(tx_15xx_to_jumbo, XgTxPkts1519toMaxOctets),
162 FALCON_DMA_STAT(tx_gtjumbo, XgTxOversizePkts),
163 FALCON_DMA_STAT(tx_non_tcpudp, XgTxNonTcpUdpPkt),
164 FALCON_DMA_STAT(tx_mac_src_error, XgTxMacSrcErrPkt),
165 FALCON_DMA_STAT(tx_ip_src_error, XgTxIpSrcErrPkt),
166 FALCON_DMA_STAT(rx_bytes, XgRxOctets),
167 FALCON_DMA_STAT(rx_good_bytes, XgRxOctetsOK),
168 FALCON_OTHER_STAT(rx_bad_bytes),
169 FALCON_DMA_STAT(rx_packets, XgRxPkts),
170 FALCON_DMA_STAT(rx_good, XgRxPktsOK),
171 FALCON_DMA_STAT(rx_bad, XgRxFCSerrorPkts),
172 FALCON_DMA_STAT(rx_pause, XgRxPausePkts),
173 FALCON_DMA_STAT(rx_control, XgRxControlPkts),
174 FALCON_DMA_STAT(rx_unicast, XgRxUnicastPkts),
175 FALCON_DMA_STAT(rx_multicast, XgRxMulticastPkts),
176 FALCON_DMA_STAT(rx_broadcast, XgRxBroadcastPkts),
177 FALCON_DMA_STAT(rx_lt64, XgRxUndersizePkts),
178 FALCON_DMA_STAT(rx_64, XgRxPkts64Octets),
179 FALCON_DMA_STAT(rx_65_to_127, XgRxPkts65to127Octets),
180 FALCON_DMA_STAT(rx_128_to_255, XgRxPkts128to255Octets),
181 FALCON_DMA_STAT(rx_256_to_511, XgRxPkts256to511Octets),
182 FALCON_DMA_STAT(rx_512_to_1023, XgRxPkts512to1023Octets),
183 FALCON_DMA_STAT(rx_1024_to_15xx, XgRxPkts1024to15xxOctets),
184 FALCON_DMA_STAT(rx_15xx_to_jumbo, XgRxPkts15xxtoMaxOctets),
185 FALCON_DMA_STAT(rx_gtjumbo, XgRxOversizePkts),
186 FALCON_DMA_STAT(rx_bad_lt64, XgRxUndersizeFCSerrorPkts),
187 FALCON_DMA_STAT(rx_bad_gtjumbo, XgRxJabberPkts),
188 FALCON_DMA_STAT(rx_overflow, XgRxDropEvents),
189 FALCON_DMA_STAT(rx_symbol_error, XgRxSymbolError),
190 FALCON_DMA_STAT(rx_align_error, XgRxAlignError),
191 FALCON_DMA_STAT(rx_length_error, XgRxLengthError),
192 FALCON_DMA_STAT(rx_internal_error, XgRxInternalMACError),
193 FALCON_OTHER_STAT(rx_nodesc_drop_cnt),
194 };
195 static const unsigned long falcon_stat_mask[] = {
196 [0 ... BITS_TO_LONGS(FALCON_STAT_COUNT) - 1] = ~0UL,
197 };
198
199 /**************************************************************************
200 *
201 * Basic SPI command set and bit definitions
202 *
203 *************************************************************************/
204
205 #define SPI_WRSR 0x01 /* Write status register */
206 #define SPI_WRITE 0x02 /* Write data to memory array */
207 #define SPI_READ 0x03 /* Read data from memory array */
208 #define SPI_WRDI 0x04 /* Reset write enable latch */
209 #define SPI_RDSR 0x05 /* Read status register */
210 #define SPI_WREN 0x06 /* Set write enable latch */
211 #define SPI_SST_EWSR 0x50 /* SST: Enable write to status register */
212
213 #define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */
214 #define SPI_STATUS_BP2 0x10 /* Block protection bit 2 */
215 #define SPI_STATUS_BP1 0x08 /* Block protection bit 1 */
216 #define SPI_STATUS_BP0 0x04 /* Block protection bit 0 */
217 #define SPI_STATUS_WEN 0x02 /* State of the write enable latch */
218 #define SPI_STATUS_NRDY 0x01 /* Device busy flag */
219
220 /**************************************************************************
221 *
222 * Non-volatile memory layout
223 *
224 **************************************************************************
225 */
226
227 /* SFC4000 flash is partitioned into:
228 * 0-0x400 chip and board config (see struct falcon_nvconfig)
229 * 0x400-0x8000 unused (or may contain VPD if EEPROM not present)
230 * 0x8000-end boot code (mapped to PCI expansion ROM)
231 * SFC4000 small EEPROM (size < 0x400) is used for VPD only.
232 * SFC4000 large EEPROM (size >= 0x400) is partitioned into:
233 * 0-0x400 chip and board config
234 * configurable VPD
235 * 0x800-0x1800 boot config
236 * Aside from the chip and board config, all of these are optional and may
237 * be absent or truncated depending on the devices used.
238 */
239 #define FALCON_NVCONFIG_END 0x400U
240 #define FALCON_FLASH_BOOTCODE_START 0x8000U
241 #define FALCON_EEPROM_BOOTCONFIG_START 0x800U
242 #define FALCON_EEPROM_BOOTCONFIG_END 0x1800U
243
244 /* Board configuration v2 (v1 is obsolete; later versions are compatible) */
245 struct falcon_nvconfig_board_v2 {
246 __le16 nports;
247 u8 port0_phy_addr;
248 u8 port0_phy_type;
249 u8 port1_phy_addr;
250 u8 port1_phy_type;
251 __le16 asic_sub_revision;
252 __le16 board_revision;
253 } __packed;
254
255 /* Board configuration v3 extra information */
256 struct falcon_nvconfig_board_v3 {
257 __le32 spi_device_type[2];
258 } __packed;
259
260 /* Bit numbers for spi_device_type */
261 #define SPI_DEV_TYPE_SIZE_LBN 0
262 #define SPI_DEV_TYPE_SIZE_WIDTH 5
263 #define SPI_DEV_TYPE_ADDR_LEN_LBN 6
264 #define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
265 #define SPI_DEV_TYPE_ERASE_CMD_LBN 8
266 #define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
267 #define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
268 #define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
269 #define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
270 #define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
271 #define SPI_DEV_TYPE_FIELD(type, field) \
272 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
273
274 #define FALCON_NVCONFIG_OFFSET 0x300
275
276 #define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
277 struct falcon_nvconfig {
278 efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
279 u8 mac_address[2][8]; /* 0x310 */
280 efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */
281 efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */
282 efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */
283 efx_oword_t hw_init_reg; /* 0x350 */
284 efx_oword_t nic_stat_reg; /* 0x360 */
285 efx_oword_t glb_ctl_reg; /* 0x370 */
286 efx_oword_t srm_cfg_reg; /* 0x380 */
287 efx_oword_t spare_reg; /* 0x390 */
288 __le16 board_magic_num; /* 0x3A0 */
289 __le16 board_struct_ver;
290 __le16 board_checksum;
291 struct falcon_nvconfig_board_v2 board_v2;
292 efx_oword_t ee_base_page_reg; /* 0x3B0 */
293 struct falcon_nvconfig_board_v3 board_v3; /* 0x3C0 */
294 } __packed;
295
296 /*************************************************************************/
297
298 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method);
299 static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
300
301 static const unsigned int
302 /* "Large" EEPROM device: Atmel AT25640 or similar
303 * 8 KB, 16-bit address, 32 B write block */
304 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
305 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
306 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
307 /* Default flash device: Atmel AT25F1024
308 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
309 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
310 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
311 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
312 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
313 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
314
315 /**************************************************************************
316 *
317 * I2C bus - this is a bit-bashing interface using GPIO pins
318 * Note that it uses the output enables to tristate the outputs
319 * SDA is the data pin and SCL is the clock
320 *
321 **************************************************************************
322 */
323 static void falcon_setsda(void *data, int state)
324 {
325 struct efx_nic *efx = (struct efx_nic *)data;
326 efx_oword_t reg;
327
328 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
329 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
330 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
331 }
332
333 static void falcon_setscl(void *data, int state)
334 {
335 struct efx_nic *efx = (struct efx_nic *)data;
336 efx_oword_t reg;
337
338 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
339 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
340 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
341 }
342
343 static int falcon_getsda(void *data)
344 {
345 struct efx_nic *efx = (struct efx_nic *)data;
346 efx_oword_t reg;
347
348 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
349 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
350 }
351
352 static int falcon_getscl(void *data)
353 {
354 struct efx_nic *efx = (struct efx_nic *)data;
355 efx_oword_t reg;
356
357 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
358 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
359 }
360
361 static const struct i2c_algo_bit_data falcon_i2c_bit_operations = {
362 .setsda = falcon_setsda,
363 .setscl = falcon_setscl,
364 .getsda = falcon_getsda,
365 .getscl = falcon_getscl,
366 .udelay = 5,
367 /* Wait up to 50 ms for slave to let us pull SCL high */
368 .timeout = DIV_ROUND_UP(HZ, 20),
369 };
370
371 static void falcon_push_irq_moderation(struct efx_channel *channel)
372 {
373 efx_dword_t timer_cmd;
374 struct efx_nic *efx = channel->efx;
375
376 /* Set timer register */
377 if (channel->irq_moderation) {
378 EFX_POPULATE_DWORD_2(timer_cmd,
379 FRF_AB_TC_TIMER_MODE,
380 FFE_BB_TIMER_MODE_INT_HLDOFF,
381 FRF_AB_TC_TIMER_VAL,
382 channel->irq_moderation - 1);
383 } else {
384 EFX_POPULATE_DWORD_2(timer_cmd,
385 FRF_AB_TC_TIMER_MODE,
386 FFE_BB_TIMER_MODE_DIS,
387 FRF_AB_TC_TIMER_VAL, 0);
388 }
389 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
390 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
391 channel->channel);
392 }
393
394 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
395
396 static void falcon_prepare_flush(struct efx_nic *efx)
397 {
398 falcon_deconfigure_mac_wrapper(efx);
399
400 /* Wait for the tx and rx fifo's to get to the next packet boundary
401 * (~1ms without back-pressure), then to drain the remainder of the
402 * fifo's at data path speeds (negligible), with a healthy margin. */
403 msleep(10);
404 }
405
406 /* Acknowledge a legacy interrupt from Falcon
407 *
408 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
409 *
410 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
411 * BIU. Interrupt acknowledge is read sensitive so must write instead
412 * (then read to ensure the BIU collector is flushed)
413 *
414 * NB most hardware supports MSI interrupts
415 */
416 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
417 {
418 efx_dword_t reg;
419
420 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
421 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
422 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
423 }
424
425
426 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
427 {
428 struct efx_nic *efx = dev_id;
429 efx_oword_t *int_ker = efx->irq_status.addr;
430 int syserr;
431 int queues;
432
433 /* Check to see if this is our interrupt. If it isn't, we
434 * exit without having touched the hardware.
435 */
436 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
437 netif_vdbg(efx, intr, efx->net_dev,
438 "IRQ %d on CPU %d not for me\n", irq,
439 raw_smp_processor_id());
440 return IRQ_NONE;
441 }
442 efx->last_irq_cpu = raw_smp_processor_id();
443 netif_vdbg(efx, intr, efx->net_dev,
444 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
445 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
446
447 if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
448 return IRQ_HANDLED;
449
450 /* Check to see if we have a serious error condition */
451 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
452 if (unlikely(syserr))
453 return efx_farch_fatal_interrupt(efx);
454
455 /* Determine interrupting queues, clear interrupt status
456 * register and acknowledge the device interrupt.
457 */
458 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
459 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
460 EFX_ZERO_OWORD(*int_ker);
461 wmb(); /* Ensure the vector is cleared before interrupt ack */
462 falcon_irq_ack_a1(efx);
463
464 if (queues & 1)
465 efx_schedule_channel_irq(efx_get_channel(efx, 0));
466 if (queues & 2)
467 efx_schedule_channel_irq(efx_get_channel(efx, 1));
468 return IRQ_HANDLED;
469 }
470 /**************************************************************************
471 *
472 * EEPROM/flash
473 *
474 **************************************************************************
475 */
476
477 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
478
479 static int falcon_spi_poll(struct efx_nic *efx)
480 {
481 efx_oword_t reg;
482 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
483 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
484 }
485
486 /* Wait for SPI command completion */
487 static int falcon_spi_wait(struct efx_nic *efx)
488 {
489 /* Most commands will finish quickly, so we start polling at
490 * very short intervals. Sometimes the command may have to
491 * wait for VPD or expansion ROM access outside of our
492 * control, so we allow up to 100 ms. */
493 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
494 int i;
495
496 for (i = 0; i < 10; i++) {
497 if (!falcon_spi_poll(efx))
498 return 0;
499 udelay(10);
500 }
501
502 for (;;) {
503 if (!falcon_spi_poll(efx))
504 return 0;
505 if (time_after_eq(jiffies, timeout)) {
506 netif_err(efx, hw, efx->net_dev,
507 "timed out waiting for SPI\n");
508 return -ETIMEDOUT;
509 }
510 schedule_timeout_uninterruptible(1);
511 }
512 }
513
514 static int
515 falcon_spi_cmd(struct efx_nic *efx, const struct falcon_spi_device *spi,
516 unsigned int command, int address,
517 const void *in, void *out, size_t len)
518 {
519 bool addressed = (address >= 0);
520 bool reading = (out != NULL);
521 efx_oword_t reg;
522 int rc;
523
524 /* Input validation */
525 if (len > FALCON_SPI_MAX_LEN)
526 return -EINVAL;
527
528 /* Check that previous command is not still running */
529 rc = falcon_spi_poll(efx);
530 if (rc)
531 return rc;
532
533 /* Program address register, if we have an address */
534 if (addressed) {
535 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
536 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
537 }
538
539 /* Program data register, if we have data */
540 if (in != NULL) {
541 memcpy(&reg, in, len);
542 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
543 }
544
545 /* Issue read/write command */
546 EFX_POPULATE_OWORD_7(reg,
547 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
548 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
549 FRF_AB_EE_SPI_HCMD_DABCNT, len,
550 FRF_AB_EE_SPI_HCMD_READ, reading,
551 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
552 FRF_AB_EE_SPI_HCMD_ADBCNT,
553 (addressed ? spi->addr_len : 0),
554 FRF_AB_EE_SPI_HCMD_ENC, command);
555 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
556
557 /* Wait for read/write to complete */
558 rc = falcon_spi_wait(efx);
559 if (rc)
560 return rc;
561
562 /* Read data */
563 if (out != NULL) {
564 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
565 memcpy(out, &reg, len);
566 }
567
568 return 0;
569 }
570
571 static inline u8
572 falcon_spi_munge_command(const struct falcon_spi_device *spi,
573 const u8 command, const unsigned int address)
574 {
575 return command | (((address >> 8) & spi->munge_address) << 3);
576 }
577
578 static int
579 falcon_spi_read(struct efx_nic *efx, const struct falcon_spi_device *spi,
580 loff_t start, size_t len, size_t *retlen, u8 *buffer)
581 {
582 size_t block_len, pos = 0;
583 unsigned int command;
584 int rc = 0;
585
586 while (pos < len) {
587 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
588
589 command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
590 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
591 buffer + pos, block_len);
592 if (rc)
593 break;
594 pos += block_len;
595
596 /* Avoid locking up the system */
597 cond_resched();
598 if (signal_pending(current)) {
599 rc = -EINTR;
600 break;
601 }
602 }
603
604 if (retlen)
605 *retlen = pos;
606 return rc;
607 }
608
609 #ifdef CONFIG_SFC_MTD
610
611 struct falcon_mtd_partition {
612 struct efx_mtd_partition common;
613 const struct falcon_spi_device *spi;
614 size_t offset;
615 };
616
617 #define to_falcon_mtd_partition(mtd) \
618 container_of(mtd, struct falcon_mtd_partition, common.mtd)
619
620 static size_t
621 falcon_spi_write_limit(const struct falcon_spi_device *spi, size_t start)
622 {
623 return min(FALCON_SPI_MAX_LEN,
624 (spi->block_size - (start & (spi->block_size - 1))));
625 }
626
627 /* Wait up to 10 ms for buffered write completion */
628 static int
629 falcon_spi_wait_write(struct efx_nic *efx, const struct falcon_spi_device *spi)
630 {
631 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
632 u8 status;
633 int rc;
634
635 for (;;) {
636 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
637 &status, sizeof(status));
638 if (rc)
639 return rc;
640 if (!(status & SPI_STATUS_NRDY))
641 return 0;
642 if (time_after_eq(jiffies, timeout)) {
643 netif_err(efx, hw, efx->net_dev,
644 "SPI write timeout on device %d"
645 " last status=0x%02x\n",
646 spi->device_id, status);
647 return -ETIMEDOUT;
648 }
649 schedule_timeout_uninterruptible(1);
650 }
651 }
652
653 static int
654 falcon_spi_write(struct efx_nic *efx, const struct falcon_spi_device *spi,
655 loff_t start, size_t len, size_t *retlen, const u8 *buffer)
656 {
657 u8 verify_buffer[FALCON_SPI_MAX_LEN];
658 size_t block_len, pos = 0;
659 unsigned int command;
660 int rc = 0;
661
662 while (pos < len) {
663 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
664 if (rc)
665 break;
666
667 block_len = min(len - pos,
668 falcon_spi_write_limit(spi, start + pos));
669 command = falcon_spi_munge_command(spi, SPI_WRITE, start + pos);
670 rc = falcon_spi_cmd(efx, spi, command, start + pos,
671 buffer + pos, NULL, block_len);
672 if (rc)
673 break;
674
675 rc = falcon_spi_wait_write(efx, spi);
676 if (rc)
677 break;
678
679 command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
680 rc = falcon_spi_cmd(efx, spi, command, start + pos,
681 NULL, verify_buffer, block_len);
682 if (memcmp(verify_buffer, buffer + pos, block_len)) {
683 rc = -EIO;
684 break;
685 }
686
687 pos += block_len;
688
689 /* Avoid locking up the system */
690 cond_resched();
691 if (signal_pending(current)) {
692 rc = -EINTR;
693 break;
694 }
695 }
696
697 if (retlen)
698 *retlen = pos;
699 return rc;
700 }
701
702 static int
703 falcon_spi_slow_wait(struct falcon_mtd_partition *part, bool uninterruptible)
704 {
705 const struct falcon_spi_device *spi = part->spi;
706 struct efx_nic *efx = part->common.mtd.priv;
707 u8 status;
708 int rc, i;
709
710 /* Wait up to 4s for flash/EEPROM to finish a slow operation. */
711 for (i = 0; i < 40; i++) {
712 __set_current_state(uninterruptible ?
713 TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE);
714 schedule_timeout(HZ / 10);
715 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
716 &status, sizeof(status));
717 if (rc)
718 return rc;
719 if (!(status & SPI_STATUS_NRDY))
720 return 0;
721 if (signal_pending(current))
722 return -EINTR;
723 }
724 pr_err("%s: timed out waiting for %s\n",
725 part->common.name, part->common.dev_type_name);
726 return -ETIMEDOUT;
727 }
728
729 static int
730 falcon_spi_unlock(struct efx_nic *efx, const struct falcon_spi_device *spi)
731 {
732 const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 |
733 SPI_STATUS_BP0);
734 u8 status;
735 int rc;
736
737 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
738 &status, sizeof(status));
739 if (rc)
740 return rc;
741
742 if (!(status & unlock_mask))
743 return 0; /* already unlocked */
744
745 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
746 if (rc)
747 return rc;
748 rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
749 if (rc)
750 return rc;
751
752 status &= ~unlock_mask;
753 rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
754 NULL, sizeof(status));
755 if (rc)
756 return rc;
757 rc = falcon_spi_wait_write(efx, spi);
758 if (rc)
759 return rc;
760
761 return 0;
762 }
763
764 #define FALCON_SPI_VERIFY_BUF_LEN 16
765
766 static int
767 falcon_spi_erase(struct falcon_mtd_partition *part, loff_t start, size_t len)
768 {
769 const struct falcon_spi_device *spi = part->spi;
770 struct efx_nic *efx = part->common.mtd.priv;
771 unsigned pos, block_len;
772 u8 empty[FALCON_SPI_VERIFY_BUF_LEN];
773 u8 buffer[FALCON_SPI_VERIFY_BUF_LEN];
774 int rc;
775
776 if (len != spi->erase_size)
777 return -EINVAL;
778
779 if (spi->erase_command == 0)
780 return -EOPNOTSUPP;
781
782 rc = falcon_spi_unlock(efx, spi);
783 if (rc)
784 return rc;
785 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
786 if (rc)
787 return rc;
788 rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
789 NULL, 0);
790 if (rc)
791 return rc;
792 rc = falcon_spi_slow_wait(part, false);
793
794 /* Verify the entire region has been wiped */
795 memset(empty, 0xff, sizeof(empty));
796 for (pos = 0; pos < len; pos += block_len) {
797 block_len = min(len - pos, sizeof(buffer));
798 rc = falcon_spi_read(efx, spi, start + pos, block_len,
799 NULL, buffer);
800 if (rc)
801 return rc;
802 if (memcmp(empty, buffer, block_len))
803 return -EIO;
804
805 /* Avoid locking up the system */
806 cond_resched();
807 if (signal_pending(current))
808 return -EINTR;
809 }
810
811 return rc;
812 }
813
814 static void falcon_mtd_rename(struct efx_mtd_partition *part)
815 {
816 struct efx_nic *efx = part->mtd.priv;
817
818 snprintf(part->name, sizeof(part->name), "%s %s",
819 efx->name, part->type_name);
820 }
821
822 static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
823 size_t len, size_t *retlen, u8 *buffer)
824 {
825 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
826 struct efx_nic *efx = mtd->priv;
827 struct falcon_nic_data *nic_data = efx->nic_data;
828 int rc;
829
830 rc = mutex_lock_interruptible(&nic_data->spi_lock);
831 if (rc)
832 return rc;
833 rc = falcon_spi_read(efx, part->spi, part->offset + start,
834 len, retlen, buffer);
835 mutex_unlock(&nic_data->spi_lock);
836 return rc;
837 }
838
839 static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
840 {
841 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
842 struct efx_nic *efx = mtd->priv;
843 struct falcon_nic_data *nic_data = efx->nic_data;
844 int rc;
845
846 rc = mutex_lock_interruptible(&nic_data->spi_lock);
847 if (rc)
848 return rc;
849 rc = falcon_spi_erase(part, part->offset + start, len);
850 mutex_unlock(&nic_data->spi_lock);
851 return rc;
852 }
853
854 static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
855 size_t len, size_t *retlen, const u8 *buffer)
856 {
857 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
858 struct efx_nic *efx = mtd->priv;
859 struct falcon_nic_data *nic_data = efx->nic_data;
860 int rc;
861
862 rc = mutex_lock_interruptible(&nic_data->spi_lock);
863 if (rc)
864 return rc;
865 rc = falcon_spi_write(efx, part->spi, part->offset + start,
866 len, retlen, buffer);
867 mutex_unlock(&nic_data->spi_lock);
868 return rc;
869 }
870
871 static int falcon_mtd_sync(struct mtd_info *mtd)
872 {
873 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
874 struct efx_nic *efx = mtd->priv;
875 struct falcon_nic_data *nic_data = efx->nic_data;
876 int rc;
877
878 mutex_lock(&nic_data->spi_lock);
879 rc = falcon_spi_slow_wait(part, true);
880 mutex_unlock(&nic_data->spi_lock);
881 return rc;
882 }
883
884 static int falcon_mtd_probe(struct efx_nic *efx)
885 {
886 struct falcon_nic_data *nic_data = efx->nic_data;
887 struct falcon_mtd_partition *parts;
888 struct falcon_spi_device *spi;
889 size_t n_parts;
890 int rc = -ENODEV;
891
892 ASSERT_RTNL();
893
894 /* Allocate space for maximum number of partitions */
895 parts = kcalloc(2, sizeof(*parts), GFP_KERNEL);
896 n_parts = 0;
897
898 spi = &nic_data->spi_flash;
899 if (falcon_spi_present(spi) && spi->size > FALCON_FLASH_BOOTCODE_START) {
900 parts[n_parts].spi = spi;
901 parts[n_parts].offset = FALCON_FLASH_BOOTCODE_START;
902 parts[n_parts].common.dev_type_name = "flash";
903 parts[n_parts].common.type_name = "sfc_flash_bootrom";
904 parts[n_parts].common.mtd.type = MTD_NORFLASH;
905 parts[n_parts].common.mtd.flags = MTD_CAP_NORFLASH;
906 parts[n_parts].common.mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
907 parts[n_parts].common.mtd.erasesize = spi->erase_size;
908 n_parts++;
909 }
910
911 spi = &nic_data->spi_eeprom;
912 if (falcon_spi_present(spi) && spi->size > FALCON_EEPROM_BOOTCONFIG_START) {
913 parts[n_parts].spi = spi;
914 parts[n_parts].offset = FALCON_EEPROM_BOOTCONFIG_START;
915 parts[n_parts].common.dev_type_name = "EEPROM";
916 parts[n_parts].common.type_name = "sfc_bootconfig";
917 parts[n_parts].common.mtd.type = MTD_RAM;
918 parts[n_parts].common.mtd.flags = MTD_CAP_RAM;
919 parts[n_parts].common.mtd.size =
920 min(spi->size, FALCON_EEPROM_BOOTCONFIG_END) -
921 FALCON_EEPROM_BOOTCONFIG_START;
922 parts[n_parts].common.mtd.erasesize = spi->erase_size;
923 n_parts++;
924 }
925
926 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
927 if (rc)
928 kfree(parts);
929 return rc;
930 }
931
932 #endif /* CONFIG_SFC_MTD */
933
934 /**************************************************************************
935 *
936 * XMAC operations
937 *
938 **************************************************************************
939 */
940
941 /* Configure the XAUI driver that is an output from Falcon */
942 static void falcon_setup_xaui(struct efx_nic *efx)
943 {
944 efx_oword_t sdctl, txdrv;
945
946 /* Move the XAUI into low power, unless there is no PHY, in
947 * which case the XAUI will have to drive a cable. */
948 if (efx->phy_type == PHY_TYPE_NONE)
949 return;
950
951 efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
952 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
953 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
954 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
955 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
956 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
957 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
958 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
959 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
960 efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
961
962 EFX_POPULATE_OWORD_8(txdrv,
963 FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
964 FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
965 FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
966 FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
967 FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
968 FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
969 FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
970 FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
971 efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
972 }
973
974 int falcon_reset_xaui(struct efx_nic *efx)
975 {
976 struct falcon_nic_data *nic_data = efx->nic_data;
977 efx_oword_t reg;
978 int count;
979
980 /* Don't fetch MAC statistics over an XMAC reset */
981 WARN_ON(nic_data->stats_disable_count == 0);
982
983 /* Start reset sequence */
984 EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
985 efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
986
987 /* Wait up to 10 ms for completion, then reinitialise */
988 for (count = 0; count < 1000; count++) {
989 efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
990 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
991 EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
992 falcon_setup_xaui(efx);
993 return 0;
994 }
995 udelay(10);
996 }
997 netif_err(efx, hw, efx->net_dev,
998 "timed out waiting for XAUI/XGXS reset\n");
999 return -ETIMEDOUT;
1000 }
1001
1002 static void falcon_ack_status_intr(struct efx_nic *efx)
1003 {
1004 struct falcon_nic_data *nic_data = efx->nic_data;
1005 efx_oword_t reg;
1006
1007 if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
1008 return;
1009
1010 /* We expect xgmii faults if the wireside link is down */
1011 if (!efx->link_state.up)
1012 return;
1013
1014 /* We can only use this interrupt to signal the negative edge of
1015 * xaui_align [we have to poll the positive edge]. */
1016 if (nic_data->xmac_poll_required)
1017 return;
1018
1019 efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
1020 }
1021
1022 static bool falcon_xgxs_link_ok(struct efx_nic *efx)
1023 {
1024 efx_oword_t reg;
1025 bool align_done, link_ok = false;
1026 int sync_status;
1027
1028 /* Read link status */
1029 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1030
1031 align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
1032 sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
1033 if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
1034 link_ok = true;
1035
1036 /* Clear link status ready for next read */
1037 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
1038 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
1039 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
1040 efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
1041
1042 return link_ok;
1043 }
1044
1045 static bool falcon_xmac_link_ok(struct efx_nic *efx)
1046 {
1047 /*
1048 * Check MAC's XGXS link status except when using XGMII loopback
1049 * which bypasses the XGXS block.
1050 * If possible, check PHY's XGXS link status except when using
1051 * MAC loopback.
1052 */
1053 return (efx->loopback_mode == LOOPBACK_XGMII ||
1054 falcon_xgxs_link_ok(efx)) &&
1055 (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
1056 LOOPBACK_INTERNAL(efx) ||
1057 efx_mdio_phyxgxs_lane_sync(efx));
1058 }
1059
1060 static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
1061 {
1062 unsigned int max_frame_len;
1063 efx_oword_t reg;
1064 bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
1065 bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
1066
1067 /* Configure MAC - cut-thru mode is hard wired on */
1068 EFX_POPULATE_OWORD_3(reg,
1069 FRF_AB_XM_RX_JUMBO_MODE, 1,
1070 FRF_AB_XM_TX_STAT_EN, 1,
1071 FRF_AB_XM_RX_STAT_EN, 1);
1072 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1073
1074 /* Configure TX */
1075 EFX_POPULATE_OWORD_6(reg,
1076 FRF_AB_XM_TXEN, 1,
1077 FRF_AB_XM_TX_PRMBL, 1,
1078 FRF_AB_XM_AUTO_PAD, 1,
1079 FRF_AB_XM_TXCRC, 1,
1080 FRF_AB_XM_FCNTL, tx_fc,
1081 FRF_AB_XM_IPG, 0x3);
1082 efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
1083
1084 /* Configure RX */
1085 EFX_POPULATE_OWORD_5(reg,
1086 FRF_AB_XM_RXEN, 1,
1087 FRF_AB_XM_AUTO_DEPAD, 0,
1088 FRF_AB_XM_ACPT_ALL_MCAST, 1,
1089 FRF_AB_XM_ACPT_ALL_UCAST, !efx->unicast_filter,
1090 FRF_AB_XM_PASS_CRC_ERR, 1);
1091 efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
1092
1093 /* Set frame length */
1094 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
1095 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
1096 efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
1097 EFX_POPULATE_OWORD_2(reg,
1098 FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
1099 FRF_AB_XM_TX_JUMBO_MODE, 1);
1100 efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
1101
1102 EFX_POPULATE_OWORD_2(reg,
1103 FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
1104 FRF_AB_XM_DIS_FCNTL, !rx_fc);
1105 efx_writeo(efx, &reg, FR_AB_XM_FC);
1106
1107 /* Set MAC address */
1108 memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
1109 efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
1110 memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
1111 efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
1112 }
1113
1114 static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
1115 {
1116 efx_oword_t reg;
1117 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
1118 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
1119 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
1120 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
1121
1122 /* XGXS block is flaky and will need to be reset if moving
1123 * into our out of XGMII, XGXS or XAUI loopbacks. */
1124 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1125 old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
1126 old_xgmii_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
1127
1128 efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
1129 old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
1130
1131 /* The PHY driver may have turned XAUI off */
1132 if ((xgxs_loopback != old_xgxs_loopback) ||
1133 (xaui_loopback != old_xaui_loopback) ||
1134 (xgmii_loopback != old_xgmii_loopback))
1135 falcon_reset_xaui(efx);
1136
1137 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1138 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
1139 (xgxs_loopback || xaui_loopback) ?
1140 FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
1141 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
1142 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
1143 efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
1144
1145 efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
1146 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
1147 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
1148 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
1149 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
1150 efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
1151 }
1152
1153
1154 /* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
1155 static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
1156 {
1157 bool mac_up = falcon_xmac_link_ok(efx);
1158
1159 if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
1160 efx_phy_mode_disabled(efx->phy_mode))
1161 /* XAUI link is expected to be down */
1162 return mac_up;
1163
1164 falcon_stop_nic_stats(efx);
1165
1166 while (!mac_up && tries) {
1167 netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
1168 falcon_reset_xaui(efx);
1169 udelay(200);
1170
1171 mac_up = falcon_xmac_link_ok(efx);
1172 --tries;
1173 }
1174
1175 falcon_start_nic_stats(efx);
1176
1177 return mac_up;
1178 }
1179
1180 static bool falcon_xmac_check_fault(struct efx_nic *efx)
1181 {
1182 return !falcon_xmac_link_ok_retry(efx, 5);
1183 }
1184
1185 static int falcon_reconfigure_xmac(struct efx_nic *efx)
1186 {
1187 struct falcon_nic_data *nic_data = efx->nic_data;
1188
1189 efx_farch_filter_sync_rx_mode(efx);
1190
1191 falcon_reconfigure_xgxs_core(efx);
1192 falcon_reconfigure_xmac_core(efx);
1193
1194 falcon_reconfigure_mac_wrapper(efx);
1195
1196 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
1197 falcon_ack_status_intr(efx);
1198
1199 return 0;
1200 }
1201
1202 static void falcon_poll_xmac(struct efx_nic *efx)
1203 {
1204 struct falcon_nic_data *nic_data = efx->nic_data;
1205
1206 /* We expect xgmii faults if the wireside link is down */
1207 if (!efx->link_state.up || !nic_data->xmac_poll_required)
1208 return;
1209
1210 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
1211 falcon_ack_status_intr(efx);
1212 }
1213
1214 /**************************************************************************
1215 *
1216 * MAC wrapper
1217 *
1218 **************************************************************************
1219 */
1220
1221 static void falcon_push_multicast_hash(struct efx_nic *efx)
1222 {
1223 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1224
1225 WARN_ON(!mutex_is_locked(&efx->mac_lock));
1226
1227 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
1228 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
1229 }
1230
1231 static void falcon_reset_macs(struct efx_nic *efx)
1232 {
1233 struct falcon_nic_data *nic_data = efx->nic_data;
1234 efx_oword_t reg, mac_ctrl;
1235 int count;
1236
1237 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
1238 /* It's not safe to use GLB_CTL_REG to reset the
1239 * macs, so instead use the internal MAC resets
1240 */
1241 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1242 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1243
1244 for (count = 0; count < 10000; count++) {
1245 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1246 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1247 0)
1248 return;
1249 udelay(10);
1250 }
1251
1252 netif_err(efx, hw, efx->net_dev,
1253 "timed out waiting for XMAC core reset\n");
1254 }
1255
1256 /* Mac stats will fail whist the TX fifo is draining */
1257 WARN_ON(nic_data->stats_disable_count == 0);
1258
1259 efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1260 EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
1261 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1262
1263 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1264 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1265 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1266 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1267 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1268
1269 count = 0;
1270 while (1) {
1271 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1272 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1273 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1274 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1275 netif_dbg(efx, hw, efx->net_dev,
1276 "Completed MAC reset after %d loops\n",
1277 count);
1278 break;
1279 }
1280 if (count > 20) {
1281 netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
1282 break;
1283 }
1284 count++;
1285 udelay(10);
1286 }
1287
1288 /* Ensure the correct MAC is selected before statistics
1289 * are re-enabled by the caller */
1290 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1291
1292 falcon_setup_xaui(efx);
1293 }
1294
1295 static void falcon_drain_tx_fifo(struct efx_nic *efx)
1296 {
1297 efx_oword_t reg;
1298
1299 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
1300 (efx->loopback_mode != LOOPBACK_NONE))
1301 return;
1302
1303 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1304 /* There is no point in draining more than once */
1305 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1306 return;
1307
1308 falcon_reset_macs(efx);
1309 }
1310
1311 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1312 {
1313 efx_oword_t reg;
1314
1315 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1316 return;
1317
1318 /* Isolate the MAC -> RX */
1319 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1320 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1321 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1322
1323 /* Isolate TX -> MAC */
1324 falcon_drain_tx_fifo(efx);
1325 }
1326
1327 static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1328 {
1329 struct efx_link_state *link_state = &efx->link_state;
1330 efx_oword_t reg;
1331 int link_speed, isolate;
1332
1333 isolate = !!ACCESS_ONCE(efx->reset_pending);
1334
1335 switch (link_state->speed) {
1336 case 10000: link_speed = 3; break;
1337 case 1000: link_speed = 2; break;
1338 case 100: link_speed = 1; break;
1339 default: link_speed = 0; break;
1340 }
1341 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1342 * as advertised. Disable to ensure packets are not
1343 * indefinitely held and TX queue can be flushed at any point
1344 * while the link is down. */
1345 EFX_POPULATE_OWORD_5(reg,
1346 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1347 FRF_AB_MAC_BCAD_ACPT, 1,
1348 FRF_AB_MAC_UC_PROM, !efx->unicast_filter,
1349 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1350 FRF_AB_MAC_SPEED, link_speed);
1351 /* On B0, MAC backpressure can be disabled and packets get
1352 * discarded. */
1353 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1354 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1355 !link_state->up || isolate);
1356 }
1357
1358 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1359
1360 /* Restore the multicast hash registers. */
1361 falcon_push_multicast_hash(efx);
1362
1363 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1364 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
1365 * initialisation but it may read back as 0) */
1366 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1367 /* Unisolate the MAC -> RX */
1368 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1369 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
1370 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1371 }
1372
1373 static void falcon_stats_request(struct efx_nic *efx)
1374 {
1375 struct falcon_nic_data *nic_data = efx->nic_data;
1376 efx_oword_t reg;
1377
1378 WARN_ON(nic_data->stats_pending);
1379 WARN_ON(nic_data->stats_disable_count);
1380
1381 FALCON_XMAC_STATS_DMA_FLAG(efx) = 0;
1382 nic_data->stats_pending = true;
1383 wmb(); /* ensure done flag is clear */
1384
1385 /* Initiate DMA transfer of stats */
1386 EFX_POPULATE_OWORD_2(reg,
1387 FRF_AB_MAC_STAT_DMA_CMD, 1,
1388 FRF_AB_MAC_STAT_DMA_ADR,
1389 efx->stats_buffer.dma_addr);
1390 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
1391
1392 mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
1393 }
1394
1395 static void falcon_stats_complete(struct efx_nic *efx)
1396 {
1397 struct falcon_nic_data *nic_data = efx->nic_data;
1398
1399 if (!nic_data->stats_pending)
1400 return;
1401
1402 nic_data->stats_pending = false;
1403 if (FALCON_XMAC_STATS_DMA_FLAG(efx)) {
1404 rmb(); /* read the done flag before the stats */
1405 efx_nic_update_stats(falcon_stat_desc, FALCON_STAT_COUNT,
1406 falcon_stat_mask, nic_data->stats,
1407 efx->stats_buffer.addr, true);
1408 } else {
1409 netif_err(efx, hw, efx->net_dev,
1410 "timed out waiting for statistics\n");
1411 }
1412 }
1413
1414 static void falcon_stats_timer_func(unsigned long context)
1415 {
1416 struct efx_nic *efx = (struct efx_nic *)context;
1417 struct falcon_nic_data *nic_data = efx->nic_data;
1418
1419 spin_lock(&efx->stats_lock);
1420
1421 falcon_stats_complete(efx);
1422 if (nic_data->stats_disable_count == 0)
1423 falcon_stats_request(efx);
1424
1425 spin_unlock(&efx->stats_lock);
1426 }
1427
1428 static bool falcon_loopback_link_poll(struct efx_nic *efx)
1429 {
1430 struct efx_link_state old_state = efx->link_state;
1431
1432 WARN_ON(!mutex_is_locked(&efx->mac_lock));
1433 WARN_ON(!LOOPBACK_INTERNAL(efx));
1434
1435 efx->link_state.fd = true;
1436 efx->link_state.fc = efx->wanted_fc;
1437 efx->link_state.up = true;
1438 efx->link_state.speed = 10000;
1439
1440 return !efx_link_state_equal(&efx->link_state, &old_state);
1441 }
1442
1443 static int falcon_reconfigure_port(struct efx_nic *efx)
1444 {
1445 int rc;
1446
1447 WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
1448
1449 /* Poll the PHY link state *before* reconfiguring it. This means we
1450 * will pick up the correct speed (in loopback) to select the correct
1451 * MAC.
1452 */
1453 if (LOOPBACK_INTERNAL(efx))
1454 falcon_loopback_link_poll(efx);
1455 else
1456 efx->phy_op->poll(efx);
1457
1458 falcon_stop_nic_stats(efx);
1459 falcon_deconfigure_mac_wrapper(efx);
1460
1461 falcon_reset_macs(efx);
1462
1463 efx->phy_op->reconfigure(efx);
1464 rc = falcon_reconfigure_xmac(efx);
1465 BUG_ON(rc);
1466
1467 falcon_start_nic_stats(efx);
1468
1469 /* Synchronise efx->link_state with the kernel */
1470 efx_link_status_changed(efx);
1471
1472 return 0;
1473 }
1474
1475 /* TX flow control may automatically turn itself off if the link
1476 * partner (intermittently) stops responding to pause frames. There
1477 * isn't any indication that this has happened, so the best we do is
1478 * leave it up to the user to spot this and fix it by cycling transmit
1479 * flow control on this end.
1480 */
1481
1482 static void falcon_a1_prepare_enable_fc_tx(struct efx_nic *efx)
1483 {
1484 /* Schedule a reset to recover */
1485 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
1486 }
1487
1488 static void falcon_b0_prepare_enable_fc_tx(struct efx_nic *efx)
1489 {
1490 /* Recover by resetting the EM block */
1491 falcon_stop_nic_stats(efx);
1492 falcon_drain_tx_fifo(efx);
1493 falcon_reconfigure_xmac(efx);
1494 falcon_start_nic_stats(efx);
1495 }
1496
1497 /**************************************************************************
1498 *
1499 * PHY access via GMII
1500 *
1501 **************************************************************************
1502 */
1503
1504 /* Wait for GMII access to complete */
1505 static int falcon_gmii_wait(struct efx_nic *efx)
1506 {
1507 efx_oword_t md_stat;
1508 int count;
1509
1510 /* wait up to 50ms - taken max from datasheet */
1511 for (count = 0; count < 5000; count++) {
1512 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
1513 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
1514 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
1515 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
1516 netif_err(efx, hw, efx->net_dev,
1517 "error from GMII access "
1518 EFX_OWORD_FMT"\n",
1519 EFX_OWORD_VAL(md_stat));
1520 return -EIO;
1521 }
1522 return 0;
1523 }
1524 udelay(10);
1525 }
1526 netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
1527 return -ETIMEDOUT;
1528 }
1529
1530 /* Write an MDIO register of a PHY connected to Falcon. */
1531 static int falcon_mdio_write(struct net_device *net_dev,
1532 int prtad, int devad, u16 addr, u16 value)
1533 {
1534 struct efx_nic *efx = netdev_priv(net_dev);
1535 struct falcon_nic_data *nic_data = efx->nic_data;
1536 efx_oword_t reg;
1537 int rc;
1538
1539 netif_vdbg(efx, hw, efx->net_dev,
1540 "writing MDIO %d register %d.%d with 0x%04x\n",
1541 prtad, devad, addr, value);
1542
1543 mutex_lock(&nic_data->mdio_lock);
1544
1545 /* Check MDIO not currently being accessed */
1546 rc = falcon_gmii_wait(efx);
1547 if (rc)
1548 goto out;
1549
1550 /* Write the address/ID register */
1551 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
1552 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
1553
1554 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
1555 FRF_AB_MD_DEV_ADR, devad);
1556 efx_writeo(efx, &reg, FR_AB_MD_ID);
1557
1558 /* Write data */
1559 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
1560 efx_writeo(efx, &reg, FR_AB_MD_TXD);
1561
1562 EFX_POPULATE_OWORD_2(reg,
1563 FRF_AB_MD_WRC, 1,
1564 FRF_AB_MD_GC, 0);
1565 efx_writeo(efx, &reg, FR_AB_MD_CS);
1566
1567 /* Wait for data to be written */
1568 rc = falcon_gmii_wait(efx);
1569 if (rc) {
1570 /* Abort the write operation */
1571 EFX_POPULATE_OWORD_2(reg,
1572 FRF_AB_MD_WRC, 0,
1573 FRF_AB_MD_GC, 1);
1574 efx_writeo(efx, &reg, FR_AB_MD_CS);
1575 udelay(10);
1576 }
1577
1578 out:
1579 mutex_unlock(&nic_data->mdio_lock);
1580 return rc;
1581 }
1582
1583 /* Read an MDIO register of a PHY connected to Falcon. */
1584 static int falcon_mdio_read(struct net_device *net_dev,
1585 int prtad, int devad, u16 addr)
1586 {
1587 struct efx_nic *efx = netdev_priv(net_dev);
1588 struct falcon_nic_data *nic_data = efx->nic_data;
1589 efx_oword_t reg;
1590 int rc;
1591
1592 mutex_lock(&nic_data->mdio_lock);
1593
1594 /* Check MDIO not currently being accessed */
1595 rc = falcon_gmii_wait(efx);
1596 if (rc)
1597 goto out;
1598
1599 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
1600 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
1601
1602 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
1603 FRF_AB_MD_DEV_ADR, devad);
1604 efx_writeo(efx, &reg, FR_AB_MD_ID);
1605
1606 /* Request data to be read */
1607 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
1608 efx_writeo(efx, &reg, FR_AB_MD_CS);
1609
1610 /* Wait for data to become available */
1611 rc = falcon_gmii_wait(efx);
1612 if (rc == 0) {
1613 efx_reado(efx, &reg, FR_AB_MD_RXD);
1614 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
1615 netif_vdbg(efx, hw, efx->net_dev,
1616 "read from MDIO %d register %d.%d, got %04x\n",
1617 prtad, devad, addr, rc);
1618 } else {
1619 /* Abort the read operation */
1620 EFX_POPULATE_OWORD_2(reg,
1621 FRF_AB_MD_RIC, 0,
1622 FRF_AB_MD_GC, 1);
1623 efx_writeo(efx, &reg, FR_AB_MD_CS);
1624
1625 netif_dbg(efx, hw, efx->net_dev,
1626 "read from MDIO %d register %d.%d, got error %d\n",
1627 prtad, devad, addr, rc);
1628 }
1629
1630 out:
1631 mutex_unlock(&nic_data->mdio_lock);
1632 return rc;
1633 }
1634
1635 /* This call is responsible for hooking in the MAC and PHY operations */
1636 static int falcon_probe_port(struct efx_nic *efx)
1637 {
1638 struct falcon_nic_data *nic_data = efx->nic_data;
1639 int rc;
1640
1641 switch (efx->phy_type) {
1642 case PHY_TYPE_SFX7101:
1643 efx->phy_op = &falcon_sfx7101_phy_ops;
1644 break;
1645 case PHY_TYPE_QT2022C2:
1646 case PHY_TYPE_QT2025C:
1647 efx->phy_op = &falcon_qt202x_phy_ops;
1648 break;
1649 case PHY_TYPE_TXC43128:
1650 efx->phy_op = &falcon_txc_phy_ops;
1651 break;
1652 default:
1653 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
1654 efx->phy_type);
1655 return -ENODEV;
1656 }
1657
1658 /* Fill out MDIO structure and loopback modes */
1659 mutex_init(&nic_data->mdio_lock);
1660 efx->mdio.mdio_read = falcon_mdio_read;
1661 efx->mdio.mdio_write = falcon_mdio_write;
1662 rc = efx->phy_op->probe(efx);
1663 if (rc != 0)
1664 return rc;
1665
1666 /* Initial assumption */
1667 efx->link_state.speed = 10000;
1668 efx->link_state.fd = true;
1669
1670 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
1671 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1672 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
1673 else
1674 efx->wanted_fc = EFX_FC_RX;
1675 if (efx->mdio.mmds & MDIO_DEVS_AN)
1676 efx->wanted_fc |= EFX_FC_AUTO;
1677
1678 /* Allocate buffer for stats */
1679 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
1680 FALCON_MAC_STATS_SIZE, GFP_KERNEL);
1681 if (rc)
1682 return rc;
1683 netif_dbg(efx, probe, efx->net_dev,
1684 "stats buffer at %llx (virt %p phys %llx)\n",
1685 (u64)efx->stats_buffer.dma_addr,
1686 efx->stats_buffer.addr,
1687 (u64)virt_to_phys(efx->stats_buffer.addr));
1688
1689 return 0;
1690 }
1691
1692 static void falcon_remove_port(struct efx_nic *efx)
1693 {
1694 efx->phy_op->remove(efx);
1695 efx_nic_free_buffer(efx, &efx->stats_buffer);
1696 }
1697
1698 /* Global events are basically PHY events */
1699 static bool
1700 falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
1701 {
1702 struct efx_nic *efx = channel->efx;
1703 struct falcon_nic_data *nic_data = efx->nic_data;
1704
1705 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
1706 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
1707 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR))
1708 /* Ignored */
1709 return true;
1710
1711 if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
1712 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
1713 nic_data->xmac_poll_required = true;
1714 return true;
1715 }
1716
1717 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
1718 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
1719 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
1720 netif_err(efx, rx_err, efx->net_dev,
1721 "channel %d seen global RX_RESET event. Resetting.\n",
1722 channel->channel);
1723
1724 atomic_inc(&efx->rx_reset);
1725 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1726 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1727 return true;
1728 }
1729
1730 return false;
1731 }
1732
1733 /**************************************************************************
1734 *
1735 * Falcon test code
1736 *
1737 **************************************************************************/
1738
1739 static int
1740 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
1741 {
1742 struct falcon_nic_data *nic_data = efx->nic_data;
1743 struct falcon_nvconfig *nvconfig;
1744 struct falcon_spi_device *spi;
1745 void *region;
1746 int rc, magic_num, struct_ver;
1747 __le16 *word, *limit;
1748 u32 csum;
1749
1750 if (falcon_spi_present(&nic_data->spi_flash))
1751 spi = &nic_data->spi_flash;
1752 else if (falcon_spi_present(&nic_data->spi_eeprom))
1753 spi = &nic_data->spi_eeprom;
1754 else
1755 return -EINVAL;
1756
1757 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
1758 if (!region)
1759 return -ENOMEM;
1760 nvconfig = region + FALCON_NVCONFIG_OFFSET;
1761
1762 mutex_lock(&nic_data->spi_lock);
1763 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
1764 mutex_unlock(&nic_data->spi_lock);
1765 if (rc) {
1766 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
1767 falcon_spi_present(&nic_data->spi_flash) ?
1768 "flash" : "EEPROM");
1769 rc = -EIO;
1770 goto out;
1771 }
1772
1773 magic_num = le16_to_cpu(nvconfig->board_magic_num);
1774 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
1775
1776 rc = -EINVAL;
1777 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
1778 netif_err(efx, hw, efx->net_dev,
1779 "NVRAM bad magic 0x%x\n", magic_num);
1780 goto out;
1781 }
1782 if (struct_ver < 2) {
1783 netif_err(efx, hw, efx->net_dev,
1784 "NVRAM has ancient version 0x%x\n", struct_ver);
1785 goto out;
1786 } else if (struct_ver < 4) {
1787 word = &nvconfig->board_magic_num;
1788 limit = (__le16 *) (nvconfig + 1);
1789 } else {
1790 word = region;
1791 limit = region + FALCON_NVCONFIG_END;
1792 }
1793 for (csum = 0; word < limit; ++word)
1794 csum += le16_to_cpu(*word);
1795
1796 if (~csum & 0xffff) {
1797 netif_err(efx, hw, efx->net_dev,
1798 "NVRAM has incorrect checksum\n");
1799 goto out;
1800 }
1801
1802 rc = 0;
1803 if (nvconfig_out)
1804 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
1805
1806 out:
1807 kfree(region);
1808 return rc;
1809 }
1810
1811 static int falcon_test_nvram(struct efx_nic *efx)
1812 {
1813 return falcon_read_nvram(efx, NULL);
1814 }
1815
1816 static const struct efx_farch_register_test falcon_b0_register_tests[] = {
1817 { FR_AZ_ADR_REGION,
1818 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1819 { FR_AZ_RX_CFG,
1820 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1821 { FR_AZ_TX_CFG,
1822 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1823 { FR_AZ_TX_RESERVED,
1824 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1825 { FR_AB_MAC_CTRL,
1826 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1827 { FR_AZ_SRM_TX_DC_CFG,
1828 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1829 { FR_AZ_RX_DC_CFG,
1830 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1831 { FR_AZ_RX_DC_PF_WM,
1832 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1833 { FR_BZ_DP_CTRL,
1834 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1835 { FR_AB_GM_CFG2,
1836 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1837 { FR_AB_GMF_CFG0,
1838 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1839 { FR_AB_XM_GLB_CFG,
1840 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1841 { FR_AB_XM_TX_CFG,
1842 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1843 { FR_AB_XM_RX_CFG,
1844 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1845 { FR_AB_XM_RX_PARAM,
1846 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1847 { FR_AB_XM_FC,
1848 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1849 { FR_AB_XM_ADR_LO,
1850 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1851 { FR_AB_XX_SD_CTL,
1852 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1853 };
1854
1855 static int
1856 falcon_b0_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
1857 {
1858 enum reset_type reset_method = RESET_TYPE_INVISIBLE;
1859 int rc, rc2;
1860
1861 mutex_lock(&efx->mac_lock);
1862 if (efx->loopback_modes) {
1863 /* We need the 312 clock from the PHY to test the XMAC
1864 * registers, so move into XGMII loopback if available */
1865 if (efx->loopback_modes & (1 << LOOPBACK_XGMII))
1866 efx->loopback_mode = LOOPBACK_XGMII;
1867 else
1868 efx->loopback_mode = __ffs(efx->loopback_modes);
1869 }
1870 __efx_reconfigure_port(efx);
1871 mutex_unlock(&efx->mac_lock);
1872
1873 efx_reset_down(efx, reset_method);
1874
1875 tests->registers =
1876 efx_farch_test_registers(efx, falcon_b0_register_tests,
1877 ARRAY_SIZE(falcon_b0_register_tests))
1878 ? -1 : 1;
1879
1880 rc = falcon_reset_hw(efx, reset_method);
1881 rc2 = efx_reset_up(efx, reset_method, rc == 0);
1882 return rc ? rc : rc2;
1883 }
1884
1885 /**************************************************************************
1886 *
1887 * Device reset
1888 *
1889 **************************************************************************
1890 */
1891
1892 static enum reset_type falcon_map_reset_reason(enum reset_type reason)
1893 {
1894 switch (reason) {
1895 case RESET_TYPE_RX_RECOVERY:
1896 case RESET_TYPE_DMA_ERROR:
1897 case RESET_TYPE_TX_SKIP:
1898 /* These can occasionally occur due to hardware bugs.
1899 * We try to reset without disrupting the link.
1900 */
1901 return RESET_TYPE_INVISIBLE;
1902 default:
1903 return RESET_TYPE_ALL;
1904 }
1905 }
1906
1907 static int falcon_map_reset_flags(u32 *flags)
1908 {
1909 enum {
1910 FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER |
1911 ETH_RESET_OFFLOAD | ETH_RESET_MAC),
1912 FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY,
1913 FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ,
1914 };
1915
1916 if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) {
1917 *flags &= ~FALCON_RESET_WORLD;
1918 return RESET_TYPE_WORLD;
1919 }
1920
1921 if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) {
1922 *flags &= ~FALCON_RESET_ALL;
1923 return RESET_TYPE_ALL;
1924 }
1925
1926 if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) {
1927 *flags &= ~FALCON_RESET_INVISIBLE;
1928 return RESET_TYPE_INVISIBLE;
1929 }
1930
1931 return -EINVAL;
1932 }
1933
1934 /* Resets NIC to known state. This routine must be called in process
1935 * context and is allowed to sleep. */
1936 static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1937 {
1938 struct falcon_nic_data *nic_data = efx->nic_data;
1939 efx_oword_t glb_ctl_reg_ker;
1940 int rc;
1941
1942 netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1943 RESET_TYPE(method));
1944
1945 /* Initiate device reset */
1946 if (method == RESET_TYPE_WORLD) {
1947 rc = pci_save_state(efx->pci_dev);
1948 if (rc) {
1949 netif_err(efx, drv, efx->net_dev,
1950 "failed to backup PCI state of primary "
1951 "function prior to hardware reset\n");
1952 goto fail1;
1953 }
1954 if (efx_nic_is_dual_func(efx)) {
1955 rc = pci_save_state(nic_data->pci_dev2);
1956 if (rc) {
1957 netif_err(efx, drv, efx->net_dev,
1958 "failed to backup PCI state of "
1959 "secondary function prior to "
1960 "hardware reset\n");
1961 goto fail2;
1962 }
1963 }
1964
1965 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1966 FRF_AB_EXT_PHY_RST_DUR,
1967 FFE_AB_EXT_PHY_RST_DUR_10240US,
1968 FRF_AB_SWRST, 1);
1969 } else {
1970 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1971 /* exclude PHY from "invisible" reset */
1972 FRF_AB_EXT_PHY_RST_CTL,
1973 method == RESET_TYPE_INVISIBLE,
1974 /* exclude EEPROM/flash and PCIe */
1975 FRF_AB_PCIE_CORE_RST_CTL, 1,
1976 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1977 FRF_AB_PCIE_SD_RST_CTL, 1,
1978 FRF_AB_EE_RST_CTL, 1,
1979 FRF_AB_EXT_PHY_RST_DUR,
1980 FFE_AB_EXT_PHY_RST_DUR_10240US,
1981 FRF_AB_SWRST, 1);
1982 }
1983 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1984
1985 netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
1986 schedule_timeout_uninterruptible(HZ / 20);
1987
1988 /* Restore PCI configuration if needed */
1989 if (method == RESET_TYPE_WORLD) {
1990 if (efx_nic_is_dual_func(efx))
1991 pci_restore_state(nic_data->pci_dev2);
1992 pci_restore_state(efx->pci_dev);
1993 netif_dbg(efx, drv, efx->net_dev,
1994 "successfully restored PCI config\n");
1995 }
1996
1997 /* Assert that reset complete */
1998 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1999 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2000 rc = -ETIMEDOUT;
2001 netif_err(efx, hw, efx->net_dev,
2002 "timed out waiting for hardware reset\n");
2003 goto fail3;
2004 }
2005 netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
2006
2007 return 0;
2008
2009 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2010 fail2:
2011 pci_restore_state(efx->pci_dev);
2012 fail1:
2013 fail3:
2014 return rc;
2015 }
2016
2017 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2018 {
2019 struct falcon_nic_data *nic_data = efx->nic_data;
2020 int rc;
2021
2022 mutex_lock(&nic_data->spi_lock);
2023 rc = __falcon_reset_hw(efx, method);
2024 mutex_unlock(&nic_data->spi_lock);
2025
2026 return rc;
2027 }
2028
2029 static void falcon_monitor(struct efx_nic *efx)
2030 {
2031 bool link_changed;
2032 int rc;
2033
2034 BUG_ON(!mutex_is_locked(&efx->mac_lock));
2035
2036 rc = falcon_board(efx)->type->monitor(efx);
2037 if (rc) {
2038 netif_err(efx, hw, efx->net_dev,
2039 "Board sensor %s; shutting down PHY\n",
2040 (rc == -ERANGE) ? "reported fault" : "failed");
2041 efx->phy_mode |= PHY_MODE_LOW_POWER;
2042 rc = __efx_reconfigure_port(efx);
2043 WARN_ON(rc);
2044 }
2045
2046 if (LOOPBACK_INTERNAL(efx))
2047 link_changed = falcon_loopback_link_poll(efx);
2048 else
2049 link_changed = efx->phy_op->poll(efx);
2050
2051 if (link_changed) {
2052 falcon_stop_nic_stats(efx);
2053 falcon_deconfigure_mac_wrapper(efx);
2054
2055 falcon_reset_macs(efx);
2056 rc = falcon_reconfigure_xmac(efx);
2057 BUG_ON(rc);
2058
2059 falcon_start_nic_stats(efx);
2060
2061 efx_link_status_changed(efx);
2062 }
2063
2064 falcon_poll_xmac(efx);
2065 }
2066
2067 /* Zeroes out the SRAM contents. This routine must be called in
2068 * process context and is allowed to sleep.
2069 */
2070 static int falcon_reset_sram(struct efx_nic *efx)
2071 {
2072 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2073 int count;
2074
2075 /* Set the SRAM wake/sleep GPIO appropriately. */
2076 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2077 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2078 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2079 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2080
2081 /* Initiate SRAM reset */
2082 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2083 FRF_AZ_SRM_INIT_EN, 1,
2084 FRF_AZ_SRM_NB_SZ, 0);
2085 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2086
2087 /* Wait for SRAM reset to complete */
2088 count = 0;
2089 do {
2090 netif_dbg(efx, hw, efx->net_dev,
2091 "waiting for SRAM reset (attempt %d)...\n", count);
2092
2093 /* SRAM reset is slow; expect around 16ms */
2094 schedule_timeout_uninterruptible(HZ / 50);
2095
2096 /* Check for reset complete */
2097 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2098 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2099 netif_dbg(efx, hw, efx->net_dev,
2100 "SRAM reset complete\n");
2101
2102 return 0;
2103 }
2104 } while (++count < 20); /* wait up to 0.4 sec */
2105
2106 netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
2107 return -ETIMEDOUT;
2108 }
2109
2110 static void falcon_spi_device_init(struct efx_nic *efx,
2111 struct falcon_spi_device *spi_device,
2112 unsigned int device_id, u32 device_type)
2113 {
2114 if (device_type != 0) {
2115 spi_device->device_id = device_id;
2116 spi_device->size =
2117 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2118 spi_device->addr_len =
2119 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2120 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2121 spi_device->addr_len == 1);
2122 spi_device->erase_command =
2123 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2124 spi_device->erase_size =
2125 1 << SPI_DEV_TYPE_FIELD(device_type,
2126 SPI_DEV_TYPE_ERASE_SIZE);
2127 spi_device->block_size =
2128 1 << SPI_DEV_TYPE_FIELD(device_type,
2129 SPI_DEV_TYPE_BLOCK_SIZE);
2130 } else {
2131 spi_device->size = 0;
2132 }
2133 }
2134
2135 /* Extract non-volatile configuration */
2136 static int falcon_probe_nvconfig(struct efx_nic *efx)
2137 {
2138 struct falcon_nic_data *nic_data = efx->nic_data;
2139 struct falcon_nvconfig *nvconfig;
2140 int rc;
2141
2142 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2143 if (!nvconfig)
2144 return -ENOMEM;
2145
2146 rc = falcon_read_nvram(efx, nvconfig);
2147 if (rc)
2148 goto out;
2149
2150 efx->phy_type = nvconfig->board_v2.port0_phy_type;
2151 efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
2152
2153 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2154 falcon_spi_device_init(
2155 efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2156 le32_to_cpu(nvconfig->board_v3
2157 .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
2158 falcon_spi_device_init(
2159 efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2160 le32_to_cpu(nvconfig->board_v3
2161 .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
2162 }
2163
2164 /* Read the MAC addresses */
2165 memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN);
2166
2167 netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
2168 efx->phy_type, efx->mdio.prtad);
2169
2170 rc = falcon_probe_board(efx,
2171 le16_to_cpu(nvconfig->board_v2.board_revision));
2172 out:
2173 kfree(nvconfig);
2174 return rc;
2175 }
2176
2177 static int falcon_dimension_resources(struct efx_nic *efx)
2178 {
2179 efx->rx_dc_base = 0x20000;
2180 efx->tx_dc_base = 0x26000;
2181 return 0;
2182 }
2183
2184 /* Probe all SPI devices on the NIC */
2185 static void falcon_probe_spi_devices(struct efx_nic *efx)
2186 {
2187 struct falcon_nic_data *nic_data = efx->nic_data;
2188 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2189 int boot_dev;
2190
2191 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2192 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2193 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2194
2195 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2196 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2197 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2198 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
2199 boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
2200 "flash" : "EEPROM");
2201 } else {
2202 /* Disable VPD and set clock dividers to safe
2203 * values for initial programming. */
2204 boot_dev = -1;
2205 netif_dbg(efx, probe, efx->net_dev,
2206 "Booted from internal ASIC settings;"
2207 " setting SPI config\n");
2208 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2209 /* 125 MHz / 7 ~= 20 MHz */
2210 FRF_AB_EE_SF_CLOCK_DIV, 7,
2211 /* 125 MHz / 63 ~= 2 MHz */
2212 FRF_AB_EE_EE_CLOCK_DIV, 63);
2213 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2214 }
2215
2216 mutex_init(&nic_data->spi_lock);
2217
2218 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2219 falcon_spi_device_init(efx, &nic_data->spi_flash,
2220 FFE_AB_SPI_DEVICE_FLASH,
2221 default_flash_type);
2222 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2223 falcon_spi_device_init(efx, &nic_data->spi_eeprom,
2224 FFE_AB_SPI_DEVICE_EEPROM,
2225 large_eeprom_type);
2226 }
2227
2228 static unsigned int falcon_a1_mem_map_size(struct efx_nic *efx)
2229 {
2230 return 0x20000;
2231 }
2232
2233 static unsigned int falcon_b0_mem_map_size(struct efx_nic *efx)
2234 {
2235 /* Map everything up to and including the RSS indirection table.
2236 * The PCI core takes care of mapping the MSI-X tables.
2237 */
2238 return FR_BZ_RX_INDIRECTION_TBL +
2239 FR_BZ_RX_INDIRECTION_TBL_STEP * FR_BZ_RX_INDIRECTION_TBL_ROWS;
2240 }
2241
2242 static int falcon_probe_nic(struct efx_nic *efx)
2243 {
2244 struct falcon_nic_data *nic_data;
2245 struct falcon_board *board;
2246 int rc;
2247
2248 /* Allocate storage for hardware specific data */
2249 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2250 if (!nic_data)
2251 return -ENOMEM;
2252 efx->nic_data = nic_data;
2253
2254 rc = -ENODEV;
2255
2256 if (efx_farch_fpga_ver(efx) != 0) {
2257 netif_err(efx, probe, efx->net_dev,
2258 "Falcon FPGA not supported\n");
2259 goto fail1;
2260 }
2261
2262 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2263 efx_oword_t nic_stat;
2264 struct pci_dev *dev;
2265 u8 pci_rev = efx->pci_dev->revision;
2266
2267 if ((pci_rev == 0xff) || (pci_rev == 0)) {
2268 netif_err(efx, probe, efx->net_dev,
2269 "Falcon rev A0 not supported\n");
2270 goto fail1;
2271 }
2272 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2273 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
2274 netif_err(efx, probe, efx->net_dev,
2275 "Falcon rev A1 1G not supported\n");
2276 goto fail1;
2277 }
2278 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2279 netif_err(efx, probe, efx->net_dev,
2280 "Falcon rev A1 PCI-X not supported\n");
2281 goto fail1;
2282 }
2283
2284 dev = pci_dev_get(efx->pci_dev);
2285 while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE,
2286 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1,
2287 dev))) {
2288 if (dev->bus == efx->pci_dev->bus &&
2289 dev->devfn == efx->pci_dev->devfn + 1) {
2290 nic_data->pci_dev2 = dev;
2291 break;
2292 }
2293 }
2294 if (!nic_data->pci_dev2) {
2295 netif_err(efx, probe, efx->net_dev,
2296 "failed to find secondary function\n");
2297 rc = -ENODEV;
2298 goto fail2;
2299 }
2300 }
2301
2302 /* Now we can reset the NIC */
2303 rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
2304 if (rc) {
2305 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
2306 goto fail3;
2307 }
2308
2309 /* Allocate memory for INT_KER */
2310 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
2311 GFP_KERNEL);
2312 if (rc)
2313 goto fail4;
2314 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2315
2316 netif_dbg(efx, probe, efx->net_dev,
2317 "INT_KER at %llx (virt %p phys %llx)\n",
2318 (u64)efx->irq_status.dma_addr,
2319 efx->irq_status.addr,
2320 (u64)virt_to_phys(efx->irq_status.addr));
2321
2322 falcon_probe_spi_devices(efx);
2323
2324 /* Read in the non-volatile configuration */
2325 rc = falcon_probe_nvconfig(efx);
2326 if (rc) {
2327 if (rc == -EINVAL)
2328 netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
2329 goto fail5;
2330 }
2331
2332 efx->max_channels = (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? 4 :
2333 EFX_MAX_CHANNELS);
2334 efx->timer_quantum_ns = 4968; /* 621 cycles */
2335
2336 /* Initialise I2C adapter */
2337 board = falcon_board(efx);
2338 board->i2c_adap.owner = THIS_MODULE;
2339 board->i2c_data = falcon_i2c_bit_operations;
2340 board->i2c_data.data = efx;
2341 board->i2c_adap.algo_data = &board->i2c_data;
2342 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2343 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2344 sizeof(board->i2c_adap.name));
2345 rc = i2c_bit_add_bus(&board->i2c_adap);
2346 if (rc)
2347 goto fail5;
2348
2349 rc = falcon_board(efx)->type->init(efx);
2350 if (rc) {
2351 netif_err(efx, probe, efx->net_dev,
2352 "failed to initialise board\n");
2353 goto fail6;
2354 }
2355
2356 nic_data->stats_disable_count = 1;
2357 setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
2358 (unsigned long)efx);
2359
2360 return 0;
2361
2362 fail6:
2363 i2c_del_adapter(&board->i2c_adap);
2364 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2365 fail5:
2366 efx_nic_free_buffer(efx, &efx->irq_status);
2367 fail4:
2368 fail3:
2369 if (nic_data->pci_dev2) {
2370 pci_dev_put(nic_data->pci_dev2);
2371 nic_data->pci_dev2 = NULL;
2372 }
2373 fail2:
2374 fail1:
2375 kfree(efx->nic_data);
2376 return rc;
2377 }
2378
2379 static void falcon_init_rx_cfg(struct efx_nic *efx)
2380 {
2381 /* RX control FIFO thresholds (32 entries) */
2382 const unsigned ctrl_xon_thr = 20;
2383 const unsigned ctrl_xoff_thr = 25;
2384 efx_oword_t reg;
2385
2386 efx_reado(efx, &reg, FR_AZ_RX_CFG);
2387 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2388 /* Data FIFO size is 5.5K. The RX DMA engine only
2389 * supports scattering for user-mode queues, but will
2390 * split DMA writes at intervals of RX_USR_BUF_SIZE
2391 * (32-byte units) even for kernel-mode queues. We
2392 * set it to be so large that that never happens.
2393 */
2394 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2395 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2396 (3 * 4096) >> 5);
2397 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);
2398 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);
2399 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2400 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2401 } else {
2402 /* Data FIFO size is 80K; register fields moved */
2403 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2404 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2405 EFX_RX_USR_BUF_SIZE >> 5);
2406 /* Send XON and XOFF at ~3 * max MTU away from empty/full */
2407 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);
2408 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);
2409 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2410 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2411 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2412
2413 /* Enable hash insertion. This is broken for the
2414 * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
2415 * IPv4 hashes. */
2416 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
2417 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
2418 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
2419 }
2420 /* Always enable XOFF signal from RX FIFO. We enable
2421 * or disable transmission of pause frames at the MAC. */
2422 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
2423 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2424 }
2425
2426 /* This call performs hardware-specific global initialisation, such as
2427 * defining the descriptor cache sizes and number of RSS channels.
2428 * It does not set up any buffers, descriptor rings or event queues.
2429 */
2430 static int falcon_init_nic(struct efx_nic *efx)
2431 {
2432 efx_oword_t temp;
2433 int rc;
2434
2435 /* Use on-chip SRAM */
2436 efx_reado(efx, &temp, FR_AB_NIC_STAT);
2437 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2438 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2439
2440 rc = falcon_reset_sram(efx);
2441 if (rc)
2442 return rc;
2443
2444 /* Clear the parity enables on the TX data fifos as
2445 * they produce false parity errors because of timing issues
2446 */
2447 if (EFX_WORKAROUND_5129(efx)) {
2448 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
2449 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
2450 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
2451 }
2452
2453 if (EFX_WORKAROUND_7244(efx)) {
2454 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
2455 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
2456 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
2457 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
2458 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
2459 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
2460 }
2461
2462 /* XXX This is documented only for Falcon A0/A1 */
2463 /* Setup RX. Wait for descriptor is broken and must
2464 * be disabled. RXDP recovery shouldn't be needed, but is.
2465 */
2466 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
2467 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
2468 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
2469 if (EFX_WORKAROUND_5583(efx))
2470 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
2471 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
2472
2473 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2474 * descriptors (which is bad).
2475 */
2476 efx_reado(efx, &temp, FR_AZ_TX_CFG);
2477 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
2478 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
2479
2480 falcon_init_rx_cfg(efx);
2481
2482 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2483 /* Set hash key for IPv4 */
2484 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
2485 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
2486
2487 /* Set destination of both TX and RX Flush events */
2488 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
2489 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
2490 }
2491
2492 efx_farch_init_common(efx);
2493
2494 return 0;
2495 }
2496
2497 static void falcon_remove_nic(struct efx_nic *efx)
2498 {
2499 struct falcon_nic_data *nic_data = efx->nic_data;
2500 struct falcon_board *board = falcon_board(efx);
2501
2502 board->type->fini(efx);
2503
2504 /* Remove I2C adapter and clear it in preparation for a retry */
2505 i2c_del_adapter(&board->i2c_adap);
2506 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2507
2508 efx_nic_free_buffer(efx, &efx->irq_status);
2509
2510 __falcon_reset_hw(efx, RESET_TYPE_ALL);
2511
2512 /* Release the second function after the reset */
2513 if (nic_data->pci_dev2) {
2514 pci_dev_put(nic_data->pci_dev2);
2515 nic_data->pci_dev2 = NULL;
2516 }
2517
2518 /* Tear down the private nic state */
2519 kfree(efx->nic_data);
2520 efx->nic_data = NULL;
2521 }
2522
2523 static size_t falcon_describe_nic_stats(struct efx_nic *efx, u8 *names)
2524 {
2525 return efx_nic_describe_stats(falcon_stat_desc, FALCON_STAT_COUNT,
2526 falcon_stat_mask, names);
2527 }
2528
2529 static size_t falcon_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
2530 struct rtnl_link_stats64 *core_stats)
2531 {
2532 struct falcon_nic_data *nic_data = efx->nic_data;
2533 u64 *stats = nic_data->stats;
2534 efx_oword_t cnt;
2535
2536 if (!nic_data->stats_disable_count) {
2537 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
2538 stats[FALCON_STAT_rx_nodesc_drop_cnt] +=
2539 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
2540
2541 if (nic_data->stats_pending &&
2542 FALCON_XMAC_STATS_DMA_FLAG(efx)) {
2543 nic_data->stats_pending = false;
2544 rmb(); /* read the done flag before the stats */
2545 efx_nic_update_stats(
2546 falcon_stat_desc, FALCON_STAT_COUNT,
2547 falcon_stat_mask,
2548 stats, efx->stats_buffer.addr, true);
2549 }
2550
2551 /* Update derived statistic */
2552 efx_update_diff_stat(&stats[FALCON_STAT_rx_bad_bytes],
2553 stats[FALCON_STAT_rx_bytes] -
2554 stats[FALCON_STAT_rx_good_bytes] -
2555 stats[FALCON_STAT_rx_control] * 64);
2556 }
2557
2558 if (full_stats)
2559 memcpy(full_stats, stats, sizeof(u64) * FALCON_STAT_COUNT);
2560
2561 if (core_stats) {
2562 core_stats->rx_packets = stats[FALCON_STAT_rx_packets];
2563 core_stats->tx_packets = stats[FALCON_STAT_tx_packets];
2564 core_stats->rx_bytes = stats[FALCON_STAT_rx_bytes];
2565 core_stats->tx_bytes = stats[FALCON_STAT_tx_bytes];
2566 core_stats->rx_dropped = stats[FALCON_STAT_rx_nodesc_drop_cnt];
2567 core_stats->multicast = stats[FALCON_STAT_rx_multicast];
2568 core_stats->rx_length_errors =
2569 stats[FALCON_STAT_rx_gtjumbo] +
2570 stats[FALCON_STAT_rx_length_error];
2571 core_stats->rx_crc_errors = stats[FALCON_STAT_rx_bad];
2572 core_stats->rx_frame_errors = stats[FALCON_STAT_rx_align_error];
2573 core_stats->rx_fifo_errors = stats[FALCON_STAT_rx_overflow];
2574
2575 core_stats->rx_errors = (core_stats->rx_length_errors +
2576 core_stats->rx_crc_errors +
2577 core_stats->rx_frame_errors +
2578 stats[FALCON_STAT_rx_symbol_error]);
2579 }
2580
2581 return FALCON_STAT_COUNT;
2582 }
2583
2584 void falcon_start_nic_stats(struct efx_nic *efx)
2585 {
2586 struct falcon_nic_data *nic_data = efx->nic_data;
2587
2588 spin_lock_bh(&efx->stats_lock);
2589 if (--nic_data->stats_disable_count == 0)
2590 falcon_stats_request(efx);
2591 spin_unlock_bh(&efx->stats_lock);
2592 }
2593
2594 void falcon_stop_nic_stats(struct efx_nic *efx)
2595 {
2596 struct falcon_nic_data *nic_data = efx->nic_data;
2597 int i;
2598
2599 might_sleep();
2600
2601 spin_lock_bh(&efx->stats_lock);
2602 ++nic_data->stats_disable_count;
2603 spin_unlock_bh(&efx->stats_lock);
2604
2605 del_timer_sync(&nic_data->stats_timer);
2606
2607 /* Wait enough time for the most recent transfer to
2608 * complete. */
2609 for (i = 0; i < 4 && nic_data->stats_pending; i++) {
2610 if (FALCON_XMAC_STATS_DMA_FLAG(efx))
2611 break;
2612 msleep(1);
2613 }
2614
2615 spin_lock_bh(&efx->stats_lock);
2616 falcon_stats_complete(efx);
2617 spin_unlock_bh(&efx->stats_lock);
2618 }
2619
2620 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
2621 {
2622 falcon_board(efx)->type->set_id_led(efx, mode);
2623 }
2624
2625 /**************************************************************************
2626 *
2627 * Wake on LAN
2628 *
2629 **************************************************************************
2630 */
2631
2632 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2633 {
2634 wol->supported = 0;
2635 wol->wolopts = 0;
2636 memset(&wol->sopass, 0, sizeof(wol->sopass));
2637 }
2638
2639 static int falcon_set_wol(struct efx_nic *efx, u32 type)
2640 {
2641 if (type != 0)
2642 return -EINVAL;
2643 return 0;
2644 }
2645
2646 /**************************************************************************
2647 *
2648 * Revision-dependent attributes used by efx.c and nic.c
2649 *
2650 **************************************************************************
2651 */
2652
2653 const struct efx_nic_type falcon_a1_nic_type = {
2654 .mem_map_size = falcon_a1_mem_map_size,
2655 .probe = falcon_probe_nic,
2656 .remove = falcon_remove_nic,
2657 .init = falcon_init_nic,
2658 .dimension_resources = falcon_dimension_resources,
2659 .fini = falcon_irq_ack_a1,
2660 .monitor = falcon_monitor,
2661 .map_reset_reason = falcon_map_reset_reason,
2662 .map_reset_flags = falcon_map_reset_flags,
2663 .reset = falcon_reset_hw,
2664 .probe_port = falcon_probe_port,
2665 .remove_port = falcon_remove_port,
2666 .handle_global_event = falcon_handle_global_event,
2667 .fini_dmaq = efx_farch_fini_dmaq,
2668 .prepare_flush = falcon_prepare_flush,
2669 .finish_flush = efx_port_dummy_op_void,
2670 .describe_stats = falcon_describe_nic_stats,
2671 .update_stats = falcon_update_nic_stats,
2672 .start_stats = falcon_start_nic_stats,
2673 .stop_stats = falcon_stop_nic_stats,
2674 .set_id_led = falcon_set_id_led,
2675 .push_irq_moderation = falcon_push_irq_moderation,
2676 .reconfigure_port = falcon_reconfigure_port,
2677 .prepare_enable_fc_tx = falcon_a1_prepare_enable_fc_tx,
2678 .reconfigure_mac = falcon_reconfigure_xmac,
2679 .check_mac_fault = falcon_xmac_check_fault,
2680 .get_wol = falcon_get_wol,
2681 .set_wol = falcon_set_wol,
2682 .resume_wol = efx_port_dummy_op_void,
2683 .test_nvram = falcon_test_nvram,
2684 .irq_enable_master = efx_farch_irq_enable_master,
2685 .irq_test_generate = efx_farch_irq_test_generate,
2686 .irq_disable_non_ev = efx_farch_irq_disable_master,
2687 .irq_handle_msi = efx_farch_msi_interrupt,
2688 .irq_handle_legacy = falcon_legacy_interrupt_a1,
2689 .tx_probe = efx_farch_tx_probe,
2690 .tx_init = efx_farch_tx_init,
2691 .tx_remove = efx_farch_tx_remove,
2692 .tx_write = efx_farch_tx_write,
2693 .rx_push_indir_table = efx_farch_rx_push_indir_table,
2694 .rx_probe = efx_farch_rx_probe,
2695 .rx_init = efx_farch_rx_init,
2696 .rx_remove = efx_farch_rx_remove,
2697 .rx_write = efx_farch_rx_write,
2698 .rx_defer_refill = efx_farch_rx_defer_refill,
2699 .ev_probe = efx_farch_ev_probe,
2700 .ev_init = efx_farch_ev_init,
2701 .ev_fini = efx_farch_ev_fini,
2702 .ev_remove = efx_farch_ev_remove,
2703 .ev_process = efx_farch_ev_process,
2704 .ev_read_ack = efx_farch_ev_read_ack,
2705 .ev_test_generate = efx_farch_ev_test_generate,
2706
2707 /* We don't expose the filter table on Falcon A1 as it is not
2708 * mapped into function 0, but these implementations still
2709 * work with a degenerate case of all tables set to size 0.
2710 */
2711 .filter_table_probe = efx_farch_filter_table_probe,
2712 .filter_table_restore = efx_farch_filter_table_restore,
2713 .filter_table_remove = efx_farch_filter_table_remove,
2714 .filter_insert = efx_farch_filter_insert,
2715 .filter_remove_safe = efx_farch_filter_remove_safe,
2716 .filter_get_safe = efx_farch_filter_get_safe,
2717 .filter_clear_rx = efx_farch_filter_clear_rx,
2718 .filter_count_rx_used = efx_farch_filter_count_rx_used,
2719 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
2720 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
2721
2722 #ifdef CONFIG_SFC_MTD
2723 .mtd_probe = falcon_mtd_probe,
2724 .mtd_rename = falcon_mtd_rename,
2725 .mtd_read = falcon_mtd_read,
2726 .mtd_erase = falcon_mtd_erase,
2727 .mtd_write = falcon_mtd_write,
2728 .mtd_sync = falcon_mtd_sync,
2729 #endif
2730
2731 .revision = EFX_REV_FALCON_A1,
2732 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
2733 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
2734 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
2735 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
2736 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
2737 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
2738 .rx_buffer_padding = 0x24,
2739 .can_rx_scatter = false,
2740 .max_interrupt_mode = EFX_INT_MODE_MSI,
2741 .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
2742 .offload_features = NETIF_F_IP_CSUM,
2743 .mcdi_max_ver = -1,
2744 };
2745
2746 const struct efx_nic_type falcon_b0_nic_type = {
2747 .mem_map_size = falcon_b0_mem_map_size,
2748 .probe = falcon_probe_nic,
2749 .remove = falcon_remove_nic,
2750 .init = falcon_init_nic,
2751 .dimension_resources = falcon_dimension_resources,
2752 .fini = efx_port_dummy_op_void,
2753 .monitor = falcon_monitor,
2754 .map_reset_reason = falcon_map_reset_reason,
2755 .map_reset_flags = falcon_map_reset_flags,
2756 .reset = falcon_reset_hw,
2757 .probe_port = falcon_probe_port,
2758 .remove_port = falcon_remove_port,
2759 .handle_global_event = falcon_handle_global_event,
2760 .fini_dmaq = efx_farch_fini_dmaq,
2761 .prepare_flush = falcon_prepare_flush,
2762 .finish_flush = efx_port_dummy_op_void,
2763 .describe_stats = falcon_describe_nic_stats,
2764 .update_stats = falcon_update_nic_stats,
2765 .start_stats = falcon_start_nic_stats,
2766 .stop_stats = falcon_stop_nic_stats,
2767 .set_id_led = falcon_set_id_led,
2768 .push_irq_moderation = falcon_push_irq_moderation,
2769 .reconfigure_port = falcon_reconfigure_port,
2770 .prepare_enable_fc_tx = falcon_b0_prepare_enable_fc_tx,
2771 .reconfigure_mac = falcon_reconfigure_xmac,
2772 .check_mac_fault = falcon_xmac_check_fault,
2773 .get_wol = falcon_get_wol,
2774 .set_wol = falcon_set_wol,
2775 .resume_wol = efx_port_dummy_op_void,
2776 .test_chip = falcon_b0_test_chip,
2777 .test_nvram = falcon_test_nvram,
2778 .irq_enable_master = efx_farch_irq_enable_master,
2779 .irq_test_generate = efx_farch_irq_test_generate,
2780 .irq_disable_non_ev = efx_farch_irq_disable_master,
2781 .irq_handle_msi = efx_farch_msi_interrupt,
2782 .irq_handle_legacy = efx_farch_legacy_interrupt,
2783 .tx_probe = efx_farch_tx_probe,
2784 .tx_init = efx_farch_tx_init,
2785 .tx_remove = efx_farch_tx_remove,
2786 .tx_write = efx_farch_tx_write,
2787 .rx_push_indir_table = efx_farch_rx_push_indir_table,
2788 .rx_probe = efx_farch_rx_probe,
2789 .rx_init = efx_farch_rx_init,
2790 .rx_remove = efx_farch_rx_remove,
2791 .rx_write = efx_farch_rx_write,
2792 .rx_defer_refill = efx_farch_rx_defer_refill,
2793 .ev_probe = efx_farch_ev_probe,
2794 .ev_init = efx_farch_ev_init,
2795 .ev_fini = efx_farch_ev_fini,
2796 .ev_remove = efx_farch_ev_remove,
2797 .ev_process = efx_farch_ev_process,
2798 .ev_read_ack = efx_farch_ev_read_ack,
2799 .ev_test_generate = efx_farch_ev_test_generate,
2800 .filter_table_probe = efx_farch_filter_table_probe,
2801 .filter_table_restore = efx_farch_filter_table_restore,
2802 .filter_table_remove = efx_farch_filter_table_remove,
2803 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
2804 .filter_insert = efx_farch_filter_insert,
2805 .filter_remove_safe = efx_farch_filter_remove_safe,
2806 .filter_get_safe = efx_farch_filter_get_safe,
2807 .filter_clear_rx = efx_farch_filter_clear_rx,
2808 .filter_count_rx_used = efx_farch_filter_count_rx_used,
2809 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
2810 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
2811 #ifdef CONFIG_RFS_ACCEL
2812 .filter_rfs_insert = efx_farch_filter_rfs_insert,
2813 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
2814 #endif
2815 #ifdef CONFIG_SFC_MTD
2816 .mtd_probe = falcon_mtd_probe,
2817 .mtd_rename = falcon_mtd_rename,
2818 .mtd_read = falcon_mtd_read,
2819 .mtd_erase = falcon_mtd_erase,
2820 .mtd_write = falcon_mtd_write,
2821 .mtd_sync = falcon_mtd_sync,
2822 #endif
2823
2824 .revision = EFX_REV_FALCON_B0,
2825 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
2826 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
2827 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
2828 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
2829 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
2830 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
2831 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
2832 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
2833 .rx_buffer_padding = 0,
2834 .can_rx_scatter = true,
2835 .max_interrupt_mode = EFX_INT_MODE_MSIX,
2836 .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
2837 .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
2838 .mcdi_max_ver = -1,
2839 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
2840 };
2841
Linux kernel - Deliverables
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