drivers/net/ethernet/sfc/io.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2010 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #ifndef EFX_IO_H
  12 #define EFX_IO_H
  13
  14 #include <linux/io.h>
  15 #include <linux/spinlock.h>
  16
  17 /**************************************************************************
  18  *
  19  * NIC register I/O
  20  *
  21  **************************************************************************
  22  *
  23  * Notes on locking strategy:
  24  *
  25  * Many CSRs are very wide and cannot be read or written atomically.
  26  * Writes from the host are buffered by the Bus Interface Unit (BIU)
  27  * up to 128 bits.  Whenever the host writes part of such a register,
  28  * the BIU collects the written value and does not write to the
  29  * underlying register until all 4 dwords have been written.  A
  30  * similar buffering scheme applies to host access to the NIC's 64-bit
  31  * SRAM.
  32  *
  33  * Writes to different CSRs and 64-bit SRAM words must be serialised,
  34  * since interleaved access can result in lost writes.  We use
  35  * efx_nic::biu_lock for this.
  36  *
  37  * We also serialise reads from 128-bit CSRs and SRAM with the same
  38  * spinlock.  This may not be necessary, but it doesn't really matter
  39  * as there are no such reads on the fast path.
  40  *
  41  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
  42  * 128-bit but are special-cased in the BIU to avoid the need for
  43  * locking in the host:
  44  *
  45  * - They are write-only.
  46  * - The semantics of writing to these registers are such that
  47  *   replacing the low 96 bits with zero does not affect functionality.
  48  * - If the host writes to the last dword address of such a register
  49  *   (i.e. the high 32 bits) the underlying register will always be
  50  *   written.  If the collector and the current write together do not
  51  *   provide values for all 128 bits of the register, the low 96 bits
  52  *   will be written as zero.
  53  * - If the host writes to the address of any other part of such a
  54  *   register while the collector already holds values for some other
  55  *   register, the write is discarded and the collector maintains its
  56  *   current state.
  57  */
  58
  59 #if BITS_PER_LONG == 64
  60 #define EFX_USE_QWORD_IO 1
  61 #endif
  62
  63 #ifdef EFX_USE_QWORD_IO
  64 static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
  65                                   unsigned int reg)
  66 {
  67         __raw_writeq((__force u64)value, efx->membase + reg);
  68 }
  69 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
  70 {
  71         return (__force __le64)__raw_readq(efx->membase + reg);
  72 }
  73 #endif
  74
  75 static inline void _efx_writed(struct efx_nic *efx, __le32 value,
  76                                   unsigned int reg)
  77 {
  78         __raw_writel((__force u32)value, efx->membase + reg);
  79 }
  80 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
  81 {
  82         return (__force __le32)__raw_readl(efx->membase + reg);
  83 }
  84
  85 /* Write a normal 128-bit CSR, locking as appropriate. */
  86 static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
  87                               unsigned int reg)
  88 {
  89         unsigned long flags __attribute__ ((unused));
  90
  91         netif_vdbg(efx, hw, efx->net_dev,
  92                    "writing register %x with " EFX_OWORD_FMT "\n", reg,
  93                    EFX_OWORD_VAL(*value));
  94
  95         spin_lock_irqsave(&efx->biu_lock, flags);
  96 #ifdef EFX_USE_QWORD_IO
  97         _efx_writeq(efx, value->u64[0], reg + 0);
  98         _efx_writeq(efx, value->u64[1], reg + 8);
  99 #else
 100         _efx_writed(efx, value->u32[0], reg + 0);
 101         _efx_writed(efx, value->u32[1], reg + 4);
 102         _efx_writed(efx, value->u32[2], reg + 8);
 103         _efx_writed(efx, value->u32[3], reg + 12);
 104 #endif
 105         mmiowb();
 106         spin_unlock_irqrestore(&efx->biu_lock, flags);
 107 }
 108
 109 /* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
 110 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
 111                                    efx_qword_t *value, unsigned int index)
 112 {
 113         unsigned int addr = index * sizeof(*value);
 114         unsigned long flags __attribute__ ((unused));
 115
 116         netif_vdbg(efx, hw, efx->net_dev,
 117                    "writing SRAM address %x with " EFX_QWORD_FMT "\n",
 118                    addr, EFX_QWORD_VAL(*value));
 119
 120         spin_lock_irqsave(&efx->biu_lock, flags);
 121 #ifdef EFX_USE_QWORD_IO
 122         __raw_writeq((__force u64)value->u64[0], membase + addr);
 123 #else
 124         __raw_writel((__force u32)value->u32[0], membase + addr);
 125         __raw_writel((__force u32)value->u32[1], membase + addr + 4);
 126 #endif
 127         mmiowb();
 128         spin_unlock_irqrestore(&efx->biu_lock, flags);
 129 }
 130
 131 /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
 132 static inline void efx_writed(struct efx_nic *efx, efx_dword_t *value,
 133                               unsigned int reg)
 134 {
 135         netif_vdbg(efx, hw, efx->net_dev,
 136                    "writing register %x with "EFX_DWORD_FMT"\n",
 137                    reg, EFX_DWORD_VAL(*value));
 138
 139         /* No lock required */
 140         _efx_writed(efx, value->u32[0], reg);
 141 }
 142
 143 /* Read a 128-bit CSR, locking as appropriate. */
 144 static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
 145                              unsigned int reg)
 146 {
 147         unsigned long flags __attribute__ ((unused));
 148
 149         spin_lock_irqsave(&efx->biu_lock, flags);
 150         value->u32[0] = _efx_readd(efx, reg + 0);
 151         value->u32[1] = _efx_readd(efx, reg + 4);
 152         value->u32[2] = _efx_readd(efx, reg + 8);
 153         value->u32[3] = _efx_readd(efx, reg + 12);
 154         spin_unlock_irqrestore(&efx->biu_lock, flags);
 155
 156         netif_vdbg(efx, hw, efx->net_dev,
 157                    "read from register %x, got " EFX_OWORD_FMT "\n", reg,
 158                    EFX_OWORD_VAL(*value));
 159 }
 160
 161 /* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
 162 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
 163                                   efx_qword_t *value, unsigned int index)
 164 {
 165         unsigned int addr = index * sizeof(*value);
 166         unsigned long flags __attribute__ ((unused));
 167
 168         spin_lock_irqsave(&efx->biu_lock, flags);
 169 #ifdef EFX_USE_QWORD_IO
 170         value->u64[0] = (__force __le64)__raw_readq(membase + addr);
 171 #else
 172         value->u32[0] = (__force __le32)__raw_readl(membase + addr);
 173         value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
 174 #endif
 175         spin_unlock_irqrestore(&efx->biu_lock, flags);
 176
 177         netif_vdbg(efx, hw, efx->net_dev,
 178                    "read from SRAM address %x, got "EFX_QWORD_FMT"\n",
 179                    addr, EFX_QWORD_VAL(*value));
 180 }
 181
 182 /* Read a 32-bit CSR or SRAM */
 183 static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
 184                                 unsigned int reg)
 185 {
 186         value->u32[0] = _efx_readd(efx, reg);
 187         netif_vdbg(efx, hw, efx->net_dev,
 188                    "read from register %x, got "EFX_DWORD_FMT"\n",
 189                    reg, EFX_DWORD_VAL(*value));
 190 }
 191
 192 /* Write a 128-bit CSR forming part of a table */
 193 static inline void efx_writeo_table(struct efx_nic *efx, efx_oword_t *value,
 194                                       unsigned int reg, unsigned int index)
 195 {
 196         efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
 197 }
 198
 199 /* Read a 128-bit CSR forming part of a table */
 200 static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
 201                                      unsigned int reg, unsigned int index)
 202 {
 203         efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
 204 }
 205
 206 /* Page-mapped register block size */
 207 #define EFX_PAGE_BLOCK_SIZE 0x2000
 208
 209 /* Calculate offset to page-mapped register block */
 210 #define EFX_PAGED_REG(page, reg) \
 211         ((page) * EFX_PAGE_BLOCK_SIZE + (reg))
 212
 213 /* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
 214 static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
 215                                     unsigned int reg, unsigned int page)
 216 {
 217         reg = EFX_PAGED_REG(page, reg);
 218
 219         netif_vdbg(efx, hw, efx->net_dev,
 220                    "writing register %x with " EFX_OWORD_FMT "\n", reg,
 221                    EFX_OWORD_VAL(*value));
 222
 223 #ifdef EFX_USE_QWORD_IO
 224         _efx_writeq(efx, value->u64[0], reg + 0);
 225         _efx_writeq(efx, value->u64[1], reg + 8);
 226 #else
 227         _efx_writed(efx, value->u32[0], reg + 0);
 228         _efx_writed(efx, value->u32[1], reg + 4);
 229         _efx_writed(efx, value->u32[2], reg + 8);
 230         _efx_writed(efx, value->u32[3], reg + 12);
 231 #endif
 232 }
 233 #define efx_writeo_page(efx, value, reg, page)                          \
 234         _efx_writeo_page(efx, value,                                    \
 235                          reg +                                          \
 236                          BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
 237                          page)
 238
 239 /* Write a page-mapped 32-bit CSR (EVQ_RPTR or the high bits of
 240  * RX_DESC_UPD or TX_DESC_UPD)
 241  */
 242 static inline void _efx_writed_page(struct efx_nic *efx, efx_dword_t *value,
 243                                     unsigned int reg, unsigned int page)
 244 {
 245         efx_writed(efx, value, EFX_PAGED_REG(page, reg));
 246 }
 247 #define efx_writed_page(efx, value, reg, page)                          \
 248         _efx_writed_page(efx, value,                                    \
 249                          reg +                                          \
 250                          BUILD_BUG_ON_ZERO((reg) != 0x400 && (reg) != 0x83c \
 251                                            && (reg) != 0xa1c),          \
 252                          page)
 253
 254 /* Write TIMER_COMMAND.  This is a page-mapped 32-bit CSR, but a bug
 255  * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
 256  * collector register.
 257  */
 258 static inline void _efx_writed_page_locked(struct efx_nic *efx,
 259                                            efx_dword_t *value,
 260                                            unsigned int reg,
 261                                            unsigned int page)
 262 {
 263         unsigned long flags __attribute__ ((unused));
 264
 265         if (page == 0) {
 266                 spin_lock_irqsave(&efx->biu_lock, flags);
 267                 efx_writed(efx, value, EFX_PAGED_REG(page, reg));
 268                 spin_unlock_irqrestore(&efx->biu_lock, flags);
 269         } else {
 270                 efx_writed(efx, value, EFX_PAGED_REG(page, reg));
 271         }
 272 }
 273 #define efx_writed_page_locked(efx, value, reg, page)                   \
 274         _efx_writed_page_locked(efx, value,                             \
 275                                 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
 276                                 page)
 277
 278 #endif /* EFX_IO_H */