1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2011 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_vlan.h>
20 #include <linux/timer.h>
21 #include <linux/mdio.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/device.h>
25 #include <linux/highmem.h>
26 #include <linux/workqueue.h>
27 #include <linux/mutex.h>
28 #include <linux/vmalloc.h>
29 #include <linux/i2c.h>
34 /**************************************************************************
38 **************************************************************************/
40 #define EFX_DRIVER_VERSION "3.1"
43 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
44 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
46 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
47 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
50 /**************************************************************************
54 **************************************************************************/
56 #define EFX_MAX_CHANNELS 32U
57 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
58 #define EFX_EXTRA_CHANNEL_IOV 0
59 #define EFX_MAX_EXTRA_CHANNELS 1U
61 /* Checksum generation is a per-queue option in hardware, so each
62 * queue visible to the networking core is backed by two hardware TX
64 #define EFX_MAX_TX_TC 2
65 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
66 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
67 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
68 #define EFX_TXQ_TYPES 4
69 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
72 * struct efx_special_buffer - An Efx special buffer
73 * @addr: CPU base address of the buffer
74 * @dma_addr: DMA base address of the buffer
75 * @len: Buffer length, in bytes
76 * @index: Buffer index within controller;s buffer table
77 * @entries: Number of buffer table entries
79 * Special buffers are used for the event queues and the TX and RX
80 * descriptor queues for each channel. They are *not* used for the
81 * actual transmit and receive buffers.
83 struct efx_special_buffer
{
92 * struct efx_tx_buffer - An Efx TX buffer
93 * @skb: The associated socket buffer.
94 * Set only on the final fragment of a packet; %NULL for all other
95 * fragments. When this fragment completes, then we can free this
97 * @tsoh: The associated TSO header structure, or %NULL if this
98 * buffer is not a TSO header.
99 * @dma_addr: DMA address of the fragment.
100 * @len: Length of this fragment.
101 * This field is zero when the queue slot is empty.
102 * @continuation: True if this fragment is not the end of a packet.
103 * @unmap_single: True if pci_unmap_single should be used.
104 * @unmap_len: Length of this fragment to unmap
106 struct efx_tx_buffer
{
107 const struct sk_buff
*skb
;
108 struct efx_tso_header
*tsoh
;
113 unsigned short unmap_len
;
117 * struct efx_tx_queue - An Efx TX queue
119 * This is a ring buffer of TX fragments.
120 * Since the TX completion path always executes on the same
121 * CPU and the xmit path can operate on different CPUs,
122 * performance is increased by ensuring that the completion
123 * path and the xmit path operate on different cache lines.
124 * This is particularly important if the xmit path is always
125 * executing on one CPU which is different from the completion
126 * path. There is also a cache line for members which are
127 * read but not written on the fast path.
129 * @efx: The associated Efx NIC
130 * @queue: DMA queue number
131 * @channel: The associated channel
132 * @core_txq: The networking core TX queue structure
133 * @buffer: The software buffer ring
134 * @txd: The hardware descriptor ring
135 * @ptr_mask: The size of the ring minus 1.
136 * @initialised: Has hardware queue been initialised?
137 * @read_count: Current read pointer.
138 * This is the number of buffers that have been removed from both rings.
139 * @old_write_count: The value of @write_count when last checked.
140 * This is here for performance reasons. The xmit path will
141 * only get the up-to-date value of @write_count if this
142 * variable indicates that the queue is empty. This is to
143 * avoid cache-line ping-pong between the xmit path and the
145 * @insert_count: Current insert pointer
146 * This is the number of buffers that have been added to the
148 * @write_count: Current write pointer
149 * This is the number of buffers that have been added to the
151 * @old_read_count: The value of read_count when last checked.
152 * This is here for performance reasons. The xmit path will
153 * only get the up-to-date value of read_count if this
154 * variable indicates that the queue is full. This is to
155 * avoid cache-line ping-pong between the xmit path and the
157 * @tso_headers_free: A list of TSO headers allocated for this TX queue
158 * that are not in use, and so available for new TSO sends. The list
159 * is protected by the TX queue lock.
160 * @tso_bursts: Number of times TSO xmit invoked by kernel
161 * @tso_long_headers: Number of packets with headers too long for standard
163 * @tso_packets: Number of packets via the TSO xmit path
164 * @pushes: Number of times the TX push feature has been used
165 * @empty_read_count: If the completion path has seen the queue as empty
166 * and the transmission path has not yet checked this, the value of
167 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
169 struct efx_tx_queue
{
170 /* Members which don't change on the fast path */
171 struct efx_nic
*efx ____cacheline_aligned_in_smp
;
173 struct efx_channel
*channel
;
174 struct netdev_queue
*core_txq
;
175 struct efx_tx_buffer
*buffer
;
176 struct efx_special_buffer txd
;
177 unsigned int ptr_mask
;
180 /* Members used mainly on the completion path */
181 unsigned int read_count ____cacheline_aligned_in_smp
;
182 unsigned int old_write_count
;
184 /* Members used only on the xmit path */
185 unsigned int insert_count ____cacheline_aligned_in_smp
;
186 unsigned int write_count
;
187 unsigned int old_read_count
;
188 struct efx_tso_header
*tso_headers_free
;
189 unsigned int tso_bursts
;
190 unsigned int tso_long_headers
;
191 unsigned int tso_packets
;
194 /* Members shared between paths and sometimes updated */
195 unsigned int empty_read_count ____cacheline_aligned_in_smp
;
196 #define EFX_EMPTY_COUNT_VALID 0x80000000
200 * struct efx_rx_buffer - An Efx RX data buffer
201 * @dma_addr: DMA base address of the buffer
202 * @skb: The associated socket buffer. Valid iff !(@flags & %EFX_RX_BUF_PAGE).
203 * Will be %NULL if the buffer slot is currently free.
204 * @page: The associated page buffer. Valif iff @flags & %EFX_RX_BUF_PAGE.
205 * Will be %NULL if the buffer slot is currently free.
206 * @len: Buffer length, in bytes.
207 * @flags: Flags for buffer and packet state.
209 struct efx_rx_buffer
{
218 #define EFX_RX_BUF_PAGE 0x0001
219 #define EFX_RX_PKT_CSUMMED 0x0002
220 #define EFX_RX_PKT_DISCARD 0x0004
223 * struct efx_rx_page_state - Page-based rx buffer state
225 * Inserted at the start of every page allocated for receive buffers.
226 * Used to facilitate sharing dma mappings between recycled rx buffers
227 * and those passed up to the kernel.
229 * @refcnt: Number of struct efx_rx_buffer's referencing this page.
230 * When refcnt falls to zero, the page is unmapped for dma
231 * @dma_addr: The dma address of this page.
233 struct efx_rx_page_state
{
237 unsigned int __pad
[0] ____cacheline_aligned
;
241 * struct efx_rx_queue - An Efx RX queue
242 * @efx: The associated Efx NIC
243 * @buffer: The software buffer ring
244 * @rxd: The hardware descriptor ring
245 * @ptr_mask: The size of the ring minus 1.
246 * @enabled: Receive queue enabled indicator.
247 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
248 * @rxq_flush_pending.
249 * @added_count: Number of buffers added to the receive queue.
250 * @notified_count: Number of buffers given to NIC (<= @added_count).
251 * @removed_count: Number of buffers removed from the receive queue.
252 * @max_fill: RX descriptor maximum fill level (<= ring size)
253 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
255 * @fast_fill_limit: The level to which a fast fill will fill
256 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
257 * @min_fill: RX descriptor minimum non-zero fill level.
258 * This records the minimum fill level observed when a ring
259 * refill was triggered.
260 * @alloc_page_count: RX allocation strategy counter.
261 * @alloc_skb_count: RX allocation strategy counter.
262 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
264 struct efx_rx_queue
{
266 struct efx_rx_buffer
*buffer
;
267 struct efx_special_buffer rxd
;
268 unsigned int ptr_mask
;
275 unsigned int max_fill
;
276 unsigned int fast_fill_trigger
;
277 unsigned int fast_fill_limit
;
278 unsigned int min_fill
;
279 unsigned int min_overfill
;
280 unsigned int alloc_page_count
;
281 unsigned int alloc_skb_count
;
282 struct timer_list slow_fill
;
283 unsigned int slow_fill_count
;
287 * struct efx_buffer - An Efx general-purpose buffer
288 * @addr: host base address of the buffer
289 * @dma_addr: DMA base address of the buffer
290 * @len: Buffer length, in bytes
292 * The NIC uses these buffers for its interrupt status registers and
302 enum efx_rx_alloc_method
{
303 RX_ALLOC_METHOD_AUTO
= 0,
304 RX_ALLOC_METHOD_SKB
= 1,
305 RX_ALLOC_METHOD_PAGE
= 2,
309 * struct efx_channel - An Efx channel
311 * A channel comprises an event queue, at least one TX queue, at least
312 * one RX queue, and an associated tasklet for processing the event
315 * @efx: Associated Efx NIC
316 * @channel: Channel instance number
317 * @type: Channel type definition
318 * @enabled: Channel enabled indicator
319 * @irq: IRQ number (MSI and MSI-X only)
320 * @irq_moderation: IRQ moderation value (in hardware ticks)
321 * @napi_dev: Net device used with NAPI
322 * @napi_str: NAPI control structure
323 * @work_pending: Is work pending via NAPI?
324 * @eventq: Event queue buffer
325 * @eventq_mask: Event queue pointer mask
326 * @eventq_read_ptr: Event queue read pointer
327 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
328 * @irq_count: Number of IRQs since last adaptive moderation decision
329 * @irq_mod_score: IRQ moderation score
330 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
331 * and diagnostic counters
332 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
334 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
335 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
336 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
337 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
338 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
339 * @n_rx_overlength: Count of RX_OVERLENGTH errors
340 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
341 * @rx_queue: RX queue for this channel
342 * @tx_queue: TX queues for this channel
347 const struct efx_channel_type
*type
;
350 unsigned int irq_moderation
;
351 struct net_device
*napi_dev
;
352 struct napi_struct napi_str
;
354 struct efx_special_buffer eventq
;
355 unsigned int eventq_mask
;
356 unsigned int eventq_read_ptr
;
359 unsigned int irq_count
;
360 unsigned int irq_mod_score
;
361 #ifdef CONFIG_RFS_ACCEL
362 unsigned int rfs_filters_added
;
366 int rx_alloc_push_pages
;
368 unsigned n_rx_tobe_disc
;
369 unsigned n_rx_ip_hdr_chksum_err
;
370 unsigned n_rx_tcp_udp_chksum_err
;
371 unsigned n_rx_mcast_mismatch
;
372 unsigned n_rx_frm_trunc
;
373 unsigned n_rx_overlength
;
374 unsigned n_skbuff_leaks
;
376 /* Used to pipeline received packets in order to optimise memory
377 * access with prefetches.
379 struct efx_rx_buffer
*rx_pkt
;
381 struct efx_rx_queue rx_queue
;
382 struct efx_tx_queue tx_queue
[EFX_TXQ_TYPES
];
386 * struct efx_channel_type - distinguishes traffic and extra channels
387 * @handle_no_channel: Handle failure to allocate an extra channel
388 * @pre_probe: Set up extra state prior to initialisation
389 * @post_remove: Tear down extra state after finalisation, if allocated.
390 * May be called on channels that have not been probed.
391 * @get_name: Generate the channel's name (used for its IRQ handler)
392 * @copy: Copy the channel state prior to reallocation. May be %NULL if
393 * reallocation is not supported.
394 * @keep_eventq: Flag for whether event queue should be kept initialised
395 * while the device is stopped
397 struct efx_channel_type
{
398 void (*handle_no_channel
)(struct efx_nic
*);
399 int (*pre_probe
)(struct efx_channel
*);
400 void (*get_name
)(struct efx_channel
*, char *buf
, size_t len
);
401 struct efx_channel
*(*copy
)(const struct efx_channel
*);
411 #define STRING_TABLE_LOOKUP(val, member) \
412 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
414 extern const char *const efx_loopback_mode_names
[];
415 extern const unsigned int efx_loopback_mode_max
;
416 #define LOOPBACK_MODE(efx) \
417 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
419 extern const char *const efx_reset_type_names
[];
420 extern const unsigned int efx_reset_type_max
;
421 #define RESET_TYPE(type) \
422 STRING_TABLE_LOOKUP(type, efx_reset_type)
425 /* Be careful if altering to correct macro below */
426 EFX_INT_MODE_MSIX
= 0,
427 EFX_INT_MODE_MSI
= 1,
428 EFX_INT_MODE_LEGACY
= 2,
429 EFX_INT_MODE_MAX
/* Insert any new items before this */
431 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
442 * Alignment of page-allocated RX buffers
444 * Controls the number of bytes inserted at the start of an RX buffer.
445 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
446 * of the skb->head for hardware DMA].
448 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
449 #define EFX_PAGE_IP_ALIGN 0
451 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
455 * Alignment of the skb->head which wraps a page-allocated RX buffer
457 * The skb allocated to wrap an rx_buffer can have this alignment. Since
458 * the data is memcpy'd from the rx_buf, it does not need to be equal to
461 #define EFX_PAGE_SKB_ALIGN 2
463 /* Forward declaration */
466 /* Pseudo bit-mask flow control field */
467 #define EFX_FC_RX FLOW_CTRL_RX
468 #define EFX_FC_TX FLOW_CTRL_TX
469 #define EFX_FC_AUTO 4
472 * struct efx_link_state - Current state of the link
474 * @fd: Link is full-duplex
475 * @fc: Actual flow control flags
476 * @speed: Link speed (Mbps)
478 struct efx_link_state
{
485 static inline bool efx_link_state_equal(const struct efx_link_state
*left
,
486 const struct efx_link_state
*right
)
488 return left
->up
== right
->up
&& left
->fd
== right
->fd
&&
489 left
->fc
== right
->fc
&& left
->speed
== right
->speed
;
493 * struct efx_phy_operations - Efx PHY operations table
494 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
495 * efx->loopback_modes.
496 * @init: Initialise PHY
497 * @fini: Shut down PHY
498 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
499 * @poll: Update @link_state and report whether it changed.
500 * Serialised by the mac_lock.
501 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
502 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
503 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
504 * (only needed where AN bit is set in mmds)
505 * @test_alive: Test that PHY is 'alive' (online)
506 * @test_name: Get the name of a PHY-specific test/result
507 * @run_tests: Run tests and record results as appropriate (offline).
508 * Flags are the ethtool tests flags.
510 struct efx_phy_operations
{
511 int (*probe
) (struct efx_nic
*efx
);
512 int (*init
) (struct efx_nic
*efx
);
513 void (*fini
) (struct efx_nic
*efx
);
514 void (*remove
) (struct efx_nic
*efx
);
515 int (*reconfigure
) (struct efx_nic
*efx
);
516 bool (*poll
) (struct efx_nic
*efx
);
517 void (*get_settings
) (struct efx_nic
*efx
,
518 struct ethtool_cmd
*ecmd
);
519 int (*set_settings
) (struct efx_nic
*efx
,
520 struct ethtool_cmd
*ecmd
);
521 void (*set_npage_adv
) (struct efx_nic
*efx
, u32
);
522 int (*test_alive
) (struct efx_nic
*efx
);
523 const char *(*test_name
) (struct efx_nic
*efx
, unsigned int index
);
524 int (*run_tests
) (struct efx_nic
*efx
, int *results
, unsigned flags
);
528 * @enum efx_phy_mode - PHY operating mode flags
529 * @PHY_MODE_NORMAL: on and should pass traffic
530 * @PHY_MODE_TX_DISABLED: on with TX disabled
531 * @PHY_MODE_LOW_POWER: set to low power through MDIO
532 * @PHY_MODE_OFF: switched off through external control
533 * @PHY_MODE_SPECIAL: on but will not pass traffic
537 PHY_MODE_TX_DISABLED
= 1,
538 PHY_MODE_LOW_POWER
= 2,
540 PHY_MODE_SPECIAL
= 8,
543 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode
)
545 return !!(mode
& ~PHY_MODE_TX_DISABLED
);
549 * Efx extended statistics
551 * Not all statistics are provided by all supported MACs. The purpose
552 * is this structure is to contain the raw statistics provided by each
555 struct efx_mac_stats
{
573 u64 tx_15xx_to_jumbo
;
576 u64 tx_single_collision
;
577 u64 tx_multiple_collision
;
578 u64 tx_excessive_collision
;
580 u64 tx_late_collision
;
581 u64 tx_excessive_deferred
;
583 u64 tx_mac_src_error
;
603 u64 rx_15xx_to_jumbo
;
606 u64 rx_bad_64_to_15xx
;
607 u64 rx_bad_15xx_to_jumbo
;
611 u64 rx_false_carrier
;
615 u64 rx_internal_error
;
619 /* Number of bits used in a multicast filter hash address */
620 #define EFX_MCAST_HASH_BITS 8
622 /* Number of (single-bit) entries in a multicast filter hash */
623 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
625 /* An Efx multicast filter hash */
626 union efx_multicast_hash
{
627 u8 byte
[EFX_MCAST_HASH_ENTRIES
/ 8];
628 efx_oword_t oword
[EFX_MCAST_HASH_ENTRIES
/ sizeof(efx_oword_t
) / 8];
631 struct efx_filter_state
;
636 * struct efx_nic - an Efx NIC
637 * @name: Device name (net device name or bus id before net device registered)
638 * @pci_dev: The PCI device
639 * @type: Controller type attributes
640 * @legacy_irq: IRQ number
641 * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)?
642 * @workqueue: Workqueue for port reconfigures and the HW monitor.
643 * Work items do not hold and must not acquire RTNL.
644 * @workqueue_name: Name of workqueue
645 * @reset_work: Scheduled reset workitem
646 * @membase_phys: Memory BAR value as physical address
647 * @membase: Memory BAR value
648 * @interrupt_mode: Interrupt mode
649 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
650 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
651 * @irq_rx_moderation: IRQ moderation time for RX event queues
652 * @msg_enable: Log message enable flags
653 * @state: Device state flag. Serialised by the rtnl_lock.
654 * @reset_pending: Bitmask for pending resets
655 * @tx_queue: TX DMA queues
656 * @rx_queue: RX DMA queues
658 * @channel_name: Names for channels and their IRQs
659 * @extra_channel_types: Types of extra (non-traffic) channels that
660 * should be allocated for this NIC
661 * @rxq_entries: Size of receive queues requested by user.
662 * @txq_entries: Size of transmit queues requested by user.
663 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
664 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
665 * @sram_lim_qw: Qword address limit of SRAM
666 * @next_buffer_table: First available buffer table id
667 * @n_channels: Number of channels in use
668 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
669 * @n_tx_channels: Number of channels used for TX
670 * @rx_buffer_len: RX buffer length
671 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
672 * @rx_hash_key: Toeplitz hash key for RSS
673 * @rx_indir_table: Indirection table for RSS
674 * @int_error_count: Number of internal errors seen recently
675 * @int_error_expire: Time at which error count will be expired
676 * @irq_status: Interrupt status buffer
677 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
678 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
679 * @selftest_work: Work item for asynchronous self-test
680 * @mtd_list: List of MTDs attached to the NIC
681 * @nic_data: Hardware dependent state
682 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
683 * efx_monitor() and efx_reconfigure_port()
684 * @port_enabled: Port enabled indicator.
685 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
686 * efx_mac_work() with kernel interfaces. Safe to read under any
687 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
688 * be held to modify it.
689 * @port_initialized: Port initialized?
690 * @net_dev: Operating system network device. Consider holding the rtnl lock
691 * @stats_buffer: DMA buffer for statistics
692 * @phy_type: PHY type
693 * @phy_op: PHY interface
694 * @phy_data: PHY private data (including PHY-specific stats)
695 * @mdio: PHY MDIO interface
696 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
697 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
698 * @link_advertising: Autonegotiation advertising flags
699 * @link_state: Current state of the link
700 * @n_link_state_changes: Number of times the link has changed state
701 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
702 * @multicast_hash: Multicast hash table
703 * @wanted_fc: Wanted flow control flags
704 * @fc_disable: When non-zero flow control is disabled. Typically used to
705 * ensure that network back pressure doesn't delay dma queue flushes.
706 * Serialised by the rtnl lock.
707 * @mac_work: Work item for changing MAC promiscuity and multicast hash
708 * @loopback_mode: Loopback status
709 * @loopback_modes: Supported loopback mode bitmask
710 * @loopback_selftest: Offline self-test private state
711 * @drain_pending: Count of RX and TX queues that haven't been flushed and drained.
712 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
713 * Decremented when the efx_flush_rx_queue() is called.
714 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
715 * completed (either success or failure). Not used when MCDI is used to
716 * flush receive queues.
717 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
718 * @vf: Array of &struct efx_vf objects.
719 * @vf_count: Number of VFs intended to be enabled.
720 * @vf_init_count: Number of VFs that have been fully initialised.
721 * @vi_scale: log2 number of vnics per VF.
722 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
723 * @vfdi_status: Common VFDI status page to be dmad to VF address space.
724 * @local_addr_list: List of local addresses. Protected by %local_lock.
725 * @local_page_list: List of DMA addressable pages used to broadcast
726 * %local_addr_list. Protected by %local_lock.
727 * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
728 * @peer_work: Work item to broadcast peer addresses to VMs.
729 * @monitor_work: Hardware monitor workitem
730 * @biu_lock: BIU (bus interface unit) lock
731 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
732 * field is used by efx_test_interrupts() to verify that an
733 * interrupt has occurred.
734 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
735 * @mac_stats: MAC statistics. These include all statistics the MACs
736 * can provide. Generic code converts these into a standard
737 * &struct net_device_stats.
738 * @stats_lock: Statistics update lock. Serialises statistics fetches
739 * and access to @mac_stats.
741 * This is stored in the private area of the &struct net_device.
744 /* The following fields should be written very rarely */
747 struct pci_dev
*pci_dev
;
748 const struct efx_nic_type
*type
;
750 bool legacy_irq_enabled
;
751 struct workqueue_struct
*workqueue
;
752 char workqueue_name
[16];
753 struct work_struct reset_work
;
754 resource_size_t membase_phys
;
755 void __iomem
*membase
;
757 enum efx_int_mode interrupt_mode
;
758 unsigned int timer_quantum_ns
;
759 bool irq_rx_adaptive
;
760 unsigned int irq_rx_moderation
;
763 enum nic_state state
;
764 unsigned long reset_pending
;
766 struct efx_channel
*channel
[EFX_MAX_CHANNELS
];
767 char channel_name
[EFX_MAX_CHANNELS
][IFNAMSIZ
+ 6];
768 const struct efx_channel_type
*
769 extra_channel_type
[EFX_MAX_EXTRA_CHANNELS
];
771 unsigned rxq_entries
;
772 unsigned txq_entries
;
775 unsigned sram_lim_qw
;
776 unsigned next_buffer_table
;
778 unsigned n_rx_channels
;
780 unsigned tx_channel_offset
;
781 unsigned n_tx_channels
;
782 unsigned int rx_buffer_len
;
783 unsigned int rx_buffer_order
;
785 u32 rx_indir_table
[128];
787 unsigned int_error_count
;
788 unsigned long int_error_expire
;
790 struct efx_buffer irq_status
;
791 unsigned irq_zero_count
;
793 struct delayed_work selftest_work
;
795 #ifdef CONFIG_SFC_MTD
796 struct list_head mtd_list
;
801 struct mutex mac_lock
;
802 struct work_struct mac_work
;
805 bool port_initialized
;
806 struct net_device
*net_dev
;
808 struct efx_buffer stats_buffer
;
810 unsigned int phy_type
;
811 const struct efx_phy_operations
*phy_op
;
813 struct mdio_if_info mdio
;
814 unsigned int mdio_bus
;
815 enum efx_phy_mode phy_mode
;
817 u32 link_advertising
;
818 struct efx_link_state link_state
;
819 unsigned int n_link_state_changes
;
822 union efx_multicast_hash multicast_hash
;
827 enum efx_loopback_mode loopback_mode
;
830 void *loopback_selftest
;
832 struct efx_filter_state
*filter_state
;
834 atomic_t drain_pending
;
835 atomic_t rxq_flush_pending
;
836 atomic_t rxq_flush_outstanding
;
837 wait_queue_head_t flush_wq
;
839 #ifdef CONFIG_SFC_SRIOV
840 struct efx_channel
*vfdi_channel
;
843 unsigned vf_init_count
;
845 unsigned vf_buftbl_base
;
846 struct efx_buffer vfdi_status
;
847 struct list_head local_addr_list
;
848 struct list_head local_page_list
;
849 struct mutex local_lock
;
850 struct work_struct peer_work
;
853 /* The following fields may be written more often */
855 struct delayed_work monitor_work ____cacheline_aligned_in_smp
;
858 unsigned n_rx_nodesc_drop_cnt
;
859 struct efx_mac_stats mac_stats
;
860 spinlock_t stats_lock
;
863 static inline int efx_dev_registered(struct efx_nic
*efx
)
865 return efx
->net_dev
->reg_state
== NETREG_REGISTERED
;
868 static inline unsigned int efx_port_num(struct efx_nic
*efx
)
870 return efx
->net_dev
->dev_id
;
874 * struct efx_nic_type - Efx device type definition
875 * @probe: Probe the controller
876 * @remove: Free resources allocated by probe()
877 * @init: Initialise the controller
878 * @dimension_resources: Dimension controller resources (buffer table,
879 * and VIs once the available interrupt resources are clear)
880 * @fini: Shut down the controller
881 * @monitor: Periodic function for polling link state and hardware monitor
882 * @map_reset_reason: Map ethtool reset reason to a reset method
883 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
884 * @reset: Reset the controller hardware and possibly the PHY. This will
885 * be called while the controller is uninitialised.
886 * @probe_port: Probe the MAC and PHY
887 * @remove_port: Free resources allocated by probe_port()
888 * @handle_global_event: Handle a "global" event (may be %NULL)
889 * @prepare_flush: Prepare the hardware for flushing the DMA queues
890 * @update_stats: Update statistics not provided by event handling
891 * @start_stats: Start the regular fetching of statistics
892 * @stop_stats: Stop the regular fetching of statistics
893 * @set_id_led: Set state of identifying LED or revert to automatic function
894 * @push_irq_moderation: Apply interrupt moderation value
895 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
896 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
897 * to the hardware. Serialised by the mac_lock.
898 * @check_mac_fault: Check MAC fault state. True if fault present.
899 * @get_wol: Get WoL configuration from driver state
900 * @set_wol: Push WoL configuration to the NIC
901 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
902 * @test_registers: Test read/write functionality of control registers
903 * @test_nvram: Test validity of NVRAM contents
904 * @revision: Hardware architecture revision
905 * @mem_map_size: Memory BAR mapped size
906 * @txd_ptr_tbl_base: TX descriptor ring base address
907 * @rxd_ptr_tbl_base: RX descriptor ring base address
908 * @buf_tbl_base: Buffer table base address
909 * @evq_ptr_tbl_base: Event queue pointer table base address
910 * @evq_rptr_tbl_base: Event queue read-pointer table base address
911 * @max_dma_mask: Maximum possible DMA mask
912 * @rx_buffer_hash_size: Size of hash at start of RX buffer
913 * @rx_buffer_padding: Size of padding at end of RX buffer
914 * @max_interrupt_mode: Highest capability interrupt mode supported
915 * from &enum efx_init_mode.
916 * @phys_addr_channels: Number of channels with physically addressed
918 * @timer_period_max: Maximum period of interrupt timer (in ticks)
919 * @offload_features: net_device feature flags for protocol offload
920 * features implemented in hardware
922 struct efx_nic_type
{
923 int (*probe
)(struct efx_nic
*efx
);
924 void (*remove
)(struct efx_nic
*efx
);
925 int (*init
)(struct efx_nic
*efx
);
926 void (*dimension_resources
)(struct efx_nic
*efx
);
927 void (*fini
)(struct efx_nic
*efx
);
928 void (*monitor
)(struct efx_nic
*efx
);
929 enum reset_type (*map_reset_reason
)(enum reset_type reason
);
930 int (*map_reset_flags
)(u32
*flags
);
931 int (*reset
)(struct efx_nic
*efx
, enum reset_type method
);
932 int (*probe_port
)(struct efx_nic
*efx
);
933 void (*remove_port
)(struct efx_nic
*efx
);
934 bool (*handle_global_event
)(struct efx_channel
*channel
, efx_qword_t
*);
935 void (*prepare_flush
)(struct efx_nic
*efx
);
936 void (*update_stats
)(struct efx_nic
*efx
);
937 void (*start_stats
)(struct efx_nic
*efx
);
938 void (*stop_stats
)(struct efx_nic
*efx
);
939 void (*set_id_led
)(struct efx_nic
*efx
, enum efx_led_mode mode
);
940 void (*push_irq_moderation
)(struct efx_channel
*channel
);
941 int (*reconfigure_port
)(struct efx_nic
*efx
);
942 int (*reconfigure_mac
)(struct efx_nic
*efx
);
943 bool (*check_mac_fault
)(struct efx_nic
*efx
);
944 void (*get_wol
)(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
);
945 int (*set_wol
)(struct efx_nic
*efx
, u32 type
);
946 void (*resume_wol
)(struct efx_nic
*efx
);
947 int (*test_registers
)(struct efx_nic
*efx
);
948 int (*test_nvram
)(struct efx_nic
*efx
);
951 unsigned int mem_map_size
;
952 unsigned int txd_ptr_tbl_base
;
953 unsigned int rxd_ptr_tbl_base
;
954 unsigned int buf_tbl_base
;
955 unsigned int evq_ptr_tbl_base
;
956 unsigned int evq_rptr_tbl_base
;
958 unsigned int rx_buffer_hash_size
;
959 unsigned int rx_buffer_padding
;
960 unsigned int max_interrupt_mode
;
961 unsigned int phys_addr_channels
;
962 unsigned int timer_period_max
;
963 netdev_features_t offload_features
;
966 /**************************************************************************
968 * Prototypes and inline functions
970 *************************************************************************/
972 static inline struct efx_channel
*
973 efx_get_channel(struct efx_nic
*efx
, unsigned index
)
975 EFX_BUG_ON_PARANOID(index
>= efx
->n_channels
);
976 return efx
->channel
[index
];
979 /* Iterate over all used channels */
980 #define efx_for_each_channel(_channel, _efx) \
981 for (_channel = (_efx)->channel[0]; \
983 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
984 (_efx)->channel[_channel->channel + 1] : NULL)
986 /* Iterate over all used channels in reverse */
987 #define efx_for_each_channel_rev(_channel, _efx) \
988 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
990 _channel = _channel->channel ? \
991 (_efx)->channel[_channel->channel - 1] : NULL)
993 static inline struct efx_tx_queue
*
994 efx_get_tx_queue(struct efx_nic
*efx
, unsigned index
, unsigned type
)
996 EFX_BUG_ON_PARANOID(index
>= efx
->n_tx_channels
||
997 type
>= EFX_TXQ_TYPES
);
998 return &efx
->channel
[efx
->tx_channel_offset
+ index
]->tx_queue
[type
];
1001 static inline bool efx_channel_has_tx_queues(struct efx_channel
*channel
)
1003 return channel
->channel
- channel
->efx
->tx_channel_offset
<
1004 channel
->efx
->n_tx_channels
;
1007 static inline struct efx_tx_queue
*
1008 efx_channel_get_tx_queue(struct efx_channel
*channel
, unsigned type
)
1010 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel
) ||
1011 type
>= EFX_TXQ_TYPES
);
1012 return &channel
->tx_queue
[type
];
1015 static inline bool efx_tx_queue_used(struct efx_tx_queue
*tx_queue
)
1017 return !(tx_queue
->efx
->net_dev
->num_tc
< 2 &&
1018 tx_queue
->queue
& EFX_TXQ_TYPE_HIGHPRI
);
1021 /* Iterate over all TX queues belonging to a channel */
1022 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1023 if (!efx_channel_has_tx_queues(_channel)) \
1026 for (_tx_queue = (_channel)->tx_queue; \
1027 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1028 efx_tx_queue_used(_tx_queue); \
1031 /* Iterate over all possible TX queues belonging to a channel */
1032 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
1033 if (!efx_channel_has_tx_queues(_channel)) \
1036 for (_tx_queue = (_channel)->tx_queue; \
1037 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
1040 static inline bool efx_channel_has_rx_queue(struct efx_channel
*channel
)
1042 return channel
->channel
< channel
->efx
->n_rx_channels
;
1045 static inline struct efx_rx_queue
*
1046 efx_channel_get_rx_queue(struct efx_channel
*channel
)
1048 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel
));
1049 return &channel
->rx_queue
;
1052 /* Iterate over all RX queues belonging to a channel */
1053 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1054 if (!efx_channel_has_rx_queue(_channel)) \
1057 for (_rx_queue = &(_channel)->rx_queue; \
1061 static inline struct efx_channel
*
1062 efx_rx_queue_channel(struct efx_rx_queue
*rx_queue
)
1064 return container_of(rx_queue
, struct efx_channel
, rx_queue
);
1067 static inline int efx_rx_queue_index(struct efx_rx_queue
*rx_queue
)
1069 return efx_rx_queue_channel(rx_queue
)->channel
;
1072 /* Returns a pointer to the specified receive buffer in the RX
1075 static inline struct efx_rx_buffer
*efx_rx_buffer(struct efx_rx_queue
*rx_queue
,
1078 return &rx_queue
->buffer
[index
];
1081 /* Set bit in a little-endian bitfield */
1082 static inline void set_bit_le(unsigned nr
, unsigned char *addr
)
1084 addr
[nr
/ 8] |= (1 << (nr
% 8));
1087 /* Clear bit in a little-endian bitfield */
1088 static inline void clear_bit_le(unsigned nr
, unsigned char *addr
)
1090 addr
[nr
/ 8] &= ~(1 << (nr
% 8));
1095 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1097 * This calculates the maximum frame length that will be used for a
1098 * given MTU. The frame length will be equal to the MTU plus a
1099 * constant amount of header space and padding. This is the quantity
1100 * that the net driver will program into the MAC as the maximum frame
1103 * The 10G MAC requires 8-byte alignment on the frame
1104 * length, so we round up to the nearest 8.
1106 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1107 * XGMII cycle). If the frame length reaches the maximum value in the
1108 * same cycle, the XMAC can miss the IPG altogether. We work around
1109 * this by adding a further 16 bytes.
1111 #define EFX_MAX_FRAME_LEN(mtu) \
1112 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1115 #endif /* EFX_NET_DRIVER_H */