drivers/net/ethernet/sfc/nic.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2011 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #ifndef EFX_NIC_H
  12 #define EFX_NIC_H
  13
  14 #include <linux/net_tstamp.h>
  15 #include <linux/i2c-algo-bit.h>
  16 #include "net_driver.h"
  17 #include "efx.h"
  18 #include "mcdi.h"
  19 #include "spi.h"
  20
  21 /*
  22  * Falcon hardware control
  23  */
  24
  25 enum {
  26         EFX_REV_FALCON_A0 = 0,
  27         EFX_REV_FALCON_A1 = 1,
  28         EFX_REV_FALCON_B0 = 2,
  29         EFX_REV_SIENA_A0 = 3,
  30 };
  31
  32 static inline int efx_nic_rev(struct efx_nic *efx)
  33 {
  34         return efx->type->revision;
  35 }
  36
  37 extern u32 efx_farch_fpga_ver(struct efx_nic *efx);
  38
  39 /* NIC has two interlinked PCI functions for the same port. */
  40 static inline bool efx_nic_is_dual_func(struct efx_nic *efx)
  41 {
  42         return efx_nic_rev(efx) < EFX_REV_FALCON_B0;
  43 }
  44
  45 /* Read the current event from the event queue */
  46 static inline efx_qword_t *efx_event(struct efx_channel *channel,
  47                                      unsigned int index)
  48 {
  49         return ((efx_qword_t *) (channel->eventq.buf.addr)) +
  50                 (index & channel->eventq_mask);
  51 }
  52
  53 /* See if an event is present
  54  *
  55  * We check both the high and low dword of the event for all ones.  We
  56  * wrote all ones when we cleared the event, and no valid event can
  57  * have all ones in either its high or low dwords.  This approach is
  58  * robust against reordering.
  59  *
  60  * Note that using a single 64-bit comparison is incorrect; even
  61  * though the CPU read will be atomic, the DMA write may not be.
  62  */
  63 static inline int efx_event_present(efx_qword_t *event)
  64 {
  65         return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
  66                   EFX_DWORD_IS_ALL_ONES(event->dword[1]));
  67 }
  68
  69 /* Returns a pointer to the specified transmit descriptor in the TX
  70  * descriptor queue belonging to the specified channel.
  71  */
  72 static inline efx_qword_t *
  73 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
  74 {
  75         return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
  76 }
  77
  78 /* Decide whether to push a TX descriptor to the NIC vs merely writing
  79  * the doorbell.  This can reduce latency when we are adding a single
  80  * descriptor to an empty queue, but is otherwise pointless.  Further,
  81  * Falcon and Siena have hardware bugs (SF bug 33851) that may be
  82  * triggered if we don't check this.
  83  */
  84 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
  85                                             unsigned int write_count)
  86 {
  87         unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
  88
  89         if (empty_read_count == 0)
  90                 return false;
  91
  92         tx_queue->empty_read_count = 0;
  93         return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0
  94                 && tx_queue->write_count - write_count == 1;
  95 }
  96
  97 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
  98 static inline efx_qword_t *
  99 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
 100 {
 101         return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
 102 }
 103
 104 enum {
 105         PHY_TYPE_NONE = 0,
 106         PHY_TYPE_TXC43128 = 1,
 107         PHY_TYPE_88E1111 = 2,
 108         PHY_TYPE_SFX7101 = 3,
 109         PHY_TYPE_QT2022C2 = 4,
 110         PHY_TYPE_PM8358 = 6,
 111         PHY_TYPE_SFT9001A = 8,
 112         PHY_TYPE_QT2025C = 9,
 113         PHY_TYPE_SFT9001B = 10,
 114 };
 115
 116 #define FALCON_XMAC_LOOPBACKS                   \
 117         ((1 << LOOPBACK_XGMII) |                \
 118          (1 << LOOPBACK_XGXS) |                 \
 119          (1 << LOOPBACK_XAUI))
 120
 121 #define FALCON_GMAC_LOOPBACKS                   \
 122         (1 << LOOPBACK_GMAC)
 123
 124 /* Alignment of PCIe DMA boundaries (4KB) */
 125 #define EFX_PAGE_SIZE   4096
 126 /* Size and alignment of buffer table entries (same) */
 127 #define EFX_BUF_SIZE    EFX_PAGE_SIZE
 128
 129 /**
 130  * struct falcon_board_type - board operations and type information
 131  * @id: Board type id, as found in NVRAM
 132  * @init: Allocate resources and initialise peripheral hardware
 133  * @init_phy: Do board-specific PHY initialisation
 134  * @fini: Shut down hardware and free resources
 135  * @set_id_led: Set state of identifying LED or revert to automatic function
 136  * @monitor: Board-specific health check function
 137  */
 138 struct falcon_board_type {
 139         u8 id;
 140         int (*init) (struct efx_nic *nic);
 141         void (*init_phy) (struct efx_nic *efx);
 142         void (*fini) (struct efx_nic *nic);
 143         void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode);
 144         int (*monitor) (struct efx_nic *nic);
 145 };
 146
 147 /**
 148  * struct falcon_board - board information
 149  * @type: Type of board
 150  * @major: Major rev. ('A', 'B' ...)
 151  * @minor: Minor rev. (0, 1, ...)
 152  * @i2c_adap: I2C adapter for on-board peripherals
 153  * @i2c_data: Data for bit-banging algorithm
 154  * @hwmon_client: I2C client for hardware monitor
 155  * @ioexp_client: I2C client for power/port control
 156  */
 157 struct falcon_board {
 158         const struct falcon_board_type *type;
 159         int major;
 160         int minor;
 161         struct i2c_adapter i2c_adap;
 162         struct i2c_algo_bit_data i2c_data;
 163         struct i2c_client *hwmon_client, *ioexp_client;
 164 };
 165
 166 /**
 167  * struct falcon_nic_data - Falcon NIC state
 168  * @pci_dev2: Secondary function of Falcon A
 169  * @board: Board state and functions
 170  * @stats_disable_count: Nest count for disabling statistics fetches
 171  * @stats_pending: Is there a pending DMA of MAC statistics.
 172  * @stats_timer: A timer for regularly fetching MAC statistics.
 173  * @stats_dma_done: Pointer to the flag which indicates DMA completion.
 174  * @spi_flash: SPI flash device
 175  * @spi_eeprom: SPI EEPROM device
 176  * @spi_lock: SPI bus lock
 177  * @mdio_lock: MDIO bus lock
 178  * @xmac_poll_required: XMAC link state needs polling
 179  */
 180 struct falcon_nic_data {
 181         struct pci_dev *pci_dev2;
 182         struct falcon_board board;
 183         unsigned int stats_disable_count;
 184         bool stats_pending;
 185         struct timer_list stats_timer;
 186         u32 *stats_dma_done;
 187         struct efx_spi_device spi_flash;
 188         struct efx_spi_device spi_eeprom;
 189         struct mutex spi_lock;
 190         struct mutex mdio_lock;
 191         bool xmac_poll_required;
 192 };
 193
 194 static inline struct falcon_board *falcon_board(struct efx_nic *efx)
 195 {
 196         struct falcon_nic_data *data = efx->nic_data;
 197         return &data->board;
 198 }
 199
 200 /**
 201  * struct siena_nic_data - Siena NIC state
 202  * @wol_filter_id: Wake-on-LAN packet filter id
 203  */
 204 struct siena_nic_data {
 205         int wol_filter_id;
 206 };
 207
 208 /*
 209  * On the SFC9000 family each port is associated with 1 PCI physical
 210  * function (PF) handled by sfc and a configurable number of virtual
 211  * functions (VFs) that may be handled by some other driver, often in
 212  * a VM guest.  The queue pointer registers are mapped in both PF and
 213  * VF BARs such that an 8K region provides access to a single RX, TX
 214  * and event queue (collectively a Virtual Interface, VI or VNIC).
 215  *
 216  * The PF has access to all 1024 VIs while VFs are mapped to VIs
 217  * according to VI_BASE and VI_SCALE: VF i has access to VIs numbered
 218  * in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE).
 219  * The number of VIs and the VI_SCALE value are configurable but must
 220  * be established at boot time by firmware.
 221  */
 222
 223 /* Maximum VI_SCALE parameter supported by Siena */
 224 #define EFX_VI_SCALE_MAX 6
 225 /* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX),
 226  * so this is the smallest allowed value. */
 227 #define EFX_VI_BASE 128U
 228 /* Maximum number of VFs allowed */
 229 #define EFX_VF_COUNT_MAX 127
 230 /* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */
 231 #define EFX_MAX_VF_EVQ_SIZE 8192UL
 232 /* The number of buffer table entries reserved for each VI on a VF */
 233 #define EFX_VF_BUFTBL_PER_VI                                    \
 234         ((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) *        \
 235          sizeof(efx_qword_t) / EFX_BUF_SIZE)
 236
 237 #ifdef CONFIG_SFC_SRIOV
 238
 239 static inline bool efx_sriov_wanted(struct efx_nic *efx)
 240 {
 241         return efx->vf_count != 0;
 242 }
 243 static inline bool efx_sriov_enabled(struct efx_nic *efx)
 244 {
 245         return efx->vf_init_count != 0;
 246 }
 247 static inline unsigned int efx_vf_size(struct efx_nic *efx)
 248 {
 249         return 1 << efx->vi_scale;
 250 }
 251
 252 extern int efx_init_sriov(void);
 253 extern void efx_sriov_probe(struct efx_nic *efx);
 254 extern int efx_sriov_init(struct efx_nic *efx);
 255 extern void efx_sriov_mac_address_changed(struct efx_nic *efx);
 256 extern void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event);
 257 extern void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event);
 258 extern void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event);
 259 extern void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq);
 260 extern void efx_sriov_flr(struct efx_nic *efx, unsigned flr);
 261 extern void efx_sriov_reset(struct efx_nic *efx);
 262 extern void efx_sriov_fini(struct efx_nic *efx);
 263 extern void efx_fini_sriov(void);
 264
 265 #else
 266
 267 static inline bool efx_sriov_wanted(struct efx_nic *efx) { return false; }
 268 static inline bool efx_sriov_enabled(struct efx_nic *efx) { return false; }
 269 static inline unsigned int efx_vf_size(struct efx_nic *efx) { return 0; }
 270
 271 static inline int efx_init_sriov(void) { return 0; }
 272 static inline void efx_sriov_probe(struct efx_nic *efx) {}
 273 static inline int efx_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; }
 274 static inline void efx_sriov_mac_address_changed(struct efx_nic *efx) {}
 275 static inline void efx_sriov_tx_flush_done(struct efx_nic *efx,
 276                                            efx_qword_t *event) {}
 277 static inline void efx_sriov_rx_flush_done(struct efx_nic *efx,
 278                                            efx_qword_t *event) {}
 279 static inline void efx_sriov_event(struct efx_channel *channel,
 280                                    efx_qword_t *event) {}
 281 static inline void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) {}
 282 static inline void efx_sriov_flr(struct efx_nic *efx, unsigned flr) {}
 283 static inline void efx_sriov_reset(struct efx_nic *efx) {}
 284 static inline void efx_sriov_fini(struct efx_nic *efx) {}
 285 static inline void efx_fini_sriov(void) {}
 286
 287 #endif
 288
 289 extern int efx_sriov_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
 290 extern int efx_sriov_set_vf_vlan(struct net_device *dev, int vf,
 291                                  u16 vlan, u8 qos);
 292 extern int efx_sriov_get_vf_config(struct net_device *dev, int vf,
 293                                    struct ifla_vf_info *ivf);
 294 extern int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf,
 295                                      bool spoofchk);
 296
 297 struct ethtool_ts_info;
 298 extern void efx_ptp_probe(struct efx_nic *efx);
 299 extern int efx_ptp_ioctl(struct efx_nic *efx, struct ifreq *ifr, int cmd);
 300 extern void efx_ptp_get_ts_info(struct efx_nic *efx,
 301                                 struct ethtool_ts_info *ts_info);
 302 extern bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
 303 extern int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
 304 extern void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
 305
 306 extern const struct efx_nic_type falcon_a1_nic_type;
 307 extern const struct efx_nic_type falcon_b0_nic_type;
 308 extern const struct efx_nic_type siena_a0_nic_type;
 309
 310 /**************************************************************************
 311  *
 312  * Externs
 313  *
 314  **************************************************************************
 315  */
 316
 317 extern int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
 318
 319 /* TX data path */
 320 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
 321 {
 322         return tx_queue->efx->type->tx_probe(tx_queue);
 323 }
 324 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
 325 {
 326         tx_queue->efx->type->tx_init(tx_queue);
 327 }
 328 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
 329 {
 330         tx_queue->efx->type->tx_remove(tx_queue);
 331 }
 332 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
 333 {
 334         tx_queue->efx->type->tx_write(tx_queue);
 335 }
 336
 337 /* RX data path */
 338 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
 339 {
 340         return rx_queue->efx->type->rx_probe(rx_queue);
 341 }
 342 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
 343 {
 344         rx_queue->efx->type->rx_init(rx_queue);
 345 }
 346 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
 347 {
 348         rx_queue->efx->type->rx_remove(rx_queue);
 349 }
 350 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
 351 {
 352         rx_queue->efx->type->rx_write(rx_queue);
 353 }
 354 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
 355 {
 356         rx_queue->efx->type->rx_defer_refill(rx_queue);
 357 }
 358
 359 /* Event data path */
 360 static inline int efx_nic_probe_eventq(struct efx_channel *channel)
 361 {
 362         return channel->efx->type->ev_probe(channel);
 363 }
 364 static inline void efx_nic_init_eventq(struct efx_channel *channel)
 365 {
 366         channel->efx->type->ev_init(channel);
 367 }
 368 static inline void efx_nic_fini_eventq(struct efx_channel *channel)
 369 {
 370         channel->efx->type->ev_fini(channel);
 371 }
 372 static inline void efx_nic_remove_eventq(struct efx_channel *channel)
 373 {
 374         channel->efx->type->ev_remove(channel);
 375 }
 376 static inline int
 377 efx_nic_process_eventq(struct efx_channel *channel, int quota)
 378 {
 379         return channel->efx->type->ev_process(channel, quota);
 380 }
 381 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
 382 {
 383         channel->efx->type->ev_read_ack(channel);
 384 }
 385 extern void efx_nic_event_test_start(struct efx_channel *channel);
 386
 387 /* Falcon/Siena queue operations */
 388 extern int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
 389 extern void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
 390 extern void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
 391 extern void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
 392 extern void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
 393 extern int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
 394 extern void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
 395 extern void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
 396 extern void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
 397 extern void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
 398 extern void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
 399 extern int efx_farch_ev_probe(struct efx_channel *channel);
 400 extern void efx_farch_ev_init(struct efx_channel *channel);
 401 extern void efx_farch_ev_fini(struct efx_channel *channel);
 402 extern void efx_farch_ev_remove(struct efx_channel *channel);
 403 extern int efx_farch_ev_process(struct efx_channel *channel, int quota);
 404 extern void efx_farch_ev_read_ack(struct efx_channel *channel);
 405 extern void efx_farch_ev_test_generate(struct efx_channel *channel);
 406
 407 /* Falcon/Siena filter operations */
 408 extern int efx_farch_filter_table_probe(struct efx_nic *efx);
 409 extern void efx_farch_filter_table_restore(struct efx_nic *efx);
 410 extern void efx_farch_filter_table_remove(struct efx_nic *efx);
 411 extern void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
 412 extern s32 efx_farch_filter_insert(struct efx_nic *efx,
 413                                    struct efx_filter_spec *spec, bool replace);
 414 extern int efx_farch_filter_remove_safe(struct efx_nic *efx,
 415                                         enum efx_filter_priority priority,
 416                                         u32 filter_id);
 417 extern int efx_farch_filter_get_safe(struct efx_nic *efx,
 418                                      enum efx_filter_priority priority,
 419                                      u32 filter_id, struct efx_filter_spec *);
 420 extern void efx_farch_filter_clear_rx(struct efx_nic *efx,
 421                                       enum efx_filter_priority priority);
 422 extern u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
 423                                           enum efx_filter_priority priority);
 424 extern u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
 425 extern s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
 426                                        enum efx_filter_priority priority,
 427                                        u32 *buf, u32 size);
 428 #ifdef CONFIG_RFS_ACCEL
 429 extern s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
 430                                        struct efx_filter_spec *spec);
 431 extern bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
 432                                             unsigned int index);
 433 #endif
 434 extern void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
 435
 436 extern bool efx_nic_event_present(struct efx_channel *channel);
 437
 438 /* Some statistics are computed as A - B where A and B each increase
 439  * linearly with some hardware counter(s) and the counters are read
 440  * asynchronously.  If the counters contributing to B are always read
 441  * after those contributing to A, the computed value may be lower than
 442  * the true value by some variable amount, and may decrease between
 443  * subsequent computations.
 444  *
 445  * We should never allow statistics to decrease or to exceed the true
 446  * value.  Since the computed value will never be greater than the
 447  * true value, we can achieve this by only storing the computed value
 448  * when it increases.
 449  */
 450 static inline void efx_update_diff_stat(u64 *stat, u64 diff)
 451 {
 452         if ((s64)(diff - *stat) > 0)
 453                 *stat = diff;
 454 }
 455
 456 /* Interrupts */
 457 extern int efx_nic_init_interrupt(struct efx_nic *efx);
 458 extern void efx_nic_irq_test_start(struct efx_nic *efx);
 459 extern void efx_nic_fini_interrupt(struct efx_nic *efx);
 460
 461 /* Falcon/Siena interrupts */
 462 extern void efx_farch_irq_enable_master(struct efx_nic *efx);
 463 extern void efx_farch_irq_test_generate(struct efx_nic *efx);
 464 extern void efx_farch_irq_disable_master(struct efx_nic *efx);
 465 extern irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
 466 extern irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
 467 extern irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
 468
 469 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
 470 {
 471         return ACCESS_ONCE(channel->event_test_cpu);
 472 }
 473 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
 474 {
 475         return ACCESS_ONCE(efx->last_irq_cpu);
 476 }
 477
 478 /* Global Resources */
 479 extern int efx_nic_flush_queues(struct efx_nic *efx);
 480 extern void siena_prepare_flush(struct efx_nic *efx);
 481 extern int efx_farch_fini_dmaq(struct efx_nic *efx);
 482 extern void siena_finish_flush(struct efx_nic *efx);
 483 extern void falcon_start_nic_stats(struct efx_nic *efx);
 484 extern void falcon_stop_nic_stats(struct efx_nic *efx);
 485 extern int falcon_reset_xaui(struct efx_nic *efx);
 486 extern void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
 487 extern void efx_farch_init_common(struct efx_nic *efx);
 488 static inline void efx_nic_push_rx_indir_table(struct efx_nic *efx)
 489 {
 490         efx->type->rx_push_indir_table(efx);
 491 }
 492 extern void efx_farch_rx_push_indir_table(struct efx_nic *efx);
 493
 494 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
 495                          unsigned int len, gfp_t gfp_flags);
 496 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
 497
 498 /* Tests */
 499 struct efx_farch_register_test {
 500         unsigned address;
 501         efx_oword_t mask;
 502 };
 503 extern int efx_farch_test_registers(struct efx_nic *efx,
 504                                     const struct efx_farch_register_test *regs,
 505                                     size_t n_regs);
 506
 507 extern size_t efx_nic_get_regs_len(struct efx_nic *efx);
 508 extern void efx_nic_get_regs(struct efx_nic *efx, void *buf);
 509
 510 #define EFX_MAX_FLUSH_TIME 5000
 511
 512 extern void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
 513                                      efx_qword_t *event);
 514
 515 #endif /* EFX_NIC_H */