drivers/net/ethernet/sfc/nic.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2011 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #ifndef EFX_NIC_H
  12 #define EFX_NIC_H
  13
  14 #include <linux/net_tstamp.h>
  15 #include <linux/i2c-algo-bit.h>
  16 #include "net_driver.h"
  17 #include "efx.h"
  18 #include "mcdi.h"
  19
  20 /*
  21  * Falcon hardware control
  22  */
  23
  24 enum {
  25         EFX_REV_FALCON_A0 = 0,
  26         EFX_REV_FALCON_A1 = 1,
  27         EFX_REV_FALCON_B0 = 2,
  28         EFX_REV_SIENA_A0 = 3,
  29 };
  30
  31 static inline int efx_nic_rev(struct efx_nic *efx)
  32 {
  33         return efx->type->revision;
  34 }
  35
  36 extern u32 efx_farch_fpga_ver(struct efx_nic *efx);
  37
  38 /* NIC has two interlinked PCI functions for the same port. */
  39 static inline bool efx_nic_is_dual_func(struct efx_nic *efx)
  40 {
  41         return efx_nic_rev(efx) < EFX_REV_FALCON_B0;
  42 }
  43
  44 /* Read the current event from the event queue */
  45 static inline efx_qword_t *efx_event(struct efx_channel *channel,
  46                                      unsigned int index)
  47 {
  48         return ((efx_qword_t *) (channel->eventq.buf.addr)) +
  49                 (index & channel->eventq_mask);
  50 }
  51
  52 /* See if an event is present
  53  *
  54  * We check both the high and low dword of the event for all ones.  We
  55  * wrote all ones when we cleared the event, and no valid event can
  56  * have all ones in either its high or low dwords.  This approach is
  57  * robust against reordering.
  58  *
  59  * Note that using a single 64-bit comparison is incorrect; even
  60  * though the CPU read will be atomic, the DMA write may not be.
  61  */
  62 static inline int efx_event_present(efx_qword_t *event)
  63 {
  64         return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
  65                   EFX_DWORD_IS_ALL_ONES(event->dword[1]));
  66 }
  67
  68 /* Returns a pointer to the specified transmit descriptor in the TX
  69  * descriptor queue belonging to the specified channel.
  70  */
  71 static inline efx_qword_t *
  72 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
  73 {
  74         return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
  75 }
  76
  77 /* Decide whether to push a TX descriptor to the NIC vs merely writing
  78  * the doorbell.  This can reduce latency when we are adding a single
  79  * descriptor to an empty queue, but is otherwise pointless.  Further,
  80  * Falcon and Siena have hardware bugs (SF bug 33851) that may be
  81  * triggered if we don't check this.
  82  */
  83 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
  84                                             unsigned int write_count)
  85 {
  86         unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
  87
  88         if (empty_read_count == 0)
  89                 return false;
  90
  91         tx_queue->empty_read_count = 0;
  92         return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0
  93                 && tx_queue->write_count - write_count == 1;
  94 }
  95
  96 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
  97 static inline efx_qword_t *
  98 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
  99 {
 100         return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
 101 }
 102
 103 enum {
 104         PHY_TYPE_NONE = 0,
 105         PHY_TYPE_TXC43128 = 1,
 106         PHY_TYPE_88E1111 = 2,
 107         PHY_TYPE_SFX7101 = 3,
 108         PHY_TYPE_QT2022C2 = 4,
 109         PHY_TYPE_PM8358 = 6,
 110         PHY_TYPE_SFT9001A = 8,
 111         PHY_TYPE_QT2025C = 9,
 112         PHY_TYPE_SFT9001B = 10,
 113 };
 114
 115 #define FALCON_XMAC_LOOPBACKS                   \
 116         ((1 << LOOPBACK_XGMII) |                \
 117          (1 << LOOPBACK_XGXS) |                 \
 118          (1 << LOOPBACK_XAUI))
 119
 120 /* Alignment of PCIe DMA boundaries (4KB) */
 121 #define EFX_PAGE_SIZE   4096
 122 /* Size and alignment of buffer table entries (same) */
 123 #define EFX_BUF_SIZE    EFX_PAGE_SIZE
 124
 125 /**
 126  * struct falcon_board_type - board operations and type information
 127  * @id: Board type id, as found in NVRAM
 128  * @init: Allocate resources and initialise peripheral hardware
 129  * @init_phy: Do board-specific PHY initialisation
 130  * @fini: Shut down hardware and free resources
 131  * @set_id_led: Set state of identifying LED or revert to automatic function
 132  * @monitor: Board-specific health check function
 133  */
 134 struct falcon_board_type {
 135         u8 id;
 136         int (*init) (struct efx_nic *nic);
 137         void (*init_phy) (struct efx_nic *efx);
 138         void (*fini) (struct efx_nic *nic);
 139         void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode);
 140         int (*monitor) (struct efx_nic *nic);
 141 };
 142
 143 /**
 144  * struct falcon_board - board information
 145  * @type: Type of board
 146  * @major: Major rev. ('A', 'B' ...)
 147  * @minor: Minor rev. (0, 1, ...)
 148  * @i2c_adap: I2C adapter for on-board peripherals
 149  * @i2c_data: Data for bit-banging algorithm
 150  * @hwmon_client: I2C client for hardware monitor
 151  * @ioexp_client: I2C client for power/port control
 152  */
 153 struct falcon_board {
 154         const struct falcon_board_type *type;
 155         int major;
 156         int minor;
 157         struct i2c_adapter i2c_adap;
 158         struct i2c_algo_bit_data i2c_data;
 159         struct i2c_client *hwmon_client, *ioexp_client;
 160 };
 161
 162 /**
 163  * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device
 164  * @device_id:          Controller's id for the device
 165  * @size:               Size (in bytes)
 166  * @addr_len:           Number of address bytes in read/write commands
 167  * @munge_address:      Flag whether addresses should be munged.
 168  *      Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
 169  *      use bit 3 of the command byte as address bit A8, rather
 170  *      than having a two-byte address.  If this flag is set, then
 171  *      commands should be munged in this way.
 172  * @erase_command:      Erase command (or 0 if sector erase not needed).
 173  * @erase_size:         Erase sector size (in bytes)
 174  *      Erase commands affect sectors with this size and alignment.
 175  *      This must be a power of two.
 176  * @block_size:         Write block size (in bytes).
 177  *      Write commands are limited to blocks with this size and alignment.
 178  */
 179 struct falcon_spi_device {
 180         int device_id;
 181         unsigned int size;
 182         unsigned int addr_len;
 183         unsigned int munge_address:1;
 184         u8 erase_command;
 185         unsigned int erase_size;
 186         unsigned int block_size;
 187 };
 188
 189 static inline bool falcon_spi_present(const struct falcon_spi_device *spi)
 190 {
 191         return spi->size != 0;
 192 }
 193
 194 /**
 195  * struct falcon_nic_data - Falcon NIC state
 196  * @pci_dev2: Secondary function of Falcon A
 197  * @board: Board state and functions
 198  * @stats_disable_count: Nest count for disabling statistics fetches
 199  * @stats_pending: Is there a pending DMA of MAC statistics.
 200  * @stats_timer: A timer for regularly fetching MAC statistics.
 201  * @spi_flash: SPI flash device
 202  * @spi_eeprom: SPI EEPROM device
 203  * @spi_lock: SPI bus lock
 204  * @mdio_lock: MDIO bus lock
 205  * @xmac_poll_required: XMAC link state needs polling
 206  */
 207 struct falcon_nic_data {
 208         struct pci_dev *pci_dev2;
 209         struct falcon_board board;
 210         unsigned int stats_disable_count;
 211         bool stats_pending;
 212         struct timer_list stats_timer;
 213         struct falcon_spi_device spi_flash;
 214         struct falcon_spi_device spi_eeprom;
 215         struct mutex spi_lock;
 216         struct mutex mdio_lock;
 217         bool xmac_poll_required;
 218 };
 219
 220 static inline struct falcon_board *falcon_board(struct efx_nic *efx)
 221 {
 222         struct falcon_nic_data *data = efx->nic_data;
 223         return &data->board;
 224 }
 225
 226 /**
 227  * struct siena_nic_data - Siena NIC state
 228  * @wol_filter_id: Wake-on-LAN packet filter id
 229  */
 230 struct siena_nic_data {
 231         int wol_filter_id;
 232 };
 233
 234 /*
 235  * On the SFC9000 family each port is associated with 1 PCI physical
 236  * function (PF) handled by sfc and a configurable number of virtual
 237  * functions (VFs) that may be handled by some other driver, often in
 238  * a VM guest.  The queue pointer registers are mapped in both PF and
 239  * VF BARs such that an 8K region provides access to a single RX, TX
 240  * and event queue (collectively a Virtual Interface, VI or VNIC).
 241  *
 242  * The PF has access to all 1024 VIs while VFs are mapped to VIs
 243  * according to VI_BASE and VI_SCALE: VF i has access to VIs numbered
 244  * in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE).
 245  * The number of VIs and the VI_SCALE value are configurable but must
 246  * be established at boot time by firmware.
 247  */
 248
 249 /* Maximum VI_SCALE parameter supported by Siena */
 250 #define EFX_VI_SCALE_MAX 6
 251 /* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX),
 252  * so this is the smallest allowed value. */
 253 #define EFX_VI_BASE 128U
 254 /* Maximum number of VFs allowed */
 255 #define EFX_VF_COUNT_MAX 127
 256 /* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */
 257 #define EFX_MAX_VF_EVQ_SIZE 8192UL
 258 /* The number of buffer table entries reserved for each VI on a VF */
 259 #define EFX_VF_BUFTBL_PER_VI                                    \
 260         ((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) *        \
 261          sizeof(efx_qword_t) / EFX_BUF_SIZE)
 262
 263 #ifdef CONFIG_SFC_SRIOV
 264
 265 static inline bool efx_sriov_wanted(struct efx_nic *efx)
 266 {
 267         return efx->vf_count != 0;
 268 }
 269 static inline bool efx_sriov_enabled(struct efx_nic *efx)
 270 {
 271         return efx->vf_init_count != 0;
 272 }
 273 static inline unsigned int efx_vf_size(struct efx_nic *efx)
 274 {
 275         return 1 << efx->vi_scale;
 276 }
 277
 278 extern int efx_init_sriov(void);
 279 extern void efx_sriov_probe(struct efx_nic *efx);
 280 extern int efx_sriov_init(struct efx_nic *efx);
 281 extern void efx_sriov_mac_address_changed(struct efx_nic *efx);
 282 extern void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event);
 283 extern void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event);
 284 extern void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event);
 285 extern void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq);
 286 extern void efx_sriov_flr(struct efx_nic *efx, unsigned flr);
 287 extern void efx_sriov_reset(struct efx_nic *efx);
 288 extern void efx_sriov_fini(struct efx_nic *efx);
 289 extern void efx_fini_sriov(void);
 290
 291 #else
 292
 293 static inline bool efx_sriov_wanted(struct efx_nic *efx) { return false; }
 294 static inline bool efx_sriov_enabled(struct efx_nic *efx) { return false; }
 295 static inline unsigned int efx_vf_size(struct efx_nic *efx) { return 0; }
 296
 297 static inline int efx_init_sriov(void) { return 0; }
 298 static inline void efx_sriov_probe(struct efx_nic *efx) {}
 299 static inline int efx_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; }
 300 static inline void efx_sriov_mac_address_changed(struct efx_nic *efx) {}
 301 static inline void efx_sriov_tx_flush_done(struct efx_nic *efx,
 302                                            efx_qword_t *event) {}
 303 static inline void efx_sriov_rx_flush_done(struct efx_nic *efx,
 304                                            efx_qword_t *event) {}
 305 static inline void efx_sriov_event(struct efx_channel *channel,
 306                                    efx_qword_t *event) {}
 307 static inline void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) {}
 308 static inline void efx_sriov_flr(struct efx_nic *efx, unsigned flr) {}
 309 static inline void efx_sriov_reset(struct efx_nic *efx) {}
 310 static inline void efx_sriov_fini(struct efx_nic *efx) {}
 311 static inline void efx_fini_sriov(void) {}
 312
 313 #endif
 314
 315 extern int efx_sriov_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
 316 extern int efx_sriov_set_vf_vlan(struct net_device *dev, int vf,
 317                                  u16 vlan, u8 qos);
 318 extern int efx_sriov_get_vf_config(struct net_device *dev, int vf,
 319                                    struct ifla_vf_info *ivf);
 320 extern int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf,
 321                                      bool spoofchk);
 322
 323 struct ethtool_ts_info;
 324 extern void efx_ptp_probe(struct efx_nic *efx);
 325 extern int efx_ptp_ioctl(struct efx_nic *efx, struct ifreq *ifr, int cmd);
 326 extern void efx_ptp_get_ts_info(struct efx_nic *efx,
 327                                 struct ethtool_ts_info *ts_info);
 328 extern bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
 329 extern int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
 330 extern void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
 331
 332 extern const struct efx_nic_type falcon_a1_nic_type;
 333 extern const struct efx_nic_type falcon_b0_nic_type;
 334 extern const struct efx_nic_type siena_a0_nic_type;
 335
 336 /**************************************************************************
 337  *
 338  * Externs
 339  *
 340  **************************************************************************
 341  */
 342
 343 extern int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
 344
 345 /* TX data path */
 346 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
 347 {
 348         return tx_queue->efx->type->tx_probe(tx_queue);
 349 }
 350 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
 351 {
 352         tx_queue->efx->type->tx_init(tx_queue);
 353 }
 354 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
 355 {
 356         tx_queue->efx->type->tx_remove(tx_queue);
 357 }
 358 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
 359 {
 360         tx_queue->efx->type->tx_write(tx_queue);
 361 }
 362
 363 /* RX data path */
 364 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
 365 {
 366         return rx_queue->efx->type->rx_probe(rx_queue);
 367 }
 368 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
 369 {
 370         rx_queue->efx->type->rx_init(rx_queue);
 371 }
 372 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
 373 {
 374         rx_queue->efx->type->rx_remove(rx_queue);
 375 }
 376 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
 377 {
 378         rx_queue->efx->type->rx_write(rx_queue);
 379 }
 380 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
 381 {
 382         rx_queue->efx->type->rx_defer_refill(rx_queue);
 383 }
 384
 385 /* Event data path */
 386 static inline int efx_nic_probe_eventq(struct efx_channel *channel)
 387 {
 388         return channel->efx->type->ev_probe(channel);
 389 }
 390 static inline void efx_nic_init_eventq(struct efx_channel *channel)
 391 {
 392         channel->efx->type->ev_init(channel);
 393 }
 394 static inline void efx_nic_fini_eventq(struct efx_channel *channel)
 395 {
 396         channel->efx->type->ev_fini(channel);
 397 }
 398 static inline void efx_nic_remove_eventq(struct efx_channel *channel)
 399 {
 400         channel->efx->type->ev_remove(channel);
 401 }
 402 static inline int
 403 efx_nic_process_eventq(struct efx_channel *channel, int quota)
 404 {
 405         return channel->efx->type->ev_process(channel, quota);
 406 }
 407 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
 408 {
 409         channel->efx->type->ev_read_ack(channel);
 410 }
 411 extern void efx_nic_event_test_start(struct efx_channel *channel);
 412
 413 /* Falcon/Siena queue operations */
 414 extern int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
 415 extern void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
 416 extern void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
 417 extern void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
 418 extern void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
 419 extern int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
 420 extern void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
 421 extern void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
 422 extern void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
 423 extern void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
 424 extern void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
 425 extern int efx_farch_ev_probe(struct efx_channel *channel);
 426 extern void efx_farch_ev_init(struct efx_channel *channel);
 427 extern void efx_farch_ev_fini(struct efx_channel *channel);
 428 extern void efx_farch_ev_remove(struct efx_channel *channel);
 429 extern int efx_farch_ev_process(struct efx_channel *channel, int quota);
 430 extern void efx_farch_ev_read_ack(struct efx_channel *channel);
 431 extern void efx_farch_ev_test_generate(struct efx_channel *channel);
 432
 433 /* Falcon/Siena filter operations */
 434 extern int efx_farch_filter_table_probe(struct efx_nic *efx);
 435 extern void efx_farch_filter_table_restore(struct efx_nic *efx);
 436 extern void efx_farch_filter_table_remove(struct efx_nic *efx);
 437 extern void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
 438 extern s32 efx_farch_filter_insert(struct efx_nic *efx,
 439                                    struct efx_filter_spec *spec, bool replace);
 440 extern int efx_farch_filter_remove_safe(struct efx_nic *efx,
 441                                         enum efx_filter_priority priority,
 442                                         u32 filter_id);
 443 extern int efx_farch_filter_get_safe(struct efx_nic *efx,
 444                                      enum efx_filter_priority priority,
 445                                      u32 filter_id, struct efx_filter_spec *);
 446 extern void efx_farch_filter_clear_rx(struct efx_nic *efx,
 447                                       enum efx_filter_priority priority);
 448 extern u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
 449                                           enum efx_filter_priority priority);
 450 extern u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
 451 extern s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
 452                                        enum efx_filter_priority priority,
 453                                        u32 *buf, u32 size);
 454 #ifdef CONFIG_RFS_ACCEL
 455 extern s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
 456                                        struct efx_filter_spec *spec);
 457 extern bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
 458                                             unsigned int index);
 459 #endif
 460 extern void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
 461
 462 extern bool efx_nic_event_present(struct efx_channel *channel);
 463
 464 /* Some statistics are computed as A - B where A and B each increase
 465  * linearly with some hardware counter(s) and the counters are read
 466  * asynchronously.  If the counters contributing to B are always read
 467  * after those contributing to A, the computed value may be lower than
 468  * the true value by some variable amount, and may decrease between
 469  * subsequent computations.
 470  *
 471  * We should never allow statistics to decrease or to exceed the true
 472  * value.  Since the computed value will never be greater than the
 473  * true value, we can achieve this by only storing the computed value
 474  * when it increases.
 475  */
 476 static inline void efx_update_diff_stat(u64 *stat, u64 diff)
 477 {
 478         if ((s64)(diff - *stat) > 0)
 479                 *stat = diff;
 480 }
 481
 482 /* Interrupts */
 483 extern int efx_nic_init_interrupt(struct efx_nic *efx);
 484 extern void efx_nic_irq_test_start(struct efx_nic *efx);
 485 extern void efx_nic_fini_interrupt(struct efx_nic *efx);
 486
 487 /* Falcon/Siena interrupts */
 488 extern void efx_farch_irq_enable_master(struct efx_nic *efx);
 489 extern void efx_farch_irq_test_generate(struct efx_nic *efx);
 490 extern void efx_farch_irq_disable_master(struct efx_nic *efx);
 491 extern irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
 492 extern irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
 493 extern irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
 494
 495 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
 496 {
 497         return ACCESS_ONCE(channel->event_test_cpu);
 498 }
 499 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
 500 {
 501         return ACCESS_ONCE(efx->last_irq_cpu);
 502 }
 503
 504 /* Global Resources */
 505 extern int efx_nic_flush_queues(struct efx_nic *efx);
 506 extern void siena_prepare_flush(struct efx_nic *efx);
 507 extern int efx_farch_fini_dmaq(struct efx_nic *efx);
 508 extern void siena_finish_flush(struct efx_nic *efx);
 509 extern void falcon_start_nic_stats(struct efx_nic *efx);
 510 extern void falcon_stop_nic_stats(struct efx_nic *efx);
 511 extern int falcon_reset_xaui(struct efx_nic *efx);
 512 extern void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
 513 extern void efx_farch_init_common(struct efx_nic *efx);
 514 static inline void efx_nic_push_rx_indir_table(struct efx_nic *efx)
 515 {
 516         efx->type->rx_push_indir_table(efx);
 517 }
 518 extern void efx_farch_rx_push_indir_table(struct efx_nic *efx);
 519
 520 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
 521                          unsigned int len, gfp_t gfp_flags);
 522 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
 523
 524 /* Tests */
 525 struct efx_farch_register_test {
 526         unsigned address;
 527         efx_oword_t mask;
 528 };
 529 extern int efx_farch_test_registers(struct efx_nic *efx,
 530                                     const struct efx_farch_register_test *regs,
 531                                     size_t n_regs);
 532
 533 extern size_t efx_nic_get_regs_len(struct efx_nic *efx);
 534 extern void efx_nic_get_regs(struct efx_nic *efx, void *buf);
 535
 536 #define EFX_MAX_FLUSH_TIME 5000
 537
 538 extern void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
 539                                      efx_qword_t *event);
 540
 541 #endif /* EFX_NIC_H */