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[deliverable/linux.git] / drivers / net / ethernet / sfc / siena.c
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
18 #include "bitfield.h"
19 #include "efx.h"
20 #include "nic.h"
21 #include "farch_regs.h"
22 #include "io.h"
23 #include "phy.h"
24 #include "workarounds.h"
25 #include "mcdi.h"
26 #include "mcdi_pcol.h"
27 #include "selftest.h"
28 #include "siena_sriov.h"
29
30 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31
32 static void siena_init_wol(struct efx_nic *efx);
33
34
35 static void siena_push_irq_moderation(struct efx_channel *channel)
36 {
37 efx_dword_t timer_cmd;
38
39 if (channel->irq_moderation)
40 EFX_POPULATE_DWORD_2(timer_cmd,
41 FRF_CZ_TC_TIMER_MODE,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
43 FRF_CZ_TC_TIMER_VAL,
44 channel->irq_moderation - 1);
45 else
46 EFX_POPULATE_DWORD_2(timer_cmd,
47 FRF_CZ_TC_TIMER_MODE,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
51 channel->channel);
52 }
53
54 void siena_prepare_flush(struct efx_nic *efx)
55 {
56 if (efx->fc_disable++ == 0)
57 efx_mcdi_set_mac(efx);
58 }
59
60 void siena_finish_flush(struct efx_nic *efx)
61 {
62 if (--efx->fc_disable == 0)
63 efx_mcdi_set_mac(efx);
64 }
65
66 static const struct efx_farch_register_test siena_register_tests[] = {
67 { FR_AZ_ADR_REGION,
68 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
69 { FR_CZ_USR_EV_CFG,
70 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
71 { FR_AZ_RX_CFG,
72 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
73 { FR_AZ_TX_CFG,
74 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
75 { FR_AZ_TX_RESERVED,
76 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
77 { FR_AZ_SRM_TX_DC_CFG,
78 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
79 { FR_AZ_RX_DC_CFG,
80 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
81 { FR_AZ_RX_DC_PF_WM,
82 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
83 { FR_BZ_DP_CTRL,
84 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
85 { FR_BZ_RX_RSS_TKEY,
86 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
87 { FR_CZ_RX_RSS_IPV6_REG1,
88 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
89 { FR_CZ_RX_RSS_IPV6_REG2,
90 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
91 { FR_CZ_RX_RSS_IPV6_REG3,
92 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
93 };
94
95 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
96 {
97 enum reset_type reset_method = RESET_TYPE_ALL;
98 int rc, rc2;
99
100 efx_reset_down(efx, reset_method);
101
102 /* Reset the chip immediately so that it is completely
103 * quiescent regardless of what any VF driver does.
104 */
105 rc = efx_mcdi_reset(efx, reset_method);
106 if (rc)
107 goto out;
108
109 tests->registers =
110 efx_farch_test_registers(efx, siena_register_tests,
111 ARRAY_SIZE(siena_register_tests))
112 ? -1 : 1;
113
114 rc = efx_mcdi_reset(efx, reset_method);
115 out:
116 rc2 = efx_reset_up(efx, reset_method, rc == 0);
117 return rc ? rc : rc2;
118 }
119
120 /**************************************************************************
121 *
122 * PTP
123 *
124 **************************************************************************
125 */
126
127 static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
128 {
129 _efx_writed(efx, cpu_to_le32(host_time),
130 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
131 }
132
133 static int siena_ptp_set_ts_config(struct efx_nic *efx,
134 struct hwtstamp_config *init)
135 {
136 int rc;
137
138 switch (init->rx_filter) {
139 case HWTSTAMP_FILTER_NONE:
140 /* if TX timestamping is still requested then leave PTP on */
141 return efx_ptp_change_mode(efx,
142 init->tx_type != HWTSTAMP_TX_OFF,
143 efx_ptp_get_mode(efx));
144 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
145 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
146 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
147 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
148 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
149 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
150 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
151 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
152 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
153 rc = efx_ptp_change_mode(efx, true,
154 MC_CMD_PTP_MODE_V2_ENHANCED);
155 /* bug 33070 - old versions of the firmware do not support the
156 * improved UUID filtering option. Similarly old versions of the
157 * application do not expect it to be enabled. If the firmware
158 * does not accept the enhanced mode, fall back to the standard
159 * PTP v2 UUID filtering. */
160 if (rc != 0)
161 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
162 return rc;
163 default:
164 return -ERANGE;
165 }
166 }
167
168 /**************************************************************************
169 *
170 * Device reset
171 *
172 **************************************************************************
173 */
174
175 static int siena_map_reset_flags(u32 *flags)
176 {
177 enum {
178 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
179 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
180 ETH_RESET_PHY),
181 SIENA_RESET_MC = (SIENA_RESET_PORT |
182 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
183 };
184
185 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
186 *flags &= ~SIENA_RESET_MC;
187 return RESET_TYPE_WORLD;
188 }
189
190 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
191 *flags &= ~SIENA_RESET_PORT;
192 return RESET_TYPE_ALL;
193 }
194
195 /* no invisible reset implemented */
196
197 return -EINVAL;
198 }
199
200 #ifdef CONFIG_EEH
201 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
202 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
203 * was written to minimise MMIO read (for latency) then a periodic call to check
204 * the EEH status of the device is required so that device recovery can happen
205 * in a timely fashion.
206 */
207 static void siena_monitor(struct efx_nic *efx)
208 {
209 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
210
211 eeh_dev_check_failure(eehdev);
212 }
213 #endif
214
215 static int siena_probe_nvconfig(struct efx_nic *efx)
216 {
217 u32 caps = 0;
218 int rc;
219
220 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
221
222 efx->timer_quantum_ns =
223 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
224 3072 : 6144; /* 768 cycles */
225 return rc;
226 }
227
228 static int siena_dimension_resources(struct efx_nic *efx)
229 {
230 /* Each port has a small block of internal SRAM dedicated to
231 * the buffer table and descriptor caches. In theory we can
232 * map both blocks to one port, but we don't.
233 */
234 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
235 return 0;
236 }
237
238 static unsigned int siena_mem_map_size(struct efx_nic *efx)
239 {
240 return FR_CZ_MC_TREG_SMEM +
241 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
242 }
243
244 static int siena_probe_nic(struct efx_nic *efx)
245 {
246 struct siena_nic_data *nic_data;
247 efx_oword_t reg;
248 int rc;
249
250 /* Allocate storage for hardware specific data */
251 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
252 if (!nic_data)
253 return -ENOMEM;
254 nic_data->efx = efx;
255 efx->nic_data = nic_data;
256
257 if (efx_farch_fpga_ver(efx) != 0) {
258 netif_err(efx, probe, efx->net_dev,
259 "Siena FPGA not supported\n");
260 rc = -ENODEV;
261 goto fail1;
262 }
263
264 efx->max_channels = EFX_MAX_CHANNELS;
265
266 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
267 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
268
269 rc = efx_mcdi_init(efx);
270 if (rc)
271 goto fail1;
272
273 /* Now we can reset the NIC */
274 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
275 if (rc) {
276 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
277 goto fail3;
278 }
279
280 siena_init_wol(efx);
281
282 /* Allocate memory for INT_KER */
283 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
284 GFP_KERNEL);
285 if (rc)
286 goto fail4;
287 BUG_ON(efx->irq_status.dma_addr & 0x0f);
288
289 netif_dbg(efx, probe, efx->net_dev,
290 "INT_KER at %llx (virt %p phys %llx)\n",
291 (unsigned long long)efx->irq_status.dma_addr,
292 efx->irq_status.addr,
293 (unsigned long long)virt_to_phys(efx->irq_status.addr));
294
295 /* Read in the non-volatile configuration */
296 rc = siena_probe_nvconfig(efx);
297 if (rc == -EINVAL) {
298 netif_err(efx, probe, efx->net_dev,
299 "NVRAM is invalid therefore using defaults\n");
300 efx->phy_type = PHY_TYPE_NONE;
301 efx->mdio.prtad = MDIO_PRTAD_NONE;
302 } else if (rc) {
303 goto fail5;
304 }
305
306 rc = efx_mcdi_mon_probe(efx);
307 if (rc)
308 goto fail5;
309
310 #ifdef CONFIG_SFC_SRIOV
311 efx_siena_sriov_probe(efx);
312 #endif
313 efx_ptp_defer_probe_with_channel(efx);
314
315 return 0;
316
317 fail5:
318 efx_nic_free_buffer(efx, &efx->irq_status);
319 fail4:
320 fail3:
321 efx_mcdi_fini(efx);
322 fail1:
323 kfree(efx->nic_data);
324 return rc;
325 }
326
327 static void siena_rx_push_rss_config(struct efx_nic *efx)
328 {
329 efx_oword_t temp;
330
331 /* Set hash key for IPv4 */
332 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
333 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
334
335 /* Enable IPv6 RSS */
336 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
337 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
338 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
339 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
340 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
341 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
342 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
343 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
344 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
345 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
346 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
347 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
348
349 efx_farch_rx_push_indir_table(efx);
350 }
351
352 /* This call performs hardware-specific global initialisation, such as
353 * defining the descriptor cache sizes and number of RSS channels.
354 * It does not set up any buffers, descriptor rings or event queues.
355 */
356 static int siena_init_nic(struct efx_nic *efx)
357 {
358 efx_oword_t temp;
359 int rc;
360
361 /* Recover from a failed assertion post-reset */
362 rc = efx_mcdi_handle_assertion(efx);
363 if (rc)
364 return rc;
365
366 /* Squash TX of packets of 16 bytes or less */
367 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
368 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
369 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
370
371 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
372 * descriptors (which is bad).
373 */
374 efx_reado(efx, &temp, FR_AZ_TX_CFG);
375 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
376 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
377 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
378
379 efx_reado(efx, &temp, FR_AZ_RX_CFG);
380 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
381 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
382 /* Enable hash insertion. This is broken for the 'Falcon' hash
383 * if IPv6 hashing is also enabled, so also select Toeplitz
384 * TCP/IPv4 and IPv4 hashes. */
385 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
386 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
387 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
388 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
389 EFX_RX_USR_BUF_SIZE >> 5);
390 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
391
392 siena_rx_push_rss_config(efx);
393
394 /* Enable event logging */
395 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
396 if (rc)
397 return rc;
398
399 /* Set destination of both TX and RX Flush events */
400 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
401 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
402
403 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
404 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
405
406 efx_farch_init_common(efx);
407 return 0;
408 }
409
410 static void siena_remove_nic(struct efx_nic *efx)
411 {
412 efx_mcdi_mon_remove(efx);
413
414 efx_nic_free_buffer(efx, &efx->irq_status);
415
416 efx_mcdi_reset(efx, RESET_TYPE_ALL);
417
418 efx_mcdi_fini(efx);
419
420 /* Tear down the private nic state */
421 kfree(efx->nic_data);
422 efx->nic_data = NULL;
423 }
424
425 #define SIENA_DMA_STAT(ext_name, mcdi_name) \
426 [SIENA_STAT_ ## ext_name] = \
427 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
428 #define SIENA_OTHER_STAT(ext_name) \
429 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
430 #define GENERIC_SW_STAT(ext_name) \
431 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
432
433 static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
434 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
435 SIENA_OTHER_STAT(tx_good_bytes),
436 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
437 SIENA_DMA_STAT(tx_packets, TX_PKTS),
438 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
439 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
440 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
441 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
442 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
443 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
444 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
445 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
446 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
447 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
448 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
449 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
450 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
451 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
452 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
453 SIENA_OTHER_STAT(tx_collision),
454 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
455 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
456 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
457 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
458 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
459 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
460 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
461 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
462 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
463 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
464 SIENA_OTHER_STAT(rx_good_bytes),
465 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
466 SIENA_DMA_STAT(rx_packets, RX_PKTS),
467 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
468 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
469 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
470 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
471 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
472 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
473 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
474 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
475 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
476 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
477 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
478 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
479 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
480 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
481 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
482 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
483 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
484 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
485 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
486 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
487 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
488 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
489 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
490 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
491 GENERIC_SW_STAT(rx_nodesc_trunc),
492 GENERIC_SW_STAT(rx_noskb_drops),
493 };
494 static const unsigned long siena_stat_mask[] = {
495 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
496 };
497
498 static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
499 {
500 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
501 siena_stat_mask, names);
502 }
503
504 static int siena_try_update_nic_stats(struct efx_nic *efx)
505 {
506 struct siena_nic_data *nic_data = efx->nic_data;
507 u64 *stats = nic_data->stats;
508 __le64 *dma_stats;
509 __le64 generation_start, generation_end;
510
511 dma_stats = efx->stats_buffer.addr;
512
513 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
514 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
515 return 0;
516 rmb();
517 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
518 stats, efx->stats_buffer.addr, false);
519 rmb();
520 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
521 if (generation_end != generation_start)
522 return -EAGAIN;
523
524 /* Update derived statistics */
525 efx_nic_fix_nodesc_drop_stat(efx,
526 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
527 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
528 stats[SIENA_STAT_tx_bytes] -
529 stats[SIENA_STAT_tx_bad_bytes]);
530 stats[SIENA_STAT_tx_collision] =
531 stats[SIENA_STAT_tx_single_collision] +
532 stats[SIENA_STAT_tx_multiple_collision] +
533 stats[SIENA_STAT_tx_excessive_collision] +
534 stats[SIENA_STAT_tx_late_collision];
535 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
536 stats[SIENA_STAT_rx_bytes] -
537 stats[SIENA_STAT_rx_bad_bytes]);
538 efx_update_sw_stats(efx, stats);
539 return 0;
540 }
541
542 static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
543 struct rtnl_link_stats64 *core_stats)
544 {
545 struct siena_nic_data *nic_data = efx->nic_data;
546 u64 *stats = nic_data->stats;
547 int retry;
548
549 /* If we're unlucky enough to read statistics wduring the DMA, wait
550 * up to 10ms for it to finish (typically takes <500us) */
551 for (retry = 0; retry < 100; ++retry) {
552 if (siena_try_update_nic_stats(efx) == 0)
553 break;
554 udelay(100);
555 }
556
557 if (full_stats)
558 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
559
560 if (core_stats) {
561 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
562 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
563 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
564 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
565 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
566 stats[GENERIC_STAT_rx_nodesc_trunc] +
567 stats[GENERIC_STAT_rx_noskb_drops];
568 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
569 core_stats->collisions = stats[SIENA_STAT_tx_collision];
570 core_stats->rx_length_errors =
571 stats[SIENA_STAT_rx_gtjumbo] +
572 stats[SIENA_STAT_rx_length_error];
573 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
574 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
575 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
576 core_stats->tx_window_errors =
577 stats[SIENA_STAT_tx_late_collision];
578
579 core_stats->rx_errors = (core_stats->rx_length_errors +
580 core_stats->rx_crc_errors +
581 core_stats->rx_frame_errors +
582 stats[SIENA_STAT_rx_symbol_error]);
583 core_stats->tx_errors = (core_stats->tx_window_errors +
584 stats[SIENA_STAT_tx_bad]);
585 }
586
587 return SIENA_STAT_COUNT;
588 }
589
590 static int siena_mac_reconfigure(struct efx_nic *efx)
591 {
592 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
593 int rc;
594
595 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
596 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
597 sizeof(efx->multicast_hash));
598
599 efx_farch_filter_sync_rx_mode(efx);
600
601 WARN_ON(!mutex_is_locked(&efx->mac_lock));
602
603 rc = efx_mcdi_set_mac(efx);
604 if (rc != 0)
605 return rc;
606
607 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
608 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
609 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
610 inbuf, sizeof(inbuf), NULL, 0, NULL);
611 }
612
613 /**************************************************************************
614 *
615 * Wake on LAN
616 *
617 **************************************************************************
618 */
619
620 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
621 {
622 struct siena_nic_data *nic_data = efx->nic_data;
623
624 wol->supported = WAKE_MAGIC;
625 if (nic_data->wol_filter_id != -1)
626 wol->wolopts = WAKE_MAGIC;
627 else
628 wol->wolopts = 0;
629 memset(&wol->sopass, 0, sizeof(wol->sopass));
630 }
631
632
633 static int siena_set_wol(struct efx_nic *efx, u32 type)
634 {
635 struct siena_nic_data *nic_data = efx->nic_data;
636 int rc;
637
638 if (type & ~WAKE_MAGIC)
639 return -EINVAL;
640
641 if (type & WAKE_MAGIC) {
642 if (nic_data->wol_filter_id != -1)
643 efx_mcdi_wol_filter_remove(efx,
644 nic_data->wol_filter_id);
645 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
646 &nic_data->wol_filter_id);
647 if (rc)
648 goto fail;
649
650 pci_wake_from_d3(efx->pci_dev, true);
651 } else {
652 rc = efx_mcdi_wol_filter_reset(efx);
653 nic_data->wol_filter_id = -1;
654 pci_wake_from_d3(efx->pci_dev, false);
655 if (rc)
656 goto fail;
657 }
658
659 return 0;
660 fail:
661 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
662 __func__, type, rc);
663 return rc;
664 }
665
666
667 static void siena_init_wol(struct efx_nic *efx)
668 {
669 struct siena_nic_data *nic_data = efx->nic_data;
670 int rc;
671
672 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
673
674 if (rc != 0) {
675 /* If it failed, attempt to get into a synchronised
676 * state with MC by resetting any set WoL filters */
677 efx_mcdi_wol_filter_reset(efx);
678 nic_data->wol_filter_id = -1;
679 } else if (nic_data->wol_filter_id != -1) {
680 pci_wake_from_d3(efx->pci_dev, true);
681 }
682 }
683
684 /**************************************************************************
685 *
686 * MCDI
687 *
688 **************************************************************************
689 */
690
691 #define MCDI_PDU(efx) \
692 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
693 #define MCDI_DOORBELL(efx) \
694 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
695 #define MCDI_STATUS(efx) \
696 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
697
698 static void siena_mcdi_request(struct efx_nic *efx,
699 const efx_dword_t *hdr, size_t hdr_len,
700 const efx_dword_t *sdu, size_t sdu_len)
701 {
702 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
703 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
704 unsigned int i;
705 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
706
707 EFX_BUG_ON_PARANOID(hdr_len != 4);
708
709 efx_writed(efx, hdr, pdu);
710
711 for (i = 0; i < inlen_dw; i++)
712 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
713
714 /* Ensure the request is written out before the doorbell */
715 wmb();
716
717 /* ring the doorbell with a distinctive value */
718 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
719 }
720
721 static bool siena_mcdi_poll_response(struct efx_nic *efx)
722 {
723 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
724 efx_dword_t hdr;
725
726 efx_readd(efx, &hdr, pdu);
727
728 /* All 1's indicates that shared memory is in reset (and is
729 * not a valid hdr). Wait for it to come out reset before
730 * completing the command
731 */
732 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
733 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
734 }
735
736 static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
737 size_t offset, size_t outlen)
738 {
739 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
740 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
741 int i;
742
743 for (i = 0; i < outlen_dw; i++)
744 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
745 }
746
747 static int siena_mcdi_poll_reboot(struct efx_nic *efx)
748 {
749 struct siena_nic_data *nic_data = efx->nic_data;
750 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
751 efx_dword_t reg;
752 u32 value;
753
754 efx_readd(efx, &reg, addr);
755 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
756
757 if (value == 0)
758 return 0;
759
760 EFX_ZERO_DWORD(reg);
761 efx_writed(efx, &reg, addr);
762
763 /* MAC statistics have been cleared on the NIC; clear the local
764 * copies that we update with efx_update_diff_stat().
765 */
766 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
767 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
768
769 if (value == MC_STATUS_DWORD_ASSERT)
770 return -EINTR;
771 else
772 return -EIO;
773 }
774
775 /**************************************************************************
776 *
777 * MTD
778 *
779 **************************************************************************
780 */
781
782 #ifdef CONFIG_SFC_MTD
783
784 struct siena_nvram_type_info {
785 int port;
786 const char *name;
787 };
788
789 static const struct siena_nvram_type_info siena_nvram_types[] = {
790 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
791 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
792 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
793 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
794 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
795 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
796 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
797 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
798 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
799 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
800 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
801 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
802 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
803 };
804
805 static int siena_mtd_probe_partition(struct efx_nic *efx,
806 struct efx_mcdi_mtd_partition *part,
807 unsigned int type)
808 {
809 const struct siena_nvram_type_info *info;
810 size_t size, erase_size;
811 bool protected;
812 int rc;
813
814 if (type >= ARRAY_SIZE(siena_nvram_types) ||
815 siena_nvram_types[type].name == NULL)
816 return -ENODEV;
817
818 info = &siena_nvram_types[type];
819
820 if (info->port != efx_port_num(efx))
821 return -ENODEV;
822
823 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
824 if (rc)
825 return rc;
826 if (protected)
827 return -ENODEV; /* hide it */
828
829 part->nvram_type = type;
830 part->common.dev_type_name = "Siena NVRAM manager";
831 part->common.type_name = info->name;
832
833 part->common.mtd.type = MTD_NORFLASH;
834 part->common.mtd.flags = MTD_CAP_NORFLASH;
835 part->common.mtd.size = size;
836 part->common.mtd.erasesize = erase_size;
837
838 return 0;
839 }
840
841 static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
842 struct efx_mcdi_mtd_partition *parts,
843 size_t n_parts)
844 {
845 uint16_t fw_subtype_list[
846 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
847 size_t i;
848 int rc;
849
850 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
851 if (rc)
852 return rc;
853
854 for (i = 0; i < n_parts; i++)
855 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
856
857 return 0;
858 }
859
860 static int siena_mtd_probe(struct efx_nic *efx)
861 {
862 struct efx_mcdi_mtd_partition *parts;
863 u32 nvram_types;
864 unsigned int type;
865 size_t n_parts;
866 int rc;
867
868 ASSERT_RTNL();
869
870 rc = efx_mcdi_nvram_types(efx, &nvram_types);
871 if (rc)
872 return rc;
873
874 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
875 if (!parts)
876 return -ENOMEM;
877
878 type = 0;
879 n_parts = 0;
880
881 while (nvram_types != 0) {
882 if (nvram_types & 1) {
883 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
884 type);
885 if (rc == 0)
886 n_parts++;
887 else if (rc != -ENODEV)
888 goto fail;
889 }
890 type++;
891 nvram_types >>= 1;
892 }
893
894 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
895 if (rc)
896 goto fail;
897
898 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
899 fail:
900 if (rc)
901 kfree(parts);
902 return rc;
903 }
904
905 #endif /* CONFIG_SFC_MTD */
906
907 /**************************************************************************
908 *
909 * Revision-dependent attributes used by efx.c and nic.c
910 *
911 **************************************************************************
912 */
913
914 const struct efx_nic_type siena_a0_nic_type = {
915 .mem_map_size = siena_mem_map_size,
916 .probe = siena_probe_nic,
917 .remove = siena_remove_nic,
918 .init = siena_init_nic,
919 .dimension_resources = siena_dimension_resources,
920 .fini = efx_port_dummy_op_void,
921 #ifdef CONFIG_EEH
922 .monitor = siena_monitor,
923 #else
924 .monitor = NULL,
925 #endif
926 .map_reset_reason = efx_mcdi_map_reset_reason,
927 .map_reset_flags = siena_map_reset_flags,
928 .reset = efx_mcdi_reset,
929 .probe_port = efx_mcdi_port_probe,
930 .remove_port = efx_mcdi_port_remove,
931 .fini_dmaq = efx_farch_fini_dmaq,
932 .prepare_flush = siena_prepare_flush,
933 .finish_flush = siena_finish_flush,
934 .prepare_flr = efx_port_dummy_op_void,
935 .finish_flr = efx_farch_finish_flr,
936 .describe_stats = siena_describe_nic_stats,
937 .update_stats = siena_update_nic_stats,
938 .start_stats = efx_mcdi_mac_start_stats,
939 .pull_stats = efx_mcdi_mac_pull_stats,
940 .stop_stats = efx_mcdi_mac_stop_stats,
941 .set_id_led = efx_mcdi_set_id_led,
942 .push_irq_moderation = siena_push_irq_moderation,
943 .reconfigure_mac = siena_mac_reconfigure,
944 .check_mac_fault = efx_mcdi_mac_check_fault,
945 .reconfigure_port = efx_mcdi_port_reconfigure,
946 .get_wol = siena_get_wol,
947 .set_wol = siena_set_wol,
948 .resume_wol = siena_init_wol,
949 .test_chip = siena_test_chip,
950 .test_nvram = efx_mcdi_nvram_test_all,
951 .mcdi_request = siena_mcdi_request,
952 .mcdi_poll_response = siena_mcdi_poll_response,
953 .mcdi_read_response = siena_mcdi_read_response,
954 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
955 .irq_enable_master = efx_farch_irq_enable_master,
956 .irq_test_generate = efx_farch_irq_test_generate,
957 .irq_disable_non_ev = efx_farch_irq_disable_master,
958 .irq_handle_msi = efx_farch_msi_interrupt,
959 .irq_handle_legacy = efx_farch_legacy_interrupt,
960 .tx_probe = efx_farch_tx_probe,
961 .tx_init = efx_farch_tx_init,
962 .tx_remove = efx_farch_tx_remove,
963 .tx_write = efx_farch_tx_write,
964 .rx_push_rss_config = siena_rx_push_rss_config,
965 .rx_probe = efx_farch_rx_probe,
966 .rx_init = efx_farch_rx_init,
967 .rx_remove = efx_farch_rx_remove,
968 .rx_write = efx_farch_rx_write,
969 .rx_defer_refill = efx_farch_rx_defer_refill,
970 .ev_probe = efx_farch_ev_probe,
971 .ev_init = efx_farch_ev_init,
972 .ev_fini = efx_farch_ev_fini,
973 .ev_remove = efx_farch_ev_remove,
974 .ev_process = efx_farch_ev_process,
975 .ev_read_ack = efx_farch_ev_read_ack,
976 .ev_test_generate = efx_farch_ev_test_generate,
977 .filter_table_probe = efx_farch_filter_table_probe,
978 .filter_table_restore = efx_farch_filter_table_restore,
979 .filter_table_remove = efx_farch_filter_table_remove,
980 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
981 .filter_insert = efx_farch_filter_insert,
982 .filter_remove_safe = efx_farch_filter_remove_safe,
983 .filter_get_safe = efx_farch_filter_get_safe,
984 .filter_clear_rx = efx_farch_filter_clear_rx,
985 .filter_count_rx_used = efx_farch_filter_count_rx_used,
986 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
987 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
988 #ifdef CONFIG_RFS_ACCEL
989 .filter_rfs_insert = efx_farch_filter_rfs_insert,
990 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
991 #endif
992 #ifdef CONFIG_SFC_MTD
993 .mtd_probe = siena_mtd_probe,
994 .mtd_rename = efx_mcdi_mtd_rename,
995 .mtd_read = efx_mcdi_mtd_read,
996 .mtd_erase = efx_mcdi_mtd_erase,
997 .mtd_write = efx_mcdi_mtd_write,
998 .mtd_sync = efx_mcdi_mtd_sync,
999 #endif
1000 .ptp_write_host_time = siena_ptp_write_host_time,
1001 .ptp_set_ts_config = siena_ptp_set_ts_config,
1002 #ifdef CONFIG_SFC_SRIOV
1003 .sriov_configure = efx_siena_sriov_configure,
1004 .sriov_init = efx_siena_sriov_init,
1005 .sriov_fini = efx_siena_sriov_fini,
1006 .sriov_mac_address_changed = efx_siena_sriov_mac_address_changed,
1007 .sriov_wanted = efx_siena_sriov_wanted,
1008 .sriov_reset = efx_siena_sriov_reset,
1009 .sriov_flr = efx_siena_sriov_flr,
1010 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1011 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1012 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1013 .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
1014 .vswitching_probe = efx_port_dummy_op_int,
1015 .vswitching_restore = efx_port_dummy_op_int,
1016 .vswitching_remove = efx_port_dummy_op_void,
1017 #endif
1018
1019 .revision = EFX_REV_SIENA_A0,
1020 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1021 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1022 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1023 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1024 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1025 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1026 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1027 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
1028 .rx_buffer_padding = 0,
1029 .can_rx_scatter = true,
1030 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1031 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
1032 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1033 NETIF_F_RXHASH | NETIF_F_NTUPLE),
1034 .mcdi_max_ver = 1,
1035 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
1036 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1037 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
1038 1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC |
1039 1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ |
1040 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT |
1041 1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC |
1042 1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ),
1043 };
Linux kernel - Deliverables
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