1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2010 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/pci.h>
12 #include <linux/tcp.h>
15 #include <linux/ipv6.h>
16 #include <linux/slab.h>
18 #include <linux/if_ether.h>
19 #include <linux/highmem.h>
20 #include "net_driver.h"
23 #include "workarounds.h"
25 static void efx_dequeue_buffer(struct efx_tx_queue
*tx_queue
,
26 struct efx_tx_buffer
*buffer
,
27 unsigned int *pkts_compl
,
28 unsigned int *bytes_compl
)
30 if (buffer
->unmap_len
) {
31 struct device
*dma_dev
= &tx_queue
->efx
->pci_dev
->dev
;
32 dma_addr_t unmap_addr
= (buffer
->dma_addr
+ buffer
->len
-
34 if (buffer
->flags
& EFX_TX_BUF_MAP_SINGLE
)
35 dma_unmap_single(dma_dev
, unmap_addr
, buffer
->unmap_len
,
38 dma_unmap_page(dma_dev
, unmap_addr
, buffer
->unmap_len
,
40 buffer
->unmap_len
= 0;
43 if (buffer
->flags
& EFX_TX_BUF_SKB
) {
45 (*bytes_compl
) += buffer
->skb
->len
;
46 dev_kfree_skb_any((struct sk_buff
*) buffer
->skb
);
47 netif_vdbg(tx_queue
->efx
, tx_done
, tx_queue
->efx
->net_dev
,
48 "TX queue %d transmission id %x complete\n",
49 tx_queue
->queue
, tx_queue
->read_count
);
50 } else if (buffer
->flags
& EFX_TX_BUF_HEAP
) {
51 kfree(buffer
->heap_buf
);
58 static int efx_enqueue_skb_tso(struct efx_tx_queue
*tx_queue
,
61 static inline unsigned
62 efx_max_tx_len(struct efx_nic
*efx
, dma_addr_t dma_addr
)
64 /* Depending on the NIC revision, we can use descriptor
65 * lengths up to 8K or 8K-1. However, since PCI Express
66 * devices must split read requests at 4K boundaries, there is
67 * little benefit from using descriptors that cross those
68 * boundaries and we keep things simple by not doing so.
70 unsigned len
= (~dma_addr
& (EFX_PAGE_SIZE
- 1)) + 1;
72 /* Work around hardware bug for unaligned buffers. */
73 if (EFX_WORKAROUND_5391(efx
) && (dma_addr
& 0xf))
74 len
= min_t(unsigned, len
, 512 - (dma_addr
& 0xf));
79 unsigned int efx_tx_max_skb_descs(struct efx_nic
*efx
)
81 /* Header and payload descriptor for each output segment, plus
82 * one for every input fragment boundary within a segment
84 unsigned int max_descs
= EFX_TSO_MAX_SEGS
* 2 + MAX_SKB_FRAGS
;
86 /* Possibly one more per segment for the alignment workaround */
87 if (EFX_WORKAROUND_5391(efx
))
88 max_descs
+= EFX_TSO_MAX_SEGS
;
90 /* Possibly more for PCIe page boundaries within input fragments */
91 if (PAGE_SIZE
> EFX_PAGE_SIZE
)
92 max_descs
+= max_t(unsigned int, MAX_SKB_FRAGS
,
93 DIV_ROUND_UP(GSO_MAX_SIZE
, EFX_PAGE_SIZE
));
98 /* Get partner of a TX queue, seen as part of the same net core queue */
99 static struct efx_tx_queue
*efx_tx_queue_partner(struct efx_tx_queue
*tx_queue
)
101 if (tx_queue
->queue
& EFX_TXQ_TYPE_OFFLOAD
)
102 return tx_queue
- EFX_TXQ_TYPE_OFFLOAD
;
104 return tx_queue
+ EFX_TXQ_TYPE_OFFLOAD
;
107 static void efx_tx_maybe_stop_queue(struct efx_tx_queue
*txq1
)
109 /* We need to consider both queues that the net core sees as one */
110 struct efx_tx_queue
*txq2
= efx_tx_queue_partner(txq1
);
111 struct efx_nic
*efx
= txq1
->efx
;
112 unsigned int fill_level
;
114 fill_level
= max(txq1
->insert_count
- txq1
->old_read_count
,
115 txq2
->insert_count
- txq2
->old_read_count
);
116 if (likely(fill_level
< efx
->txq_stop_thresh
))
119 /* We used the stale old_read_count above, which gives us a
120 * pessimistic estimate of the fill level (which may even
121 * validly be >= efx->txq_entries). Now try again using
122 * read_count (more likely to be a cache miss).
124 * If we read read_count and then conditionally stop the
125 * queue, it is possible for the completion path to race with
126 * us and complete all outstanding descriptors in the middle,
127 * after which there will be no more completions to wake it.
128 * Therefore we stop the queue first, then read read_count
129 * (with a memory barrier to ensure the ordering), then
130 * restart the queue if the fill level turns out to be low
133 netif_tx_stop_queue(txq1
->core_txq
);
135 txq1
->old_read_count
= ACCESS_ONCE(txq1
->read_count
);
136 txq2
->old_read_count
= ACCESS_ONCE(txq2
->read_count
);
138 fill_level
= max(txq1
->insert_count
- txq1
->old_read_count
,
139 txq2
->insert_count
- txq2
->old_read_count
);
140 EFX_BUG_ON_PARANOID(fill_level
>= efx
->txq_entries
);
141 if (likely(fill_level
< efx
->txq_stop_thresh
)) {
143 if (likely(!efx
->loopback_selftest
))
144 netif_tx_start_queue(txq1
->core_txq
);
149 * Add a socket buffer to a TX queue
151 * This maps all fragments of a socket buffer for DMA and adds them to
152 * the TX queue. The queue's insert pointer will be incremented by
153 * the number of fragments in the socket buffer.
155 * If any DMA mapping fails, any mapped fragments will be unmapped,
156 * the queue's insert pointer will be restored to its original value.
158 * This function is split out from efx_hard_start_xmit to allow the
159 * loopback test to direct packets via specific TX queues.
161 * Returns NETDEV_TX_OK.
162 * You must hold netif_tx_lock() to call this function.
164 netdev_tx_t
efx_enqueue_skb(struct efx_tx_queue
*tx_queue
, struct sk_buff
*skb
)
166 struct efx_nic
*efx
= tx_queue
->efx
;
167 struct device
*dma_dev
= &efx
->pci_dev
->dev
;
168 struct efx_tx_buffer
*buffer
;
169 skb_frag_t
*fragment
;
170 unsigned int len
, unmap_len
= 0, insert_ptr
;
171 dma_addr_t dma_addr
, unmap_addr
= 0;
172 unsigned int dma_len
;
173 unsigned short dma_flags
;
176 EFX_BUG_ON_PARANOID(tx_queue
->write_count
!= tx_queue
->insert_count
);
178 if (skb_shinfo(skb
)->gso_size
)
179 return efx_enqueue_skb_tso(tx_queue
, skb
);
181 /* Get size of the initial fragment */
182 len
= skb_headlen(skb
);
184 /* Pad if necessary */
185 if (EFX_WORKAROUND_15592(efx
) && skb
->len
<= 32) {
186 EFX_BUG_ON_PARANOID(skb
->data_len
);
188 if (skb_pad(skb
, len
- skb
->len
))
192 /* Map for DMA. Use dma_map_single rather than dma_map_page
193 * since this is more efficient on machines with sparse
196 dma_flags
= EFX_TX_BUF_MAP_SINGLE
;
197 dma_addr
= dma_map_single(dma_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
199 /* Process all fragments */
201 if (unlikely(dma_mapping_error(dma_dev
, dma_addr
)))
204 /* Store fields for marking in the per-fragment final
207 unmap_addr
= dma_addr
;
209 /* Add to TX queue, splitting across DMA boundaries */
211 insert_ptr
= tx_queue
->insert_count
& tx_queue
->ptr_mask
;
212 buffer
= &tx_queue
->buffer
[insert_ptr
];
213 EFX_BUG_ON_PARANOID(buffer
->flags
);
214 EFX_BUG_ON_PARANOID(buffer
->len
);
215 EFX_BUG_ON_PARANOID(buffer
->unmap_len
);
217 dma_len
= efx_max_tx_len(efx
, dma_addr
);
218 if (likely(dma_len
>= len
))
221 /* Fill out per descriptor fields */
222 buffer
->len
= dma_len
;
223 buffer
->dma_addr
= dma_addr
;
224 buffer
->flags
= EFX_TX_BUF_CONT
;
227 ++tx_queue
->insert_count
;
230 /* Transfer ownership of the unmapping to the final buffer */
231 buffer
->flags
= EFX_TX_BUF_CONT
| dma_flags
;
232 buffer
->unmap_len
= unmap_len
;
235 /* Get address and size of next fragment */
236 if (i
>= skb_shinfo(skb
)->nr_frags
)
238 fragment
= &skb_shinfo(skb
)->frags
[i
];
239 len
= skb_frag_size(fragment
);
243 dma_addr
= skb_frag_dma_map(dma_dev
, fragment
, 0, len
,
247 /* Transfer ownership of the skb to the final buffer */
249 buffer
->flags
= EFX_TX_BUF_SKB
| dma_flags
;
251 netdev_tx_sent_queue(tx_queue
->core_txq
, skb
->len
);
253 /* Pass off to hardware */
254 efx_nic_push_buffers(tx_queue
);
256 efx_tx_maybe_stop_queue(tx_queue
);
261 netif_err(efx
, tx_err
, efx
->net_dev
,
262 " TX queue %d could not map skb with %d bytes %d "
263 "fragments for DMA\n", tx_queue
->queue
, skb
->len
,
264 skb_shinfo(skb
)->nr_frags
+ 1);
266 /* Mark the packet as transmitted, and free the SKB ourselves */
267 dev_kfree_skb_any(skb
);
269 /* Work backwards until we hit the original insert pointer value */
270 while (tx_queue
->insert_count
!= tx_queue
->write_count
) {
271 unsigned int pkts_compl
= 0, bytes_compl
= 0;
272 --tx_queue
->insert_count
;
273 insert_ptr
= tx_queue
->insert_count
& tx_queue
->ptr_mask
;
274 buffer
= &tx_queue
->buffer
[insert_ptr
];
275 efx_dequeue_buffer(tx_queue
, buffer
, &pkts_compl
, &bytes_compl
);
278 /* Free the fragment we were mid-way through pushing */
280 if (dma_flags
& EFX_TX_BUF_MAP_SINGLE
)
281 dma_unmap_single(dma_dev
, unmap_addr
, unmap_len
,
284 dma_unmap_page(dma_dev
, unmap_addr
, unmap_len
,
291 /* Remove packets from the TX queue
293 * This removes packets from the TX queue, up to and including the
296 static void efx_dequeue_buffers(struct efx_tx_queue
*tx_queue
,
298 unsigned int *pkts_compl
,
299 unsigned int *bytes_compl
)
301 struct efx_nic
*efx
= tx_queue
->efx
;
302 unsigned int stop_index
, read_ptr
;
304 stop_index
= (index
+ 1) & tx_queue
->ptr_mask
;
305 read_ptr
= tx_queue
->read_count
& tx_queue
->ptr_mask
;
307 while (read_ptr
!= stop_index
) {
308 struct efx_tx_buffer
*buffer
= &tx_queue
->buffer
[read_ptr
];
309 if (unlikely(buffer
->len
== 0)) {
310 netif_err(efx
, tx_err
, efx
->net_dev
,
311 "TX queue %d spurious TX completion id %x\n",
312 tx_queue
->queue
, read_ptr
);
313 efx_schedule_reset(efx
, RESET_TYPE_TX_SKIP
);
317 efx_dequeue_buffer(tx_queue
, buffer
, pkts_compl
, bytes_compl
);
319 ++tx_queue
->read_count
;
320 read_ptr
= tx_queue
->read_count
& tx_queue
->ptr_mask
;
324 /* Initiate a packet transmission. We use one channel per CPU
325 * (sharing when we have more CPUs than channels). On Falcon, the TX
326 * completion events will be directed back to the CPU that transmitted
327 * the packet, which should be cache-efficient.
329 * Context: non-blocking.
330 * Note that returning anything other than NETDEV_TX_OK will cause the
331 * OS to free the skb.
333 netdev_tx_t
efx_hard_start_xmit(struct sk_buff
*skb
,
334 struct net_device
*net_dev
)
336 struct efx_nic
*efx
= netdev_priv(net_dev
);
337 struct efx_tx_queue
*tx_queue
;
338 unsigned index
, type
;
340 EFX_WARN_ON_PARANOID(!netif_device_present(net_dev
));
342 /* PTP "event" packet */
343 if (unlikely(efx_xmit_with_hwtstamp(skb
)) &&
344 unlikely(efx_ptp_is_ptp_tx(efx
, skb
))) {
345 return efx_ptp_tx(efx
, skb
);
348 index
= skb_get_queue_mapping(skb
);
349 type
= skb
->ip_summed
== CHECKSUM_PARTIAL
? EFX_TXQ_TYPE_OFFLOAD
: 0;
350 if (index
>= efx
->n_tx_channels
) {
351 index
-= efx
->n_tx_channels
;
352 type
|= EFX_TXQ_TYPE_HIGHPRI
;
354 tx_queue
= efx_get_tx_queue(efx
, index
, type
);
356 return efx_enqueue_skb(tx_queue
, skb
);
359 void efx_init_tx_queue_core_txq(struct efx_tx_queue
*tx_queue
)
361 struct efx_nic
*efx
= tx_queue
->efx
;
363 /* Must be inverse of queue lookup in efx_hard_start_xmit() */
365 netdev_get_tx_queue(efx
->net_dev
,
366 tx_queue
->queue
/ EFX_TXQ_TYPES
+
367 ((tx_queue
->queue
& EFX_TXQ_TYPE_HIGHPRI
) ?
368 efx
->n_tx_channels
: 0));
371 int efx_setup_tc(struct net_device
*net_dev
, u8 num_tc
)
373 struct efx_nic
*efx
= netdev_priv(net_dev
);
374 struct efx_channel
*channel
;
375 struct efx_tx_queue
*tx_queue
;
379 if (efx_nic_rev(efx
) < EFX_REV_FALCON_B0
|| num_tc
> EFX_MAX_TX_TC
)
382 if (num_tc
== net_dev
->num_tc
)
385 for (tc
= 0; tc
< num_tc
; tc
++) {
386 net_dev
->tc_to_txq
[tc
].offset
= tc
* efx
->n_tx_channels
;
387 net_dev
->tc_to_txq
[tc
].count
= efx
->n_tx_channels
;
390 if (num_tc
> net_dev
->num_tc
) {
391 /* Initialise high-priority queues as necessary */
392 efx_for_each_channel(channel
, efx
) {
393 efx_for_each_possible_channel_tx_queue(tx_queue
,
395 if (!(tx_queue
->queue
& EFX_TXQ_TYPE_HIGHPRI
))
397 if (!tx_queue
->buffer
) {
398 rc
= efx_probe_tx_queue(tx_queue
);
402 if (!tx_queue
->initialised
)
403 efx_init_tx_queue(tx_queue
);
404 efx_init_tx_queue_core_txq(tx_queue
);
408 /* Reduce number of classes before number of queues */
409 net_dev
->num_tc
= num_tc
;
412 rc
= netif_set_real_num_tx_queues(net_dev
,
413 max_t(int, num_tc
, 1) *
418 /* Do not destroy high-priority queues when they become
419 * unused. We would have to flush them first, and it is
420 * fairly difficult to flush a subset of TX queues. Leave
421 * it to efx_fini_channels().
424 net_dev
->num_tc
= num_tc
;
428 void efx_xmit_done(struct efx_tx_queue
*tx_queue
, unsigned int index
)
431 struct efx_nic
*efx
= tx_queue
->efx
;
432 struct efx_tx_queue
*txq2
;
433 unsigned int pkts_compl
= 0, bytes_compl
= 0;
435 EFX_BUG_ON_PARANOID(index
> tx_queue
->ptr_mask
);
437 efx_dequeue_buffers(tx_queue
, index
, &pkts_compl
, &bytes_compl
);
438 netdev_tx_completed_queue(tx_queue
->core_txq
, pkts_compl
, bytes_compl
);
441 ++tx_queue
->merge_events
;
443 /* See if we need to restart the netif queue. This memory
444 * barrier ensures that we write read_count (inside
445 * efx_dequeue_buffers()) before reading the queue status.
448 if (unlikely(netif_tx_queue_stopped(tx_queue
->core_txq
)) &&
449 likely(efx
->port_enabled
) &&
450 likely(netif_device_present(efx
->net_dev
))) {
451 txq2
= efx_tx_queue_partner(tx_queue
);
452 fill_level
= max(tx_queue
->insert_count
- tx_queue
->read_count
,
453 txq2
->insert_count
- txq2
->read_count
);
454 if (fill_level
<= efx
->txq_wake_thresh
)
455 netif_tx_wake_queue(tx_queue
->core_txq
);
458 /* Check whether the hardware queue is now empty */
459 if ((int)(tx_queue
->read_count
- tx_queue
->old_write_count
) >= 0) {
460 tx_queue
->old_write_count
= ACCESS_ONCE(tx_queue
->write_count
);
461 if (tx_queue
->read_count
== tx_queue
->old_write_count
) {
463 tx_queue
->empty_read_count
=
464 tx_queue
->read_count
| EFX_EMPTY_COUNT_VALID
;
469 /* Size of page-based TSO header buffers. Larger blocks must be
470 * allocated from the heap.
472 #define TSOH_STD_SIZE 128
473 #define TSOH_PER_PAGE (PAGE_SIZE / TSOH_STD_SIZE)
475 /* At most half the descriptors in the queue at any time will refer to
476 * a TSO header buffer, since they must always be followed by a
477 * payload descriptor referring to an skb.
479 static unsigned int efx_tsoh_page_count(struct efx_tx_queue
*tx_queue
)
481 return DIV_ROUND_UP(tx_queue
->ptr_mask
+ 1, 2 * TSOH_PER_PAGE
);
484 int efx_probe_tx_queue(struct efx_tx_queue
*tx_queue
)
486 struct efx_nic
*efx
= tx_queue
->efx
;
487 unsigned int entries
;
490 /* Create the smallest power-of-two aligned ring */
491 entries
= max(roundup_pow_of_two(efx
->txq_entries
), EFX_MIN_DMAQ_SIZE
);
492 EFX_BUG_ON_PARANOID(entries
> EFX_MAX_DMAQ_SIZE
);
493 tx_queue
->ptr_mask
= entries
- 1;
495 netif_dbg(efx
, probe
, efx
->net_dev
,
496 "creating TX queue %d size %#x mask %#x\n",
497 tx_queue
->queue
, efx
->txq_entries
, tx_queue
->ptr_mask
);
499 /* Allocate software ring */
500 tx_queue
->buffer
= kcalloc(entries
, sizeof(*tx_queue
->buffer
),
502 if (!tx_queue
->buffer
)
505 if (tx_queue
->queue
& EFX_TXQ_TYPE_OFFLOAD
) {
506 tx_queue
->tsoh_page
=
507 kcalloc(efx_tsoh_page_count(tx_queue
),
508 sizeof(tx_queue
->tsoh_page
[0]), GFP_KERNEL
);
509 if (!tx_queue
->tsoh_page
) {
515 /* Allocate hardware ring */
516 rc
= efx_nic_probe_tx(tx_queue
);
523 kfree(tx_queue
->tsoh_page
);
524 tx_queue
->tsoh_page
= NULL
;
526 kfree(tx_queue
->buffer
);
527 tx_queue
->buffer
= NULL
;
531 void efx_init_tx_queue(struct efx_tx_queue
*tx_queue
)
533 netif_dbg(tx_queue
->efx
, drv
, tx_queue
->efx
->net_dev
,
534 "initialising TX queue %d\n", tx_queue
->queue
);
536 tx_queue
->insert_count
= 0;
537 tx_queue
->write_count
= 0;
538 tx_queue
->old_write_count
= 0;
539 tx_queue
->read_count
= 0;
540 tx_queue
->old_read_count
= 0;
541 tx_queue
->empty_read_count
= 0 | EFX_EMPTY_COUNT_VALID
;
543 /* Set up TX descriptor ring */
544 efx_nic_init_tx(tx_queue
);
546 tx_queue
->initialised
= true;
549 void efx_fini_tx_queue(struct efx_tx_queue
*tx_queue
)
551 struct efx_tx_buffer
*buffer
;
553 netif_dbg(tx_queue
->efx
, drv
, tx_queue
->efx
->net_dev
,
554 "shutting down TX queue %d\n", tx_queue
->queue
);
556 if (!tx_queue
->buffer
)
559 /* Free any buffers left in the ring */
560 while (tx_queue
->read_count
!= tx_queue
->write_count
) {
561 unsigned int pkts_compl
= 0, bytes_compl
= 0;
562 buffer
= &tx_queue
->buffer
[tx_queue
->read_count
& tx_queue
->ptr_mask
];
563 efx_dequeue_buffer(tx_queue
, buffer
, &pkts_compl
, &bytes_compl
);
565 ++tx_queue
->read_count
;
567 netdev_tx_reset_queue(tx_queue
->core_txq
);
570 void efx_remove_tx_queue(struct efx_tx_queue
*tx_queue
)
574 if (!tx_queue
->buffer
)
577 netif_dbg(tx_queue
->efx
, drv
, tx_queue
->efx
->net_dev
,
578 "destroying TX queue %d\n", tx_queue
->queue
);
579 efx_nic_remove_tx(tx_queue
);
581 if (tx_queue
->tsoh_page
) {
582 for (i
= 0; i
< efx_tsoh_page_count(tx_queue
); i
++)
583 efx_nic_free_buffer(tx_queue
->efx
,
584 &tx_queue
->tsoh_page
[i
]);
585 kfree(tx_queue
->tsoh_page
);
586 tx_queue
->tsoh_page
= NULL
;
589 kfree(tx_queue
->buffer
);
590 tx_queue
->buffer
= NULL
;
594 /* Efx TCP segmentation acceleration.
596 * Why? Because by doing it here in the driver we can go significantly
597 * faster than the GSO.
599 * Requires TX checksum offload support.
602 /* Number of bytes inserted at the start of a TSO header buffer,
603 * similar to NET_IP_ALIGN.
605 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
606 #define TSOH_OFFSET 0
608 #define TSOH_OFFSET NET_IP_ALIGN
611 #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
614 * struct tso_state - TSO state for an SKB
615 * @out_len: Remaining length in current segment
616 * @seqnum: Current sequence number
617 * @ipv4_id: Current IPv4 ID, host endian
618 * @packet_space: Remaining space in current packet
619 * @dma_addr: DMA address of current position
620 * @in_len: Remaining length in current SKB fragment
621 * @unmap_len: Length of SKB fragment
622 * @unmap_addr: DMA address of SKB fragment
623 * @dma_flags: TX buffer flags for DMA mapping - %EFX_TX_BUF_MAP_SINGLE or 0
624 * @protocol: Network protocol (after any VLAN header)
625 * @ip_off: Offset of IP header
626 * @tcp_off: Offset of TCP header
627 * @header_len: Number of bytes of header
628 * @ip_base_len: IPv4 tot_len or IPv6 payload_len, before TCP payload
630 * The state used during segmentation. It is put into this data structure
631 * just to make it easy to pass into inline functions.
634 /* Output position */
638 unsigned packet_space
;
644 dma_addr_t unmap_addr
;
645 unsigned short dma_flags
;
649 unsigned int tcp_off
;
651 unsigned int ip_base_len
;
656 * Verify that our various assumptions about sk_buffs and the conditions
657 * under which TSO will be attempted hold true. Return the protocol number.
659 static __be16
efx_tso_check_protocol(struct sk_buff
*skb
)
661 __be16 protocol
= skb
->protocol
;
663 EFX_BUG_ON_PARANOID(((struct ethhdr
*)skb
->data
)->h_proto
!=
665 if (protocol
== htons(ETH_P_8021Q
)) {
666 struct vlan_ethhdr
*veh
= (struct vlan_ethhdr
*)skb
->data
;
667 protocol
= veh
->h_vlan_encapsulated_proto
;
670 if (protocol
== htons(ETH_P_IP
)) {
671 EFX_BUG_ON_PARANOID(ip_hdr(skb
)->protocol
!= IPPROTO_TCP
);
673 EFX_BUG_ON_PARANOID(protocol
!= htons(ETH_P_IPV6
));
674 EFX_BUG_ON_PARANOID(ipv6_hdr(skb
)->nexthdr
!= NEXTHDR_TCP
);
676 EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb
), skb
->data
)
677 + (tcp_hdr(skb
)->doff
<< 2u)) >
683 static u8
*efx_tsoh_get_buffer(struct efx_tx_queue
*tx_queue
,
684 struct efx_tx_buffer
*buffer
, unsigned int len
)
688 EFX_BUG_ON_PARANOID(buffer
->len
);
689 EFX_BUG_ON_PARANOID(buffer
->flags
);
690 EFX_BUG_ON_PARANOID(buffer
->unmap_len
);
692 if (likely(len
<= TSOH_STD_SIZE
- TSOH_OFFSET
)) {
694 (tx_queue
->insert_count
& tx_queue
->ptr_mask
) / 2;
695 struct efx_buffer
*page_buf
=
696 &tx_queue
->tsoh_page
[index
/ TSOH_PER_PAGE
];
698 TSOH_STD_SIZE
* (index
% TSOH_PER_PAGE
) + TSOH_OFFSET
;
700 if (unlikely(!page_buf
->addr
) &&
701 efx_nic_alloc_buffer(tx_queue
->efx
, page_buf
, PAGE_SIZE
,
705 result
= (u8
*)page_buf
->addr
+ offset
;
706 buffer
->dma_addr
= page_buf
->dma_addr
+ offset
;
707 buffer
->flags
= EFX_TX_BUF_CONT
;
709 tx_queue
->tso_long_headers
++;
711 buffer
->heap_buf
= kmalloc(TSOH_OFFSET
+ len
, GFP_ATOMIC
);
712 if (unlikely(!buffer
->heap_buf
))
714 result
= (u8
*)buffer
->heap_buf
+ TSOH_OFFSET
;
715 buffer
->flags
= EFX_TX_BUF_CONT
| EFX_TX_BUF_HEAP
;
724 * efx_tx_queue_insert - push descriptors onto the TX queue
725 * @tx_queue: Efx TX queue
726 * @dma_addr: DMA address of fragment
727 * @len: Length of fragment
728 * @final_buffer: The final buffer inserted into the queue
730 * Push descriptors onto the TX queue.
732 static void efx_tx_queue_insert(struct efx_tx_queue
*tx_queue
,
733 dma_addr_t dma_addr
, unsigned len
,
734 struct efx_tx_buffer
**final_buffer
)
736 struct efx_tx_buffer
*buffer
;
737 struct efx_nic
*efx
= tx_queue
->efx
;
738 unsigned dma_len
, insert_ptr
;
740 EFX_BUG_ON_PARANOID(len
<= 0);
743 insert_ptr
= tx_queue
->insert_count
& tx_queue
->ptr_mask
;
744 buffer
= &tx_queue
->buffer
[insert_ptr
];
745 ++tx_queue
->insert_count
;
747 EFX_BUG_ON_PARANOID(tx_queue
->insert_count
-
748 tx_queue
->read_count
>=
751 EFX_BUG_ON_PARANOID(buffer
->len
);
752 EFX_BUG_ON_PARANOID(buffer
->unmap_len
);
753 EFX_BUG_ON_PARANOID(buffer
->flags
);
755 buffer
->dma_addr
= dma_addr
;
757 dma_len
= efx_max_tx_len(efx
, dma_addr
);
759 /* If there is enough space to send then do so */
763 buffer
->len
= dma_len
;
764 buffer
->flags
= EFX_TX_BUF_CONT
;
769 EFX_BUG_ON_PARANOID(!len
);
771 *final_buffer
= buffer
;
776 * Put a TSO header into the TX queue.
778 * This is special-cased because we know that it is small enough to fit in
779 * a single fragment, and we know it doesn't cross a page boundary. It
780 * also allows us to not worry about end-of-packet etc.
782 static int efx_tso_put_header(struct efx_tx_queue
*tx_queue
,
783 struct efx_tx_buffer
*buffer
, u8
*header
)
785 if (unlikely(buffer
->flags
& EFX_TX_BUF_HEAP
)) {
786 buffer
->dma_addr
= dma_map_single(&tx_queue
->efx
->pci_dev
->dev
,
789 if (unlikely(dma_mapping_error(&tx_queue
->efx
->pci_dev
->dev
,
790 buffer
->dma_addr
))) {
791 kfree(buffer
->heap_buf
);
796 buffer
->unmap_len
= buffer
->len
;
797 buffer
->flags
|= EFX_TX_BUF_MAP_SINGLE
;
800 ++tx_queue
->insert_count
;
805 /* Remove buffers put into a tx_queue. None of the buffers must have
808 static void efx_enqueue_unwind(struct efx_tx_queue
*tx_queue
)
810 struct efx_tx_buffer
*buffer
;
812 /* Work backwards until we hit the original insert pointer value */
813 while (tx_queue
->insert_count
!= tx_queue
->write_count
) {
814 --tx_queue
->insert_count
;
815 buffer
= &tx_queue
->buffer
[tx_queue
->insert_count
&
817 efx_dequeue_buffer(tx_queue
, buffer
, NULL
, NULL
);
822 /* Parse the SKB header and initialise state. */
823 static void tso_start(struct tso_state
*st
, const struct sk_buff
*skb
)
825 st
->ip_off
= skb_network_header(skb
) - skb
->data
;
826 st
->tcp_off
= skb_transport_header(skb
) - skb
->data
;
827 st
->header_len
= st
->tcp_off
+ (tcp_hdr(skb
)->doff
<< 2u);
828 if (st
->protocol
== htons(ETH_P_IP
)) {
829 st
->ip_base_len
= st
->header_len
- st
->ip_off
;
830 st
->ipv4_id
= ntohs(ip_hdr(skb
)->id
);
832 st
->ip_base_len
= st
->header_len
- st
->tcp_off
;
835 st
->seqnum
= ntohl(tcp_hdr(skb
)->seq
);
837 EFX_BUG_ON_PARANOID(tcp_hdr(skb
)->urg
);
838 EFX_BUG_ON_PARANOID(tcp_hdr(skb
)->syn
);
839 EFX_BUG_ON_PARANOID(tcp_hdr(skb
)->rst
);
841 st
->out_len
= skb
->len
- st
->header_len
;
846 static int tso_get_fragment(struct tso_state
*st
, struct efx_nic
*efx
,
849 st
->unmap_addr
= skb_frag_dma_map(&efx
->pci_dev
->dev
, frag
, 0,
850 skb_frag_size(frag
), DMA_TO_DEVICE
);
851 if (likely(!dma_mapping_error(&efx
->pci_dev
->dev
, st
->unmap_addr
))) {
853 st
->unmap_len
= skb_frag_size(frag
);
854 st
->in_len
= skb_frag_size(frag
);
855 st
->dma_addr
= st
->unmap_addr
;
861 static int tso_get_head_fragment(struct tso_state
*st
, struct efx_nic
*efx
,
862 const struct sk_buff
*skb
)
864 int hl
= st
->header_len
;
865 int len
= skb_headlen(skb
) - hl
;
867 st
->unmap_addr
= dma_map_single(&efx
->pci_dev
->dev
, skb
->data
+ hl
,
869 if (likely(!dma_mapping_error(&efx
->pci_dev
->dev
, st
->unmap_addr
))) {
870 st
->dma_flags
= EFX_TX_BUF_MAP_SINGLE
;
873 st
->dma_addr
= st
->unmap_addr
;
881 * tso_fill_packet_with_fragment - form descriptors for the current fragment
882 * @tx_queue: Efx TX queue
883 * @skb: Socket buffer
886 * Form descriptors for the current fragment, until we reach the end
887 * of fragment or end-of-packet.
889 static void tso_fill_packet_with_fragment(struct efx_tx_queue
*tx_queue
,
890 const struct sk_buff
*skb
,
891 struct tso_state
*st
)
893 struct efx_tx_buffer
*buffer
;
898 if (st
->packet_space
== 0)
901 EFX_BUG_ON_PARANOID(st
->in_len
<= 0);
902 EFX_BUG_ON_PARANOID(st
->packet_space
<= 0);
904 n
= min(st
->in_len
, st
->packet_space
);
906 st
->packet_space
-= n
;
910 efx_tx_queue_insert(tx_queue
, st
->dma_addr
, n
, &buffer
);
912 if (st
->out_len
== 0) {
913 /* Transfer ownership of the skb */
915 buffer
->flags
= EFX_TX_BUF_SKB
;
916 } else if (st
->packet_space
!= 0) {
917 buffer
->flags
= EFX_TX_BUF_CONT
;
920 if (st
->in_len
== 0) {
921 /* Transfer ownership of the DMA mapping */
922 buffer
->unmap_len
= st
->unmap_len
;
923 buffer
->flags
|= st
->dma_flags
;
932 * tso_start_new_packet - generate a new header and prepare for the new packet
933 * @tx_queue: Efx TX queue
934 * @skb: Socket buffer
937 * Generate a new header and prepare for the new packet. Return 0 on
938 * success, or -%ENOMEM if failed to alloc header.
940 static int tso_start_new_packet(struct efx_tx_queue
*tx_queue
,
941 const struct sk_buff
*skb
,
942 struct tso_state
*st
)
944 struct efx_tx_buffer
*buffer
=
945 &tx_queue
->buffer
[tx_queue
->insert_count
& tx_queue
->ptr_mask
];
946 struct tcphdr
*tsoh_th
;
951 /* Allocate and insert a DMA-mapped header buffer. */
952 header
= efx_tsoh_get_buffer(tx_queue
, buffer
, st
->header_len
);
956 tsoh_th
= (struct tcphdr
*)(header
+ st
->tcp_off
);
958 /* Copy and update the headers. */
959 memcpy(header
, skb
->data
, st
->header_len
);
961 tsoh_th
->seq
= htonl(st
->seqnum
);
962 st
->seqnum
+= skb_shinfo(skb
)->gso_size
;
963 if (st
->out_len
> skb_shinfo(skb
)->gso_size
) {
964 /* This packet will not finish the TSO burst. */
965 st
->packet_space
= skb_shinfo(skb
)->gso_size
;
969 /* This packet will be the last in the TSO burst. */
970 st
->packet_space
= st
->out_len
;
971 tsoh_th
->fin
= tcp_hdr(skb
)->fin
;
972 tsoh_th
->psh
= tcp_hdr(skb
)->psh
;
974 ip_length
= st
->ip_base_len
+ st
->packet_space
;
976 if (st
->protocol
== htons(ETH_P_IP
)) {
977 struct iphdr
*tsoh_iph
= (struct iphdr
*)(header
+ st
->ip_off
);
979 tsoh_iph
->tot_len
= htons(ip_length
);
981 /* Linux leaves suitable gaps in the IP ID space for us to fill. */
982 tsoh_iph
->id
= htons(st
->ipv4_id
);
985 struct ipv6hdr
*tsoh_iph
=
986 (struct ipv6hdr
*)(header
+ st
->ip_off
);
988 tsoh_iph
->payload_len
= htons(ip_length
);
991 rc
= efx_tso_put_header(tx_queue
, buffer
, header
);
995 ++tx_queue
->tso_packets
;
1002 * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
1003 * @tx_queue: Efx TX queue
1004 * @skb: Socket buffer
1006 * Context: You must hold netif_tx_lock() to call this function.
1008 * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
1009 * @skb was not enqueued. In all cases @skb is consumed. Return
1012 static int efx_enqueue_skb_tso(struct efx_tx_queue
*tx_queue
,
1013 struct sk_buff
*skb
)
1015 struct efx_nic
*efx
= tx_queue
->efx
;
1017 struct tso_state state
;
1019 /* Find the packet protocol and sanity-check it */
1020 state
.protocol
= efx_tso_check_protocol(skb
);
1022 EFX_BUG_ON_PARANOID(tx_queue
->write_count
!= tx_queue
->insert_count
);
1024 tso_start(&state
, skb
);
1026 /* Assume that skb header area contains exactly the headers, and
1027 * all payload is in the frag list.
1029 if (skb_headlen(skb
) == state
.header_len
) {
1030 /* Grab the first payload fragment. */
1031 EFX_BUG_ON_PARANOID(skb_shinfo(skb
)->nr_frags
< 1);
1033 rc
= tso_get_fragment(&state
, efx
,
1034 skb_shinfo(skb
)->frags
+ frag_i
);
1038 rc
= tso_get_head_fragment(&state
, efx
, skb
);
1044 if (tso_start_new_packet(tx_queue
, skb
, &state
) < 0)
1048 tso_fill_packet_with_fragment(tx_queue
, skb
, &state
);
1050 /* Move onto the next fragment? */
1051 if (state
.in_len
== 0) {
1052 if (++frag_i
>= skb_shinfo(skb
)->nr_frags
)
1053 /* End of payload reached. */
1055 rc
= tso_get_fragment(&state
, efx
,
1056 skb_shinfo(skb
)->frags
+ frag_i
);
1061 /* Start at new packet? */
1062 if (state
.packet_space
== 0 &&
1063 tso_start_new_packet(tx_queue
, skb
, &state
) < 0)
1067 netdev_tx_sent_queue(tx_queue
->core_txq
, skb
->len
);
1069 /* Pass off to hardware */
1070 efx_nic_push_buffers(tx_queue
);
1072 efx_tx_maybe_stop_queue(tx_queue
);
1074 tx_queue
->tso_bursts
++;
1075 return NETDEV_TX_OK
;
1078 netif_err(efx
, tx_err
, efx
->net_dev
,
1079 "Out of memory for TSO headers, or DMA mapping error\n");
1080 dev_kfree_skb_any(skb
);
1082 /* Free the DMA mapping we were in the process of writing out */
1083 if (state
.unmap_len
) {
1084 if (state
.dma_flags
& EFX_TX_BUF_MAP_SINGLE
)
1085 dma_unmap_single(&efx
->pci_dev
->dev
, state
.unmap_addr
,
1086 state
.unmap_len
, DMA_TO_DEVICE
);
1088 dma_unmap_page(&efx
->pci_dev
->dev
, state
.unmap_addr
,
1089 state
.unmap_len
, DMA_TO_DEVICE
);
1092 efx_enqueue_unwind(tx_queue
);
1093 return NETDEV_TX_OK
;