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9f5f35e041ac599681576aa06b9ee24033cfbd12
[deliverable/linux.git] / drivers / net / ethernet / sgi / meth.c
1 /*
2 * meth.c -- O2 Builtin 10/100 Ethernet driver
3 *
4 * Copyright (C) 2001-2003 Ilya Volynets
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 #include <linux/errno.h>
19 #include <linux/types.h>
20 #include <linux/interrupt.h>
21
22 #include <linux/in.h>
23 #include <linux/in6.h>
24 #include <linux/device.h> /* struct device, et al */
25 #include <linux/netdevice.h> /* struct device, and other headers */
26 #include <linux/etherdevice.h> /* eth_type_trans */
27 #include <linux/ip.h> /* struct iphdr */
28 #include <linux/tcp.h> /* struct tcphdr */
29 #include <linux/skbuff.h>
30 #include <linux/mii.h> /* MII definitions */
31 #include <linux/crc32.h>
32
33 #include <asm/ip32/mace.h>
34 #include <asm/ip32/ip32_ints.h>
35
36 #include <asm/io.h>
37
38 #include "meth.h"
39
40 #ifndef MFE_DEBUG
41 #define MFE_DEBUG 0
42 #endif
43
44 #if MFE_DEBUG>=1
45 #define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __func__ , ## args)
46 #define MFE_RX_DEBUG 2
47 #else
48 #define DPRINTK(str,args...)
49 #define MFE_RX_DEBUG 0
50 #endif
51
52
53 static const char *meth_str="SGI O2 Fast Ethernet";
54
55 /* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
56 #define TX_TIMEOUT (400*HZ/1000)
57
58 static int timeout = TX_TIMEOUT;
59 module_param(timeout, int, 0);
60
61 /*
62 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
63 * MACE Ethernet uses a 64 element hash table based on the Ethernet CRC.
64 */
65 #define METH_MCF_LIMIT 32
66
67 /*
68 * This structure is private to each device. It is used to pass
69 * packets in and out, so there is place for a packet
70 */
71 struct meth_private {
72 /* in-memory copy of MAC Control register */
73 u64 mac_ctrl;
74
75 /* in-memory copy of DMA Control register */
76 unsigned long dma_ctrl;
77 /* address of PHY, used by mdio_* functions, initialized in mdio_probe */
78 unsigned long phy_addr;
79 tx_packet *tx_ring;
80 dma_addr_t tx_ring_dma;
81 struct sk_buff *tx_skbs[TX_RING_ENTRIES];
82 dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
83 unsigned long tx_read, tx_write, tx_count;
84
85 rx_packet *rx_ring[RX_RING_ENTRIES];
86 dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
87 struct sk_buff *rx_skbs[RX_RING_ENTRIES];
88 unsigned long rx_write;
89
90 /* Multicast filter. */
91 u64 mcast_filter;
92
93 spinlock_t meth_lock;
94 };
95
96 static void meth_tx_timeout(struct net_device *dev);
97 static irqreturn_t meth_interrupt(int irq, void *dev_id);
98
99 /* global, initialized in ip32-setup.c */
100 char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
101
102 static inline void load_eaddr(struct net_device *dev)
103 {
104 int i;
105 u64 macaddr;
106
107 DPRINTK("Loading MAC Address: %pM\n", dev->dev_addr);
108 macaddr = 0;
109 for (i = 0; i < 6; i++)
110 macaddr |= (u64)dev->dev_addr[i] << ((5 - i) * 8);
111
112 mace->eth.mac_addr = macaddr;
113 }
114
115 /*
116 * Waits for BUSY status of mdio bus to clear
117 */
118 #define WAIT_FOR_PHY(___rval) \
119 while ((___rval = mace->eth.phy_data) & MDIO_BUSY) { \
120 udelay(25); \
121 }
122 /*read phy register, return value read */
123 static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
124 {
125 unsigned long rval;
126 WAIT_FOR_PHY(rval);
127 mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
128 udelay(25);
129 mace->eth.phy_trans_go = 1;
130 udelay(25);
131 WAIT_FOR_PHY(rval);
132 return rval & MDIO_DATA_MASK;
133 }
134
135 static int mdio_probe(struct meth_private *priv)
136 {
137 int i;
138 unsigned long p2, p3, flags;
139 /* check if phy is detected already */
140 if(priv->phy_addr>=0&&priv->phy_addr<32)
141 return 0;
142 spin_lock_irqsave(&priv->meth_lock, flags);
143 for (i=0;i<32;++i){
144 priv->phy_addr=i;
145 p2=mdio_read(priv,2);
146 p3=mdio_read(priv,3);
147 #if MFE_DEBUG>=2
148 switch ((p2<<12)|(p3>>4)){
149 case PHY_QS6612X:
150 DPRINTK("PHY is QS6612X\n");
151 break;
152 case PHY_ICS1889:
153 DPRINTK("PHY is ICS1889\n");
154 break;
155 case PHY_ICS1890:
156 DPRINTK("PHY is ICS1890\n");
157 break;
158 case PHY_DP83840:
159 DPRINTK("PHY is DP83840\n");
160 break;
161 }
162 #endif
163 if(p2!=0xffff&&p2!=0x0000){
164 DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
165 break;
166 }
167 }
168 spin_unlock_irqrestore(&priv->meth_lock, flags);
169 if(priv->phy_addr<32) {
170 return 0;
171 }
172 DPRINTK("Oopsie! PHY is not known!\n");
173 priv->phy_addr=-1;
174 return -ENODEV;
175 }
176
177 static void meth_check_link(struct net_device *dev)
178 {
179 struct meth_private *priv = netdev_priv(dev);
180 unsigned long mii_advertising = mdio_read(priv, 4);
181 unsigned long mii_partner = mdio_read(priv, 5);
182 unsigned long negotiated = mii_advertising & mii_partner;
183 unsigned long duplex, speed;
184
185 if (mii_partner == 0xffff)
186 return;
187
188 speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
189 duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
190 METH_PHY_FDX : 0;
191
192 if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
193 DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
194 if (duplex)
195 priv->mac_ctrl |= METH_PHY_FDX;
196 else
197 priv->mac_ctrl &= ~METH_PHY_FDX;
198 mace->eth.mac_ctrl = priv->mac_ctrl;
199 }
200
201 if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
202 DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
203 if (duplex)
204 priv->mac_ctrl |= METH_100MBIT;
205 else
206 priv->mac_ctrl &= ~METH_100MBIT;
207 mace->eth.mac_ctrl = priv->mac_ctrl;
208 }
209 }
210
211
212 static int meth_init_tx_ring(struct meth_private *priv)
213 {
214 /* Init TX ring */
215 priv->tx_ring = dma_alloc_coherent(NULL, TX_RING_BUFFER_SIZE,
216 &priv->tx_ring_dma,
217 GFP_ATOMIC | __GFP_ZERO);
218 if (!priv->tx_ring)
219 return -ENOMEM;
220
221 priv->tx_count = priv->tx_read = priv->tx_write = 0;
222 mace->eth.tx_ring_base = priv->tx_ring_dma;
223 /* Now init skb save area */
224 memset(priv->tx_skbs, 0, sizeof(priv->tx_skbs));
225 memset(priv->tx_skb_dmas, 0, sizeof(priv->tx_skb_dmas));
226 return 0;
227 }
228
229 static int meth_init_rx_ring(struct meth_private *priv)
230 {
231 int i;
232
233 for (i = 0; i < RX_RING_ENTRIES; i++) {
234 priv->rx_skbs[i] = alloc_skb(METH_RX_BUFF_SIZE, 0);
235 /* 8byte status vector + 3quad padding + 2byte padding,
236 * to put data on 64bit aligned boundary */
237 skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
238 priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
239 /* I'll need to re-sync it after each RX */
240 priv->rx_ring_dmas[i] =
241 dma_map_single(NULL, priv->rx_ring[i],
242 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
243 mace->eth.rx_fifo = priv->rx_ring_dmas[i];
244 }
245 priv->rx_write = 0;
246 return 0;
247 }
248 static void meth_free_tx_ring(struct meth_private *priv)
249 {
250 int i;
251
252 /* Remove any pending skb */
253 for (i = 0; i < TX_RING_ENTRIES; i++) {
254 if (priv->tx_skbs[i])
255 dev_kfree_skb(priv->tx_skbs[i]);
256 priv->tx_skbs[i] = NULL;
257 }
258 dma_free_coherent(NULL, TX_RING_BUFFER_SIZE, priv->tx_ring,
259 priv->tx_ring_dma);
260 }
261
262 /* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
263 static void meth_free_rx_ring(struct meth_private *priv)
264 {
265 int i;
266
267 for (i = 0; i < RX_RING_ENTRIES; i++) {
268 dma_unmap_single(NULL, priv->rx_ring_dmas[i],
269 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
270 priv->rx_ring[i] = 0;
271 priv->rx_ring_dmas[i] = 0;
272 kfree_skb(priv->rx_skbs[i]);
273 }
274 }
275
276 int meth_reset(struct net_device *dev)
277 {
278 struct meth_private *priv = netdev_priv(dev);
279
280 /* Reset card */
281 mace->eth.mac_ctrl = SGI_MAC_RESET;
282 udelay(1);
283 mace->eth.mac_ctrl = 0;
284 udelay(25);
285
286 /* Load ethernet address */
287 load_eaddr(dev);
288 /* Should load some "errata", but later */
289
290 /* Check for device */
291 if (mdio_probe(priv) < 0) {
292 DPRINTK("Unable to find PHY\n");
293 return -ENODEV;
294 }
295
296 /* Initial mode: 10 | Half-duplex | Accept normal packets */
297 priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
298 if (dev->flags & IFF_PROMISC)
299 priv->mac_ctrl |= METH_PROMISC;
300 mace->eth.mac_ctrl = priv->mac_ctrl;
301
302 /* Autonegotiate speed and duplex mode */
303 meth_check_link(dev);
304
305 /* Now set dma control, but don't enable DMA, yet */
306 priv->dma_ctrl = (4 << METH_RX_OFFSET_SHIFT) |
307 (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
308 mace->eth.dma_ctrl = priv->dma_ctrl;
309
310 return 0;
311 }
312
313 /*============End Helper Routines=====================*/
314
315 /*
316 * Open and close
317 */
318 static int meth_open(struct net_device *dev)
319 {
320 struct meth_private *priv = netdev_priv(dev);
321 int ret;
322
323 priv->phy_addr = -1; /* No PHY is known yet... */
324
325 /* Initialize the hardware */
326 ret = meth_reset(dev);
327 if (ret < 0)
328 return ret;
329
330 /* Allocate the ring buffers */
331 ret = meth_init_tx_ring(priv);
332 if (ret < 0)
333 return ret;
334 ret = meth_init_rx_ring(priv);
335 if (ret < 0)
336 goto out_free_tx_ring;
337
338 ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
339 if (ret) {
340 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
341 goto out_free_rx_ring;
342 }
343
344 /* Start DMA */
345 priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
346 METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
347 mace->eth.dma_ctrl = priv->dma_ctrl;
348
349 DPRINTK("About to start queue\n");
350 netif_start_queue(dev);
351
352 return 0;
353
354 out_free_rx_ring:
355 meth_free_rx_ring(priv);
356 out_free_tx_ring:
357 meth_free_tx_ring(priv);
358
359 return ret;
360 }
361
362 static int meth_release(struct net_device *dev)
363 {
364 struct meth_private *priv = netdev_priv(dev);
365
366 DPRINTK("Stopping queue\n");
367 netif_stop_queue(dev); /* can't transmit any more */
368 /* shut down DMA */
369 priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
370 METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
371 mace->eth.dma_ctrl = priv->dma_ctrl;
372 free_irq(dev->irq, dev);
373 meth_free_tx_ring(priv);
374 meth_free_rx_ring(priv);
375
376 return 0;
377 }
378
379 /*
380 * Receive a packet: retrieve, encapsulate and pass over to upper levels
381 */
382 static void meth_rx(struct net_device* dev, unsigned long int_status)
383 {
384 struct sk_buff *skb;
385 unsigned long status, flags;
386 struct meth_private *priv = netdev_priv(dev);
387 unsigned long fifo_rptr = (int_status & METH_INT_RX_RPTR_MASK) >> 8;
388
389 spin_lock_irqsave(&priv->meth_lock, flags);
390 priv->dma_ctrl &= ~METH_DMA_RX_INT_EN;
391 mace->eth.dma_ctrl = priv->dma_ctrl;
392 spin_unlock_irqrestore(&priv->meth_lock, flags);
393
394 if (int_status & METH_INT_RX_UNDERFLOW) {
395 fifo_rptr = (fifo_rptr - 1) & 0x0f;
396 }
397 while (priv->rx_write != fifo_rptr) {
398 dma_unmap_single(NULL, priv->rx_ring_dmas[priv->rx_write],
399 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
400 status = priv->rx_ring[priv->rx_write]->status.raw;
401 #if MFE_DEBUG
402 if (!(status & METH_RX_ST_VALID)) {
403 DPRINTK("Not received? status=%016lx\n",status);
404 }
405 #endif
406 if ((!(status & METH_RX_STATUS_ERRORS)) && (status & METH_RX_ST_VALID)) {
407 int len = (status & 0xffff) - 4; /* omit CRC */
408 /* length sanity check */
409 if (len < 60 || len > 1518) {
410 printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2Lx.\n",
411 dev->name, priv->rx_write,
412 priv->rx_ring[priv->rx_write]->status.raw);
413 dev->stats.rx_errors++;
414 dev->stats.rx_length_errors++;
415 skb = priv->rx_skbs[priv->rx_write];
416 } else {
417 skb = alloc_skb(METH_RX_BUFF_SIZE, GFP_ATOMIC);
418 if (!skb) {
419 /* Ouch! No memory! Drop packet on the floor */
420 DPRINTK("No mem: dropping packet\n");
421 dev->stats.rx_dropped++;
422 skb = priv->rx_skbs[priv->rx_write];
423 } else {
424 struct sk_buff *skb_c = priv->rx_skbs[priv->rx_write];
425 /* 8byte status vector + 3quad padding + 2byte padding,
426 * to put data on 64bit aligned boundary */
427 skb_reserve(skb, METH_RX_HEAD);
428 /* Write metadata, and then pass to the receive level */
429 skb_put(skb_c, len);
430 priv->rx_skbs[priv->rx_write] = skb;
431 skb_c->protocol = eth_type_trans(skb_c, dev);
432 dev->stats.rx_packets++;
433 dev->stats.rx_bytes += len;
434 netif_rx(skb_c);
435 }
436 }
437 } else {
438 dev->stats.rx_errors++;
439 skb=priv->rx_skbs[priv->rx_write];
440 #if MFE_DEBUG>0
441 printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
442 if(status&METH_RX_ST_RCV_CODE_VIOLATION)
443 printk(KERN_WARNING "Receive Code Violation\n");
444 if(status&METH_RX_ST_CRC_ERR)
445 printk(KERN_WARNING "CRC error\n");
446 if(status&METH_RX_ST_INV_PREAMBLE_CTX)
447 printk(KERN_WARNING "Invalid Preamble Context\n");
448 if(status&METH_RX_ST_LONG_EVT_SEEN)
449 printk(KERN_WARNING "Long Event Seen...\n");
450 if(status&METH_RX_ST_BAD_PACKET)
451 printk(KERN_WARNING "Bad Packet\n");
452 if(status&METH_RX_ST_CARRIER_EVT_SEEN)
453 printk(KERN_WARNING "Carrier Event Seen\n");
454 #endif
455 }
456 priv->rx_ring[priv->rx_write] = (rx_packet*)skb->head;
457 priv->rx_ring[priv->rx_write]->status.raw = 0;
458 priv->rx_ring_dmas[priv->rx_write] =
459 dma_map_single(NULL, priv->rx_ring[priv->rx_write],
460 METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
461 mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
462 ADVANCE_RX_PTR(priv->rx_write);
463 }
464 spin_lock_irqsave(&priv->meth_lock, flags);
465 /* In case there was underflow, and Rx DMA was disabled */
466 priv->dma_ctrl |= METH_DMA_RX_INT_EN | METH_DMA_RX_EN;
467 mace->eth.dma_ctrl = priv->dma_ctrl;
468 mace->eth.int_stat = METH_INT_RX_THRESHOLD;
469 spin_unlock_irqrestore(&priv->meth_lock, flags);
470 }
471
472 static int meth_tx_full(struct net_device *dev)
473 {
474 struct meth_private *priv = netdev_priv(dev);
475
476 return priv->tx_count >= TX_RING_ENTRIES - 1;
477 }
478
479 static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
480 {
481 struct meth_private *priv = netdev_priv(dev);
482 unsigned long status, flags;
483 struct sk_buff *skb;
484 unsigned long rptr = (int_status&TX_INFO_RPTR) >> 16;
485
486 spin_lock_irqsave(&priv->meth_lock, flags);
487
488 /* Stop DMA notification */
489 priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
490 mace->eth.dma_ctrl = priv->dma_ctrl;
491
492 while (priv->tx_read != rptr) {
493 skb = priv->tx_skbs[priv->tx_read];
494 status = priv->tx_ring[priv->tx_read].header.raw;
495 #if MFE_DEBUG>=1
496 if (priv->tx_read == priv->tx_write)
497 DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n", priv->tx_read, priv->tx_write,rptr);
498 #endif
499 if (status & METH_TX_ST_DONE) {
500 if (status & METH_TX_ST_SUCCESS){
501 dev->stats.tx_packets++;
502 dev->stats.tx_bytes += skb->len;
503 } else {
504 dev->stats.tx_errors++;
505 #if MFE_DEBUG>=1
506 DPRINTK("TX error: status=%016lx <",status);
507 if(status & METH_TX_ST_SUCCESS)
508 printk(" SUCCESS");
509 if(status & METH_TX_ST_TOOLONG)
510 printk(" TOOLONG");
511 if(status & METH_TX_ST_UNDERRUN)
512 printk(" UNDERRUN");
513 if(status & METH_TX_ST_EXCCOLL)
514 printk(" EXCCOLL");
515 if(status & METH_TX_ST_DEFER)
516 printk(" DEFER");
517 if(status & METH_TX_ST_LATECOLL)
518 printk(" LATECOLL");
519 printk(" >\n");
520 #endif
521 }
522 } else {
523 DPRINTK("RPTR points us here, but packet not done?\n");
524 break;
525 }
526 dev_kfree_skb_irq(skb);
527 priv->tx_skbs[priv->tx_read] = NULL;
528 priv->tx_ring[priv->tx_read].header.raw = 0;
529 priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
530 priv->tx_count--;
531 }
532
533 /* wake up queue if it was stopped */
534 if (netif_queue_stopped(dev) && !meth_tx_full(dev)) {
535 netif_wake_queue(dev);
536 }
537
538 mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
539 spin_unlock_irqrestore(&priv->meth_lock, flags);
540 }
541
542 static void meth_error(struct net_device* dev, unsigned status)
543 {
544 struct meth_private *priv = netdev_priv(dev);
545 unsigned long flags;
546
547 printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
548 /* check for errors too... */
549 if (status & (METH_INT_TX_LINK_FAIL))
550 printk(KERN_WARNING "meth: link failure\n");
551 /* Should I do full reset in this case? */
552 if (status & (METH_INT_MEM_ERROR))
553 printk(KERN_WARNING "meth: memory error\n");
554 if (status & (METH_INT_TX_ABORT))
555 printk(KERN_WARNING "meth: aborted\n");
556 if (status & (METH_INT_RX_OVERFLOW))
557 printk(KERN_WARNING "meth: Rx overflow\n");
558 if (status & (METH_INT_RX_UNDERFLOW)) {
559 printk(KERN_WARNING "meth: Rx underflow\n");
560 spin_lock_irqsave(&priv->meth_lock, flags);
561 mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
562 /* more underflow interrupts will be delivered,
563 * effectively throwing us into an infinite loop.
564 * Thus I stop processing Rx in this case. */
565 priv->dma_ctrl &= ~METH_DMA_RX_EN;
566 mace->eth.dma_ctrl = priv->dma_ctrl;
567 DPRINTK("Disabled meth Rx DMA temporarily\n");
568 spin_unlock_irqrestore(&priv->meth_lock, flags);
569 }
570 mace->eth.int_stat = METH_INT_ERROR;
571 }
572
573 /*
574 * The typical interrupt entry point
575 */
576 static irqreturn_t meth_interrupt(int irq, void *dev_id)
577 {
578 struct net_device *dev = (struct net_device *)dev_id;
579 struct meth_private *priv = netdev_priv(dev);
580 unsigned long status;
581
582 status = mace->eth.int_stat;
583 while (status & 0xff) {
584 /* First handle errors - if we get Rx underflow,
585 * Rx DMA will be disabled, and Rx handler will reenable
586 * it. I don't think it's possible to get Rx underflow,
587 * without getting Rx interrupt */
588 if (status & METH_INT_ERROR) {
589 meth_error(dev, status);
590 }
591 if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
592 /* a transmission is over: free the skb */
593 meth_tx_cleanup(dev, status);
594 }
595 if (status & METH_INT_RX_THRESHOLD) {
596 if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
597 break;
598 /* send it to meth_rx for handling */
599 meth_rx(dev, status);
600 }
601 status = mace->eth.int_stat;
602 }
603
604 return IRQ_HANDLED;
605 }
606
607 /*
608 * Transmits packets that fit into TX descriptor (are <=120B)
609 */
610 static void meth_tx_short_prepare(struct meth_private *priv,
611 struct sk_buff *skb)
612 {
613 tx_packet *desc = &priv->tx_ring[priv->tx_write];
614 int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
615
616 desc->header.raw = METH_TX_CMD_INT_EN | (len-1) | ((128-len) << 16);
617 /* maybe I should set whole thing to 0 first... */
618 skb_copy_from_linear_data(skb, desc->data.dt + (120 - len), skb->len);
619 if (skb->len < len)
620 memset(desc->data.dt + 120 - len + skb->len, 0, len-skb->len);
621 }
622 #define TX_CATBUF1 BIT(25)
623 static void meth_tx_1page_prepare(struct meth_private *priv,
624 struct sk_buff *skb)
625 {
626 tx_packet *desc = &priv->tx_ring[priv->tx_write];
627 void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
628 int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
629 int buffer_len = skb->len - unaligned_len;
630 dma_addr_t catbuf;
631
632 desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | (skb->len - 1);
633
634 /* unaligned part */
635 if (unaligned_len) {
636 skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
637 unaligned_len);
638 desc->header.raw |= (128 - unaligned_len) << 16;
639 }
640
641 /* first page */
642 catbuf = dma_map_single(NULL, buffer_data, buffer_len,
643 DMA_TO_DEVICE);
644 desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
645 desc->data.cat_buf[0].form.len = buffer_len - 1;
646 }
647 #define TX_CATBUF2 BIT(26)
648 static void meth_tx_2page_prepare(struct meth_private *priv,
649 struct sk_buff *skb)
650 {
651 tx_packet *desc = &priv->tx_ring[priv->tx_write];
652 void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
653 void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
654 int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
655 int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
656 int buffer2_len = skb->len - buffer1_len - unaligned_len;
657 dma_addr_t catbuf1, catbuf2;
658
659 desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | TX_CATBUF2| (skb->len - 1);
660 /* unaligned part */
661 if (unaligned_len){
662 skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
663 unaligned_len);
664 desc->header.raw |= (128 - unaligned_len) << 16;
665 }
666
667 /* first page */
668 catbuf1 = dma_map_single(NULL, buffer1_data, buffer1_len,
669 DMA_TO_DEVICE);
670 desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
671 desc->data.cat_buf[0].form.len = buffer1_len - 1;
672 /* second page */
673 catbuf2 = dma_map_single(NULL, buffer2_data, buffer2_len,
674 DMA_TO_DEVICE);
675 desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
676 desc->data.cat_buf[1].form.len = buffer2_len - 1;
677 }
678
679 static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
680 {
681 /* Remember the skb, so we can free it at interrupt time */
682 priv->tx_skbs[priv->tx_write] = skb;
683 if (skb->len <= 120) {
684 /* Whole packet fits into descriptor */
685 meth_tx_short_prepare(priv, skb);
686 } else if (PAGE_ALIGN((unsigned long)skb->data) !=
687 PAGE_ALIGN((unsigned long)skb->data + skb->len - 1)) {
688 /* Packet crosses page boundary */
689 meth_tx_2page_prepare(priv, skb);
690 } else {
691 /* Packet is in one page */
692 meth_tx_1page_prepare(priv, skb);
693 }
694 priv->tx_write = (priv->tx_write + 1) & (TX_RING_ENTRIES - 1);
695 mace->eth.tx_info = priv->tx_write;
696 priv->tx_count++;
697 }
698
699 /*
700 * Transmit a packet (called by the kernel)
701 */
702 static int meth_tx(struct sk_buff *skb, struct net_device *dev)
703 {
704 struct meth_private *priv = netdev_priv(dev);
705 unsigned long flags;
706
707 spin_lock_irqsave(&priv->meth_lock, flags);
708 /* Stop DMA notification */
709 priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
710 mace->eth.dma_ctrl = priv->dma_ctrl;
711
712 meth_add_to_tx_ring(priv, skb);
713 dev->trans_start = jiffies; /* save the timestamp */
714
715 /* If TX ring is full, tell the upper layer to stop sending packets */
716 if (meth_tx_full(dev)) {
717 printk(KERN_DEBUG "TX full: stopping\n");
718 netif_stop_queue(dev);
719 }
720
721 /* Restart DMA notification */
722 priv->dma_ctrl |= METH_DMA_TX_INT_EN;
723 mace->eth.dma_ctrl = priv->dma_ctrl;
724
725 spin_unlock_irqrestore(&priv->meth_lock, flags);
726
727 return NETDEV_TX_OK;
728 }
729
730 /*
731 * Deal with a transmit timeout.
732 */
733 static void meth_tx_timeout(struct net_device *dev)
734 {
735 struct meth_private *priv = netdev_priv(dev);
736 unsigned long flags;
737
738 printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
739
740 /* Protect against concurrent rx interrupts */
741 spin_lock_irqsave(&priv->meth_lock,flags);
742
743 /* Try to reset the interface. */
744 meth_reset(dev);
745
746 dev->stats.tx_errors++;
747
748 /* Clear all rings */
749 meth_free_tx_ring(priv);
750 meth_free_rx_ring(priv);
751 meth_init_tx_ring(priv);
752 meth_init_rx_ring(priv);
753
754 /* Restart dma */
755 priv->dma_ctrl |= METH_DMA_TX_EN | METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
756 mace->eth.dma_ctrl = priv->dma_ctrl;
757
758 /* Enable interrupt */
759 spin_unlock_irqrestore(&priv->meth_lock, flags);
760
761 dev->trans_start = jiffies; /* prevent tx timeout */
762 netif_wake_queue(dev);
763 }
764
765 /*
766 * Ioctl commands
767 */
768 static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
769 {
770 /* XXX Not yet implemented */
771 switch(cmd) {
772 case SIOCGMIIPHY:
773 case SIOCGMIIREG:
774 case SIOCSMIIREG:
775 default:
776 return -EOPNOTSUPP;
777 }
778 }
779
780 static void meth_set_rx_mode(struct net_device *dev)
781 {
782 struct meth_private *priv = netdev_priv(dev);
783 unsigned long flags;
784
785 netif_stop_queue(dev);
786 spin_lock_irqsave(&priv->meth_lock, flags);
787 priv->mac_ctrl &= ~METH_PROMISC;
788
789 if (dev->flags & IFF_PROMISC) {
790 priv->mac_ctrl |= METH_PROMISC;
791 priv->mcast_filter = 0xffffffffffffffffUL;
792 } else if ((netdev_mc_count(dev) > METH_MCF_LIMIT) ||
793 (dev->flags & IFF_ALLMULTI)) {
794 priv->mac_ctrl |= METH_ACCEPT_AMCAST;
795 priv->mcast_filter = 0xffffffffffffffffUL;
796 } else {
797 struct netdev_hw_addr *ha;
798 priv->mac_ctrl |= METH_ACCEPT_MCAST;
799
800 netdev_for_each_mc_addr(ha, dev)
801 set_bit((ether_crc(ETH_ALEN, ha->addr) >> 26),
802 (volatile unsigned long *)&priv->mcast_filter);
803 }
804
805 /* Write the changes to the chip registers. */
806 mace->eth.mac_ctrl = priv->mac_ctrl;
807 mace->eth.mcast_filter = priv->mcast_filter;
808
809 /* Done! */
810 spin_unlock_irqrestore(&priv->meth_lock, flags);
811 netif_wake_queue(dev);
812 }
813
814 static const struct net_device_ops meth_netdev_ops = {
815 .ndo_open = meth_open,
816 .ndo_stop = meth_release,
817 .ndo_start_xmit = meth_tx,
818 .ndo_do_ioctl = meth_ioctl,
819 .ndo_tx_timeout = meth_tx_timeout,
820 .ndo_change_mtu = eth_change_mtu,
821 .ndo_validate_addr = eth_validate_addr,
822 .ndo_set_mac_address = eth_mac_addr,
823 .ndo_set_rx_mode = meth_set_rx_mode,
824 };
825
826 /*
827 * The init function.
828 */
829 static int meth_probe(struct platform_device *pdev)
830 {
831 struct net_device *dev;
832 struct meth_private *priv;
833 int err;
834
835 dev = alloc_etherdev(sizeof(struct meth_private));
836 if (!dev)
837 return -ENOMEM;
838
839 dev->netdev_ops = &meth_netdev_ops;
840 dev->watchdog_timeo = timeout;
841 dev->irq = MACE_ETHERNET_IRQ;
842 dev->base_addr = (unsigned long)&mace->eth;
843 memcpy(dev->dev_addr, o2meth_eaddr, 6);
844
845 priv = netdev_priv(dev);
846 spin_lock_init(&priv->meth_lock);
847 SET_NETDEV_DEV(dev, &pdev->dev);
848
849 err = register_netdev(dev);
850 if (err) {
851 free_netdev(dev);
852 return err;
853 }
854
855 printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
856 dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));
857 return 0;
858 }
859
860 static int __exit meth_remove(struct platform_device *pdev)
861 {
862 struct net_device *dev = platform_get_drvdata(pdev);
863
864 unregister_netdev(dev);
865 free_netdev(dev);
866
867 return 0;
868 }
869
870 static struct platform_driver meth_driver = {
871 .probe = meth_probe,
872 .remove = __exit_p(meth_remove),
873 .driver = {
874 .name = "meth",
875 .owner = THIS_MODULE,
876 }
877 };
878
879 module_platform_driver(meth_driver);
880
881 MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
882 MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
883 MODULE_LICENSE("GPL");
884 MODULE_ALIAS("platform:meth");
Linux kernel - Deliverables
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