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drivers/net: Add module.h to drivers who were implicitly using it
[deliverable/linux.git] / drivers / net / ethernet / smsc / smsc9420.c
1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 ***************************************************************************
20 */
21
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/netdevice.h>
25 #include <linux/phy.h>
26 #include <linux/pci.h>
27 #include <linux/if_vlan.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/crc32.h>
30 #include <linux/slab.h>
31 #include <linux/module.h>
32 #include <asm/unaligned.h>
33 #include "smsc9420.h"
34
35 #define DRV_NAME "smsc9420"
36 #define PFX DRV_NAME ": "
37 #define DRV_MDIONAME "smsc9420-mdio"
38 #define DRV_DESCRIPTION "SMSC LAN9420 driver"
39 #define DRV_VERSION "1.01"
40
41 MODULE_LICENSE("GPL");
42 MODULE_VERSION(DRV_VERSION);
43
44 struct smsc9420_dma_desc {
45 u32 status;
46 u32 length;
47 u32 buffer1;
48 u32 buffer2;
49 };
50
51 struct smsc9420_ring_info {
52 struct sk_buff *skb;
53 dma_addr_t mapping;
54 };
55
56 struct smsc9420_pdata {
57 void __iomem *base_addr;
58 struct pci_dev *pdev;
59 struct net_device *dev;
60
61 struct smsc9420_dma_desc *rx_ring;
62 struct smsc9420_dma_desc *tx_ring;
63 struct smsc9420_ring_info *tx_buffers;
64 struct smsc9420_ring_info *rx_buffers;
65 dma_addr_t rx_dma_addr;
66 dma_addr_t tx_dma_addr;
67 int tx_ring_head, tx_ring_tail;
68 int rx_ring_head, rx_ring_tail;
69
70 spinlock_t int_lock;
71 spinlock_t phy_lock;
72
73 struct napi_struct napi;
74
75 bool software_irq_signal;
76 bool rx_csum;
77 u32 msg_enable;
78
79 struct phy_device *phy_dev;
80 struct mii_bus *mii_bus;
81 int phy_irq[PHY_MAX_ADDR];
82 int last_duplex;
83 int last_carrier;
84 };
85
86 static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = {
87 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
88 { 0, }
89 };
90
91 MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
92
93 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
94
95 static uint smsc_debug;
96 static uint debug = -1;
97 module_param(debug, uint, 0);
98 MODULE_PARM_DESC(debug, "debug level");
99
100 #define smsc_dbg(TYPE, f, a...) \
101 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
102 printk(KERN_DEBUG PFX f "\n", ## a); \
103 } while (0)
104
105 #define smsc_info(TYPE, f, a...) \
106 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
107 printk(KERN_INFO PFX f "\n", ## a); \
108 } while (0)
109
110 #define smsc_warn(TYPE, f, a...) \
111 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
112 printk(KERN_WARNING PFX f "\n", ## a); \
113 } while (0)
114
115 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
116 {
117 return ioread32(pd->base_addr + offset);
118 }
119
120 static inline void
121 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
122 {
123 iowrite32(value, pd->base_addr + offset);
124 }
125
126 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
127 {
128 /* to ensure PCI write completion, we must perform a PCI read */
129 smsc9420_reg_read(pd, ID_REV);
130 }
131
132 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
133 {
134 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
135 unsigned long flags;
136 u32 addr;
137 int i, reg = -EIO;
138
139 spin_lock_irqsave(&pd->phy_lock, flags);
140
141 /* confirm MII not busy */
142 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
143 smsc_warn(DRV, "MII is busy???");
144 goto out;
145 }
146
147 /* set the address, index & direction (read from PHY) */
148 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
149 MII_ACCESS_MII_READ_;
150 smsc9420_reg_write(pd, MII_ACCESS, addr);
151
152 /* wait for read to complete with 50us timeout */
153 for (i = 0; i < 5; i++) {
154 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
155 MII_ACCESS_MII_BUSY_)) {
156 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
157 goto out;
158 }
159 udelay(10);
160 }
161
162 smsc_warn(DRV, "MII busy timeout!");
163
164 out:
165 spin_unlock_irqrestore(&pd->phy_lock, flags);
166 return reg;
167 }
168
169 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
170 u16 val)
171 {
172 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
173 unsigned long flags;
174 u32 addr;
175 int i, reg = -EIO;
176
177 spin_lock_irqsave(&pd->phy_lock, flags);
178
179 /* confirm MII not busy */
180 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
181 smsc_warn(DRV, "MII is busy???");
182 goto out;
183 }
184
185 /* put the data to write in the MAC */
186 smsc9420_reg_write(pd, MII_DATA, (u32)val);
187
188 /* set the address, index & direction (write to PHY) */
189 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
190 MII_ACCESS_MII_WRITE_;
191 smsc9420_reg_write(pd, MII_ACCESS, addr);
192
193 /* wait for write to complete with 50us timeout */
194 for (i = 0; i < 5; i++) {
195 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
196 MII_ACCESS_MII_BUSY_)) {
197 reg = 0;
198 goto out;
199 }
200 udelay(10);
201 }
202
203 smsc_warn(DRV, "MII busy timeout!");
204
205 out:
206 spin_unlock_irqrestore(&pd->phy_lock, flags);
207 return reg;
208 }
209
210 /* Returns hash bit number for given MAC address
211 * Example:
212 * 01 00 5E 00 00 01 -> returns bit number 31 */
213 static u32 smsc9420_hash(u8 addr[ETH_ALEN])
214 {
215 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
216 }
217
218 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
219 {
220 int timeout = 100000;
221
222 BUG_ON(!pd);
223
224 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
225 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy");
226 return -EIO;
227 }
228
229 smsc9420_reg_write(pd, E2P_CMD,
230 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
231
232 do {
233 udelay(10);
234 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
235 return 0;
236 } while (timeout--);
237
238 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out");
239 return -EIO;
240 }
241
242 /* Standard ioctls for mii-tool */
243 static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
244 {
245 struct smsc9420_pdata *pd = netdev_priv(dev);
246
247 if (!netif_running(dev) || !pd->phy_dev)
248 return -EINVAL;
249
250 return phy_mii_ioctl(pd->phy_dev, ifr, cmd);
251 }
252
253 static int smsc9420_ethtool_get_settings(struct net_device *dev,
254 struct ethtool_cmd *cmd)
255 {
256 struct smsc9420_pdata *pd = netdev_priv(dev);
257
258 if (!pd->phy_dev)
259 return -ENODEV;
260
261 cmd->maxtxpkt = 1;
262 cmd->maxrxpkt = 1;
263 return phy_ethtool_gset(pd->phy_dev, cmd);
264 }
265
266 static int smsc9420_ethtool_set_settings(struct net_device *dev,
267 struct ethtool_cmd *cmd)
268 {
269 struct smsc9420_pdata *pd = netdev_priv(dev);
270
271 if (!pd->phy_dev)
272 return -ENODEV;
273
274 return phy_ethtool_sset(pd->phy_dev, cmd);
275 }
276
277 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
278 struct ethtool_drvinfo *drvinfo)
279 {
280 struct smsc9420_pdata *pd = netdev_priv(netdev);
281
282 strcpy(drvinfo->driver, DRV_NAME);
283 strcpy(drvinfo->bus_info, pci_name(pd->pdev));
284 strcpy(drvinfo->version, DRV_VERSION);
285 }
286
287 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
288 {
289 struct smsc9420_pdata *pd = netdev_priv(netdev);
290 return pd->msg_enable;
291 }
292
293 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
294 {
295 struct smsc9420_pdata *pd = netdev_priv(netdev);
296 pd->msg_enable = data;
297 }
298
299 static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
300 {
301 struct smsc9420_pdata *pd = netdev_priv(netdev);
302
303 if (!pd->phy_dev)
304 return -ENODEV;
305
306 return phy_start_aneg(pd->phy_dev);
307 }
308
309 static int smsc9420_ethtool_getregslen(struct net_device *dev)
310 {
311 /* all smsc9420 registers plus all phy registers */
312 return 0x100 + (32 * sizeof(u32));
313 }
314
315 static void
316 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
317 void *buf)
318 {
319 struct smsc9420_pdata *pd = netdev_priv(dev);
320 struct phy_device *phy_dev = pd->phy_dev;
321 unsigned int i, j = 0;
322 u32 *data = buf;
323
324 regs->version = smsc9420_reg_read(pd, ID_REV);
325 for (i = 0; i < 0x100; i += (sizeof(u32)))
326 data[j++] = smsc9420_reg_read(pd, i);
327
328 // cannot read phy registers if the net device is down
329 if (!phy_dev)
330 return;
331
332 for (i = 0; i <= 31; i++)
333 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i);
334 }
335
336 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
337 {
338 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
339 temp &= ~GPIO_CFG_EEPR_EN_;
340 smsc9420_reg_write(pd, GPIO_CFG, temp);
341 msleep(1);
342 }
343
344 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
345 {
346 int timeout = 100;
347 u32 e2cmd;
348
349 smsc_dbg(HW, "op 0x%08x", op);
350 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
351 smsc_warn(HW, "Busy at start");
352 return -EBUSY;
353 }
354
355 e2cmd = op | E2P_CMD_EPC_BUSY_;
356 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
357
358 do {
359 msleep(1);
360 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
361 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
362
363 if (!timeout) {
364 smsc_info(HW, "TIMED OUT");
365 return -EAGAIN;
366 }
367
368 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
369 smsc_info(HW, "Error occurred during eeprom operation");
370 return -EINVAL;
371 }
372
373 return 0;
374 }
375
376 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
377 u8 address, u8 *data)
378 {
379 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
380 int ret;
381
382 smsc_dbg(HW, "address 0x%x", address);
383 ret = smsc9420_eeprom_send_cmd(pd, op);
384
385 if (!ret)
386 data[address] = smsc9420_reg_read(pd, E2P_DATA);
387
388 return ret;
389 }
390
391 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
392 u8 address, u8 data)
393 {
394 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
395 int ret;
396
397 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data);
398 ret = smsc9420_eeprom_send_cmd(pd, op);
399
400 if (!ret) {
401 op = E2P_CMD_EPC_CMD_WRITE_ | address;
402 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
403 ret = smsc9420_eeprom_send_cmd(pd, op);
404 }
405
406 return ret;
407 }
408
409 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
410 {
411 return SMSC9420_EEPROM_SIZE;
412 }
413
414 static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
415 struct ethtool_eeprom *eeprom, u8 *data)
416 {
417 struct smsc9420_pdata *pd = netdev_priv(dev);
418 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
419 int len, i;
420
421 smsc9420_eeprom_enable_access(pd);
422
423 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
424 for (i = 0; i < len; i++) {
425 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
426 if (ret < 0) {
427 eeprom->len = 0;
428 return ret;
429 }
430 }
431
432 memcpy(data, &eeprom_data[eeprom->offset], len);
433 eeprom->magic = SMSC9420_EEPROM_MAGIC;
434 eeprom->len = len;
435 return 0;
436 }
437
438 static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
439 struct ethtool_eeprom *eeprom, u8 *data)
440 {
441 struct smsc9420_pdata *pd = netdev_priv(dev);
442 int ret;
443
444 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
445 return -EINVAL;
446
447 smsc9420_eeprom_enable_access(pd);
448 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
449 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
450 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
451
452 /* Single byte write, according to man page */
453 eeprom->len = 1;
454
455 return ret;
456 }
457
458 static const struct ethtool_ops smsc9420_ethtool_ops = {
459 .get_settings = smsc9420_ethtool_get_settings,
460 .set_settings = smsc9420_ethtool_set_settings,
461 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
462 .get_msglevel = smsc9420_ethtool_get_msglevel,
463 .set_msglevel = smsc9420_ethtool_set_msglevel,
464 .nway_reset = smsc9420_ethtool_nway_reset,
465 .get_link = ethtool_op_get_link,
466 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
467 .get_eeprom = smsc9420_ethtool_get_eeprom,
468 .set_eeprom = smsc9420_ethtool_set_eeprom,
469 .get_regs_len = smsc9420_ethtool_getregslen,
470 .get_regs = smsc9420_ethtool_getregs,
471 };
472
473 /* Sets the device MAC address to dev_addr */
474 static void smsc9420_set_mac_address(struct net_device *dev)
475 {
476 struct smsc9420_pdata *pd = netdev_priv(dev);
477 u8 *dev_addr = dev->dev_addr;
478 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
479 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
480 (dev_addr[1] << 8) | dev_addr[0];
481
482 smsc9420_reg_write(pd, ADDRH, mac_high16);
483 smsc9420_reg_write(pd, ADDRL, mac_low32);
484 }
485
486 static void smsc9420_check_mac_address(struct net_device *dev)
487 {
488 struct smsc9420_pdata *pd = netdev_priv(dev);
489
490 /* Check if mac address has been specified when bringing interface up */
491 if (is_valid_ether_addr(dev->dev_addr)) {
492 smsc9420_set_mac_address(dev);
493 smsc_dbg(PROBE, "MAC Address is specified by configuration");
494 } else {
495 /* Try reading mac address from device. if EEPROM is present
496 * it will already have been set */
497 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
498 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
499 dev->dev_addr[0] = (u8)(mac_low32);
500 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
501 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
502 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
503 dev->dev_addr[4] = (u8)(mac_high16);
504 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
505
506 if (is_valid_ether_addr(dev->dev_addr)) {
507 /* eeprom values are valid so use them */
508 smsc_dbg(PROBE, "Mac Address is read from EEPROM");
509 } else {
510 /* eeprom values are invalid, generate random MAC */
511 random_ether_addr(dev->dev_addr);
512 smsc9420_set_mac_address(dev);
513 smsc_dbg(PROBE,
514 "MAC Address is set to random_ether_addr");
515 }
516 }
517 }
518
519 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
520 {
521 u32 dmac_control, mac_cr, dma_intr_ena;
522 int timeout = 1000;
523
524 /* disable TX DMAC */
525 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
526 dmac_control &= (~DMAC_CONTROL_ST_);
527 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
528
529 /* Wait max 10ms for transmit process to stop */
530 while (--timeout) {
531 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
532 break;
533 udelay(10);
534 }
535
536 if (!timeout)
537 smsc_warn(IFDOWN, "TX DMAC failed to stop");
538
539 /* ACK Tx DMAC stop bit */
540 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
541
542 /* mask TX DMAC interrupts */
543 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
544 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
545 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
546 smsc9420_pci_flush_write(pd);
547
548 /* stop MAC TX */
549 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
550 smsc9420_reg_write(pd, MAC_CR, mac_cr);
551 smsc9420_pci_flush_write(pd);
552 }
553
554 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
555 {
556 int i;
557
558 BUG_ON(!pd->tx_ring);
559
560 if (!pd->tx_buffers)
561 return;
562
563 for (i = 0; i < TX_RING_SIZE; i++) {
564 struct sk_buff *skb = pd->tx_buffers[i].skb;
565
566 if (skb) {
567 BUG_ON(!pd->tx_buffers[i].mapping);
568 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
569 skb->len, PCI_DMA_TODEVICE);
570 dev_kfree_skb_any(skb);
571 }
572
573 pd->tx_ring[i].status = 0;
574 pd->tx_ring[i].length = 0;
575 pd->tx_ring[i].buffer1 = 0;
576 pd->tx_ring[i].buffer2 = 0;
577 }
578 wmb();
579
580 kfree(pd->tx_buffers);
581 pd->tx_buffers = NULL;
582
583 pd->tx_ring_head = 0;
584 pd->tx_ring_tail = 0;
585 }
586
587 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
588 {
589 int i;
590
591 BUG_ON(!pd->rx_ring);
592
593 if (!pd->rx_buffers)
594 return;
595
596 for (i = 0; i < RX_RING_SIZE; i++) {
597 if (pd->rx_buffers[i].skb)
598 dev_kfree_skb_any(pd->rx_buffers[i].skb);
599
600 if (pd->rx_buffers[i].mapping)
601 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
602 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
603
604 pd->rx_ring[i].status = 0;
605 pd->rx_ring[i].length = 0;
606 pd->rx_ring[i].buffer1 = 0;
607 pd->rx_ring[i].buffer2 = 0;
608 }
609 wmb();
610
611 kfree(pd->rx_buffers);
612 pd->rx_buffers = NULL;
613
614 pd->rx_ring_head = 0;
615 pd->rx_ring_tail = 0;
616 }
617
618 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
619 {
620 int timeout = 1000;
621 u32 mac_cr, dmac_control, dma_intr_ena;
622
623 /* mask RX DMAC interrupts */
624 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
625 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
626 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
627 smsc9420_pci_flush_write(pd);
628
629 /* stop RX MAC prior to stoping DMA */
630 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
631 smsc9420_reg_write(pd, MAC_CR, mac_cr);
632 smsc9420_pci_flush_write(pd);
633
634 /* stop RX DMAC */
635 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
636 dmac_control &= (~DMAC_CONTROL_SR_);
637 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
638 smsc9420_pci_flush_write(pd);
639
640 /* wait up to 10ms for receive to stop */
641 while (--timeout) {
642 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
643 break;
644 udelay(10);
645 }
646
647 if (!timeout)
648 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout.");
649
650 /* ACK the Rx DMAC stop bit */
651 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
652 }
653
654 static irqreturn_t smsc9420_isr(int irq, void *dev_id)
655 {
656 struct smsc9420_pdata *pd = dev_id;
657 u32 int_cfg, int_sts, int_ctl;
658 irqreturn_t ret = IRQ_NONE;
659 ulong flags;
660
661 BUG_ON(!pd);
662 BUG_ON(!pd->base_addr);
663
664 int_cfg = smsc9420_reg_read(pd, INT_CFG);
665
666 /* check if it's our interrupt */
667 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
668 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
669 return IRQ_NONE;
670
671 int_sts = smsc9420_reg_read(pd, INT_STAT);
672
673 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
674 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
675 u32 ints_to_clear = 0;
676
677 if (status & DMAC_STS_TX_) {
678 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
679 netif_wake_queue(pd->dev);
680 }
681
682 if (status & DMAC_STS_RX_) {
683 /* mask RX DMAC interrupts */
684 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
685 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
686 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
687 smsc9420_pci_flush_write(pd);
688
689 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
690 napi_schedule(&pd->napi);
691 }
692
693 if (ints_to_clear)
694 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
695
696 ret = IRQ_HANDLED;
697 }
698
699 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
700 /* mask software interrupt */
701 spin_lock_irqsave(&pd->int_lock, flags);
702 int_ctl = smsc9420_reg_read(pd, INT_CTL);
703 int_ctl &= (~INT_CTL_SW_INT_EN_);
704 smsc9420_reg_write(pd, INT_CTL, int_ctl);
705 spin_unlock_irqrestore(&pd->int_lock, flags);
706
707 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
708 pd->software_irq_signal = true;
709 smp_wmb();
710
711 ret = IRQ_HANDLED;
712 }
713
714 /* to ensure PCI write completion, we must perform a PCI read */
715 smsc9420_pci_flush_write(pd);
716
717 return ret;
718 }
719
720 #ifdef CONFIG_NET_POLL_CONTROLLER
721 static void smsc9420_poll_controller(struct net_device *dev)
722 {
723 disable_irq(dev->irq);
724 smsc9420_isr(0, dev);
725 enable_irq(dev->irq);
726 }
727 #endif /* CONFIG_NET_POLL_CONTROLLER */
728
729 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
730 {
731 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
732 smsc9420_reg_read(pd, BUS_MODE);
733 udelay(2);
734 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
735 smsc_warn(DRV, "Software reset not cleared");
736 }
737
738 static int smsc9420_stop(struct net_device *dev)
739 {
740 struct smsc9420_pdata *pd = netdev_priv(dev);
741 u32 int_cfg;
742 ulong flags;
743
744 BUG_ON(!pd);
745 BUG_ON(!pd->phy_dev);
746
747 /* disable master interrupt */
748 spin_lock_irqsave(&pd->int_lock, flags);
749 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
750 smsc9420_reg_write(pd, INT_CFG, int_cfg);
751 spin_unlock_irqrestore(&pd->int_lock, flags);
752
753 netif_tx_disable(dev);
754 napi_disable(&pd->napi);
755
756 smsc9420_stop_tx(pd);
757 smsc9420_free_tx_ring(pd);
758
759 smsc9420_stop_rx(pd);
760 smsc9420_free_rx_ring(pd);
761
762 free_irq(dev->irq, pd);
763
764 smsc9420_dmac_soft_reset(pd);
765
766 phy_stop(pd->phy_dev);
767
768 phy_disconnect(pd->phy_dev);
769 pd->phy_dev = NULL;
770 mdiobus_unregister(pd->mii_bus);
771 mdiobus_free(pd->mii_bus);
772
773 return 0;
774 }
775
776 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
777 {
778 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
779 dev->stats.rx_errors++;
780 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
781 dev->stats.rx_over_errors++;
782 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
783 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
784 dev->stats.rx_frame_errors++;
785 else if (desc_status & RDES0_CRC_ERROR_)
786 dev->stats.rx_crc_errors++;
787 }
788
789 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
790 dev->stats.rx_length_errors++;
791
792 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
793 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
794 dev->stats.rx_length_errors++;
795
796 if (desc_status & RDES0_MULTICAST_FRAME_)
797 dev->stats.multicast++;
798 }
799
800 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
801 const u32 status)
802 {
803 struct net_device *dev = pd->dev;
804 struct sk_buff *skb;
805 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
806 >> RDES0_FRAME_LENGTH_SHFT_;
807
808 /* remove crc from packet lendth */
809 packet_length -= 4;
810
811 if (pd->rx_csum)
812 packet_length -= 2;
813
814 dev->stats.rx_packets++;
815 dev->stats.rx_bytes += packet_length;
816
817 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
818 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
819 pd->rx_buffers[index].mapping = 0;
820
821 skb = pd->rx_buffers[index].skb;
822 pd->rx_buffers[index].skb = NULL;
823
824 if (pd->rx_csum) {
825 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
826 NET_IP_ALIGN + packet_length + 4);
827 put_unaligned_le16(hw_csum, &skb->csum);
828 skb->ip_summed = CHECKSUM_COMPLETE;
829 }
830
831 skb_reserve(skb, NET_IP_ALIGN);
832 skb_put(skb, packet_length);
833
834 skb->protocol = eth_type_trans(skb, dev);
835
836 netif_receive_skb(skb);
837 }
838
839 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
840 {
841 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
842 dma_addr_t mapping;
843
844 BUG_ON(pd->rx_buffers[index].skb);
845 BUG_ON(pd->rx_buffers[index].mapping);
846
847 if (unlikely(!skb)) {
848 smsc_warn(RX_ERR, "Failed to allocate new skb!");
849 return -ENOMEM;
850 }
851
852 skb->dev = pd->dev;
853
854 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
855 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
856 if (pci_dma_mapping_error(pd->pdev, mapping)) {
857 dev_kfree_skb_any(skb);
858 smsc_warn(RX_ERR, "pci_map_single failed!");
859 return -ENOMEM;
860 }
861
862 pd->rx_buffers[index].skb = skb;
863 pd->rx_buffers[index].mapping = mapping;
864 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
865 pd->rx_ring[index].status = RDES0_OWN_;
866 wmb();
867
868 return 0;
869 }
870
871 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
872 {
873 while (pd->rx_ring_tail != pd->rx_ring_head) {
874 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
875 break;
876
877 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
878 }
879 }
880
881 static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
882 {
883 struct smsc9420_pdata *pd =
884 container_of(napi, struct smsc9420_pdata, napi);
885 struct net_device *dev = pd->dev;
886 u32 drop_frame_cnt, dma_intr_ena, status;
887 int work_done;
888
889 for (work_done = 0; work_done < budget; work_done++) {
890 rmb();
891 status = pd->rx_ring[pd->rx_ring_head].status;
892
893 /* stop if DMAC owns this dma descriptor */
894 if (status & RDES0_OWN_)
895 break;
896
897 smsc9420_rx_count_stats(dev, status);
898 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
899 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
900 smsc9420_alloc_new_rx_buffers(pd);
901 }
902
903 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
904 dev->stats.rx_dropped +=
905 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
906
907 /* Kick RXDMA */
908 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
909 smsc9420_pci_flush_write(pd);
910
911 if (work_done < budget) {
912 napi_complete(&pd->napi);
913
914 /* re-enable RX DMA interrupts */
915 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
916 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
917 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
918 smsc9420_pci_flush_write(pd);
919 }
920 return work_done;
921 }
922
923 static void
924 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
925 {
926 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
927 dev->stats.tx_errors++;
928 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
929 TDES0_EXCESSIVE_COLLISIONS_))
930 dev->stats.tx_aborted_errors++;
931
932 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
933 dev->stats.tx_carrier_errors++;
934 } else {
935 dev->stats.tx_packets++;
936 dev->stats.tx_bytes += (length & 0x7FF);
937 }
938
939 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
940 dev->stats.collisions += 16;
941 } else {
942 dev->stats.collisions +=
943 (status & TDES0_COLLISION_COUNT_MASK_) >>
944 TDES0_COLLISION_COUNT_SHFT_;
945 }
946
947 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
948 dev->stats.tx_heartbeat_errors++;
949 }
950
951 /* Check for completed dma transfers, update stats and free skbs */
952 static void smsc9420_complete_tx(struct net_device *dev)
953 {
954 struct smsc9420_pdata *pd = netdev_priv(dev);
955
956 while (pd->tx_ring_tail != pd->tx_ring_head) {
957 int index = pd->tx_ring_tail;
958 u32 status, length;
959
960 rmb();
961 status = pd->tx_ring[index].status;
962 length = pd->tx_ring[index].length;
963
964 /* Check if DMA still owns this descriptor */
965 if (unlikely(TDES0_OWN_ & status))
966 break;
967
968 smsc9420_tx_update_stats(dev, status, length);
969
970 BUG_ON(!pd->tx_buffers[index].skb);
971 BUG_ON(!pd->tx_buffers[index].mapping);
972
973 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
974 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
975 pd->tx_buffers[index].mapping = 0;
976
977 dev_kfree_skb_any(pd->tx_buffers[index].skb);
978 pd->tx_buffers[index].skb = NULL;
979
980 pd->tx_ring[index].buffer1 = 0;
981 wmb();
982
983 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
984 }
985 }
986
987 static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
988 struct net_device *dev)
989 {
990 struct smsc9420_pdata *pd = netdev_priv(dev);
991 dma_addr_t mapping;
992 int index = pd->tx_ring_head;
993 u32 tmp_desc1;
994 bool about_to_take_last_desc =
995 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
996
997 smsc9420_complete_tx(dev);
998
999 rmb();
1000 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
1001 BUG_ON(pd->tx_buffers[index].skb);
1002 BUG_ON(pd->tx_buffers[index].mapping);
1003
1004 mapping = pci_map_single(pd->pdev, skb->data,
1005 skb->len, PCI_DMA_TODEVICE);
1006 if (pci_dma_mapping_error(pd->pdev, mapping)) {
1007 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet");
1008 return NETDEV_TX_BUSY;
1009 }
1010
1011 pd->tx_buffers[index].skb = skb;
1012 pd->tx_buffers[index].mapping = mapping;
1013
1014 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
1015 if (unlikely(about_to_take_last_desc)) {
1016 tmp_desc1 |= TDES1_IC_;
1017 netif_stop_queue(pd->dev);
1018 }
1019
1020 /* check if we are at the last descriptor and need to set EOR */
1021 if (unlikely(index == (TX_RING_SIZE - 1)))
1022 tmp_desc1 |= TDES1_TER_;
1023
1024 pd->tx_ring[index].buffer1 = mapping;
1025 pd->tx_ring[index].length = tmp_desc1;
1026 wmb();
1027
1028 /* increment head */
1029 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
1030
1031 /* assign ownership to DMAC */
1032 pd->tx_ring[index].status = TDES0_OWN_;
1033 wmb();
1034
1035 skb_tx_timestamp(skb);
1036
1037 /* kick the DMA */
1038 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
1039 smsc9420_pci_flush_write(pd);
1040
1041 return NETDEV_TX_OK;
1042 }
1043
1044 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
1045 {
1046 struct smsc9420_pdata *pd = netdev_priv(dev);
1047 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1048 dev->stats.rx_dropped +=
1049 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
1050 return &dev->stats;
1051 }
1052
1053 static void smsc9420_set_multicast_list(struct net_device *dev)
1054 {
1055 struct smsc9420_pdata *pd = netdev_priv(dev);
1056 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1057
1058 if (dev->flags & IFF_PROMISC) {
1059 smsc_dbg(HW, "Promiscuous Mode Enabled");
1060 mac_cr |= MAC_CR_PRMS_;
1061 mac_cr &= (~MAC_CR_MCPAS_);
1062 mac_cr &= (~MAC_CR_HPFILT_);
1063 } else if (dev->flags & IFF_ALLMULTI) {
1064 smsc_dbg(HW, "Receive all Multicast Enabled");
1065 mac_cr &= (~MAC_CR_PRMS_);
1066 mac_cr |= MAC_CR_MCPAS_;
1067 mac_cr &= (~MAC_CR_HPFILT_);
1068 } else if (!netdev_mc_empty(dev)) {
1069 struct netdev_hw_addr *ha;
1070 u32 hash_lo = 0, hash_hi = 0;
1071
1072 smsc_dbg(HW, "Multicast filter enabled");
1073 netdev_for_each_mc_addr(ha, dev) {
1074 u32 bit_num = smsc9420_hash(ha->addr);
1075 u32 mask = 1 << (bit_num & 0x1F);
1076
1077 if (bit_num & 0x20)
1078 hash_hi |= mask;
1079 else
1080 hash_lo |= mask;
1081
1082 }
1083 smsc9420_reg_write(pd, HASHH, hash_hi);
1084 smsc9420_reg_write(pd, HASHL, hash_lo);
1085
1086 mac_cr &= (~MAC_CR_PRMS_);
1087 mac_cr &= (~MAC_CR_MCPAS_);
1088 mac_cr |= MAC_CR_HPFILT_;
1089 } else {
1090 smsc_dbg(HW, "Receive own packets only.");
1091 smsc9420_reg_write(pd, HASHH, 0);
1092 smsc9420_reg_write(pd, HASHL, 0);
1093
1094 mac_cr &= (~MAC_CR_PRMS_);
1095 mac_cr &= (~MAC_CR_MCPAS_);
1096 mac_cr &= (~MAC_CR_HPFILT_);
1097 }
1098
1099 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1100 smsc9420_pci_flush_write(pd);
1101 }
1102
1103 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1104 {
1105 struct phy_device *phy_dev = pd->phy_dev;
1106 u32 flow;
1107
1108 if (phy_dev->duplex == DUPLEX_FULL) {
1109 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1110 u16 rmtadv = phy_read(phy_dev, MII_LPA);
1111 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1112
1113 if (cap & FLOW_CTRL_RX)
1114 flow = 0xFFFF0002;
1115 else
1116 flow = 0;
1117
1118 smsc_info(LINK, "rx pause %s, tx pause %s",
1119 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1120 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1121 } else {
1122 smsc_info(LINK, "half duplex");
1123 flow = 0;
1124 }
1125
1126 smsc9420_reg_write(pd, FLOW, flow);
1127 }
1128
1129 /* Update link mode if anything has changed. Called periodically when the
1130 * PHY is in polling mode, even if nothing has changed. */
1131 static void smsc9420_phy_adjust_link(struct net_device *dev)
1132 {
1133 struct smsc9420_pdata *pd = netdev_priv(dev);
1134 struct phy_device *phy_dev = pd->phy_dev;
1135 int carrier;
1136
1137 if (phy_dev->duplex != pd->last_duplex) {
1138 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1139 if (phy_dev->duplex) {
1140 smsc_dbg(LINK, "full duplex mode");
1141 mac_cr |= MAC_CR_FDPX_;
1142 } else {
1143 smsc_dbg(LINK, "half duplex mode");
1144 mac_cr &= ~MAC_CR_FDPX_;
1145 }
1146 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1147
1148 smsc9420_phy_update_flowcontrol(pd);
1149 pd->last_duplex = phy_dev->duplex;
1150 }
1151
1152 carrier = netif_carrier_ok(dev);
1153 if (carrier != pd->last_carrier) {
1154 if (carrier)
1155 smsc_dbg(LINK, "carrier OK");
1156 else
1157 smsc_dbg(LINK, "no carrier");
1158 pd->last_carrier = carrier;
1159 }
1160 }
1161
1162 static int smsc9420_mii_probe(struct net_device *dev)
1163 {
1164 struct smsc9420_pdata *pd = netdev_priv(dev);
1165 struct phy_device *phydev = NULL;
1166
1167 BUG_ON(pd->phy_dev);
1168
1169 /* Device only supports internal PHY at address 1 */
1170 if (!pd->mii_bus->phy_map[1]) {
1171 pr_err("%s: no PHY found at address 1\n", dev->name);
1172 return -ENODEV;
1173 }
1174
1175 phydev = pd->mii_bus->phy_map[1];
1176 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr,
1177 phydev->phy_id);
1178
1179 phydev = phy_connect(dev, dev_name(&phydev->dev),
1180 smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII);
1181
1182 if (IS_ERR(phydev)) {
1183 pr_err("%s: Could not attach to PHY\n", dev->name);
1184 return PTR_ERR(phydev);
1185 }
1186
1187 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1188 dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1189
1190 /* mask with MAC supported features */
1191 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1192 SUPPORTED_Asym_Pause);
1193 phydev->advertising = phydev->supported;
1194
1195 pd->phy_dev = phydev;
1196 pd->last_duplex = -1;
1197 pd->last_carrier = -1;
1198
1199 return 0;
1200 }
1201
1202 static int smsc9420_mii_init(struct net_device *dev)
1203 {
1204 struct smsc9420_pdata *pd = netdev_priv(dev);
1205 int err = -ENXIO, i;
1206
1207 pd->mii_bus = mdiobus_alloc();
1208 if (!pd->mii_bus) {
1209 err = -ENOMEM;
1210 goto err_out_1;
1211 }
1212 pd->mii_bus->name = DRV_MDIONAME;
1213 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1214 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1215 pd->mii_bus->priv = pd;
1216 pd->mii_bus->read = smsc9420_mii_read;
1217 pd->mii_bus->write = smsc9420_mii_write;
1218 pd->mii_bus->irq = pd->phy_irq;
1219 for (i = 0; i < PHY_MAX_ADDR; ++i)
1220 pd->mii_bus->irq[i] = PHY_POLL;
1221
1222 /* Mask all PHYs except ID 1 (internal) */
1223 pd->mii_bus->phy_mask = ~(1 << 1);
1224
1225 if (mdiobus_register(pd->mii_bus)) {
1226 smsc_warn(PROBE, "Error registering mii bus");
1227 goto err_out_free_bus_2;
1228 }
1229
1230 if (smsc9420_mii_probe(dev) < 0) {
1231 smsc_warn(PROBE, "Error probing mii bus");
1232 goto err_out_unregister_bus_3;
1233 }
1234
1235 return 0;
1236
1237 err_out_unregister_bus_3:
1238 mdiobus_unregister(pd->mii_bus);
1239 err_out_free_bus_2:
1240 mdiobus_free(pd->mii_bus);
1241 err_out_1:
1242 return err;
1243 }
1244
1245 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1246 {
1247 int i;
1248
1249 BUG_ON(!pd->tx_ring);
1250
1251 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1252 TX_RING_SIZE), GFP_KERNEL);
1253 if (!pd->tx_buffers) {
1254 smsc_warn(IFUP, "Failed to allocated tx_buffers");
1255 return -ENOMEM;
1256 }
1257
1258 /* Initialize the TX Ring */
1259 for (i = 0; i < TX_RING_SIZE; i++) {
1260 pd->tx_buffers[i].skb = NULL;
1261 pd->tx_buffers[i].mapping = 0;
1262 pd->tx_ring[i].status = 0;
1263 pd->tx_ring[i].length = 0;
1264 pd->tx_ring[i].buffer1 = 0;
1265 pd->tx_ring[i].buffer2 = 0;
1266 }
1267 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1268 wmb();
1269
1270 pd->tx_ring_head = 0;
1271 pd->tx_ring_tail = 0;
1272
1273 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1274 smsc9420_pci_flush_write(pd);
1275
1276 return 0;
1277 }
1278
1279 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1280 {
1281 int i;
1282
1283 BUG_ON(!pd->rx_ring);
1284
1285 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1286 RX_RING_SIZE), GFP_KERNEL);
1287 if (pd->rx_buffers == NULL) {
1288 smsc_warn(IFUP, "Failed to allocated rx_buffers");
1289 goto out;
1290 }
1291
1292 /* initialize the rx ring */
1293 for (i = 0; i < RX_RING_SIZE; i++) {
1294 pd->rx_ring[i].status = 0;
1295 pd->rx_ring[i].length = PKT_BUF_SZ;
1296 pd->rx_ring[i].buffer2 = 0;
1297 pd->rx_buffers[i].skb = NULL;
1298 pd->rx_buffers[i].mapping = 0;
1299 }
1300 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1301
1302 /* now allocate the entire ring of skbs */
1303 for (i = 0; i < RX_RING_SIZE; i++) {
1304 if (smsc9420_alloc_rx_buffer(pd, i)) {
1305 smsc_warn(IFUP, "failed to allocate rx skb %d", i);
1306 goto out_free_rx_skbs;
1307 }
1308 }
1309
1310 pd->rx_ring_head = 0;
1311 pd->rx_ring_tail = 0;
1312
1313 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1314 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1315
1316 if (pd->rx_csum) {
1317 /* Enable RX COE */
1318 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1319 smsc9420_reg_write(pd, COE_CR, coe);
1320 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe);
1321 }
1322
1323 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1324 smsc9420_pci_flush_write(pd);
1325
1326 return 0;
1327
1328 out_free_rx_skbs:
1329 smsc9420_free_rx_ring(pd);
1330 out:
1331 return -ENOMEM;
1332 }
1333
1334 static int smsc9420_open(struct net_device *dev)
1335 {
1336 struct smsc9420_pdata *pd;
1337 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1338 unsigned long flags;
1339 int result = 0, timeout;
1340
1341 BUG_ON(!dev);
1342 pd = netdev_priv(dev);
1343 BUG_ON(!pd);
1344
1345 if (!is_valid_ether_addr(dev->dev_addr)) {
1346 smsc_warn(IFUP, "dev_addr is not a valid MAC address");
1347 result = -EADDRNOTAVAIL;
1348 goto out_0;
1349 }
1350
1351 netif_carrier_off(dev);
1352
1353 /* disable, mask and acknowledge all interrupts */
1354 spin_lock_irqsave(&pd->int_lock, flags);
1355 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1356 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1357 smsc9420_reg_write(pd, INT_CTL, 0);
1358 spin_unlock_irqrestore(&pd->int_lock, flags);
1359 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1360 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1361 smsc9420_pci_flush_write(pd);
1362
1363 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED,
1364 DRV_NAME, pd)) {
1365 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq);
1366 result = -ENODEV;
1367 goto out_0;
1368 }
1369
1370 smsc9420_dmac_soft_reset(pd);
1371
1372 /* make sure MAC_CR is sane */
1373 smsc9420_reg_write(pd, MAC_CR, 0);
1374
1375 smsc9420_set_mac_address(dev);
1376
1377 /* Configure GPIO pins to drive LEDs */
1378 smsc9420_reg_write(pd, GPIO_CFG,
1379 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1380
1381 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1382
1383 #ifdef __BIG_ENDIAN
1384 bus_mode |= BUS_MODE_DBO_;
1385 #endif
1386
1387 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1388
1389 smsc9420_pci_flush_write(pd);
1390
1391 /* set bus master bridge arbitration priority for Rx and TX DMA */
1392 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1393
1394 smsc9420_reg_write(pd, DMAC_CONTROL,
1395 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1396
1397 smsc9420_pci_flush_write(pd);
1398
1399 /* test the IRQ connection to the ISR */
1400 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq);
1401 pd->software_irq_signal = false;
1402
1403 spin_lock_irqsave(&pd->int_lock, flags);
1404 /* configure interrupt deassertion timer and enable interrupts */
1405 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1406 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1407 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1408 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1409
1410 /* unmask software interrupt */
1411 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1412 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1413 spin_unlock_irqrestore(&pd->int_lock, flags);
1414 smsc9420_pci_flush_write(pd);
1415
1416 timeout = 1000;
1417 while (timeout--) {
1418 if (pd->software_irq_signal)
1419 break;
1420 msleep(1);
1421 }
1422
1423 /* disable interrupts */
1424 spin_lock_irqsave(&pd->int_lock, flags);
1425 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1426 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1427 spin_unlock_irqrestore(&pd->int_lock, flags);
1428
1429 if (!pd->software_irq_signal) {
1430 smsc_warn(IFUP, "ISR failed signaling test");
1431 result = -ENODEV;
1432 goto out_free_irq_1;
1433 }
1434
1435 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq);
1436
1437 result = smsc9420_alloc_tx_ring(pd);
1438 if (result) {
1439 smsc_warn(IFUP, "Failed to Initialize tx dma ring");
1440 result = -ENOMEM;
1441 goto out_free_irq_1;
1442 }
1443
1444 result = smsc9420_alloc_rx_ring(pd);
1445 if (result) {
1446 smsc_warn(IFUP, "Failed to Initialize rx dma ring");
1447 result = -ENOMEM;
1448 goto out_free_tx_ring_2;
1449 }
1450
1451 result = smsc9420_mii_init(dev);
1452 if (result) {
1453 smsc_warn(IFUP, "Failed to initialize Phy");
1454 result = -ENODEV;
1455 goto out_free_rx_ring_3;
1456 }
1457
1458 /* Bring the PHY up */
1459 phy_start(pd->phy_dev);
1460
1461 napi_enable(&pd->napi);
1462
1463 /* start tx and rx */
1464 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1465 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1466
1467 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1468 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1469 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1470 smsc9420_pci_flush_write(pd);
1471
1472 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1473 dma_intr_ena |=
1474 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1475 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1476 smsc9420_pci_flush_write(pd);
1477
1478 netif_wake_queue(dev);
1479
1480 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1481
1482 /* enable interrupts */
1483 spin_lock_irqsave(&pd->int_lock, flags);
1484 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1485 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1486 spin_unlock_irqrestore(&pd->int_lock, flags);
1487
1488 return 0;
1489
1490 out_free_rx_ring_3:
1491 smsc9420_free_rx_ring(pd);
1492 out_free_tx_ring_2:
1493 smsc9420_free_tx_ring(pd);
1494 out_free_irq_1:
1495 free_irq(dev->irq, pd);
1496 out_0:
1497 return result;
1498 }
1499
1500 #ifdef CONFIG_PM
1501
1502 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1503 {
1504 struct net_device *dev = pci_get_drvdata(pdev);
1505 struct smsc9420_pdata *pd = netdev_priv(dev);
1506 u32 int_cfg;
1507 ulong flags;
1508
1509 /* disable interrupts */
1510 spin_lock_irqsave(&pd->int_lock, flags);
1511 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1512 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1513 spin_unlock_irqrestore(&pd->int_lock, flags);
1514
1515 if (netif_running(dev)) {
1516 netif_tx_disable(dev);
1517 smsc9420_stop_tx(pd);
1518 smsc9420_free_tx_ring(pd);
1519
1520 napi_disable(&pd->napi);
1521 smsc9420_stop_rx(pd);
1522 smsc9420_free_rx_ring(pd);
1523
1524 free_irq(dev->irq, pd);
1525
1526 netif_device_detach(dev);
1527 }
1528
1529 pci_save_state(pdev);
1530 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1531 pci_disable_device(pdev);
1532 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1533
1534 return 0;
1535 }
1536
1537 static int smsc9420_resume(struct pci_dev *pdev)
1538 {
1539 struct net_device *dev = pci_get_drvdata(pdev);
1540 struct smsc9420_pdata *pd = netdev_priv(dev);
1541 int err;
1542
1543 pci_set_power_state(pdev, PCI_D0);
1544 pci_restore_state(pdev);
1545
1546 err = pci_enable_device(pdev);
1547 if (err)
1548 return err;
1549
1550 pci_set_master(pdev);
1551
1552 err = pci_enable_wake(pdev, 0, 0);
1553 if (err)
1554 smsc_warn(IFUP, "pci_enable_wake failed: %d", err);
1555
1556 if (netif_running(dev)) {
1557 err = smsc9420_open(dev);
1558 netif_device_attach(dev);
1559 }
1560 return err;
1561 }
1562
1563 #endif /* CONFIG_PM */
1564
1565 static const struct net_device_ops smsc9420_netdev_ops = {
1566 .ndo_open = smsc9420_open,
1567 .ndo_stop = smsc9420_stop,
1568 .ndo_start_xmit = smsc9420_hard_start_xmit,
1569 .ndo_get_stats = smsc9420_get_stats,
1570 .ndo_set_rx_mode = smsc9420_set_multicast_list,
1571 .ndo_do_ioctl = smsc9420_do_ioctl,
1572 .ndo_validate_addr = eth_validate_addr,
1573 .ndo_set_mac_address = eth_mac_addr,
1574 #ifdef CONFIG_NET_POLL_CONTROLLER
1575 .ndo_poll_controller = smsc9420_poll_controller,
1576 #endif /* CONFIG_NET_POLL_CONTROLLER */
1577 };
1578
1579 static int __devinit
1580 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1581 {
1582 struct net_device *dev;
1583 struct smsc9420_pdata *pd;
1584 void __iomem *virt_addr;
1585 int result = 0;
1586 u32 id_rev;
1587
1588 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n");
1589
1590 /* First do the PCI initialisation */
1591 result = pci_enable_device(pdev);
1592 if (unlikely(result)) {
1593 printk(KERN_ERR "Cannot enable smsc9420\n");
1594 goto out_0;
1595 }
1596
1597 pci_set_master(pdev);
1598
1599 dev = alloc_etherdev(sizeof(*pd));
1600 if (!dev) {
1601 printk(KERN_ERR "ether device alloc failed\n");
1602 goto out_disable_pci_device_1;
1603 }
1604
1605 SET_NETDEV_DEV(dev, &pdev->dev);
1606
1607 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1608 printk(KERN_ERR "Cannot find PCI device base address\n");
1609 goto out_free_netdev_2;
1610 }
1611
1612 if ((pci_request_regions(pdev, DRV_NAME))) {
1613 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1614 goto out_free_netdev_2;
1615 }
1616
1617 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1618 printk(KERN_ERR "No usable DMA configuration, aborting.\n");
1619 goto out_free_regions_3;
1620 }
1621
1622 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1623 pci_resource_len(pdev, SMSC_BAR));
1624 if (!virt_addr) {
1625 printk(KERN_ERR "Cannot map device registers, aborting.\n");
1626 goto out_free_regions_3;
1627 }
1628
1629 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1630 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1631
1632 dev->base_addr = (ulong)virt_addr;
1633
1634 pd = netdev_priv(dev);
1635
1636 /* pci descriptors are created in the PCI consistent area */
1637 pd->rx_ring = pci_alloc_consistent(pdev,
1638 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1639 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1640 &pd->rx_dma_addr);
1641
1642 if (!pd->rx_ring)
1643 goto out_free_io_4;
1644
1645 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1646 pd->tx_ring = (struct smsc9420_dma_desc *)
1647 (pd->rx_ring + RX_RING_SIZE);
1648 pd->tx_dma_addr = pd->rx_dma_addr +
1649 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1650
1651 pd->pdev = pdev;
1652 pd->dev = dev;
1653 pd->base_addr = virt_addr;
1654 pd->msg_enable = smsc_debug;
1655 pd->rx_csum = true;
1656
1657 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr);
1658
1659 id_rev = smsc9420_reg_read(pd, ID_REV);
1660 switch (id_rev & 0xFFFF0000) {
1661 case 0x94200000:
1662 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev);
1663 break;
1664 default:
1665 smsc_warn(PROBE, "LAN9420 NOT identified");
1666 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev);
1667 goto out_free_dmadesc_5;
1668 }
1669
1670 smsc9420_dmac_soft_reset(pd);
1671 smsc9420_eeprom_reload(pd);
1672 smsc9420_check_mac_address(dev);
1673
1674 dev->netdev_ops = &smsc9420_netdev_ops;
1675 dev->ethtool_ops = &smsc9420_ethtool_ops;
1676 dev->irq = pdev->irq;
1677
1678 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1679
1680 result = register_netdev(dev);
1681 if (result) {
1682 smsc_warn(PROBE, "error %i registering device", result);
1683 goto out_free_dmadesc_5;
1684 }
1685
1686 pci_set_drvdata(pdev, dev);
1687
1688 spin_lock_init(&pd->int_lock);
1689 spin_lock_init(&pd->phy_lock);
1690
1691 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1692
1693 return 0;
1694
1695 out_free_dmadesc_5:
1696 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1697 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1698 out_free_io_4:
1699 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1700 out_free_regions_3:
1701 pci_release_regions(pdev);
1702 out_free_netdev_2:
1703 free_netdev(dev);
1704 out_disable_pci_device_1:
1705 pci_disable_device(pdev);
1706 out_0:
1707 return -ENODEV;
1708 }
1709
1710 static void __devexit smsc9420_remove(struct pci_dev *pdev)
1711 {
1712 struct net_device *dev;
1713 struct smsc9420_pdata *pd;
1714
1715 dev = pci_get_drvdata(pdev);
1716 if (!dev)
1717 return;
1718
1719 pci_set_drvdata(pdev, NULL);
1720
1721 pd = netdev_priv(dev);
1722 unregister_netdev(dev);
1723
1724 /* tx_buffers and rx_buffers are freed in stop */
1725 BUG_ON(pd->tx_buffers);
1726 BUG_ON(pd->rx_buffers);
1727
1728 BUG_ON(!pd->tx_ring);
1729 BUG_ON(!pd->rx_ring);
1730
1731 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1732 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1733
1734 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1735 pci_release_regions(pdev);
1736 free_netdev(dev);
1737 pci_disable_device(pdev);
1738 }
1739
1740 static struct pci_driver smsc9420_driver = {
1741 .name = DRV_NAME,
1742 .id_table = smsc9420_id_table,
1743 .probe = smsc9420_probe,
1744 .remove = __devexit_p(smsc9420_remove),
1745 #ifdef CONFIG_PM
1746 .suspend = smsc9420_suspend,
1747 .resume = smsc9420_resume,
1748 #endif /* CONFIG_PM */
1749 };
1750
1751 static int __init smsc9420_init_module(void)
1752 {
1753 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1754
1755 return pci_register_driver(&smsc9420_driver);
1756 }
1757
1758 static void __exit smsc9420_exit_module(void)
1759 {
1760 pci_unregister_driver(&smsc9420_driver);
1761 }
1762
1763 module_init(smsc9420_init_module);
1764 module_exit(smsc9420_exit_module);
Linux kernel - Deliverables
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